1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/Constants.h"
27 #include "llvm/DerivedTypes.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/SmallPtrSet.h"
39 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
40 cl::desc("Pop up a window to show dags before legalize"));
42 static const bool ViewLegalizeDAGs = 0;
45 //===----------------------------------------------------------------------===//
46 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
47 /// hacks on it until the target machine can handle it. This involves
48 /// eliminating value sizes the machine cannot handle (promoting small sizes to
49 /// large sizes or splitting up large values into small values) as well as
50 /// eliminating operations the machine cannot handle.
52 /// This code also does a small amount of optimization and recognition of idioms
53 /// as part of its processing. For example, if a target does not support a
54 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
55 /// will attempt merge setcc and brc instructions into brcc's.
58 class VISIBILITY_HIDDEN SelectionDAGLegalize {
62 // Libcall insertion helpers.
64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
65 /// legalized. We use this to ensure that calls are properly serialized
66 /// against each other, including inserted libcalls.
67 SDOperand LastCALLSEQ_END;
69 /// IsLegalizingCall - This member is used *only* for purposes of providing
70 /// helpful assertions that a libcall isn't created while another call is
71 /// being legalized (which could lead to non-serialized call sequences).
72 bool IsLegalizingCall;
75 Legal, // The target natively supports this operation.
76 Promote, // This operation should be executed in a larger type.
77 Expand // Try to expand this to other ops, otherwise use a libcall.
80 /// ValueTypeActions - This is a bitvector that contains two bits for each
81 /// value type, where the two bits correspond to the LegalizeAction enum.
82 /// This can be queried with "getTypeAction(VT)".
83 TargetLowering::ValueTypeActionImpl ValueTypeActions;
85 /// LegalizedNodes - For nodes that are of legal width, and that have more
86 /// than one use, this map indicates what regularized operand to use. This
87 /// allows us to avoid legalizing the same thing more than once.
88 DenseMap<SDOperand, SDOperand> LegalizedNodes;
90 /// PromotedNodes - For nodes that are below legal width, and that have more
91 /// than one use, this map indicates what promoted value to use. This allows
92 /// us to avoid promoting the same thing more than once.
93 DenseMap<SDOperand, SDOperand> PromotedNodes;
95 /// ExpandedNodes - For nodes that need to be expanded this map indicates
96 /// which which operands are the expanded version of the input. This allows
97 /// us to avoid expanding the same node more than once.
98 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
100 /// SplitNodes - For vector nodes that need to be split, this map indicates
101 /// which which operands are the split version of the input. This allows us
102 /// to avoid splitting the same node more than once.
103 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
105 /// ScalarizedNodes - For nodes that need to be converted from vector types to
106 /// scalar types, this contains the mapping of ones we have already
107 /// processed to the result.
108 std::map<SDOperand, SDOperand> ScalarizedNodes;
110 void AddLegalizedOperand(SDOperand From, SDOperand To) {
111 LegalizedNodes.insert(std::make_pair(From, To));
112 // If someone requests legalization of the new node, return itself.
114 LegalizedNodes.insert(std::make_pair(To, To));
116 void AddPromotedOperand(SDOperand From, SDOperand To) {
117 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
118 assert(isNew && "Got into the map somehow?");
119 // If someone requests legalization of the new node, return itself.
120 LegalizedNodes.insert(std::make_pair(To, To));
125 SelectionDAGLegalize(SelectionDAG &DAG);
127 /// getTypeAction - Return how we should legalize values of this type, either
128 /// it is already legal or we need to expand it into multiple registers of
129 /// smaller integer type, or we need to promote it to a larger type.
130 LegalizeAction getTypeAction(MVT::ValueType VT) const {
131 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
134 /// isTypeLegal - Return true if this type is legal on this target.
136 bool isTypeLegal(MVT::ValueType VT) const {
137 return getTypeAction(VT) == Legal;
143 /// HandleOp - Legalize, Promote, or Expand the specified operand as
144 /// appropriate for its type.
145 void HandleOp(SDOperand Op);
147 /// LegalizeOp - We know that the specified value has a legal type.
148 /// Recursively ensure that the operands have legal types, then return the
150 SDOperand LegalizeOp(SDOperand O);
152 /// UnrollVectorOp - We know that the given vector has a legal type, however
153 /// the operation it performs is not legal and is an operation that we have
154 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
155 /// operating on each element individually.
156 SDOperand UnrollVectorOp(SDOperand O);
158 /// PromoteOp - Given an operation that produces a value in an invalid type,
159 /// promote it to compute the value into a larger type. The produced value
160 /// will have the correct bits for the low portion of the register, but no
161 /// guarantee is made about the top bits: it may be zero, sign-extended, or
163 SDOperand PromoteOp(SDOperand O);
165 /// ExpandOp - Expand the specified SDOperand into its two component pieces
166 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
167 /// the LegalizeNodes map is filled in for any results that are not expanded,
168 /// the ExpandedNodes map is filled in for any results that are expanded, and
169 /// the Lo/Hi values are returned. This applies to integer types and Vector
171 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
173 /// SplitVectorOp - Given an operand of vector type, break it down into
174 /// two smaller values.
175 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
177 /// ScalarizeVectorOp - Given an operand of single-element vector type
178 /// (e.g. v1f32), convert it into the equivalent operation that returns a
179 /// scalar (e.g. f32) value.
180 SDOperand ScalarizeVectorOp(SDOperand O);
182 /// isShuffleLegal - Return true if a vector shuffle is legal with the
183 /// specified mask and type. Targets can specify exactly which masks they
184 /// support and the code generator is tasked with not creating illegal masks.
186 /// Note that this will also return true for shuffles that are promoted to a
189 /// If this is a legal shuffle, this method returns the (possibly promoted)
190 /// build_vector Mask. If it's not a legal shuffle, it returns null.
191 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
193 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
194 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
196 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
198 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
200 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
203 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT,
204 MVT::ValueType DestVT);
205 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
206 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
207 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
209 MVT::ValueType DestVT);
210 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
212 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
215 SDOperand ExpandBSWAP(SDOperand Op);
216 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
217 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
218 SDOperand &Lo, SDOperand &Hi);
219 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
220 SDOperand &Lo, SDOperand &Hi);
222 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
223 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
227 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
228 /// specified mask and type. Targets can specify exactly which masks they
229 /// support and the code generator is tasked with not creating illegal masks.
231 /// Note that this will also return true for shuffles that are promoted to a
233 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
234 SDOperand Mask) const {
235 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
237 case TargetLowering::Legal:
238 case TargetLowering::Custom:
240 case TargetLowering::Promote: {
241 // If this is promoted to a different type, convert the shuffle mask and
242 // ask if it is legal in the promoted type!
243 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
245 // If we changed # elements, change the shuffle mask.
246 unsigned NumEltsGrowth =
247 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
248 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
249 if (NumEltsGrowth > 1) {
250 // Renumber the elements.
251 SmallVector<SDOperand, 8> Ops;
252 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
253 SDOperand InOp = Mask.getOperand(i);
254 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
255 if (InOp.getOpcode() == ISD::UNDEF)
256 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
258 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
259 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
263 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
269 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
272 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
273 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
274 ValueTypeActions(TLI.getValueTypeActions()) {
275 assert(MVT::LAST_VALUETYPE <= 32 &&
276 "Too many value types for ValueTypeActions to hold!");
279 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
280 /// contains all of a nodes operands before it contains the node.
281 static void ComputeTopDownOrdering(SelectionDAG &DAG,
282 SmallVector<SDNode*, 64> &Order) {
284 DenseMap<SDNode*, unsigned> Visited;
285 std::vector<SDNode*> Worklist;
286 Worklist.reserve(128);
288 // Compute ordering from all of the leaves in the graphs, those (like the
289 // entry node) that have no operands.
290 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
291 E = DAG.allnodes_end(); I != E; ++I) {
292 if (I->getNumOperands() == 0) {
294 Worklist.push_back(I);
298 while (!Worklist.empty()) {
299 SDNode *N = Worklist.back();
302 if (++Visited[N] != N->getNumOperands())
303 continue; // Haven't visited all operands yet
307 // Now that we have N in, add anything that uses it if all of their operands
309 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
311 Worklist.push_back(*UI);
314 assert(Order.size() == Visited.size() &&
316 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
317 "Error: DAG is cyclic!");
321 void SelectionDAGLegalize::LegalizeDAG() {
322 LastCALLSEQ_END = DAG.getEntryNode();
323 IsLegalizingCall = false;
325 // The legalize process is inherently a bottom-up recursive process (users
326 // legalize their uses before themselves). Given infinite stack space, we
327 // could just start legalizing on the root and traverse the whole graph. In
328 // practice however, this causes us to run out of stack space on large basic
329 // blocks. To avoid this problem, compute an ordering of the nodes where each
330 // node is only legalized after all of its operands are legalized.
331 SmallVector<SDNode*, 64> Order;
332 ComputeTopDownOrdering(DAG, Order);
334 for (unsigned i = 0, e = Order.size(); i != e; ++i)
335 HandleOp(SDOperand(Order[i], 0));
337 // Finally, it's possible the root changed. Get the new root.
338 SDOperand OldRoot = DAG.getRoot();
339 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
340 DAG.setRoot(LegalizedNodes[OldRoot]);
342 ExpandedNodes.clear();
343 LegalizedNodes.clear();
344 PromotedNodes.clear();
346 ScalarizedNodes.clear();
348 // Remove dead nodes now.
349 DAG.RemoveDeadNodes();
353 /// FindCallEndFromCallStart - Given a chained node that is part of a call
354 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
355 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
356 if (Node->getOpcode() == ISD::CALLSEQ_END)
358 if (Node->use_empty())
359 return 0; // No CallSeqEnd
361 // The chain is usually at the end.
362 SDOperand TheChain(Node, Node->getNumValues()-1);
363 if (TheChain.getValueType() != MVT::Other) {
364 // Sometimes it's at the beginning.
365 TheChain = SDOperand(Node, 0);
366 if (TheChain.getValueType() != MVT::Other) {
367 // Otherwise, hunt for it.
368 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
369 if (Node->getValueType(i) == MVT::Other) {
370 TheChain = SDOperand(Node, i);
374 // Otherwise, we walked into a node without a chain.
375 if (TheChain.getValueType() != MVT::Other)
380 for (SDNode::use_iterator UI = Node->use_begin(),
381 E = Node->use_end(); UI != E; ++UI) {
383 // Make sure to only follow users of our token chain.
385 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
386 if (User->getOperand(i) == TheChain)
387 if (SDNode *Result = FindCallEndFromCallStart(User))
393 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
394 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
395 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
396 assert(Node && "Didn't find callseq_start for a call??");
397 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
399 assert(Node->getOperand(0).getValueType() == MVT::Other &&
400 "Node doesn't have a token chain argument!");
401 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
404 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
405 /// see if any uses can reach Dest. If no dest operands can get to dest,
406 /// legalize them, legalize ourself, and return false, otherwise, return true.
408 /// Keep track of the nodes we fine that actually do lead to Dest in
409 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
411 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
412 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
413 if (N == Dest) return true; // N certainly leads to Dest :)
415 // If we've already processed this node and it does lead to Dest, there is no
416 // need to reprocess it.
417 if (NodesLeadingTo.count(N)) return true;
419 // If the first result of this node has been already legalized, then it cannot
421 switch (getTypeAction(N->getValueType(0))) {
423 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
426 if (PromotedNodes.count(SDOperand(N, 0))) return false;
429 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
433 // Okay, this node has not already been legalized. Check and legalize all
434 // operands. If none lead to Dest, then we can legalize this node.
435 bool OperandsLeadToDest = false;
436 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
437 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
438 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
440 if (OperandsLeadToDest) {
441 NodesLeadingTo.insert(N);
445 // Okay, this node looks safe, legalize it and return false.
446 HandleOp(SDOperand(N, 0));
450 /// HandleOp - Legalize, Promote, or Expand the specified operand as
451 /// appropriate for its type.
452 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
453 MVT::ValueType VT = Op.getValueType();
454 switch (getTypeAction(VT)) {
455 default: assert(0 && "Bad type action!");
456 case Legal: (void)LegalizeOp(Op); break;
457 case Promote: (void)PromoteOp(Op); break;
459 if (!MVT::isVector(VT)) {
460 // If this is an illegal scalar, expand it into its two component
463 if (Op.getOpcode() == ISD::TargetConstant)
464 break; // Allow illegal target nodes.
466 } else if (MVT::getVectorNumElements(VT) == 1) {
467 // If this is an illegal single element vector, convert it to a
469 (void)ScalarizeVectorOp(Op);
471 // Otherwise, this is an illegal multiple element vector.
472 // Split it in half and legalize both parts.
474 SplitVectorOp(Op, X, Y);
480 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
481 /// a load from the constant pool.
482 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
483 SelectionDAG &DAG, TargetLowering &TLI) {
486 // If a FP immediate is precise when represented as a float and if the
487 // target can do an extending load from float to double, we put it into
488 // the constant pool as a float, even if it's is statically typed as a
490 MVT::ValueType VT = CFP->getValueType(0);
491 bool isDouble = VT == MVT::f64;
492 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
495 if (VT!=MVT::f64 && VT!=MVT::f32)
496 assert(0 && "Invalid type expansion");
497 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(),
498 isDouble ? MVT::i64 : MVT::i32);
501 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) &&
502 // Only do this if the target has a native EXTLOAD instruction from f32.
503 // Do not try to be clever about long doubles (so far)
504 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
505 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
510 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
512 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
513 CPIdx, PseudoSourceValue::getConstantPool(),
516 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
517 PseudoSourceValue::getConstantPool(), 0);
522 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
525 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
526 SelectionDAG &DAG, TargetLowering &TLI) {
527 MVT::ValueType VT = Node->getValueType(0);
528 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
529 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
530 "fcopysign expansion only supported for f32 and f64");
531 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
533 // First get the sign bit of second operand.
534 SDOperand Mask1 = (SrcVT == MVT::f64)
535 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
536 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
537 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
538 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
539 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
540 // Shift right or sign-extend it if the two operands have different types.
541 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
543 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
544 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
545 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
546 } else if (SizeDiff < 0)
547 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
549 // Clear the sign bit of first operand.
550 SDOperand Mask2 = (VT == MVT::f64)
551 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
552 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
553 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
554 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
555 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
557 // Or the value with the sign bit.
558 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
562 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
564 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
565 TargetLowering &TLI) {
566 SDOperand Chain = ST->getChain();
567 SDOperand Ptr = ST->getBasePtr();
568 SDOperand Val = ST->getValue();
569 MVT::ValueType VT = Val.getValueType();
570 int Alignment = ST->getAlignment();
571 int SVOffset = ST->getSrcValueOffset();
572 if (MVT::isFloatingPoint(ST->getMemoryVT())) {
573 // Expand to a bitconvert of the value to the integer type of the
574 // same size, then a (misaligned) int store.
575 MVT::ValueType intVT;
578 else if (VT==MVT::f32)
581 assert(0 && "Unaligned load of unsupported floating point type");
583 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
584 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
585 SVOffset, ST->isVolatile(), Alignment);
587 assert(MVT::isInteger(ST->getMemoryVT()) &&
588 "Unaligned store of unknown type.");
589 // Get the half-size VT
590 MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1;
591 int NumBits = MVT::getSizeInBits(NewStoredVT);
592 int IncrementSize = NumBits / 8;
594 // Divide the stored value in two parts.
595 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
597 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
599 // Store the two parts
600 SDOperand Store1, Store2;
601 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
602 ST->getSrcValue(), SVOffset, NewStoredVT,
603 ST->isVolatile(), Alignment);
604 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
605 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
606 Alignment = MinAlign(Alignment, IncrementSize);
607 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
608 ST->getSrcValue(), SVOffset + IncrementSize,
609 NewStoredVT, ST->isVolatile(), Alignment);
611 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
614 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
616 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
617 TargetLowering &TLI) {
618 int SVOffset = LD->getSrcValueOffset();
619 SDOperand Chain = LD->getChain();
620 SDOperand Ptr = LD->getBasePtr();
621 MVT::ValueType VT = LD->getValueType(0);
622 MVT::ValueType LoadedVT = LD->getMemoryVT();
623 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT)) {
624 // Expand to a (misaligned) integer load of the same size,
625 // then bitconvert to floating point.
626 MVT::ValueType intVT;
627 if (LoadedVT == MVT::f64)
629 else if (LoadedVT == MVT::f32)
632 assert(0 && "Unaligned load of unsupported floating point type");
634 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
635 SVOffset, LD->isVolatile(),
637 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
639 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
641 SDOperand Ops[] = { Result, Chain };
642 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
645 assert((MVT::isInteger(LoadedVT) || MVT::isVector(LoadedVT)) &&
646 "Unaligned load of unsupported type.");
648 // Compute the new VT that is half the size of the old one. We either have an
649 // integer MVT or we have a vector MVT.
650 unsigned NumBits = MVT::getSizeInBits(LoadedVT);
651 MVT::ValueType NewLoadedVT;
652 if (!MVT::isVector(LoadedVT)) {
653 NewLoadedVT = MVT::getIntegerType(NumBits/2);
655 // FIXME: This is not right for <1 x anything> it is also not right for
656 // non-power-of-two vectors.
657 NewLoadedVT = MVT::getVectorType(MVT::getVectorElementType(LoadedVT),
658 MVT::getVectorNumElements(LoadedVT)/2);
662 unsigned Alignment = LD->getAlignment();
663 unsigned IncrementSize = NumBits / 8;
664 ISD::LoadExtType HiExtType = LD->getExtensionType();
666 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
667 if (HiExtType == ISD::NON_EXTLOAD)
668 HiExtType = ISD::ZEXTLOAD;
670 // Load the value in two parts
672 if (TLI.isLittleEndian()) {
673 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
674 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
675 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
676 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
677 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
678 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
679 MinAlign(Alignment, IncrementSize));
681 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
682 NewLoadedVT,LD->isVolatile(), Alignment);
683 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
684 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
685 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
686 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
687 MinAlign(Alignment, IncrementSize));
690 // aggregate the two parts
691 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
692 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
693 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
695 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
698 SDOperand Ops[] = { Result, TF };
699 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
702 /// UnrollVectorOp - We know that the given vector has a legal type, however
703 /// the operation it performs is not legal and is an operation that we have
704 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
705 /// operating on each element individually.
706 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
707 MVT::ValueType VT = Op.getValueType();
708 assert(isTypeLegal(VT) &&
709 "Caller should expand or promote operands that are not legal!");
710 assert(Op.Val->getNumValues() == 1 &&
711 "Can't unroll a vector with multiple results!");
712 unsigned NE = MVT::getVectorNumElements(VT);
713 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
715 SmallVector<SDOperand, 8> Scalars;
716 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
717 for (unsigned i = 0; i != NE; ++i) {
718 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
719 SDOperand Operand = Op.getOperand(j);
720 MVT::ValueType OperandVT = Operand.getValueType();
721 if (MVT::isVector(OperandVT)) {
722 // A vector operand; extract a single element.
723 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
724 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
727 DAG.getConstant(i, MVT::i32));
729 // A scalar operand; just use it as is.
730 Operands[j] = Operand;
733 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
734 &Operands[0], Operands.size()));
737 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
740 /// GetFPLibCall - Return the right libcall for the given floating point type.
741 static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
742 RTLIB::Libcall Call_F32,
743 RTLIB::Libcall Call_F64,
744 RTLIB::Libcall Call_F80,
745 RTLIB::Libcall Call_PPCF128) {
747 VT == MVT::f32 ? Call_F32 :
748 VT == MVT::f64 ? Call_F64 :
749 VT == MVT::f80 ? Call_F80 :
750 VT == MVT::ppcf128 ? Call_PPCF128 :
751 RTLIB::UNKNOWN_LIBCALL;
754 /// LegalizeOp - We know that the specified value has a legal type, and
755 /// that its operands are legal. Now ensure that the operation itself
756 /// is legal, recursively ensuring that the operands' operations remain
758 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
759 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
762 assert(isTypeLegal(Op.getValueType()) &&
763 "Caller should expand or promote operands that are not legal!");
764 SDNode *Node = Op.Val;
766 // If this operation defines any values that cannot be represented in a
767 // register on this target, make sure to expand or promote them.
768 if (Node->getNumValues() > 1) {
769 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
770 if (getTypeAction(Node->getValueType(i)) != Legal) {
771 HandleOp(Op.getValue(i));
772 assert(LegalizedNodes.count(Op) &&
773 "Handling didn't add legal operands!");
774 return LegalizedNodes[Op];
778 // Note that LegalizeOp may be reentered even from single-use nodes, which
779 // means that we always must cache transformed nodes.
780 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
781 if (I != LegalizedNodes.end()) return I->second;
783 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
784 SDOperand Result = Op;
785 bool isCustom = false;
787 switch (Node->getOpcode()) {
788 case ISD::FrameIndex:
789 case ISD::EntryToken:
791 case ISD::BasicBlock:
792 case ISD::TargetFrameIndex:
793 case ISD::TargetJumpTable:
794 case ISD::TargetConstant:
795 case ISD::TargetConstantFP:
796 case ISD::TargetConstantPool:
797 case ISD::TargetGlobalAddress:
798 case ISD::TargetGlobalTLSAddress:
799 case ISD::TargetExternalSymbol:
802 case ISD::MEMOPERAND:
805 // Primitives must all be legal.
806 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
807 "This must be legal!");
810 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
811 // If this is a target node, legalize it by legalizing the operands then
812 // passing it through.
813 SmallVector<SDOperand, 8> Ops;
814 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
815 Ops.push_back(LegalizeOp(Node->getOperand(i)));
817 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
819 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
820 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
821 return Result.getValue(Op.ResNo);
823 // Otherwise this is an unhandled builtin node. splat.
825 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
827 assert(0 && "Do not know how to legalize this operator!");
829 case ISD::GLOBAL_OFFSET_TABLE:
830 case ISD::GlobalAddress:
831 case ISD::GlobalTLSAddress:
832 case ISD::ExternalSymbol:
833 case ISD::ConstantPool:
834 case ISD::JumpTable: // Nothing to do.
835 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
836 default: assert(0 && "This action is not supported yet!");
837 case TargetLowering::Custom:
838 Tmp1 = TLI.LowerOperation(Op, DAG);
839 if (Tmp1.Val) Result = Tmp1;
840 // FALLTHROUGH if the target doesn't want to lower this op after all.
841 case TargetLowering::Legal:
846 case ISD::RETURNADDR:
847 // The only option for these nodes is to custom lower them. If the target
848 // does not custom lower them, then return zero.
849 Tmp1 = TLI.LowerOperation(Op, DAG);
853 Result = DAG.getConstant(0, TLI.getPointerTy());
855 case ISD::FRAME_TO_ARGS_OFFSET: {
856 MVT::ValueType VT = Node->getValueType(0);
857 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
858 default: assert(0 && "This action is not supported yet!");
859 case TargetLowering::Custom:
860 Result = TLI.LowerOperation(Op, DAG);
861 if (Result.Val) break;
863 case TargetLowering::Legal:
864 Result = DAG.getConstant(0, VT);
869 case ISD::EXCEPTIONADDR: {
870 Tmp1 = LegalizeOp(Node->getOperand(0));
871 MVT::ValueType VT = Node->getValueType(0);
872 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
873 default: assert(0 && "This action is not supported yet!");
874 case TargetLowering::Expand: {
875 unsigned Reg = TLI.getExceptionAddressRegister();
876 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
879 case TargetLowering::Custom:
880 Result = TLI.LowerOperation(Op, DAG);
881 if (Result.Val) break;
883 case TargetLowering::Legal: {
884 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
885 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
891 if (Result.Val->getNumValues() == 1) break;
893 assert(Result.Val->getNumValues() == 2 &&
894 "Cannot return more than two values!");
896 // Since we produced two values, make sure to remember that we
897 // legalized both of them.
898 Tmp1 = LegalizeOp(Result);
899 Tmp2 = LegalizeOp(Result.getValue(1));
900 AddLegalizedOperand(Op.getValue(0), Tmp1);
901 AddLegalizedOperand(Op.getValue(1), Tmp2);
902 return Op.ResNo ? Tmp2 : Tmp1;
903 case ISD::EHSELECTION: {
904 Tmp1 = LegalizeOp(Node->getOperand(0));
905 Tmp2 = LegalizeOp(Node->getOperand(1));
906 MVT::ValueType VT = Node->getValueType(0);
907 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
908 default: assert(0 && "This action is not supported yet!");
909 case TargetLowering::Expand: {
910 unsigned Reg = TLI.getExceptionSelectorRegister();
911 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
914 case TargetLowering::Custom:
915 Result = TLI.LowerOperation(Op, DAG);
916 if (Result.Val) break;
918 case TargetLowering::Legal: {
919 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
920 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
926 if (Result.Val->getNumValues() == 1) break;
928 assert(Result.Val->getNumValues() == 2 &&
929 "Cannot return more than two values!");
931 // Since we produced two values, make sure to remember that we
932 // legalized both of them.
933 Tmp1 = LegalizeOp(Result);
934 Tmp2 = LegalizeOp(Result.getValue(1));
935 AddLegalizedOperand(Op.getValue(0), Tmp1);
936 AddLegalizedOperand(Op.getValue(1), Tmp2);
937 return Op.ResNo ? Tmp2 : Tmp1;
938 case ISD::EH_RETURN: {
939 MVT::ValueType VT = Node->getValueType(0);
940 // The only "good" option for this node is to custom lower it.
941 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
942 default: assert(0 && "This action is not supported at all!");
943 case TargetLowering::Custom:
944 Result = TLI.LowerOperation(Op, DAG);
945 if (Result.Val) break;
947 case TargetLowering::Legal:
948 // Target does not know, how to lower this, lower to noop
949 Result = LegalizeOp(Node->getOperand(0));
954 case ISD::AssertSext:
955 case ISD::AssertZext:
956 Tmp1 = LegalizeOp(Node->getOperand(0));
957 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
959 case ISD::MERGE_VALUES:
960 // Legalize eliminates MERGE_VALUES nodes.
961 Result = Node->getOperand(Op.ResNo);
963 case ISD::CopyFromReg:
964 Tmp1 = LegalizeOp(Node->getOperand(0));
965 Result = Op.getValue(0);
966 if (Node->getNumValues() == 2) {
967 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
969 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
970 if (Node->getNumOperands() == 3) {
971 Tmp2 = LegalizeOp(Node->getOperand(2));
972 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
974 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
976 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
978 // Since CopyFromReg produces two values, make sure to remember that we
979 // legalized both of them.
980 AddLegalizedOperand(Op.getValue(0), Result);
981 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
982 return Result.getValue(Op.ResNo);
984 MVT::ValueType VT = Op.getValueType();
985 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
986 default: assert(0 && "This action is not supported yet!");
987 case TargetLowering::Expand:
988 if (MVT::isInteger(VT))
989 Result = DAG.getConstant(0, VT);
990 else if (MVT::isFloatingPoint(VT))
991 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
994 assert(0 && "Unknown value type!");
996 case TargetLowering::Legal:
1002 case ISD::INTRINSIC_W_CHAIN:
1003 case ISD::INTRINSIC_WO_CHAIN:
1004 case ISD::INTRINSIC_VOID: {
1005 SmallVector<SDOperand, 8> Ops;
1006 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1007 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1008 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1010 // Allow the target to custom lower its intrinsics if it wants to.
1011 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1012 TargetLowering::Custom) {
1013 Tmp3 = TLI.LowerOperation(Result, DAG);
1014 if (Tmp3.Val) Result = Tmp3;
1017 if (Result.Val->getNumValues() == 1) break;
1019 // Must have return value and chain result.
1020 assert(Result.Val->getNumValues() == 2 &&
1021 "Cannot return more than two values!");
1023 // Since loads produce two values, make sure to remember that we
1024 // legalized both of them.
1025 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1026 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1027 return Result.getValue(Op.ResNo);
1031 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
1032 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1034 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
1035 case TargetLowering::Promote:
1036 default: assert(0 && "This action is not supported yet!");
1037 case TargetLowering::Expand: {
1038 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1039 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1040 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
1042 if (MMI && (useDEBUG_LOC || useLABEL)) {
1043 const std::string &FName =
1044 cast<StringSDNode>(Node->getOperand(3))->getValue();
1045 const std::string &DirName =
1046 cast<StringSDNode>(Node->getOperand(4))->getValue();
1047 unsigned SrcFile = MMI->RecordSource(DirName, FName);
1049 SmallVector<SDOperand, 8> Ops;
1050 Ops.push_back(Tmp1); // chain
1051 SDOperand LineOp = Node->getOperand(1);
1052 SDOperand ColOp = Node->getOperand(2);
1055 Ops.push_back(LineOp); // line #
1056 Ops.push_back(ColOp); // col #
1057 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1058 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1060 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
1061 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
1062 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1063 Ops.push_back(DAG.getConstant(ID, MVT::i32));
1064 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label
1065 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size());
1068 Result = Tmp1; // chain
1072 case TargetLowering::Legal:
1073 if (Tmp1 != Node->getOperand(0) ||
1074 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1075 SmallVector<SDOperand, 8> Ops;
1076 Ops.push_back(Tmp1);
1077 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1078 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1079 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1081 // Otherwise promote them.
1082 Ops.push_back(PromoteOp(Node->getOperand(1)));
1083 Ops.push_back(PromoteOp(Node->getOperand(2)));
1085 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1086 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1087 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1094 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1095 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1096 default: assert(0 && "This action is not supported yet!");
1097 case TargetLowering::Legal:
1098 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1099 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1100 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1101 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1106 case ISD::DEBUG_LOC:
1107 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1108 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1109 default: assert(0 && "This action is not supported yet!");
1110 case TargetLowering::Legal:
1111 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1112 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1113 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1114 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1115 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1121 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!");
1122 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1123 default: assert(0 && "This action is not supported yet!");
1124 case TargetLowering::Legal:
1125 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1126 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1127 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand.
1128 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1130 case TargetLowering::Expand:
1131 Result = LegalizeOp(Node->getOperand(0));
1136 case ISD::Constant: {
1137 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1139 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1141 // We know we don't need to expand constants here, constants only have one
1142 // value and we check that it is fine above.
1144 if (opAction == TargetLowering::Custom) {
1145 Tmp1 = TLI.LowerOperation(Result, DAG);
1151 case ISD::ConstantFP: {
1152 // Spill FP immediates to the constant pool if the target cannot directly
1153 // codegen them. Targets often have some immediate values that can be
1154 // efficiently generated into an FP register without a load. We explicitly
1155 // leave these constants as ConstantFP nodes for the target to deal with.
1156 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1158 // Check to see if this FP immediate is already legal.
1159 bool isLegal = false;
1160 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1161 E = TLI.legal_fpimm_end(); I != E; ++I)
1162 if (CFP->isExactlyValue(*I)) {
1167 // If this is a legal constant, turn it into a TargetConstantFP node.
1169 Result = DAG.getTargetConstantFP(CFP->getValueAPF(),
1170 CFP->getValueType(0));
1174 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1175 default: assert(0 && "This action is not supported yet!");
1176 case TargetLowering::Custom:
1177 Tmp3 = TLI.LowerOperation(Result, DAG);
1183 case TargetLowering::Expand:
1184 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1188 case ISD::TokenFactor:
1189 if (Node->getNumOperands() == 2) {
1190 Tmp1 = LegalizeOp(Node->getOperand(0));
1191 Tmp2 = LegalizeOp(Node->getOperand(1));
1192 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1193 } else if (Node->getNumOperands() == 3) {
1194 Tmp1 = LegalizeOp(Node->getOperand(0));
1195 Tmp2 = LegalizeOp(Node->getOperand(1));
1196 Tmp3 = LegalizeOp(Node->getOperand(2));
1197 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1199 SmallVector<SDOperand, 8> Ops;
1200 // Legalize the operands.
1201 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1202 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1203 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1207 case ISD::FORMAL_ARGUMENTS:
1209 // The only option for this is to custom lower it.
1210 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1211 assert(Tmp3.Val && "Target didn't custom lower this node!");
1213 // The number of incoming and outgoing values should match; unless the final
1214 // outgoing value is a flag.
1215 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1216 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1217 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1219 "Lowering call/formal_arguments produced unexpected # results!");
1221 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1222 // remember that we legalized all of them, so it doesn't get relegalized.
1223 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1224 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1226 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1229 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1232 case ISD::EXTRACT_SUBREG: {
1233 Tmp1 = LegalizeOp(Node->getOperand(0));
1234 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1235 assert(idx && "Operand must be a constant");
1236 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1237 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1240 case ISD::INSERT_SUBREG: {
1241 Tmp1 = LegalizeOp(Node->getOperand(0));
1242 Tmp2 = LegalizeOp(Node->getOperand(1));
1243 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1244 assert(idx && "Operand must be a constant");
1245 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1246 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1249 case ISD::BUILD_VECTOR:
1250 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1251 default: assert(0 && "This action is not supported yet!");
1252 case TargetLowering::Custom:
1253 Tmp3 = TLI.LowerOperation(Result, DAG);
1259 case TargetLowering::Expand:
1260 Result = ExpandBUILD_VECTOR(Result.Val);
1264 case ISD::INSERT_VECTOR_ELT:
1265 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1266 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
1267 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1268 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1270 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1271 Node->getValueType(0))) {
1272 default: assert(0 && "This action is not supported yet!");
1273 case TargetLowering::Legal:
1275 case TargetLowering::Custom:
1276 Tmp4 = TLI.LowerOperation(Result, DAG);
1282 case TargetLowering::Expand: {
1283 // If the insert index is a constant, codegen this as a scalar_to_vector,
1284 // then a shuffle that inserts it into the right position in the vector.
1285 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1286 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1287 Tmp1.getValueType(), Tmp2);
1289 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1290 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1291 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1293 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
1294 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
1296 SmallVector<SDOperand, 8> ShufOps;
1297 for (unsigned i = 0; i != NumElts; ++i) {
1298 if (i != InsertPos->getValue())
1299 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1301 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1303 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1304 &ShufOps[0], ShufOps.size());
1306 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1307 Tmp1, ScVec, ShufMask);
1308 Result = LegalizeOp(Result);
1312 // If the target doesn't support this, we have to spill the input vector
1313 // to a temporary stack slot, update the element, then reload it. This is
1314 // badness. We could also load the value into a vector register (either
1315 // with a "move to register" or "extload into register" instruction, then
1316 // permute it into place, if the idx is a constant and if the idx is
1317 // supported by the target.
1318 MVT::ValueType VT = Tmp1.getValueType();
1319 MVT::ValueType EltVT = Tmp2.getValueType();
1320 MVT::ValueType IdxVT = Tmp3.getValueType();
1321 MVT::ValueType PtrVT = TLI.getPointerTy();
1322 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
1324 FrameIndexSDNode *StackPtrFI = dyn_cast<FrameIndexSDNode>(StackPtr.Val);
1326 int SPFI = StackPtrFI->getIndex();
1328 // Store the vector.
1329 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
1330 PseudoSourceValue::getFixedStack(),
1333 // Truncate or zero extend offset to target pointer type.
1334 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1335 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1336 // Add the offset to the index.
1337 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1338 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1339 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1340 // Store the scalar value.
1341 Ch = DAG.getStore(Ch, Tmp2, StackPtr2,
1342 PseudoSourceValue::getFixedStack(), SPFI);
1343 // Load the updated vector.
1344 Result = DAG.getLoad(VT, Ch, StackPtr,
1345 PseudoSourceValue::getFixedStack(), SPFI);
1350 case ISD::SCALAR_TO_VECTOR:
1351 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1352 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1356 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1357 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1358 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1359 Node->getValueType(0))) {
1360 default: assert(0 && "This action is not supported yet!");
1361 case TargetLowering::Legal:
1363 case TargetLowering::Custom:
1364 Tmp3 = TLI.LowerOperation(Result, DAG);
1370 case TargetLowering::Expand:
1371 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1375 case ISD::VECTOR_SHUFFLE:
1376 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1377 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1378 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1380 // Allow targets to custom lower the SHUFFLEs they support.
1381 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1382 default: assert(0 && "Unknown operation action!");
1383 case TargetLowering::Legal:
1384 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1385 "vector shuffle should not be created if not legal!");
1387 case TargetLowering::Custom:
1388 Tmp3 = TLI.LowerOperation(Result, DAG);
1394 case TargetLowering::Expand: {
1395 MVT::ValueType VT = Node->getValueType(0);
1396 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1397 MVT::ValueType PtrVT = TLI.getPointerTy();
1398 SDOperand Mask = Node->getOperand(2);
1399 unsigned NumElems = Mask.getNumOperands();
1400 SmallVector<SDOperand,8> Ops;
1401 for (unsigned i = 0; i != NumElems; ++i) {
1402 SDOperand Arg = Mask.getOperand(i);
1403 if (Arg.getOpcode() == ISD::UNDEF) {
1404 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1406 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1407 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1409 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1410 DAG.getConstant(Idx, PtrVT)));
1412 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1413 DAG.getConstant(Idx - NumElems, PtrVT)));
1416 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1419 case TargetLowering::Promote: {
1420 // Change base type to a different vector type.
1421 MVT::ValueType OVT = Node->getValueType(0);
1422 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1424 // Cast the two input vectors.
1425 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1426 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1428 // Convert the shuffle mask to the right # elements.
1429 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1430 assert(Tmp3.Val && "Shuffle not legal?");
1431 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1432 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1438 case ISD::EXTRACT_VECTOR_ELT:
1439 Tmp1 = Node->getOperand(0);
1440 Tmp2 = LegalizeOp(Node->getOperand(1));
1441 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1442 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1445 case ISD::EXTRACT_SUBVECTOR:
1446 Tmp1 = Node->getOperand(0);
1447 Tmp2 = LegalizeOp(Node->getOperand(1));
1448 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1449 Result = ExpandEXTRACT_SUBVECTOR(Result);
1452 case ISD::CALLSEQ_START: {
1453 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1455 // Recursively Legalize all of the inputs of the call end that do not lead
1456 // to this call start. This ensures that any libcalls that need be inserted
1457 // are inserted *before* the CALLSEQ_START.
1458 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1459 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1460 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1464 // Now that we legalized all of the inputs (which may have inserted
1465 // libcalls) create the new CALLSEQ_START node.
1466 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1468 // Merge in the last call, to ensure that this call start after the last
1470 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1471 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1472 Tmp1 = LegalizeOp(Tmp1);
1475 // Do not try to legalize the target-specific arguments (#1+).
1476 if (Tmp1 != Node->getOperand(0)) {
1477 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1479 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1482 // Remember that the CALLSEQ_START is legalized.
1483 AddLegalizedOperand(Op.getValue(0), Result);
1484 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1485 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1487 // Now that the callseq_start and all of the non-call nodes above this call
1488 // sequence have been legalized, legalize the call itself. During this
1489 // process, no libcalls can/will be inserted, guaranteeing that no calls
1491 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1492 SDOperand InCallSEQ = LastCALLSEQ_END;
1493 // Note that we are selecting this call!
1494 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1495 IsLegalizingCall = true;
1497 // Legalize the call, starting from the CALLSEQ_END.
1498 LegalizeOp(LastCALLSEQ_END);
1499 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1502 case ISD::CALLSEQ_END:
1503 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1504 // will cause this node to be legalized as well as handling libcalls right.
1505 if (LastCALLSEQ_END.Val != Node) {
1506 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1507 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1508 assert(I != LegalizedNodes.end() &&
1509 "Legalizing the call start should have legalized this node!");
1513 // Otherwise, the call start has been legalized and everything is going
1514 // according to plan. Just legalize ourselves normally here.
1515 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1516 // Do not try to legalize the target-specific arguments (#1+), except for
1517 // an optional flag input.
1518 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1519 if (Tmp1 != Node->getOperand(0)) {
1520 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1522 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1525 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1526 if (Tmp1 != Node->getOperand(0) ||
1527 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1528 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1531 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1534 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1535 // This finishes up call legalization.
1536 IsLegalizingCall = false;
1538 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1539 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1540 if (Node->getNumValues() == 2)
1541 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1542 return Result.getValue(Op.ResNo);
1543 case ISD::DYNAMIC_STACKALLOC: {
1544 MVT::ValueType VT = Node->getValueType(0);
1545 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1546 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1547 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1548 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1550 Tmp1 = Result.getValue(0);
1551 Tmp2 = Result.getValue(1);
1552 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1553 default: assert(0 && "This action is not supported yet!");
1554 case TargetLowering::Expand: {
1555 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1556 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1557 " not tell us which reg is the stack pointer!");
1558 SDOperand Chain = Tmp1.getOperand(0);
1560 // Chain the dynamic stack allocation so that it doesn't modify the stack
1561 // pointer when other instructions are using the stack.
1562 Chain = DAG.getCALLSEQ_START(Chain,
1563 DAG.getConstant(0, TLI.getPointerTy()));
1565 SDOperand Size = Tmp2.getOperand(1);
1566 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1567 Chain = SP.getValue(1);
1568 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1569 unsigned StackAlign =
1570 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1571 if (Align > StackAlign)
1572 SP = DAG.getNode(ISD::AND, VT, SP,
1573 DAG.getConstant(-(uint64_t)Align, VT));
1574 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1575 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1578 DAG.getCALLSEQ_END(Chain,
1579 DAG.getConstant(0, TLI.getPointerTy()),
1580 DAG.getConstant(0, TLI.getPointerTy()),
1583 Tmp1 = LegalizeOp(Tmp1);
1584 Tmp2 = LegalizeOp(Tmp2);
1587 case TargetLowering::Custom:
1588 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1590 Tmp1 = LegalizeOp(Tmp3);
1591 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1594 case TargetLowering::Legal:
1597 // Since this op produce two values, make sure to remember that we
1598 // legalized both of them.
1599 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1600 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1601 return Op.ResNo ? Tmp2 : Tmp1;
1603 case ISD::INLINEASM: {
1604 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1605 bool Changed = false;
1606 // Legalize all of the operands of the inline asm, in case they are nodes
1607 // that need to be expanded or something. Note we skip the asm string and
1608 // all of the TargetConstant flags.
1609 SDOperand Op = LegalizeOp(Ops[0]);
1610 Changed = Op != Ops[0];
1613 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1614 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1615 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1616 for (++i; NumVals; ++i, --NumVals) {
1617 SDOperand Op = LegalizeOp(Ops[i]);
1626 Op = LegalizeOp(Ops.back());
1627 Changed |= Op != Ops.back();
1632 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1634 // INLINE asm returns a chain and flag, make sure to add both to the map.
1635 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1636 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1637 return Result.getValue(Op.ResNo);
1640 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1641 // Ensure that libcalls are emitted before a branch.
1642 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1643 Tmp1 = LegalizeOp(Tmp1);
1644 LastCALLSEQ_END = DAG.getEntryNode();
1646 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1649 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1650 // Ensure that libcalls are emitted before a branch.
1651 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1652 Tmp1 = LegalizeOp(Tmp1);
1653 LastCALLSEQ_END = DAG.getEntryNode();
1655 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1656 default: assert(0 && "Indirect target must be legal type (pointer)!");
1658 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1661 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1664 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1665 // Ensure that libcalls are emitted before a branch.
1666 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1667 Tmp1 = LegalizeOp(Tmp1);
1668 LastCALLSEQ_END = DAG.getEntryNode();
1670 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1671 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1673 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1674 default: assert(0 && "This action is not supported yet!");
1675 case TargetLowering::Legal: break;
1676 case TargetLowering::Custom:
1677 Tmp1 = TLI.LowerOperation(Result, DAG);
1678 if (Tmp1.Val) Result = Tmp1;
1680 case TargetLowering::Expand: {
1681 SDOperand Chain = Result.getOperand(0);
1682 SDOperand Table = Result.getOperand(1);
1683 SDOperand Index = Result.getOperand(2);
1685 MVT::ValueType PTy = TLI.getPointerTy();
1686 MachineFunction &MF = DAG.getMachineFunction();
1687 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1688 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1689 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1692 switch (EntrySize) {
1693 default: assert(0 && "Size of jump table not supported yet."); break;
1694 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1695 PseudoSourceValue::getJumpTable(), 0); break;
1696 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1697 PseudoSourceValue::getJumpTable(), 0); break;
1701 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1702 // For PIC, the sequence is:
1703 // BRIND(load(Jumptable + index) + RelocBase)
1704 // RelocBase can be JumpTable, GOT or some sort of global base.
1705 if (PTy != MVT::i32)
1706 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1707 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1708 TLI.getPICJumpTableRelocBase(Table, DAG));
1710 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1715 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1716 // Ensure that libcalls are emitted before a return.
1717 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1718 Tmp1 = LegalizeOp(Tmp1);
1719 LastCALLSEQ_END = DAG.getEntryNode();
1721 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1722 case Expand: assert(0 && "It's impossible to expand bools");
1724 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1727 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1729 // The top bits of the promoted condition are not necessarily zero, ensure
1730 // that the value is properly zero extended.
1731 if (!DAG.MaskedValueIsZero(Tmp2,
1732 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1733 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1737 // Basic block destination (Op#2) is always legal.
1738 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1740 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1741 default: assert(0 && "This action is not supported yet!");
1742 case TargetLowering::Legal: break;
1743 case TargetLowering::Custom:
1744 Tmp1 = TLI.LowerOperation(Result, DAG);
1745 if (Tmp1.Val) Result = Tmp1;
1747 case TargetLowering::Expand:
1748 // Expand brcond's setcc into its constituent parts and create a BR_CC
1750 if (Tmp2.getOpcode() == ISD::SETCC) {
1751 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1752 Tmp2.getOperand(0), Tmp2.getOperand(1),
1753 Node->getOperand(2));
1755 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1756 DAG.getCondCode(ISD::SETNE), Tmp2,
1757 DAG.getConstant(0, Tmp2.getValueType()),
1758 Node->getOperand(2));
1764 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1765 // Ensure that libcalls are emitted before a branch.
1766 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1767 Tmp1 = LegalizeOp(Tmp1);
1768 Tmp2 = Node->getOperand(2); // LHS
1769 Tmp3 = Node->getOperand(3); // RHS
1770 Tmp4 = Node->getOperand(1); // CC
1772 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1773 LastCALLSEQ_END = DAG.getEntryNode();
1775 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1776 // the LHS is a legal SETCC itself. In this case, we need to compare
1777 // the result against zero to select between true and false values.
1778 if (Tmp3.Val == 0) {
1779 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1780 Tmp4 = DAG.getCondCode(ISD::SETNE);
1783 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1784 Node->getOperand(4));
1786 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1787 default: assert(0 && "Unexpected action for BR_CC!");
1788 case TargetLowering::Legal: break;
1789 case TargetLowering::Custom:
1790 Tmp4 = TLI.LowerOperation(Result, DAG);
1791 if (Tmp4.Val) Result = Tmp4;
1796 LoadSDNode *LD = cast<LoadSDNode>(Node);
1797 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1798 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1800 ISD::LoadExtType ExtType = LD->getExtensionType();
1801 if (ExtType == ISD::NON_EXTLOAD) {
1802 MVT::ValueType VT = Node->getValueType(0);
1803 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1804 Tmp3 = Result.getValue(0);
1805 Tmp4 = Result.getValue(1);
1807 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1808 default: assert(0 && "This action is not supported yet!");
1809 case TargetLowering::Legal:
1810 // If this is an unaligned load and the target doesn't support it,
1812 if (!TLI.allowsUnalignedMemoryAccesses()) {
1813 unsigned ABIAlignment = TLI.getTargetData()->
1814 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
1815 if (LD->getAlignment() < ABIAlignment){
1816 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1818 Tmp3 = Result.getOperand(0);
1819 Tmp4 = Result.getOperand(1);
1820 Tmp3 = LegalizeOp(Tmp3);
1821 Tmp4 = LegalizeOp(Tmp4);
1825 case TargetLowering::Custom:
1826 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1828 Tmp3 = LegalizeOp(Tmp1);
1829 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1832 case TargetLowering::Promote: {
1833 // Only promote a load of vector type to another.
1834 assert(MVT::isVector(VT) && "Cannot promote this load!");
1835 // Change base type to a different vector type.
1836 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1838 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1839 LD->getSrcValueOffset(),
1840 LD->isVolatile(), LD->getAlignment());
1841 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1842 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1846 // Since loads produce two values, make sure to remember that we
1847 // legalized both of them.
1848 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1849 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1850 return Op.ResNo ? Tmp4 : Tmp3;
1852 MVT::ValueType SrcVT = LD->getMemoryVT();
1853 unsigned SrcWidth = MVT::getSizeInBits(SrcVT);
1854 int SVOffset = LD->getSrcValueOffset();
1855 unsigned Alignment = LD->getAlignment();
1856 bool isVolatile = LD->isVolatile();
1858 if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) &&
1859 // Some targets pretend to have an i1 loading operation, and actually
1860 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1861 // bits are guaranteed to be zero; it helps the optimizers understand
1862 // that these bits are zero. It is also useful for EXTLOAD, since it
1863 // tells the optimizers that those bits are undefined. It would be
1864 // nice to have an effective generic way of getting these benefits...
1865 // Until such a way is found, don't insist on promoting i1 here.
1866 (SrcVT != MVT::i1 ||
1867 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1868 // Promote to a byte-sized load if not loading an integral number of
1869 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1870 unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT);
1871 MVT::ValueType NVT = MVT::getIntegerType(NewWidth);
1874 // The extra bits are guaranteed to be zero, since we stored them that
1875 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1877 ISD::LoadExtType NewExtType =
1878 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1880 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
1881 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1882 NVT, isVolatile, Alignment);
1884 Ch = Result.getValue(1); // The chain.
1886 if (ExtType == ISD::SEXTLOAD)
1887 // Having the top bits zero doesn't help when sign extending.
1888 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1889 Result, DAG.getValueType(SrcVT));
1890 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1891 // All the top bits are guaranteed to be zero - inform the optimizers.
1892 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
1893 DAG.getValueType(SrcVT));
1895 Tmp1 = LegalizeOp(Result);
1896 Tmp2 = LegalizeOp(Ch);
1897 } else if (SrcWidth & (SrcWidth - 1)) {
1898 // If not loading a power-of-2 number of bits, expand as two loads.
1899 assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) &&
1900 "Unsupported extload!");
1901 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1902 assert(RoundWidth < SrcWidth);
1903 unsigned ExtraWidth = SrcWidth - RoundWidth;
1904 assert(ExtraWidth < RoundWidth);
1905 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1906 "Load size not an integral number of bytes!");
1907 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
1908 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
1909 SDOperand Lo, Hi, Ch;
1910 unsigned IncrementSize;
1912 if (TLI.isLittleEndian()) {
1913 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1914 // Load the bottom RoundWidth bits.
1915 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
1916 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1919 // Load the remaining ExtraWidth bits.
1920 IncrementSize = RoundWidth / 8;
1921 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1922 DAG.getIntPtrConstant(IncrementSize));
1923 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1924 LD->getSrcValue(), SVOffset + IncrementSize,
1925 ExtraVT, isVolatile,
1926 MinAlign(Alignment, IncrementSize));
1928 // Build a factor node to remember that this load is independent of the
1930 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1933 // Move the top bits to the right place.
1934 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
1935 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1937 // Join the hi and lo parts.
1938 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
1940 // Big endian - avoid unaligned loads.
1941 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1942 // Load the top RoundWidth bits.
1943 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1944 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1947 // Load the remaining ExtraWidth bits.
1948 IncrementSize = RoundWidth / 8;
1949 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1950 DAG.getIntPtrConstant(IncrementSize));
1951 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
1952 LD->getSrcValue(), SVOffset + IncrementSize,
1953 ExtraVT, isVolatile,
1954 MinAlign(Alignment, IncrementSize));
1956 // Build a factor node to remember that this load is independent of the
1958 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1961 // Move the top bits to the right place.
1962 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
1963 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1965 // Join the hi and lo parts.
1966 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
1969 Tmp1 = LegalizeOp(Result);
1970 Tmp2 = LegalizeOp(Ch);
1972 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1973 default: assert(0 && "This action is not supported yet!");
1974 case TargetLowering::Custom:
1977 case TargetLowering::Legal:
1978 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1979 Tmp1 = Result.getValue(0);
1980 Tmp2 = Result.getValue(1);
1983 Tmp3 = TLI.LowerOperation(Result, DAG);
1985 Tmp1 = LegalizeOp(Tmp3);
1986 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1989 // If this is an unaligned load and the target doesn't support it,
1991 if (!TLI.allowsUnalignedMemoryAccesses()) {
1992 unsigned ABIAlignment = TLI.getTargetData()->
1993 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
1994 if (LD->getAlignment() < ABIAlignment){
1995 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1997 Tmp1 = Result.getOperand(0);
1998 Tmp2 = Result.getOperand(1);
1999 Tmp1 = LegalizeOp(Tmp1);
2000 Tmp2 = LegalizeOp(Tmp2);
2005 case TargetLowering::Expand:
2006 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2007 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2008 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2009 LD->getSrcValueOffset(),
2010 LD->isVolatile(), LD->getAlignment());
2011 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2012 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2013 Tmp2 = LegalizeOp(Load.getValue(1));
2016 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2017 // Turn the unsupported load into an EXTLOAD followed by an explicit
2018 // zero/sign extend inreg.
2019 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2020 Tmp1, Tmp2, LD->getSrcValue(),
2021 LD->getSrcValueOffset(), SrcVT,
2022 LD->isVolatile(), LD->getAlignment());
2024 if (ExtType == ISD::SEXTLOAD)
2025 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2026 Result, DAG.getValueType(SrcVT));
2028 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2029 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2030 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2035 // Since loads produce two values, make sure to remember that we legalized
2037 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2038 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2039 return Op.ResNo ? Tmp2 : Tmp1;
2042 case ISD::EXTRACT_ELEMENT: {
2043 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
2044 switch (getTypeAction(OpTy)) {
2045 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2047 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2049 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2050 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
2051 TLI.getShiftAmountTy()));
2052 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2055 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2056 Node->getOperand(0));
2060 // Get both the low and high parts.
2061 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2062 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2063 Result = Tmp2; // 1 -> Hi
2065 Result = Tmp1; // 0 -> Lo
2071 case ISD::CopyToReg:
2072 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2074 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2075 "Register type must be legal!");
2076 // Legalize the incoming value (must be a legal type).
2077 Tmp2 = LegalizeOp(Node->getOperand(2));
2078 if (Node->getNumValues() == 1) {
2079 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2081 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2082 if (Node->getNumOperands() == 4) {
2083 Tmp3 = LegalizeOp(Node->getOperand(3));
2084 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2087 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2090 // Since this produces two values, make sure to remember that we legalized
2092 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2093 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2099 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2101 // Ensure that libcalls are emitted before a return.
2102 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2103 Tmp1 = LegalizeOp(Tmp1);
2104 LastCALLSEQ_END = DAG.getEntryNode();
2106 switch (Node->getNumOperands()) {
2108 Tmp2 = Node->getOperand(1);
2109 Tmp3 = Node->getOperand(2); // Signness
2110 switch (getTypeAction(Tmp2.getValueType())) {
2112 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2115 if (!MVT::isVector(Tmp2.getValueType())) {
2117 ExpandOp(Tmp2, Lo, Hi);
2119 // Big endian systems want the hi reg first.
2120 if (!TLI.isLittleEndian())
2124 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2126 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2127 Result = LegalizeOp(Result);
2129 SDNode *InVal = Tmp2.Val;
2130 int InIx = Tmp2.ResNo;
2131 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
2132 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
2134 // Figure out if there is a simple type corresponding to this Vector
2135 // type. If so, convert to the vector type.
2136 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2137 if (TLI.isTypeLegal(TVT)) {
2138 // Turn this into a return of the vector type.
2139 Tmp2 = LegalizeOp(Tmp2);
2140 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2141 } else if (NumElems == 1) {
2142 // Turn this into a return of the scalar type.
2143 Tmp2 = ScalarizeVectorOp(Tmp2);
2144 Tmp2 = LegalizeOp(Tmp2);
2145 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2147 // FIXME: Returns of gcc generic vectors smaller than a legal type
2148 // should be returned in integer registers!
2150 // The scalarized value type may not be legal, e.g. it might require
2151 // promotion or expansion. Relegalize the return.
2152 Result = LegalizeOp(Result);
2154 // FIXME: Returns of gcc generic vectors larger than a legal vector
2155 // type should be returned by reference!
2157 SplitVectorOp(Tmp2, Lo, Hi);
2158 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2159 Result = LegalizeOp(Result);
2164 Tmp2 = PromoteOp(Node->getOperand(1));
2165 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2166 Result = LegalizeOp(Result);
2171 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2173 default: { // ret <values>
2174 SmallVector<SDOperand, 8> NewValues;
2175 NewValues.push_back(Tmp1);
2176 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2177 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2179 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2180 NewValues.push_back(Node->getOperand(i+1));
2184 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
2185 "FIXME: TODO: implement returning non-legal vector types!");
2186 ExpandOp(Node->getOperand(i), Lo, Hi);
2187 NewValues.push_back(Lo);
2188 NewValues.push_back(Node->getOperand(i+1));
2190 NewValues.push_back(Hi);
2191 NewValues.push_back(Node->getOperand(i+1));
2196 assert(0 && "Can't promote multiple return value yet!");
2199 if (NewValues.size() == Node->getNumOperands())
2200 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2202 Result = DAG.getNode(ISD::RET, MVT::Other,
2203 &NewValues[0], NewValues.size());
2208 if (Result.getOpcode() == ISD::RET) {
2209 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2210 default: assert(0 && "This action is not supported yet!");
2211 case TargetLowering::Legal: break;
2212 case TargetLowering::Custom:
2213 Tmp1 = TLI.LowerOperation(Result, DAG);
2214 if (Tmp1.Val) Result = Tmp1;
2220 StoreSDNode *ST = cast<StoreSDNode>(Node);
2221 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2222 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2223 int SVOffset = ST->getSrcValueOffset();
2224 unsigned Alignment = ST->getAlignment();
2225 bool isVolatile = ST->isVolatile();
2227 if (!ST->isTruncatingStore()) {
2228 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2229 // FIXME: We shouldn't do this for TargetConstantFP's.
2230 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2231 // to phase ordering between legalized code and the dag combiner. This
2232 // probably means that we need to integrate dag combiner and legalizer
2234 // We generally can't do this one for long doubles.
2235 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2236 if (CFP->getValueType(0) == MVT::f32 &&
2237 getTypeAction(MVT::i32) == Legal) {
2238 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF().
2239 convertToAPInt().getZExtValue(),
2241 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2242 SVOffset, isVolatile, Alignment);
2244 } else if (CFP->getValueType(0) == MVT::f64) {
2245 // If this target supports 64-bit registers, do a single 64-bit store.
2246 if (getTypeAction(MVT::i64) == Legal) {
2247 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2248 getZExtValue(), MVT::i64);
2249 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2250 SVOffset, isVolatile, Alignment);
2252 } else if (getTypeAction(MVT::i32) == Legal) {
2253 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2254 // stores. If the target supports neither 32- nor 64-bits, this
2255 // xform is certainly not worth it.
2256 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue();
2257 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32);
2258 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32);
2259 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
2261 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2262 SVOffset, isVolatile, Alignment);
2263 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2264 DAG.getIntPtrConstant(4));
2265 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2266 isVolatile, MinAlign(Alignment, 4U));
2268 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2274 switch (getTypeAction(ST->getMemoryVT())) {
2276 Tmp3 = LegalizeOp(ST->getValue());
2277 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2280 MVT::ValueType VT = Tmp3.getValueType();
2281 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2282 default: assert(0 && "This action is not supported yet!");
2283 case TargetLowering::Legal:
2284 // If this is an unaligned store and the target doesn't support it,
2286 if (!TLI.allowsUnalignedMemoryAccesses()) {
2287 unsigned ABIAlignment = TLI.getTargetData()->
2288 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2289 if (ST->getAlignment() < ABIAlignment)
2290 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2294 case TargetLowering::Custom:
2295 Tmp1 = TLI.LowerOperation(Result, DAG);
2296 if (Tmp1.Val) Result = Tmp1;
2298 case TargetLowering::Promote:
2299 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2300 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2301 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2302 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2303 ST->getSrcValue(), SVOffset, isVolatile,
2310 // Truncate the value and store the result.
2311 Tmp3 = PromoteOp(ST->getValue());
2312 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2313 SVOffset, ST->getMemoryVT(),
2314 isVolatile, Alignment);
2318 unsigned IncrementSize = 0;
2321 // If this is a vector type, then we have to calculate the increment as
2322 // the product of the element size in bytes, and the number of elements
2323 // in the high half of the vector.
2324 if (MVT::isVector(ST->getValue().getValueType())) {
2325 SDNode *InVal = ST->getValue().Val;
2326 int InIx = ST->getValue().ResNo;
2327 MVT::ValueType InVT = InVal->getValueType(InIx);
2328 unsigned NumElems = MVT::getVectorNumElements(InVT);
2329 MVT::ValueType EVT = MVT::getVectorElementType(InVT);
2331 // Figure out if there is a simple type corresponding to this Vector
2332 // type. If so, convert to the vector type.
2333 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2334 if (TLI.isTypeLegal(TVT)) {
2335 // Turn this into a normal store of the vector type.
2336 Tmp3 = LegalizeOp(Node->getOperand(1));
2337 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2338 SVOffset, isVolatile, Alignment);
2339 Result = LegalizeOp(Result);
2341 } else if (NumElems == 1) {
2342 // Turn this into a normal store of the scalar type.
2343 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
2344 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2345 SVOffset, isVolatile, Alignment);
2346 // The scalarized value type may not be legal, e.g. it might require
2347 // promotion or expansion. Relegalize the scalar store.
2348 Result = LegalizeOp(Result);
2351 SplitVectorOp(Node->getOperand(1), Lo, Hi);
2352 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
2353 MVT::getSizeInBits(EVT)/8;
2356 ExpandOp(Node->getOperand(1), Lo, Hi);
2357 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2359 if (!TLI.isLittleEndian())
2363 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2364 SVOffset, isVolatile, Alignment);
2366 if (Hi.Val == NULL) {
2367 // Must be int <-> float one-to-one expansion.
2372 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2373 DAG.getIntPtrConstant(IncrementSize));
2374 assert(isTypeLegal(Tmp2.getValueType()) &&
2375 "Pointers must be legal!");
2376 SVOffset += IncrementSize;
2377 Alignment = MinAlign(Alignment, IncrementSize);
2378 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2379 SVOffset, isVolatile, Alignment);
2380 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2384 switch (getTypeAction(ST->getValue().getValueType())) {
2386 Tmp3 = LegalizeOp(ST->getValue());
2389 // We can promote the value, the truncstore will still take care of it.
2390 Tmp3 = PromoteOp(ST->getValue());
2393 // Just store the low part. This may become a non-trunc store, so make
2394 // sure to use getTruncStore, not UpdateNodeOperands below.
2395 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2396 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2397 SVOffset, MVT::i8, isVolatile, Alignment);
2400 MVT::ValueType StVT = ST->getMemoryVT();
2401 unsigned StWidth = MVT::getSizeInBits(StVT);
2403 if (StWidth != MVT::getStoreSizeInBits(StVT)) {
2404 // Promote to a byte-sized store with upper bits zero if not
2405 // storing an integral number of bytes. For example, promote
2406 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2407 MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT));
2408 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2409 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2410 SVOffset, NVT, isVolatile, Alignment);
2411 } else if (StWidth & (StWidth - 1)) {
2412 // If not storing a power-of-2 number of bits, expand as two stores.
2413 assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) &&
2414 "Unsupported truncstore!");
2415 unsigned RoundWidth = 1 << Log2_32(StWidth);
2416 assert(RoundWidth < StWidth);
2417 unsigned ExtraWidth = StWidth - RoundWidth;
2418 assert(ExtraWidth < RoundWidth);
2419 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2420 "Store size not an integral number of bytes!");
2421 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
2422 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
2424 unsigned IncrementSize;
2426 if (TLI.isLittleEndian()) {
2427 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2428 // Store the bottom RoundWidth bits.
2429 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2431 isVolatile, Alignment);
2433 // Store the remaining ExtraWidth bits.
2434 IncrementSize = RoundWidth / 8;
2435 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2436 DAG.getIntPtrConstant(IncrementSize));
2437 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2438 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2439 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2440 SVOffset + IncrementSize, ExtraVT, isVolatile,
2441 MinAlign(Alignment, IncrementSize));
2443 // Big endian - avoid unaligned stores.
2444 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2445 // Store the top RoundWidth bits.
2446 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2447 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2448 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2449 RoundVT, isVolatile, Alignment);
2451 // Store the remaining ExtraWidth bits.
2452 IncrementSize = RoundWidth / 8;
2453 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2454 DAG.getIntPtrConstant(IncrementSize));
2455 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2456 SVOffset + IncrementSize, ExtraVT, isVolatile,
2457 MinAlign(Alignment, IncrementSize));
2460 // The order of the stores doesn't matter.
2461 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2463 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2464 Tmp2 != ST->getBasePtr())
2465 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2468 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2469 default: assert(0 && "This action is not supported yet!");
2470 case TargetLowering::Legal:
2471 // If this is an unaligned store and the target doesn't support it,
2473 if (!TLI.allowsUnalignedMemoryAccesses()) {
2474 unsigned ABIAlignment = TLI.getTargetData()->
2475 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2476 if (ST->getAlignment() < ABIAlignment)
2477 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2481 case TargetLowering::Custom:
2482 Result = TLI.LowerOperation(Result, DAG);
2485 // TRUNCSTORE:i16 i32 -> STORE i16
2486 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2487 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2488 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2489 isVolatile, Alignment);
2497 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2498 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2500 case ISD::STACKSAVE:
2501 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2502 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2503 Tmp1 = Result.getValue(0);
2504 Tmp2 = Result.getValue(1);
2506 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2507 default: assert(0 && "This action is not supported yet!");
2508 case TargetLowering::Legal: break;
2509 case TargetLowering::Custom:
2510 Tmp3 = TLI.LowerOperation(Result, DAG);
2512 Tmp1 = LegalizeOp(Tmp3);
2513 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2516 case TargetLowering::Expand:
2517 // Expand to CopyFromReg if the target set
2518 // StackPointerRegisterToSaveRestore.
2519 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2520 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2521 Node->getValueType(0));
2522 Tmp2 = Tmp1.getValue(1);
2524 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2525 Tmp2 = Node->getOperand(0);
2530 // Since stacksave produce two values, make sure to remember that we
2531 // legalized both of them.
2532 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2533 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2534 return Op.ResNo ? Tmp2 : Tmp1;
2536 case ISD::STACKRESTORE:
2537 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2538 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2539 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2541 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2542 default: assert(0 && "This action is not supported yet!");
2543 case TargetLowering::Legal: break;
2544 case TargetLowering::Custom:
2545 Tmp1 = TLI.LowerOperation(Result, DAG);
2546 if (Tmp1.Val) Result = Tmp1;
2548 case TargetLowering::Expand:
2549 // Expand to CopyToReg if the target set
2550 // StackPointerRegisterToSaveRestore.
2551 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2552 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2560 case ISD::READCYCLECOUNTER:
2561 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2562 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2563 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2564 Node->getValueType(0))) {
2565 default: assert(0 && "This action is not supported yet!");
2566 case TargetLowering::Legal:
2567 Tmp1 = Result.getValue(0);
2568 Tmp2 = Result.getValue(1);
2570 case TargetLowering::Custom:
2571 Result = TLI.LowerOperation(Result, DAG);
2572 Tmp1 = LegalizeOp(Result.getValue(0));
2573 Tmp2 = LegalizeOp(Result.getValue(1));
2577 // Since rdcc produce two values, make sure to remember that we legalized
2579 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2580 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2584 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2585 case Expand: assert(0 && "It's impossible to expand bools");
2587 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2590 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2591 // Make sure the condition is either zero or one.
2592 if (!DAG.MaskedValueIsZero(Tmp1,
2593 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2594 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2597 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2598 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2600 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2602 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2603 default: assert(0 && "This action is not supported yet!");
2604 case TargetLowering::Legal: break;
2605 case TargetLowering::Custom: {
2606 Tmp1 = TLI.LowerOperation(Result, DAG);
2607 if (Tmp1.Val) Result = Tmp1;
2610 case TargetLowering::Expand:
2611 if (Tmp1.getOpcode() == ISD::SETCC) {
2612 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2614 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2616 Result = DAG.getSelectCC(Tmp1,
2617 DAG.getConstant(0, Tmp1.getValueType()),
2618 Tmp2, Tmp3, ISD::SETNE);
2621 case TargetLowering::Promote: {
2622 MVT::ValueType NVT =
2623 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2624 unsigned ExtOp, TruncOp;
2625 if (MVT::isVector(Tmp2.getValueType())) {
2626 ExtOp = ISD::BIT_CONVERT;
2627 TruncOp = ISD::BIT_CONVERT;
2628 } else if (MVT::isInteger(Tmp2.getValueType())) {
2629 ExtOp = ISD::ANY_EXTEND;
2630 TruncOp = ISD::TRUNCATE;
2632 ExtOp = ISD::FP_EXTEND;
2633 TruncOp = ISD::FP_ROUND;
2635 // Promote each of the values to the new type.
2636 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2637 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2638 // Perform the larger operation, then round down.
2639 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2640 if (TruncOp != ISD::FP_ROUND)
2641 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2643 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2644 DAG.getIntPtrConstant(0));
2649 case ISD::SELECT_CC: {
2650 Tmp1 = Node->getOperand(0); // LHS
2651 Tmp2 = Node->getOperand(1); // RHS
2652 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2653 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2654 SDOperand CC = Node->getOperand(4);
2656 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2658 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2659 // the LHS is a legal SETCC itself. In this case, we need to compare
2660 // the result against zero to select between true and false values.
2661 if (Tmp2.Val == 0) {
2662 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2663 CC = DAG.getCondCode(ISD::SETNE);
2665 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2667 // Everything is legal, see if we should expand this op or something.
2668 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2669 default: assert(0 && "This action is not supported yet!");
2670 case TargetLowering::Legal: break;
2671 case TargetLowering::Custom:
2672 Tmp1 = TLI.LowerOperation(Result, DAG);
2673 if (Tmp1.Val) Result = Tmp1;
2679 Tmp1 = Node->getOperand(0);
2680 Tmp2 = Node->getOperand(1);
2681 Tmp3 = Node->getOperand(2);
2682 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2684 // If we had to Expand the SetCC operands into a SELECT node, then it may
2685 // not always be possible to return a true LHS & RHS. In this case, just
2686 // return the value we legalized, returned in the LHS
2687 if (Tmp2.Val == 0) {
2692 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2693 default: assert(0 && "Cannot handle this action for SETCC yet!");
2694 case TargetLowering::Custom:
2697 case TargetLowering::Legal:
2698 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2700 Tmp4 = TLI.LowerOperation(Result, DAG);
2701 if (Tmp4.Val) Result = Tmp4;
2704 case TargetLowering::Promote: {
2705 // First step, figure out the appropriate operation to use.
2706 // Allow SETCC to not be supported for all legal data types
2707 // Mostly this targets FP
2708 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2709 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2711 // Scan for the appropriate larger type to use.
2713 NewInTy = (MVT::ValueType)(NewInTy+1);
2715 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2716 "Fell off of the edge of the integer world");
2717 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2718 "Fell off of the edge of the floating point world");
2720 // If the target supports SETCC of this type, use it.
2721 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2724 if (MVT::isInteger(NewInTy))
2725 assert(0 && "Cannot promote Legal Integer SETCC yet");
2727 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2728 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2730 Tmp1 = LegalizeOp(Tmp1);
2731 Tmp2 = LegalizeOp(Tmp2);
2732 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2733 Result = LegalizeOp(Result);
2736 case TargetLowering::Expand:
2737 // Expand a setcc node into a select_cc of the same condition, lhs, and
2738 // rhs that selects between const 1 (true) and const 0 (false).
2739 MVT::ValueType VT = Node->getValueType(0);
2740 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2741 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2748 case ISD::MEMMOVE: {
2749 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2750 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2752 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2753 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2754 case Expand: assert(0 && "Cannot expand a byte!");
2756 Tmp3 = LegalizeOp(Node->getOperand(2));
2759 Tmp3 = PromoteOp(Node->getOperand(2));
2763 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2767 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2769 // Length is too big, just take the lo-part of the length.
2771 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2775 Tmp4 = LegalizeOp(Node->getOperand(3));
2778 Tmp4 = PromoteOp(Node->getOperand(3));
2783 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2784 case Expand: assert(0 && "Cannot expand this yet!");
2786 Tmp5 = LegalizeOp(Node->getOperand(4));
2789 Tmp5 = PromoteOp(Node->getOperand(4));
2794 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool
2795 case Expand: assert(0 && "Cannot expand this yet!");
2797 Tmp6 = LegalizeOp(Node->getOperand(5));
2800 Tmp6 = PromoteOp(Node->getOperand(5));
2804 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2805 default: assert(0 && "This action not implemented for this operation!");
2806 case TargetLowering::Custom:
2809 case TargetLowering::Legal: {
2810 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 };
2811 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
2813 Tmp1 = TLI.LowerOperation(Result, DAG);
2814 if (Tmp1.Val) Result = Tmp1;
2818 case TargetLowering::Expand: {
2819 // Otherwise, the target does not support this operation. Lower the
2820 // operation to an explicit libcall as appropriate.
2821 MVT::ValueType IntPtr = TLI.getPointerTy();
2822 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2823 TargetLowering::ArgListTy Args;
2824 TargetLowering::ArgListEntry Entry;
2826 const char *FnName = 0;
2827 if (Node->getOpcode() == ISD::MEMSET) {
2828 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2829 Args.push_back(Entry);
2830 // Extend the (previously legalized) ubyte argument to be an int value
2832 if (Tmp3.getValueType() > MVT::i32)
2833 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2835 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2836 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2837 Args.push_back(Entry);
2838 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2839 Args.push_back(Entry);
2842 } else if (Node->getOpcode() == ISD::MEMCPY ||
2843 Node->getOpcode() == ISD::MEMMOVE) {
2844 Entry.Ty = IntPtrTy;
2845 Entry.Node = Tmp2; Args.push_back(Entry);
2846 Entry.Node = Tmp3; Args.push_back(Entry);
2847 Entry.Node = Tmp4; Args.push_back(Entry);
2848 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2850 assert(0 && "Unknown op!");
2853 std::pair<SDOperand,SDOperand> CallResult =
2854 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2855 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2856 Result = CallResult.second;
2863 case ISD::SHL_PARTS:
2864 case ISD::SRA_PARTS:
2865 case ISD::SRL_PARTS: {
2866 SmallVector<SDOperand, 8> Ops;
2867 bool Changed = false;
2868 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2869 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2870 Changed |= Ops.back() != Node->getOperand(i);
2873 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2875 switch (TLI.getOperationAction(Node->getOpcode(),
2876 Node->getValueType(0))) {
2877 default: assert(0 && "This action is not supported yet!");
2878 case TargetLowering::Legal: break;
2879 case TargetLowering::Custom:
2880 Tmp1 = TLI.LowerOperation(Result, DAG);
2882 SDOperand Tmp2, RetVal(0, 0);
2883 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2884 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2885 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2889 assert(RetVal.Val && "Illegal result number");
2895 // Since these produce multiple values, make sure to remember that we
2896 // legalized all of them.
2897 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2898 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2899 return Result.getValue(Op.ResNo);
2921 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2922 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2923 case Expand: assert(0 && "Not possible");
2925 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2928 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2932 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2934 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2935 default: assert(0 && "BinOp legalize operation not supported");
2936 case TargetLowering::Legal: break;
2937 case TargetLowering::Custom:
2938 Tmp1 = TLI.LowerOperation(Result, DAG);
2939 if (Tmp1.Val) Result = Tmp1;
2941 case TargetLowering::Expand: {
2942 MVT::ValueType VT = Op.getValueType();
2944 // See if multiply or divide can be lowered using two-result operations.
2945 SDVTList VTs = DAG.getVTList(VT, VT);
2946 if (Node->getOpcode() == ISD::MUL) {
2947 // We just need the low half of the multiply; try both the signed
2948 // and unsigned forms. If the target supports both SMUL_LOHI and
2949 // UMUL_LOHI, form a preference by checking which forms of plain
2950 // MULH it supports.
2951 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2952 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2953 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2954 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2955 unsigned OpToUse = 0;
2956 if (HasSMUL_LOHI && !HasMULHS) {
2957 OpToUse = ISD::SMUL_LOHI;
2958 } else if (HasUMUL_LOHI && !HasMULHU) {
2959 OpToUse = ISD::UMUL_LOHI;
2960 } else if (HasSMUL_LOHI) {
2961 OpToUse = ISD::SMUL_LOHI;
2962 } else if (HasUMUL_LOHI) {
2963 OpToUse = ISD::UMUL_LOHI;
2966 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
2970 if (Node->getOpcode() == ISD::MULHS &&
2971 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
2972 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2975 if (Node->getOpcode() == ISD::MULHU &&
2976 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
2977 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2980 if (Node->getOpcode() == ISD::SDIV &&
2981 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
2982 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2985 if (Node->getOpcode() == ISD::UDIV &&
2986 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
2987 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2991 // Check to see if we have a libcall for this operator.
2992 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2993 bool isSigned = false;
2994 switch (Node->getOpcode()) {
2997 if (VT == MVT::i32) {
2998 LC = Node->getOpcode() == ISD::UDIV
2999 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3000 isSigned = Node->getOpcode() == ISD::SDIV;
3004 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3005 RTLIB::POW_PPCF128);
3009 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3011 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3015 assert(MVT::isVector(Node->getValueType(0)) &&
3016 "Cannot expand this binary operator!");
3017 // Expand the operation into a bunch of nasty scalar code.
3018 Result = LegalizeOp(UnrollVectorOp(Op));
3021 case TargetLowering::Promote: {
3022 switch (Node->getOpcode()) {
3023 default: assert(0 && "Do not know how to promote this BinOp!");
3027 MVT::ValueType OVT = Node->getValueType(0);
3028 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3029 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
3030 // Bit convert each of the values to the new type.
3031 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3032 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3033 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3034 // Bit convert the result back the original type.
3035 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3043 case ISD::SMUL_LOHI:
3044 case ISD::UMUL_LOHI:
3047 // These nodes will only be produced by target-specific lowering, so
3048 // they shouldn't be here if they aren't legal.
3049 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3050 "This must be legal!");
3052 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3053 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3054 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3057 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3058 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3059 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3060 case Expand: assert(0 && "Not possible");
3062 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3065 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3069 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3071 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3072 default: assert(0 && "Operation not supported");
3073 case TargetLowering::Custom:
3074 Tmp1 = TLI.LowerOperation(Result, DAG);
3075 if (Tmp1.Val) Result = Tmp1;
3077 case TargetLowering::Legal: break;
3078 case TargetLowering::Expand: {
3079 // If this target supports fabs/fneg natively and select is cheap,
3080 // do this efficiently.
3081 if (!TLI.isSelectExpensive() &&
3082 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3083 TargetLowering::Legal &&
3084 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3085 TargetLowering::Legal) {
3086 // Get the sign bit of the RHS.
3087 MVT::ValueType IVT =
3088 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3089 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3090 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
3091 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3092 // Get the absolute value of the result.
3093 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3094 // Select between the nabs and abs value based on the sign bit of
3096 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3097 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3100 Result = LegalizeOp(Result);
3104 // Otherwise, do bitwise ops!
3105 MVT::ValueType NVT =
3106 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3107 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3108 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3109 Result = LegalizeOp(Result);
3117 Tmp1 = LegalizeOp(Node->getOperand(0));
3118 Tmp2 = LegalizeOp(Node->getOperand(1));
3119 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3120 // Since this produces two values, make sure to remember that we legalized
3122 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3123 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3128 Tmp1 = LegalizeOp(Node->getOperand(0));
3129 Tmp2 = LegalizeOp(Node->getOperand(1));
3130 Tmp3 = LegalizeOp(Node->getOperand(2));
3131 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3132 // Since this produces two values, make sure to remember that we legalized
3134 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3135 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3138 case ISD::BUILD_PAIR: {
3139 MVT::ValueType PairTy = Node->getValueType(0);
3140 // TODO: handle the case where the Lo and Hi operands are not of legal type
3141 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3142 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3143 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3144 case TargetLowering::Promote:
3145 case TargetLowering::Custom:
3146 assert(0 && "Cannot promote/custom this yet!");
3147 case TargetLowering::Legal:
3148 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3149 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3151 case TargetLowering::Expand:
3152 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3153 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3154 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3155 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
3156 TLI.getShiftAmountTy()));
3157 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3166 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3167 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3169 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3170 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3171 case TargetLowering::Custom:
3174 case TargetLowering::Legal:
3175 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3177 Tmp1 = TLI.LowerOperation(Result, DAG);
3178 if (Tmp1.Val) Result = Tmp1;
3181 case TargetLowering::Expand: {
3182 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3183 bool isSigned = DivOpc == ISD::SDIV;
3184 MVT::ValueType VT = Node->getValueType(0);
3186 // See if remainder can be lowered using two-result operations.
3187 SDVTList VTs = DAG.getVTList(VT, VT);
3188 if (Node->getOpcode() == ISD::SREM &&
3189 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3190 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3193 if (Node->getOpcode() == ISD::UREM &&
3194 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3195 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3199 if (MVT::isInteger(VT)) {
3200 if (TLI.getOperationAction(DivOpc, VT) ==
3201 TargetLowering::Legal) {
3203 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3204 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3205 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3206 } else if (MVT::isVector(VT)) {
3207 Result = LegalizeOp(UnrollVectorOp(Op));
3209 assert(VT == MVT::i32 &&
3210 "Cannot expand this binary operator!");
3211 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3212 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3214 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3217 assert(MVT::isFloatingPoint(VT) &&
3218 "remainder op must have integer or floating-point type");
3219 if (MVT::isVector(VT)) {
3220 Result = LegalizeOp(UnrollVectorOp(Op));
3222 // Floating point mod -> fmod libcall.
3223 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3224 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3226 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3227 false/*sign irrelevant*/, Dummy);
3235 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3236 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3238 MVT::ValueType VT = Node->getValueType(0);
3239 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3240 default: assert(0 && "This action is not supported yet!");
3241 case TargetLowering::Custom:
3244 case TargetLowering::Legal:
3245 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3246 Result = Result.getValue(0);
3247 Tmp1 = Result.getValue(1);
3250 Tmp2 = TLI.LowerOperation(Result, DAG);
3252 Result = LegalizeOp(Tmp2);
3253 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3257 case TargetLowering::Expand: {
3258 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3259 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3260 // Increment the pointer, VAList, to the next vaarg
3261 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3262 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3263 TLI.getPointerTy()));
3264 // Store the incremented VAList to the legalized pointer
3265 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3266 // Load the actual argument out of the pointer VAList
3267 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3268 Tmp1 = LegalizeOp(Result.getValue(1));
3269 Result = LegalizeOp(Result);
3273 // Since VAARG produces two values, make sure to remember that we
3274 // legalized both of them.
3275 AddLegalizedOperand(SDOperand(Node, 0), Result);
3276 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3277 return Op.ResNo ? Tmp1 : Result;
3281 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3282 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3283 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3285 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3286 default: assert(0 && "This action is not supported yet!");
3287 case TargetLowering::Custom:
3290 case TargetLowering::Legal:
3291 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3292 Node->getOperand(3), Node->getOperand(4));
3294 Tmp1 = TLI.LowerOperation(Result, DAG);
3295 if (Tmp1.Val) Result = Tmp1;
3298 case TargetLowering::Expand:
3299 // This defaults to loading a pointer from the input and storing it to the
3300 // output, returning the chain.
3301 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3302 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3303 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VD, 0);
3304 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VS, 0);
3310 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3311 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3313 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3314 default: assert(0 && "This action is not supported yet!");
3315 case TargetLowering::Custom:
3318 case TargetLowering::Legal:
3319 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3321 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3322 if (Tmp1.Val) Result = Tmp1;
3325 case TargetLowering::Expand:
3326 Result = Tmp1; // Default to a no-op, return the chain
3332 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3333 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3335 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3337 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3338 default: assert(0 && "This action is not supported yet!");
3339 case TargetLowering::Legal: break;
3340 case TargetLowering::Custom:
3341 Tmp1 = TLI.LowerOperation(Result, DAG);
3342 if (Tmp1.Val) Result = Tmp1;
3349 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3350 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3351 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3352 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3354 assert(0 && "ROTL/ROTR legalize operation not supported");
3356 case TargetLowering::Legal:
3358 case TargetLowering::Custom:
3359 Tmp1 = TLI.LowerOperation(Result, DAG);
3360 if (Tmp1.Val) Result = Tmp1;
3362 case TargetLowering::Promote:
3363 assert(0 && "Do not know how to promote ROTL/ROTR");
3365 case TargetLowering::Expand:
3366 assert(0 && "Do not know how to expand ROTL/ROTR");
3372 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3373 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3374 case TargetLowering::Custom:
3375 assert(0 && "Cannot custom legalize this yet!");
3376 case TargetLowering::Legal:
3377 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3379 case TargetLowering::Promote: {
3380 MVT::ValueType OVT = Tmp1.getValueType();
3381 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3382 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
3384 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3385 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3386 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3387 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3390 case TargetLowering::Expand:
3391 Result = ExpandBSWAP(Tmp1);
3399 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3400 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3401 case TargetLowering::Custom:
3402 case TargetLowering::Legal:
3403 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3404 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3405 TargetLowering::Custom) {
3406 Tmp1 = TLI.LowerOperation(Result, DAG);
3412 case TargetLowering::Promote: {
3413 MVT::ValueType OVT = Tmp1.getValueType();
3414 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3416 // Zero extend the argument.
3417 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3418 // Perform the larger operation, then subtract if needed.
3419 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3420 switch (Node->getOpcode()) {
3425 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3426 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3427 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3429 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3430 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
3433 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3434 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3435 DAG.getConstant(MVT::getSizeInBits(NVT) -
3436 MVT::getSizeInBits(OVT), NVT));
3441 case TargetLowering::Expand:
3442 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3453 Tmp1 = LegalizeOp(Node->getOperand(0));
3454 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3455 case TargetLowering::Promote:
3456 case TargetLowering::Custom:
3459 case TargetLowering::Legal:
3460 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3462 Tmp1 = TLI.LowerOperation(Result, DAG);
3463 if (Tmp1.Val) Result = Tmp1;
3466 case TargetLowering::Expand:
3467 switch (Node->getOpcode()) {
3468 default: assert(0 && "Unreachable!");
3470 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3471 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3472 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3475 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3476 MVT::ValueType VT = Node->getValueType(0);
3477 Tmp2 = DAG.getConstantFP(0.0, VT);
3478 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
3479 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3480 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3486 MVT::ValueType VT = Node->getValueType(0);
3488 // Expand unsupported unary vector operators by unrolling them.
3489 if (MVT::isVector(VT)) {
3490 Result = LegalizeOp(UnrollVectorOp(Op));
3494 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3495 switch(Node->getOpcode()) {
3497 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3498 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3501 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3502 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3505 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3506 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3508 default: assert(0 && "Unreachable!");
3511 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3512 false/*sign irrelevant*/, Dummy);
3520 MVT::ValueType VT = Node->getValueType(0);
3522 // Expand unsupported unary vector operators by unrolling them.
3523 if (MVT::isVector(VT)) {
3524 Result = LegalizeOp(UnrollVectorOp(Op));
3528 // We always lower FPOWI into a libcall. No target support for it yet.
3529 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3530 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3532 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3533 false/*sign irrelevant*/, Dummy);
3536 case ISD::BIT_CONVERT:
3537 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3538 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3539 Node->getValueType(0));
3540 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3541 // The input has to be a vector type, we have to either scalarize it, pack
3542 // it, or convert it based on whether the input vector type is legal.
3543 SDNode *InVal = Node->getOperand(0).Val;
3544 int InIx = Node->getOperand(0).ResNo;
3545 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
3546 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
3548 // Figure out if there is a simple type corresponding to this Vector
3549 // type. If so, convert to the vector type.
3550 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3551 if (TLI.isTypeLegal(TVT)) {
3552 // Turn this into a bit convert of the vector input.
3553 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3554 LegalizeOp(Node->getOperand(0)));
3556 } else if (NumElems == 1) {
3557 // Turn this into a bit convert of the scalar input.
3558 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3559 ScalarizeVectorOp(Node->getOperand(0)));
3562 // FIXME: UNIMP! Store then reload
3563 assert(0 && "Cast from unsupported vector type not implemented yet!");
3566 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3567 Node->getOperand(0).getValueType())) {
3568 default: assert(0 && "Unknown operation action!");
3569 case TargetLowering::Expand:
3570 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3571 Node->getValueType(0));
3573 case TargetLowering::Legal:
3574 Tmp1 = LegalizeOp(Node->getOperand(0));
3575 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3581 // Conversion operators. The source and destination have different types.
3582 case ISD::SINT_TO_FP:
3583 case ISD::UINT_TO_FP: {
3584 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3585 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3587 switch (TLI.getOperationAction(Node->getOpcode(),
3588 Node->getOperand(0).getValueType())) {
3589 default: assert(0 && "Unknown operation action!");
3590 case TargetLowering::Custom:
3593 case TargetLowering::Legal:
3594 Tmp1 = LegalizeOp(Node->getOperand(0));
3595 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3597 Tmp1 = TLI.LowerOperation(Result, DAG);
3598 if (Tmp1.Val) Result = Tmp1;
3601 case TargetLowering::Expand:
3602 Result = ExpandLegalINT_TO_FP(isSigned,
3603 LegalizeOp(Node->getOperand(0)),
3604 Node->getValueType(0));
3606 case TargetLowering::Promote:
3607 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3608 Node->getValueType(0),
3614 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3615 Node->getValueType(0), Node->getOperand(0));
3618 Tmp1 = PromoteOp(Node->getOperand(0));
3620 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3621 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3623 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3624 Node->getOperand(0).getValueType());
3626 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3627 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3633 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3635 Tmp1 = LegalizeOp(Node->getOperand(0));
3636 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3639 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3641 // Since the result is legal, we should just be able to truncate the low
3642 // part of the source.
3643 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3646 Result = PromoteOp(Node->getOperand(0));
3647 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3652 case ISD::FP_TO_SINT:
3653 case ISD::FP_TO_UINT:
3654 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3656 Tmp1 = LegalizeOp(Node->getOperand(0));
3658 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3659 default: assert(0 && "Unknown operation action!");
3660 case TargetLowering::Custom:
3663 case TargetLowering::Legal:
3664 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3666 Tmp1 = TLI.LowerOperation(Result, DAG);
3667 if (Tmp1.Val) Result = Tmp1;
3670 case TargetLowering::Promote:
3671 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3672 Node->getOpcode() == ISD::FP_TO_SINT);
3674 case TargetLowering::Expand:
3675 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3676 SDOperand True, False;
3677 MVT::ValueType VT = Node->getOperand(0).getValueType();
3678 MVT::ValueType NVT = Node->getValueType(0);
3679 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1;
3680 const uint64_t zero[] = {0, 0};
3681 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3682 uint64_t x = 1ULL << ShiftAmt;
3683 (void)apf.convertFromZeroExtendedInteger
3684 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven);
3685 Tmp2 = DAG.getConstantFP(apf, VT);
3686 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3687 Node->getOperand(0), Tmp2, ISD::SETLT);
3688 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3689 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3690 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3692 False = DAG.getNode(ISD::XOR, NVT, False,
3693 DAG.getConstant(1ULL << ShiftAmt, NVT));
3694 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3697 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3703 MVT::ValueType VT = Op.getValueType();
3704 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3705 // Convert ppcf128 to i32
3706 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3707 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3708 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3709 Node->getOperand(0), DAG.getValueType(MVT::f64));
3710 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3711 DAG.getIntPtrConstant(1));
3712 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3714 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3715 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3716 Tmp2 = DAG.getConstantFP(apf, OVT);
3717 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3718 // FIXME: generated code sucks.
3719 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3720 DAG.getNode(ISD::ADD, MVT::i32,
3721 DAG.getNode(ISD::FP_TO_SINT, VT,
3722 DAG.getNode(ISD::FSUB, OVT,
3723 Node->getOperand(0), Tmp2)),
3724 DAG.getConstant(0x80000000, MVT::i32)),
3725 DAG.getNode(ISD::FP_TO_SINT, VT,
3726 Node->getOperand(0)),
3727 DAG.getCondCode(ISD::SETGE));
3731 // Convert f32 / f64 to i32 / i64.
3732 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3733 switch (Node->getOpcode()) {
3734 case ISD::FP_TO_SINT: {
3735 if (OVT == MVT::f32)
3736 LC = (VT == MVT::i32)
3737 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3738 else if (OVT == MVT::f64)
3739 LC = (VT == MVT::i32)
3740 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3741 else if (OVT == MVT::f80) {
3742 assert(VT == MVT::i64);
3743 LC = RTLIB::FPTOSINT_F80_I64;
3745 else if (OVT == MVT::ppcf128) {
3746 assert(VT == MVT::i64);
3747 LC = RTLIB::FPTOSINT_PPCF128_I64;
3751 case ISD::FP_TO_UINT: {
3752 if (OVT == MVT::f32)
3753 LC = (VT == MVT::i32)
3754 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3755 else if (OVT == MVT::f64)
3756 LC = (VT == MVT::i32)
3757 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3758 else if (OVT == MVT::f80) {
3759 LC = (VT == MVT::i32)
3760 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64;
3762 else if (OVT == MVT::ppcf128) {
3763 assert(VT == MVT::i64);
3764 LC = RTLIB::FPTOUINT_PPCF128_I64;
3768 default: assert(0 && "Unreachable!");
3771 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3772 false/*sign irrelevant*/, Dummy);
3776 Tmp1 = PromoteOp(Node->getOperand(0));
3777 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3778 Result = LegalizeOp(Result);
3783 case ISD::FP_EXTEND: {
3784 MVT::ValueType DstVT = Op.getValueType();
3785 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3786 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3787 // The only other way we can lower this is to turn it into a STORE,
3788 // LOAD pair, targetting a temporary location (a stack slot).
3789 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3792 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3793 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3795 Tmp1 = LegalizeOp(Node->getOperand(0));
3796 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3799 Tmp1 = PromoteOp(Node->getOperand(0));
3800 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3805 case ISD::FP_ROUND: {
3806 MVT::ValueType DstVT = Op.getValueType();
3807 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3808 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3809 if (SrcVT == MVT::ppcf128) {
3811 ExpandOp(Node->getOperand(0), Lo, Result);
3812 // Round it the rest of the way (e.g. to f32) if needed.
3813 if (DstVT!=MVT::f64)
3814 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3817 // The only other way we can lower this is to turn it into a STORE,
3818 // LOAD pair, targetting a temporary location (a stack slot).
3819 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3822 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3823 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3825 Tmp1 = LegalizeOp(Node->getOperand(0));
3826 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3829 Tmp1 = PromoteOp(Node->getOperand(0));
3830 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3831 Node->getOperand(1));
3836 case ISD::ANY_EXTEND:
3837 case ISD::ZERO_EXTEND:
3838 case ISD::SIGN_EXTEND:
3839 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3840 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3842 Tmp1 = LegalizeOp(Node->getOperand(0));
3843 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3846 switch (Node->getOpcode()) {
3847 case ISD::ANY_EXTEND:
3848 Tmp1 = PromoteOp(Node->getOperand(0));
3849 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3851 case ISD::ZERO_EXTEND:
3852 Result = PromoteOp(Node->getOperand(0));
3853 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3854 Result = DAG.getZeroExtendInReg(Result,
3855 Node->getOperand(0).getValueType());
3857 case ISD::SIGN_EXTEND:
3858 Result = PromoteOp(Node->getOperand(0));
3859 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3860 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3862 DAG.getValueType(Node->getOperand(0).getValueType()));
3867 case ISD::FP_ROUND_INREG:
3868 case ISD::SIGN_EXTEND_INREG: {
3869 Tmp1 = LegalizeOp(Node->getOperand(0));
3870 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3872 // If this operation is not supported, convert it to a shl/shr or load/store
3874 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3875 default: assert(0 && "This action not supported for this op yet!");
3876 case TargetLowering::Legal:
3877 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3879 case TargetLowering::Expand:
3880 // If this is an integer extend and shifts are supported, do that.
3881 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3882 // NOTE: we could fall back on load/store here too for targets without
3883 // SAR. However, it is doubtful that any exist.
3884 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3885 MVT::getSizeInBits(ExtraVT);
3886 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3887 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3888 Node->getOperand(0), ShiftCst);
3889 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3891 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3892 // The only way we can lower this is to turn it into a TRUNCSTORE,
3893 // EXTLOAD pair, targetting a temporary location (a stack slot).
3895 // NOTE: there is a choice here between constantly creating new stack
3896 // slots and always reusing the same one. We currently always create
3897 // new ones, as reuse may inhibit scheduling.
3898 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3899 Node->getValueType(0));
3901 assert(0 && "Unknown op");
3907 case ISD::TRAMPOLINE: {
3909 for (unsigned i = 0; i != 6; ++i)
3910 Ops[i] = LegalizeOp(Node->getOperand(i));
3911 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3912 // The only option for this node is to custom lower it.
3913 Result = TLI.LowerOperation(Result, DAG);
3914 assert(Result.Val && "Should always custom lower!");
3916 // Since trampoline produces two values, make sure to remember that we
3917 // legalized both of them.
3918 Tmp1 = LegalizeOp(Result.getValue(1));
3919 Result = LegalizeOp(Result);
3920 AddLegalizedOperand(SDOperand(Node, 0), Result);
3921 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3922 return Op.ResNo ? Tmp1 : Result;
3924 case ISD::FLT_ROUNDS_: {
3925 MVT::ValueType VT = Node->getValueType(0);
3926 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3927 default: assert(0 && "This action not supported for this op yet!");
3928 case TargetLowering::Custom:
3929 Result = TLI.LowerOperation(Op, DAG);
3930 if (Result.Val) break;
3932 case TargetLowering::Legal:
3933 // If this operation is not supported, lower it to constant 1
3934 Result = DAG.getConstant(1, VT);
3939 MVT::ValueType VT = Node->getValueType(0);
3940 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3941 default: assert(0 && "This action not supported for this op yet!");
3942 case TargetLowering::Legal:
3943 Tmp1 = LegalizeOp(Node->getOperand(0));
3944 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3946 case TargetLowering::Custom:
3947 Result = TLI.LowerOperation(Op, DAG);
3948 if (Result.Val) break;
3950 case TargetLowering::Expand:
3951 // If this operation is not supported, lower it to 'abort()' call
3952 Tmp1 = LegalizeOp(Node->getOperand(0));
3953 TargetLowering::ArgListTy Args;
3954 std::pair<SDOperand,SDOperand> CallResult =
3955 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
3956 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3958 Result = CallResult.second;
3965 assert(Result.getValueType() == Op.getValueType() &&
3966 "Bad legalization!");
3968 // Make sure that the generated code is itself legal.
3970 Result = LegalizeOp(Result);
3972 // Note that LegalizeOp may be reentered even from single-use nodes, which
3973 // means that we always must cache transformed nodes.
3974 AddLegalizedOperand(Op, Result);
3978 /// PromoteOp - Given an operation that produces a value in an invalid type,
3979 /// promote it to compute the value into a larger type. The produced value will
3980 /// have the correct bits for the low portion of the register, but no guarantee
3981 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3982 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3983 MVT::ValueType VT = Op.getValueType();
3984 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3985 assert(getTypeAction(VT) == Promote &&
3986 "Caller should expand or legalize operands that are not promotable!");
3987 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3988 "Cannot promote to smaller type!");
3990 SDOperand Tmp1, Tmp2, Tmp3;
3992 SDNode *Node = Op.Val;
3994 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3995 if (I != PromotedNodes.end()) return I->second;
3997 switch (Node->getOpcode()) {
3998 case ISD::CopyFromReg:
3999 assert(0 && "CopyFromReg must be legal!");
4002 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4004 assert(0 && "Do not know how to promote this operator!");
4007 Result = DAG.getNode(ISD::UNDEF, NVT);
4011 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4013 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4014 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4016 case ISD::ConstantFP:
4017 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4018 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4022 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
4023 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
4024 Node->getOperand(1), Node->getOperand(2));
4028 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4030 Result = LegalizeOp(Node->getOperand(0));
4031 assert(Result.getValueType() >= NVT &&
4032 "This truncation doesn't make sense!");
4033 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
4034 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4037 // The truncation is not required, because we don't guarantee anything
4038 // about high bits anyway.
4039 Result = PromoteOp(Node->getOperand(0));
4042 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4043 // Truncate the low part of the expanded value to the result type
4044 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4047 case ISD::SIGN_EXTEND:
4048 case ISD::ZERO_EXTEND:
4049 case ISD::ANY_EXTEND:
4050 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4051 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4053 // Input is legal? Just do extend all the way to the larger type.
4054 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4057 // Promote the reg if it's smaller.
4058 Result = PromoteOp(Node->getOperand(0));
4059 // The high bits are not guaranteed to be anything. Insert an extend.
4060 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4061 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4062 DAG.getValueType(Node->getOperand(0).getValueType()));
4063 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4064 Result = DAG.getZeroExtendInReg(Result,
4065 Node->getOperand(0).getValueType());
4069 case ISD::BIT_CONVERT:
4070 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4071 Node->getValueType(0));
4072 Result = PromoteOp(Result);
4075 case ISD::FP_EXTEND:
4076 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4078 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4079 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4080 case Promote: assert(0 && "Unreachable with 2 FP types!");
4082 if (Node->getConstantOperandVal(1) == 0) {
4083 // Input is legal? Do an FP_ROUND_INREG.
4084 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4085 DAG.getValueType(VT));
4087 // Just remove the truncate, it isn't affecting the value.
4088 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4089 Node->getOperand(1));
4094 case ISD::SINT_TO_FP:
4095 case ISD::UINT_TO_FP:
4096 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4098 // No extra round required here.
4099 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4103 Result = PromoteOp(Node->getOperand(0));
4104 if (Node->getOpcode() == ISD::SINT_TO_FP)
4105 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4107 DAG.getValueType(Node->getOperand(0).getValueType()));
4109 Result = DAG.getZeroExtendInReg(Result,
4110 Node->getOperand(0).getValueType());
4111 // No extra round required here.
4112 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4115 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4116 Node->getOperand(0));
4117 // Round if we cannot tolerate excess precision.
4118 if (NoExcessFPPrecision)
4119 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4120 DAG.getValueType(VT));
4125 case ISD::SIGN_EXTEND_INREG:
4126 Result = PromoteOp(Node->getOperand(0));
4127 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4128 Node->getOperand(1));
4130 case ISD::FP_TO_SINT:
4131 case ISD::FP_TO_UINT:
4132 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4135 Tmp1 = Node->getOperand(0);
4138 // The input result is prerounded, so we don't have to do anything
4140 Tmp1 = PromoteOp(Node->getOperand(0));
4143 // If we're promoting a UINT to a larger size, check to see if the new node
4144 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4145 // we can use that instead. This allows us to generate better code for
4146 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4147 // legal, such as PowerPC.
4148 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4149 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4150 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4151 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4152 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4154 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4160 Tmp1 = PromoteOp(Node->getOperand(0));
4161 assert(Tmp1.getValueType() == NVT);
4162 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4163 // NOTE: we do not have to do any extra rounding here for
4164 // NoExcessFPPrecision, because we know the input will have the appropriate
4165 // precision, and these operations don't modify precision at all.
4171 Tmp1 = PromoteOp(Node->getOperand(0));
4172 assert(Tmp1.getValueType() == NVT);
4173 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4174 if (NoExcessFPPrecision)
4175 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4176 DAG.getValueType(VT));
4180 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4181 // directly as well, which may be better.
4182 Tmp1 = PromoteOp(Node->getOperand(0));
4183 assert(Tmp1.getValueType() == NVT);
4184 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4185 if (NoExcessFPPrecision)
4186 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4187 DAG.getValueType(VT));
4197 // The input may have strange things in the top bits of the registers, but
4198 // these operations don't care. They may have weird bits going out, but
4199 // that too is okay if they are integer operations.
4200 Tmp1 = PromoteOp(Node->getOperand(0));
4201 Tmp2 = PromoteOp(Node->getOperand(1));
4202 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4203 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4208 Tmp1 = PromoteOp(Node->getOperand(0));
4209 Tmp2 = PromoteOp(Node->getOperand(1));
4210 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4211 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4213 // Floating point operations will give excess precision that we may not be
4214 // able to tolerate. If we DO allow excess precision, just leave it,
4215 // otherwise excise it.
4216 // FIXME: Why would we need to round FP ops more than integer ones?
4217 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4218 if (NoExcessFPPrecision)
4219 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4220 DAG.getValueType(VT));
4225 // These operators require that their input be sign extended.
4226 Tmp1 = PromoteOp(Node->getOperand(0));
4227 Tmp2 = PromoteOp(Node->getOperand(1));
4228 if (MVT::isInteger(NVT)) {
4229 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4230 DAG.getValueType(VT));
4231 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4232 DAG.getValueType(VT));
4234 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4236 // Perform FP_ROUND: this is probably overly pessimistic.
4237 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
4238 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4239 DAG.getValueType(VT));
4243 case ISD::FCOPYSIGN:
4244 // These operators require that their input be fp extended.
4245 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4246 case Expand: assert(0 && "not implemented");
4247 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4248 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4250 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4251 case Expand: assert(0 && "not implemented");
4252 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4253 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4255 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4257 // Perform FP_ROUND: this is probably overly pessimistic.
4258 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4259 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4260 DAG.getValueType(VT));
4265 // These operators require that their input be zero extended.
4266 Tmp1 = PromoteOp(Node->getOperand(0));
4267 Tmp2 = PromoteOp(Node->getOperand(1));
4268 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
4269 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4270 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4271 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4275 Tmp1 = PromoteOp(Node->getOperand(0));
4276 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4279 // The input value must be properly sign extended.
4280 Tmp1 = PromoteOp(Node->getOperand(0));
4281 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4282 DAG.getValueType(VT));
4283 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4286 // The input value must be properly zero extended.
4287 Tmp1 = PromoteOp(Node->getOperand(0));
4288 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4289 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4293 Tmp1 = Node->getOperand(0); // Get the chain.
4294 Tmp2 = Node->getOperand(1); // Get the pointer.
4295 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4296 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4297 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
4299 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4300 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4301 // Increment the pointer, VAList, to the next vaarg
4302 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4303 DAG.getConstant(MVT::getSizeInBits(VT)/8,
4304 TLI.getPointerTy()));
4305 // Store the incremented VAList to the legalized pointer
4306 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4307 // Load the actual argument out of the pointer VAList
4308 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4310 // Remember that we legalized the chain.
4311 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4315 LoadSDNode *LD = cast<LoadSDNode>(Node);
4316 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4317 ? ISD::EXTLOAD : LD->getExtensionType();
4318 Result = DAG.getExtLoad(ExtType, NVT,
4319 LD->getChain(), LD->getBasePtr(),
4320 LD->getSrcValue(), LD->getSrcValueOffset(),
4323 LD->getAlignment());
4324 // Remember that we legalized the chain.
4325 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4329 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4330 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4331 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
4333 case ISD::SELECT_CC:
4334 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4335 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4336 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4337 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4340 Tmp1 = Node->getOperand(0);
4341 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4342 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4343 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4344 DAG.getConstant(MVT::getSizeInBits(NVT) -
4345 MVT::getSizeInBits(VT),
4346 TLI.getShiftAmountTy()));
4351 // Zero extend the argument
4352 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4353 // Perform the larger operation, then subtract if needed.
4354 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4355 switch(Node->getOpcode()) {
4360 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4361 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
4362 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
4364 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4365 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
4368 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4369 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4370 DAG.getConstant(MVT::getSizeInBits(NVT) -
4371 MVT::getSizeInBits(VT), NVT));
4375 case ISD::EXTRACT_SUBVECTOR:
4376 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4378 case ISD::EXTRACT_VECTOR_ELT:
4379 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4383 assert(Result.Val && "Didn't set a result!");
4385 // Make sure the result is itself legal.
4386 Result = LegalizeOp(Result);
4388 // Remember that we promoted this!
4389 AddPromotedOperand(Op, Result);
4393 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4394 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4395 /// based on the vector type. The return type of this matches the element type
4396 /// of the vector, which may not be legal for the target.
4397 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4398 // We know that operand #0 is the Vec vector. If the index is a constant
4399 // or if the invec is a supported hardware type, we can use it. Otherwise,
4400 // lower to a store then an indexed load.
4401 SDOperand Vec = Op.getOperand(0);
4402 SDOperand Idx = Op.getOperand(1);
4404 MVT::ValueType TVT = Vec.getValueType();
4405 unsigned NumElems = MVT::getVectorNumElements(TVT);
4407 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4408 default: assert(0 && "This action is not supported yet!");
4409 case TargetLowering::Custom: {
4410 Vec = LegalizeOp(Vec);
4411 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4412 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4417 case TargetLowering::Legal:
4418 if (isTypeLegal(TVT)) {
4419 Vec = LegalizeOp(Vec);
4420 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4424 case TargetLowering::Expand:
4428 if (NumElems == 1) {
4429 // This must be an access of the only element. Return it.
4430 Op = ScalarizeVectorOp(Vec);
4431 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4432 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4433 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4435 SplitVectorOp(Vec, Lo, Hi);
4436 if (CIdx->getValue() < NumLoElts) {
4440 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4441 Idx.getValueType());
4444 // It's now an extract from the appropriate high or low part. Recurse.
4445 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4446 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4448 // Store the value to a temporary stack slot, then LOAD the scalar
4449 // element back out.
4450 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4451 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4453 // Add the offset to the index.
4454 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
4455 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4456 DAG.getConstant(EltSize, Idx.getValueType()));
4458 if (MVT::getSizeInBits(Idx.getValueType()) >
4459 MVT::getSizeInBits(TLI.getPointerTy()))
4460 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4462 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4464 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4466 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4471 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4472 /// we assume the operation can be split if it is not already legal.
4473 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4474 // We know that operand #0 is the Vec vector. For now we assume the index
4475 // is a constant and that the extracted result is a supported hardware type.
4476 SDOperand Vec = Op.getOperand(0);
4477 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4479 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
4481 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
4482 // This must be an access of the desired vector length. Return it.
4486 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4488 SplitVectorOp(Vec, Lo, Hi);
4489 if (CIdx->getValue() < NumElems/2) {
4493 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4496 // It's now an extract from the appropriate high or low part. Recurse.
4497 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4498 return ExpandEXTRACT_SUBVECTOR(Op);
4501 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4502 /// with condition CC on the current target. This usually involves legalizing
4503 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4504 /// there may be no choice but to create a new SetCC node to represent the
4505 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4506 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4507 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4510 SDOperand Tmp1, Tmp2, Tmp3, Result;
4512 switch (getTypeAction(LHS.getValueType())) {
4514 Tmp1 = LegalizeOp(LHS); // LHS
4515 Tmp2 = LegalizeOp(RHS); // RHS
4518 Tmp1 = PromoteOp(LHS); // LHS
4519 Tmp2 = PromoteOp(RHS); // RHS
4521 // If this is an FP compare, the operands have already been extended.
4522 if (MVT::isInteger(LHS.getValueType())) {
4523 MVT::ValueType VT = LHS.getValueType();
4524 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4526 // Otherwise, we have to insert explicit sign or zero extends. Note
4527 // that we could insert sign extends for ALL conditions, but zero extend
4528 // is cheaper on many machines (an AND instead of two shifts), so prefer
4530 switch (cast<CondCodeSDNode>(CC)->get()) {
4531 default: assert(0 && "Unknown integer comparison!");
4538 // ALL of these operations will work if we either sign or zero extend
4539 // the operands (including the unsigned comparisons!). Zero extend is
4540 // usually a simpler/cheaper operation, so prefer it.
4541 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4542 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4548 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4549 DAG.getValueType(VT));
4550 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4551 DAG.getValueType(VT));
4557 MVT::ValueType VT = LHS.getValueType();
4558 if (VT == MVT::f32 || VT == MVT::f64) {
4559 // Expand into one or more soft-fp libcall(s).
4560 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4561 switch (cast<CondCodeSDNode>(CC)->get()) {
4564 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4568 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4572 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4576 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4580 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4584 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4587 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4590 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4593 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4594 switch (cast<CondCodeSDNode>(CC)->get()) {
4596 // SETONE = SETOLT | SETOGT
4597 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4600 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4603 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4606 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4609 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4612 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4614 default: assert(0 && "Unsupported FP setcc!");
4619 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4620 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4621 false /*sign irrelevant*/, Dummy);
4622 Tmp2 = DAG.getConstant(0, MVT::i32);
4623 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4624 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4625 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4626 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4627 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4628 false /*sign irrelevant*/, Dummy);
4629 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4630 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4631 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4639 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4640 ExpandOp(LHS, LHSLo, LHSHi);
4641 ExpandOp(RHS, RHSLo, RHSHi);
4642 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4644 if (VT==MVT::ppcf128) {
4645 // FIXME: This generated code sucks. We want to generate
4646 // FCMP crN, hi1, hi2
4648 // FCMP crN, lo1, lo2
4649 // The following can be improved, but not that much.
4650 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4651 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
4652 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4653 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
4654 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
4655 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4656 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4665 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4666 if (RHSCST->isAllOnesValue()) {
4667 // Comparison to -1.
4668 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4673 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4674 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4675 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4676 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4679 // If this is a comparison of the sign bit, just look at the top part.
4681 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4682 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4683 CST->getValue() == 0) || // X < 0
4684 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4685 CST->isAllOnesValue())) { // X > -1
4691 // FIXME: This generated code sucks.
4692 ISD::CondCode LowCC;
4694 default: assert(0 && "Unknown integer setcc!");
4696 case ISD::SETULT: LowCC = ISD::SETULT; break;
4698 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4700 case ISD::SETULE: LowCC = ISD::SETULE; break;
4702 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4705 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4706 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4707 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4709 // NOTE: on targets without efficient SELECT of bools, we can always use
4710 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4711 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4712 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4713 false, DagCombineInfo);
4715 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4716 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4717 CCCode, false, DagCombineInfo);
4719 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC);
4721 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4722 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4723 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4724 (Tmp2C && Tmp2C->getValue() == 0 &&
4725 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4726 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4727 (Tmp2C && Tmp2C->getValue() == 1 &&
4728 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4729 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4730 // low part is known false, returns high part.
4731 // For LE / GE, if high part is known false, ignore the low part.
4732 // For LT / GT, if high part is known true, ignore the low part.
4736 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4737 ISD::SETEQ, false, DagCombineInfo);
4739 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4740 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4741 Result, Tmp1, Tmp2));
4752 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4753 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4754 /// a load from the stack slot to DestVT, extending it if needed.
4755 /// The resultant code need not be legal.
4756 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4757 MVT::ValueType SlotVT,
4758 MVT::ValueType DestVT) {
4759 // Create the stack frame object.
4760 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
4762 FrameIndexSDNode *StackPtrFI = dyn_cast<FrameIndexSDNode>(FIPtr);
4764 int SPFI = StackPtrFI->getIndex();
4766 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType());
4767 unsigned SlotSize = MVT::getSizeInBits(SlotVT);
4768 unsigned DestSize = MVT::getSizeInBits(DestVT);
4770 // Emit a store to the stack slot. Use a truncstore if the input value is
4771 // later than DestVT.
4773 if (SrcSize > SlotSize)
4774 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4775 PseudoSourceValue::getFixedStack(),
4778 assert(SrcSize == SlotSize && "Invalid store");
4779 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4780 PseudoSourceValue::getFixedStack(),
4784 // Result is a load from the stack slot.
4785 if (SlotSize == DestSize)
4786 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4788 assert(SlotSize < DestSize && "Unknown extension!");
4789 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT);
4792 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4793 // Create a vector sized/aligned stack slot, store the value to element #0,
4794 // then load the whole vector back out.
4795 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4797 FrameIndexSDNode *StackPtrFI = dyn_cast<FrameIndexSDNode>(StackPtr);
4799 int SPFI = StackPtrFI->getIndex();
4801 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4802 PseudoSourceValue::getFixedStack(), SPFI);
4803 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4804 PseudoSourceValue::getFixedStack(), SPFI);
4808 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4809 /// support the operation, but do support the resultant vector type.
4810 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4812 // If the only non-undef value is the low element, turn this into a
4813 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4814 unsigned NumElems = Node->getNumOperands();
4815 bool isOnlyLowElement = true;
4816 SDOperand SplatValue = Node->getOperand(0);
4817 std::map<SDOperand, std::vector<unsigned> > Values;
4818 Values[SplatValue].push_back(0);
4819 bool isConstant = true;
4820 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4821 SplatValue.getOpcode() != ISD::UNDEF)
4824 for (unsigned i = 1; i < NumElems; ++i) {
4825 SDOperand V = Node->getOperand(i);
4826 Values[V].push_back(i);
4827 if (V.getOpcode() != ISD::UNDEF)
4828 isOnlyLowElement = false;
4829 if (SplatValue != V)
4830 SplatValue = SDOperand(0,0);
4832 // If this isn't a constant element or an undef, we can't use a constant
4834 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4835 V.getOpcode() != ISD::UNDEF)
4839 if (isOnlyLowElement) {
4840 // If the low element is an undef too, then this whole things is an undef.
4841 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4842 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4843 // Otherwise, turn this into a scalar_to_vector node.
4844 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4845 Node->getOperand(0));
4848 // If all elements are constants, create a load from the constant pool.
4850 MVT::ValueType VT = Node->getValueType(0);
4852 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4853 std::vector<Constant*> CV;
4854 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4855 if (ConstantFPSDNode *V =
4856 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4857 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4858 } else if (ConstantSDNode *V =
4859 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4860 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4862 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4863 CV.push_back(UndefValue::get(OpNTy));
4866 Constant *CP = ConstantVector::get(CV);
4867 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4868 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4869 PseudoSourceValue::getConstantPool(), 0);
4872 if (SplatValue.Val) { // Splat of one value?
4873 // Build the shuffle constant vector: <0, 0, 0, 0>
4874 MVT::ValueType MaskVT =
4875 MVT::getIntVectorWithNumElements(NumElems);
4876 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4877 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4878 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4879 &ZeroVec[0], ZeroVec.size());
4881 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4882 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4883 // Get the splatted value into the low element of a vector register.
4884 SDOperand LowValVec =
4885 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4887 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4888 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4889 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4894 // If there are only two unique elements, we may be able to turn this into a
4896 if (Values.size() == 2) {
4897 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4898 MVT::ValueType MaskVT =
4899 MVT::getIntVectorWithNumElements(NumElems);
4900 std::vector<SDOperand> MaskVec(NumElems);
4902 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4903 E = Values.end(); I != E; ++I) {
4904 for (std::vector<unsigned>::iterator II = I->second.begin(),
4905 EE = I->second.end(); II != EE; ++II)
4906 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4909 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4910 &MaskVec[0], MaskVec.size());
4912 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4913 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4914 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4915 SmallVector<SDOperand, 8> Ops;
4916 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4917 E = Values.end(); I != E; ++I) {
4918 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4922 Ops.push_back(ShuffleMask);
4924 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4925 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4926 &Ops[0], Ops.size());
4930 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4931 // aligned object on the stack, store each element into it, then load
4932 // the result as a vector.
4933 MVT::ValueType VT = Node->getValueType(0);
4934 // Create the stack frame object.
4935 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
4937 // Emit a store of each element to the stack slot.
4938 SmallVector<SDOperand, 8> Stores;
4939 unsigned TypeByteSize =
4940 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4941 // Store (in the right endianness) the elements to memory.
4942 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4943 // Ignore undef elements.
4944 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4946 unsigned Offset = TypeByteSize*i;
4948 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4949 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4951 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4955 SDOperand StoreChain;
4956 if (!Stores.empty()) // Not all undef elements?
4957 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4958 &Stores[0], Stores.size());
4960 StoreChain = DAG.getEntryNode();
4962 // Result is a load from the stack slot.
4963 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4966 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4967 SDOperand Op, SDOperand Amt,
4968 SDOperand &Lo, SDOperand &Hi) {
4969 // Expand the subcomponents.
4970 SDOperand LHSL, LHSH;
4971 ExpandOp(Op, LHSL, LHSH);
4973 SDOperand Ops[] = { LHSL, LHSH, Amt };
4974 MVT::ValueType VT = LHSL.getValueType();
4975 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4976 Hi = Lo.getValue(1);
4980 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4981 /// smaller elements. If we can't find a way that is more efficient than a
4982 /// libcall on this target, return false. Otherwise, return true with the
4983 /// low-parts expanded into Lo and Hi.
4984 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4985 SDOperand &Lo, SDOperand &Hi) {
4986 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4987 "This is not a shift!");
4989 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4990 SDOperand ShAmt = LegalizeOp(Amt);
4991 MVT::ValueType ShTy = ShAmt.getValueType();
4992 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4993 unsigned NVTBits = MVT::getSizeInBits(NVT);
4995 // Handle the case when Amt is an immediate.
4996 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4997 unsigned Cst = CN->getValue();
4998 // Expand the incoming operand to be shifted, so that we have its parts
5000 ExpandOp(Op, InL, InH);
5004 Lo = DAG.getConstant(0, NVT);
5005 Hi = DAG.getConstant(0, NVT);
5006 } else if (Cst > NVTBits) {
5007 Lo = DAG.getConstant(0, NVT);
5008 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5009 } else if (Cst == NVTBits) {
5010 Lo = DAG.getConstant(0, NVT);
5013 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5014 Hi = DAG.getNode(ISD::OR, NVT,
5015 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5016 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5021 Lo = DAG.getConstant(0, NVT);
5022 Hi = DAG.getConstant(0, NVT);
5023 } else if (Cst > NVTBits) {
5024 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5025 Hi = DAG.getConstant(0, NVT);
5026 } else if (Cst == NVTBits) {
5028 Hi = DAG.getConstant(0, NVT);
5030 Lo = DAG.getNode(ISD::OR, NVT,
5031 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5032 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5033 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5038 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5039 DAG.getConstant(NVTBits-1, ShTy));
5040 } else if (Cst > NVTBits) {
5041 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5042 DAG.getConstant(Cst-NVTBits, ShTy));
5043 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5044 DAG.getConstant(NVTBits-1, ShTy));
5045 } else if (Cst == NVTBits) {
5047 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5048 DAG.getConstant(NVTBits-1, ShTy));
5050 Lo = DAG.getNode(ISD::OR, NVT,
5051 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5052 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5053 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5059 // Okay, the shift amount isn't constant. However, if we can tell that it is
5060 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5061 uint64_t Mask = NVTBits, KnownZero, KnownOne;
5062 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5064 // If we know that the high bit of the shift amount is one, then we can do
5065 // this as a couple of simple shifts.
5066 if (KnownOne & Mask) {
5067 // Mask out the high bit, which we know is set.
5068 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5069 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5071 // Expand the incoming operand to be shifted, so that we have its parts
5073 ExpandOp(Op, InL, InH);
5076 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5077 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5080 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5081 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5084 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5085 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5086 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5091 // If we know that the high bit of the shift amount is zero, then we can do
5092 // this as a couple of simple shifts.
5093 if (KnownZero & Mask) {
5095 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5096 DAG.getConstant(NVTBits, Amt.getValueType()),
5099 // Expand the incoming operand to be shifted, so that we have its parts
5101 ExpandOp(Op, InL, InH);
5104 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5105 Hi = DAG.getNode(ISD::OR, NVT,
5106 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5107 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5110 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5111 Lo = DAG.getNode(ISD::OR, NVT,
5112 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5113 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5116 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5117 Lo = DAG.getNode(ISD::OR, NVT,
5118 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5119 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5128 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5129 // does not fit into a register, return the lo part and set the hi part to the
5130 // by-reg argument. If it does fit into a single register, return the result
5131 // and leave the Hi part unset.
5132 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
5133 bool isSigned, SDOperand &Hi) {
5134 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5135 // The input chain to this libcall is the entry node of the function.
5136 // Legalizing the call will automatically add the previous call to the
5138 SDOperand InChain = DAG.getEntryNode();
5140 TargetLowering::ArgListTy Args;
5141 TargetLowering::ArgListEntry Entry;
5142 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5143 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
5144 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
5145 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5146 Entry.isSExt = isSigned;
5147 Args.push_back(Entry);
5149 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
5151 // Splice the libcall in wherever FindInputOutputChains tells us to.
5152 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
5153 std::pair<SDOperand,SDOperand> CallInfo =
5154 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
5157 // Legalize the call sequence, starting with the chain. This will advance
5158 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5159 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5160 LegalizeOp(CallInfo.second);
5162 switch (getTypeAction(CallInfo.first.getValueType())) {
5163 default: assert(0 && "Unknown thing");
5165 Result = CallInfo.first;
5168 ExpandOp(CallInfo.first, Result, Hi);
5175 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5177 SDOperand SelectionDAGLegalize::
5178 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
5179 assert(getTypeAction(Source.getValueType()) == Expand &&
5180 "This is not an expansion!");
5181 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
5184 assert(Source.getValueType() == MVT::i64 &&
5185 "This only works for 64-bit -> FP");
5186 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
5187 // incoming integer is set. To handle this, we dynamically test to see if
5188 // it is set, and, if so, add a fudge factor.
5190 ExpandOp(Source, Lo, Hi);
5192 // If this is unsigned, and not supported, first perform the conversion to
5193 // signed, then adjust the result if the sign bit is set.
5194 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
5195 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
5197 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
5198 DAG.getConstant(0, Hi.getValueType()),
5200 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5201 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5202 SignSet, Four, Zero);
5203 uint64_t FF = 0x5f800000ULL;
5204 if (TLI.isLittleEndian()) FF <<= 32;
5205 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5207 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5208 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5209 SDOperand FudgeInReg;
5210 if (DestTy == MVT::f32)
5211 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5212 PseudoSourceValue::getConstantPool(), 0);
5213 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
5214 // FIXME: Avoid the extend by construction the right constantpool?
5215 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5217 PseudoSourceValue::getConstantPool(), 0,
5220 assert(0 && "Unexpected conversion");
5222 MVT::ValueType SCVT = SignedConv.getValueType();
5223 if (SCVT != DestTy) {
5224 // Destination type needs to be expanded as well. The FADD now we are
5225 // constructing will be expanded into a libcall.
5226 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
5227 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
5228 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
5229 SignedConv, SignedConv.getValue(1));
5231 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5233 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5236 // Check to see if the target has a custom way to lower this. If so, use it.
5237 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
5238 default: assert(0 && "This action not implemented for this operation!");
5239 case TargetLowering::Legal:
5240 case TargetLowering::Expand:
5241 break; // This case is handled below.
5242 case TargetLowering::Custom: {
5243 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5246 return LegalizeOp(NV);
5247 break; // The target decided this was legal after all
5251 // Expand the source, then glue it back together for the call. We must expand
5252 // the source in case it is shared (this pass of legalize must traverse it).
5253 SDOperand SrcLo, SrcHi;
5254 ExpandOp(Source, SrcLo, SrcHi);
5255 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
5258 if (DestTy == MVT::f32)
5259 LC = RTLIB::SINTTOFP_I64_F32;
5261 assert(DestTy == MVT::f64 && "Unknown fp value type!");
5262 LC = RTLIB::SINTTOFP_I64_F64;
5265 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
5266 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5267 SDOperand UnusedHiPart;
5268 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
5272 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5273 /// INT_TO_FP operation of the specified operand when the target requests that
5274 /// we expand it. At this point, we know that the result and operand types are
5275 /// legal for the target.
5276 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5278 MVT::ValueType DestVT) {
5279 if (Op0.getValueType() == MVT::i32) {
5280 // simple 32-bit [signed|unsigned] integer to float/double expansion
5282 // Get the stack frame index of a 8 byte buffer.
5283 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5285 // word offset constant for Hi/Lo address computation
5286 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5287 // set up Hi and Lo (into buffer) address based on endian
5288 SDOperand Hi = StackSlot;
5289 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5290 if (TLI.isLittleEndian())
5293 // if signed map to unsigned space
5294 SDOperand Op0Mapped;
5296 // constant used to invert sign bit (signed to unsigned mapping)
5297 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5298 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5302 // store the lo of the constructed double - based on integer input
5303 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5304 Op0Mapped, Lo, NULL, 0);
5305 // initial hi portion of constructed double
5306 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5307 // store the hi of the constructed double - biased exponent
5308 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5309 // load the constructed double
5310 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5311 // FP constant to bias correct the final result
5312 SDOperand Bias = DAG.getConstantFP(isSigned ?
5313 BitsToDouble(0x4330000080000000ULL)
5314 : BitsToDouble(0x4330000000000000ULL),
5316 // subtract the bias
5317 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5320 // handle final rounding
5321 if (DestVT == MVT::f64) {
5324 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
5325 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5326 DAG.getIntPtrConstant(0));
5327 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
5328 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5332 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5333 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5335 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
5336 DAG.getConstant(0, Op0.getValueType()),
5338 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5339 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5340 SignSet, Four, Zero);
5342 // If the sign bit of the integer is set, the large number will be treated
5343 // as a negative number. To counteract this, the dynamic code adds an
5344 // offset depending on the data type.
5346 switch (Op0.getValueType()) {
5347 default: assert(0 && "Unsupported integer type!");
5348 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5349 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5350 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5351 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5353 if (TLI.isLittleEndian()) FF <<= 32;
5354 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5356 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5357 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5358 SDOperand FudgeInReg;
5359 if (DestVT == MVT::f32)
5360 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5361 PseudoSourceValue::getConstantPool(), 0);
5364 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5365 DAG.getEntryNode(), CPIdx,
5366 PseudoSourceValue::getConstantPool(), 0,
5370 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5373 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5374 /// *INT_TO_FP operation of the specified operand when the target requests that
5375 /// we promote it. At this point, we know that the result and operand types are
5376 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5377 /// operation that takes a larger input.
5378 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5379 MVT::ValueType DestVT,
5381 // First step, figure out the appropriate *INT_TO_FP operation to use.
5382 MVT::ValueType NewInTy = LegalOp.getValueType();
5384 unsigned OpToUse = 0;
5386 // Scan for the appropriate larger type to use.
5388 NewInTy = (MVT::ValueType)(NewInTy+1);
5389 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
5391 // If the target supports SINT_TO_FP of this type, use it.
5392 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5394 case TargetLowering::Legal:
5395 if (!TLI.isTypeLegal(NewInTy))
5396 break; // Can't use this datatype.
5398 case TargetLowering::Custom:
5399 OpToUse = ISD::SINT_TO_FP;
5403 if (isSigned) continue;
5405 // If the target supports UINT_TO_FP of this type, use it.
5406 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5408 case TargetLowering::Legal:
5409 if (!TLI.isTypeLegal(NewInTy))
5410 break; // Can't use this datatype.
5412 case TargetLowering::Custom:
5413 OpToUse = ISD::UINT_TO_FP;
5418 // Otherwise, try a larger type.
5421 // Okay, we found the operation and type to use. Zero extend our input to the
5422 // desired type then run the operation on it.
5423 return DAG.getNode(OpToUse, DestVT,
5424 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5428 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5429 /// FP_TO_*INT operation of the specified operand when the target requests that
5430 /// we promote it. At this point, we know that the result and operand types are
5431 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5432 /// operation that returns a larger result.
5433 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5434 MVT::ValueType DestVT,
5436 // First step, figure out the appropriate FP_TO*INT operation to use.
5437 MVT::ValueType NewOutTy = DestVT;
5439 unsigned OpToUse = 0;
5441 // Scan for the appropriate larger type to use.
5443 NewOutTy = (MVT::ValueType)(NewOutTy+1);
5444 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
5446 // If the target supports FP_TO_SINT returning this type, use it.
5447 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5449 case TargetLowering::Legal:
5450 if (!TLI.isTypeLegal(NewOutTy))
5451 break; // Can't use this datatype.
5453 case TargetLowering::Custom:
5454 OpToUse = ISD::FP_TO_SINT;
5459 // If the target supports FP_TO_UINT of this type, use it.
5460 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5462 case TargetLowering::Legal:
5463 if (!TLI.isTypeLegal(NewOutTy))
5464 break; // Can't use this datatype.
5466 case TargetLowering::Custom:
5467 OpToUse = ISD::FP_TO_UINT;
5472 // Otherwise, try a larger type.
5476 // Okay, we found the operation and type to use.
5477 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5479 // If the operation produces an invalid type, it must be custom lowered. Use
5480 // the target lowering hooks to expand it. Just keep the low part of the
5481 // expanded operation, we know that we're truncating anyway.
5482 if (getTypeAction(NewOutTy) == Expand) {
5483 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
5484 assert(Operation.Val && "Didn't return anything");
5487 // Truncate the result of the extended FP_TO_*INT operation to the desired
5489 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5492 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5494 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5495 MVT::ValueType VT = Op.getValueType();
5496 MVT::ValueType SHVT = TLI.getShiftAmountTy();
5497 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5499 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5501 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5502 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5503 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5505 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5506 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5507 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5508 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5509 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5510 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5511 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5512 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5513 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5515 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5516 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5517 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5518 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5519 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5520 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5521 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5522 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5523 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5524 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5525 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5526 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5527 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5528 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5529 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5530 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5531 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5532 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5533 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5534 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5535 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5539 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5541 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5543 default: assert(0 && "Cannot expand this yet!");
5545 static const uint64_t mask[6] = {
5546 0x5555555555555555ULL, 0x3333333333333333ULL,
5547 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5548 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5550 MVT::ValueType VT = Op.getValueType();
5551 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5552 unsigned len = MVT::getSizeInBits(VT);
5553 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5554 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5555 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5556 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5557 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5558 DAG.getNode(ISD::AND, VT,
5559 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5564 // for now, we do this:
5565 // x = x | (x >> 1);
5566 // x = x | (x >> 2);
5568 // x = x | (x >>16);
5569 // x = x | (x >>32); // for 64-bit input
5570 // return popcount(~x);
5572 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5573 MVT::ValueType VT = Op.getValueType();
5574 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5575 unsigned len = MVT::getSizeInBits(VT);
5576 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5577 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5578 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5580 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5581 return DAG.getNode(ISD::CTPOP, VT, Op);
5584 // for now, we use: { return popcount(~x & (x - 1)); }
5585 // unless the target has ctlz but not ctpop, in which case we use:
5586 // { return 32 - nlz(~x & (x-1)); }
5587 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5588 MVT::ValueType VT = Op.getValueType();
5589 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5590 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5591 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5592 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5593 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5594 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5595 TLI.isOperationLegal(ISD::CTLZ, VT))
5596 return DAG.getNode(ISD::SUB, VT,
5597 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5598 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5599 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5604 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5605 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5606 /// LegalizeNodes map is filled in for any results that are not expanded, the
5607 /// ExpandedNodes map is filled in for any results that are expanded, and the
5608 /// Lo/Hi values are returned.
5609 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5610 MVT::ValueType VT = Op.getValueType();
5611 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5612 SDNode *Node = Op.Val;
5613 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5614 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5615 MVT::isVector(VT)) &&
5616 "Cannot expand to FP value or to larger int value!");
5618 // See if we already expanded it.
5619 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5620 = ExpandedNodes.find(Op);
5621 if (I != ExpandedNodes.end()) {
5622 Lo = I->second.first;
5623 Hi = I->second.second;
5627 switch (Node->getOpcode()) {
5628 case ISD::CopyFromReg:
5629 assert(0 && "CopyFromReg must be legal!");
5630 case ISD::FP_ROUND_INREG:
5631 if (VT == MVT::ppcf128 &&
5632 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5633 TargetLowering::Custom) {
5634 SDOperand SrcLo, SrcHi, Src;
5635 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5636 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5637 SDOperand Result = TLI.LowerOperation(
5638 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5639 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5640 Lo = Result.Val->getOperand(0);
5641 Hi = Result.Val->getOperand(1);
5647 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5649 assert(0 && "Do not know how to expand this operator!");
5651 case ISD::EXTRACT_VECTOR_ELT:
5652 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5653 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5654 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5655 return ExpandOp(Lo, Lo, Hi);
5657 NVT = TLI.getTypeToExpandTo(VT);
5658 Lo = DAG.getNode(ISD::UNDEF, NVT);
5659 Hi = DAG.getNode(ISD::UNDEF, NVT);
5661 case ISD::Constant: {
5662 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
5663 Lo = DAG.getConstant(Cst, NVT);
5664 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
5667 case ISD::ConstantFP: {
5668 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5669 if (CFP->getValueType(0) == MVT::ppcf128) {
5670 APInt api = CFP->getValueAPF().convertToAPInt();
5671 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5673 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5677 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5678 if (getTypeAction(Lo.getValueType()) == Expand)
5679 ExpandOp(Lo, Lo, Hi);
5682 case ISD::BUILD_PAIR:
5683 // Return the operands.
5684 Lo = Node->getOperand(0);
5685 Hi = Node->getOperand(1);
5688 case ISD::MERGE_VALUES:
5689 if (Node->getNumValues() == 1) {
5690 ExpandOp(Op.getOperand(0), Lo, Hi);
5693 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5694 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5695 Op.getValue(1).getValueType() == MVT::Other &&
5696 "unhandled MERGE_VALUES");
5697 ExpandOp(Op.getOperand(0), Lo, Hi);
5698 // Remember that we legalized the chain.
5699 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5702 case ISD::SIGN_EXTEND_INREG:
5703 ExpandOp(Node->getOperand(0), Lo, Hi);
5704 // sext_inreg the low part if needed.
5705 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5707 // The high part gets the sign extension from the lo-part. This handles
5708 // things like sextinreg V:i64 from i8.
5709 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5710 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5711 TLI.getShiftAmountTy()));
5715 ExpandOp(Node->getOperand(0), Lo, Hi);
5716 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5717 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5723 ExpandOp(Node->getOperand(0), Lo, Hi);
5724 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5725 DAG.getNode(ISD::CTPOP, NVT, Lo),
5726 DAG.getNode(ISD::CTPOP, NVT, Hi));
5727 Hi = DAG.getConstant(0, NVT);
5731 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5732 ExpandOp(Node->getOperand(0), Lo, Hi);
5733 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5734 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5735 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5737 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5738 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5740 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5741 Hi = DAG.getConstant(0, NVT);
5746 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5747 ExpandOp(Node->getOperand(0), Lo, Hi);
5748 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5749 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5750 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5752 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5753 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5755 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5756 Hi = DAG.getConstant(0, NVT);
5761 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5762 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5763 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5764 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5766 // Remember that we legalized the chain.
5767 Hi = LegalizeOp(Hi);
5768 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5769 if (!TLI.isLittleEndian())
5775 LoadSDNode *LD = cast<LoadSDNode>(Node);
5776 SDOperand Ch = LD->getChain(); // Legalize the chain.
5777 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5778 ISD::LoadExtType ExtType = LD->getExtensionType();
5779 int SVOffset = LD->getSrcValueOffset();
5780 unsigned Alignment = LD->getAlignment();
5781 bool isVolatile = LD->isVolatile();
5783 if (ExtType == ISD::NON_EXTLOAD) {
5784 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5785 isVolatile, Alignment);
5786 if (VT == MVT::f32 || VT == MVT::f64) {
5787 // f32->i32 or f64->i64 one to one expansion.
5788 // Remember that we legalized the chain.
5789 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5790 // Recursively expand the new load.
5791 if (getTypeAction(NVT) == Expand)
5792 ExpandOp(Lo, Lo, Hi);
5796 // Increment the pointer to the other half.
5797 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5798 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5799 DAG.getIntPtrConstant(IncrementSize));
5800 SVOffset += IncrementSize;
5801 Alignment = MinAlign(Alignment, IncrementSize);
5802 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5803 isVolatile, Alignment);
5805 // Build a factor node to remember that this load is independent of the
5807 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5810 // Remember that we legalized the chain.
5811 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5812 if (!TLI.isLittleEndian())
5815 MVT::ValueType EVT = LD->getMemoryVT();
5817 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5818 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5819 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5820 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5821 SVOffset, isVolatile, Alignment);
5822 // Remember that we legalized the chain.
5823 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5824 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5829 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5830 SVOffset, isVolatile, Alignment);
5832 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5833 SVOffset, EVT, isVolatile,
5836 // Remember that we legalized the chain.
5837 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5839 if (ExtType == ISD::SEXTLOAD) {
5840 // The high part is obtained by SRA'ing all but one of the bits of the
5842 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5843 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5844 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5845 } else if (ExtType == ISD::ZEXTLOAD) {
5846 // The high part is just a zero.
5847 Hi = DAG.getConstant(0, NVT);
5848 } else /* if (ExtType == ISD::EXTLOAD) */ {
5849 // The high part is undefined.
5850 Hi = DAG.getNode(ISD::UNDEF, NVT);
5857 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5858 SDOperand LL, LH, RL, RH;
5859 ExpandOp(Node->getOperand(0), LL, LH);
5860 ExpandOp(Node->getOperand(1), RL, RH);
5861 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5862 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5866 SDOperand LL, LH, RL, RH;
5867 ExpandOp(Node->getOperand(1), LL, LH);
5868 ExpandOp(Node->getOperand(2), RL, RH);
5869 if (getTypeAction(NVT) == Expand)
5870 NVT = TLI.getTypeToExpandTo(NVT);
5871 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5873 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5876 case ISD::SELECT_CC: {
5877 SDOperand TL, TH, FL, FH;
5878 ExpandOp(Node->getOperand(2), TL, TH);
5879 ExpandOp(Node->getOperand(3), FL, FH);
5880 if (getTypeAction(NVT) == Expand)
5881 NVT = TLI.getTypeToExpandTo(NVT);
5882 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5883 Node->getOperand(1), TL, FL, Node->getOperand(4));
5885 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5886 Node->getOperand(1), TH, FH, Node->getOperand(4));
5889 case ISD::ANY_EXTEND:
5890 // The low part is any extension of the input (which degenerates to a copy).
5891 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5892 // The high part is undefined.
5893 Hi = DAG.getNode(ISD::UNDEF, NVT);
5895 case ISD::SIGN_EXTEND: {
5896 // The low part is just a sign extension of the input (which degenerates to
5898 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5900 // The high part is obtained by SRA'ing all but one of the bits of the lo
5902 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5903 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5904 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5907 case ISD::ZERO_EXTEND:
5908 // The low part is just a zero extension of the input (which degenerates to
5910 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5912 // The high part is just a zero.
5913 Hi = DAG.getConstant(0, NVT);
5916 case ISD::TRUNCATE: {
5917 // The input value must be larger than this value. Expand *it*.
5919 ExpandOp(Node->getOperand(0), NewLo, Hi);
5921 // The low part is now either the right size, or it is closer. If not the
5922 // right size, make an illegal truncate so we recursively expand it.
5923 if (NewLo.getValueType() != Node->getValueType(0))
5924 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
5925 ExpandOp(NewLo, Lo, Hi);
5929 case ISD::BIT_CONVERT: {
5931 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
5932 // If the target wants to, allow it to lower this itself.
5933 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5934 case Expand: assert(0 && "cannot expand FP!");
5935 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
5936 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
5938 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
5941 // f32 / f64 must be expanded to i32 / i64.
5942 if (VT == MVT::f32 || VT == MVT::f64) {
5943 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5944 if (getTypeAction(NVT) == Expand)
5945 ExpandOp(Lo, Lo, Hi);
5949 // If source operand will be expanded to the same type as VT, i.e.
5950 // i64 <- f64, i32 <- f32, expand the source operand instead.
5951 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
5952 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
5953 ExpandOp(Node->getOperand(0), Lo, Hi);
5957 // Turn this into a load/store pair by default.
5959 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
5961 ExpandOp(Tmp, Lo, Hi);
5965 case ISD::READCYCLECOUNTER: {
5966 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5967 TargetLowering::Custom &&
5968 "Must custom expand ReadCycleCounter");
5969 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
5970 assert(Tmp.Val && "Node must be custom expanded!");
5971 ExpandOp(Tmp.getValue(0), Lo, Hi);
5972 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5973 LegalizeOp(Tmp.getValue(1)));
5977 // These operators cannot be expanded directly, emit them as calls to
5978 // library functions.
5979 case ISD::FP_TO_SINT: {
5980 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5982 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5983 case Expand: assert(0 && "cannot expand FP!");
5984 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5985 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5988 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5990 // Now that the custom expander is done, expand the result, which is still
5993 ExpandOp(Op, Lo, Hi);
5998 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5999 if (Node->getOperand(0).getValueType() == MVT::f32)
6000 LC = RTLIB::FPTOSINT_F32_I64;
6001 else if (Node->getOperand(0).getValueType() == MVT::f64)
6002 LC = RTLIB::FPTOSINT_F64_I64;
6003 else if (Node->getOperand(0).getValueType() == MVT::f80)
6004 LC = RTLIB::FPTOSINT_F80_I64;
6005 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6006 LC = RTLIB::FPTOSINT_PPCF128_I64;
6007 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6008 false/*sign irrelevant*/, Hi);
6012 case ISD::FP_TO_UINT: {
6013 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6015 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6016 case Expand: assert(0 && "cannot expand FP!");
6017 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6018 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6021 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6023 // Now that the custom expander is done, expand the result.
6025 ExpandOp(Op, Lo, Hi);
6030 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6031 if (Node->getOperand(0).getValueType() == MVT::f32)
6032 LC = RTLIB::FPTOUINT_F32_I64;
6033 else if (Node->getOperand(0).getValueType() == MVT::f64)
6034 LC = RTLIB::FPTOUINT_F64_I64;
6035 else if (Node->getOperand(0).getValueType() == MVT::f80)
6036 LC = RTLIB::FPTOUINT_F80_I64;
6037 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6038 LC = RTLIB::FPTOUINT_PPCF128_I64;
6039 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6040 false/*sign irrelevant*/, Hi);
6045 // If the target wants custom lowering, do so.
6046 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6047 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6048 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6049 Op = TLI.LowerOperation(Op, DAG);
6051 // Now that the custom expander is done, expand the result, which is
6053 ExpandOp(Op, Lo, Hi);
6058 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6059 // this X << 1 as X+X.
6060 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6061 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6062 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6063 SDOperand LoOps[2], HiOps[3];
6064 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6065 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6066 LoOps[1] = LoOps[0];
6067 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6069 HiOps[1] = HiOps[0];
6070 HiOps[2] = Lo.getValue(1);
6071 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6076 // If we can emit an efficient shift operation, do so now.
6077 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6080 // If this target supports SHL_PARTS, use it.
6081 TargetLowering::LegalizeAction Action =
6082 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6083 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6084 Action == TargetLowering::Custom) {
6085 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6089 // Otherwise, emit a libcall.
6090 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
6091 false/*left shift=unsigned*/, Hi);
6096 // If the target wants custom lowering, do so.
6097 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6098 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6099 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6100 Op = TLI.LowerOperation(Op, DAG);
6102 // Now that the custom expander is done, expand the result, which is
6104 ExpandOp(Op, Lo, Hi);
6109 // If we can emit an efficient shift operation, do so now.
6110 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6113 // If this target supports SRA_PARTS, use it.
6114 TargetLowering::LegalizeAction Action =
6115 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6116 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6117 Action == TargetLowering::Custom) {
6118 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6122 // Otherwise, emit a libcall.
6123 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
6124 true/*ashr is signed*/, Hi);
6129 // If the target wants custom lowering, do so.
6130 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6131 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6132 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6133 Op = TLI.LowerOperation(Op, DAG);
6135 // Now that the custom expander is done, expand the result, which is
6137 ExpandOp(Op, Lo, Hi);
6142 // If we can emit an efficient shift operation, do so now.
6143 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6146 // If this target supports SRL_PARTS, use it.
6147 TargetLowering::LegalizeAction Action =
6148 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6149 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6150 Action == TargetLowering::Custom) {
6151 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6155 // Otherwise, emit a libcall.
6156 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
6157 false/*lshr is unsigned*/, Hi);
6163 // If the target wants to custom expand this, let them.
6164 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6165 TargetLowering::Custom) {
6166 Op = TLI.LowerOperation(Op, DAG);
6168 ExpandOp(Op, Lo, Hi);
6173 // Expand the subcomponents.
6174 SDOperand LHSL, LHSH, RHSL, RHSH;
6175 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6176 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6177 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6178 SDOperand LoOps[2], HiOps[3];
6183 if (Node->getOpcode() == ISD::ADD) {
6184 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6185 HiOps[2] = Lo.getValue(1);
6186 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6188 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6189 HiOps[2] = Lo.getValue(1);
6190 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6197 // Expand the subcomponents.
6198 SDOperand LHSL, LHSH, RHSL, RHSH;
6199 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6200 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6201 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6202 SDOperand LoOps[2] = { LHSL, RHSL };
6203 SDOperand HiOps[3] = { LHSH, RHSH };
6205 if (Node->getOpcode() == ISD::ADDC) {
6206 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6207 HiOps[2] = Lo.getValue(1);
6208 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6210 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6211 HiOps[2] = Lo.getValue(1);
6212 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6214 // Remember that we legalized the flag.
6215 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6220 // Expand the subcomponents.
6221 SDOperand LHSL, LHSH, RHSL, RHSH;
6222 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6223 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6224 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6225 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6226 SDOperand HiOps[3] = { LHSH, RHSH };
6228 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6229 HiOps[2] = Lo.getValue(1);
6230 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6232 // Remember that we legalized the flag.
6233 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6237 // If the target wants to custom expand this, let them.
6238 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6239 SDOperand New = TLI.LowerOperation(Op, DAG);
6241 ExpandOp(New, Lo, Hi);
6246 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6247 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6248 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6249 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6250 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6251 SDOperand LL, LH, RL, RH;
6252 ExpandOp(Node->getOperand(0), LL, LH);
6253 ExpandOp(Node->getOperand(1), RL, RH);
6254 unsigned BitSize = MVT::getSizeInBits(RH.getValueType());
6255 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6256 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6257 // FIXME: generalize this to handle other bit sizes
6258 if (LHSSB == 32 && RHSSB == 32 &&
6259 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) &&
6260 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) {
6261 // The inputs are both zero-extended.
6263 // We can emit a umul_lohi.
6264 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6265 Hi = SDOperand(Lo.Val, 1);
6269 // We can emit a mulhu+mul.
6270 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6271 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6275 if (LHSSB > BitSize && RHSSB > BitSize) {
6276 // The input values are both sign-extended.
6278 // We can emit a smul_lohi.
6279 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6280 Hi = SDOperand(Lo.Val, 1);
6284 // We can emit a mulhs+mul.
6285 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6286 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6291 // Lo,Hi = umul LHS, RHS.
6292 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6293 DAG.getVTList(NVT, NVT), LL, RL);
6295 Hi = UMulLOHI.getValue(1);
6296 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6297 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6298 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6299 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6303 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6304 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6305 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6306 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6307 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6308 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6313 // If nothing else, we can make a libcall.
6314 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
6315 false/*sign irrelevant*/, Hi);
6319 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
6322 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
6325 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
6328 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
6332 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32,
6335 RTLIB::ADD_PPCF128)),
6339 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32,
6342 RTLIB::SUB_PPCF128)),
6346 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32,
6349 RTLIB::MUL_PPCF128)),
6353 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32,
6356 RTLIB::DIV_PPCF128)),
6359 case ISD::FP_EXTEND:
6360 if (VT == MVT::ppcf128) {
6361 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6362 Node->getOperand(0).getValueType()==MVT::f64);
6363 const uint64_t zero = 0;
6364 if (Node->getOperand(0).getValueType()==MVT::f32)
6365 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6367 Hi = Node->getOperand(0);
6368 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6371 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
6374 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
6377 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32,
6380 RTLIB::POWI_PPCF128)),
6386 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6387 switch(Node->getOpcode()) {
6389 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6390 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6393 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6394 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6397 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6398 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6400 default: assert(0 && "Unreachable!");
6402 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
6406 if (VT == MVT::ppcf128) {
6408 ExpandOp(Node->getOperand(0), Lo, Tmp);
6409 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6410 // lo = hi==fabs(hi) ? lo : -lo;
6411 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6412 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6413 DAG.getCondCode(ISD::SETEQ));
6416 SDOperand Mask = (VT == MVT::f64)
6417 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6418 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6419 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6420 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6421 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6422 if (getTypeAction(NVT) == Expand)
6423 ExpandOp(Lo, Lo, Hi);
6427 if (VT == MVT::ppcf128) {
6428 ExpandOp(Node->getOperand(0), Lo, Hi);
6429 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6430 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6433 SDOperand Mask = (VT == MVT::f64)
6434 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6435 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6436 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6437 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6438 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6439 if (getTypeAction(NVT) == Expand)
6440 ExpandOp(Lo, Lo, Hi);
6443 case ISD::FCOPYSIGN: {
6444 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6445 if (getTypeAction(NVT) == Expand)
6446 ExpandOp(Lo, Lo, Hi);
6449 case ISD::SINT_TO_FP:
6450 case ISD::UINT_TO_FP: {
6451 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6452 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
6453 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) {
6454 static uint64_t zero = 0;
6456 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6457 Node->getOperand(0)));
6458 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6460 static uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6461 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6462 Node->getOperand(0)));
6463 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6464 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6465 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6466 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6467 DAG.getConstant(0, MVT::i32),
6468 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6470 APFloat(APInt(128, 2, TwoE32)),
6473 DAG.getCondCode(ISD::SETLT)),
6478 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6479 // si64->ppcf128 done by libcall, below
6480 static uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6481 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6483 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6484 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6485 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6486 DAG.getConstant(0, MVT::i64),
6487 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6489 APFloat(APInt(128, 2, TwoE64)),
6492 DAG.getCondCode(ISD::SETLT)),
6496 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6497 if (Node->getOperand(0).getValueType() == MVT::i64) {
6499 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
6500 else if (VT == MVT::f64)
6501 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
6502 else if (VT == MVT::f80) {
6504 LC = RTLIB::SINTTOFP_I64_F80;
6506 else if (VT == MVT::ppcf128) {
6508 LC = RTLIB::SINTTOFP_I64_PPCF128;
6512 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
6514 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
6517 // Promote the operand if needed.
6518 if (getTypeAction(SrcVT) == Promote) {
6519 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6521 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6522 DAG.getValueType(SrcVT))
6523 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6524 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6527 const char *LibCall = TLI.getLibcallName(LC);
6529 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
6531 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6532 Node->getOperand(0));
6533 if (getTypeAction(Lo.getValueType()) == Expand)
6534 ExpandOp(Lo, Lo, Hi);
6540 // Make sure the resultant values have been legalized themselves, unless this
6541 // is a type that requires multi-step expansion.
6542 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6543 Lo = LegalizeOp(Lo);
6545 // Don't legalize the high part if it is expanded to a single node.
6546 Hi = LegalizeOp(Hi);
6549 // Remember in a map if the values will be reused later.
6550 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6551 assert(isNew && "Value already expanded?!?");
6554 /// SplitVectorOp - Given an operand of vector type, break it down into
6555 /// two smaller values, still of vector type.
6556 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6558 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
6559 SDNode *Node = Op.Val;
6560 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
6561 assert(NumElements > 1 && "Cannot split a single element vector!");
6563 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
6565 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6566 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6568 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
6569 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
6571 // See if we already split it.
6572 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6573 = SplitNodes.find(Op);
6574 if (I != SplitNodes.end()) {
6575 Lo = I->second.first;
6576 Hi = I->second.second;
6580 switch (Node->getOpcode()) {
6585 assert(0 && "Unhandled operation in SplitVectorOp!");
6587 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6588 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6590 case ISD::BUILD_PAIR:
6591 Lo = Node->getOperand(0);
6592 Hi = Node->getOperand(1);
6594 case ISD::INSERT_VECTOR_ELT: {
6595 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6596 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
6597 SDOperand ScalarOp = Node->getOperand(1);
6598 if (Index < NewNumElts_Lo)
6599 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6600 DAG.getConstant(Index, TLI.getPointerTy()));
6602 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6603 DAG.getConstant(Index - NewNumElts_Lo,
6604 TLI.getPointerTy()));
6607 case ISD::VECTOR_SHUFFLE: {
6608 // Build the low part.
6609 SDOperand Mask = Node->getOperand(2);
6610 SmallVector<SDOperand, 8> Ops;
6611 MVT::ValueType PtrVT = TLI.getPointerTy();
6613 // Insert all of the elements from the input that are needed. We use
6614 // buildvector of extractelement here because the input vectors will have
6615 // to be legalized, so this makes the code simpler.
6616 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6617 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6618 SDOperand InVec = Node->getOperand(0);
6619 if (Idx >= NumElements) {
6620 InVec = Node->getOperand(1);
6623 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6624 DAG.getConstant(Idx, PtrVT)));
6626 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6629 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6630 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6631 SDOperand InVec = Node->getOperand(0);
6632 if (Idx >= NumElements) {
6633 InVec = Node->getOperand(1);
6636 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6637 DAG.getConstant(Idx, PtrVT)));
6639 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6642 case ISD::BUILD_VECTOR: {
6643 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6644 Node->op_begin()+NewNumElts_Lo);
6645 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6647 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6649 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6652 case ISD::CONCAT_VECTORS: {
6653 // FIXME: Handle non-power-of-two vectors?
6654 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6655 if (NewNumSubvectors == 1) {
6656 Lo = Node->getOperand(0);
6657 Hi = Node->getOperand(1);
6659 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6660 Node->op_begin()+NewNumSubvectors);
6661 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6663 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6665 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6670 SDOperand Cond = Node->getOperand(0);
6672 SDOperand LL, LH, RL, RH;
6673 SplitVectorOp(Node->getOperand(1), LL, LH);
6674 SplitVectorOp(Node->getOperand(2), RL, RH);
6676 if (MVT::isVector(Cond.getValueType())) {
6677 // Handle a vector merge.
6679 SplitVectorOp(Cond, CL, CH);
6680 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6681 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6683 // Handle a simple select with vector operands.
6684 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6685 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6705 SDOperand LL, LH, RL, RH;
6706 SplitVectorOp(Node->getOperand(0), LL, LH);
6707 SplitVectorOp(Node->getOperand(1), RL, RH);
6709 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6710 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6715 SplitVectorOp(Node->getOperand(0), L, H);
6717 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6718 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6729 case ISD::FP_TO_SINT:
6730 case ISD::FP_TO_UINT:
6731 case ISD::SINT_TO_FP:
6732 case ISD::UINT_TO_FP: {
6734 SplitVectorOp(Node->getOperand(0), L, H);
6736 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6737 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6741 LoadSDNode *LD = cast<LoadSDNode>(Node);
6742 SDOperand Ch = LD->getChain();
6743 SDOperand Ptr = LD->getBasePtr();
6744 const Value *SV = LD->getSrcValue();
6745 int SVOffset = LD->getSrcValueOffset();
6746 unsigned Alignment = LD->getAlignment();
6747 bool isVolatile = LD->isVolatile();
6749 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6750 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
6751 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6752 DAG.getIntPtrConstant(IncrementSize));
6753 SVOffset += IncrementSize;
6754 Alignment = MinAlign(Alignment, IncrementSize);
6755 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6757 // Build a factor node to remember that this load is independent of the
6759 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6762 // Remember that we legalized the chain.
6763 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6766 case ISD::BIT_CONVERT: {
6767 // We know the result is a vector. The input may be either a vector or a
6769 SDOperand InOp = Node->getOperand(0);
6770 if (!MVT::isVector(InOp.getValueType()) ||
6771 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
6772 // The input is a scalar or single-element vector.
6773 // Lower to a store/load so that it can be split.
6774 // FIXME: this could be improved probably.
6775 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6776 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr.Val);
6777 assert(FI && "Expecting CreateStackTemporary to return a frame index.\n");
6779 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6781 PseudoSourceValue::getFixedStack(),
6783 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
6784 PseudoSourceValue::getFixedStack(),
6787 // Split the vector and convert each of the pieces now.
6788 SplitVectorOp(InOp, Lo, Hi);
6789 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6790 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6795 // Remember in a map if the values will be reused later.
6797 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6798 assert(isNew && "Value already split?!?");
6802 /// ScalarizeVectorOp - Given an operand of single-element vector type
6803 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6804 /// scalar (e.g. f32) value.
6805 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6806 assert(MVT::isVector(Op.getValueType()) &&
6807 "Bad ScalarizeVectorOp invocation!");
6808 SDNode *Node = Op.Val;
6809 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
6810 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
6812 // See if we already scalarized it.
6813 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
6814 if (I != ScalarizedNodes.end()) return I->second;
6817 switch (Node->getOpcode()) {
6820 Node->dump(&DAG); cerr << "\n";
6822 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
6839 Result = DAG.getNode(Node->getOpcode(),
6841 ScalarizeVectorOp(Node->getOperand(0)),
6842 ScalarizeVectorOp(Node->getOperand(1)));
6849 Result = DAG.getNode(Node->getOpcode(),
6851 ScalarizeVectorOp(Node->getOperand(0)));
6854 Result = DAG.getNode(Node->getOpcode(),
6856 ScalarizeVectorOp(Node->getOperand(0)),
6857 Node->getOperand(1));
6860 LoadSDNode *LD = cast<LoadSDNode>(Node);
6861 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
6862 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
6864 const Value *SV = LD->getSrcValue();
6865 int SVOffset = LD->getSrcValueOffset();
6866 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
6867 LD->isVolatile(), LD->getAlignment());
6869 // Remember that we legalized the chain.
6870 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
6873 case ISD::BUILD_VECTOR:
6874 Result = Node->getOperand(0);
6876 case ISD::INSERT_VECTOR_ELT:
6877 // Returning the inserted scalar element.
6878 Result = Node->getOperand(1);
6880 case ISD::CONCAT_VECTORS:
6881 assert(Node->getOperand(0).getValueType() == NewVT &&
6882 "Concat of non-legal vectors not yet supported!");
6883 Result = Node->getOperand(0);
6885 case ISD::VECTOR_SHUFFLE: {
6886 // Figure out if the scalar is the LHS or RHS and return it.
6887 SDOperand EltNum = Node->getOperand(2).getOperand(0);
6888 if (cast<ConstantSDNode>(EltNum)->getValue())
6889 Result = ScalarizeVectorOp(Node->getOperand(1));
6891 Result = ScalarizeVectorOp(Node->getOperand(0));
6894 case ISD::EXTRACT_SUBVECTOR:
6895 Result = Node->getOperand(0);
6896 assert(Result.getValueType() == NewVT);
6898 case ISD::BIT_CONVERT:
6899 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
6902 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
6903 ScalarizeVectorOp(Op.getOperand(1)),
6904 ScalarizeVectorOp(Op.getOperand(2)));
6908 if (TLI.isTypeLegal(NewVT))
6909 Result = LegalizeOp(Result);
6910 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
6911 assert(isNew && "Value already scalarized?");
6916 // SelectionDAG::Legalize - This is the entry point for the file.
6918 void SelectionDAG::Legalize() {
6919 if (ViewLegalizeDAGs) viewGraph();
6921 /// run - This is the main entry point to this class.
6923 SelectionDAGLegalize(*this).LegalizeDAG();