1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Triple.h"
18 #include "llvm/CodeGen/Analysis.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/DebugInfo.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/IR/DerivedTypes.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/LLVMContext.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetFrameLowering.h"
33 #include "llvm/Target/TargetLowering.h"
34 #include "llvm/Target/TargetMachine.h"
37 //===----------------------------------------------------------------------===//
38 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
39 /// hacks on it until the target machine can handle it. This involves
40 /// eliminating value sizes the machine cannot handle (promoting small sizes to
41 /// large sizes or splitting up large values into small values) as well as
42 /// eliminating operations the machine cannot handle.
44 /// This code also does a small amount of optimization and recognition of idioms
45 /// as part of its processing. For example, if a target does not support a
46 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
47 /// will attempt merge setcc and brc instructions into brcc's.
50 class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
51 const TargetMachine &TM;
52 const TargetLowering &TLI;
55 /// LegalizePosition - The iterator for walking through the node list.
56 SelectionDAG::allnodes_iterator LegalizePosition;
58 /// LegalizedNodes - The set of nodes which have already been legalized.
59 SmallPtrSet<SDNode *, 16> LegalizedNodes;
61 EVT getSetCCResultType(EVT VT) const {
62 return TLI.getSetCCResultType(*DAG.getContext(), VT);
65 // Libcall insertion helpers.
68 explicit SelectionDAGLegalize(SelectionDAG &DAG);
73 /// LegalizeOp - Legalizes the given operation.
74 void LegalizeOp(SDNode *Node);
76 SDValue OptimizeFloatStore(StoreSDNode *ST);
78 void LegalizeLoadOps(SDNode *Node);
79 void LegalizeStoreOps(SDNode *Node);
81 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
82 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
83 /// is necessary to spill the vector being inserted into to memory, perform
84 /// the insert there, and then read the result back.
85 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
86 SDValue Idx, SDLoc dl);
87 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
88 SDValue Idx, SDLoc dl);
90 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
91 /// performs the same shuffe in terms of order or result bytes, but on a type
92 /// whose vector element type is narrower than the original shuffle type.
93 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
94 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
95 SDValue N1, SDValue N2,
96 ArrayRef<int> Mask) const;
98 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
99 bool &NeedInvert, SDLoc dl);
101 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
102 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
103 unsigned NumOps, bool isSigned, SDLoc dl);
105 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
106 SDNode *Node, bool isSigned);
107 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
108 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
109 RTLIB::Libcall Call_F128,
110 RTLIB::Libcall Call_PPCF128);
111 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
112 RTLIB::Libcall Call_I8,
113 RTLIB::Libcall Call_I16,
114 RTLIB::Libcall Call_I32,
115 RTLIB::Libcall Call_I64,
116 RTLIB::Libcall Call_I128);
117 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
118 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
120 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
121 SDValue ExpandBUILD_VECTOR(SDNode *Node);
122 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
123 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
124 SmallVectorImpl<SDValue> &Results);
125 SDValue ExpandFCOPYSIGN(SDNode *Node);
126 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
128 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
130 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
133 SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
134 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
136 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
137 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
138 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
140 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
142 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
144 void ExpandNode(SDNode *Node);
145 void PromoteNode(SDNode *Node);
147 void ForgetNode(SDNode *N) {
148 LegalizedNodes.erase(N);
149 if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
154 // DAGUpdateListener implementation.
155 virtual void NodeDeleted(SDNode *N, SDNode *E) {
158 virtual void NodeUpdated(SDNode *N) {}
160 // Node replacement helpers
161 void ReplacedNode(SDNode *N) {
162 if (N->use_empty()) {
163 DAG.RemoveDeadNode(N);
168 void ReplaceNode(SDNode *Old, SDNode *New) {
169 DAG.ReplaceAllUsesWith(Old, New);
172 void ReplaceNode(SDValue Old, SDValue New) {
173 DAG.ReplaceAllUsesWith(Old, New);
174 ReplacedNode(Old.getNode());
176 void ReplaceNode(SDNode *Old, const SDValue *New) {
177 DAG.ReplaceAllUsesWith(Old, New);
183 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
184 /// performs the same shuffe in terms of order or result bytes, but on a type
185 /// whose vector element type is narrower than the original shuffle type.
186 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
188 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
189 SDValue N1, SDValue N2,
190 ArrayRef<int> Mask) const {
191 unsigned NumMaskElts = VT.getVectorNumElements();
192 unsigned NumDestElts = NVT.getVectorNumElements();
193 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
195 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
197 if (NumEltsGrowth == 1)
198 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
200 SmallVector<int, 8> NewMask;
201 for (unsigned i = 0; i != NumMaskElts; ++i) {
203 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
205 NewMask.push_back(-1);
207 NewMask.push_back(Idx * NumEltsGrowth + j);
210 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
211 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
212 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
215 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
216 : SelectionDAG::DAGUpdateListener(dag),
217 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
221 void SelectionDAGLegalize::LegalizeDAG() {
222 DAG.AssignTopologicalOrder();
224 // Visit all the nodes. We start in topological order, so that we see
225 // nodes with their original operands intact. Legalization can produce
226 // new nodes which may themselves need to be legalized. Iterate until all
227 // nodes have been legalized.
229 bool AnyLegalized = false;
230 for (LegalizePosition = DAG.allnodes_end();
231 LegalizePosition != DAG.allnodes_begin(); ) {
234 SDNode *N = LegalizePosition;
235 if (LegalizedNodes.insert(N)) {
245 // Remove dead nodes now.
246 DAG.RemoveDeadNodes();
249 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
250 /// a load from the constant pool.
252 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
256 // If a FP immediate is precise when represented as a float and if the
257 // target can do an extending load from float to double, we put it into
258 // the constant pool as a float, even if it's is statically typed as a
259 // double. This shrinks FP constants and canonicalizes them for targets where
260 // an FP extending load is the same cost as a normal load (such as on the x87
261 // fp stack or PPC FP unit).
262 EVT VT = CFP->getValueType(0);
263 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
265 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
266 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
267 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
272 while (SVT != MVT::f32) {
273 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
274 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
275 // Only do this if the target has a native EXTLOAD instruction from
277 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
278 TLI.ShouldShrinkFPConstant(OrigVT)) {
279 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
280 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
286 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
287 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
290 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
292 CPIdx, MachinePointerInfo::getConstantPool(),
293 VT, false, false, Alignment);
297 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
298 MachinePointerInfo::getConstantPool(), false, false, false,
303 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
304 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
305 const TargetLowering &TLI,
306 SelectionDAGLegalize *DAGLegalize) {
307 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
308 "unaligned indexed stores not implemented!");
309 SDValue Chain = ST->getChain();
310 SDValue Ptr = ST->getBasePtr();
311 SDValue Val = ST->getValue();
312 EVT VT = Val.getValueType();
313 int Alignment = ST->getAlignment();
314 unsigned AS = ST->getAddressSpace();
317 if (ST->getMemoryVT().isFloatingPoint() ||
318 ST->getMemoryVT().isVector()) {
319 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
320 if (TLI.isTypeLegal(intVT)) {
321 // Expand to a bitconvert of the value to the integer type of the
322 // same size, then a (misaligned) int store.
323 // FIXME: Does not handle truncating floating point stores!
324 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
325 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
326 ST->isVolatile(), ST->isNonTemporal(), Alignment);
327 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
330 // Do a (aligned) store to a stack slot, then copy from the stack slot
331 // to the final destination using (unaligned) integer loads and stores.
332 EVT StoredVT = ST->getMemoryVT();
334 TLI.getRegisterType(*DAG.getContext(),
335 EVT::getIntegerVT(*DAG.getContext(),
336 StoredVT.getSizeInBits()));
337 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
338 unsigned RegBytes = RegVT.getSizeInBits() / 8;
339 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
341 // Make sure the stack slot is also aligned for the register type.
342 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
344 // Perform the original store, only redirected to the stack slot.
345 SDValue Store = DAG.getTruncStore(Chain, dl,
346 Val, StackPtr, MachinePointerInfo(),
347 StoredVT, false, false, 0);
348 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy(AS));
349 SmallVector<SDValue, 8> Stores;
352 // Do all but one copies using the full register width.
353 for (unsigned i = 1; i < NumRegs; i++) {
354 // Load one integer register's worth from the stack slot.
355 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
356 MachinePointerInfo(),
357 false, false, false, 0);
358 // Store it to the final location. Remember the store.
359 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
360 ST->getPointerInfo().getWithOffset(Offset),
361 ST->isVolatile(), ST->isNonTemporal(),
362 MinAlign(ST->getAlignment(), Offset)));
363 // Increment the pointers.
365 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
367 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
370 // The last store may be partial. Do a truncating store. On big-endian
371 // machines this requires an extending load from the stack slot to ensure
372 // that the bits are in the right place.
373 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
374 8 * (StoredBytes - Offset));
376 // Load from the stack slot.
377 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
378 MachinePointerInfo(),
379 MemVT, false, false, 0);
381 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
383 .getWithOffset(Offset),
384 MemVT, ST->isVolatile(),
386 MinAlign(ST->getAlignment(), Offset),
388 // The order of the stores doesn't matter - say it with a TokenFactor.
390 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
392 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
395 assert(ST->getMemoryVT().isInteger() &&
396 !ST->getMemoryVT().isVector() &&
397 "Unaligned store of unknown type.");
398 // Get the half-size VT
399 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
400 int NumBits = NewStoredVT.getSizeInBits();
401 int IncrementSize = NumBits / 8;
403 // Divide the stored value in two parts.
404 SDValue ShiftAmount = DAG.getConstant(NumBits,
405 TLI.getShiftAmountTy(Val.getValueType()));
407 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
409 // Store the two parts
410 SDValue Store1, Store2;
411 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
412 ST->getPointerInfo(), NewStoredVT,
413 ST->isVolatile(), ST->isNonTemporal(), Alignment);
415 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
416 DAG.getConstant(IncrementSize, TLI.getPointerTy(AS)));
417 Alignment = MinAlign(Alignment, IncrementSize);
418 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
419 ST->getPointerInfo().getWithOffset(IncrementSize),
420 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
421 Alignment, ST->getTBAAInfo());
424 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
425 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
428 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
430 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
431 const TargetLowering &TLI,
432 SDValue &ValResult, SDValue &ChainResult) {
433 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
434 "unaligned indexed loads not implemented!");
435 SDValue Chain = LD->getChain();
436 SDValue Ptr = LD->getBasePtr();
437 EVT VT = LD->getValueType(0);
438 EVT LoadedVT = LD->getMemoryVT();
440 if (VT.isFloatingPoint() || VT.isVector()) {
441 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
442 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
443 // Expand to a (misaligned) integer load of the same size,
444 // then bitconvert to floating point or vector.
445 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
446 LD->getMemOperand());
447 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
449 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
450 ISD::ANY_EXTEND, dl, VT, Result);
457 // Copy the value to a (aligned) stack slot using (unaligned) integer
458 // loads and stores, then do a (aligned) load from the stack slot.
459 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
460 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
461 unsigned RegBytes = RegVT.getSizeInBits() / 8;
462 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
464 // Make sure the stack slot is also aligned for the register type.
465 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
467 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
468 SmallVector<SDValue, 8> Stores;
469 SDValue StackPtr = StackBase;
472 // Do all but one copies using the full register width.
473 for (unsigned i = 1; i < NumRegs; i++) {
474 // Load one integer register's worth from the original location.
475 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
476 LD->getPointerInfo().getWithOffset(Offset),
477 LD->isVolatile(), LD->isNonTemporal(),
479 MinAlign(LD->getAlignment(), Offset),
481 // Follow the load with a store to the stack slot. Remember the store.
482 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
483 MachinePointerInfo(), false, false, 0));
484 // Increment the pointers.
486 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
487 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
491 // The last copy may be partial. Do an extending load.
492 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
493 8 * (LoadedBytes - Offset));
494 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
495 LD->getPointerInfo().getWithOffset(Offset),
496 MemVT, LD->isVolatile(),
498 MinAlign(LD->getAlignment(), Offset),
500 // Follow the load with a store to the stack slot. Remember the store.
501 // On big-endian machines this requires a truncating store to ensure
502 // that the bits end up in the right place.
503 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
504 MachinePointerInfo(), MemVT,
507 // The order of the stores doesn't matter - say it with a TokenFactor.
508 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
511 // Finally, perform the original load only redirected to the stack slot.
512 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
513 MachinePointerInfo(), LoadedVT, false, false, 0);
515 // Callers expect a MERGE_VALUES node.
520 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
521 "Unaligned load of unsupported type.");
523 // Compute the new VT that is half the size of the old one. This is an
525 unsigned NumBits = LoadedVT.getSizeInBits();
527 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
530 unsigned Alignment = LD->getAlignment();
531 unsigned IncrementSize = NumBits / 8;
532 ISD::LoadExtType HiExtType = LD->getExtensionType();
534 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
535 if (HiExtType == ISD::NON_EXTLOAD)
536 HiExtType = ISD::ZEXTLOAD;
538 // Load the value in two parts
540 if (TLI.isLittleEndian()) {
541 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
542 NewLoadedVT, LD->isVolatile(),
543 LD->isNonTemporal(), Alignment, LD->getTBAAInfo());
544 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
545 DAG.getConstant(IncrementSize, Ptr.getValueType()));
546 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
547 LD->getPointerInfo().getWithOffset(IncrementSize),
548 NewLoadedVT, LD->isVolatile(),
549 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize),
552 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
553 NewLoadedVT, LD->isVolatile(),
554 LD->isNonTemporal(), Alignment, LD->getTBAAInfo());
555 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
556 DAG.getConstant(IncrementSize, Ptr.getValueType()));
557 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
558 LD->getPointerInfo().getWithOffset(IncrementSize),
559 NewLoadedVT, LD->isVolatile(),
560 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize),
564 // aggregate the two parts
565 SDValue ShiftAmount = DAG.getConstant(NumBits,
566 TLI.getShiftAmountTy(Hi.getValueType()));
567 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
568 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
570 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
577 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
578 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
579 /// is necessary to spill the vector being inserted into to memory, perform
580 /// the insert there, and then read the result back.
581 SDValue SelectionDAGLegalize::
582 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
588 // If the target doesn't support this, we have to spill the input vector
589 // to a temporary stack slot, update the element, then reload it. This is
590 // badness. We could also load the value into a vector register (either
591 // with a "move to register" or "extload into register" instruction, then
592 // permute it into place, if the idx is a constant and if the idx is
593 // supported by the target.
594 EVT VT = Tmp1.getValueType();
595 EVT EltVT = VT.getVectorElementType();
596 EVT IdxVT = Tmp3.getValueType();
597 EVT PtrVT = TLI.getPointerTy();
598 SDValue StackPtr = DAG.CreateStackTemporary(VT);
600 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
603 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
604 MachinePointerInfo::getFixedStack(SPFI),
607 // Truncate or zero extend offset to target pointer type.
608 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
609 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
610 // Add the offset to the index.
611 unsigned EltSize = EltVT.getSizeInBits()/8;
612 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
613 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
614 // Store the scalar value.
615 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
617 // Load the updated vector.
618 return DAG.getLoad(VT, dl, Ch, StackPtr,
619 MachinePointerInfo::getFixedStack(SPFI), false, false,
624 SDValue SelectionDAGLegalize::
625 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
626 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
627 // SCALAR_TO_VECTOR requires that the type of the value being inserted
628 // match the element type of the vector being created, except for
629 // integers in which case the inserted value can be over width.
630 EVT EltVT = Vec.getValueType().getVectorElementType();
631 if (Val.getValueType() == EltVT ||
632 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
633 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
634 Vec.getValueType(), Val);
636 unsigned NumElts = Vec.getValueType().getVectorNumElements();
637 // We generate a shuffle of InVec and ScVec, so the shuffle mask
638 // should be 0,1,2,3,4,5... with the appropriate element replaced with
640 SmallVector<int, 8> ShufOps;
641 for (unsigned i = 0; i != NumElts; ++i)
642 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
644 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
648 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
651 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
652 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
653 // FIXME: We shouldn't do this for TargetConstantFP's.
654 // FIXME: move this to the DAG Combiner! Note that we can't regress due
655 // to phase ordering between legalized code and the dag combiner. This
656 // probably means that we need to integrate dag combiner and legalizer
658 // We generally can't do this one for long doubles.
659 SDValue Chain = ST->getChain();
660 SDValue Ptr = ST->getBasePtr();
661 unsigned Alignment = ST->getAlignment();
662 bool isVolatile = ST->isVolatile();
663 bool isNonTemporal = ST->isNonTemporal();
664 const MDNode *TBAAInfo = ST->getTBAAInfo();
666 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
667 if (CFP->getValueType(0) == MVT::f32 &&
668 TLI.isTypeLegal(MVT::i32)) {
669 SDValue Con = DAG.getConstant(CFP->getValueAPF().
670 bitcastToAPInt().zextOrTrunc(32),
672 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
673 isVolatile, isNonTemporal, Alignment, TBAAInfo);
676 if (CFP->getValueType(0) == MVT::f64) {
677 // If this target supports 64-bit registers, do a single 64-bit store.
678 if (TLI.isTypeLegal(MVT::i64)) {
679 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
680 zextOrTrunc(64), MVT::i64);
681 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
682 isVolatile, isNonTemporal, Alignment, TBAAInfo);
685 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
686 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
687 // stores. If the target supports neither 32- nor 64-bits, this
688 // xform is certainly not worth it.
689 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
690 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
691 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
692 if (TLI.isBigEndian()) std::swap(Lo, Hi);
694 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
695 isNonTemporal, Alignment, TBAAInfo);
696 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
697 DAG.getConstant(4, Ptr.getValueType()));
698 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
699 ST->getPointerInfo().getWithOffset(4),
700 isVolatile, isNonTemporal, MinAlign(Alignment, 4U),
703 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
707 return SDValue(0, 0);
710 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
711 StoreSDNode *ST = cast<StoreSDNode>(Node);
712 SDValue Chain = ST->getChain();
713 SDValue Ptr = ST->getBasePtr();
716 unsigned Alignment = ST->getAlignment();
717 bool isVolatile = ST->isVolatile();
718 bool isNonTemporal = ST->isNonTemporal();
719 const MDNode *TBAAInfo = ST->getTBAAInfo();
721 if (!ST->isTruncatingStore()) {
722 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
723 ReplaceNode(ST, OptStore);
728 SDValue Value = ST->getValue();
729 MVT VT = Value.getSimpleValueType();
730 switch (TLI.getOperationAction(ISD::STORE, VT)) {
731 default: llvm_unreachable("This action is not supported yet!");
732 case TargetLowering::Legal:
733 // If this is an unaligned store and the target doesn't support it,
735 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
736 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
737 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
738 if (ST->getAlignment() < ABIAlignment)
739 ExpandUnalignedStore(cast<StoreSDNode>(Node),
743 case TargetLowering::Custom: {
744 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
746 ReplaceNode(SDValue(Node, 0), Res);
749 case TargetLowering::Promote: {
750 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
751 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
752 "Can only promote stores to same size type");
753 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
755 DAG.getStore(Chain, dl, Value, Ptr,
756 ST->getPointerInfo(), isVolatile,
757 isNonTemporal, Alignment, TBAAInfo);
758 ReplaceNode(SDValue(Node, 0), Result);
765 SDValue Value = ST->getValue();
767 EVT StVT = ST->getMemoryVT();
768 unsigned StWidth = StVT.getSizeInBits();
770 if (StWidth != StVT.getStoreSizeInBits()) {
771 // Promote to a byte-sized store with upper bits zero if not
772 // storing an integral number of bytes. For example, promote
773 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
774 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
775 StVT.getStoreSizeInBits());
776 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
778 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
779 NVT, isVolatile, isNonTemporal, Alignment,
781 ReplaceNode(SDValue(Node, 0), Result);
782 } else if (StWidth & (StWidth - 1)) {
783 // If not storing a power-of-2 number of bits, expand as two stores.
784 assert(!StVT.isVector() && "Unsupported truncstore!");
785 unsigned RoundWidth = 1 << Log2_32(StWidth);
786 assert(RoundWidth < StWidth);
787 unsigned ExtraWidth = StWidth - RoundWidth;
788 assert(ExtraWidth < RoundWidth);
789 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
790 "Store size not an integral number of bytes!");
791 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
792 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
794 unsigned IncrementSize;
796 if (TLI.isLittleEndian()) {
797 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
798 // Store the bottom RoundWidth bits.
799 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
801 isVolatile, isNonTemporal, Alignment,
804 // Store the remaining ExtraWidth bits.
805 IncrementSize = RoundWidth / 8;
806 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
807 DAG.getConstant(IncrementSize, Ptr.getValueType()));
808 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
809 DAG.getConstant(RoundWidth,
810 TLI.getShiftAmountTy(Value.getValueType())));
811 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
812 ST->getPointerInfo().getWithOffset(IncrementSize),
813 ExtraVT, isVolatile, isNonTemporal,
814 MinAlign(Alignment, IncrementSize), TBAAInfo);
816 // Big endian - avoid unaligned stores.
817 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
818 // Store the top RoundWidth bits.
819 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
820 DAG.getConstant(ExtraWidth,
821 TLI.getShiftAmountTy(Value.getValueType())));
822 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
823 RoundVT, isVolatile, isNonTemporal, Alignment,
826 // Store the remaining ExtraWidth bits.
827 IncrementSize = RoundWidth / 8;
828 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
829 DAG.getConstant(IncrementSize, Ptr.getValueType()));
830 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
831 ST->getPointerInfo().getWithOffset(IncrementSize),
832 ExtraVT, isVolatile, isNonTemporal,
833 MinAlign(Alignment, IncrementSize), TBAAInfo);
836 // The order of the stores doesn't matter.
837 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
838 ReplaceNode(SDValue(Node, 0), Result);
840 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(),
841 StVT.getSimpleVT())) {
842 default: llvm_unreachable("This action is not supported yet!");
843 case TargetLowering::Legal:
844 // If this is an unaligned store and the target doesn't support it,
846 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
847 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
848 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
849 if (ST->getAlignment() < ABIAlignment)
850 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
853 case TargetLowering::Custom: {
854 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
856 ReplaceNode(SDValue(Node, 0), Res);
859 case TargetLowering::Expand:
860 assert(!StVT.isVector() &&
861 "Vector Stores are handled in LegalizeVectorOps");
863 // TRUNCSTORE:i16 i32 -> STORE i16
864 assert(TLI.isTypeLegal(StVT) &&
865 "Do not know how to expand this store!");
866 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
868 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
869 isVolatile, isNonTemporal, Alignment, TBAAInfo);
870 ReplaceNode(SDValue(Node, 0), Result);
877 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
878 LoadSDNode *LD = cast<LoadSDNode>(Node);
879 SDValue Chain = LD->getChain(); // The chain.
880 SDValue Ptr = LD->getBasePtr(); // The base pointer.
881 SDValue Value; // The value returned by the load op.
884 ISD::LoadExtType ExtType = LD->getExtensionType();
885 if (ExtType == ISD::NON_EXTLOAD) {
886 MVT VT = Node->getSimpleValueType(0);
887 SDValue RVal = SDValue(Node, 0);
888 SDValue RChain = SDValue(Node, 1);
890 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
891 default: llvm_unreachable("This action is not supported yet!");
892 case TargetLowering::Legal:
893 // If this is an unaligned load and the target doesn't support it,
895 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
896 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
897 unsigned ABIAlignment =
898 TLI.getDataLayout()->getABITypeAlignment(Ty);
899 if (LD->getAlignment() < ABIAlignment){
900 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
904 case TargetLowering::Custom: {
905 SDValue Res = TLI.LowerOperation(RVal, DAG);
908 RChain = Res.getValue(1);
912 case TargetLowering::Promote: {
913 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
914 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
915 "Can only promote loads to same size type");
917 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
918 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
919 RChain = Res.getValue(1);
923 if (RChain.getNode() != Node) {
924 assert(RVal.getNode() != Node && "Load must be completely replaced");
925 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
926 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
932 EVT SrcVT = LD->getMemoryVT();
933 unsigned SrcWidth = SrcVT.getSizeInBits();
934 unsigned Alignment = LD->getAlignment();
935 bool isVolatile = LD->isVolatile();
936 bool isNonTemporal = LD->isNonTemporal();
937 const MDNode *TBAAInfo = LD->getTBAAInfo();
939 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
940 // Some targets pretend to have an i1 loading operation, and actually
941 // load an i8. This trick is correct for ZEXTLOAD because the top 7
942 // bits are guaranteed to be zero; it helps the optimizers understand
943 // that these bits are zero. It is also useful for EXTLOAD, since it
944 // tells the optimizers that those bits are undefined. It would be
945 // nice to have an effective generic way of getting these benefits...
946 // Until such a way is found, don't insist on promoting i1 here.
948 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
949 // Promote to a byte-sized load if not loading an integral number of
950 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
951 unsigned NewWidth = SrcVT.getStoreSizeInBits();
952 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
955 // The extra bits are guaranteed to be zero, since we stored them that
956 // way. A zext load from NVT thus automatically gives zext from SrcVT.
958 ISD::LoadExtType NewExtType =
959 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
962 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
963 Chain, Ptr, LD->getPointerInfo(),
964 NVT, isVolatile, isNonTemporal, Alignment, TBAAInfo);
966 Ch = Result.getValue(1); // The chain.
968 if (ExtType == ISD::SEXTLOAD)
969 // Having the top bits zero doesn't help when sign extending.
970 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
971 Result.getValueType(),
972 Result, DAG.getValueType(SrcVT));
973 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
974 // All the top bits are guaranteed to be zero - inform the optimizers.
975 Result = DAG.getNode(ISD::AssertZext, dl,
976 Result.getValueType(), Result,
977 DAG.getValueType(SrcVT));
981 } else if (SrcWidth & (SrcWidth - 1)) {
982 // If not loading a power-of-2 number of bits, expand as two loads.
983 assert(!SrcVT.isVector() && "Unsupported extload!");
984 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
985 assert(RoundWidth < SrcWidth);
986 unsigned ExtraWidth = SrcWidth - RoundWidth;
987 assert(ExtraWidth < RoundWidth);
988 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
989 "Load size not an integral number of bytes!");
990 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
991 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
993 unsigned IncrementSize;
995 if (TLI.isLittleEndian()) {
996 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
997 // Load the bottom RoundWidth bits.
998 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1000 LD->getPointerInfo(), RoundVT, isVolatile,
1001 isNonTemporal, Alignment, TBAAInfo);
1003 // Load the remaining ExtraWidth bits.
1004 IncrementSize = RoundWidth / 8;
1005 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1006 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1007 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1008 LD->getPointerInfo().getWithOffset(IncrementSize),
1009 ExtraVT, isVolatile, isNonTemporal,
1010 MinAlign(Alignment, IncrementSize), TBAAInfo);
1012 // Build a factor node to remember that this load is independent of
1014 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1017 // Move the top bits to the right place.
1018 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1019 DAG.getConstant(RoundWidth,
1020 TLI.getShiftAmountTy(Hi.getValueType())));
1022 // Join the hi and lo parts.
1023 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1025 // Big endian - avoid unaligned loads.
1026 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1027 // Load the top RoundWidth bits.
1028 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1029 LD->getPointerInfo(), RoundVT, isVolatile,
1030 isNonTemporal, Alignment, TBAAInfo);
1032 // Load the remaining ExtraWidth bits.
1033 IncrementSize = RoundWidth / 8;
1034 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1035 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1036 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1037 dl, Node->getValueType(0), Chain, Ptr,
1038 LD->getPointerInfo().getWithOffset(IncrementSize),
1039 ExtraVT, isVolatile, isNonTemporal,
1040 MinAlign(Alignment, IncrementSize), TBAAInfo);
1042 // Build a factor node to remember that this load is independent of
1044 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1047 // Move the top bits to the right place.
1048 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1049 DAG.getConstant(ExtraWidth,
1050 TLI.getShiftAmountTy(Hi.getValueType())));
1052 // Join the hi and lo parts.
1053 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1058 bool isCustom = false;
1059 switch (TLI.getLoadExtAction(ExtType, SrcVT.getSimpleVT())) {
1060 default: llvm_unreachable("This action is not supported yet!");
1061 case TargetLowering::Custom:
1064 case TargetLowering::Legal: {
1065 Value = SDValue(Node, 0);
1066 Chain = SDValue(Node, 1);
1069 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1070 if (Res.getNode()) {
1072 Chain = Res.getValue(1);
1075 // If this is an unaligned load and the target doesn't support
1077 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1079 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1080 unsigned ABIAlignment =
1081 TLI.getDataLayout()->getABITypeAlignment(Ty);
1082 if (LD->getAlignment() < ABIAlignment){
1083 ExpandUnalignedLoad(cast<LoadSDNode>(Node),
1084 DAG, TLI, Value, Chain);
1090 case TargetLowering::Expand:
1091 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) &&
1092 TLI.isTypeLegal(SrcVT)) {
1093 SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr,
1094 LD->getMemOperand());
1098 ExtendOp = (SrcVT.isFloatingPoint() ?
1099 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1101 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1102 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1103 default: llvm_unreachable("Unexpected extend load type!");
1105 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1106 Chain = Load.getValue(1);
1110 assert(!SrcVT.isVector() &&
1111 "Vector Loads are handled in LegalizeVectorOps");
1113 // FIXME: This does not work for vectors on most targets. Sign-
1114 // and zero-extend operations are currently folded into extending
1115 // loads, whether they are legal or not, and then we end up here
1116 // without any support for legalizing them.
1117 assert(ExtType != ISD::EXTLOAD &&
1118 "EXTLOAD should always be supported!");
1119 // Turn the unsupported load into an EXTLOAD followed by an
1120 // explicit zero/sign extend inreg.
1121 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1122 Node->getValueType(0),
1124 LD->getMemOperand());
1126 if (ExtType == ISD::SEXTLOAD)
1127 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1128 Result.getValueType(),
1129 Result, DAG.getValueType(SrcVT));
1131 ValRes = DAG.getZeroExtendInReg(Result, dl,
1132 SrcVT.getScalarType());
1134 Chain = Result.getValue(1);
1139 // Since loads produce two values, make sure to remember that we legalized
1141 if (Chain.getNode() != Node) {
1142 assert(Value.getNode() != Node && "Load must be completely replaced");
1143 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1144 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1149 /// LegalizeOp - Return a legal replacement for the given operation, with
1150 /// all legal operands.
1151 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1152 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1155 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1156 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1157 TargetLowering::TypeLegal &&
1158 "Unexpected illegal type!");
1160 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1161 assert((TLI.getTypeAction(*DAG.getContext(),
1162 Node->getOperand(i).getValueType()) ==
1163 TargetLowering::TypeLegal ||
1164 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1165 "Unexpected illegal type!");
1167 // Figure out the correct action; the way to query this varies by opcode
1168 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1169 bool SimpleFinishLegalizing = true;
1170 switch (Node->getOpcode()) {
1171 case ISD::INTRINSIC_W_CHAIN:
1172 case ISD::INTRINSIC_WO_CHAIN:
1173 case ISD::INTRINSIC_VOID:
1174 case ISD::STACKSAVE:
1175 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1178 Action = TLI.getOperationAction(Node->getOpcode(),
1179 Node->getValueType(0));
1180 if (Action != TargetLowering::Promote)
1181 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1183 case ISD::SINT_TO_FP:
1184 case ISD::UINT_TO_FP:
1185 case ISD::EXTRACT_VECTOR_ELT:
1186 Action = TLI.getOperationAction(Node->getOpcode(),
1187 Node->getOperand(0).getValueType());
1189 case ISD::FP_ROUND_INREG:
1190 case ISD::SIGN_EXTEND_INREG: {
1191 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1192 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1195 case ISD::ATOMIC_STORE: {
1196 Action = TLI.getOperationAction(Node->getOpcode(),
1197 Node->getOperand(2).getValueType());
1200 case ISD::SELECT_CC:
1203 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1204 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1205 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1206 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1207 ISD::CondCode CCCode =
1208 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1209 Action = TLI.getCondCodeAction(CCCode, OpVT);
1210 if (Action == TargetLowering::Legal) {
1211 if (Node->getOpcode() == ISD::SELECT_CC)
1212 Action = TLI.getOperationAction(Node->getOpcode(),
1213 Node->getValueType(0));
1215 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1221 // FIXME: Model these properly. LOAD and STORE are complicated, and
1222 // STORE expects the unlegalized operand in some cases.
1223 SimpleFinishLegalizing = false;
1225 case ISD::CALLSEQ_START:
1226 case ISD::CALLSEQ_END:
1227 // FIXME: This shouldn't be necessary. These nodes have special properties
1228 // dealing with the recursive nature of legalization. Removing this
1229 // special case should be done as part of making LegalizeDAG non-recursive.
1230 SimpleFinishLegalizing = false;
1232 case ISD::EXTRACT_ELEMENT:
1233 case ISD::FLT_ROUNDS_:
1241 case ISD::MERGE_VALUES:
1242 case ISD::EH_RETURN:
1243 case ISD::FRAME_TO_ARGS_OFFSET:
1244 case ISD::EH_SJLJ_SETJMP:
1245 case ISD::EH_SJLJ_LONGJMP:
1246 // These operations lie about being legal: when they claim to be legal,
1247 // they should actually be expanded.
1248 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1249 if (Action == TargetLowering::Legal)
1250 Action = TargetLowering::Expand;
1252 case ISD::INIT_TRAMPOLINE:
1253 case ISD::ADJUST_TRAMPOLINE:
1254 case ISD::FRAMEADDR:
1255 case ISD::RETURNADDR:
1256 // These operations lie about being legal: when they claim to be legal,
1257 // they should actually be custom-lowered.
1258 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1259 if (Action == TargetLowering::Legal)
1260 Action = TargetLowering::Custom;
1262 case ISD::DEBUGTRAP:
1263 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1264 if (Action == TargetLowering::Expand) {
1265 // replace ISD::DEBUGTRAP with ISD::TRAP
1267 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1268 Node->getOperand(0));
1269 ReplaceNode(Node, NewVal.getNode());
1270 LegalizeOp(NewVal.getNode());
1276 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1277 Action = TargetLowering::Legal;
1279 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1284 if (SimpleFinishLegalizing) {
1285 SDNode *NewNode = Node;
1286 switch (Node->getOpcode()) {
1293 // Legalizing shifts/rotates requires adjusting the shift amount
1294 // to the appropriate width.
1295 if (!Node->getOperand(1).getValueType().isVector()) {
1297 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1298 Node->getOperand(1));
1299 HandleSDNode Handle(SAO);
1300 LegalizeOp(SAO.getNode());
1301 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1305 case ISD::SRL_PARTS:
1306 case ISD::SRA_PARTS:
1307 case ISD::SHL_PARTS:
1308 // Legalizing shifts/rotates requires adjusting the shift amount
1309 // to the appropriate width.
1310 if (!Node->getOperand(2).getValueType().isVector()) {
1312 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1313 Node->getOperand(2));
1314 HandleSDNode Handle(SAO);
1315 LegalizeOp(SAO.getNode());
1316 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1317 Node->getOperand(1),
1323 if (NewNode != Node) {
1324 DAG.ReplaceAllUsesWith(Node, NewNode);
1325 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1326 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
1331 case TargetLowering::Legal:
1333 case TargetLowering::Custom: {
1334 // FIXME: The handling for custom lowering with multiple results is
1336 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1337 if (Res.getNode()) {
1338 SmallVector<SDValue, 8> ResultVals;
1339 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1341 ResultVals.push_back(Res);
1343 ResultVals.push_back(Res.getValue(i));
1345 if (Res.getNode() != Node || Res.getResNo() != 0) {
1346 DAG.ReplaceAllUsesWith(Node, ResultVals.data());
1347 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1348 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
1355 case TargetLowering::Expand:
1358 case TargetLowering::Promote:
1364 switch (Node->getOpcode()) {
1371 llvm_unreachable("Do not know how to legalize this operator!");
1373 case ISD::CALLSEQ_START:
1374 case ISD::CALLSEQ_END:
1377 return LegalizeLoadOps(Node);
1380 return LegalizeStoreOps(Node);
1385 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1386 SDValue Vec = Op.getOperand(0);
1387 SDValue Idx = Op.getOperand(1);
1389 // Store the value to a temporary stack slot, then LOAD the returned part.
1390 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1391 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1392 MachinePointerInfo(), false, false, 0);
1394 // Add the offset to the index.
1396 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1397 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1398 DAG.getConstant(EltSize, Idx.getValueType()));
1400 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1401 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1403 if (Op.getValueType().isVector())
1404 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1405 false, false, false, 0);
1406 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1407 MachinePointerInfo(),
1408 Vec.getValueType().getVectorElementType(),
1412 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1413 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1415 SDValue Vec = Op.getOperand(0);
1416 SDValue Part = Op.getOperand(1);
1417 SDValue Idx = Op.getOperand(2);
1420 // Store the value to a temporary stack slot, then LOAD the returned part.
1422 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1423 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1424 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1426 // First store the whole vector.
1427 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1430 // Then store the inserted part.
1432 // Add the offset to the index.
1434 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1436 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1437 DAG.getConstant(EltSize, Idx.getValueType()));
1438 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1440 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1443 // Store the subvector.
1444 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1445 MachinePointerInfo(), false, false, 0);
1447 // Finally, load the updated vector.
1448 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1449 false, false, false, 0);
1452 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1453 // We can't handle this case efficiently. Allocate a sufficiently
1454 // aligned object on the stack, store each element into it, then load
1455 // the result as a vector.
1456 // Create the stack frame object.
1457 EVT VT = Node->getValueType(0);
1458 EVT EltVT = VT.getVectorElementType();
1460 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1461 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1462 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1464 // Emit a store of each element to the stack slot.
1465 SmallVector<SDValue, 8> Stores;
1466 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1467 // Store (in the right endianness) the elements to memory.
1468 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1469 // Ignore undef elements.
1470 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1472 unsigned Offset = TypeByteSize*i;
1474 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1475 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1477 // If the destination vector element type is narrower than the source
1478 // element type, only store the bits necessary.
1479 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1480 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1481 Node->getOperand(i), Idx,
1482 PtrInfo.getWithOffset(Offset),
1483 EltVT, false, false, 0));
1485 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1486 Node->getOperand(i), Idx,
1487 PtrInfo.getWithOffset(Offset),
1492 if (!Stores.empty()) // Not all undef elements?
1493 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1494 &Stores[0], Stores.size());
1496 StoreChain = DAG.getEntryNode();
1498 // Result is a load from the stack slot.
1499 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1500 false, false, false, 0);
1503 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1505 SDValue Tmp1 = Node->getOperand(0);
1506 SDValue Tmp2 = Node->getOperand(1);
1508 // Get the sign bit of the RHS. First obtain a value that has the same
1509 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1511 EVT FloatVT = Tmp2.getValueType();
1512 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1513 if (TLI.isTypeLegal(IVT)) {
1514 // Convert to an integer with the same sign bit.
1515 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1517 // Store the float to memory, then load the sign part out as an integer.
1518 MVT LoadTy = TLI.getPointerTy();
1519 // First create a temporary that is aligned for both the load and store.
1520 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1521 // Then store the float to it.
1523 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1525 if (TLI.isBigEndian()) {
1526 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1527 // Load out a legal integer with the same sign bit as the float.
1528 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1529 false, false, false, 0);
1530 } else { // Little endian
1531 SDValue LoadPtr = StackPtr;
1532 // The float may be wider than the integer we are going to load. Advance
1533 // the pointer so that the loaded integer will contain the sign bit.
1534 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1535 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1536 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), LoadPtr,
1537 DAG.getConstant(ByteOffset, LoadPtr.getValueType()));
1538 // Load a legal integer containing the sign bit.
1539 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1540 false, false, false, 0);
1541 // Move the sign bit to the top bit of the loaded integer.
1542 unsigned BitShift = LoadTy.getSizeInBits() -
1543 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1544 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1546 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1547 DAG.getConstant(BitShift,
1548 TLI.getShiftAmountTy(SignBit.getValueType())));
1551 // Now get the sign bit proper, by seeing whether the value is negative.
1552 SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
1553 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1555 // Get the absolute value of the result.
1556 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1557 // Select between the nabs and abs value based on the sign bit of
1559 return DAG.getSelect(dl, AbsVal.getValueType(), SignBit,
1560 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1564 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1565 SmallVectorImpl<SDValue> &Results) {
1566 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1567 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1568 " not tell us which reg is the stack pointer!");
1570 EVT VT = Node->getValueType(0);
1571 SDValue Tmp1 = SDValue(Node, 0);
1572 SDValue Tmp2 = SDValue(Node, 1);
1573 SDValue Tmp3 = Node->getOperand(2);
1574 SDValue Chain = Tmp1.getOperand(0);
1576 // Chain the dynamic stack allocation so that it doesn't modify the stack
1577 // pointer when other instructions are using the stack.
1578 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
1581 SDValue Size = Tmp2.getOperand(1);
1582 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1583 Chain = SP.getValue(1);
1584 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1585 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1586 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1587 if (Align > StackAlign)
1588 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1589 DAG.getConstant(-(uint64_t)Align, VT));
1590 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1592 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1593 DAG.getIntPtrConstant(0, true), SDValue(),
1596 Results.push_back(Tmp1);
1597 Results.push_back(Tmp2);
1600 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1601 /// condition code CC on the current target.
1603 /// If the SETCC has been legalized using AND / OR, then the legalized node
1604 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1605 /// will be set to false.
1607 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1608 /// then the values of LHS and RHS will be swapped, CC will be set to the
1609 /// new condition, and NeedInvert will be set to false.
1611 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1612 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1613 /// will be set to true. The caller must invert the result of the SETCC with
1614 /// SelectionDAG::getNOT() or take equivalent action to swap the effect of a
1615 /// true/false result.
1617 /// \returns true if the SetCC has been legalized, false if it hasn't.
1618 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1619 SDValue &LHS, SDValue &RHS,
1623 MVT OpVT = LHS.getSimpleValueType();
1624 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1626 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1627 default: llvm_unreachable("Unknown condition code action!");
1628 case TargetLowering::Legal:
1631 case TargetLowering::Expand: {
1632 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1633 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1634 std::swap(LHS, RHS);
1635 CC = DAG.getCondCode(InvCC);
1638 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1641 default: llvm_unreachable("Don't know how to expand this condition!");
1643 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1644 == TargetLowering::Legal
1645 && "If SETO is expanded, SETOEQ must be legal!");
1646 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1648 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1649 == TargetLowering::Legal
1650 && "If SETUO is expanded, SETUNE must be legal!");
1651 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1664 // If we are floating point, assign and break, otherwise fall through.
1665 if (!OpVT.isInteger()) {
1666 // We can use the 4th bit to tell if we are the unordered
1667 // or ordered version of the opcode.
1668 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1669 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1670 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1673 // Fallthrough if we are unsigned integer.
1678 // We only support using the inverted operation, which is computed above
1679 // and not a different manner of supporting expanding these cases.
1680 llvm_unreachable("Don't know how to expand this condition!");
1683 // Try inverting the result of the inverse condition.
1684 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1685 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1686 CC = DAG.getCondCode(InvCC);
1690 // If inverting the condition didn't work then we have no means to expand
1692 llvm_unreachable("Don't know how to expand this condition!");
1695 SDValue SetCC1, SetCC2;
1696 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1697 // If we aren't the ordered or unorder operation,
1698 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1699 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1700 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1702 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1703 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1704 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1706 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1715 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1716 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1717 /// a load from the stack slot to DestVT, extending it if needed.
1718 /// The resultant code need not be legal.
1719 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1723 // Create the stack frame object.
1725 TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType().
1726 getTypeForEVT(*DAG.getContext()));
1727 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1729 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1730 int SPFI = StackPtrFI->getIndex();
1731 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1733 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1734 unsigned SlotSize = SlotVT.getSizeInBits();
1735 unsigned DestSize = DestVT.getSizeInBits();
1736 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1737 unsigned DestAlign = TLI.getDataLayout()->getPrefTypeAlignment(DestType);
1739 // Emit a store to the stack slot. Use a truncstore if the input value is
1740 // later than DestVT.
1743 if (SrcSize > SlotSize)
1744 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1745 PtrInfo, SlotVT, false, false, SrcAlign);
1747 assert(SrcSize == SlotSize && "Invalid store");
1748 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1749 PtrInfo, false, false, SrcAlign);
1752 // Result is a load from the stack slot.
1753 if (SlotSize == DestSize)
1754 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1755 false, false, false, DestAlign);
1757 assert(SlotSize < DestSize && "Unknown extension!");
1758 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1759 PtrInfo, SlotVT, false, false, DestAlign);
1762 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1764 // Create a vector sized/aligned stack slot, store the value to element #0,
1765 // then load the whole vector back out.
1766 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1768 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1769 int SPFI = StackPtrFI->getIndex();
1771 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1773 MachinePointerInfo::getFixedStack(SPFI),
1774 Node->getValueType(0).getVectorElementType(),
1776 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1777 MachinePointerInfo::getFixedStack(SPFI),
1778 false, false, false, 0);
1782 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1783 /// support the operation, but do support the resultant vector type.
1784 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1785 unsigned NumElems = Node->getNumOperands();
1786 SDValue Value1, Value2;
1788 EVT VT = Node->getValueType(0);
1789 EVT OpVT = Node->getOperand(0).getValueType();
1790 EVT EltVT = VT.getVectorElementType();
1792 // If the only non-undef value is the low element, turn this into a
1793 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1794 bool isOnlyLowElement = true;
1795 bool MoreThanTwoValues = false;
1796 bool isConstant = true;
1797 for (unsigned i = 0; i < NumElems; ++i) {
1798 SDValue V = Node->getOperand(i);
1799 if (V.getOpcode() == ISD::UNDEF)
1802 isOnlyLowElement = false;
1803 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1806 if (!Value1.getNode()) {
1808 } else if (!Value2.getNode()) {
1811 } else if (V != Value1 && V != Value2) {
1812 MoreThanTwoValues = true;
1816 if (!Value1.getNode())
1817 return DAG.getUNDEF(VT);
1819 if (isOnlyLowElement)
1820 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1822 // If all elements are constants, create a load from the constant pool.
1824 SmallVector<Constant*, 16> CV;
1825 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1826 if (ConstantFPSDNode *V =
1827 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1828 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1829 } else if (ConstantSDNode *V =
1830 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1832 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1834 // If OpVT and EltVT don't match, EltVT is not legal and the
1835 // element values have been promoted/truncated earlier. Undo this;
1836 // we don't want a v16i8 to become a v16i32 for example.
1837 const ConstantInt *CI = V->getConstantIntValue();
1838 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1839 CI->getZExtValue()));
1842 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1843 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1844 CV.push_back(UndefValue::get(OpNTy));
1847 Constant *CP = ConstantVector::get(CV);
1848 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1849 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1850 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1851 MachinePointerInfo::getConstantPool(),
1852 false, false, false, Alignment);
1855 if (!MoreThanTwoValues) {
1856 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1857 for (unsigned i = 0; i < NumElems; ++i) {
1858 SDValue V = Node->getOperand(i);
1859 if (V.getOpcode() == ISD::UNDEF)
1861 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1863 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1864 // Get the splatted value into the low element of a vector register.
1865 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1867 if (Value2.getNode())
1868 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1870 Vec2 = DAG.getUNDEF(VT);
1872 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1873 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1877 // Otherwise, we can't handle this case efficiently.
1878 return ExpandVectorBuildThroughStack(Node);
1881 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1882 // does not fit into a register, return the lo part and set the hi part to the
1883 // by-reg argument. If it does fit into a single register, return the result
1884 // and leave the Hi part unset.
1885 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1887 TargetLowering::ArgListTy Args;
1888 TargetLowering::ArgListEntry Entry;
1889 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1890 EVT ArgVT = Node->getOperand(i).getValueType();
1891 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1892 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1893 Entry.isSExt = isSigned;
1894 Entry.isZExt = !isSigned;
1895 Args.push_back(Entry);
1897 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1898 TLI.getPointerTy());
1900 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1902 // By default, the input chain to this libcall is the entry node of the
1903 // function. If the libcall is going to be emitted as a tail call then
1904 // TLI.isUsedByReturnOnly will change it to the right chain if the return
1905 // node which is being folded has a non-entry input chain.
1906 SDValue InChain = DAG.getEntryNode();
1908 // isTailCall may be true since the callee does not reference caller stack
1909 // frame. Check if it's in the right position.
1910 SDValue TCChain = InChain;
1911 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
1916 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1917 0, TLI.getLibcallCallingConv(LC), isTailCall,
1918 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1919 Callee, Args, DAG, SDLoc(Node));
1920 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1923 if (!CallInfo.second.getNode())
1924 // It's a tailcall, return the chain (which is the DAG root).
1925 return DAG.getRoot();
1927 return CallInfo.first;
1930 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
1931 /// and returning a result of type RetVT.
1932 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
1933 const SDValue *Ops, unsigned NumOps,
1934 bool isSigned, SDLoc dl) {
1935 TargetLowering::ArgListTy Args;
1936 Args.reserve(NumOps);
1938 TargetLowering::ArgListEntry Entry;
1939 for (unsigned i = 0; i != NumOps; ++i) {
1940 Entry.Node = Ops[i];
1941 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
1942 Entry.isSExt = isSigned;
1943 Entry.isZExt = !isSigned;
1944 Args.push_back(Entry);
1946 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1947 TLI.getPointerTy());
1949 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
1951 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
1952 false, 0, TLI.getLibcallCallingConv(LC),
1953 /*isTailCall=*/false,
1954 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1955 Callee, Args, DAG, dl);
1956 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
1958 return CallInfo.first;
1961 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
1962 // ExpandLibCall except that the first operand is the in-chain.
1963 std::pair<SDValue, SDValue>
1964 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
1967 SDValue InChain = Node->getOperand(0);
1969 TargetLowering::ArgListTy Args;
1970 TargetLowering::ArgListEntry Entry;
1971 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
1972 EVT ArgVT = Node->getOperand(i).getValueType();
1973 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1974 Entry.Node = Node->getOperand(i);
1976 Entry.isSExt = isSigned;
1977 Entry.isZExt = !isSigned;
1978 Args.push_back(Entry);
1980 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1981 TLI.getPointerTy());
1983 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1985 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1986 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
1987 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1988 Callee, Args, DAG, SDLoc(Node));
1989 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1994 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1995 RTLIB::Libcall Call_F32,
1996 RTLIB::Libcall Call_F64,
1997 RTLIB::Libcall Call_F80,
1998 RTLIB::Libcall Call_F128,
1999 RTLIB::Libcall Call_PPCF128) {
2001 switch (Node->getSimpleValueType(0).SimpleTy) {
2002 default: llvm_unreachable("Unexpected request for libcall!");
2003 case MVT::f32: LC = Call_F32; break;
2004 case MVT::f64: LC = Call_F64; break;
2005 case MVT::f80: LC = Call_F80; break;
2006 case MVT::f128: LC = Call_F128; break;
2007 case MVT::ppcf128: LC = Call_PPCF128; break;
2009 return ExpandLibCall(LC, Node, false);
2012 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2013 RTLIB::Libcall Call_I8,
2014 RTLIB::Libcall Call_I16,
2015 RTLIB::Libcall Call_I32,
2016 RTLIB::Libcall Call_I64,
2017 RTLIB::Libcall Call_I128) {
2019 switch (Node->getSimpleValueType(0).SimpleTy) {
2020 default: llvm_unreachable("Unexpected request for libcall!");
2021 case MVT::i8: LC = Call_I8; break;
2022 case MVT::i16: LC = Call_I16; break;
2023 case MVT::i32: LC = Call_I32; break;
2024 case MVT::i64: LC = Call_I64; break;
2025 case MVT::i128: LC = Call_I128; break;
2027 return ExpandLibCall(LC, Node, isSigned);
2030 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
2031 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2032 const TargetLowering &TLI) {
2034 switch (Node->getSimpleValueType(0).SimpleTy) {
2035 default: llvm_unreachable("Unexpected request for libcall!");
2036 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2037 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2038 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2039 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2040 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2043 return TLI.getLibcallName(LC) != 0;
2046 /// useDivRem - Only issue divrem libcall if both quotient and remainder are
2048 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2049 // The other use might have been replaced with a divrem already.
2050 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2051 unsigned OtherOpcode = 0;
2053 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2055 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2057 SDValue Op0 = Node->getOperand(0);
2058 SDValue Op1 = Node->getOperand(1);
2059 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2060 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2064 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2065 User->getOperand(0) == Op0 &&
2066 User->getOperand(1) == Op1)
2072 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2075 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2076 SmallVectorImpl<SDValue> &Results) {
2077 unsigned Opcode = Node->getOpcode();
2078 bool isSigned = Opcode == ISD::SDIVREM;
2081 switch (Node->getSimpleValueType(0).SimpleTy) {
2082 default: llvm_unreachable("Unexpected request for libcall!");
2083 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2084 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2085 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2086 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2087 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2090 // The input chain to this libcall is the entry node of the function.
2091 // Legalizing the call will automatically add the previous call to the
2093 SDValue InChain = DAG.getEntryNode();
2095 EVT RetVT = Node->getValueType(0);
2096 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2098 TargetLowering::ArgListTy Args;
2099 TargetLowering::ArgListEntry Entry;
2100 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2101 EVT ArgVT = Node->getOperand(i).getValueType();
2102 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2103 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2104 Entry.isSExt = isSigned;
2105 Entry.isZExt = !isSigned;
2106 Args.push_back(Entry);
2109 // Also pass the return address of the remainder.
2110 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2112 Entry.Ty = RetTy->getPointerTo();
2113 Entry.isSExt = isSigned;
2114 Entry.isZExt = !isSigned;
2115 Args.push_back(Entry);
2117 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2118 TLI.getPointerTy());
2122 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2123 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2124 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2125 Callee, Args, DAG, dl);
2126 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2128 // Remainder is loaded back from the stack frame.
2129 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2130 MachinePointerInfo(), false, false, false, 0);
2131 Results.push_back(CallInfo.first);
2132 Results.push_back(Rem);
2135 /// isSinCosLibcallAvailable - Return true if sincos libcall is available.
2136 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2138 switch (Node->getSimpleValueType(0).SimpleTy) {
2139 default: llvm_unreachable("Unexpected request for libcall!");
2140 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2141 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2142 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2143 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2144 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2146 return TLI.getLibcallName(LC) != 0;
2149 /// canCombineSinCosLibcall - Return true if sincos libcall is available and
2150 /// can be used to combine sin and cos.
2151 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2152 const TargetMachine &TM) {
2153 if (!isSinCosLibcallAvailable(Node, TLI))
2155 // GNU sin/cos functions set errno while sincos does not. Therefore
2156 // combining sin and cos is only safe if unsafe-fpmath is enabled.
2157 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2158 if (isGNU && !TM.Options.UnsafeFPMath)
2163 /// useSinCos - Only issue sincos libcall if both sin and cos are
2165 static bool useSinCos(SDNode *Node) {
2166 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2167 ? ISD::FCOS : ISD::FSIN;
2169 SDValue Op0 = Node->getOperand(0);
2170 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2171 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2175 // The other user might have been turned into sincos already.
2176 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2182 /// ExpandSinCosLibCall - Issue libcalls to sincos to compute sin / cos
2185 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2186 SmallVectorImpl<SDValue> &Results) {
2188 switch (Node->getSimpleValueType(0).SimpleTy) {
2189 default: llvm_unreachable("Unexpected request for libcall!");
2190 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2191 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2192 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2193 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2194 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2197 // The input chain to this libcall is the entry node of the function.
2198 // Legalizing the call will automatically add the previous call to the
2200 SDValue InChain = DAG.getEntryNode();
2202 EVT RetVT = Node->getValueType(0);
2203 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2205 TargetLowering::ArgListTy Args;
2206 TargetLowering::ArgListEntry Entry;
2208 // Pass the argument.
2209 Entry.Node = Node->getOperand(0);
2211 Entry.isSExt = false;
2212 Entry.isZExt = false;
2213 Args.push_back(Entry);
2215 // Pass the return address of sin.
2216 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2217 Entry.Node = SinPtr;
2218 Entry.Ty = RetTy->getPointerTo();
2219 Entry.isSExt = false;
2220 Entry.isZExt = false;
2221 Args.push_back(Entry);
2223 // Also pass the return address of the cos.
2224 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2225 Entry.Node = CosPtr;
2226 Entry.Ty = RetTy->getPointerTo();
2227 Entry.isSExt = false;
2228 Entry.isZExt = false;
2229 Args.push_back(Entry);
2231 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2232 TLI.getPointerTy());
2236 CallLoweringInfo CLI(InChain, Type::getVoidTy(*DAG.getContext()),
2237 false, false, false, false,
2238 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2239 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2240 Callee, Args, DAG, dl);
2241 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2243 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2244 MachinePointerInfo(), false, false, false, 0));
2245 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2246 MachinePointerInfo(), false, false, false, 0));
2249 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2250 /// INT_TO_FP operation of the specified operand when the target requests that
2251 /// we expand it. At this point, we know that the result and operand types are
2252 /// legal for the target.
2253 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2257 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2258 // simple 32-bit [signed|unsigned] integer to float/double expansion
2260 // Get the stack frame index of a 8 byte buffer.
2261 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2263 // word offset constant for Hi/Lo address computation
2264 SDValue WordOff = DAG.getConstant(sizeof(int), StackSlot.getValueType());
2265 // set up Hi and Lo (into buffer) address based on endian
2266 SDValue Hi = StackSlot;
2267 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2268 StackSlot, WordOff);
2269 if (TLI.isLittleEndian())
2272 // if signed map to unsigned space
2275 // constant used to invert sign bit (signed to unsigned mapping)
2276 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2277 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2281 // store the lo of the constructed double - based on integer input
2282 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2283 Op0Mapped, Lo, MachinePointerInfo(),
2285 // initial hi portion of constructed double
2286 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2287 // store the hi of the constructed double - biased exponent
2288 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2289 MachinePointerInfo(),
2291 // load the constructed double
2292 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2293 MachinePointerInfo(), false, false, false, 0);
2294 // FP constant to bias correct the final result
2295 SDValue Bias = DAG.getConstantFP(isSigned ?
2296 BitsToDouble(0x4330000080000000ULL) :
2297 BitsToDouble(0x4330000000000000ULL),
2299 // subtract the bias
2300 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2303 // handle final rounding
2304 if (DestVT == MVT::f64) {
2307 } else if (DestVT.bitsLT(MVT::f64)) {
2308 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2309 DAG.getIntPtrConstant(0));
2310 } else if (DestVT.bitsGT(MVT::f64)) {
2311 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2315 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2316 // Code below here assumes !isSigned without checking again.
2318 // Implementation of unsigned i64 to f64 following the algorithm in
2319 // __floatundidf in compiler_rt. This implementation has the advantage
2320 // of performing rounding correctly, both in the default rounding mode
2321 // and in all alternate rounding modes.
2322 // TODO: Generalize this for use with other types.
2323 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2325 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2326 SDValue TwoP84PlusTwoP52 =
2327 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2329 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2331 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2332 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2333 DAG.getConstant(32, MVT::i64));
2334 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2335 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2336 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2337 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2338 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2340 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2343 // Implementation of unsigned i64 to f32.
2344 // TODO: Generalize this for use with other types.
2345 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2346 // For unsigned conversions, convert them to signed conversions using the
2347 // algorithm from the x86_64 __floatundidf in compiler_rt.
2349 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2351 SDValue ShiftConst =
2352 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2353 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2354 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2355 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2356 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2358 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2359 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2361 // TODO: This really should be implemented using a branch rather than a
2362 // select. We happen to get lucky and machinesink does the right
2363 // thing most of the time. This would be a good candidate for a
2364 //pseudo-op, or, even better, for whole-function isel.
2365 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2366 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2367 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2370 // Otherwise, implement the fully general conversion.
2372 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2373 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2374 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2375 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2376 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2377 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2378 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2379 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2380 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2381 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2382 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2384 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2385 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2387 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2388 DAG.getConstant(32, SHVT));
2389 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2390 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2392 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2393 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2394 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2395 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2396 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2397 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2398 DAG.getIntPtrConstant(0));
2401 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2403 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2404 Op0, DAG.getConstant(0, Op0.getValueType()),
2406 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2407 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2408 SignSet, Four, Zero);
2410 // If the sign bit of the integer is set, the large number will be treated
2411 // as a negative number. To counteract this, the dynamic code adds an
2412 // offset depending on the data type.
2414 switch (Op0.getSimpleValueType().SimpleTy) {
2415 default: llvm_unreachable("Unsupported integer type!");
2416 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2417 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2418 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2419 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2421 if (TLI.isLittleEndian()) FF <<= 32;
2422 Constant *FudgeFactor = ConstantInt::get(
2423 Type::getInt64Ty(*DAG.getContext()), FF);
2425 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2426 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2427 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2428 Alignment = std::min(Alignment, 4u);
2430 if (DestVT == MVT::f32)
2431 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2432 MachinePointerInfo::getConstantPool(),
2433 false, false, false, Alignment);
2435 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2436 DAG.getEntryNode(), CPIdx,
2437 MachinePointerInfo::getConstantPool(),
2438 MVT::f32, false, false, Alignment);
2439 HandleSDNode Handle(Load);
2440 LegalizeOp(Load.getNode());
2441 FudgeInReg = Handle.getValue();
2444 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2447 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2448 /// *INT_TO_FP operation of the specified operand when the target requests that
2449 /// we promote it. At this point, we know that the result and operand types are
2450 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2451 /// operation that takes a larger input.
2452 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2456 // First step, figure out the appropriate *INT_TO_FP operation to use.
2457 EVT NewInTy = LegalOp.getValueType();
2459 unsigned OpToUse = 0;
2461 // Scan for the appropriate larger type to use.
2463 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2464 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2466 // If the target supports SINT_TO_FP of this type, use it.
2467 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2468 OpToUse = ISD::SINT_TO_FP;
2471 if (isSigned) continue;
2473 // If the target supports UINT_TO_FP of this type, use it.
2474 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2475 OpToUse = ISD::UINT_TO_FP;
2479 // Otherwise, try a larger type.
2482 // Okay, we found the operation and type to use. Zero extend our input to the
2483 // desired type then run the operation on it.
2484 return DAG.getNode(OpToUse, dl, DestVT,
2485 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2486 dl, NewInTy, LegalOp));
2489 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2490 /// FP_TO_*INT operation of the specified operand when the target requests that
2491 /// we promote it. At this point, we know that the result and operand types are
2492 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2493 /// operation that returns a larger result.
2494 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2498 // First step, figure out the appropriate FP_TO*INT operation to use.
2499 EVT NewOutTy = DestVT;
2501 unsigned OpToUse = 0;
2503 // Scan for the appropriate larger type to use.
2505 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2506 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2508 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2509 OpToUse = ISD::FP_TO_SINT;
2513 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2514 OpToUse = ISD::FP_TO_UINT;
2518 // Otherwise, try a larger type.
2522 // Okay, we found the operation and type to use.
2523 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2525 // Truncate the result of the extended FP_TO_*INT operation to the desired
2527 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2530 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2532 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2533 EVT VT = Op.getValueType();
2534 EVT SHVT = TLI.getShiftAmountTy(VT);
2535 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2536 switch (VT.getSimpleVT().SimpleTy) {
2537 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2539 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2540 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2541 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2543 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2544 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2545 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2546 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2547 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2548 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2549 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2550 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2551 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2553 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2554 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2555 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2556 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2557 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2558 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2559 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2560 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2561 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2562 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2563 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2564 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2565 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2566 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2567 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2568 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2569 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2570 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2571 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2572 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2573 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2577 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2579 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2582 default: llvm_unreachable("Cannot expand this yet!");
2584 EVT VT = Op.getValueType();
2585 EVT ShVT = TLI.getShiftAmountTy(VT);
2586 unsigned Len = VT.getSizeInBits();
2588 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2589 "CTPOP not implemented for this type.");
2591 // This is the "best" algorithm from
2592 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2594 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), VT);
2595 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), VT);
2596 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), VT);
2597 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), VT);
2599 // v = v - ((v >> 1) & 0x55555555...)
2600 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2601 DAG.getNode(ISD::AND, dl, VT,
2602 DAG.getNode(ISD::SRL, dl, VT, Op,
2603 DAG.getConstant(1, ShVT)),
2605 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2606 Op = DAG.getNode(ISD::ADD, dl, VT,
2607 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2608 DAG.getNode(ISD::AND, dl, VT,
2609 DAG.getNode(ISD::SRL, dl, VT, Op,
2610 DAG.getConstant(2, ShVT)),
2612 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2613 Op = DAG.getNode(ISD::AND, dl, VT,
2614 DAG.getNode(ISD::ADD, dl, VT, Op,
2615 DAG.getNode(ISD::SRL, dl, VT, Op,
2616 DAG.getConstant(4, ShVT))),
2618 // v = (v * 0x01010101...) >> (Len - 8)
2619 Op = DAG.getNode(ISD::SRL, dl, VT,
2620 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2621 DAG.getConstant(Len - 8, ShVT));
2625 case ISD::CTLZ_ZERO_UNDEF:
2626 // This trivially expands to CTLZ.
2627 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2629 // for now, we do this:
2630 // x = x | (x >> 1);
2631 // x = x | (x >> 2);
2633 // x = x | (x >>16);
2634 // x = x | (x >>32); // for 64-bit input
2635 // return popcount(~x);
2637 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2638 EVT VT = Op.getValueType();
2639 EVT ShVT = TLI.getShiftAmountTy(VT);
2640 unsigned len = VT.getSizeInBits();
2641 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2642 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2643 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2644 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2646 Op = DAG.getNOT(dl, Op, VT);
2647 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2649 case ISD::CTTZ_ZERO_UNDEF:
2650 // This trivially expands to CTTZ.
2651 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2653 // for now, we use: { return popcount(~x & (x - 1)); }
2654 // unless the target has ctlz but not ctpop, in which case we use:
2655 // { return 32 - nlz(~x & (x-1)); }
2656 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2657 EVT VT = Op.getValueType();
2658 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2659 DAG.getNOT(dl, Op, VT),
2660 DAG.getNode(ISD::SUB, dl, VT, Op,
2661 DAG.getConstant(1, VT)));
2662 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2663 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2664 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2665 return DAG.getNode(ISD::SUB, dl, VT,
2666 DAG.getConstant(VT.getSizeInBits(), VT),
2667 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2668 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2673 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2674 unsigned Opc = Node->getOpcode();
2675 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2680 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2681 case ISD::ATOMIC_SWAP:
2682 switch (VT.SimpleTy) {
2683 default: llvm_unreachable("Unexpected value type for atomic!");
2684 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2685 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2686 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2687 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2688 case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;
2691 case ISD::ATOMIC_CMP_SWAP:
2692 switch (VT.SimpleTy) {
2693 default: llvm_unreachable("Unexpected value type for atomic!");
2694 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2695 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2696 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2697 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2698 case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;
2701 case ISD::ATOMIC_LOAD_ADD:
2702 switch (VT.SimpleTy) {
2703 default: llvm_unreachable("Unexpected value type for atomic!");
2704 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2705 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2706 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2707 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2708 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;
2711 case ISD::ATOMIC_LOAD_SUB:
2712 switch (VT.SimpleTy) {
2713 default: llvm_unreachable("Unexpected value type for atomic!");
2714 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2715 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2716 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2717 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2718 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;
2721 case ISD::ATOMIC_LOAD_AND:
2722 switch (VT.SimpleTy) {
2723 default: llvm_unreachable("Unexpected value type for atomic!");
2724 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2725 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2726 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2727 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2728 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;
2731 case ISD::ATOMIC_LOAD_OR:
2732 switch (VT.SimpleTy) {
2733 default: llvm_unreachable("Unexpected value type for atomic!");
2734 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2735 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2736 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2737 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2738 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;
2741 case ISD::ATOMIC_LOAD_XOR:
2742 switch (VT.SimpleTy) {
2743 default: llvm_unreachable("Unexpected value type for atomic!");
2744 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2745 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2746 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2747 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2748 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;
2751 case ISD::ATOMIC_LOAD_NAND:
2752 switch (VT.SimpleTy) {
2753 default: llvm_unreachable("Unexpected value type for atomic!");
2754 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2755 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2756 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2757 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2758 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;
2761 case ISD::ATOMIC_LOAD_MAX:
2762 switch (VT.SimpleTy) {
2763 default: llvm_unreachable("Unexpected value type for atomic!");
2764 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MAX_1; break;
2765 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MAX_2; break;
2766 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MAX_4; break;
2767 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MAX_8; break;
2768 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MAX_16;break;
2771 case ISD::ATOMIC_LOAD_UMAX:
2772 switch (VT.SimpleTy) {
2773 default: llvm_unreachable("Unexpected value type for atomic!");
2774 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMAX_1; break;
2775 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMAX_2; break;
2776 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMAX_4; break;
2777 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMAX_8; break;
2778 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMAX_16;break;
2781 case ISD::ATOMIC_LOAD_MIN:
2782 switch (VT.SimpleTy) {
2783 default: llvm_unreachable("Unexpected value type for atomic!");
2784 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MIN_1; break;
2785 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MIN_2; break;
2786 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MIN_4; break;
2787 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MIN_8; break;
2788 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MIN_16;break;
2791 case ISD::ATOMIC_LOAD_UMIN:
2792 switch (VT.SimpleTy) {
2793 default: llvm_unreachable("Unexpected value type for atomic!");
2794 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMIN_1; break;
2795 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMIN_2; break;
2796 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMIN_4; break;
2797 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMIN_8; break;
2798 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMIN_16;break;
2803 return ExpandChainLibCall(LC, Node, false);
2806 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2807 SmallVector<SDValue, 8> Results;
2809 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2811 switch (Node->getOpcode()) {
2814 case ISD::CTLZ_ZERO_UNDEF:
2816 case ISD::CTTZ_ZERO_UNDEF:
2817 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2818 Results.push_back(Tmp1);
2821 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2823 case ISD::FRAMEADDR:
2824 case ISD::RETURNADDR:
2825 case ISD::FRAME_TO_ARGS_OFFSET:
2826 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2828 case ISD::FLT_ROUNDS_:
2829 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2831 case ISD::EH_RETURN:
2835 case ISD::EH_SJLJ_LONGJMP:
2836 // If the target didn't expand these, there's nothing to do, so just
2837 // preserve the chain and be done.
2838 Results.push_back(Node->getOperand(0));
2840 case ISD::EH_SJLJ_SETJMP:
2841 // If the target didn't expand this, just return 'zero' and preserve the
2843 Results.push_back(DAG.getConstant(0, MVT::i32));
2844 Results.push_back(Node->getOperand(0));
2846 case ISD::ATOMIC_FENCE: {
2847 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2848 // FIXME: handle "fence singlethread" more efficiently.
2849 TargetLowering::ArgListTy Args;
2851 CallLoweringInfo CLI(Node->getOperand(0),
2852 Type::getVoidTy(*DAG.getContext()),
2853 false, false, false, false, 0, CallingConv::C,
2854 /*isTailCall=*/false,
2855 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2856 DAG.getExternalSymbol("__sync_synchronize",
2857 TLI.getPointerTy()),
2859 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2861 Results.push_back(CallResult.second);
2864 case ISD::ATOMIC_LOAD: {
2865 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2866 SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
2867 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
2868 cast<AtomicSDNode>(Node)->getMemoryVT(),
2869 Node->getOperand(0),
2870 Node->getOperand(1), Zero, Zero,
2871 cast<AtomicSDNode>(Node)->getMemOperand(),
2872 cast<AtomicSDNode>(Node)->getOrdering(),
2873 cast<AtomicSDNode>(Node)->getSynchScope());
2874 Results.push_back(Swap.getValue(0));
2875 Results.push_back(Swap.getValue(1));
2878 case ISD::ATOMIC_STORE: {
2879 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2880 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2881 cast<AtomicSDNode>(Node)->getMemoryVT(),
2882 Node->getOperand(0),
2883 Node->getOperand(1), Node->getOperand(2),
2884 cast<AtomicSDNode>(Node)->getMemOperand(),
2885 cast<AtomicSDNode>(Node)->getOrdering(),
2886 cast<AtomicSDNode>(Node)->getSynchScope());
2887 Results.push_back(Swap.getValue(1));
2890 // By default, atomic intrinsics are marked Legal and lowered. Targets
2891 // which don't support them directly, however, may want libcalls, in which
2892 // case they mark them Expand, and we get here.
2893 case ISD::ATOMIC_SWAP:
2894 case ISD::ATOMIC_LOAD_ADD:
2895 case ISD::ATOMIC_LOAD_SUB:
2896 case ISD::ATOMIC_LOAD_AND:
2897 case ISD::ATOMIC_LOAD_OR:
2898 case ISD::ATOMIC_LOAD_XOR:
2899 case ISD::ATOMIC_LOAD_NAND:
2900 case ISD::ATOMIC_LOAD_MIN:
2901 case ISD::ATOMIC_LOAD_MAX:
2902 case ISD::ATOMIC_LOAD_UMIN:
2903 case ISD::ATOMIC_LOAD_UMAX:
2904 case ISD::ATOMIC_CMP_SWAP: {
2905 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2906 Results.push_back(Tmp.first);
2907 Results.push_back(Tmp.second);
2910 case ISD::DYNAMIC_STACKALLOC:
2911 ExpandDYNAMIC_STACKALLOC(Node, Results);
2913 case ISD::MERGE_VALUES:
2914 for (unsigned i = 0; i < Node->getNumValues(); i++)
2915 Results.push_back(Node->getOperand(i));
2918 EVT VT = Node->getValueType(0);
2920 Results.push_back(DAG.getConstant(0, VT));
2922 assert(VT.isFloatingPoint() && "Unknown value type!");
2923 Results.push_back(DAG.getConstantFP(0, VT));
2928 // If this operation is not supported, lower it to 'abort()' call
2929 TargetLowering::ArgListTy Args;
2931 CallLoweringInfo CLI(Node->getOperand(0),
2932 Type::getVoidTy(*DAG.getContext()),
2933 false, false, false, false, 0, CallingConv::C,
2934 /*isTailCall=*/false,
2935 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2936 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2938 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2940 Results.push_back(CallResult.second);
2945 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2946 Node->getValueType(0), dl);
2947 Results.push_back(Tmp1);
2949 case ISD::FP_EXTEND:
2950 Tmp1 = EmitStackConvert(Node->getOperand(0),
2951 Node->getOperand(0).getValueType(),
2952 Node->getValueType(0), dl);
2953 Results.push_back(Tmp1);
2955 case ISD::SIGN_EXTEND_INREG: {
2956 // NOTE: we could fall back on load/store here too for targets without
2957 // SAR. However, it is doubtful that any exist.
2958 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2959 EVT VT = Node->getValueType(0);
2960 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
2963 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2964 ExtraVT.getScalarType().getSizeInBits();
2965 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2966 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2967 Node->getOperand(0), ShiftCst);
2968 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2969 Results.push_back(Tmp1);
2972 case ISD::FP_ROUND_INREG: {
2973 // The only way we can lower this is to turn it into a TRUNCSTORE,
2974 // EXTLOAD pair, targeting a temporary location (a stack slot).
2976 // NOTE: there is a choice here between constantly creating new stack
2977 // slots and always reusing the same one. We currently always create
2978 // new ones, as reuse may inhibit scheduling.
2979 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2980 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2981 Node->getValueType(0), dl);
2982 Results.push_back(Tmp1);
2985 case ISD::SINT_TO_FP:
2986 case ISD::UINT_TO_FP:
2987 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2988 Node->getOperand(0), Node->getValueType(0), dl);
2989 Results.push_back(Tmp1);
2991 case ISD::FP_TO_UINT: {
2992 SDValue True, False;
2993 EVT VT = Node->getOperand(0).getValueType();
2994 EVT NVT = Node->getValueType(0);
2995 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
2996 APInt::getNullValue(VT.getSizeInBits()));
2997 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2998 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2999 Tmp1 = DAG.getConstantFP(apf, VT);
3000 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
3001 Node->getOperand(0),
3003 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3004 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3005 DAG.getNode(ISD::FSUB, dl, VT,
3006 Node->getOperand(0), Tmp1));
3007 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3008 DAG.getConstant(x, NVT));
3009 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
3010 Results.push_back(Tmp1);
3014 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3015 EVT VT = Node->getValueType(0);
3016 Tmp1 = Node->getOperand(0);
3017 Tmp2 = Node->getOperand(1);
3018 unsigned Align = Node->getConstantOperandVal(3);
3020 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
3021 MachinePointerInfo(V),
3022 false, false, false, 0);
3023 SDValue VAList = VAListLoad;
3025 if (Align > TLI.getMinStackArgumentAlignment()) {
3026 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
3028 VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3029 DAG.getConstant(Align - 1,
3030 VAList.getValueType()));
3032 VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList,
3033 DAG.getConstant(-(int64_t)Align,
3034 VAList.getValueType()));
3037 // Increment the pointer, VAList, to the next vaarg
3038 Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3039 DAG.getConstant(TLI.getDataLayout()->
3040 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
3041 VAList.getValueType()));
3042 // Store the incremented VAList to the legalized pointer
3043 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
3044 MachinePointerInfo(V), false, false, 0);
3045 // Load the actual argument out of the pointer VAList
3046 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
3047 false, false, false, 0));
3048 Results.push_back(Results[0].getValue(1));
3052 // This defaults to loading a pointer from the input and storing it to the
3053 // output, returning the chain.
3054 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3055 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3056 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
3057 Node->getOperand(2), MachinePointerInfo(VS),
3058 false, false, false, 0);
3059 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3060 MachinePointerInfo(VD), false, false, 0);
3061 Results.push_back(Tmp1);
3064 case ISD::EXTRACT_VECTOR_ELT:
3065 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3066 // This must be an access of the only element. Return it.
3067 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3068 Node->getOperand(0));
3070 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3071 Results.push_back(Tmp1);
3073 case ISD::EXTRACT_SUBVECTOR:
3074 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3076 case ISD::INSERT_SUBVECTOR:
3077 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3079 case ISD::CONCAT_VECTORS: {
3080 Results.push_back(ExpandVectorBuildThroughStack(Node));
3083 case ISD::SCALAR_TO_VECTOR:
3084 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3086 case ISD::INSERT_VECTOR_ELT:
3087 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3088 Node->getOperand(1),
3089 Node->getOperand(2), dl));
3091 case ISD::VECTOR_SHUFFLE: {
3092 SmallVector<int, 32> NewMask;
3093 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3095 EVT VT = Node->getValueType(0);
3096 EVT EltVT = VT.getVectorElementType();
3097 SDValue Op0 = Node->getOperand(0);
3098 SDValue Op1 = Node->getOperand(1);
3099 if (!TLI.isTypeLegal(EltVT)) {
3101 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3103 // BUILD_VECTOR operands are allowed to be wider than the element type.
3104 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3106 if (NewEltVT.bitsLT(EltVT)) {
3108 // Convert shuffle node.
3109 // If original node was v4i64 and the new EltVT is i32,
3110 // cast operands to v8i32 and re-build the mask.
3112 // Calculate new VT, the size of the new VT should be equal to original.
3114 EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3115 VT.getSizeInBits() / NewEltVT.getSizeInBits());
3116 assert(NewVT.bitsEq(VT));
3118 // cast operands to new VT
3119 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3120 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3122 // Convert the shuffle mask
3123 unsigned int factor =
3124 NewVT.getVectorNumElements()/VT.getVectorNumElements();
3126 // EltVT gets smaller
3129 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3131 for (unsigned fi = 0; fi < factor; ++fi)
3132 NewMask.push_back(Mask[i]);
3135 for (unsigned fi = 0; fi < factor; ++fi)
3136 NewMask.push_back(Mask[i]*factor+fi);
3144 unsigned NumElems = VT.getVectorNumElements();
3145 SmallVector<SDValue, 16> Ops;
3146 for (unsigned i = 0; i != NumElems; ++i) {
3148 Ops.push_back(DAG.getUNDEF(EltVT));
3151 unsigned Idx = Mask[i];
3153 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3155 DAG.getConstant(Idx, TLI.getVectorIdxTy())));
3157 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3159 DAG.getConstant(Idx - NumElems,
3160 TLI.getVectorIdxTy())));
3163 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
3164 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3165 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3166 Results.push_back(Tmp1);
3169 case ISD::EXTRACT_ELEMENT: {
3170 EVT OpTy = Node->getOperand(0).getValueType();
3171 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3173 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3174 DAG.getConstant(OpTy.getSizeInBits()/2,
3175 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3176 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3179 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3180 Node->getOperand(0));
3182 Results.push_back(Tmp1);
3185 case ISD::STACKSAVE:
3186 // Expand to CopyFromReg if the target set
3187 // StackPointerRegisterToSaveRestore.
3188 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3189 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3190 Node->getValueType(0)));
3191 Results.push_back(Results[0].getValue(1));
3193 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3194 Results.push_back(Node->getOperand(0));
3197 case ISD::STACKRESTORE:
3198 // Expand to CopyToReg if the target set
3199 // StackPointerRegisterToSaveRestore.
3200 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3201 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3202 Node->getOperand(1)));
3204 Results.push_back(Node->getOperand(0));
3207 case ISD::FCOPYSIGN:
3208 Results.push_back(ExpandFCOPYSIGN(Node));
3211 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3212 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3213 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3214 Node->getOperand(0));
3215 Results.push_back(Tmp1);
3218 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3219 EVT VT = Node->getValueType(0);
3220 Tmp1 = Node->getOperand(0);
3221 Tmp2 = DAG.getConstantFP(0.0, VT);
3222 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
3223 Tmp1, Tmp2, ISD::SETUGT);
3224 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3225 Tmp1 = DAG.getSelect(dl, VT, Tmp2, Tmp1, Tmp3);
3226 Results.push_back(Tmp1);
3230 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3231 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3232 RTLIB::SQRT_PPCF128));
3236 EVT VT = Node->getValueType(0);
3237 bool isSIN = Node->getOpcode() == ISD::FSIN;
3238 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3239 // fcos which share the same operand and both are used.
3240 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3241 canCombineSinCosLibcall(Node, TLI, TM))
3242 && useSinCos(Node)) {
3243 SDVTList VTs = DAG.getVTList(VT, VT);
3244 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3246 Tmp1 = Tmp1.getValue(1);
3247 Results.push_back(Tmp1);
3249 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3250 RTLIB::SIN_F80, RTLIB::SIN_F128,
3251 RTLIB::SIN_PPCF128));
3253 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3254 RTLIB::COS_F80, RTLIB::COS_F128,
3255 RTLIB::COS_PPCF128));
3260 // Expand into sincos libcall.
3261 ExpandSinCosLibCall(Node, Results);
3264 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3265 RTLIB::LOG_F80, RTLIB::LOG_F128,
3266 RTLIB::LOG_PPCF128));
3269 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3270 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3271 RTLIB::LOG2_PPCF128));
3274 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3275 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3276 RTLIB::LOG10_PPCF128));
3279 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3280 RTLIB::EXP_F80, RTLIB::EXP_F128,
3281 RTLIB::EXP_PPCF128));
3284 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3285 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3286 RTLIB::EXP2_PPCF128));
3289 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3290 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3291 RTLIB::TRUNC_PPCF128));
3294 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3295 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3296 RTLIB::FLOOR_PPCF128));
3299 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3300 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3301 RTLIB::CEIL_PPCF128));
3304 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3305 RTLIB::RINT_F80, RTLIB::RINT_F128,
3306 RTLIB::RINT_PPCF128));
3308 case ISD::FNEARBYINT:
3309 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3310 RTLIB::NEARBYINT_F64,
3311 RTLIB::NEARBYINT_F80,
3312 RTLIB::NEARBYINT_F128,
3313 RTLIB::NEARBYINT_PPCF128));
3316 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3320 RTLIB::ROUND_PPCF128));
3323 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3324 RTLIB::POWI_F80, RTLIB::POWI_F128,
3325 RTLIB::POWI_PPCF128));
3328 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3329 RTLIB::POW_F80, RTLIB::POW_F128,
3330 RTLIB::POW_PPCF128));
3333 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3334 RTLIB::DIV_F80, RTLIB::DIV_F128,
3335 RTLIB::DIV_PPCF128));
3338 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3339 RTLIB::REM_F80, RTLIB::REM_F128,
3340 RTLIB::REM_PPCF128));
3343 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3344 RTLIB::FMA_F80, RTLIB::FMA_F128,
3345 RTLIB::FMA_PPCF128));
3347 case ISD::FP16_TO_FP32:
3348 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3350 case ISD::FP32_TO_FP16:
3351 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3353 case ISD::ConstantFP: {
3354 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3355 // Check to see if this FP immediate is already legal.
3356 // If this is a legal constant, turn it into a TargetConstantFP node.
3357 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3358 Results.push_back(ExpandConstantFP(CFP, true));
3362 EVT VT = Node->getValueType(0);
3363 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3364 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3365 "Don't know how to expand this FP subtraction!");
3366 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3367 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3368 Results.push_back(Tmp1);
3372 EVT VT = Node->getValueType(0);
3373 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3374 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3375 "Don't know how to expand this subtraction!");
3376 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3377 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3378 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3379 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3384 EVT VT = Node->getValueType(0);
3385 bool isSigned = Node->getOpcode() == ISD::SREM;
3386 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3387 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3388 Tmp2 = Node->getOperand(0);
3389 Tmp3 = Node->getOperand(1);
3390 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3391 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3392 // If div is legal, it's better to do the normal expansion
3393 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
3394 useDivRem(Node, isSigned, false))) {
3395 SDVTList VTs = DAG.getVTList(VT, VT);
3396 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3397 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3399 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3400 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3401 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3402 } else if (isSigned)
3403 Tmp1 = ExpandIntLibCall(Node, true,
3405 RTLIB::SREM_I16, RTLIB::SREM_I32,
3406 RTLIB::SREM_I64, RTLIB::SREM_I128);
3408 Tmp1 = ExpandIntLibCall(Node, false,
3410 RTLIB::UREM_I16, RTLIB::UREM_I32,
3411 RTLIB::UREM_I64, RTLIB::UREM_I128);
3412 Results.push_back(Tmp1);
3417 bool isSigned = Node->getOpcode() == ISD::SDIV;
3418 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3419 EVT VT = Node->getValueType(0);
3420 SDVTList VTs = DAG.getVTList(VT, VT);
3421 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3422 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3423 useDivRem(Node, isSigned, true)))
3424 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3425 Node->getOperand(1));
3427 Tmp1 = ExpandIntLibCall(Node, true,
3429 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3430 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3432 Tmp1 = ExpandIntLibCall(Node, false,
3434 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3435 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3436 Results.push_back(Tmp1);
3441 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3443 EVT VT = Node->getValueType(0);
3444 SDVTList VTs = DAG.getVTList(VT, VT);
3445 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3446 "If this wasn't legal, it shouldn't have been created!");
3447 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3448 Node->getOperand(1));
3449 Results.push_back(Tmp1.getValue(1));
3454 // Expand into divrem libcall
3455 ExpandDivRemLibCall(Node, Results);
3458 EVT VT = Node->getValueType(0);
3459 SDVTList VTs = DAG.getVTList(VT, VT);
3460 // See if multiply or divide can be lowered using two-result operations.
3461 // We just need the low half of the multiply; try both the signed
3462 // and unsigned forms. If the target supports both SMUL_LOHI and
3463 // UMUL_LOHI, form a preference by checking which forms of plain
3464 // MULH it supports.
3465 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3466 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3467 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3468 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3469 unsigned OpToUse = 0;
3470 if (HasSMUL_LOHI && !HasMULHS) {
3471 OpToUse = ISD::SMUL_LOHI;
3472 } else if (HasUMUL_LOHI && !HasMULHU) {
3473 OpToUse = ISD::UMUL_LOHI;
3474 } else if (HasSMUL_LOHI) {
3475 OpToUse = ISD::SMUL_LOHI;
3476 } else if (HasUMUL_LOHI) {
3477 OpToUse = ISD::UMUL_LOHI;
3480 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3481 Node->getOperand(1)));
3484 Tmp1 = ExpandIntLibCall(Node, false,
3486 RTLIB::MUL_I16, RTLIB::MUL_I32,
3487 RTLIB::MUL_I64, RTLIB::MUL_I128);
3488 Results.push_back(Tmp1);
3493 SDValue LHS = Node->getOperand(0);
3494 SDValue RHS = Node->getOperand(1);
3495 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3496 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3498 Results.push_back(Sum);
3499 EVT OType = Node->getValueType(1);
3501 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3503 // LHSSign -> LHS >= 0
3504 // RHSSign -> RHS >= 0
3505 // SumSign -> Sum >= 0
3508 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3510 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3512 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3513 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3514 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3515 Node->getOpcode() == ISD::SADDO ?
3516 ISD::SETEQ : ISD::SETNE);
3518 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3519 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3521 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3522 Results.push_back(Cmp);
3527 SDValue LHS = Node->getOperand(0);
3528 SDValue RHS = Node->getOperand(1);
3529 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3530 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3532 Results.push_back(Sum);
3533 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3534 Node->getOpcode () == ISD::UADDO ?
3535 ISD::SETULT : ISD::SETUGT));
3540 EVT VT = Node->getValueType(0);
3541 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3542 SDValue LHS = Node->getOperand(0);
3543 SDValue RHS = Node->getOperand(1);
3546 static const unsigned Ops[2][3] =
3547 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3548 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3549 bool isSigned = Node->getOpcode() == ISD::SMULO;
3550 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3551 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3552 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3553 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3554 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3556 TopHalf = BottomHalf.getValue(1);
3557 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3558 VT.getSizeInBits() * 2))) {
3559 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3560 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3561 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3562 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3563 DAG.getIntPtrConstant(0));
3564 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3565 DAG.getIntPtrConstant(1));
3567 // We can fall back to a libcall with an illegal type for the MUL if we
3568 // have a libcall big enough.
3569 // Also, we can fall back to a division in some cases, but that's a big
3570 // performance hit in the general case.
3571 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3572 if (WideVT == MVT::i16)
3573 LC = RTLIB::MUL_I16;
3574 else if (WideVT == MVT::i32)
3575 LC = RTLIB::MUL_I32;
3576 else if (WideVT == MVT::i64)
3577 LC = RTLIB::MUL_I64;
3578 else if (WideVT == MVT::i128)
3579 LC = RTLIB::MUL_I128;
3580 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3582 // The high part is obtained by SRA'ing all but one of the bits of low
3584 unsigned LoSize = VT.getSizeInBits();
3585 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3586 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3587 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3588 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3590 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3591 // pre-lowered to the correct types. This all depends upon WideVT not
3592 // being a legal type for the architecture and thus has to be split to
3594 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3595 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3596 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3597 DAG.getIntPtrConstant(0));
3598 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3599 DAG.getIntPtrConstant(1));
3600 // Ret is a node with an illegal type. Because such things are not
3601 // generally permitted during this phase of legalization, delete the
3602 // node. The above EXTRACT_ELEMENT nodes should have been folded.
3603 DAG.DeleteNode(Ret.getNode());
3607 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3608 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3609 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3610 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3613 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3614 DAG.getConstant(0, VT), ISD::SETNE);
3616 Results.push_back(BottomHalf);
3617 Results.push_back(TopHalf);
3620 case ISD::BUILD_PAIR: {
3621 EVT PairTy = Node->getValueType(0);
3622 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3623 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3624 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3625 DAG.getConstant(PairTy.getSizeInBits()/2,
3626 TLI.getShiftAmountTy(PairTy)));
3627 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3631 Tmp1 = Node->getOperand(0);
3632 Tmp2 = Node->getOperand(1);
3633 Tmp3 = Node->getOperand(2);
3634 if (Tmp1.getOpcode() == ISD::SETCC) {
3635 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3637 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3639 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3640 DAG.getConstant(0, Tmp1.getValueType()),
3641 Tmp2, Tmp3, ISD::SETNE);
3643 Results.push_back(Tmp1);
3646 SDValue Chain = Node->getOperand(0);
3647 SDValue Table = Node->getOperand(1);
3648 SDValue Index = Node->getOperand(2);
3650 EVT PTy = TLI.getPointerTy();
3652 const DataLayout &TD = *TLI.getDataLayout();
3653 unsigned EntrySize =
3654 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3656 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(),
3657 Index, DAG.getConstant(EntrySize, Index.getValueType()));
3658 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3661 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3662 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3663 MachinePointerInfo::getJumpTable(), MemVT,
3666 if (TM.getRelocationModel() == Reloc::PIC_) {
3667 // For PIC, the sequence is:
3668 // BRIND(load(Jumptable + index) + RelocBase)
3669 // RelocBase can be JumpTable, GOT or some sort of global base.
3670 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3671 TLI.getPICJumpTableRelocBase(Table, DAG));
3673 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3674 Results.push_back(Tmp1);
3678 // Expand brcond's setcc into its constituent parts and create a BR_CC
3680 Tmp1 = Node->getOperand(0);
3681 Tmp2 = Node->getOperand(1);
3682 if (Tmp2.getOpcode() == ISD::SETCC) {
3683 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3684 Tmp1, Tmp2.getOperand(2),
3685 Tmp2.getOperand(0), Tmp2.getOperand(1),
3686 Node->getOperand(2));
3688 // We test only the i1 bit. Skip the AND if UNDEF.
3689 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3690 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3691 DAG.getConstant(1, Tmp2.getValueType()));
3692 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3693 DAG.getCondCode(ISD::SETNE), Tmp3,
3694 DAG.getConstant(0, Tmp3.getValueType()),
3695 Node->getOperand(2));
3697 Results.push_back(Tmp1);
3700 Tmp1 = Node->getOperand(0);
3701 Tmp2 = Node->getOperand(1);
3702 Tmp3 = Node->getOperand(2);
3703 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3704 Tmp3, NeedInvert, dl);
3707 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3708 // condition code, create a new SETCC node.
3710 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3713 // If we expanded the SETCC by inverting the condition code, then wrap
3714 // the existing SETCC in a NOT to restore the intended condition.
3716 Tmp1 = DAG.getNOT(dl, Tmp1, Tmp1->getValueType(0));
3718 Results.push_back(Tmp1);
3722 // Otherwise, SETCC for the given comparison type must be completely
3723 // illegal; expand it into a SELECT_CC.
3724 EVT VT = Node->getValueType(0);
3726 switch (TLI.getBooleanContents(VT.isVector())) {
3727 case TargetLowering::ZeroOrOneBooleanContent:
3728 case TargetLowering::UndefinedBooleanContent:
3731 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3735 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3736 DAG.getConstant(TrueValue, VT), DAG.getConstant(0, VT),
3738 Results.push_back(Tmp1);
3741 case ISD::SELECT_CC: {
3742 Tmp1 = Node->getOperand(0); // LHS
3743 Tmp2 = Node->getOperand(1); // RHS
3744 Tmp3 = Node->getOperand(2); // True
3745 Tmp4 = Node->getOperand(3); // False
3746 SDValue CC = Node->getOperand(4);
3748 bool Legalized = false;
3749 // Try to legalize by inverting the condition. This is for targets that
3750 // might support an ordered version of a condition, but not the unordered
3751 // version (or vice versa).
3752 ISD::CondCode InvCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3753 Tmp1.getValueType().isInteger());
3754 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
3755 // Use the new condition code and swap true and false
3757 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3759 // If The inverse is not legal, then try to swap the arguments using
3760 // the inverse condition code.
3761 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3762 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
3763 // The swapped inverse condition is legal, so swap true and false,
3766 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3771 Legalized = LegalizeSetCCCondCode(
3772 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3775 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3777 // If we expanded the SETCC by inverting the condition code, then swap
3778 // the True/False operands to match.
3780 std::swap(Tmp3, Tmp4);
3782 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3783 // condition code, create a new SELECT_CC node.
3785 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3786 Tmp1, Tmp2, Tmp3, Tmp4, CC);
3788 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3789 CC = DAG.getCondCode(ISD::SETNE);
3790 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3791 Tmp2, Tmp3, Tmp4, CC);
3794 Results.push_back(Tmp1);
3798 Tmp1 = Node->getOperand(0); // Chain
3799 Tmp2 = Node->getOperand(2); // LHS
3800 Tmp3 = Node->getOperand(3); // RHS
3801 Tmp4 = Node->getOperand(1); // CC
3803 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3804 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
3806 assert(Legalized && "Can't legalize BR_CC with legal condition!");
3808 // If we expanded the SETCC by inverting the condition code, then wrap
3809 // the existing SETCC in a NOT to restore the intended condition.
3811 Tmp4 = DAG.getNOT(dl, Tmp4, Tmp4->getValueType(0));
3813 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3815 if (Tmp4.getNode()) {
3816 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3817 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3819 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3820 Tmp4 = DAG.getCondCode(ISD::SETNE);
3821 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
3822 Tmp2, Tmp3, Node->getOperand(4));
3824 Results.push_back(Tmp1);
3827 case ISD::BUILD_VECTOR:
3828 Results.push_back(ExpandBUILD_VECTOR(Node));
3833 // Scalarize vector SRA/SRL/SHL.
3834 EVT VT = Node->getValueType(0);
3835 assert(VT.isVector() && "Unable to legalize non-vector shift");
3836 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3837 unsigned NumElem = VT.getVectorNumElements();
3839 SmallVector<SDValue, 8> Scalars;
3840 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3841 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3843 Node->getOperand(0), DAG.getConstant(Idx,
3844 TLI.getVectorIdxTy()));
3845 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3847 Node->getOperand(1), DAG.getConstant(Idx,
3848 TLI.getVectorIdxTy()));
3849 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3850 VT.getScalarType(), Ex, Sh));
3853 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
3854 &Scalars[0], Scalars.size());
3855 ReplaceNode(SDValue(Node, 0), Result);
3858 case ISD::GLOBAL_OFFSET_TABLE:
3859 case ISD::GlobalAddress:
3860 case ISD::GlobalTLSAddress:
3861 case ISD::ExternalSymbol:
3862 case ISD::ConstantPool:
3863 case ISD::JumpTable:
3864 case ISD::INTRINSIC_W_CHAIN:
3865 case ISD::INTRINSIC_WO_CHAIN:
3866 case ISD::INTRINSIC_VOID:
3867 // FIXME: Custom lowering for these operations shouldn't return null!
3871 // Replace the original node with the legalized result.
3872 if (!Results.empty())
3873 ReplaceNode(Node, Results.data());
3876 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
3877 SmallVector<SDValue, 8> Results;
3878 MVT OVT = Node->getSimpleValueType(0);
3879 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3880 Node->getOpcode() == ISD::SINT_TO_FP ||
3881 Node->getOpcode() == ISD::SETCC) {
3882 OVT = Node->getOperand(0).getSimpleValueType();
3884 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3886 SDValue Tmp1, Tmp2, Tmp3;
3887 switch (Node->getOpcode()) {
3889 case ISD::CTTZ_ZERO_UNDEF:
3891 case ISD::CTLZ_ZERO_UNDEF:
3893 // Zero extend the argument.
3894 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3895 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
3896 // already the correct result.
3897 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3898 if (Node->getOpcode() == ISD::CTTZ) {
3899 // FIXME: This should set a bit in the zero extended value instead.
3900 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
3901 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3903 Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
3904 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3905 } else if (Node->getOpcode() == ISD::CTLZ ||
3906 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
3907 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3908 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3909 DAG.getConstant(NVT.getSizeInBits() -
3910 OVT.getSizeInBits(), NVT));
3912 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3915 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3916 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3917 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3918 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3919 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3920 Results.push_back(Tmp1);
3923 case ISD::FP_TO_UINT:
3924 case ISD::FP_TO_SINT:
3925 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3926 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3927 Results.push_back(Tmp1);
3929 case ISD::UINT_TO_FP:
3930 case ISD::SINT_TO_FP:
3931 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3932 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3933 Results.push_back(Tmp1);
3936 SDValue Chain = Node->getOperand(0); // Get the chain.
3937 SDValue Ptr = Node->getOperand(1); // Get the pointer.
3940 if (OVT.isVector()) {
3941 TruncOp = ISD::BITCAST;
3943 assert(OVT.isInteger()
3944 && "VAARG promotion is supported only for vectors or integer types");
3945 TruncOp = ISD::TRUNCATE;
3948 // Perform the larger operation, then convert back
3949 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
3950 Node->getConstantOperandVal(3));
3951 Chain = Tmp1.getValue(1);
3953 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
3955 // Modified the chain result - switch anything that used the old chain to
3957 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
3958 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
3965 unsigned ExtOp, TruncOp;
3966 if (OVT.isVector()) {
3967 ExtOp = ISD::BITCAST;
3968 TruncOp = ISD::BITCAST;
3970 assert(OVT.isInteger() && "Cannot promote logic operation");
3971 ExtOp = ISD::ANY_EXTEND;
3972 TruncOp = ISD::TRUNCATE;
3974 // Promote each of the values to the new type.
3975 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3976 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3977 // Perform the larger operation, then convert back
3978 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3979 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3983 unsigned ExtOp, TruncOp;
3984 if (Node->getValueType(0).isVector()) {
3985 ExtOp = ISD::BITCAST;
3986 TruncOp = ISD::BITCAST;
3987 } else if (Node->getValueType(0).isInteger()) {
3988 ExtOp = ISD::ANY_EXTEND;
3989 TruncOp = ISD::TRUNCATE;
3991 ExtOp = ISD::FP_EXTEND;
3992 TruncOp = ISD::FP_ROUND;
3994 Tmp1 = Node->getOperand(0);
3995 // Promote each of the values to the new type.
3996 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3997 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3998 // Perform the larger operation, then round down.
3999 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4000 if (TruncOp != ISD::FP_ROUND)
4001 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4003 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4004 DAG.getIntPtrConstant(0));
4005 Results.push_back(Tmp1);
4008 case ISD::VECTOR_SHUFFLE: {
4009 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4011 // Cast the two input vectors.
4012 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4013 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4015 // Convert the shuffle mask to the right # elements.
4016 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4017 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4018 Results.push_back(Tmp1);
4022 unsigned ExtOp = ISD::FP_EXTEND;
4023 if (NVT.isInteger()) {
4024 ISD::CondCode CCCode =
4025 cast<CondCodeSDNode>(Node->getOperand(2))->get();
4026 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4028 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4029 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4030 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4031 Tmp1, Tmp2, Node->getOperand(2)));
4037 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4038 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4039 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4040 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4041 Tmp3, DAG.getIntPtrConstant(0)));
4048 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4049 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4050 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4051 Tmp2, DAG.getIntPtrConstant(0)));
4056 // Replace the original node with the legalized result.
4057 if (!Results.empty())
4058 ReplaceNode(Node, Results.data());
4061 // SelectionDAG::Legalize - This is the entry point for the file.
4063 void SelectionDAG::Legalize() {
4064 /// run - This is the main entry point to this class.
4066 SelectionDAGLegalize(*this).LegalizeDAG();