1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/DwarfWriter.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetSubtarget.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/DerivedTypes.h"
31 #include "llvm/Function.h"
32 #include "llvm/GlobalVariable.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/ADT/DenseMap.h"
37 #include "llvm/ADT/SmallVector.h"
38 #include "llvm/ADT/SmallPtrSet.h"
42 //===----------------------------------------------------------------------===//
43 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class VISIBILITY_HIDDEN SelectionDAGLegalize {
58 bool TypesNeedLegalizing;
61 // Libcall insertion helpers.
63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
64 /// legalized. We use this to ensure that calls are properly serialized
65 /// against each other, including inserted libcalls.
66 SDValue LastCALLSEQ_END;
68 /// IsLegalizingCall - This member is used *only* for purposes of providing
69 /// helpful assertions that a libcall isn't created while another call is
70 /// being legalized (which could lead to non-serialized call sequences).
71 bool IsLegalizingCall;
73 /// IsLegalizingCallArguments - This member is used only for the purpose
74 /// of providing assert to check for LegalizeTypes because legalizing an
75 /// operation might introduce call nodes that might need type legalization.
76 bool IsLegalizingCallArgs;
79 Legal, // The target natively supports this operation.
80 Promote, // This operation should be executed in a larger type.
81 Expand // Try to expand this to other ops, otherwise use a libcall.
84 /// ValueTypeActions - This is a bitvector that contains two bits for each
85 /// value type, where the two bits correspond to the LegalizeAction enum.
86 /// This can be queried with "getTypeAction(VT)".
87 TargetLowering::ValueTypeActionImpl ValueTypeActions;
89 /// LegalizedNodes - For nodes that are of legal width, and that have more
90 /// than one use, this map indicates what regularized operand to use. This
91 /// allows us to avoid legalizing the same thing more than once.
92 DenseMap<SDValue, SDValue> LegalizedNodes;
94 /// PromotedNodes - For nodes that are below legal width, and that have more
95 /// than one use, this map indicates what promoted value to use. This allows
96 /// us to avoid promoting the same thing more than once.
97 DenseMap<SDValue, SDValue> PromotedNodes;
99 /// ExpandedNodes - For nodes that need to be expanded this map indicates
100 /// which operands are the expanded version of the input. This allows
101 /// us to avoid expanding the same node more than once.
102 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
104 /// SplitNodes - For vector nodes that need to be split, this map indicates
105 /// which operands are the split version of the input. This allows us
106 /// to avoid splitting the same node more than once.
107 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
109 /// ScalarizedNodes - For nodes that need to be converted from vector types to
110 /// scalar types, this contains the mapping of ones we have already
111 /// processed to the result.
112 std::map<SDValue, SDValue> ScalarizedNodes;
114 /// WidenNodes - For nodes that need to be widened from one vector type to
115 /// another, this contains the mapping of those that we have already widen.
116 /// This allows us to avoid widening more than once.
117 std::map<SDValue, SDValue> WidenNodes;
119 void AddLegalizedOperand(SDValue From, SDValue To) {
120 LegalizedNodes.insert(std::make_pair(From, To));
121 // If someone requests legalization of the new node, return itself.
123 LegalizedNodes.insert(std::make_pair(To, To));
125 void AddPromotedOperand(SDValue From, SDValue To) {
126 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
127 assert(isNew && "Got into the map somehow?");
129 // If someone requests legalization of the new node, return itself.
130 LegalizedNodes.insert(std::make_pair(To, To));
132 void AddWidenedOperand(SDValue From, SDValue To) {
133 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second;
134 assert(isNew && "Got into the map somehow?");
136 // If someone requests legalization of the new node, return itself.
137 LegalizedNodes.insert(std::make_pair(To, To));
141 explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing,
144 /// getTypeAction - Return how we should legalize values of this type, either
145 /// it is already legal or we need to expand it into multiple registers of
146 /// smaller integer type, or we need to promote it to a larger type.
147 LegalizeAction getTypeAction(MVT VT) const {
148 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
151 /// isTypeLegal - Return true if this type is legal on this target.
153 bool isTypeLegal(MVT VT) const {
154 return getTypeAction(VT) == Legal;
160 /// HandleOp - Legalize, Promote, or Expand the specified operand as
161 /// appropriate for its type.
162 void HandleOp(SDValue Op);
164 /// LegalizeOp - We know that the specified value has a legal type.
165 /// Recursively ensure that the operands have legal types, then return the
167 SDValue LegalizeOp(SDValue O);
169 /// UnrollVectorOp - We know that the given vector has a legal type, however
170 /// the operation it performs is not legal and is an operation that we have
171 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
172 /// operating on each element individually.
173 SDValue UnrollVectorOp(SDValue O);
175 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
176 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
177 /// is necessary to spill the vector being inserted into to memory, perform
178 /// the insert there, and then read the result back.
179 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
180 SDValue Idx, DebugLoc dl);
182 /// PromoteOp - Given an operation that produces a value in an invalid type,
183 /// promote it to compute the value into a larger type. The produced value
184 /// will have the correct bits for the low portion of the register, but no
185 /// guarantee is made about the top bits: it may be zero, sign-extended, or
187 SDValue PromoteOp(SDValue O);
189 /// ExpandOp - Expand the specified SDValue into its two component pieces
190 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
191 /// the LegalizedNodes map is filled in for any results that are not expanded,
192 /// the ExpandedNodes map is filled in for any results that are expanded, and
193 /// the Lo/Hi values are returned. This applies to integer types and Vector
195 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
197 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
198 /// (e.g., v3i32 to v4i32). The produced value will have the correct value
199 /// for the existing elements but no guarantee is made about the new elements
200 /// at the end of the vector: it may be zero, ones, or garbage. This is useful
201 /// when we have an instruction operating on an illegal vector type and we
202 /// want to widen it to do the computation on a legal wider vector type.
203 SDValue WidenVectorOp(SDValue Op, MVT WidenVT);
205 /// SplitVectorOp - Given an operand of vector type, break it down into
206 /// two smaller values.
207 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
209 /// ScalarizeVectorOp - Given an operand of single-element vector type
210 /// (e.g. v1f32), convert it into the equivalent operation that returns a
211 /// scalar (e.g. f32) value.
212 SDValue ScalarizeVectorOp(SDValue O);
214 /// Useful 16 element vector type that is used to pass operands for widening.
215 typedef SmallVector<SDValue, 16> SDValueVector;
217 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if
218 /// the LdChain contains a single load and false if it contains a token
219 /// factor for multiple loads. It takes
220 /// Result: location to return the result
221 /// LdChain: location to return the load chain
222 /// Op: load operation to widen
223 /// NVT: widen vector result type we want for the load
224 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
225 SDValue Op, MVT NVT);
227 /// Helper genWidenVectorLoads - Helper function to generate a set of
228 /// loads to load a vector with a resulting wider type. It takes
229 /// LdChain: list of chains for the load we have generated
230 /// Chain: incoming chain for the ld vector
231 /// BasePtr: base pointer to load from
232 /// SV: memory disambiguation source value
233 /// SVOffset: memory disambiugation offset
234 /// Alignment: alignment of the memory
235 /// isVolatile: volatile load
236 /// LdWidth: width of memory that we want to load
237 /// ResType: the wider result result type for the resulting loaded vector
238 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain,
239 SDValue BasePtr, const Value *SV,
240 int SVOffset, unsigned Alignment,
241 bool isVolatile, unsigned LdWidth,
242 MVT ResType, DebugLoc dl);
244 /// StoreWidenVectorOp - Stores a widen vector into non widen memory
245 /// location. It takes
246 /// ST: store node that we want to replace
247 /// Chain: incoming store chain
248 /// BasePtr: base address of where we want to store into
249 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
252 /// Helper genWidenVectorStores - Helper function to generate a set of
253 /// stores to store a widen vector into non widen memory
255 // StChain: list of chains for the stores we have generated
256 // Chain: incoming chain for the ld vector
257 // BasePtr: base pointer to load from
258 // SV: memory disambiguation source value
259 // SVOffset: memory disambiugation offset
260 // Alignment: alignment of the memory
261 // isVolatile: volatile lod
262 // ValOp: value to store
263 // StWidth: width of memory that we want to store
264 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain,
265 SDValue BasePtr, const Value *SV,
266 int SVOffset, unsigned Alignment,
267 bool isVolatile, SDValue ValOp,
268 unsigned StWidth, DebugLoc dl);
270 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
271 /// specified mask and type. Targets can specify exactly which masks they
272 /// support and the code generator is tasked with not creating illegal masks.
274 /// Note that this will also return true for shuffles that are promoted to a
277 /// If this is a legal shuffle, this method returns the (possibly promoted)
278 /// build_vector Mask. If it's not a legal shuffle, it returns null.
279 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
281 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
282 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
284 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC,
286 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
288 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
290 LegalizeSetCCOperands(LHS, RHS, CC, dl);
291 LegalizeSetCCCondCode(VT, LHS, RHS, CC, dl);
294 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
296 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl);
298 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl);
299 SDValue ExpandBUILD_VECTOR(SDNode *Node);
300 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
301 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy,
302 SDValue Op, DebugLoc dl);
303 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT,
305 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned,
307 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned,
310 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
311 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
312 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
313 SDValue &Lo, SDValue &Hi, DebugLoc dl);
314 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
315 SDValue &Lo, SDValue &Hi, DebugLoc dl);
317 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
318 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
322 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
323 /// specified mask and type. Targets can specify exactly which masks they
324 /// support and the code generator is tasked with not creating illegal masks.
326 /// Note that this will also return true for shuffles that are promoted to a
328 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
329 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
331 case TargetLowering::Legal:
332 case TargetLowering::Custom:
334 case TargetLowering::Promote: {
335 // If this is promoted to a different type, convert the shuffle mask and
336 // ask if it is legal in the promoted type!
337 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
338 MVT EltVT = NVT.getVectorElementType();
340 // If we changed # elements, change the shuffle mask.
341 unsigned NumEltsGrowth =
342 NVT.getVectorNumElements() / VT.getVectorNumElements();
343 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
344 if (NumEltsGrowth > 1) {
345 // Renumber the elements.
346 SmallVector<SDValue, 8> Ops;
347 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
348 SDValue InOp = Mask.getOperand(i);
349 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
350 if (InOp.getOpcode() == ISD::UNDEF)
351 Ops.push_back(DAG.getUNDEF(EltVT));
353 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
354 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
358 Mask = DAG.getBUILD_VECTOR(NVT, Mask.getDebugLoc(), &Ops[0], Ops.size());
364 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
367 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
368 bool types, bool fast)
369 : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types),
370 Fast(fast), ValueTypeActions(TLI.getValueTypeActions()) {
371 assert(MVT::LAST_VALUETYPE <= 32 &&
372 "Too many value types for ValueTypeActions to hold!");
375 void SelectionDAGLegalize::LegalizeDAG() {
376 LastCALLSEQ_END = DAG.getEntryNode();
377 IsLegalizingCall = false;
378 IsLegalizingCallArgs = false;
380 // The legalize process is inherently a bottom-up recursive process (users
381 // legalize their uses before themselves). Given infinite stack space, we
382 // could just start legalizing on the root and traverse the whole graph. In
383 // practice however, this causes us to run out of stack space on large basic
384 // blocks. To avoid this problem, compute an ordering of the nodes where each
385 // node is only legalized after all of its operands are legalized.
386 DAG.AssignTopologicalOrder();
387 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
388 E = prior(DAG.allnodes_end()); I != next(E); ++I)
389 HandleOp(SDValue(I, 0));
391 // Finally, it's possible the root changed. Get the new root.
392 SDValue OldRoot = DAG.getRoot();
393 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
394 DAG.setRoot(LegalizedNodes[OldRoot]);
396 ExpandedNodes.clear();
397 LegalizedNodes.clear();
398 PromotedNodes.clear();
400 ScalarizedNodes.clear();
403 // Remove dead nodes now.
404 DAG.RemoveDeadNodes();
408 /// FindCallEndFromCallStart - Given a chained node that is part of a call
409 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
410 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
411 if (Node->getOpcode() == ISD::CALLSEQ_END)
413 if (Node->use_empty())
414 return 0; // No CallSeqEnd
416 // The chain is usually at the end.
417 SDValue TheChain(Node, Node->getNumValues()-1);
418 if (TheChain.getValueType() != MVT::Other) {
419 // Sometimes it's at the beginning.
420 TheChain = SDValue(Node, 0);
421 if (TheChain.getValueType() != MVT::Other) {
422 // Otherwise, hunt for it.
423 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
424 if (Node->getValueType(i) == MVT::Other) {
425 TheChain = SDValue(Node, i);
429 // Otherwise, we walked into a node without a chain.
430 if (TheChain.getValueType() != MVT::Other)
435 for (SDNode::use_iterator UI = Node->use_begin(),
436 E = Node->use_end(); UI != E; ++UI) {
438 // Make sure to only follow users of our token chain.
440 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
441 if (User->getOperand(i) == TheChain)
442 if (SDNode *Result = FindCallEndFromCallStart(User))
448 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
449 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
450 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
451 assert(Node && "Didn't find callseq_start for a call??");
452 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
454 assert(Node->getOperand(0).getValueType() == MVT::Other &&
455 "Node doesn't have a token chain argument!");
456 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
459 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
460 /// see if any uses can reach Dest. If no dest operands can get to dest,
461 /// legalize them, legalize ourself, and return false, otherwise, return true.
463 /// Keep track of the nodes we fine that actually do lead to Dest in
464 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
466 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
467 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
468 if (N == Dest) return true; // N certainly leads to Dest :)
470 // If we've already processed this node and it does lead to Dest, there is no
471 // need to reprocess it.
472 if (NodesLeadingTo.count(N)) return true;
474 // If the first result of this node has been already legalized, then it cannot
476 switch (getTypeAction(N->getValueType(0))) {
478 if (LegalizedNodes.count(SDValue(N, 0))) return false;
481 if (PromotedNodes.count(SDValue(N, 0))) return false;
484 if (ExpandedNodes.count(SDValue(N, 0))) return false;
488 // Okay, this node has not already been legalized. Check and legalize all
489 // operands. If none lead to Dest, then we can legalize this node.
490 bool OperandsLeadToDest = false;
491 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
492 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
493 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
495 if (OperandsLeadToDest) {
496 NodesLeadingTo.insert(N);
500 // Okay, this node looks safe, legalize it and return false.
501 HandleOp(SDValue(N, 0));
505 /// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as
506 /// appropriate for its type.
507 void SelectionDAGLegalize::HandleOp(SDValue Op) {
508 MVT VT = Op.getValueType();
509 // If the type legalizer was run then we should never see any illegal result
510 // types here except for target constants (the type legalizer does not touch
511 // those) or for build vector used as a mask for a vector shuffle.
512 // FIXME: We can removed the BUILD_VECTOR case when we fix PR2957.
513 assert((TypesNeedLegalizing || getTypeAction(VT) == Legal ||
514 IsLegalizingCallArgs || Op.getOpcode() == ISD::TargetConstant ||
515 Op.getOpcode() == ISD::BUILD_VECTOR) &&
516 "Illegal type introduced after type legalization?");
517 switch (getTypeAction(VT)) {
518 default: assert(0 && "Bad type action!");
519 case Legal: (void)LegalizeOp(Op); break;
521 if (!VT.isVector()) {
526 // See if we can widen otherwise use Expand to either scalarize or split
527 MVT WidenVT = TLI.getWidenVectorType(VT);
528 if (WidenVT != MVT::Other) {
529 (void) WidenVectorOp(Op, WidenVT);
532 // else fall thru to expand since we can't widen the vector
535 if (!VT.isVector()) {
536 // If this is an illegal scalar, expand it into its two component
539 if (Op.getOpcode() == ISD::TargetConstant)
540 break; // Allow illegal target nodes.
542 } else if (VT.getVectorNumElements() == 1) {
543 // If this is an illegal single element vector, convert it to a
545 (void)ScalarizeVectorOp(Op);
547 // This is an illegal multiple element vector.
548 // Split it in half and legalize both parts.
550 SplitVectorOp(Op, X, Y);
556 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
557 /// a load from the constant pool.
558 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
559 SelectionDAG &DAG, const TargetLowering &TLI) {
561 DebugLoc dl = CFP->getDebugLoc();
563 // If a FP immediate is precise when represented as a float and if the
564 // target can do an extending load from float to double, we put it into
565 // the constant pool as a float, even if it's is statically typed as a
566 // double. This shrinks FP constants and canonicalizes them for targets where
567 // an FP extending load is the same cost as a normal load (such as on the x87
568 // fp stack or PPC FP unit).
569 MVT VT = CFP->getValueType(0);
570 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
572 if (VT!=MVT::f64 && VT!=MVT::f32)
573 assert(0 && "Invalid type expansion");
574 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
575 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
580 while (SVT != MVT::f32) {
581 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
582 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
583 // Only do this if the target has a native EXTLOAD instruction from
585 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
586 TLI.ShouldShrinkFPConstant(OrigVT)) {
587 const Type *SType = SVT.getTypeForMVT();
588 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
594 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
595 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
597 return DAG.getExtLoad(ISD::EXTLOAD, dl,
598 OrigVT, DAG.getEntryNode(),
599 CPIdx, PseudoSourceValue::getConstantPool(),
600 0, VT, false, Alignment);
601 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
602 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
606 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
609 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
611 const TargetLowering &TLI) {
612 DebugLoc dl = Node->getDebugLoc();
613 MVT VT = Node->getValueType(0);
614 MVT SrcVT = Node->getOperand(1).getValueType();
615 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
616 "fcopysign expansion only supported for f32 and f64");
617 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
619 // First get the sign bit of second operand.
620 SDValue Mask1 = (SrcVT == MVT::f64)
621 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
622 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
623 Mask1 = DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT, Mask1);
624 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT,
625 Node->getOperand(1));
626 SignBit = DAG.getNode(ISD::AND, dl, SrcNVT, SignBit, Mask1);
627 // Shift right or sign-extend it if the two operands have different types.
628 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
630 SignBit = DAG.getNode(ISD::SRL, dl, SrcNVT, SignBit,
631 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
632 SignBit = DAG.getNode(ISD::TRUNCATE, dl, NVT, SignBit);
633 } else if (SizeDiff < 0) {
634 SignBit = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, SignBit);
635 SignBit = DAG.getNode(ISD::SHL, dl, NVT, SignBit,
636 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
639 // Clear the sign bit of first operand.
640 SDValue Mask2 = (VT == MVT::f64)
641 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
642 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
643 Mask2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask2);
644 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
645 Result = DAG.getNode(ISD::AND, dl, NVT, Result, Mask2);
647 // Or the value with the sign bit.
648 Result = DAG.getNode(ISD::OR, dl, NVT, Result, SignBit);
652 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
654 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
655 const TargetLowering &TLI) {
656 SDValue Chain = ST->getChain();
657 SDValue Ptr = ST->getBasePtr();
658 SDValue Val = ST->getValue();
659 MVT VT = Val.getValueType();
660 int Alignment = ST->getAlignment();
661 int SVOffset = ST->getSrcValueOffset();
662 DebugLoc dl = ST->getDebugLoc();
663 if (ST->getMemoryVT().isFloatingPoint() ||
664 ST->getMemoryVT().isVector()) {
665 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
666 if (TLI.isTypeLegal(intVT)) {
667 // Expand to a bitconvert of the value to the integer type of the
668 // same size, then a (misaligned) int store.
669 // FIXME: Does not handle truncating floating point stores!
670 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
671 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
672 SVOffset, ST->isVolatile(), Alignment);
674 // Do a (aligned) store to a stack slot, then copy from the stack slot
675 // to the final destination using (unaligned) integer loads and stores.
676 MVT StoredVT = ST->getMemoryVT();
678 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
679 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
680 unsigned RegBytes = RegVT.getSizeInBits() / 8;
681 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
683 // Make sure the stack slot is also aligned for the register type.
684 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
686 // Perform the original store, only redirected to the stack slot.
687 SDValue Store = DAG.getTruncStore(Chain, dl,
688 Val, StackPtr, NULL, 0,StoredVT);
689 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
690 SmallVector<SDValue, 8> Stores;
693 // Do all but one copies using the full register width.
694 for (unsigned i = 1; i < NumRegs; i++) {
695 // Load one integer register's worth from the stack slot.
696 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0);
697 // Store it to the final location. Remember the store.
698 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
699 ST->getSrcValue(), SVOffset + Offset,
701 MinAlign(ST->getAlignment(), Offset)));
702 // Increment the pointers.
704 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
706 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
709 // The last store may be partial. Do a truncating store. On big-endian
710 // machines this requires an extending load from the stack slot to ensure
711 // that the bits are in the right place.
712 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
714 // Load from the stack slot.
715 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
718 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
719 ST->getSrcValue(), SVOffset + Offset,
720 MemVT, ST->isVolatile(),
721 MinAlign(ST->getAlignment(), Offset)));
722 // The order of the stores doesn't matter - say it with a TokenFactor.
723 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
727 assert(ST->getMemoryVT().isInteger() &&
728 !ST->getMemoryVT().isVector() &&
729 "Unaligned store of unknown type.");
730 // Get the half-size VT
732 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
733 int NumBits = NewStoredVT.getSizeInBits();
734 int IncrementSize = NumBits / 8;
736 // Divide the stored value in two parts.
737 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
739 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
741 // Store the two parts
742 SDValue Store1, Store2;
743 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
744 ST->getSrcValue(), SVOffset, NewStoredVT,
745 ST->isVolatile(), Alignment);
746 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
747 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
748 Alignment = MinAlign(Alignment, IncrementSize);
749 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
750 ST->getSrcValue(), SVOffset + IncrementSize,
751 NewStoredVT, ST->isVolatile(), Alignment);
753 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
756 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
758 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
759 const TargetLowering &TLI) {
760 int SVOffset = LD->getSrcValueOffset();
761 SDValue Chain = LD->getChain();
762 SDValue Ptr = LD->getBasePtr();
763 MVT VT = LD->getValueType(0);
764 MVT LoadedVT = LD->getMemoryVT();
765 DebugLoc dl = LD->getDebugLoc();
766 if (VT.isFloatingPoint() || VT.isVector()) {
767 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
768 if (TLI.isTypeLegal(intVT)) {
769 // Expand to a (misaligned) integer load of the same size,
770 // then bitconvert to floating point or vector.
771 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
772 SVOffset, LD->isVolatile(),
774 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
775 if (VT.isFloatingPoint() && LoadedVT != VT)
776 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
778 SDValue Ops[] = { Result, Chain };
779 return DAG.getMergeValues(Ops, 2, dl);
781 // Copy the value to a (aligned) stack slot using (unaligned) integer
782 // loads and stores, then do a (aligned) load from the stack slot.
783 MVT RegVT = TLI.getRegisterType(intVT);
784 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
785 unsigned RegBytes = RegVT.getSizeInBits() / 8;
786 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
788 // Make sure the stack slot is also aligned for the register type.
789 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
791 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
792 SmallVector<SDValue, 8> Stores;
793 SDValue StackPtr = StackBase;
796 // Do all but one copies using the full register width.
797 for (unsigned i = 1; i < NumRegs; i++) {
798 // Load one integer register's worth from the original location.
799 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
800 SVOffset + Offset, LD->isVolatile(),
801 MinAlign(LD->getAlignment(), Offset));
802 // Follow the load with a store to the stack slot. Remember the store.
803 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
805 // Increment the pointers.
807 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
808 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
812 // The last copy may be partial. Do an extending load.
813 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
814 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
815 LD->getSrcValue(), SVOffset + Offset,
816 MemVT, LD->isVolatile(),
817 MinAlign(LD->getAlignment(), Offset));
818 // Follow the load with a store to the stack slot. Remember the store.
819 // On big-endian machines this requires a truncating store to ensure
820 // that the bits end up in the right place.
821 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
824 // The order of the stores doesn't matter - say it with a TokenFactor.
825 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
828 // Finally, perform the original load only redirected to the stack slot.
829 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
832 // Callers expect a MERGE_VALUES node.
833 SDValue Ops[] = { Load, TF };
834 return DAG.getMergeValues(Ops, 2, dl);
837 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
838 "Unaligned load of unsupported type.");
840 // Compute the new VT that is half the size of the old one. This is an
842 unsigned NumBits = LoadedVT.getSizeInBits();
844 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
847 unsigned Alignment = LD->getAlignment();
848 unsigned IncrementSize = NumBits / 8;
849 ISD::LoadExtType HiExtType = LD->getExtensionType();
851 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
852 if (HiExtType == ISD::NON_EXTLOAD)
853 HiExtType = ISD::ZEXTLOAD;
855 // Load the value in two parts
857 if (TLI.isLittleEndian()) {
858 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
859 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
860 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
861 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
862 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
863 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
864 MinAlign(Alignment, IncrementSize));
866 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
867 SVOffset, NewLoadedVT,LD->isVolatile(), Alignment);
868 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
869 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
870 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
871 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
872 MinAlign(Alignment, IncrementSize));
875 // aggregate the two parts
876 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
877 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
878 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
880 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
883 SDValue Ops[] = { Result, TF };
884 return DAG.getMergeValues(Ops, 2, dl);
887 /// UnrollVectorOp - We know that the given vector has a legal type, however
888 /// the operation it performs is not legal and is an operation that we have
889 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
890 /// operating on each element individually.
891 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
892 MVT VT = Op.getValueType();
893 assert(isTypeLegal(VT) &&
894 "Caller should expand or promote operands that are not legal!");
895 assert(Op.getNode()->getNumValues() == 1 &&
896 "Can't unroll a vector with multiple results!");
897 unsigned NE = VT.getVectorNumElements();
898 MVT EltVT = VT.getVectorElementType();
899 DebugLoc dl = Op.getDebugLoc();
901 SmallVector<SDValue, 8> Scalars;
902 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
903 for (unsigned i = 0; i != NE; ++i) {
904 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
905 SDValue Operand = Op.getOperand(j);
906 MVT OperandVT = Operand.getValueType();
907 if (OperandVT.isVector()) {
908 // A vector operand; extract a single element.
909 MVT OperandEltVT = OperandVT.getVectorElementType();
910 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
913 DAG.getConstant(i, MVT::i32));
915 // A scalar operand; just use it as is.
916 Operands[j] = Operand;
920 switch (Op.getOpcode()) {
922 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT,
923 &Operands[0], Operands.size()));
930 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, Operands[0],
931 DAG.getShiftAmountOperand(Operands[1])));
936 return DAG.getBUILD_VECTOR(VT, dl, &Scalars[0], Scalars.size());
939 /// GetFPLibCall - Return the right libcall for the given floating point type.
940 static RTLIB::Libcall GetFPLibCall(MVT VT,
941 RTLIB::Libcall Call_F32,
942 RTLIB::Libcall Call_F64,
943 RTLIB::Libcall Call_F80,
944 RTLIB::Libcall Call_PPCF128) {
946 VT == MVT::f32 ? Call_F32 :
947 VT == MVT::f64 ? Call_F64 :
948 VT == MVT::f80 ? Call_F80 :
949 VT == MVT::ppcf128 ? Call_PPCF128 :
950 RTLIB::UNKNOWN_LIBCALL;
953 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
954 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
955 /// is necessary to spill the vector being inserted into to memory, perform
956 /// the insert there, and then read the result back.
957 SDValue SelectionDAGLegalize::
958 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
964 // If the target doesn't support this, we have to spill the input vector
965 // to a temporary stack slot, update the element, then reload it. This is
966 // badness. We could also load the value into a vector register (either
967 // with a "move to register" or "extload into register" instruction, then
968 // permute it into place, if the idx is a constant and if the idx is
969 // supported by the target.
970 MVT VT = Tmp1.getValueType();
971 MVT EltVT = VT.getVectorElementType();
972 MVT IdxVT = Tmp3.getValueType();
973 MVT PtrVT = TLI.getPointerTy();
974 SDValue StackPtr = DAG.CreateStackTemporary(VT);
976 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
979 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
980 PseudoSourceValue::getFixedStack(SPFI), 0);
982 // Truncate or zero extend offset to target pointer type.
983 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
984 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
985 // Add the offset to the index.
986 unsigned EltSize = EltVT.getSizeInBits()/8;
987 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
988 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
989 // Store the scalar value.
990 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
991 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
992 // Load the updated vector.
993 return DAG.getLoad(VT, dl, Ch, StackPtr,
994 PseudoSourceValue::getFixedStack(SPFI), 0);
998 /// LegalizeOp - We know that the specified value has a legal type, and
999 /// that its operands are legal. Now ensure that the operation itself
1000 /// is legal, recursively ensuring that the operands' operations remain
1002 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
1003 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1006 assert(isTypeLegal(Op.getValueType()) &&
1007 "Caller should expand or promote operands that are not legal!");
1008 SDNode *Node = Op.getNode();
1009 DebugLoc dl = Node->getDebugLoc();
1011 // If this operation defines any values that cannot be represented in a
1012 // register on this target, make sure to expand or promote them.
1013 if (Node->getNumValues() > 1) {
1014 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1015 if (getTypeAction(Node->getValueType(i)) != Legal) {
1016 HandleOp(Op.getValue(i));
1017 assert(LegalizedNodes.count(Op) &&
1018 "Handling didn't add legal operands!");
1019 return LegalizedNodes[Op];
1023 // Note that LegalizeOp may be reentered even from single-use nodes, which
1024 // means that we always must cache transformed nodes.
1025 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1026 if (I != LegalizedNodes.end()) return I->second;
1028 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
1029 SDValue Result = Op;
1030 bool isCustom = false;
1032 switch (Node->getOpcode()) {
1033 case ISD::FrameIndex:
1034 case ISD::EntryToken:
1036 case ISD::BasicBlock:
1037 case ISD::TargetFrameIndex:
1038 case ISD::TargetJumpTable:
1039 case ISD::TargetConstant:
1040 case ISD::TargetConstantFP:
1041 case ISD::TargetConstantPool:
1042 case ISD::TargetGlobalAddress:
1043 case ISD::TargetGlobalTLSAddress:
1044 case ISD::TargetExternalSymbol:
1045 case ISD::VALUETYPE:
1047 case ISD::MEMOPERAND:
1049 case ISD::ARG_FLAGS:
1050 // Primitives must all be legal.
1051 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
1052 "This must be legal!");
1055 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1056 // If this is a target node, legalize it by legalizing the operands then
1057 // passing it through.
1058 SmallVector<SDValue, 8> Ops;
1059 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1060 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1062 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
1064 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1065 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
1066 return Result.getValue(Op.getResNo());
1068 // Otherwise this is an unhandled builtin node. splat.
1070 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
1072 assert(0 && "Do not know how to legalize this operator!");
1074 case ISD::GLOBAL_OFFSET_TABLE:
1075 case ISD::GlobalAddress:
1076 case ISD::GlobalTLSAddress:
1077 case ISD::ExternalSymbol:
1078 case ISD::ConstantPool:
1079 case ISD::JumpTable: // Nothing to do.
1080 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1081 default: assert(0 && "This action is not supported yet!");
1082 case TargetLowering::Custom:
1083 Tmp1 = TLI.LowerOperation(Op, DAG);
1084 if (Tmp1.getNode()) Result = Tmp1;
1085 // FALLTHROUGH if the target doesn't want to lower this op after all.
1086 case TargetLowering::Legal:
1090 case ISD::FRAMEADDR:
1091 case ISD::RETURNADDR:
1092 // The only option for these nodes is to custom lower them. If the target
1093 // does not custom lower them, then return zero.
1094 Tmp1 = TLI.LowerOperation(Op, DAG);
1098 Result = DAG.getConstant(0, TLI.getPointerTy());
1100 case ISD::FRAME_TO_ARGS_OFFSET: {
1101 MVT VT = Node->getValueType(0);
1102 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1103 default: assert(0 && "This action is not supported yet!");
1104 case TargetLowering::Custom:
1105 Result = TLI.LowerOperation(Op, DAG);
1106 if (Result.getNode()) break;
1108 case TargetLowering::Legal:
1109 Result = DAG.getConstant(0, VT);
1114 case ISD::EXCEPTIONADDR: {
1115 Tmp1 = LegalizeOp(Node->getOperand(0));
1116 MVT VT = Node->getValueType(0);
1117 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1118 default: assert(0 && "This action is not supported yet!");
1119 case TargetLowering::Expand: {
1120 unsigned Reg = TLI.getExceptionAddressRegister();
1121 Result = DAG.getCopyFromReg(Tmp1, dl, Reg, VT);
1124 case TargetLowering::Custom:
1125 Result = TLI.LowerOperation(Op, DAG);
1126 if (Result.getNode()) break;
1128 case TargetLowering::Legal: {
1129 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
1130 Result = DAG.getMergeValues(Ops, 2, dl);
1135 if (Result.getNode()->getNumValues() == 1) break;
1137 assert(Result.getNode()->getNumValues() == 2 &&
1138 "Cannot return more than two values!");
1140 // Since we produced two values, make sure to remember that we
1141 // legalized both of them.
1142 Tmp1 = LegalizeOp(Result);
1143 Tmp2 = LegalizeOp(Result.getValue(1));
1144 AddLegalizedOperand(Op.getValue(0), Tmp1);
1145 AddLegalizedOperand(Op.getValue(1), Tmp2);
1146 return Op.getResNo() ? Tmp2 : Tmp1;
1147 case ISD::EHSELECTION: {
1148 Tmp1 = LegalizeOp(Node->getOperand(0));
1149 Tmp2 = LegalizeOp(Node->getOperand(1));
1150 MVT VT = Node->getValueType(0);
1151 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1152 default: assert(0 && "This action is not supported yet!");
1153 case TargetLowering::Expand: {
1154 unsigned Reg = TLI.getExceptionSelectorRegister();
1155 Result = DAG.getCopyFromReg(Tmp2, dl, Reg, VT);
1158 case TargetLowering::Custom:
1159 Result = TLI.LowerOperation(Op, DAG);
1160 if (Result.getNode()) break;
1162 case TargetLowering::Legal: {
1163 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
1164 Result = DAG.getMergeValues(Ops, 2, dl);
1169 if (Result.getNode()->getNumValues() == 1) break;
1171 assert(Result.getNode()->getNumValues() == 2 &&
1172 "Cannot return more than two values!");
1174 // Since we produced two values, make sure to remember that we
1175 // legalized both of them.
1176 Tmp1 = LegalizeOp(Result);
1177 Tmp2 = LegalizeOp(Result.getValue(1));
1178 AddLegalizedOperand(Op.getValue(0), Tmp1);
1179 AddLegalizedOperand(Op.getValue(1), Tmp2);
1180 return Op.getResNo() ? Tmp2 : Tmp1;
1181 case ISD::EH_RETURN: {
1182 MVT VT = Node->getValueType(0);
1183 // The only "good" option for this node is to custom lower it.
1184 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1185 default: assert(0 && "This action is not supported at all!");
1186 case TargetLowering::Custom:
1187 Result = TLI.LowerOperation(Op, DAG);
1188 if (Result.getNode()) break;
1190 case TargetLowering::Legal:
1191 // Target does not know, how to lower this, lower to noop
1192 Result = LegalizeOp(Node->getOperand(0));
1197 case ISD::AssertSext:
1198 case ISD::AssertZext:
1199 Tmp1 = LegalizeOp(Node->getOperand(0));
1200 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1202 case ISD::MERGE_VALUES:
1203 // Legalize eliminates MERGE_VALUES nodes.
1204 Result = Node->getOperand(Op.getResNo());
1206 case ISD::CopyFromReg:
1207 Tmp1 = LegalizeOp(Node->getOperand(0));
1208 Result = Op.getValue(0);
1209 if (Node->getNumValues() == 2) {
1210 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1212 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1213 if (Node->getNumOperands() == 3) {
1214 Tmp2 = LegalizeOp(Node->getOperand(2));
1215 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1217 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1219 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1221 // Since CopyFromReg produces two values, make sure to remember that we
1222 // legalized both of them.
1223 AddLegalizedOperand(Op.getValue(0), Result);
1224 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1225 return Result.getValue(Op.getResNo());
1227 MVT VT = Op.getValueType();
1228 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1229 default: assert(0 && "This action is not supported yet!");
1230 case TargetLowering::Expand:
1232 Result = DAG.getConstant(0, VT);
1233 else if (VT.isFloatingPoint())
1234 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1237 assert(0 && "Unknown value type!");
1239 case TargetLowering::Legal:
1245 case ISD::INTRINSIC_W_CHAIN:
1246 case ISD::INTRINSIC_WO_CHAIN:
1247 case ISD::INTRINSIC_VOID: {
1248 SmallVector<SDValue, 8> Ops;
1249 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1250 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1251 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1253 // Allow the target to custom lower its intrinsics if it wants to.
1254 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1255 TargetLowering::Custom) {
1256 Tmp3 = TLI.LowerOperation(Result, DAG);
1257 if (Tmp3.getNode()) Result = Tmp3;
1260 if (Result.getNode()->getNumValues() == 1) break;
1262 // Must have return value and chain result.
1263 assert(Result.getNode()->getNumValues() == 2 &&
1264 "Cannot return more than two values!");
1266 // Since loads produce two values, make sure to remember that we
1267 // legalized both of them.
1268 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1269 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1270 return Result.getValue(Op.getResNo());
1273 case ISD::DBG_STOPPOINT:
1274 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1275 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1277 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1278 case TargetLowering::Promote:
1279 default: assert(0 && "This action is not supported yet!");
1280 case TargetLowering::Expand: {
1281 DwarfWriter *DW = DAG.getDwarfWriter();
1282 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
1284 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
1286 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1287 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
1288 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) {
1289 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit()));
1290 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(),
1293 unsigned Line = DSP->getLine();
1294 unsigned Col = DSP->getColumn();
1297 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
1298 // won't hurt anything.
1300 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1301 DAG.getConstant(Col, MVT::i32),
1302 DAG.getConstant(SrcFile, MVT::i32) };
1303 Result = DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Ops, 4);
1305 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile);
1306 Result = DAG.getLabel(ISD::DBG_LABEL, dl, Tmp1, ID);
1309 Result = Tmp1; // chain
1312 Result = Tmp1; // chain
1316 case TargetLowering::Legal: {
1317 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1318 if (Action == Legal && Tmp1 == Node->getOperand(0))
1321 SmallVector<SDValue, 8> Ops;
1322 Ops.push_back(Tmp1);
1323 if (Action == Legal) {
1324 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1325 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1327 // Otherwise promote them.
1328 Ops.push_back(PromoteOp(Node->getOperand(1)));
1329 Ops.push_back(PromoteOp(Node->getOperand(2)));
1331 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1332 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1333 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1340 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1341 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1342 default: assert(0 && "This action is not supported yet!");
1343 case TargetLowering::Legal:
1344 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1345 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1346 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1347 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1349 case TargetLowering::Expand:
1350 Result = LegalizeOp(Node->getOperand(0));
1355 case ISD::DEBUG_LOC:
1356 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1357 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1358 default: assert(0 && "This action is not supported yet!");
1359 case TargetLowering::Legal: {
1360 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1361 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1362 if (Action == Legal && Tmp1 == Node->getOperand(0))
1364 if (Action == Legal) {
1365 Tmp2 = Node->getOperand(1);
1366 Tmp3 = Node->getOperand(2);
1367 Tmp4 = Node->getOperand(3);
1369 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1370 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1371 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1373 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1379 case ISD::DBG_LABEL:
1381 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1382 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1383 default: assert(0 && "This action is not supported yet!");
1384 case TargetLowering::Legal:
1385 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1386 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1388 case TargetLowering::Expand:
1389 Result = LegalizeOp(Node->getOperand(0));
1395 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1396 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1397 default: assert(0 && "This action is not supported yet!");
1398 case TargetLowering::Legal:
1399 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1400 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1401 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1402 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1403 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1405 case TargetLowering::Expand:
1407 Result = LegalizeOp(Node->getOperand(0));
1412 case ISD::MEMBARRIER: {
1413 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1414 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1415 default: assert(0 && "This action is not supported yet!");
1416 case TargetLowering::Legal: {
1418 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1419 for (int x = 1; x < 6; ++x) {
1420 Ops[x] = Node->getOperand(x);
1421 if (!isTypeLegal(Ops[x].getValueType()))
1422 Ops[x] = PromoteOp(Ops[x]);
1424 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1427 case TargetLowering::Expand:
1428 //There is no libgcc call for this op
1429 Result = Node->getOperand(0); // Noop
1435 case ISD::ATOMIC_CMP_SWAP: {
1436 unsigned int num_operands = 4;
1437 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1439 for (unsigned int x = 0; x < num_operands; ++x)
1440 Ops[x] = LegalizeOp(Node->getOperand(x));
1441 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1443 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1444 default: assert(0 && "This action is not supported yet!");
1445 case TargetLowering::Custom:
1446 Result = TLI.LowerOperation(Result, DAG);
1448 case TargetLowering::Legal:
1451 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1452 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1453 return Result.getValue(Op.getResNo());
1455 case ISD::ATOMIC_LOAD_ADD:
1456 case ISD::ATOMIC_LOAD_SUB:
1457 case ISD::ATOMIC_LOAD_AND:
1458 case ISD::ATOMIC_LOAD_OR:
1459 case ISD::ATOMIC_LOAD_XOR:
1460 case ISD::ATOMIC_LOAD_NAND:
1461 case ISD::ATOMIC_LOAD_MIN:
1462 case ISD::ATOMIC_LOAD_MAX:
1463 case ISD::ATOMIC_LOAD_UMIN:
1464 case ISD::ATOMIC_LOAD_UMAX:
1465 case ISD::ATOMIC_SWAP: {
1466 unsigned int num_operands = 3;
1467 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1469 for (unsigned int x = 0; x < num_operands; ++x)
1470 Ops[x] = LegalizeOp(Node->getOperand(x));
1471 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1473 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1474 default: assert(0 && "This action is not supported yet!");
1475 case TargetLowering::Custom:
1476 Result = TLI.LowerOperation(Result, DAG);
1478 case TargetLowering::Legal:
1481 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1482 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1483 return Result.getValue(Op.getResNo());
1485 case ISD::Constant: {
1486 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1488 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1490 // We know we don't need to expand constants here, constants only have one
1491 // value and we check that it is fine above.
1493 if (opAction == TargetLowering::Custom) {
1494 Tmp1 = TLI.LowerOperation(Result, DAG);
1500 case ISD::ConstantFP: {
1501 // Spill FP immediates to the constant pool if the target cannot directly
1502 // codegen them. Targets often have some immediate values that can be
1503 // efficiently generated into an FP register without a load. We explicitly
1504 // leave these constants as ConstantFP nodes for the target to deal with.
1505 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1507 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1508 default: assert(0 && "This action is not supported yet!");
1509 case TargetLowering::Legal:
1511 case TargetLowering::Custom:
1512 Tmp3 = TLI.LowerOperation(Result, DAG);
1513 if (Tmp3.getNode()) {
1518 case TargetLowering::Expand: {
1519 // Check to see if this FP immediate is already legal.
1520 bool isLegal = false;
1521 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1522 E = TLI.legal_fpimm_end(); I != E; ++I) {
1523 if (CFP->isExactlyValue(*I)) {
1528 // If this is a legal constant, turn it into a TargetConstantFP node.
1531 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1536 case ISD::TokenFactor:
1537 if (Node->getNumOperands() == 2) {
1538 Tmp1 = LegalizeOp(Node->getOperand(0));
1539 Tmp2 = LegalizeOp(Node->getOperand(1));
1540 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1541 } else if (Node->getNumOperands() == 3) {
1542 Tmp1 = LegalizeOp(Node->getOperand(0));
1543 Tmp2 = LegalizeOp(Node->getOperand(1));
1544 Tmp3 = LegalizeOp(Node->getOperand(2));
1545 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1547 SmallVector<SDValue, 8> Ops;
1548 // Legalize the operands.
1549 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1550 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1551 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1555 case ISD::FORMAL_ARGUMENTS:
1557 // The only option for this is to custom lower it.
1558 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1559 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1560 // A call within a calling sequence must be legalized to something
1561 // other than the normal CALLSEQ_END. Violating this gets Legalize
1562 // into an infinite loop.
1563 assert ((!IsLegalizingCall ||
1564 Node->getOpcode() != ISD::CALL ||
1565 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1566 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1568 // The number of incoming and outgoing values should match; unless the final
1569 // outgoing value is a flag.
1570 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1571 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1572 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1574 "Lowering call/formal_arguments produced unexpected # results!");
1576 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1577 // remember that we legalized all of them, so it doesn't get relegalized.
1578 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1579 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1581 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1582 if (Op.getResNo() == i)
1584 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1587 case ISD::EXTRACT_SUBREG: {
1588 Tmp1 = LegalizeOp(Node->getOperand(0));
1589 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1590 assert(idx && "Operand must be a constant");
1591 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1592 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1595 case ISD::INSERT_SUBREG: {
1596 Tmp1 = LegalizeOp(Node->getOperand(0));
1597 Tmp2 = LegalizeOp(Node->getOperand(1));
1598 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1599 assert(idx && "Operand must be a constant");
1600 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1601 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1604 case ISD::BUILD_VECTOR:
1605 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1606 default: assert(0 && "This action is not supported yet!");
1607 case TargetLowering::Custom:
1608 Tmp3 = TLI.LowerOperation(Result, DAG);
1609 if (Tmp3.getNode()) {
1614 case TargetLowering::Expand:
1615 Result = ExpandBUILD_VECTOR(Result.getNode());
1619 case ISD::INSERT_VECTOR_ELT:
1620 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1621 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1623 // The type of the value to insert may not be legal, even though the vector
1624 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1626 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1627 default: assert(0 && "Cannot expand insert element operand");
1628 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1629 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1631 // FIXME: An alternative would be to check to see if the target is not
1632 // going to custom lower this operation, we could bitcast to half elt
1633 // width and perform two inserts at that width, if that is legal.
1634 Tmp2 = Node->getOperand(1);
1637 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1639 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1640 Node->getValueType(0))) {
1641 default: assert(0 && "This action is not supported yet!");
1642 case TargetLowering::Legal:
1644 case TargetLowering::Custom:
1645 Tmp4 = TLI.LowerOperation(Result, DAG);
1646 if (Tmp4.getNode()) {
1651 case TargetLowering::Promote:
1652 // Fall thru for vector case
1653 case TargetLowering::Expand: {
1654 // If the insert index is a constant, codegen this as a scalar_to_vector,
1655 // then a shuffle that inserts it into the right position in the vector.
1656 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1657 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1658 // match the element type of the vector being created.
1659 if (Tmp2.getValueType() ==
1660 Op.getValueType().getVectorElementType()) {
1661 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
1662 Tmp1.getValueType(), Tmp2);
1664 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1666 MVT::getIntVectorWithNumElements(NumElts);
1667 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1669 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1670 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1671 // elt 0 of the RHS.
1672 SmallVector<SDValue, 8> ShufOps;
1673 for (unsigned i = 0; i != NumElts; ++i) {
1674 if (i != InsertPos->getZExtValue())
1675 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1677 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1679 SDValue ShufMask = DAG.getBUILD_VECTOR(ShufMaskVT, dl,
1680 &ShufOps[0], ShufOps.size());
1682 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Tmp1.getValueType(),
1683 Tmp1, ScVec, ShufMask);
1684 Result = LegalizeOp(Result);
1688 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3, dl);
1693 case ISD::SCALAR_TO_VECTOR:
1694 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1695 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1699 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1700 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1701 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1702 Node->getValueType(0))) {
1703 default: assert(0 && "This action is not supported yet!");
1704 case TargetLowering::Legal:
1706 case TargetLowering::Custom:
1707 Tmp3 = TLI.LowerOperation(Result, DAG);
1708 if (Tmp3.getNode()) {
1713 case TargetLowering::Expand:
1714 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1718 case ISD::VECTOR_SHUFFLE:
1719 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1720 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1721 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1723 // Allow targets to custom lower the SHUFFLEs they support.
1724 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1725 default: assert(0 && "Unknown operation action!");
1726 case TargetLowering::Legal:
1727 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1728 "vector shuffle should not be created if not legal!");
1730 case TargetLowering::Custom:
1731 Tmp3 = TLI.LowerOperation(Result, DAG);
1732 if (Tmp3.getNode()) {
1737 case TargetLowering::Expand: {
1738 MVT VT = Node->getValueType(0);
1739 MVT EltVT = VT.getVectorElementType();
1740 MVT PtrVT = TLI.getPointerTy();
1741 SDValue Mask = Node->getOperand(2);
1742 unsigned NumElems = Mask.getNumOperands();
1743 SmallVector<SDValue,8> Ops;
1744 for (unsigned i = 0; i != NumElems; ++i) {
1745 SDValue Arg = Mask.getOperand(i);
1746 if (Arg.getOpcode() == ISD::UNDEF) {
1747 Ops.push_back(DAG.getUNDEF(EltVT));
1749 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1750 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1752 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp1,
1753 DAG.getConstant(Idx, PtrVT)));
1755 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp2,
1756 DAG.getConstant(Idx - NumElems, PtrVT)));
1759 Result = DAG.getBUILD_VECTOR(VT, dl, &Ops[0], Ops.size());
1762 case TargetLowering::Promote: {
1763 // Change base type to a different vector type.
1764 MVT OVT = Node->getValueType(0);
1765 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1767 // Cast the two input vectors.
1768 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1);
1769 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
1771 // Convert the shuffle mask to the right # elements.
1772 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1773 assert(Tmp3.getNode() && "Shuffle not legal?");
1774 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NVT, Tmp1, Tmp2, Tmp3);
1775 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
1781 case ISD::EXTRACT_VECTOR_ELT:
1782 Tmp1 = Node->getOperand(0);
1783 Tmp2 = LegalizeOp(Node->getOperand(1));
1784 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1785 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1788 case ISD::EXTRACT_SUBVECTOR:
1789 Tmp1 = Node->getOperand(0);
1790 Tmp2 = LegalizeOp(Node->getOperand(1));
1791 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1792 Result = ExpandEXTRACT_SUBVECTOR(Result);
1795 case ISD::CONCAT_VECTORS: {
1796 // Use extract/insert/build vector for now. We might try to be
1797 // more clever later.
1798 MVT PtrVT = TLI.getPointerTy();
1799 SmallVector<SDValue, 8> Ops;
1800 unsigned NumOperands = Node->getNumOperands();
1801 for (unsigned i=0; i < NumOperands; ++i) {
1802 SDValue SubOp = Node->getOperand(i);
1803 MVT VVT = SubOp.getNode()->getValueType(0);
1804 MVT EltVT = VVT.getVectorElementType();
1805 unsigned NumSubElem = VVT.getVectorNumElements();
1806 for (unsigned j=0; j < NumSubElem; ++j) {
1807 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1808 DAG.getConstant(j, PtrVT)));
1811 return LegalizeOp(DAG.getBUILD_VECTOR(Node->getValueType(0), dl,
1812 &Ops[0], Ops.size()));
1815 case ISD::CALLSEQ_START: {
1816 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1818 // Recursively Legalize all of the inputs of the call end that do not lead
1819 // to this call start. This ensures that any libcalls that need be inserted
1820 // are inserted *before* the CALLSEQ_START.
1821 IsLegalizingCallArgs = true;
1822 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1823 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1824 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1827 IsLegalizingCallArgs = false;
1829 // Now that we legalized all of the inputs (which may have inserted
1830 // libcalls) create the new CALLSEQ_START node.
1831 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1833 // Merge in the last call, to ensure that this call start after the last
1835 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1836 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1837 Tmp1, LastCALLSEQ_END);
1838 Tmp1 = LegalizeOp(Tmp1);
1841 // Do not try to legalize the target-specific arguments (#1+).
1842 if (Tmp1 != Node->getOperand(0)) {
1843 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1845 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1848 // Remember that the CALLSEQ_START is legalized.
1849 AddLegalizedOperand(Op.getValue(0), Result);
1850 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1851 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1853 // Now that the callseq_start and all of the non-call nodes above this call
1854 // sequence have been legalized, legalize the call itself. During this
1855 // process, no libcalls can/will be inserted, guaranteeing that no calls
1857 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1858 // Note that we are selecting this call!
1859 LastCALLSEQ_END = SDValue(CallEnd, 0);
1860 IsLegalizingCall = true;
1862 // Legalize the call, starting from the CALLSEQ_END.
1863 LegalizeOp(LastCALLSEQ_END);
1864 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1867 case ISD::CALLSEQ_END:
1868 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1869 // will cause this node to be legalized as well as handling libcalls right.
1870 if (LastCALLSEQ_END.getNode() != Node) {
1871 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1872 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1873 assert(I != LegalizedNodes.end() &&
1874 "Legalizing the call start should have legalized this node!");
1878 // Otherwise, the call start has been legalized and everything is going
1879 // according to plan. Just legalize ourselves normally here.
1880 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1881 // Do not try to legalize the target-specific arguments (#1+), except for
1882 // an optional flag input.
1883 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1884 if (Tmp1 != Node->getOperand(0)) {
1885 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1887 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1890 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1891 if (Tmp1 != Node->getOperand(0) ||
1892 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1893 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1896 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1899 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1900 // This finishes up call legalization.
1901 IsLegalizingCall = false;
1903 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1904 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1905 if (Node->getNumValues() == 2)
1906 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1907 return Result.getValue(Op.getResNo());
1908 case ISD::DYNAMIC_STACKALLOC: {
1909 MVT VT = Node->getValueType(0);
1910 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1911 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1912 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1913 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1915 Tmp1 = Result.getValue(0);
1916 Tmp2 = Result.getValue(1);
1917 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1918 default: assert(0 && "This action is not supported yet!");
1919 case TargetLowering::Expand: {
1920 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1921 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1922 " not tell us which reg is the stack pointer!");
1923 SDValue Chain = Tmp1.getOperand(0);
1925 // Chain the dynamic stack allocation so that it doesn't modify the stack
1926 // pointer when other instructions are using the stack.
1927 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1929 SDValue Size = Tmp2.getOperand(1);
1930 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1931 Chain = SP.getValue(1);
1932 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1933 unsigned StackAlign =
1934 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1935 if (Align > StackAlign)
1936 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1937 DAG.getConstant(-(uint64_t)Align, VT));
1938 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1939 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1941 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1942 DAG.getIntPtrConstant(0, true), SDValue());
1944 Tmp1 = LegalizeOp(Tmp1);
1945 Tmp2 = LegalizeOp(Tmp2);
1948 case TargetLowering::Custom:
1949 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1950 if (Tmp3.getNode()) {
1951 Tmp1 = LegalizeOp(Tmp3);
1952 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1955 case TargetLowering::Legal:
1958 // Since this op produce two values, make sure to remember that we
1959 // legalized both of them.
1960 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1961 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1962 return Op.getResNo() ? Tmp2 : Tmp1;
1964 case ISD::INLINEASM: {
1965 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1966 bool Changed = false;
1967 // Legalize all of the operands of the inline asm, in case they are nodes
1968 // that need to be expanded or something. Note we skip the asm string and
1969 // all of the TargetConstant flags.
1970 SDValue Op = LegalizeOp(Ops[0]);
1971 Changed = Op != Ops[0];
1974 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1975 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1976 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3;
1977 for (++i; NumVals; ++i, --NumVals) {
1978 SDValue Op = LegalizeOp(Ops[i]);
1987 Op = LegalizeOp(Ops.back());
1988 Changed |= Op != Ops.back();
1993 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1995 // INLINE asm returns a chain and flag, make sure to add both to the map.
1996 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1997 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1998 return Result.getValue(Op.getResNo());
2001 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2002 // Ensure that libcalls are emitted before a branch.
2003 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2004 Tmp1 = LegalizeOp(Tmp1);
2005 LastCALLSEQ_END = DAG.getEntryNode();
2007 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2010 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2011 // Ensure that libcalls are emitted before a branch.
2012 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2013 Tmp1 = LegalizeOp(Tmp1);
2014 LastCALLSEQ_END = DAG.getEntryNode();
2016 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2017 default: assert(0 && "Indirect target must be legal type (pointer)!");
2019 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2022 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2025 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2026 // Ensure that libcalls are emitted before a branch.
2027 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2028 Tmp1 = LegalizeOp(Tmp1);
2029 LastCALLSEQ_END = DAG.getEntryNode();
2031 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
2032 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2034 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
2035 default: assert(0 && "This action is not supported yet!");
2036 case TargetLowering::Legal: break;
2037 case TargetLowering::Custom:
2038 Tmp1 = TLI.LowerOperation(Result, DAG);
2039 if (Tmp1.getNode()) Result = Tmp1;
2041 case TargetLowering::Expand: {
2042 SDValue Chain = Result.getOperand(0);
2043 SDValue Table = Result.getOperand(1);
2044 SDValue Index = Result.getOperand(2);
2046 MVT PTy = TLI.getPointerTy();
2047 MachineFunction &MF = DAG.getMachineFunction();
2048 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
2049 Index= DAG.getNode(ISD::MUL, dl, PTy,
2050 Index, DAG.getConstant(EntrySize, PTy));
2051 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2053 MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
2054 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
2055 PseudoSourceValue::getJumpTable(), 0, MemVT);
2057 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2058 // For PIC, the sequence is:
2059 // BRIND(load(Jumptable + index) + RelocBase)
2060 // RelocBase can be JumpTable, GOT or some sort of global base.
2061 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
2062 TLI.getPICJumpTableRelocBase(Table, DAG));
2064 Result = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
2069 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2070 // Ensure that libcalls are emitted before a return.
2071 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2072 Tmp1 = LegalizeOp(Tmp1);
2073 LastCALLSEQ_END = DAG.getEntryNode();
2075 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2076 case Expand: assert(0 && "It's impossible to expand bools");
2078 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2081 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
2083 // The top bits of the promoted condition are not necessarily zero, ensure
2084 // that the value is properly zero extended.
2085 unsigned BitWidth = Tmp2.getValueSizeInBits();
2086 if (!DAG.MaskedValueIsZero(Tmp2,
2087 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2088 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, MVT::i1);
2093 // Basic block destination (Op#2) is always legal.
2094 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2096 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
2097 default: assert(0 && "This action is not supported yet!");
2098 case TargetLowering::Legal: break;
2099 case TargetLowering::Custom:
2100 Tmp1 = TLI.LowerOperation(Result, DAG);
2101 if (Tmp1.getNode()) Result = Tmp1;
2103 case TargetLowering::Expand:
2104 // Expand brcond's setcc into its constituent parts and create a BR_CC
2106 if (Tmp2.getOpcode() == ISD::SETCC) {
2107 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
2108 Tmp1, Tmp2.getOperand(2),
2109 Tmp2.getOperand(0), Tmp2.getOperand(1),
2110 Node->getOperand(2));
2112 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
2113 DAG.getCondCode(ISD::SETNE), Tmp2,
2114 DAG.getConstant(0, Tmp2.getValueType()),
2115 Node->getOperand(2));
2121 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2122 // Ensure that libcalls are emitted before a branch.
2123 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2124 Tmp1 = LegalizeOp(Tmp1);
2125 Tmp2 = Node->getOperand(2); // LHS
2126 Tmp3 = Node->getOperand(3); // RHS
2127 Tmp4 = Node->getOperand(1); // CC
2129 LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()),
2130 Tmp2, Tmp3, Tmp4, dl);
2131 LastCALLSEQ_END = DAG.getEntryNode();
2133 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2134 // the LHS is a legal SETCC itself. In this case, we need to compare
2135 // the result against zero to select between true and false values.
2136 if (Tmp3.getNode() == 0) {
2137 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2138 Tmp4 = DAG.getCondCode(ISD::SETNE);
2141 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
2142 Node->getOperand(4));
2144 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
2145 default: assert(0 && "Unexpected action for BR_CC!");
2146 case TargetLowering::Legal: break;
2147 case TargetLowering::Custom:
2148 Tmp4 = TLI.LowerOperation(Result, DAG);
2149 if (Tmp4.getNode()) Result = Tmp4;
2154 LoadSDNode *LD = cast<LoadSDNode>(Node);
2155 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
2156 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
2158 ISD::LoadExtType ExtType = LD->getExtensionType();
2159 if (ExtType == ISD::NON_EXTLOAD) {
2160 MVT VT = Node->getValueType(0);
2161 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2162 Tmp3 = Result.getValue(0);
2163 Tmp4 = Result.getValue(1);
2165 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
2166 default: assert(0 && "This action is not supported yet!");
2167 case TargetLowering::Legal:
2168 // If this is an unaligned load and the target doesn't support it,
2170 if (!TLI.allowsUnalignedMemoryAccesses()) {
2171 unsigned ABIAlignment = TLI.getTargetData()->
2172 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2173 if (LD->getAlignment() < ABIAlignment){
2174 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2176 Tmp3 = Result.getOperand(0);
2177 Tmp4 = Result.getOperand(1);
2178 Tmp3 = LegalizeOp(Tmp3);
2179 Tmp4 = LegalizeOp(Tmp4);
2183 case TargetLowering::Custom:
2184 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
2185 if (Tmp1.getNode()) {
2186 Tmp3 = LegalizeOp(Tmp1);
2187 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2190 case TargetLowering::Promote: {
2191 // Only promote a load of vector type to another.
2192 assert(VT.isVector() && "Cannot promote this load!");
2193 // Change base type to a different vector type.
2194 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
2196 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
2197 LD->getSrcValueOffset(),
2198 LD->isVolatile(), LD->getAlignment());
2199 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
2200 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2204 // Since loads produce two values, make sure to remember that we
2205 // legalized both of them.
2206 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
2207 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
2208 return Op.getResNo() ? Tmp4 : Tmp3;
2210 MVT SrcVT = LD->getMemoryVT();
2211 unsigned SrcWidth = SrcVT.getSizeInBits();
2212 int SVOffset = LD->getSrcValueOffset();
2213 unsigned Alignment = LD->getAlignment();
2214 bool isVolatile = LD->isVolatile();
2216 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
2217 // Some targets pretend to have an i1 loading operation, and actually
2218 // load an i8. This trick is correct for ZEXTLOAD because the top 7
2219 // bits are guaranteed to be zero; it helps the optimizers understand
2220 // that these bits are zero. It is also useful for EXTLOAD, since it
2221 // tells the optimizers that those bits are undefined. It would be
2222 // nice to have an effective generic way of getting these benefits...
2223 // Until such a way is found, don't insist on promoting i1 here.
2224 (SrcVT != MVT::i1 ||
2225 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2226 // Promote to a byte-sized load if not loading an integral number of
2227 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2228 unsigned NewWidth = SrcVT.getStoreSizeInBits();
2229 MVT NVT = MVT::getIntegerVT(NewWidth);
2232 // The extra bits are guaranteed to be zero, since we stored them that
2233 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2235 ISD::LoadExtType NewExtType =
2236 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2238 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
2239 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2240 NVT, isVolatile, Alignment);
2242 Ch = Result.getValue(1); // The chain.
2244 if (ExtType == ISD::SEXTLOAD)
2245 // Having the top bits zero doesn't help when sign extending.
2246 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
2247 Result.getValueType(),
2248 Result, DAG.getValueType(SrcVT));
2249 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2250 // All the top bits are guaranteed to be zero - inform the optimizers.
2251 Result = DAG.getNode(ISD::AssertZext, dl,
2252 Result.getValueType(), Result,
2253 DAG.getValueType(SrcVT));
2255 Tmp1 = LegalizeOp(Result);
2256 Tmp2 = LegalizeOp(Ch);
2257 } else if (SrcWidth & (SrcWidth - 1)) {
2258 // If not loading a power-of-2 number of bits, expand as two loads.
2259 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2260 "Unsupported extload!");
2261 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2262 assert(RoundWidth < SrcWidth);
2263 unsigned ExtraWidth = SrcWidth - RoundWidth;
2264 assert(ExtraWidth < RoundWidth);
2265 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2266 "Load size not an integral number of bytes!");
2267 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2268 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2270 unsigned IncrementSize;
2272 if (TLI.isLittleEndian()) {
2273 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2274 // Load the bottom RoundWidth bits.
2275 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
2276 Node->getValueType(0), Tmp1, Tmp2,
2277 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2280 // Load the remaining ExtraWidth bits.
2281 IncrementSize = RoundWidth / 8;
2282 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2283 DAG.getIntPtrConstant(IncrementSize));
2284 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
2285 LD->getSrcValue(), SVOffset + IncrementSize,
2286 ExtraVT, isVolatile,
2287 MinAlign(Alignment, IncrementSize));
2289 // Build a factor node to remember that this load is independent of the
2291 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2294 // Move the top bits to the right place.
2295 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
2296 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2298 // Join the hi and lo parts.
2299 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
2301 // Big endian - avoid unaligned loads.
2302 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2303 // Load the top RoundWidth bits.
2304 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
2305 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2308 // Load the remaining ExtraWidth bits.
2309 IncrementSize = RoundWidth / 8;
2310 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2311 DAG.getIntPtrConstant(IncrementSize));
2312 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
2313 Node->getValueType(0), Tmp1, Tmp2,
2314 LD->getSrcValue(), SVOffset + IncrementSize,
2315 ExtraVT, isVolatile,
2316 MinAlign(Alignment, IncrementSize));
2318 // Build a factor node to remember that this load is independent of the
2320 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2323 // Move the top bits to the right place.
2324 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
2325 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2327 // Join the hi and lo parts.
2328 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
2331 Tmp1 = LegalizeOp(Result);
2332 Tmp2 = LegalizeOp(Ch);
2334 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
2335 default: assert(0 && "This action is not supported yet!");
2336 case TargetLowering::Custom:
2339 case TargetLowering::Legal:
2340 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2341 Tmp1 = Result.getValue(0);
2342 Tmp2 = Result.getValue(1);
2345 Tmp3 = TLI.LowerOperation(Result, DAG);
2346 if (Tmp3.getNode()) {
2347 Tmp1 = LegalizeOp(Tmp3);
2348 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2351 // If this is an unaligned load and the target doesn't support it,
2353 if (!TLI.allowsUnalignedMemoryAccesses()) {
2354 unsigned ABIAlignment = TLI.getTargetData()->
2355 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2356 if (LD->getAlignment() < ABIAlignment){
2357 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2359 Tmp1 = Result.getOperand(0);
2360 Tmp2 = Result.getOperand(1);
2361 Tmp1 = LegalizeOp(Tmp1);
2362 Tmp2 = LegalizeOp(Tmp2);
2367 case TargetLowering::Expand:
2368 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2369 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2370 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
2371 LD->getSrcValueOffset(),
2372 LD->isVolatile(), LD->getAlignment());
2373 Result = DAG.getNode(ISD::FP_EXTEND, dl,
2374 Node->getValueType(0), Load);
2375 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2376 Tmp2 = LegalizeOp(Load.getValue(1));
2379 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2380 // Turn the unsupported load into an EXTLOAD followed by an explicit
2381 // zero/sign extend inreg.
2382 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
2383 Tmp1, Tmp2, LD->getSrcValue(),
2384 LD->getSrcValueOffset(), SrcVT,
2385 LD->isVolatile(), LD->getAlignment());
2387 if (ExtType == ISD::SEXTLOAD)
2388 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
2389 Result.getValueType(),
2390 Result, DAG.getValueType(SrcVT));
2392 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
2393 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2394 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2399 // Since loads produce two values, make sure to remember that we legalized
2401 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2402 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2403 return Op.getResNo() ? Tmp2 : Tmp1;
2406 case ISD::EXTRACT_ELEMENT: {
2407 MVT OpTy = Node->getOperand(0).getValueType();
2408 switch (getTypeAction(OpTy)) {
2409 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2411 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2413 Result = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2414 DAG.getConstant(OpTy.getSizeInBits()/2,
2415 TLI.getShiftAmountTy()));
2416 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Result);
2419 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2420 Node->getOperand(0));
2424 // Get both the low and high parts.
2425 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2426 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2427 Result = Tmp2; // 1 -> Hi
2429 Result = Tmp1; // 0 -> Lo
2435 case ISD::CopyToReg:
2436 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2438 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2439 "Register type must be legal!");
2440 // Legalize the incoming value (must be a legal type).
2441 Tmp2 = LegalizeOp(Node->getOperand(2));
2442 if (Node->getNumValues() == 1) {
2443 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2445 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2446 if (Node->getNumOperands() == 4) {
2447 Tmp3 = LegalizeOp(Node->getOperand(3));
2448 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2451 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2454 // Since this produces two values, make sure to remember that we legalized
2456 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2457 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2463 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2465 // Ensure that libcalls are emitted before a return.
2466 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2467 Tmp1 = LegalizeOp(Tmp1);
2468 LastCALLSEQ_END = DAG.getEntryNode();
2470 switch (Node->getNumOperands()) {
2472 Tmp2 = Node->getOperand(1);
2473 Tmp3 = Node->getOperand(2); // Signness
2474 switch (getTypeAction(Tmp2.getValueType())) {
2476 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2479 if (!Tmp2.getValueType().isVector()) {
2481 ExpandOp(Tmp2, Lo, Hi);
2483 // Big endian systems want the hi reg first.
2484 if (TLI.isBigEndian())
2488 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2489 Tmp1, Lo, Tmp3, Hi,Tmp3);
2491 Result = DAG.getNode(ISD::RET, dl, MVT::Other, Tmp1, Lo, Tmp3);
2492 Result = LegalizeOp(Result);
2494 SDNode *InVal = Tmp2.getNode();
2495 int InIx = Tmp2.getResNo();
2496 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2497 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2499 // Figure out if there is a simple type corresponding to this Vector
2500 // type. If so, convert to the vector type.
2501 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2502 if (TLI.isTypeLegal(TVT)) {
2503 // Turn this into a return of the vector type.
2504 Tmp2 = LegalizeOp(Tmp2);
2505 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2506 } else if (NumElems == 1) {
2507 // Turn this into a return of the scalar type.
2508 Tmp2 = ScalarizeVectorOp(Tmp2);
2509 Tmp2 = LegalizeOp(Tmp2);
2510 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2512 // FIXME: Returns of gcc generic vectors smaller than a legal type
2513 // should be returned in integer registers!
2515 // The scalarized value type may not be legal, e.g. it might require
2516 // promotion or expansion. Relegalize the return.
2517 Result = LegalizeOp(Result);
2519 // FIXME: Returns of gcc generic vectors larger than a legal vector
2520 // type should be returned by reference!
2522 SplitVectorOp(Tmp2, Lo, Hi);
2523 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2524 Tmp1, Lo, Tmp3, Hi,Tmp3);
2525 Result = LegalizeOp(Result);
2530 Tmp2 = PromoteOp(Node->getOperand(1));
2531 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2532 Result = LegalizeOp(Result);
2537 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2539 default: { // ret <values>
2540 SmallVector<SDValue, 8> NewValues;
2541 NewValues.push_back(Tmp1);
2542 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2543 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2545 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2546 NewValues.push_back(Node->getOperand(i+1));
2550 assert(!Node->getOperand(i).getValueType().isExtended() &&
2551 "FIXME: TODO: implement returning non-legal vector types!");
2552 ExpandOp(Node->getOperand(i), Lo, Hi);
2553 NewValues.push_back(Lo);
2554 NewValues.push_back(Node->getOperand(i+1));
2556 NewValues.push_back(Hi);
2557 NewValues.push_back(Node->getOperand(i+1));
2562 assert(0 && "Can't promote multiple return value yet!");
2565 if (NewValues.size() == Node->getNumOperands())
2566 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2568 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2569 &NewValues[0], NewValues.size());
2574 if (Result.getOpcode() == ISD::RET) {
2575 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2576 default: assert(0 && "This action is not supported yet!");
2577 case TargetLowering::Legal: break;
2578 case TargetLowering::Custom:
2579 Tmp1 = TLI.LowerOperation(Result, DAG);
2580 if (Tmp1.getNode()) Result = Tmp1;
2586 StoreSDNode *ST = cast<StoreSDNode>(Node);
2587 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2588 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2589 int SVOffset = ST->getSrcValueOffset();
2590 unsigned Alignment = ST->getAlignment();
2591 bool isVolatile = ST->isVolatile();
2593 if (!ST->isTruncatingStore()) {
2594 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2595 // FIXME: We shouldn't do this for TargetConstantFP's.
2596 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2597 // to phase ordering between legalized code and the dag combiner. This
2598 // probably means that we need to integrate dag combiner and legalizer
2600 // We generally can't do this one for long doubles.
2601 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2602 if (CFP->getValueType(0) == MVT::f32 &&
2603 getTypeAction(MVT::i32) == Legal) {
2604 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2605 bitcastToAPInt().zextOrTrunc(32),
2607 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2608 SVOffset, isVolatile, Alignment);
2610 } else if (CFP->getValueType(0) == MVT::f64) {
2611 // If this target supports 64-bit registers, do a single 64-bit store.
2612 if (getTypeAction(MVT::i64) == Legal) {
2613 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
2614 zextOrTrunc(64), MVT::i64);
2615 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2616 SVOffset, isVolatile, Alignment);
2618 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2619 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2620 // stores. If the target supports neither 32- nor 64-bits, this
2621 // xform is certainly not worth it.
2622 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
2623 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2624 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2625 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2627 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
2628 SVOffset, isVolatile, Alignment);
2629 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2630 DAG.getIntPtrConstant(4));
2631 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2632 isVolatile, MinAlign(Alignment, 4U));
2634 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2640 switch (getTypeAction(ST->getMemoryVT())) {
2642 Tmp3 = LegalizeOp(ST->getValue());
2643 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2646 MVT VT = Tmp3.getValueType();
2647 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2648 default: assert(0 && "This action is not supported yet!");
2649 case TargetLowering::Legal:
2650 // If this is an unaligned store and the target doesn't support it,
2652 if (!TLI.allowsUnalignedMemoryAccesses()) {
2653 unsigned ABIAlignment = TLI.getTargetData()->
2654 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2655 if (ST->getAlignment() < ABIAlignment)
2656 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2660 case TargetLowering::Custom:
2661 Tmp1 = TLI.LowerOperation(Result, DAG);
2662 if (Tmp1.getNode()) Result = Tmp1;
2664 case TargetLowering::Promote:
2665 assert(VT.isVector() && "Unknown legal promote case!");
2666 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
2667 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2668 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
2669 ST->getSrcValue(), SVOffset, isVolatile,
2676 if (!ST->getMemoryVT().isVector()) {
2677 // Truncate the value and store the result.
2678 Tmp3 = PromoteOp(ST->getValue());
2679 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2680 SVOffset, ST->getMemoryVT(),
2681 isVolatile, Alignment);
2684 // Fall thru to expand for vector
2686 unsigned IncrementSize = 0;
2689 // If this is a vector type, then we have to calculate the increment as
2690 // the product of the element size in bytes, and the number of elements
2691 // in the high half of the vector.
2692 if (ST->getValue().getValueType().isVector()) {
2693 SDNode *InVal = ST->getValue().getNode();
2694 int InIx = ST->getValue().getResNo();
2695 MVT InVT = InVal->getValueType(InIx);
2696 unsigned NumElems = InVT.getVectorNumElements();
2697 MVT EVT = InVT.getVectorElementType();
2699 // Figure out if there is a simple type corresponding to this Vector
2700 // type. If so, convert to the vector type.
2701 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2702 if (TLI.isTypeLegal(TVT)) {
2703 // Turn this into a normal store of the vector type.
2704 Tmp3 = LegalizeOp(ST->getValue());
2705 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2706 SVOffset, isVolatile, Alignment);
2707 Result = LegalizeOp(Result);
2709 } else if (NumElems == 1) {
2710 // Turn this into a normal store of the scalar type.
2711 Tmp3 = ScalarizeVectorOp(ST->getValue());
2712 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2713 SVOffset, isVolatile, Alignment);
2714 // The scalarized value type may not be legal, e.g. it might require
2715 // promotion or expansion. Relegalize the scalar store.
2716 Result = LegalizeOp(Result);
2719 // Check if we have widen this node with another value
2720 std::map<SDValue, SDValue>::iterator I =
2721 WidenNodes.find(ST->getValue());
2722 if (I != WidenNodes.end()) {
2723 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2);
2727 SplitVectorOp(ST->getValue(), Lo, Hi);
2728 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2729 EVT.getSizeInBits()/8;
2733 ExpandOp(ST->getValue(), Lo, Hi);
2734 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2736 if (Hi.getNode() && TLI.isBigEndian())
2740 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
2741 SVOffset, isVolatile, Alignment);
2743 if (Hi.getNode() == NULL) {
2744 // Must be int <-> float one-to-one expansion.
2749 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2750 DAG.getIntPtrConstant(IncrementSize));
2751 assert(isTypeLegal(Tmp2.getValueType()) &&
2752 "Pointers must be legal!");
2753 SVOffset += IncrementSize;
2754 Alignment = MinAlign(Alignment, IncrementSize);
2755 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2756 SVOffset, isVolatile, Alignment);
2757 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2762 switch (getTypeAction(ST->getValue().getValueType())) {
2764 Tmp3 = LegalizeOp(ST->getValue());
2767 if (!ST->getValue().getValueType().isVector()) {
2768 // We can promote the value, the truncstore will still take care of it.
2769 Tmp3 = PromoteOp(ST->getValue());
2772 // Vector case falls through to expand
2774 // Just store the low part. This may become a non-trunc store, so make
2775 // sure to use getTruncStore, not UpdateNodeOperands below.
2776 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2777 return DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2778 SVOffset, MVT::i8, isVolatile, Alignment);
2781 MVT StVT = ST->getMemoryVT();
2782 unsigned StWidth = StVT.getSizeInBits();
2784 if (StWidth != StVT.getStoreSizeInBits()) {
2785 // Promote to a byte-sized store with upper bits zero if not
2786 // storing an integral number of bytes. For example, promote
2787 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2788 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2789 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
2790 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2791 SVOffset, NVT, isVolatile, Alignment);
2792 } else if (StWidth & (StWidth - 1)) {
2793 // If not storing a power-of-2 number of bits, expand as two stores.
2794 assert(StVT.isExtended() && !StVT.isVector() &&
2795 "Unsupported truncstore!");
2796 unsigned RoundWidth = 1 << Log2_32(StWidth);
2797 assert(RoundWidth < StWidth);
2798 unsigned ExtraWidth = StWidth - RoundWidth;
2799 assert(ExtraWidth < RoundWidth);
2800 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2801 "Store size not an integral number of bytes!");
2802 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2803 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2805 unsigned IncrementSize;
2807 if (TLI.isLittleEndian()) {
2808 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2809 // Store the bottom RoundWidth bits.
2810 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2812 isVolatile, Alignment);
2814 // Store the remaining ExtraWidth bits.
2815 IncrementSize = RoundWidth / 8;
2816 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2817 DAG.getIntPtrConstant(IncrementSize));
2818 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
2819 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2820 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2821 SVOffset + IncrementSize, ExtraVT, isVolatile,
2822 MinAlign(Alignment, IncrementSize));
2824 // Big endian - avoid unaligned stores.
2825 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2826 // Store the top RoundWidth bits.
2827 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
2828 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2829 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2830 SVOffset, RoundVT, isVolatile, Alignment);
2832 // Store the remaining ExtraWidth bits.
2833 IncrementSize = RoundWidth / 8;
2834 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2835 DAG.getIntPtrConstant(IncrementSize));
2836 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2837 SVOffset + IncrementSize, ExtraVT, isVolatile,
2838 MinAlign(Alignment, IncrementSize));
2841 // The order of the stores doesn't matter.
2842 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2844 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2845 Tmp2 != ST->getBasePtr())
2846 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2849 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2850 default: assert(0 && "This action is not supported yet!");
2851 case TargetLowering::Legal:
2852 // If this is an unaligned store and the target doesn't support it,
2854 if (!TLI.allowsUnalignedMemoryAccesses()) {
2855 unsigned ABIAlignment = TLI.getTargetData()->
2856 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2857 if (ST->getAlignment() < ABIAlignment)
2858 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2862 case TargetLowering::Custom:
2863 Result = TLI.LowerOperation(Result, DAG);
2866 // TRUNCSTORE:i16 i32 -> STORE i16
2867 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2868 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
2869 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2870 SVOffset, isVolatile, Alignment);
2878 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2879 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2881 case ISD::STACKSAVE:
2882 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2883 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2884 Tmp1 = Result.getValue(0);
2885 Tmp2 = Result.getValue(1);
2887 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2888 default: assert(0 && "This action is not supported yet!");
2889 case TargetLowering::Legal: break;
2890 case TargetLowering::Custom:
2891 Tmp3 = TLI.LowerOperation(Result, DAG);
2892 if (Tmp3.getNode()) {
2893 Tmp1 = LegalizeOp(Tmp3);
2894 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2897 case TargetLowering::Expand:
2898 // Expand to CopyFromReg if the target set
2899 // StackPointerRegisterToSaveRestore.
2900 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2901 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), dl, SP,
2902 Node->getValueType(0));
2903 Tmp2 = Tmp1.getValue(1);
2905 Tmp1 = DAG.getUNDEF(Node->getValueType(0));
2906 Tmp2 = Node->getOperand(0);
2911 // Since stacksave produce two values, make sure to remember that we
2912 // legalized both of them.
2913 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2914 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2915 return Op.getResNo() ? Tmp2 : Tmp1;
2917 case ISD::STACKRESTORE:
2918 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2919 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2920 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2922 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2923 default: assert(0 && "This action is not supported yet!");
2924 case TargetLowering::Legal: break;
2925 case TargetLowering::Custom:
2926 Tmp1 = TLI.LowerOperation(Result, DAG);
2927 if (Tmp1.getNode()) Result = Tmp1;
2929 case TargetLowering::Expand:
2930 // Expand to CopyToReg if the target set
2931 // StackPointerRegisterToSaveRestore.
2932 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2933 Result = DAG.getCopyToReg(Tmp1, dl, SP, Tmp2);
2941 case ISD::READCYCLECOUNTER:
2942 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2943 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2944 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2945 Node->getValueType(0))) {
2946 default: assert(0 && "This action is not supported yet!");
2947 case TargetLowering::Legal:
2948 Tmp1 = Result.getValue(0);
2949 Tmp2 = Result.getValue(1);
2951 case TargetLowering::Custom:
2952 Result = TLI.LowerOperation(Result, DAG);
2953 Tmp1 = LegalizeOp(Result.getValue(0));
2954 Tmp2 = LegalizeOp(Result.getValue(1));
2958 // Since rdcc produce two values, make sure to remember that we legalized
2960 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2961 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2965 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2966 case Expand: assert(0 && "It's impossible to expand bools");
2968 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2971 assert(!Node->getOperand(0).getValueType().isVector() && "not possible");
2972 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2973 // Make sure the condition is either zero or one.
2974 unsigned BitWidth = Tmp1.getValueSizeInBits();
2975 if (!DAG.MaskedValueIsZero(Tmp1,
2976 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2977 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, MVT::i1);
2981 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2982 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2984 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2986 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2987 default: assert(0 && "This action is not supported yet!");
2988 case TargetLowering::Legal: break;
2989 case TargetLowering::Custom: {
2990 Tmp1 = TLI.LowerOperation(Result, DAG);
2991 if (Tmp1.getNode()) Result = Tmp1;
2994 case TargetLowering::Expand:
2995 if (Tmp1.getOpcode() == ISD::SETCC) {
2996 Result = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
2998 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3000 Result = DAG.getSelectCC(dl, Tmp1,
3001 DAG.getConstant(0, Tmp1.getValueType()),
3002 Tmp2, Tmp3, ISD::SETNE);
3005 case TargetLowering::Promote: {
3007 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
3008 unsigned ExtOp, TruncOp;
3009 if (Tmp2.getValueType().isVector()) {
3010 ExtOp = ISD::BIT_CONVERT;
3011 TruncOp = ISD::BIT_CONVERT;
3012 } else if (Tmp2.getValueType().isInteger()) {
3013 ExtOp = ISD::ANY_EXTEND;
3014 TruncOp = ISD::TRUNCATE;
3016 ExtOp = ISD::FP_EXTEND;
3017 TruncOp = ISD::FP_ROUND;
3019 // Promote each of the values to the new type.
3020 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Tmp2);
3021 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Tmp3);
3022 // Perform the larger operation, then round down.
3023 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2,Tmp3);
3024 if (TruncOp != ISD::FP_ROUND)
3025 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result);
3027 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result,
3028 DAG.getIntPtrConstant(0));
3033 case ISD::SELECT_CC: {
3034 Tmp1 = Node->getOperand(0); // LHS
3035 Tmp2 = Node->getOperand(1); // RHS
3036 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
3037 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
3038 SDValue CC = Node->getOperand(4);
3040 LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()),
3041 Tmp1, Tmp2, CC, dl);
3043 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
3044 // the LHS is a legal SETCC itself. In this case, we need to compare
3045 // the result against zero to select between true and false values.
3046 if (Tmp2.getNode() == 0) {
3047 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3048 CC = DAG.getCondCode(ISD::SETNE);
3050 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
3052 // Everything is legal, see if we should expand this op or something.
3053 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
3054 default: assert(0 && "This action is not supported yet!");
3055 case TargetLowering::Legal: break;
3056 case TargetLowering::Custom:
3057 Tmp1 = TLI.LowerOperation(Result, DAG);
3058 if (Tmp1.getNode()) Result = Tmp1;
3064 Tmp1 = Node->getOperand(0);
3065 Tmp2 = Node->getOperand(1);
3066 Tmp3 = Node->getOperand(2);
3067 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3069 // If we had to Expand the SetCC operands into a SELECT node, then it may
3070 // not always be possible to return a true LHS & RHS. In this case, just
3071 // return the value we legalized, returned in the LHS
3072 if (Tmp2.getNode() == 0) {
3077 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
3078 default: assert(0 && "Cannot handle this action for SETCC yet!");
3079 case TargetLowering::Custom:
3082 case TargetLowering::Legal:
3083 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3085 Tmp4 = TLI.LowerOperation(Result, DAG);
3086 if (Tmp4.getNode()) Result = Tmp4;
3089 case TargetLowering::Promote: {
3090 // First step, figure out the appropriate operation to use.
3091 // Allow SETCC to not be supported for all legal data types
3092 // Mostly this targets FP
3093 MVT NewInTy = Node->getOperand(0).getValueType();
3094 MVT OldVT = NewInTy; OldVT = OldVT;
3096 // Scan for the appropriate larger type to use.
3098 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
3100 assert(NewInTy.isInteger() == OldVT.isInteger() &&
3101 "Fell off of the edge of the integer world");
3102 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
3103 "Fell off of the edge of the floating point world");
3105 // If the target supports SETCC of this type, use it.
3106 if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy))
3109 if (NewInTy.isInteger())
3110 assert(0 && "Cannot promote Legal Integer SETCC yet");
3112 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1);
3113 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2);
3115 Tmp1 = LegalizeOp(Tmp1);
3116 Tmp2 = LegalizeOp(Tmp2);
3117 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3118 Result = LegalizeOp(Result);
3121 case TargetLowering::Expand:
3122 // Expand a setcc node into a select_cc of the same condition, lhs, and
3123 // rhs that selects between const 1 (true) and const 0 (false).
3124 MVT VT = Node->getValueType(0);
3125 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3126 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3132 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3133 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3134 SDValue CC = Node->getOperand(2);
3136 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
3138 // Everything is legal, see if we should expand this op or something.
3139 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
3140 default: assert(0 && "This action is not supported yet!");
3141 case TargetLowering::Legal: break;
3142 case TargetLowering::Custom:
3143 Tmp1 = TLI.LowerOperation(Result, DAG);
3144 if (Tmp1.getNode()) Result = Tmp1;
3146 case TargetLowering::Expand: {
3147 // Unroll into a nasty set of scalar code for now.
3148 MVT VT = Node->getValueType(0);
3149 unsigned NumElems = VT.getVectorNumElements();
3150 MVT EltVT = VT.getVectorElementType();
3151 MVT TmpEltVT = Tmp1.getValueType().getVectorElementType();
3152 SmallVector<SDValue, 8> Ops(NumElems);
3153 for (unsigned i = 0; i < NumElems; ++i) {
3154 SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT,
3155 Tmp1, DAG.getIntPtrConstant(i));
3156 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
3157 In1, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3159 DAG.getIntPtrConstant(i)),
3161 Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i], DAG.getConstant(
3162 APInt::getAllOnesValue(EltVT.getSizeInBits()),
3163 EltVT), DAG.getConstant(0, EltVT));
3165 Result = DAG.getBUILD_VECTOR(VT, dl, &Ops[0], NumElems);
3172 case ISD::SHL_PARTS:
3173 case ISD::SRA_PARTS:
3174 case ISD::SRL_PARTS: {
3175 SmallVector<SDValue, 8> Ops;
3176 bool Changed = false;
3177 unsigned N = Node->getNumOperands();
3178 for (unsigned i = 0; i + 1 < N; ++i) {
3179 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3180 Changed |= Ops.back() != Node->getOperand(i);
3182 Ops.push_back(LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(N-1))));
3183 Changed |= Ops.back() != Node->getOperand(N-1);
3185 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
3187 switch (TLI.getOperationAction(Node->getOpcode(),
3188 Node->getValueType(0))) {
3189 default: assert(0 && "This action is not supported yet!");
3190 case TargetLowering::Legal: break;
3191 case TargetLowering::Custom:
3192 Tmp1 = TLI.LowerOperation(Result, DAG);
3193 if (Tmp1.getNode()) {
3194 SDValue Tmp2, RetVal(0, 0);
3195 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
3196 Tmp2 = LegalizeOp(Tmp1.getValue(i));
3197 AddLegalizedOperand(SDValue(Node, i), Tmp2);
3198 if (i == Op.getResNo())
3201 assert(RetVal.getNode() && "Illegal result number");
3207 // Since these produce multiple values, make sure to remember that we
3208 // legalized all of them.
3209 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3210 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
3211 return Result.getValue(Op.getResNo());
3233 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3234 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3236 if ((Node->getOpcode() == ISD::SHL ||
3237 Node->getOpcode() == ISD::SRL ||
3238 Node->getOpcode() == ISD::SRA) &&
3239 !Node->getValueType(0).isVector())
3240 Tmp2 = DAG.getShiftAmountOperand(Tmp2);
3242 switch (getTypeAction(Tmp2.getValueType())) {
3243 case Expand: assert(0 && "Not possible");
3245 Tmp2 = LegalizeOp(Tmp2); // Legalize the RHS.
3248 Tmp2 = PromoteOp(Tmp2); // Promote the RHS.
3252 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3254 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3255 default: assert(0 && "BinOp legalize operation not supported");
3256 case TargetLowering::Legal: break;
3257 case TargetLowering::Custom:
3258 Tmp1 = TLI.LowerOperation(Result, DAG);
3259 if (Tmp1.getNode()) {
3263 // Fall through if the custom lower can't deal with the operation
3264 case TargetLowering::Expand: {
3265 MVT VT = Op.getValueType();
3267 // See if multiply or divide can be lowered using two-result operations.
3268 SDVTList VTs = DAG.getVTList(VT, VT);
3269 if (Node->getOpcode() == ISD::MUL) {
3270 // We just need the low half of the multiply; try both the signed
3271 // and unsigned forms. If the target supports both SMUL_LOHI and
3272 // UMUL_LOHI, form a preference by checking which forms of plain
3273 // MULH it supports.
3274 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3275 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3276 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3277 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3278 unsigned OpToUse = 0;
3279 if (HasSMUL_LOHI && !HasMULHS) {
3280 OpToUse = ISD::SMUL_LOHI;
3281 } else if (HasUMUL_LOHI && !HasMULHU) {
3282 OpToUse = ISD::UMUL_LOHI;
3283 } else if (HasSMUL_LOHI) {
3284 OpToUse = ISD::SMUL_LOHI;
3285 } else if (HasUMUL_LOHI) {
3286 OpToUse = ISD::UMUL_LOHI;
3289 Result = SDValue(DAG.getNode(OpToUse, dl, VTs, Tmp1, Tmp2).getNode(),
3294 if (Node->getOpcode() == ISD::MULHS &&
3295 TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
3296 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl,
3297 VTs, Tmp1, Tmp2).getNode(),
3301 if (Node->getOpcode() == ISD::MULHU &&
3302 TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) {
3303 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl,
3304 VTs, Tmp1, Tmp2).getNode(),
3308 if (Node->getOpcode() == ISD::SDIV &&
3309 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
3310 Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
3311 VTs, Tmp1, Tmp2).getNode(),
3315 if (Node->getOpcode() == ISD::UDIV &&
3316 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
3317 Result = SDValue(DAG.getNode(ISD::UDIVREM, dl,
3318 VTs, Tmp1, Tmp2).getNode(),
3323 // Check to see if we have a libcall for this operator.
3324 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3325 bool isSigned = false;
3326 switch (Node->getOpcode()) {
3329 if (VT == MVT::i32) {
3330 LC = Node->getOpcode() == ISD::UDIV
3331 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3332 isSigned = Node->getOpcode() == ISD::SDIV;
3337 LC = RTLIB::MUL_I32;
3338 else if (VT == MVT::i64)
3339 LC = RTLIB::MUL_I64;
3342 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3343 RTLIB::POW_PPCF128);
3346 LC = GetFPLibCall(VT, RTLIB::DIV_F32, RTLIB::DIV_F64, RTLIB::DIV_F80,
3347 RTLIB::DIV_PPCF128);
3351 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3353 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3357 assert(Node->getValueType(0).isVector() &&
3358 "Cannot expand this binary operator!");
3359 // Expand the operation into a bunch of nasty scalar code.
3360 Result = LegalizeOp(UnrollVectorOp(Op));
3363 case TargetLowering::Promote: {
3364 switch (Node->getOpcode()) {
3365 default: assert(0 && "Do not know how to promote this BinOp!");
3369 MVT OVT = Node->getValueType(0);
3370 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3371 assert(OVT.isVector() && "Cannot promote this BinOp!");
3372 // Bit convert each of the values to the new type.
3373 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1);
3374 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
3375 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3376 // Bit convert the result back the original type.
3377 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
3385 case ISD::SMUL_LOHI:
3386 case ISD::UMUL_LOHI:
3389 // These nodes will only be produced by target-specific lowering, so
3390 // they shouldn't be here if they aren't legal.
3391 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3392 "This must be legal!");
3394 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3395 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3396 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3399 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3400 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3401 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3402 case Expand: assert(0 && "Not possible");
3404 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3407 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3411 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3413 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3414 default: assert(0 && "Operation not supported");
3415 case TargetLowering::Custom:
3416 Tmp1 = TLI.LowerOperation(Result, DAG);
3417 if (Tmp1.getNode()) Result = Tmp1;
3419 case TargetLowering::Legal: break;
3420 case TargetLowering::Expand: {
3421 // If this target supports fabs/fneg natively and select is cheap,
3422 // do this efficiently.
3423 if (!TLI.isSelectExpensive() &&
3424 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3425 TargetLowering::Legal &&
3426 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3427 TargetLowering::Legal) {
3428 // Get the sign bit of the RHS.
3430 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3431 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
3432 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(IVT),
3433 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3434 // Get the absolute value of the result.
3435 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
3436 // Select between the nabs and abs value based on the sign bit of
3438 Result = DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
3439 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(),
3442 Result = LegalizeOp(Result);
3446 // Otherwise, do bitwise ops!
3448 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3449 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3450 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), Result);
3451 Result = LegalizeOp(Result);
3459 Tmp1 = LegalizeOp(Node->getOperand(0));
3460 Tmp2 = LegalizeOp(Node->getOperand(1));
3461 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3462 Tmp3 = Result.getValue(0);
3463 Tmp4 = Result.getValue(1);
3465 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3466 default: assert(0 && "This action is not supported yet!");
3467 case TargetLowering::Legal:
3469 case TargetLowering::Custom:
3470 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3471 if (Tmp1.getNode() != NULL) {
3472 Tmp3 = LegalizeOp(Tmp1);
3473 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3477 // Since this produces two values, make sure to remember that we legalized
3479 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3480 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3481 return Op.getResNo() ? Tmp4 : Tmp3;
3485 Tmp1 = LegalizeOp(Node->getOperand(0));
3486 Tmp2 = LegalizeOp(Node->getOperand(1));
3487 Tmp3 = LegalizeOp(Node->getOperand(2));
3488 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3489 Tmp3 = Result.getValue(0);
3490 Tmp4 = Result.getValue(1);
3492 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3493 default: assert(0 && "This action is not supported yet!");
3494 case TargetLowering::Legal:
3496 case TargetLowering::Custom:
3497 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3498 if (Tmp1.getNode() != NULL) {
3499 Tmp3 = LegalizeOp(Tmp1);
3500 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3504 // Since this produces two values, make sure to remember that we legalized
3506 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3507 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3508 return Op.getResNo() ? Tmp4 : Tmp3;
3510 case ISD::BUILD_PAIR: {
3511 MVT PairTy = Node->getValueType(0);
3512 // TODO: handle the case where the Lo and Hi operands are not of legal type
3513 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3514 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3515 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3516 case TargetLowering::Promote:
3517 case TargetLowering::Custom:
3518 assert(0 && "Cannot promote/custom this yet!");
3519 case TargetLowering::Legal:
3520 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3521 Result = DAG.getNode(ISD::BUILD_PAIR, dl, PairTy, Tmp1, Tmp2);
3523 case TargetLowering::Expand:
3524 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Tmp1);
3525 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Tmp2);
3526 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3527 DAG.getConstant(PairTy.getSizeInBits()/2,
3528 TLI.getShiftAmountTy()));
3529 Result = DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2);
3538 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3539 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3541 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3542 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3543 case TargetLowering::Custom:
3546 case TargetLowering::Legal:
3547 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3549 Tmp1 = TLI.LowerOperation(Result, DAG);
3550 if (Tmp1.getNode()) Result = Tmp1;
3553 case TargetLowering::Expand: {
3554 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3555 bool isSigned = DivOpc == ISD::SDIV;
3556 MVT VT = Node->getValueType(0);
3558 // See if remainder can be lowered using two-result operations.
3559 SDVTList VTs = DAG.getVTList(VT, VT);
3560 if (Node->getOpcode() == ISD::SREM &&
3561 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
3562 Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
3563 VTs, Tmp1, Tmp2).getNode(), 1);
3566 if (Node->getOpcode() == ISD::UREM &&
3567 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
3568 Result = SDValue(DAG.getNode(ISD::UDIVREM, dl,
3569 VTs, Tmp1, Tmp2).getNode(), 1);
3573 if (VT.isInteger()) {
3574 if (TLI.getOperationAction(DivOpc, VT) ==
3575 TargetLowering::Legal) {
3577 Result = DAG.getNode(DivOpc, dl, VT, Tmp1, Tmp2);
3578 Result = DAG.getNode(ISD::MUL, dl, VT, Result, Tmp2);
3579 Result = DAG.getNode(ISD::SUB, dl, VT, Tmp1, Result);
3580 } else if (VT.isVector()) {
3581 Result = LegalizeOp(UnrollVectorOp(Op));
3583 assert(VT == MVT::i32 &&
3584 "Cannot expand this binary operator!");
3585 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3586 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3588 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3591 assert(VT.isFloatingPoint() &&
3592 "remainder op must have integer or floating-point type");
3593 if (VT.isVector()) {
3594 Result = LegalizeOp(UnrollVectorOp(Op));
3596 // Floating point mod -> fmod libcall.
3597 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3598 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3600 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3608 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3609 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3611 MVT VT = Node->getValueType(0);
3612 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3613 default: assert(0 && "This action is not supported yet!");
3614 case TargetLowering::Custom:
3617 case TargetLowering::Legal:
3618 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3619 Result = Result.getValue(0);
3620 Tmp1 = Result.getValue(1);
3623 Tmp2 = TLI.LowerOperation(Result, DAG);
3624 if (Tmp2.getNode()) {
3625 Result = LegalizeOp(Tmp2);
3626 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3630 case TargetLowering::Expand: {
3631 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3632 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
3633 // Increment the pointer, VAList, to the next vaarg
3634 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
3635 DAG.getConstant(TLI.getTargetData()->
3636 getTypePaddedSize(VT.getTypeForMVT()),
3637 TLI.getPointerTy()));
3638 // Store the incremented VAList to the legalized pointer
3639 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
3640 // Load the actual argument out of the pointer VAList
3641 Result = DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0);
3642 Tmp1 = LegalizeOp(Result.getValue(1));
3643 Result = LegalizeOp(Result);
3647 // Since VAARG produces two values, make sure to remember that we
3648 // legalized both of them.
3649 AddLegalizedOperand(SDValue(Node, 0), Result);
3650 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3651 return Op.getResNo() ? Tmp1 : Result;
3655 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3656 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3657 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3659 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3660 default: assert(0 && "This action is not supported yet!");
3661 case TargetLowering::Custom:
3664 case TargetLowering::Legal:
3665 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3666 Node->getOperand(3), Node->getOperand(4));
3668 Tmp1 = TLI.LowerOperation(Result, DAG);
3669 if (Tmp1.getNode()) Result = Tmp1;
3672 case TargetLowering::Expand:
3673 // This defaults to loading a pointer from the input and storing it to the
3674 // output, returning the chain.
3675 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3676 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3677 Tmp4 = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp3, VS, 0);
3678 Result = DAG.getStore(Tmp4.getValue(1), dl, Tmp4, Tmp2, VD, 0);
3684 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3685 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3687 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3688 default: assert(0 && "This action is not supported yet!");
3689 case TargetLowering::Custom:
3692 case TargetLowering::Legal:
3693 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3695 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3696 if (Tmp1.getNode()) Result = Tmp1;
3699 case TargetLowering::Expand:
3700 Result = Tmp1; // Default to a no-op, return the chain
3706 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3707 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3709 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3711 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3712 default: assert(0 && "This action is not supported yet!");
3713 case TargetLowering::Legal: break;
3714 case TargetLowering::Custom:
3715 Tmp1 = TLI.LowerOperation(Result, DAG);
3716 if (Tmp1.getNode()) Result = Tmp1;
3723 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3724 Tmp2 = LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(1))); // RHS
3725 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3726 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3728 assert(0 && "ROTL/ROTR legalize operation not supported");
3730 case TargetLowering::Legal:
3732 case TargetLowering::Custom:
3733 Tmp1 = TLI.LowerOperation(Result, DAG);
3734 if (Tmp1.getNode()) Result = Tmp1;
3736 case TargetLowering::Promote:
3737 assert(0 && "Do not know how to promote ROTL/ROTR");
3739 case TargetLowering::Expand:
3740 assert(0 && "Do not know how to expand ROTL/ROTR");
3746 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3747 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3748 case TargetLowering::Custom:
3749 assert(0 && "Cannot custom legalize this yet!");
3750 case TargetLowering::Legal:
3751 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3753 case TargetLowering::Promote: {
3754 MVT OVT = Tmp1.getValueType();
3755 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3756 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3758 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
3759 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3760 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3761 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3764 case TargetLowering::Expand:
3765 Result = ExpandBSWAP(Tmp1, dl);
3773 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3774 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3775 case TargetLowering::Custom:
3776 case TargetLowering::Legal:
3777 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3778 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3779 TargetLowering::Custom) {
3780 Tmp1 = TLI.LowerOperation(Result, DAG);
3781 if (Tmp1.getNode()) {
3786 case TargetLowering::Promote: {
3787 MVT OVT = Tmp1.getValueType();
3788 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3790 // Zero extend the argument.
3791 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
3792 // Perform the larger operation, then subtract if needed.
3793 Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Tmp1);
3794 switch (Node->getOpcode()) {
3799 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3800 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3801 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3803 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3804 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3807 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3808 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3809 DAG.getConstant(NVT.getSizeInBits() -
3810 OVT.getSizeInBits(), NVT));
3815 case TargetLowering::Expand:
3816 Result = ExpandBitCount(Node->getOpcode(), Tmp1, dl);
3836 case ISD::FNEARBYINT:
3837 Tmp1 = LegalizeOp(Node->getOperand(0));
3838 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3839 case TargetLowering::Promote:
3840 case TargetLowering::Custom:
3843 case TargetLowering::Legal:
3844 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3846 Tmp1 = TLI.LowerOperation(Result, DAG);
3847 if (Tmp1.getNode()) Result = Tmp1;
3850 case TargetLowering::Expand:
3851 switch (Node->getOpcode()) {
3852 default: assert(0 && "Unreachable!");
3854 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3855 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3856 Result = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp2, Tmp1);
3859 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3860 MVT VT = Node->getValueType(0);
3861 Tmp2 = DAG.getConstantFP(0.0, VT);
3862 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3863 Tmp1, Tmp2, ISD::SETUGT);
3864 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3865 Result = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3880 case ISD::FNEARBYINT: {
3881 MVT VT = Node->getValueType(0);
3883 // Expand unsupported unary vector operators by unrolling them.
3884 if (VT.isVector()) {
3885 Result = LegalizeOp(UnrollVectorOp(Op));
3889 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3890 switch(Node->getOpcode()) {
3892 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3893 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3896 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3897 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3900 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3901 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3904 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3905 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3908 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3909 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3912 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3913 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3916 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3917 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3920 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3921 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3924 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3925 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3928 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3929 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3932 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3933 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3936 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3937 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3939 case ISD::FNEARBYINT:
3940 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3941 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3944 default: assert(0 && "Unreachable!");
3947 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3955 MVT VT = Node->getValueType(0);
3957 // Expand unsupported unary vector operators by unrolling them.
3958 if (VT.isVector()) {
3959 Result = LegalizeOp(UnrollVectorOp(Op));
3963 // We always lower FPOWI into a libcall. No target support for it yet.
3964 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3965 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3967 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3970 case ISD::BIT_CONVERT:
3971 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3972 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3973 Node->getValueType(0), dl);
3974 } else if (Op.getOperand(0).getValueType().isVector()) {
3975 // The input has to be a vector type, we have to either scalarize it, pack
3976 // it, or convert it based on whether the input vector type is legal.
3977 SDNode *InVal = Node->getOperand(0).getNode();
3978 int InIx = Node->getOperand(0).getResNo();
3979 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3980 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3982 // Figure out if there is a simple type corresponding to this Vector
3983 // type. If so, convert to the vector type.
3984 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3985 if (TLI.isTypeLegal(TVT)) {
3986 // Turn this into a bit convert of the vector input.
3987 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
3988 LegalizeOp(Node->getOperand(0)));
3990 } else if (NumElems == 1) {
3991 // Turn this into a bit convert of the scalar input.
3992 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
3993 ScalarizeVectorOp(Node->getOperand(0)));
3996 // FIXME: UNIMP! Store then reload
3997 assert(0 && "Cast from unsupported vector type not implemented yet!");
4000 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
4001 Node->getOperand(0).getValueType())) {
4002 default: assert(0 && "Unknown operation action!");
4003 case TargetLowering::Expand:
4004 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4005 Node->getValueType(0), dl);
4007 case TargetLowering::Legal:
4008 Tmp1 = LegalizeOp(Node->getOperand(0));
4009 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4014 case ISD::CONVERT_RNDSAT: {
4015 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4017 default: assert(0 && "Unknown cvt code!");
4028 SDValue DTyOp = Node->getOperand(1);
4029 SDValue STyOp = Node->getOperand(2);
4030 SDValue RndOp = Node->getOperand(3);
4031 SDValue SatOp = Node->getOperand(4);
4032 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4033 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4035 Tmp1 = LegalizeOp(Node->getOperand(0));
4036 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp,
4038 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4039 TargetLowering::Custom) {
4040 Tmp1 = TLI.LowerOperation(Result, DAG);
4041 if (Tmp1.getNode()) Result = Tmp1;
4045 Result = PromoteOp(Node->getOperand(0));
4046 // For FP, make Op1 a i32
4048 Result = DAG.getConvertRndSat(Op.getValueType(), dl, Result,
4049 DTyOp, STyOp, RndOp, SatOp, CvtCode);
4054 } // end switch CvtCode
4057 // Conversion operators. The source and destination have different types.
4058 case ISD::SINT_TO_FP:
4059 case ISD::UINT_TO_FP: {
4060 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
4061 Result = LegalizeINT_TO_FP(Result, isSigned,
4062 Node->getValueType(0), Node->getOperand(0), dl);
4066 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4068 Tmp1 = LegalizeOp(Node->getOperand(0));
4069 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
4070 default: assert(0 && "Unknown TRUNCATE legalization operation action!");
4071 case TargetLowering::Custom:
4074 case TargetLowering::Legal:
4075 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4077 Tmp1 = TLI.LowerOperation(Result, DAG);
4078 if (Tmp1.getNode()) Result = Tmp1;
4081 case TargetLowering::Expand:
4082 assert(Result.getValueType().isVector() && "must be vector type");
4083 // Unroll the truncate. We should do better.
4084 Result = LegalizeOp(UnrollVectorOp(Result));
4088 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4090 // Since the result is legal, we should just be able to truncate the low
4091 // part of the source.
4092 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
4095 Result = PromoteOp(Node->getOperand(0));
4096 Result = DAG.getNode(ISD::TRUNCATE, dl, Op.getValueType(), Result);
4101 case ISD::FP_TO_SINT:
4102 case ISD::FP_TO_UINT:
4103 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4105 Tmp1 = LegalizeOp(Node->getOperand(0));
4107 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
4108 default: assert(0 && "Unknown operation action!");
4109 case TargetLowering::Custom:
4112 case TargetLowering::Legal:
4113 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4115 Tmp1 = TLI.LowerOperation(Result, DAG);
4116 if (Tmp1.getNode()) Result = Tmp1;
4119 case TargetLowering::Promote:
4120 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
4121 Node->getOpcode() == ISD::FP_TO_SINT,
4124 case TargetLowering::Expand:
4125 if (Node->getOpcode() == ISD::FP_TO_UINT) {
4126 SDValue True, False;
4127 MVT VT = Node->getOperand(0).getValueType();
4128 MVT NVT = Node->getValueType(0);
4129 const uint64_t zero[] = {0, 0};
4130 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
4131 APInt x = APInt::getSignBit(NVT.getSizeInBits());
4132 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
4133 Tmp2 = DAG.getConstantFP(apf, VT);
4134 Tmp3 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
4135 Node->getOperand(0),
4137 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
4138 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
4139 DAG.getNode(ISD::FSUB, dl, VT,
4140 Node->getOperand(0), Tmp2));
4141 False = DAG.getNode(ISD::XOR, dl, NVT, False,
4142 DAG.getConstant(x, NVT));
4143 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp3, True, False);
4146 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
4152 MVT VT = Op.getValueType();
4153 MVT OVT = Node->getOperand(0).getValueType();
4154 // Convert ppcf128 to i32
4155 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
4156 if (Node->getOpcode() == ISD::FP_TO_SINT) {
4157 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
4158 Node->getOperand(0), DAG.getValueType(MVT::f64));
4159 Result = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Result,
4160 DAG.getIntPtrConstant(1));
4161 Result = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Result);
4163 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
4164 APFloat apf = APFloat(APInt(128, 2, TwoE31));
4165 Tmp2 = DAG.getConstantFP(apf, OVT);
4166 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
4167 // FIXME: generated code sucks.
4168 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Node->getOperand(0),
4170 DAG.getNode(ISD::ADD, dl, MVT::i32,
4171 DAG.getNode(ISD::FP_TO_SINT, dl, VT,
4172 DAG.getNode(ISD::FSUB, dl, OVT,
4173 Node->getOperand(0), Tmp2)),
4174 DAG.getConstant(0x80000000, MVT::i32)),
4175 DAG.getNode(ISD::FP_TO_SINT, dl, VT,
4176 Node->getOperand(0)),
4177 DAG.getCondCode(ISD::SETGE));
4181 // Convert f32 / f64 to i32 / i64 / i128.
4182 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
4183 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
4184 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
4186 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
4190 Tmp1 = PromoteOp(Node->getOperand(0));
4191 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
4192 Result = LegalizeOp(Result);
4197 case ISD::FP_EXTEND: {
4198 MVT DstVT = Op.getValueType();
4199 MVT SrcVT = Op.getOperand(0).getValueType();
4200 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4201 // The only other way we can lower this is to turn it into a STORE,
4202 // LOAD pair, targetting a temporary location (a stack slot).
4203 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT, dl);
4206 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4207 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4209 Tmp1 = LegalizeOp(Node->getOperand(0));
4210 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4213 Tmp1 = PromoteOp(Node->getOperand(0));
4214 Result = DAG.getNode(ISD::FP_EXTEND, dl, Op.getValueType(), Tmp1);
4219 case ISD::FP_ROUND: {
4220 MVT DstVT = Op.getValueType();
4221 MVT SrcVT = Op.getOperand(0).getValueType();
4222 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4223 if (SrcVT == MVT::ppcf128) {
4225 ExpandOp(Node->getOperand(0), Lo, Result);
4226 // Round it the rest of the way (e.g. to f32) if needed.
4227 if (DstVT!=MVT::f64)
4228 Result = DAG.getNode(ISD::FP_ROUND, dl,
4229 DstVT, Result, Op.getOperand(1));
4232 // The only other way we can lower this is to turn it into a STORE,
4233 // LOAD pair, targetting a temporary location (a stack slot).
4234 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT, dl);
4237 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4238 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4240 Tmp1 = LegalizeOp(Node->getOperand(0));
4241 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4244 Tmp1 = PromoteOp(Node->getOperand(0));
4245 Result = DAG.getNode(ISD::FP_ROUND, dl, Op.getValueType(), Tmp1,
4246 Node->getOperand(1));
4251 case ISD::ANY_EXTEND:
4252 case ISD::ZERO_EXTEND:
4253 case ISD::SIGN_EXTEND:
4254 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4255 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4257 Tmp1 = LegalizeOp(Node->getOperand(0));
4258 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4259 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4260 TargetLowering::Custom) {
4261 Tmp1 = TLI.LowerOperation(Result, DAG);
4262 if (Tmp1.getNode()) Result = Tmp1;
4266 switch (Node->getOpcode()) {
4267 case ISD::ANY_EXTEND:
4268 Tmp1 = PromoteOp(Node->getOperand(0));
4269 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Tmp1);
4271 case ISD::ZERO_EXTEND:
4272 Result = PromoteOp(Node->getOperand(0));
4273 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result);
4274 Result = DAG.getZeroExtendInReg(Result, dl,
4275 Node->getOperand(0).getValueType());
4277 case ISD::SIGN_EXTEND:
4278 Result = PromoteOp(Node->getOperand(0));
4279 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result);
4280 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(),
4282 DAG.getValueType(Node->getOperand(0).getValueType()));
4287 case ISD::FP_ROUND_INREG:
4288 case ISD::SIGN_EXTEND_INREG: {
4289 Tmp1 = LegalizeOp(Node->getOperand(0));
4290 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
4292 // If this operation is not supported, convert it to a shl/shr or load/store
4294 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
4295 default: assert(0 && "This action not supported for this op yet!");
4296 case TargetLowering::Legal:
4297 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4299 case TargetLowering::Expand:
4300 // If this is an integer extend and shifts are supported, do that.
4301 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
4302 // NOTE: we could fall back on load/store here too for targets without
4303 // SAR. However, it is doubtful that any exist.
4304 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
4305 ExtraVT.getSizeInBits();
4306 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
4307 Result = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
4308 Node->getOperand(0), ShiftCst);
4309 Result = DAG.getNode(ISD::SRA, dl, Node->getValueType(0),
4311 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
4312 // The only way we can lower this is to turn it into a TRUNCSTORE,
4313 // EXTLOAD pair, targetting a temporary location (a stack slot).
4315 // NOTE: there is a choice here between constantly creating new stack
4316 // slots and always reusing the same one. We currently always create
4317 // new ones, as reuse may inhibit scheduling.
4318 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
4319 Node->getValueType(0), dl);
4321 assert(0 && "Unknown op");
4327 case ISD::TRAMPOLINE: {
4329 for (unsigned i = 0; i != 6; ++i)
4330 Ops[i] = LegalizeOp(Node->getOperand(i));
4331 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
4332 // The only option for this node is to custom lower it.
4333 Result = TLI.LowerOperation(Result, DAG);
4334 assert(Result.getNode() && "Should always custom lower!");
4336 // Since trampoline produces two values, make sure to remember that we
4337 // legalized both of them.
4338 Tmp1 = LegalizeOp(Result.getValue(1));
4339 Result = LegalizeOp(Result);
4340 AddLegalizedOperand(SDValue(Node, 0), Result);
4341 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
4342 return Op.getResNo() ? Tmp1 : Result;
4344 case ISD::FLT_ROUNDS_: {
4345 MVT VT = Node->getValueType(0);
4346 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4347 default: assert(0 && "This action not supported for this op yet!");
4348 case TargetLowering::Custom:
4349 Result = TLI.LowerOperation(Op, DAG);
4350 if (Result.getNode()) break;
4352 case TargetLowering::Legal:
4353 // If this operation is not supported, lower it to constant 1
4354 Result = DAG.getConstant(1, VT);
4360 MVT VT = Node->getValueType(0);
4361 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4362 default: assert(0 && "This action not supported for this op yet!");
4363 case TargetLowering::Legal:
4364 Tmp1 = LegalizeOp(Node->getOperand(0));
4365 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4367 case TargetLowering::Custom:
4368 Result = TLI.LowerOperation(Op, DAG);
4369 if (Result.getNode()) break;
4371 case TargetLowering::Expand:
4372 // If this operation is not supported, lower it to 'abort()' call
4373 Tmp1 = LegalizeOp(Node->getOperand(0));
4374 TargetLowering::ArgListTy Args;
4375 std::pair<SDValue,SDValue> CallResult =
4376 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4377 false, false, false, false, CallingConv::C, false,
4378 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4380 Result = CallResult.second;
4388 MVT VT = Node->getValueType(0);
4389 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4390 default: assert(0 && "This action not supported for this op yet!");
4391 case TargetLowering::Custom:
4392 Result = TLI.LowerOperation(Op, DAG);
4393 if (Result.getNode()) break;
4395 case TargetLowering::Legal: {
4396 SDValue LHS = LegalizeOp(Node->getOperand(0));
4397 SDValue RHS = LegalizeOp(Node->getOperand(1));
4399 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
4400 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
4402 MVT OType = Node->getValueType(1);
4404 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
4406 // LHSSign -> LHS >= 0
4407 // RHSSign -> RHS >= 0
4408 // SumSign -> Sum >= 0
4411 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4413 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
4415 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
4416 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
4417 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
4418 Node->getOpcode() == ISD::SADDO ?
4419 ISD::SETEQ : ISD::SETNE);
4421 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
4422 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
4424 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
4426 MVT ValueVTs[] = { LHS.getValueType(), OType };
4427 SDValue Ops[] = { Sum, Cmp };
4429 Result = DAG.getNode(ISD::MERGE_VALUES, dl,
4430 DAG.getVTList(&ValueVTs[0], 2),
4432 SDNode *RNode = Result.getNode();
4433 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4434 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4443 MVT VT = Node->getValueType(0);
4444 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4445 default: assert(0 && "This action not supported for this op yet!");
4446 case TargetLowering::Custom:
4447 Result = TLI.LowerOperation(Op, DAG);
4448 if (Result.getNode()) break;
4450 case TargetLowering::Legal: {
4451 SDValue LHS = LegalizeOp(Node->getOperand(0));
4452 SDValue RHS = LegalizeOp(Node->getOperand(1));
4454 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
4455 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
4457 MVT OType = Node->getValueType(1);
4458 SDValue Cmp = DAG.getSetCC(dl, OType, Sum, LHS,
4459 Node->getOpcode () == ISD::UADDO ?
4460 ISD::SETULT : ISD::SETUGT);
4462 MVT ValueVTs[] = { LHS.getValueType(), OType };
4463 SDValue Ops[] = { Sum, Cmp };
4465 Result = DAG.getNode(ISD::MERGE_VALUES, dl,
4466 DAG.getVTList(&ValueVTs[0], 2),
4468 SDNode *RNode = Result.getNode();
4469 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4470 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4479 MVT VT = Node->getValueType(0);
4480 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4481 default: assert(0 && "This action is not supported at all!");
4482 case TargetLowering::Custom:
4483 Result = TLI.LowerOperation(Op, DAG);
4484 if (Result.getNode()) break;
4486 case TargetLowering::Legal:
4487 // FIXME: According to Hacker's Delight, this can be implemented in
4488 // target independent lowering, but it would be inefficient, since it
4489 // requires a division + a branch.
4490 assert(0 && "Target independent lowering is not supported for SMULO/UMULO!");
4498 assert(Result.getValueType() == Op.getValueType() &&
4499 "Bad legalization!");
4501 // Make sure that the generated code is itself legal.
4503 Result = LegalizeOp(Result);
4505 // Note that LegalizeOp may be reentered even from single-use nodes, which
4506 // means that we always must cache transformed nodes.
4507 AddLegalizedOperand(Op, Result);
4511 /// PromoteOp - Given an operation that produces a value in an invalid type,
4512 /// promote it to compute the value into a larger type. The produced value will
4513 /// have the correct bits for the low portion of the register, but no guarantee
4514 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4515 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4516 MVT VT = Op.getValueType();
4517 MVT NVT = TLI.getTypeToTransformTo(VT);
4518 assert(getTypeAction(VT) == Promote &&
4519 "Caller should expand or legalize operands that are not promotable!");
4520 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4521 "Cannot promote to smaller type!");
4523 SDValue Tmp1, Tmp2, Tmp3;
4525 SDNode *Node = Op.getNode();
4526 DebugLoc dl = Node->getDebugLoc();
4528 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4529 if (I != PromotedNodes.end()) return I->second;
4531 switch (Node->getOpcode()) {
4532 case ISD::CopyFromReg:
4533 assert(0 && "CopyFromReg must be legal!");
4536 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4538 assert(0 && "Do not know how to promote this operator!");
4541 Result = DAG.getUNDEF(NVT);
4545 Result = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Op);
4547 Result = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Op);
4548 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4550 case ISD::ConstantFP:
4551 Result = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op);
4552 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4556 MVT VT0 = Node->getOperand(0).getValueType();
4557 assert(isTypeLegal(TLI.getSetCCResultType(VT0))
4558 && "SetCC type is not legal??");
4559 Result = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(VT0),
4560 Node->getOperand(0), Node->getOperand(1),
4561 Node->getOperand(2));
4565 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4567 Result = LegalizeOp(Node->getOperand(0));
4568 assert(Result.getValueType().bitsGE(NVT) &&
4569 "This truncation doesn't make sense!");
4570 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4571 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Result);
4574 // The truncation is not required, because we don't guarantee anything
4575 // about high bits anyway.
4576 Result = PromoteOp(Node->getOperand(0));
4579 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4580 // Truncate the low part of the expanded value to the result type
4581 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Tmp1);
4584 case ISD::SIGN_EXTEND:
4585 case ISD::ZERO_EXTEND:
4586 case ISD::ANY_EXTEND:
4587 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4588 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4590 // Input is legal? Just do extend all the way to the larger type.
4591 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0));
4594 // Promote the reg if it's smaller.
4595 Result = PromoteOp(Node->getOperand(0));
4596 // The high bits are not guaranteed to be anything. Insert an extend.
4597 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4598 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
4599 DAG.getValueType(Node->getOperand(0).getValueType()));
4600 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4601 Result = DAG.getZeroExtendInReg(Result, dl,
4602 Node->getOperand(0).getValueType());
4606 case ISD::CONVERT_RNDSAT: {
4607 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4608 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
4609 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
4610 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
4611 "can only promote integers");
4612 Result = DAG.getConvertRndSat(NVT, dl, Node->getOperand(0),
4613 Node->getOperand(1), Node->getOperand(2),
4614 Node->getOperand(3), Node->getOperand(4),
4619 case ISD::BIT_CONVERT:
4620 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4621 Node->getValueType(0), dl);
4622 Result = PromoteOp(Result);
4625 case ISD::FP_EXTEND:
4626 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4628 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4629 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4630 case Promote: assert(0 && "Unreachable with 2 FP types!");
4632 if (Node->getConstantOperandVal(1) == 0) {
4633 // Input is legal? Do an FP_ROUND_INREG.
4634 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Node->getOperand(0),
4635 DAG.getValueType(VT));
4637 // Just remove the truncate, it isn't affecting the value.
4638 Result = DAG.getNode(ISD::FP_ROUND, dl, NVT, Node->getOperand(0),
4639 Node->getOperand(1));
4644 case ISD::SINT_TO_FP:
4645 case ISD::UINT_TO_FP:
4646 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4648 // No extra round required here.
4649 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0));
4653 Result = PromoteOp(Node->getOperand(0));
4654 if (Node->getOpcode() == ISD::SINT_TO_FP)
4655 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(),
4657 DAG.getValueType(Node->getOperand(0).getValueType()));
4659 Result = DAG.getZeroExtendInReg(Result, dl,
4660 Node->getOperand(0).getValueType());
4661 // No extra round required here.
4662 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Result);
4665 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4666 Node->getOperand(0), dl);
4667 // Round if we cannot tolerate excess precision.
4668 if (NoExcessFPPrecision)
4669 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4670 DAG.getValueType(VT));
4675 case ISD::SIGN_EXTEND_INREG:
4676 Result = PromoteOp(Node->getOperand(0));
4677 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
4678 Node->getOperand(1));
4680 case ISD::FP_TO_SINT:
4681 case ISD::FP_TO_UINT:
4682 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4685 Tmp1 = Node->getOperand(0);
4688 // The input result is prerounded, so we don't have to do anything
4690 Tmp1 = PromoteOp(Node->getOperand(0));
4693 // If we're promoting a UINT to a larger size, check to see if the new node
4694 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4695 // we can use that instead. This allows us to generate better code for
4696 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4697 // legal, such as PowerPC.
4698 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4699 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
4700 (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT) ||
4701 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4702 Result = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Tmp1);
4704 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4710 Tmp1 = PromoteOp(Node->getOperand(0));
4711 assert(Tmp1.getValueType() == NVT);
4712 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4713 // NOTE: we do not have to do any extra rounding here for
4714 // NoExcessFPPrecision, because we know the input will have the appropriate
4715 // precision, and these operations don't modify precision at all.
4730 case ISD::FNEARBYINT:
4731 Tmp1 = PromoteOp(Node->getOperand(0));
4732 assert(Tmp1.getValueType() == NVT);
4733 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4734 if (NoExcessFPPrecision)
4735 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4736 DAG.getValueType(VT));
4741 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4742 // directly as well, which may be better.
4743 Tmp1 = PromoteOp(Node->getOperand(0));
4744 Tmp2 = Node->getOperand(1);
4745 if (Node->getOpcode() == ISD::FPOW)
4746 Tmp2 = PromoteOp(Tmp2);
4747 assert(Tmp1.getValueType() == NVT);
4748 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4749 if (NoExcessFPPrecision)
4750 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4751 DAG.getValueType(VT));
4755 case ISD::ATOMIC_CMP_SWAP: {
4756 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4757 Tmp2 = PromoteOp(Node->getOperand(2));
4758 Tmp3 = PromoteOp(Node->getOperand(3));
4759 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
4760 AtomNode->getChain(),
4761 AtomNode->getBasePtr(), Tmp2, Tmp3,
4762 AtomNode->getSrcValue(),
4763 AtomNode->getAlignment());
4764 // Remember that we legalized the chain.
4765 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4768 case ISD::ATOMIC_LOAD_ADD:
4769 case ISD::ATOMIC_LOAD_SUB:
4770 case ISD::ATOMIC_LOAD_AND:
4771 case ISD::ATOMIC_LOAD_OR:
4772 case ISD::ATOMIC_LOAD_XOR:
4773 case ISD::ATOMIC_LOAD_NAND:
4774 case ISD::ATOMIC_LOAD_MIN:
4775 case ISD::ATOMIC_LOAD_MAX:
4776 case ISD::ATOMIC_LOAD_UMIN:
4777 case ISD::ATOMIC_LOAD_UMAX:
4778 case ISD::ATOMIC_SWAP: {
4779 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4780 Tmp2 = PromoteOp(Node->getOperand(2));
4781 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
4782 AtomNode->getChain(),
4783 AtomNode->getBasePtr(), Tmp2,
4784 AtomNode->getSrcValue(),
4785 AtomNode->getAlignment());
4786 // Remember that we legalized the chain.
4787 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4797 // The input may have strange things in the top bits of the registers, but
4798 // these operations don't care. They may have weird bits going out, but
4799 // that too is okay if they are integer operations.
4800 Tmp1 = PromoteOp(Node->getOperand(0));
4801 Tmp2 = PromoteOp(Node->getOperand(1));
4802 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4803 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4808 Tmp1 = PromoteOp(Node->getOperand(0));
4809 Tmp2 = PromoteOp(Node->getOperand(1));
4810 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4811 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4813 // Floating point operations will give excess precision that we may not be
4814 // able to tolerate. If we DO allow excess precision, just leave it,
4815 // otherwise excise it.
4816 // FIXME: Why would we need to round FP ops more than integer ones?
4817 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4818 if (NoExcessFPPrecision)
4819 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4820 DAG.getValueType(VT));
4825 // These operators require that their input be sign extended.
4826 Tmp1 = PromoteOp(Node->getOperand(0));
4827 Tmp2 = PromoteOp(Node->getOperand(1));
4828 if (NVT.isInteger()) {
4829 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
4830 DAG.getValueType(VT));
4831 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2,
4832 DAG.getValueType(VT));
4834 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4836 // Perform FP_ROUND: this is probably overly pessimistic.
4837 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4838 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4839 DAG.getValueType(VT));
4843 case ISD::FCOPYSIGN:
4844 // These operators require that their input be fp extended.
4845 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4846 case Expand: assert(0 && "not implemented");
4847 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4848 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4850 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4851 case Expand: assert(0 && "not implemented");
4852 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4853 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4855 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4857 // Perform FP_ROUND: this is probably overly pessimistic.
4858 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4859 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4860 DAG.getValueType(VT));
4865 // These operators require that their input be zero extended.
4866 Tmp1 = PromoteOp(Node->getOperand(0));
4867 Tmp2 = PromoteOp(Node->getOperand(1));
4868 assert(NVT.isInteger() && "Operators don't apply to FP!");
4869 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
4870 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT);
4871 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4875 Tmp1 = PromoteOp(Node->getOperand(0));
4876 Result = DAG.getNode(ISD::SHL, dl, NVT, Tmp1, Node->getOperand(1));
4879 // The input value must be properly sign extended.
4880 Tmp1 = PromoteOp(Node->getOperand(0));
4881 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
4882 DAG.getValueType(VT));
4883 Result = DAG.getNode(ISD::SRA, dl, NVT, Tmp1, Node->getOperand(1));
4886 // The input value must be properly zero extended.
4887 Tmp1 = PromoteOp(Node->getOperand(0));
4888 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
4889 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, Node->getOperand(1));
4893 Tmp1 = Node->getOperand(0); // Get the chain.
4894 Tmp2 = Node->getOperand(1); // Get the pointer.
4895 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4896 Tmp3 = DAG.getVAArg(VT, dl, Tmp1, Tmp2, Node->getOperand(2));
4897 Result = TLI.LowerOperation(Tmp3, DAG);
4899 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4900 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
4901 // Increment the pointer, VAList, to the next vaarg
4902 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
4903 DAG.getConstant(VT.getSizeInBits()/8,
4904 TLI.getPointerTy()));
4905 // Store the incremented VAList to the legalized pointer
4906 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
4907 // Load the actual argument out of the pointer VAList
4908 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Tmp3, VAList, NULL, 0, VT);
4910 // Remember that we legalized the chain.
4911 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4915 LoadSDNode *LD = cast<LoadSDNode>(Node);
4916 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4917 ? ISD::EXTLOAD : LD->getExtensionType();
4918 Result = DAG.getExtLoad(ExtType, dl, NVT,
4919 LD->getChain(), LD->getBasePtr(),
4920 LD->getSrcValue(), LD->getSrcValueOffset(),
4923 LD->getAlignment());
4924 // Remember that we legalized the chain.
4925 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4929 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4930 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4932 MVT VT2 = Tmp2.getValueType();
4933 assert(VT2 == Tmp3.getValueType()
4934 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4935 // Ensure that the resulting node is at least the same size as the operands'
4936 // value types, because we cannot assume that TLI.getSetCCValueType() is
4938 Result = DAG.getNode(ISD::SELECT, dl, VT2, Node->getOperand(0), Tmp2, Tmp3);
4941 case ISD::SELECT_CC:
4942 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4943 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4944 Result = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
4945 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4948 Tmp1 = Node->getOperand(0);
4949 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
4950 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4951 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
4952 DAG.getConstant(NVT.getSizeInBits() -
4954 TLI.getShiftAmountTy()));
4959 // Zero extend the argument
4960 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4961 // Perform the larger operation, then subtract if needed.
4962 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4963 switch(Node->getOpcode()) {
4968 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4969 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
4970 DAG.getConstant(NVT.getSizeInBits(), NVT),
4972 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
4973 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4976 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4977 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4978 DAG.getConstant(NVT.getSizeInBits() -
4979 VT.getSizeInBits(), NVT));
4983 case ISD::EXTRACT_SUBVECTOR:
4984 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4986 case ISD::EXTRACT_VECTOR_ELT:
4987 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4991 assert(Result.getNode() && "Didn't set a result!");
4993 // Make sure the result is itself legal.
4994 Result = LegalizeOp(Result);
4996 // Remember that we promoted this!
4997 AddPromotedOperand(Op, Result);
5001 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
5002 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
5003 /// based on the vector type. The return type of this matches the element type
5004 /// of the vector, which may not be legal for the target.
5005 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
5006 // We know that operand #0 is the Vec vector. If the index is a constant
5007 // or if the invec is a supported hardware type, we can use it. Otherwise,
5008 // lower to a store then an indexed load.
5009 SDValue Vec = Op.getOperand(0);
5010 SDValue Idx = Op.getOperand(1);
5011 DebugLoc dl = Op.getDebugLoc();
5013 MVT TVT = Vec.getValueType();
5014 unsigned NumElems = TVT.getVectorNumElements();
5016 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
5017 default: assert(0 && "This action is not supported yet!");
5018 case TargetLowering::Custom: {
5019 Vec = LegalizeOp(Vec);
5020 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5021 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
5026 case TargetLowering::Legal:
5027 if (isTypeLegal(TVT)) {
5028 Vec = LegalizeOp(Vec);
5029 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5033 case TargetLowering::Promote:
5034 assert(TVT.isVector() && "not vector type");
5035 // fall thru to expand since vectors are by default are promote
5036 case TargetLowering::Expand:
5040 if (NumElems == 1) {
5041 // This must be an access of the only element. Return it.
5042 Op = ScalarizeVectorOp(Vec);
5043 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
5044 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
5045 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5047 SplitVectorOp(Vec, Lo, Hi);
5048 if (CIdx->getZExtValue() < NumLoElts) {
5052 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
5053 Idx.getValueType());
5056 // It's now an extract from the appropriate high or low part. Recurse.
5057 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5058 Op = ExpandEXTRACT_VECTOR_ELT(Op);
5060 // Store the value to a temporary stack slot, then LOAD the scalar
5061 // element back out.
5062 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
5063 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
5065 // Add the offset to the index.
5066 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
5067 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
5068 DAG.getConstant(EltSize, Idx.getValueType()));
5070 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
5071 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
5073 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
5075 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
5077 Op = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0);
5082 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
5083 /// we assume the operation can be split if it is not already legal.
5084 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
5085 // We know that operand #0 is the Vec vector. For now we assume the index
5086 // is a constant and that the extracted result is a supported hardware type.
5087 SDValue Vec = Op.getOperand(0);
5088 SDValue Idx = LegalizeOp(Op.getOperand(1));
5090 unsigned NumElems = Vec.getValueType().getVectorNumElements();
5092 if (NumElems == Op.getValueType().getVectorNumElements()) {
5093 // This must be an access of the desired vector length. Return it.
5097 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5099 SplitVectorOp(Vec, Lo, Hi);
5100 if (CIdx->getZExtValue() < NumElems/2) {
5104 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
5105 Idx.getValueType());
5108 // It's now an extract from the appropriate high or low part. Recurse.
5109 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5110 return ExpandEXTRACT_SUBVECTOR(Op);
5113 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
5114 /// with condition CC on the current target. This usually involves legalizing
5115 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
5116 /// there may be no choice but to create a new SetCC node to represent the
5117 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
5118 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
5119 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
5123 SDValue Tmp1, Tmp2, Tmp3, Result;
5125 switch (getTypeAction(LHS.getValueType())) {
5127 Tmp1 = LegalizeOp(LHS); // LHS
5128 Tmp2 = LegalizeOp(RHS); // RHS
5131 Tmp1 = PromoteOp(LHS); // LHS
5132 Tmp2 = PromoteOp(RHS); // RHS
5134 // If this is an FP compare, the operands have already been extended.
5135 if (LHS.getValueType().isInteger()) {
5136 MVT VT = LHS.getValueType();
5137 MVT NVT = TLI.getTypeToTransformTo(VT);
5139 // Otherwise, we have to insert explicit sign or zero extends. Note
5140 // that we could insert sign extends for ALL conditions, but zero extend
5141 // is cheaper on many machines (an AND instead of two shifts), so prefer
5143 switch (cast<CondCodeSDNode>(CC)->get()) {
5144 default: assert(0 && "Unknown integer comparison!");
5151 // ALL of these operations will work if we either sign or zero extend
5152 // the operands (including the unsigned comparisons!). Zero extend is
5153 // usually a simpler/cheaper operation, so prefer it.
5154 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
5155 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT);
5161 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
5162 DAG.getValueType(VT));
5163 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2,
5164 DAG.getValueType(VT));
5165 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
5166 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
5172 MVT VT = LHS.getValueType();
5173 if (VT == MVT::f32 || VT == MVT::f64) {
5174 // Expand into one or more soft-fp libcall(s).
5175 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
5176 switch (cast<CondCodeSDNode>(CC)->get()) {
5179 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5183 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
5187 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5191 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5195 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5199 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5202 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5205 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
5208 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5209 switch (cast<CondCodeSDNode>(CC)->get()) {
5211 // SETONE = SETOLT | SETOGT
5212 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5215 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5218 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5221 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5224 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5227 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5229 default: assert(0 && "Unsupported FP setcc!");
5234 SDValue Ops[2] = { LHS, RHS };
5235 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2, dl).getNode(),
5236 false /*sign irrelevant*/, Dummy);
5237 Tmp2 = DAG.getConstant(0, MVT::i32);
5238 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
5239 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
5240 Tmp1 = DAG.getNode(ISD::SETCC, dl,
5241 TLI.getSetCCResultType(Tmp1.getValueType()),
5243 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2, dl).getNode(),
5244 false /*sign irrelevant*/, Dummy);
5245 Tmp2 = DAG.getNode(ISD::SETCC, dl,
5246 TLI.getSetCCResultType(LHS.getValueType()), LHS,
5247 Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
5248 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5251 LHS = LegalizeOp(Tmp1);
5256 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5257 ExpandOp(LHS, LHSLo, LHSHi);
5258 ExpandOp(RHS, RHSLo, RHSHi);
5259 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5261 if (VT==MVT::ppcf128) {
5262 // FIXME: This generated code sucks. We want to generate
5263 // FCMPU crN, hi1, hi2
5265 // FCMPU crN, lo1, lo2
5266 // The following can be improved, but not that much.
5267 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5268 LHSHi, RHSHi, ISD::SETOEQ);
5269 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
5270 LHSLo, RHSLo, CCCode);
5271 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5272 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5273 LHSHi, RHSHi, ISD::SETUNE);
5274 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5275 LHSHi, RHSHi, CCCode);
5276 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5277 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3);
5286 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
5287 if (RHSCST->isAllOnesValue()) {
5288 // Comparison to -1.
5289 Tmp1 = DAG.getNode(ISD::AND, dl,LHSLo.getValueType(), LHSLo, LHSHi);
5294 Tmp1 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
5295 Tmp2 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
5296 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5297 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
5300 // If this is a comparison of the sign bit, just look at the top part.
5302 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
5303 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
5304 CST->isNullValue()) || // X < 0
5305 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
5306 CST->isAllOnesValue())) { // X > -1
5312 // FIXME: This generated code sucks.
5313 ISD::CondCode LowCC;
5315 default: assert(0 && "Unknown integer setcc!");
5317 case ISD::SETULT: LowCC = ISD::SETULT; break;
5319 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5321 case ISD::SETULE: LowCC = ISD::SETULE; break;
5323 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5326 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
5327 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
5328 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
5330 // NOTE: on targets without efficient SELECT of bools, we can always use
5331 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5332 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
5333 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
5334 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
5335 if (!Tmp1.getNode())
5336 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
5337 LHSLo, RHSLo, LowCC);
5338 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5339 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
5340 if (!Tmp2.getNode())
5341 Tmp2 = DAG.getNode(ISD::SETCC, dl,
5342 TLI.getSetCCResultType(LHSHi.getValueType()),
5345 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
5346 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
5347 if ((Tmp1C && Tmp1C->isNullValue()) ||
5348 (Tmp2C && Tmp2C->isNullValue() &&
5349 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
5350 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
5351 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
5352 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
5353 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
5354 // low part is known false, returns high part.
5355 // For LE / GE, if high part is known false, ignore the low part.
5356 // For LT / GT, if high part is known true, ignore the low part.
5360 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5361 LHSHi, RHSHi, ISD::SETEQ, false,
5362 DagCombineInfo, dl);
5363 if (!Result.getNode())
5364 Result=DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5365 LHSHi, RHSHi, ISD::SETEQ);
5366 Result = LegalizeOp(DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
5367 Result, Tmp1, Tmp2));
5378 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
5379 /// condition code CC on the current target. This routine assumes LHS and rHS
5380 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
5381 /// illegal condition code into AND / OR of multiple SETCC values.
5382 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
5383 SDValue &LHS, SDValue &RHS,
5386 MVT OpVT = LHS.getValueType();
5387 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5388 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
5389 default: assert(0 && "Unknown condition code action!");
5390 case TargetLowering::Legal:
5393 case TargetLowering::Expand: {
5394 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
5397 default: assert(0 && "Don't know how to expand this condition!"); abort();
5398 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
5399 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5400 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5401 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5402 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5403 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5404 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5405 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5406 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5407 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5408 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5409 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5410 // FIXME: Implement more expansions.
5413 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
5414 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
5415 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
5423 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
5424 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
5425 /// a load from the stack slot to DestVT, extending it if needed.
5426 /// The resultant code need not be legal.
5427 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
5431 // Create the stack frame object.
5432 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
5433 SrcOp.getValueType().getTypeForMVT());
5434 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
5436 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
5437 int SPFI = StackPtrFI->getIndex();
5438 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
5440 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
5441 unsigned SlotSize = SlotVT.getSizeInBits();
5442 unsigned DestSize = DestVT.getSizeInBits();
5443 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
5444 DestVT.getTypeForMVT());
5446 // Emit a store to the stack slot. Use a truncstore if the input value is
5447 // later than DestVT.
5450 if (SrcSize > SlotSize)
5451 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
5452 SV, 0, SlotVT, false, SrcAlign);
5454 assert(SrcSize == SlotSize && "Invalid store");
5455 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
5456 SV, 0, false, SrcAlign);
5459 // Result is a load from the stack slot.
5460 if (SlotSize == DestSize)
5461 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign);
5463 assert(SlotSize < DestSize && "Unknown extension!");
5464 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
5468 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
5469 DebugLoc dl = Node->getDebugLoc();
5470 // Create a vector sized/aligned stack slot, store the value to element #0,
5471 // then load the whole vector back out.
5472 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
5474 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
5475 int SPFI = StackPtrFI->getIndex();
5477 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(0),
5479 PseudoSourceValue::getFixedStack(SPFI), 0);
5480 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
5481 PseudoSourceValue::getFixedStack(SPFI), 0);
5485 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
5486 /// support the operation, but do support the resultant vector type.
5487 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
5489 // If the only non-undef value is the low element, turn this into a
5490 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
5491 unsigned NumElems = Node->getNumOperands();
5492 bool isOnlyLowElement = true;
5493 SDValue SplatValue = Node->getOperand(0);
5494 DebugLoc dl = Node->getDebugLoc();
5496 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
5497 // and use a bitmask instead of a list of elements.
5498 std::map<SDValue, std::vector<unsigned> > Values;
5499 Values[SplatValue].push_back(0);
5500 bool isConstant = true;
5501 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
5502 SplatValue.getOpcode() != ISD::UNDEF)
5505 for (unsigned i = 1; i < NumElems; ++i) {
5506 SDValue V = Node->getOperand(i);
5507 Values[V].push_back(i);
5508 if (V.getOpcode() != ISD::UNDEF)
5509 isOnlyLowElement = false;
5510 if (SplatValue != V)
5511 SplatValue = SDValue(0,0);
5513 // If this isn't a constant element or an undef, we can't use a constant
5515 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
5516 V.getOpcode() != ISD::UNDEF)
5520 if (isOnlyLowElement) {
5521 // If the low element is an undef too, then this whole things is an undef.
5522 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
5523 return DAG.getUNDEF(Node->getValueType(0));
5524 // Otherwise, turn this into a scalar_to_vector node.
5525 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, Node->getValueType(0),
5526 Node->getOperand(0));
5529 // If all elements are constants, create a load from the constant pool.
5531 MVT VT = Node->getValueType(0);
5532 std::vector<Constant*> CV;
5533 for (unsigned i = 0, e = NumElems; i != e; ++i) {
5534 if (ConstantFPSDNode *V =
5535 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
5536 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
5537 } else if (ConstantSDNode *V =
5538 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
5539 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
5541 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
5543 Node->getOperand(0).getValueType().getTypeForMVT();
5544 CV.push_back(UndefValue::get(OpNTy));
5547 Constant *CP = ConstantVector::get(CV);
5548 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5549 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5550 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5551 PseudoSourceValue::getConstantPool(), 0,
5555 if (SplatValue.getNode()) { // Splat of one value?
5556 // Build the shuffle constant vector: <0, 0, 0, 0>
5557 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5558 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5559 std::vector<SDValue> ZeroVec(NumElems, Zero);
5560 SDValue SplatMask = DAG.getBUILD_VECTOR(MaskVT, dl,
5561 &ZeroVec[0], ZeroVec.size());
5563 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5564 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5565 // Get the splatted value into the low element of a vector register.
5567 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5568 Node->getValueType(0), SplatValue);
5570 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5571 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,
5572 Node->getValueType(0), LowValVec,
5573 DAG.getUNDEF(Node->getValueType(0)),
5578 // If there are only two unique elements, we may be able to turn this into a
5580 if (Values.size() == 2) {
5581 // Get the two values in deterministic order.
5582 SDValue Val1 = Node->getOperand(1);
5584 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5585 if (MI->first != Val1)
5588 Val2 = (++MI)->first;
5590 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5591 // vector shuffle has the undef vector on the RHS.
5592 if (Val1.getOpcode() == ISD::UNDEF)
5593 std::swap(Val1, Val2);
5595 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5596 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5597 MVT MaskEltVT = MaskVT.getVectorElementType();
5598 std::vector<SDValue> MaskVec(NumElems);
5600 // Set elements of the shuffle mask for Val1.
5601 std::vector<unsigned> &Val1Elts = Values[Val1];
5602 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5603 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5605 // Set elements of the shuffle mask for Val2.
5606 std::vector<unsigned> &Val2Elts = Values[Val2];
5607 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5608 if (Val2.getOpcode() != ISD::UNDEF)
5609 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5611 MaskVec[Val2Elts[i]] = DAG.getUNDEF(MaskEltVT);
5613 SDValue ShuffleMask = DAG.getBUILD_VECTOR(MaskVT, dl,
5614 &MaskVec[0], MaskVec.size());
5616 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5617 if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR,
5618 Node->getValueType(0)) &&
5619 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5620 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,Node->getValueType(0), Val1);
5621 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,Node->getValueType(0), Val2);
5622 SDValue Ops[] = { Val1, Val2, ShuffleMask };
5624 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5625 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,Node->getValueType(0), Ops, 3);
5629 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5630 // aligned object on the stack, store each element into it, then load
5631 // the result as a vector.
5632 MVT VT = Node->getValueType(0);
5633 // Create the stack frame object.
5634 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5635 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
5636 const Value *SV = PseudoSourceValue::getFixedStack(FI);
5638 // Emit a store of each element to the stack slot.
5639 SmallVector<SDValue, 8> Stores;
5640 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5641 // Store (in the right endianness) the elements to memory.
5642 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5643 // Ignore undef elements.
5644 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5646 unsigned Offset = TypeByteSize*i;
5648 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5649 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
5651 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
5656 if (!Stores.empty()) // Not all undef elements?
5657 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5658 &Stores[0], Stores.size());
5660 StoreChain = DAG.getEntryNode();
5662 // Result is a load from the stack slot.
5663 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0);
5666 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5667 SDValue Op, SDValue Amt,
5668 SDValue &Lo, SDValue &Hi,
5670 // Expand the subcomponents.
5672 ExpandOp(Op, LHSL, LHSH);
5674 SDValue Ops[] = { LHSL, LHSH, Amt };
5675 MVT VT = LHSL.getValueType();
5676 Lo = DAG.getNode(NodeOp, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5677 Hi = Lo.getValue(1);
5681 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5682 /// smaller elements. If we can't find a way that is more efficient than a
5683 /// libcall on this target, return false. Otherwise, return true with the
5684 /// low-parts expanded into Lo and Hi.
5685 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5686 SDValue &Lo, SDValue &Hi,
5688 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5689 "This is not a shift!");
5691 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5692 SDValue ShAmt = LegalizeOp(Amt);
5693 MVT ShTy = ShAmt.getValueType();
5694 unsigned ShBits = ShTy.getSizeInBits();
5695 unsigned VTBits = Op.getValueType().getSizeInBits();
5696 unsigned NVTBits = NVT.getSizeInBits();
5698 // Handle the case when Amt is an immediate.
5699 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5700 unsigned Cst = CN->getZExtValue();
5701 // Expand the incoming operand to be shifted, so that we have its parts
5703 ExpandOp(Op, InL, InH);
5707 Lo = DAG.getConstant(0, NVT);
5708 Hi = DAG.getConstant(0, NVT);
5709 } else if (Cst > NVTBits) {
5710 Lo = DAG.getConstant(0, NVT);
5711 Hi = DAG.getNode(ISD::SHL, dl,
5712 NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5713 } else if (Cst == NVTBits) {
5714 Lo = DAG.getConstant(0, NVT);
5717 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Cst, ShTy));
5718 Hi = DAG.getNode(ISD::OR, dl, NVT,
5719 DAG.getNode(ISD::SHL, dl, NVT, InH, DAG.getConstant(Cst, ShTy)),
5720 DAG.getNode(ISD::SRL, dl, NVT, InL,
5721 DAG.getConstant(NVTBits-Cst, ShTy)));
5726 Lo = DAG.getConstant(0, NVT);
5727 Hi = DAG.getConstant(0, NVT);
5728 } else if (Cst > NVTBits) {
5729 Lo = DAG.getNode(ISD::SRL, dl, NVT,
5730 InH, DAG.getConstant(Cst-NVTBits,ShTy));
5731 Hi = DAG.getConstant(0, NVT);
5732 } else if (Cst == NVTBits) {
5734 Hi = DAG.getConstant(0, NVT);
5736 Lo = DAG.getNode(ISD::OR, dl, NVT,
5737 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
5738 DAG.getNode(ISD::SHL, dl, NVT, InH,
5739 DAG.getConstant(NVTBits-Cst, ShTy)));
5740 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
5745 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
5746 DAG.getConstant(NVTBits-1, ShTy));
5747 } else if (Cst > NVTBits) {
5748 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
5749 DAG.getConstant(Cst-NVTBits, ShTy));
5750 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
5751 DAG.getConstant(NVTBits-1, ShTy));
5752 } else if (Cst == NVTBits) {
5754 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
5755 DAG.getConstant(NVTBits-1, ShTy));
5757 Lo = DAG.getNode(ISD::OR, dl, NVT,
5758 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
5759 DAG.getNode(ISD::SHL, dl,
5760 NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5761 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
5767 // Okay, the shift amount isn't constant. However, if we can tell that it is
5768 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5769 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5770 APInt KnownZero, KnownOne;
5771 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5773 // If we know that if any of the high bits of the shift amount are one, then
5774 // we can do this as a couple of simple shifts.
5775 if (KnownOne.intersects(Mask)) {
5776 // Mask out the high bit, which we know is set.
5777 Amt = DAG.getNode(ISD::AND, dl, Amt.getValueType(), Amt,
5778 DAG.getConstant(~Mask, Amt.getValueType()));
5780 // Expand the incoming operand to be shifted, so that we have its parts
5782 ExpandOp(Op, InL, InH);
5785 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5786 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
5789 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5790 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
5793 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
5794 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5795 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
5800 // If we know that the high bits of the shift amount are all zero, then we can
5801 // do this as a couple of simple shifts.
5802 if ((KnownZero & Mask) == Mask) {
5804 SDValue Amt2 = DAG.getNode(ISD::SUB, dl, Amt.getValueType(),
5805 DAG.getConstant(NVTBits, Amt.getValueType()),
5808 // Expand the incoming operand to be shifted, so that we have its parts
5810 ExpandOp(Op, InL, InH);
5813 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
5814 Hi = DAG.getNode(ISD::OR, dl, NVT,
5815 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
5816 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2));
5819 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
5820 Lo = DAG.getNode(ISD::OR, dl, NVT,
5821 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
5822 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
5825 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
5826 Lo = DAG.getNode(ISD::OR, dl, NVT,
5827 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
5828 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
5837 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5838 // does not fit into a register, return the lo part and set the hi part to the
5839 // by-reg argument. If it does fit into a single register, return the result
5840 // and leave the Hi part unset.
5841 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5842 bool isSigned, SDValue &Hi) {
5843 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5844 // The input chain to this libcall is the entry node of the function.
5845 // Legalizing the call will automatically add the previous call to the
5847 SDValue InChain = DAG.getEntryNode();
5849 TargetLowering::ArgListTy Args;
5850 TargetLowering::ArgListEntry Entry;
5851 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5852 MVT ArgVT = Node->getOperand(i).getValueType();
5853 const Type *ArgTy = ArgVT.getTypeForMVT();
5854 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5855 Entry.isSExt = isSigned;
5856 Entry.isZExt = !isSigned;
5857 Args.push_back(Entry);
5859 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5860 TLI.getPointerTy());
5862 // Splice the libcall in wherever FindInputOutputChains tells us to.
5863 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5864 std::pair<SDValue,SDValue> CallInfo =
5865 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5866 CallingConv::C, false, Callee, Args, DAG,
5867 Node->getDebugLoc());
5869 // Legalize the call sequence, starting with the chain. This will advance
5870 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5871 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5872 LegalizeOp(CallInfo.second);
5874 switch (getTypeAction(CallInfo.first.getValueType())) {
5875 default: assert(0 && "Unknown thing");
5877 Result = CallInfo.first;
5880 ExpandOp(CallInfo.first, Result, Hi);
5886 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5888 SDValue SelectionDAGLegalize::
5889 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op,
5891 bool isCustom = false;
5893 switch (getTypeAction(Op.getValueType())) {
5895 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5896 Op.getValueType())) {
5897 default: assert(0 && "Unknown operation action!");
5898 case TargetLowering::Custom:
5901 case TargetLowering::Legal:
5902 Tmp1 = LegalizeOp(Op);
5903 if (Result.getNode())
5904 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5906 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl,
5909 Tmp1 = TLI.LowerOperation(Result, DAG);
5910 if (Tmp1.getNode()) Result = Tmp1;
5913 case TargetLowering::Expand:
5914 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy, dl);
5916 case TargetLowering::Promote:
5917 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned, dl);
5922 Result = ExpandIntToFP(isSigned, DestTy, Op, dl) ;
5925 Tmp1 = PromoteOp(Op);
5927 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp1.getValueType(),
5928 Tmp1, DAG.getValueType(Op.getValueType()));
5930 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl,
5933 if (Result.getNode())
5934 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5936 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl,
5938 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5944 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5946 SDValue SelectionDAGLegalize::
5947 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl) {
5948 MVT SourceVT = Source.getValueType();
5949 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5951 // Expand unsupported int-to-fp vector casts by unrolling them.
5952 if (DestTy.isVector()) {
5954 return LegalizeOp(UnrollVectorOp(Source));
5955 MVT DestEltTy = DestTy.getVectorElementType();
5956 if (DestTy.getVectorNumElements() == 1) {
5957 SDValue Scalar = ScalarizeVectorOp(Source);
5958 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5959 DestEltTy, Scalar, dl);
5960 return DAG.getBUILD_VECTOR(DestTy, dl, Result);
5963 SplitVectorOp(Source, Lo, Hi);
5964 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5965 DestTy.getVectorNumElements() / 2);
5966 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
5968 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
5970 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, DestTy, LoResult,
5974 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5975 if (!isSigned && SourceVT != MVT::i32) {
5976 // The integer value loaded will be incorrectly if the 'sign bit' of the
5977 // incoming integer is set. To handle this, we dynamically test to see if
5978 // it is set, and, if so, add a fudge factor.
5982 ExpandOp(Source, Lo, Hi);
5983 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, Lo, Hi);
5985 // The comparison for the sign bit will use the entire operand.
5989 // Check to see if the target has a custom way to lower this. If so, use
5990 // it. (Note we've already expanded the operand in this case.)
5991 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) {
5992 default: assert(0 && "This action not implemented for this operation!");
5993 case TargetLowering::Legal:
5994 case TargetLowering::Expand:
5995 break; // This case is handled below.
5996 case TargetLowering::Custom: {
5997 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, dl, DestTy,
6000 return LegalizeOp(NV);
6001 break; // The target decided this was legal after all
6005 // If this is unsigned, and not supported, first perform the conversion to
6006 // signed, then adjust the result if the sign bit is set.
6007 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source, dl);
6009 SDValue SignSet = DAG.getSetCC(dl,
6010 TLI.getSetCCResultType(Hi.getValueType()),
6011 Hi, DAG.getConstant(0, Hi.getValueType()),
6013 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
6014 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
6015 SignSet, Four, Zero);
6016 uint64_t FF = 0x5f800000ULL;
6017 if (TLI.isLittleEndian()) FF <<= 32;
6018 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
6020 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
6021 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6022 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
6023 Alignment = std::min(Alignment, 4u);
6025 if (DestTy == MVT::f32)
6026 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
6027 PseudoSourceValue::getConstantPool(), 0,
6029 else if (DestTy.bitsGT(MVT::f32))
6030 // FIXME: Avoid the extend by construction the right constantpool?
6031 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, dl, DestTy, DAG.getEntryNode(),
6033 PseudoSourceValue::getConstantPool(), 0,
6034 MVT::f32, false, Alignment);
6036 assert(0 && "Unexpected conversion");
6038 MVT SCVT = SignedConv.getValueType();
6039 if (SCVT != DestTy) {
6040 // Destination type needs to be expanded as well. The FADD now we are
6041 // constructing will be expanded into a libcall.
6042 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
6043 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
6044 SignedConv = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy,
6045 SignedConv, SignedConv.getValue(1));
6047 SignedConv = DAG.getNode(ISD::BIT_CONVERT, dl, DestTy, SignedConv);
6049 return DAG.getNode(ISD::FADD, dl, DestTy, SignedConv, FudgeInReg);
6052 // Check to see if the target has a custom way to lower this. If so, use it.
6053 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
6054 default: assert(0 && "This action not implemented for this operation!");
6055 case TargetLowering::Legal:
6056 case TargetLowering::Expand:
6057 break; // This case is handled below.
6058 case TargetLowering::Custom: {
6059 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, dl, DestTy,
6062 return LegalizeOp(NV);
6063 break; // The target decided this was legal after all
6067 // Expand the source, then glue it back together for the call. We must expand
6068 // the source in case it is shared (this pass of legalize must traverse it).
6070 SDValue SrcLo, SrcHi;
6071 ExpandOp(Source, SrcLo, SrcHi);
6072 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, SrcLo, SrcHi);
6075 RTLIB::Libcall LC = isSigned ?
6076 RTLIB::getSINTTOFP(SourceVT, DestTy) :
6077 RTLIB::getUINTTOFP(SourceVT, DestTy);
6078 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
6080 Source = DAG.getNode(ISD::SINT_TO_FP, dl, DestTy, Source);
6082 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
6083 if (Result.getValueType() != DestTy && HiPart.getNode())
6084 Result = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy, Result, HiPart);
6088 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
6089 /// INT_TO_FP operation of the specified operand when the target requests that
6090 /// we expand it. At this point, we know that the result and operand types are
6091 /// legal for the target.
6092 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
6096 if (Op0.getValueType() == MVT::i32) {
6097 // simple 32-bit [signed|unsigned] integer to float/double expansion
6099 // Get the stack frame index of a 8 byte buffer.
6100 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
6102 // word offset constant for Hi/Lo address computation
6103 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
6104 // set up Hi and Lo (into buffer) address based on endian
6105 SDValue Hi = StackSlot;
6106 SDValue Lo = DAG.getNode(ISD::ADD, dl,
6107 TLI.getPointerTy(), StackSlot,WordOff);
6108 if (TLI.isLittleEndian())
6111 // if signed map to unsigned space
6114 // constant used to invert sign bit (signed to unsigned mapping)
6115 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
6116 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
6120 // store the lo of the constructed double - based on integer input
6121 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
6122 Op0Mapped, Lo, NULL, 0);
6123 // initial hi portion of constructed double
6124 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
6125 // store the hi of the constructed double - biased exponent
6126 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
6127 // load the constructed double
6128 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
6129 // FP constant to bias correct the final result
6130 SDValue Bias = DAG.getConstantFP(isSigned ?
6131 BitsToDouble(0x4330000080000000ULL)
6132 : BitsToDouble(0x4330000000000000ULL),
6134 // subtract the bias
6135 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
6138 // handle final rounding
6139 if (DestVT == MVT::f64) {
6142 } else if (DestVT.bitsLT(MVT::f64)) {
6143 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
6144 DAG.getIntPtrConstant(0));
6145 } else if (DestVT.bitsGT(MVT::f64)) {
6146 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
6150 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
6151 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
6153 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
6154 Op0, DAG.getConstant(0, Op0.getValueType()),
6156 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
6157 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
6158 SignSet, Four, Zero);
6160 // If the sign bit of the integer is set, the large number will be treated
6161 // as a negative number. To counteract this, the dynamic code adds an
6162 // offset depending on the data type.
6164 switch (Op0.getValueType().getSimpleVT()) {
6165 default: assert(0 && "Unsupported integer type!");
6166 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
6167 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
6168 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
6169 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
6171 if (TLI.isLittleEndian()) FF <<= 32;
6172 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
6174 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
6175 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6176 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
6177 Alignment = std::min(Alignment, 4u);
6179 if (DestVT == MVT::f32)
6180 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
6181 PseudoSourceValue::getConstantPool(), 0,
6185 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
6186 DAG.getEntryNode(), CPIdx,
6187 PseudoSourceValue::getConstantPool(), 0,
6188 MVT::f32, false, Alignment));
6191 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
6194 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
6195 /// *INT_TO_FP operation of the specified operand when the target requests that
6196 /// we promote it. At this point, we know that the result and operand types are
6197 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
6198 /// operation that takes a larger input.
6199 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
6203 // First step, figure out the appropriate *INT_TO_FP operation to use.
6204 MVT NewInTy = LegalOp.getValueType();
6206 unsigned OpToUse = 0;
6208 // Scan for the appropriate larger type to use.
6210 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
6211 assert(NewInTy.isInteger() && "Ran out of possibilities!");
6213 // If the target supports SINT_TO_FP of this type, use it.
6214 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
6216 case TargetLowering::Legal:
6217 if (!TLI.isTypeLegal(NewInTy))
6218 break; // Can't use this datatype.
6220 case TargetLowering::Custom:
6221 OpToUse = ISD::SINT_TO_FP;
6225 if (isSigned) continue;
6227 // If the target supports UINT_TO_FP of this type, use it.
6228 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
6230 case TargetLowering::Legal:
6231 if (!TLI.isTypeLegal(NewInTy))
6232 break; // Can't use this datatype.
6234 case TargetLowering::Custom:
6235 OpToUse = ISD::UINT_TO_FP;
6240 // Otherwise, try a larger type.
6243 // Okay, we found the operation and type to use. Zero extend our input to the
6244 // desired type then run the operation on it.
6245 return DAG.getNode(OpToUse, dl, DestVT,
6246 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
6247 dl, NewInTy, LegalOp));
6250 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
6251 /// FP_TO_*INT operation of the specified operand when the target requests that
6252 /// we promote it. At this point, we know that the result and operand types are
6253 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
6254 /// operation that returns a larger result.
6255 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
6259 // First step, figure out the appropriate FP_TO*INT operation to use.
6260 MVT NewOutTy = DestVT;
6262 unsigned OpToUse = 0;
6264 // Scan for the appropriate larger type to use.
6266 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
6267 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
6269 // If the target supports FP_TO_SINT returning this type, use it.
6270 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
6272 case TargetLowering::Legal:
6273 if (!TLI.isTypeLegal(NewOutTy))
6274 break; // Can't use this datatype.
6276 case TargetLowering::Custom:
6277 OpToUse = ISD::FP_TO_SINT;
6282 // If the target supports FP_TO_UINT of this type, use it.
6283 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
6285 case TargetLowering::Legal:
6286 if (!TLI.isTypeLegal(NewOutTy))
6287 break; // Can't use this datatype.
6289 case TargetLowering::Custom:
6290 OpToUse = ISD::FP_TO_UINT;
6295 // Otherwise, try a larger type.
6299 // Okay, we found the operation and type to use.
6300 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
6302 // If the operation produces an invalid type, it must be custom lowered. Use
6303 // the target lowering hooks to expand it. Just keep the low part of the
6304 // expanded operation, we know that we're truncating anyway.
6305 if (getTypeAction(NewOutTy) == Expand) {
6306 SmallVector<SDValue, 2> Results;
6307 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG);
6308 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!");
6309 Operation = Results[0];
6312 // Truncate the result of the extended FP_TO_*INT operation to the desired
6314 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
6317 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
6319 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
6320 MVT VT = Op.getValueType();
6321 MVT SHVT = TLI.getShiftAmountTy();
6322 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
6323 switch (VT.getSimpleVT()) {
6324 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
6326 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6327 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6328 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
6330 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
6331 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6332 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6333 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
6334 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
6335 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
6336 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
6337 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
6338 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
6340 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
6341 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
6342 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
6343 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6344 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6345 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
6346 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
6347 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
6348 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
6349 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
6350 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
6351 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
6352 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
6353 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
6354 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
6355 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
6356 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
6357 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
6358 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
6359 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
6360 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
6364 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
6366 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
6369 default: assert(0 && "Cannot expand this yet!");
6371 static const uint64_t mask[6] = {
6372 0x5555555555555555ULL, 0x3333333333333333ULL,
6373 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
6374 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
6376 MVT VT = Op.getValueType();
6377 MVT ShVT = TLI.getShiftAmountTy();
6378 unsigned len = VT.getSizeInBits();
6379 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6380 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
6381 unsigned EltSize = VT.isVector() ?
6382 VT.getVectorElementType().getSizeInBits() : len;
6383 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
6384 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6385 Op = DAG.getNode(ISD::ADD, dl, VT,
6386 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
6387 DAG.getNode(ISD::AND, dl, VT,
6388 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
6394 // for now, we do this:
6395 // x = x | (x >> 1);
6396 // x = x | (x >> 2);
6398 // x = x | (x >>16);
6399 // x = x | (x >>32); // for 64-bit input
6400 // return popcount(~x);
6402 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
6403 MVT VT = Op.getValueType();
6404 MVT ShVT = TLI.getShiftAmountTy();
6405 unsigned len = VT.getSizeInBits();
6406 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6407 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6408 Op = DAG.getNode(ISD::OR, dl, VT, Op,
6409 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
6411 Op = DAG.getNOT(dl, Op, VT);
6412 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
6415 // for now, we use: { return popcount(~x & (x - 1)); }
6416 // unless the target has ctlz but not ctpop, in which case we use:
6417 // { return 32 - nlz(~x & (x-1)); }
6418 // see also http://www.hackersdelight.org/HDcode/ntz.cc
6419 MVT VT = Op.getValueType();
6420 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
6421 DAG.getNOT(dl, Op, VT),
6422 DAG.getNode(ISD::SUB, dl, VT, Op,
6423 DAG.getConstant(1, VT)));
6424 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6425 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
6426 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
6427 return DAG.getNode(ISD::SUB, dl, VT,
6428 DAG.getConstant(VT.getSizeInBits(), VT),
6429 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
6430 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
6435 /// ExpandOp - Expand the specified SDValue into its two component pieces
6436 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
6437 /// LegalizedNodes map is filled in for any results that are not expanded, the
6438 /// ExpandedNodes map is filled in for any results that are expanded, and the
6439 /// Lo/Hi values are returned.
6440 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
6441 MVT VT = Op.getValueType();
6442 MVT NVT = TLI.getTypeToTransformTo(VT);
6443 SDNode *Node = Op.getNode();
6444 DebugLoc dl = Node->getDebugLoc();
6445 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
6446 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
6447 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
6449 // See if we already expanded it.
6450 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
6451 = ExpandedNodes.find(Op);
6452 if (I != ExpandedNodes.end()) {
6453 Lo = I->second.first;
6454 Hi = I->second.second;
6458 switch (Node->getOpcode()) {
6459 case ISD::CopyFromReg:
6460 assert(0 && "CopyFromReg must be legal!");
6461 case ISD::FP_ROUND_INREG:
6462 if (VT == MVT::ppcf128 &&
6463 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
6464 TargetLowering::Custom) {
6465 SDValue SrcLo, SrcHi, Src;
6466 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
6467 Src = DAG.getNode(ISD::BUILD_PAIR, dl, VT, SrcLo, SrcHi);
6468 SDValue Result = TLI.LowerOperation(
6469 DAG.getNode(ISD::FP_ROUND_INREG, dl, VT, Src, Op.getOperand(1)), DAG);
6470 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
6471 Lo = Result.getNode()->getOperand(0);
6472 Hi = Result.getNode()->getOperand(1);
6478 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
6480 assert(0 && "Do not know how to expand this operator!");
6482 case ISD::EXTRACT_ELEMENT:
6483 ExpandOp(Node->getOperand(0), Lo, Hi);
6484 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
6485 return ExpandOp(Hi, Lo, Hi);
6486 return ExpandOp(Lo, Lo, Hi);
6487 case ISD::EXTRACT_VECTOR_ELT:
6488 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
6489 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
6490 return ExpandOp(Lo, Lo, Hi);
6492 Lo = DAG.getUNDEF(NVT);
6493 Hi = DAG.getUNDEF(NVT);
6495 case ISD::Constant: {
6496 unsigned NVTBits = NVT.getSizeInBits();
6497 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
6498 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
6499 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
6502 case ISD::ConstantFP: {
6503 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
6504 if (CFP->getValueType(0) == MVT::ppcf128) {
6505 APInt api = CFP->getValueAPF().bitcastToAPInt();
6506 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
6508 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
6512 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
6513 if (getTypeAction(Lo.getValueType()) == Expand)
6514 ExpandOp(Lo, Lo, Hi);
6517 case ISD::BUILD_PAIR:
6518 // Return the operands.
6519 Lo = Node->getOperand(0);
6520 Hi = Node->getOperand(1);
6523 case ISD::MERGE_VALUES:
6524 if (Node->getNumValues() == 1) {
6525 ExpandOp(Op.getOperand(0), Lo, Hi);
6528 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
6529 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
6530 Op.getValue(1).getValueType() == MVT::Other &&
6531 "unhandled MERGE_VALUES");
6532 ExpandOp(Op.getOperand(0), Lo, Hi);
6533 // Remember that we legalized the chain.
6534 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
6537 case ISD::SIGN_EXTEND_INREG:
6538 ExpandOp(Node->getOperand(0), Lo, Hi);
6539 // sext_inreg the low part if needed.
6540 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Lo, Node->getOperand(1));
6542 // The high part gets the sign extension from the lo-part. This handles
6543 // things like sextinreg V:i64 from i8.
6544 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6545 DAG.getConstant(NVT.getSizeInBits()-1,
6546 TLI.getShiftAmountTy()));
6550 ExpandOp(Node->getOperand(0), Lo, Hi);
6551 SDValue TempLo = DAG.getNode(ISD::BSWAP, dl, NVT, Hi);
6552 Hi = DAG.getNode(ISD::BSWAP, dl, NVT, Lo);
6558 ExpandOp(Node->getOperand(0), Lo, Hi);
6559 Lo = DAG.getNode(ISD::ADD, dl, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
6560 DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
6561 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
6562 Hi = DAG.getConstant(0, NVT);
6566 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
6567 ExpandOp(Node->getOperand(0), Lo, Hi);
6568 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6569 SDValue HLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
6570 SDValue TopNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), HLZ,
6572 SDValue LowPart = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
6573 LowPart = DAG.getNode(ISD::ADD, dl, NVT, LowPart, BitsC);
6575 Lo = DAG.getNode(ISD::SELECT, dl, NVT, TopNotZero, HLZ, LowPart);
6576 Hi = DAG.getConstant(0, NVT);
6581 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
6582 ExpandOp(Node->getOperand(0), Lo, Hi);
6583 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6584 SDValue LTZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
6585 SDValue BotNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), LTZ,
6587 SDValue HiPart = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
6588 HiPart = DAG.getNode(ISD::ADD, dl, NVT, HiPart, BitsC);
6590 Lo = DAG.getNode(ISD::SELECT, dl, NVT, BotNotZero, LTZ, HiPart);
6591 Hi = DAG.getConstant(0, NVT);
6596 SDValue Ch = Node->getOperand(0); // Legalize the chain.
6597 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6598 Lo = DAG.getVAArg(NVT, dl, Ch, Ptr, Node->getOperand(2));
6599 Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, Node->getOperand(2));
6601 // Remember that we legalized the chain.
6602 Hi = LegalizeOp(Hi);
6603 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6604 if (TLI.isBigEndian())
6610 LoadSDNode *LD = cast<LoadSDNode>(Node);
6611 SDValue Ch = LD->getChain(); // Legalize the chain.
6612 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6613 ISD::LoadExtType ExtType = LD->getExtensionType();
6614 const Value *SV = LD->getSrcValue();
6615 int SVOffset = LD->getSrcValueOffset();
6616 unsigned Alignment = LD->getAlignment();
6617 bool isVolatile = LD->isVolatile();
6619 if (ExtType == ISD::NON_EXTLOAD) {
6620 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset,
6621 isVolatile, Alignment);
6622 if (VT == MVT::f32 || VT == MVT::f64) {
6623 // f32->i32 or f64->i64 one to one expansion.
6624 // Remember that we legalized the chain.
6625 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6626 // Recursively expand the new load.
6627 if (getTypeAction(NVT) == Expand)
6628 ExpandOp(Lo, Lo, Hi);
6632 // Increment the pointer to the other half.
6633 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6634 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
6635 DAG.getIntPtrConstant(IncrementSize));
6636 SVOffset += IncrementSize;
6637 Alignment = MinAlign(Alignment, IncrementSize);
6638 Hi = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset,
6639 isVolatile, Alignment);
6641 // Build a factor node to remember that this load is independent of the
6643 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
6646 // Remember that we legalized the chain.
6647 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6648 if (TLI.isBigEndian())
6651 MVT EVT = LD->getMemoryVT();
6653 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6654 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6655 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6656 SDValue Load = DAG.getLoad(EVT, dl, Ch, Ptr, SV,
6657 SVOffset, isVolatile, Alignment);
6658 // Remember that we legalized the chain.
6659 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6660 ExpandOp(DAG.getNode(ISD::FP_EXTEND, dl, VT, Load), Lo, Hi);
6665 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV,
6666 SVOffset, isVolatile, Alignment);
6668 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, SV,
6669 SVOffset, EVT, isVolatile,
6672 // Remember that we legalized the chain.
6673 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6675 if (ExtType == ISD::SEXTLOAD) {
6676 // The high part is obtained by SRA'ing all but one of the bits of the
6678 unsigned LoSize = Lo.getValueType().getSizeInBits();
6679 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6680 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6681 } else if (ExtType == ISD::ZEXTLOAD) {
6682 // The high part is just a zero.
6683 Hi = DAG.getConstant(0, NVT);
6684 } else /* if (ExtType == ISD::EXTLOAD) */ {
6685 // The high part is undefined.
6686 Hi = DAG.getUNDEF(NVT);
6693 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6694 SDValue LL, LH, RL, RH;
6695 ExpandOp(Node->getOperand(0), LL, LH);
6696 ExpandOp(Node->getOperand(1), RL, RH);
6697 Lo = DAG.getNode(Node->getOpcode(), dl, NVT, LL, RL);
6698 Hi = DAG.getNode(Node->getOpcode(), dl, NVT, LH, RH);
6702 SDValue LL, LH, RL, RH;
6703 ExpandOp(Node->getOperand(1), LL, LH);
6704 ExpandOp(Node->getOperand(2), RL, RH);
6705 if (getTypeAction(NVT) == Expand)
6706 NVT = TLI.getTypeToExpandTo(NVT);
6707 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LL, RL);
6709 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LH, RH);
6712 case ISD::SELECT_CC: {
6713 SDValue TL, TH, FL, FH;
6714 ExpandOp(Node->getOperand(2), TL, TH);
6715 ExpandOp(Node->getOperand(3), FL, FH);
6716 if (getTypeAction(NVT) == Expand)
6717 NVT = TLI.getTypeToExpandTo(NVT);
6718 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
6719 Node->getOperand(1), TL, FL, Node->getOperand(4));
6721 Hi = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
6722 Node->getOperand(1), TH, FH, Node->getOperand(4));
6725 case ISD::ANY_EXTEND:
6726 // The low part is any extension of the input (which degenerates to a copy).
6727 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0));
6728 // The high part is undefined.
6729 Hi = DAG.getUNDEF(NVT);
6731 case ISD::SIGN_EXTEND: {
6732 // The low part is just a sign extension of the input (which degenerates to
6734 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Node->getOperand(0));
6736 // The high part is obtained by SRA'ing all but one of the bits of the lo
6738 unsigned LoSize = Lo.getValueType().getSizeInBits();
6739 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6740 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6743 case ISD::ZERO_EXTEND:
6744 // The low part is just a zero extension of the input (which degenerates to
6746 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
6748 // The high part is just a zero.
6749 Hi = DAG.getConstant(0, NVT);
6752 case ISD::TRUNCATE: {
6753 // The input value must be larger than this value. Expand *it*.
6755 ExpandOp(Node->getOperand(0), NewLo, Hi);
6757 // The low part is now either the right size, or it is closer. If not the
6758 // right size, make an illegal truncate so we recursively expand it.
6759 if (NewLo.getValueType() != Node->getValueType(0))
6760 NewLo = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), NewLo);
6761 ExpandOp(NewLo, Lo, Hi);
6765 case ISD::BIT_CONVERT: {
6767 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6768 // If the target wants to, allow it to lower this itself.
6769 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6770 case Expand: assert(0 && "cannot expand FP!");
6771 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6772 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6774 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp), DAG);
6777 // f32 / f64 must be expanded to i32 / i64.
6778 if (VT == MVT::f32 || VT == MVT::f64) {
6779 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
6780 if (getTypeAction(NVT) == Expand)
6781 ExpandOp(Lo, Lo, Hi);
6785 // If source operand will be expanded to the same type as VT, i.e.
6786 // i64 <- f64, i32 <- f32, expand the source operand instead.
6787 MVT VT0 = Node->getOperand(0).getValueType();
6788 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6789 ExpandOp(Node->getOperand(0), Lo, Hi);
6793 // Turn this into a load/store pair by default.
6794 if (Tmp.getNode() == 0)
6795 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT, dl);
6797 ExpandOp(Tmp, Lo, Hi);
6801 case ISD::READCYCLECOUNTER: {
6802 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6803 TargetLowering::Custom &&
6804 "Must custom expand ReadCycleCounter");
6805 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6806 assert(Tmp.getNode() && "Node must be custom expanded!");
6807 ExpandOp(Tmp.getValue(0), Lo, Hi);
6808 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6809 LegalizeOp(Tmp.getValue(1)));
6813 case ISD::ATOMIC_CMP_SWAP: {
6814 // This operation does not need a loop.
6815 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6816 assert(Tmp.getNode() && "Node must be custom expanded!");
6817 ExpandOp(Tmp.getValue(0), Lo, Hi);
6818 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6819 LegalizeOp(Tmp.getValue(1)));
6823 case ISD::ATOMIC_LOAD_ADD:
6824 case ISD::ATOMIC_LOAD_SUB:
6825 case ISD::ATOMIC_LOAD_AND:
6826 case ISD::ATOMIC_LOAD_OR:
6827 case ISD::ATOMIC_LOAD_XOR:
6828 case ISD::ATOMIC_LOAD_NAND:
6829 case ISD::ATOMIC_SWAP: {
6830 // These operations require a loop to be generated. We can't do that yet,
6831 // so substitute a target-dependent pseudo and expand that later.
6832 SDValue In2Lo, In2Hi, In2;
6833 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6834 In2 = DAG.getNode(ISD::BUILD_PAIR, dl, VT, In2Lo, In2Hi);
6835 AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
6837 DAG.getAtomic(Op.getOpcode(), dl, Anode->getMemoryVT(),
6838 Op.getOperand(0), Op.getOperand(1), In2,
6839 Anode->getSrcValue(), Anode->getAlignment());
6840 SDValue Result = TLI.LowerOperation(Replace, DAG);
6841 ExpandOp(Result.getValue(0), Lo, Hi);
6842 // Remember that we legalized the chain.
6843 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
6847 // These operators cannot be expanded directly, emit them as calls to
6848 // library functions.
6849 case ISD::FP_TO_SINT: {
6850 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6852 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6853 case Expand: assert(0 && "cannot expand FP!");
6854 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6855 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6858 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op), DAG);
6860 // Now that the custom expander is done, expand the result, which is still
6863 ExpandOp(Op, Lo, Hi);
6868 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6870 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6871 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6875 case ISD::FP_TO_UINT: {
6876 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6878 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6879 case Expand: assert(0 && "cannot expand FP!");
6880 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6881 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6884 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, dl, VT, Op), DAG);
6886 // Now that the custom expander is done, expand the result.
6888 ExpandOp(Op, Lo, Hi);
6893 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6895 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6896 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6901 // If the target wants custom lowering, do so.
6902 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6903 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6904 SDValue Op = DAG.getNode(ISD::SHL, dl, VT, Node->getOperand(0), ShiftAmt);
6905 Op = TLI.LowerOperation(Op, DAG);
6907 // Now that the custom expander is done, expand the result, which is
6909 ExpandOp(Op, Lo, Hi);
6914 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6915 // this X << 1 as X+X.
6916 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6917 if (ShAmt->getAPIntValue() == 1 &&
6918 TLI.isOperationLegalOrCustom(ISD::ADDC, NVT) &&
6919 TLI.isOperationLegalOrCustom(ISD::ADDE, NVT)) {
6920 SDValue LoOps[2], HiOps[3];
6921 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6922 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6923 LoOps[1] = LoOps[0];
6924 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
6926 HiOps[1] = HiOps[0];
6927 HiOps[2] = Lo.getValue(1);
6928 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
6933 // If we can emit an efficient shift operation, do so now.
6934 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6937 // If this target supports SHL_PARTS, use it.
6938 TargetLowering::LegalizeAction Action =
6939 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6940 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6941 Action == TargetLowering::Custom) {
6942 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0),
6943 ShiftAmt, Lo, Hi, dl);
6947 // Otherwise, emit a libcall.
6948 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6953 // If the target wants custom lowering, do so.
6954 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6955 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6956 SDValue Op = DAG.getNode(ISD::SRA, dl, VT, Node->getOperand(0), ShiftAmt);
6957 Op = TLI.LowerOperation(Op, DAG);
6959 // Now that the custom expander is done, expand the result, which is
6961 ExpandOp(Op, Lo, Hi);
6966 // If we can emit an efficient shift operation, do so now.
6967 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6970 // If this target supports SRA_PARTS, use it.
6971 TargetLowering::LegalizeAction Action =
6972 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6973 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6974 Action == TargetLowering::Custom) {
6975 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0),
6976 ShiftAmt, Lo, Hi, dl);
6980 // Otherwise, emit a libcall.
6981 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6986 // If the target wants custom lowering, do so.
6987 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6988 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6989 SDValue Op = DAG.getNode(ISD::SRL, dl, VT, Node->getOperand(0), ShiftAmt);
6990 Op = TLI.LowerOperation(Op, DAG);
6992 // Now that the custom expander is done, expand the result, which is
6994 ExpandOp(Op, Lo, Hi);
6999 // If we can emit an efficient shift operation, do so now.
7000 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
7003 // If this target supports SRL_PARTS, use it.
7004 TargetLowering::LegalizeAction Action =
7005 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
7006 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
7007 Action == TargetLowering::Custom) {
7008 ExpandShiftParts(ISD::SRL_PARTS,
7009 Node->getOperand(0), ShiftAmt, Lo, Hi, dl);
7013 // Otherwise, emit a libcall.
7014 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
7020 // If the target wants to custom expand this, let them.
7021 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
7022 TargetLowering::Custom) {
7023 SDValue Result = TLI.LowerOperation(Op, DAG);
7024 if (Result.getNode()) {
7025 ExpandOp(Result, Lo, Hi);
7029 // Expand the subcomponents.
7030 SDValue LHSL, LHSH, RHSL, RHSH;
7031 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7032 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7033 SDValue LoOps[2], HiOps[3];
7039 //cascaded check to see if any smaller size has a a carry flag.
7040 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
7041 bool hasCarry = false;
7042 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
7043 MVT AVT = MVT::getIntegerVT(BitSize);
7044 if (TLI.isOperationLegalOrCustom(OpV, AVT)) {
7051 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7052 if (Node->getOpcode() == ISD::ADD) {
7053 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
7054 HiOps[2] = Lo.getValue(1);
7055 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
7057 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
7058 HiOps[2] = Lo.getValue(1);
7059 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
7063 if (Node->getOpcode() == ISD::ADD) {
7064 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
7065 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
7066 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
7067 Lo, LoOps[0], ISD::SETULT);
7068 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
7069 DAG.getConstant(1, NVT),
7070 DAG.getConstant(0, NVT));
7071 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
7072 Lo, LoOps[1], ISD::SETULT);
7073 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
7074 DAG.getConstant(1, NVT),
7076 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
7078 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
7079 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
7080 SDValue Cmp = DAG.getSetCC(dl, NVT, LoOps[0], LoOps[1], ISD::SETULT);
7081 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
7082 DAG.getConstant(1, NVT),
7083 DAG.getConstant(0, NVT));
7084 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
7092 // Expand the subcomponents.
7093 SDValue LHSL, LHSH, RHSL, RHSH;
7094 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7095 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7096 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7097 SDValue LoOps[2] = { LHSL, RHSL };
7098 SDValue HiOps[3] = { LHSH, RHSH };
7100 if (Node->getOpcode() == ISD::ADDC) {
7101 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
7102 HiOps[2] = Lo.getValue(1);
7103 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
7105 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
7106 HiOps[2] = Lo.getValue(1);
7107 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
7109 // Remember that we legalized the flag.
7110 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7115 // Expand the subcomponents.
7116 SDValue LHSL, LHSH, RHSL, RHSH;
7117 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7118 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7119 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7120 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
7121 SDValue HiOps[3] = { LHSH, RHSH };
7123 Lo = DAG.getNode(Node->getOpcode(), dl, VTList, LoOps, 3);
7124 HiOps[2] = Lo.getValue(1);
7125 Hi = DAG.getNode(Node->getOpcode(), dl, VTList, HiOps, 3);
7127 // Remember that we legalized the flag.
7128 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7132 // If the target wants to custom expand this, let them.
7133 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
7134 SDValue New = TLI.LowerOperation(Op, DAG);
7135 if (New.getNode()) {
7136 ExpandOp(New, Lo, Hi);
7141 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
7142 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
7143 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
7144 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
7145 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
7146 SDValue LL, LH, RL, RH;
7147 ExpandOp(Node->getOperand(0), LL, LH);
7148 ExpandOp(Node->getOperand(1), RL, RH);
7149 unsigned OuterBitSize = Op.getValueSizeInBits();
7150 unsigned InnerBitSize = RH.getValueSizeInBits();
7151 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
7152 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
7153 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
7154 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
7155 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
7156 // The inputs are both zero-extended.
7158 // We can emit a umul_lohi.
7159 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
7160 Hi = SDValue(Lo.getNode(), 1);
7164 // We can emit a mulhu+mul.
7165 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7166 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
7170 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
7171 // The input values are both sign-extended.
7173 // We can emit a smul_lohi.
7174 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
7175 Hi = SDValue(Lo.getNode(), 1);
7179 // We can emit a mulhs+mul.
7180 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7181 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
7186 // Lo,Hi = umul LHS, RHS.
7187 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
7188 DAG.getVTList(NVT, NVT), LL, RL);
7190 Hi = UMulLOHI.getValue(1);
7191 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
7192 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
7193 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
7194 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
7198 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7199 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
7200 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
7201 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
7202 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
7203 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
7208 // If nothing else, we can make a libcall.
7209 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
7213 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
7216 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
7219 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
7222 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
7226 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
7229 RTLIB::ADD_PPCF128),
7233 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
7236 RTLIB::SUB_PPCF128),
7240 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
7243 RTLIB::MUL_PPCF128),
7247 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
7250 RTLIB::DIV_PPCF128),
7253 case ISD::FP_EXTEND: {
7254 if (VT == MVT::ppcf128) {
7255 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
7256 Node->getOperand(0).getValueType()==MVT::f64);
7257 const uint64_t zero = 0;
7258 if (Node->getOperand(0).getValueType()==MVT::f32)
7259 Hi = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Node->getOperand(0));
7261 Hi = Node->getOperand(0);
7262 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7265 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
7266 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
7267 Lo = ExpandLibCall(LC, Node, true, Hi);
7270 case ISD::FP_ROUND: {
7271 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
7273 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
7274 Lo = ExpandLibCall(LC, Node, true, Hi);
7289 case ISD::FNEARBYINT:
7292 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
7293 switch(Node->getOpcode()) {
7295 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
7296 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
7299 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
7300 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
7303 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
7304 RTLIB::COS_F80, RTLIB::COS_PPCF128);
7307 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
7308 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
7311 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
7312 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
7315 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
7316 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
7319 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
7320 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
7323 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
7324 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
7327 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
7328 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
7331 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
7332 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
7335 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
7336 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
7339 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
7340 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
7342 case ISD::FNEARBYINT:
7343 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
7344 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
7347 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
7348 RTLIB::POW_PPCF128);
7351 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
7352 RTLIB::POWI_PPCF128);
7354 default: assert(0 && "Unreachable!");
7356 Lo = ExpandLibCall(LC, Node, false, Hi);
7360 if (VT == MVT::ppcf128) {
7362 ExpandOp(Node->getOperand(0), Lo, Tmp);
7363 Hi = DAG.getNode(ISD::FABS, dl, NVT, Tmp);
7364 // lo = hi==fabs(hi) ? lo : -lo;
7365 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Hi, Tmp,
7366 Lo, DAG.getNode(ISD::FNEG, dl, NVT, Lo),
7367 DAG.getCondCode(ISD::SETEQ));
7370 SDValue Mask = (VT == MVT::f64)
7371 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
7372 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
7373 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask);
7374 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
7375 Lo = DAG.getNode(ISD::AND, dl, NVT, Lo, Mask);
7376 if (getTypeAction(NVT) == Expand)
7377 ExpandOp(Lo, Lo, Hi);
7381 if (VT == MVT::ppcf128) {
7382 ExpandOp(Node->getOperand(0), Lo, Hi);
7383 Lo = DAG.getNode(ISD::FNEG, dl, MVT::f64, Lo);
7384 Hi = DAG.getNode(ISD::FNEG, dl, MVT::f64, Hi);
7387 SDValue Mask = (VT == MVT::f64)
7388 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
7389 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
7390 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask);
7391 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
7392 Lo = DAG.getNode(ISD::XOR, dl, NVT, Lo, Mask);
7393 if (getTypeAction(NVT) == Expand)
7394 ExpandOp(Lo, Lo, Hi);
7397 case ISD::FCOPYSIGN: {
7398 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
7399 if (getTypeAction(NVT) == Expand)
7400 ExpandOp(Lo, Lo, Hi);
7403 case ISD::SINT_TO_FP:
7404 case ISD::UINT_TO_FP: {
7405 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
7406 MVT SrcVT = Node->getOperand(0).getValueType();
7408 // Promote the operand if needed. Do this before checking for
7409 // ppcf128 so conversions of i16 and i8 work.
7410 if (getTypeAction(SrcVT) == Promote) {
7411 SDValue Tmp = PromoteOp(Node->getOperand(0));
7413 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp.getValueType(), Tmp,
7414 DAG.getValueType(SrcVT))
7415 : DAG.getZeroExtendInReg(Tmp, dl, SrcVT);
7416 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
7417 SrcVT = Node->getOperand(0).getValueType();
7420 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
7421 static const uint64_t zero = 0;
7423 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
7424 Node->getOperand(0)));
7425 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7427 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
7428 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
7429 Node->getOperand(0)));
7430 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7431 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
7432 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
7433 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl,
7434 MVT::ppcf128, Node->getOperand(0),
7435 DAG.getConstant(0, MVT::i32),
7436 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
7438 APFloat(APInt(128, 2, TwoE32)),
7441 DAG.getCondCode(ISD::SETLT)),
7446 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
7447 // si64->ppcf128 done by libcall, below
7448 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
7449 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::ppcf128,
7450 Node->getOperand(0)), Lo, Hi);
7451 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
7452 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
7453 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl, MVT::ppcf128,
7454 Node->getOperand(0),
7455 DAG.getConstant(0, MVT::i64),
7456 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
7458 APFloat(APInt(128, 2, TwoE64)),
7461 DAG.getCondCode(ISD::SETLT)),
7466 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
7467 Node->getOperand(0), dl);
7468 if (getTypeAction(Lo.getValueType()) == Expand)
7469 // float to i32 etc. can be 'expanded' to a single node.
7470 ExpandOp(Lo, Lo, Hi);
7475 // Make sure the resultant values have been legalized themselves, unless this
7476 // is a type that requires multi-step expansion.
7477 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
7478 Lo = LegalizeOp(Lo);
7480 // Don't legalize the high part if it is expanded to a single node.
7481 Hi = LegalizeOp(Hi);
7484 // Remember in a map if the values will be reused later.
7486 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7487 assert(isNew && "Value already expanded?!?");
7491 /// SplitVectorOp - Given an operand of vector type, break it down into
7492 /// two smaller values, still of vector type.
7493 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
7495 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
7496 SDNode *Node = Op.getNode();
7497 DebugLoc dl = Node->getDebugLoc();
7498 unsigned NumElements = Op.getValueType().getVectorNumElements();
7499 assert(NumElements > 1 && "Cannot split a single element vector!");
7501 MVT NewEltVT = Op.getValueType().getVectorElementType();
7503 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
7504 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
7506 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
7507 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
7509 // See if we already split it.
7510 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
7511 = SplitNodes.find(Op);
7512 if (I != SplitNodes.end()) {
7513 Lo = I->second.first;
7514 Hi = I->second.second;
7518 switch (Node->getOpcode()) {
7523 assert(0 && "Unhandled operation in SplitVectorOp!");
7525 Lo = DAG.getUNDEF(NewVT_Lo);
7526 Hi = DAG.getUNDEF(NewVT_Hi);
7528 case ISD::BUILD_PAIR:
7529 Lo = Node->getOperand(0);
7530 Hi = Node->getOperand(1);
7532 case ISD::INSERT_VECTOR_ELT: {
7533 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
7534 SplitVectorOp(Node->getOperand(0), Lo, Hi);
7535 unsigned Index = Idx->getZExtValue();
7536 SDValue ScalarOp = Node->getOperand(1);
7537 if (Index < NewNumElts_Lo)
7538 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Lo, Lo, ScalarOp,
7539 DAG.getIntPtrConstant(Index));
7541 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Hi, Hi, ScalarOp,
7542 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
7545 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
7546 Node->getOperand(1),
7547 Node->getOperand(2), dl);
7548 SplitVectorOp(Tmp, Lo, Hi);
7551 case ISD::VECTOR_SHUFFLE: {
7552 // Build the low part.
7553 SDValue Mask = Node->getOperand(2);
7554 SmallVector<SDValue, 8> Ops;
7555 MVT PtrVT = TLI.getPointerTy();
7557 // Insert all of the elements from the input that are needed. We use
7558 // buildvector of extractelement here because the input vectors will have
7559 // to be legalized, so this makes the code simpler.
7560 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
7561 SDValue IdxNode = Mask.getOperand(i);
7562 if (IdxNode.getOpcode() == ISD::UNDEF) {
7563 Ops.push_back(DAG.getUNDEF(NewEltVT));
7566 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7567 SDValue InVec = Node->getOperand(0);
7568 if (Idx >= NumElements) {
7569 InVec = Node->getOperand(1);
7572 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
7573 DAG.getConstant(Idx, PtrVT)));
7575 Lo = DAG.getBUILD_VECTOR(NewVT_Lo, dl, &Ops[0], Ops.size());
7578 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
7579 SDValue IdxNode = Mask.getOperand(i);
7580 if (IdxNode.getOpcode() == ISD::UNDEF) {
7581 Ops.push_back(DAG.getUNDEF(NewEltVT));
7584 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7585 SDValue InVec = Node->getOperand(0);
7586 if (Idx >= NumElements) {
7587 InVec = Node->getOperand(1);
7590 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
7591 DAG.getConstant(Idx, PtrVT)));
7593 Hi = DAG.getBUILD_VECTOR(NewVT_Hi, dl, &Ops[0], Ops.size());
7596 case ISD::BUILD_VECTOR: {
7597 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7598 Node->op_begin()+NewNumElts_Lo);
7599 Lo = DAG.getBUILD_VECTOR(NewVT_Lo, dl, &LoOps[0], LoOps.size());
7601 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
7603 Hi = DAG.getBUILD_VECTOR(NewVT_Hi, dl, &HiOps[0], HiOps.size());
7606 case ISD::CONCAT_VECTORS: {
7607 // FIXME: Handle non-power-of-two vectors?
7608 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
7609 if (NewNumSubvectors == 1) {
7610 Lo = Node->getOperand(0);
7611 Hi = Node->getOperand(1);
7613 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7614 Node->op_begin()+NewNumSubvectors);
7615 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Lo,
7616 &LoOps[0], LoOps.size());
7618 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
7620 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Hi,
7621 &HiOps[0], HiOps.size());
7625 case ISD::EXTRACT_SUBVECTOR: {
7626 SDValue Vec = Op.getOperand(0);
7627 SDValue Idx = Op.getOperand(1);
7628 MVT IdxVT = Idx.getValueType();
7630 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Lo, Vec, Idx);
7631 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
7633 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec,
7634 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo,
7637 Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx,
7638 DAG.getConstant(NewNumElts_Lo, IdxVT));
7639 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec, Idx);
7644 SDValue Cond = Node->getOperand(0);
7646 SDValue LL, LH, RL, RH;
7647 SplitVectorOp(Node->getOperand(1), LL, LH);
7648 SplitVectorOp(Node->getOperand(2), RL, RH);
7650 if (Cond.getValueType().isVector()) {
7651 // Handle a vector merge.
7653 SplitVectorOp(Cond, CL, CH);
7654 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, CL, LL, RL);
7655 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, CH, LH, RH);
7657 // Handle a simple select with vector operands.
7658 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, Cond, LL, RL);
7659 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, Cond, LH, RH);
7663 case ISD::SELECT_CC: {
7664 SDValue CondLHS = Node->getOperand(0);
7665 SDValue CondRHS = Node->getOperand(1);
7666 SDValue CondCode = Node->getOperand(4);
7668 SDValue LL, LH, RL, RH;
7669 SplitVectorOp(Node->getOperand(2), LL, LH);
7670 SplitVectorOp(Node->getOperand(3), RL, RH);
7672 // Handle a simple select with vector operands.
7673 Lo = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Lo, CondLHS, CondRHS,
7675 Hi = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Hi, CondLHS, CondRHS,
7680 SDValue LL, LH, RL, RH;
7681 SplitVectorOp(Node->getOperand(0), LL, LH);
7682 SplitVectorOp(Node->getOperand(1), RL, RH);
7683 Lo = DAG.getNode(ISD::VSETCC, dl, NewVT_Lo, LL, RL, Node->getOperand(2));
7684 Hi = DAG.getNode(ISD::VSETCC, dl, NewVT_Hi, LH, RH, Node->getOperand(2));
7706 SDValue LL, LH, RL, RH;
7707 SplitVectorOp(Node->getOperand(0), LL, LH);
7708 SplitVectorOp(Node->getOperand(1), RL, RH);
7710 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, LL, RL);
7711 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, LH, RH);
7717 SplitVectorOp(Node->getOperand(0), L, H);
7719 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L, Node->getOperand(1));
7720 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H, Node->getOperand(1));
7736 case ISD::FP_TO_SINT:
7737 case ISD::FP_TO_UINT:
7738 case ISD::SINT_TO_FP:
7739 case ISD::UINT_TO_FP:
7741 case ISD::ANY_EXTEND:
7742 case ISD::SIGN_EXTEND:
7743 case ISD::ZERO_EXTEND:
7744 case ISD::FP_EXTEND: {
7746 SplitVectorOp(Node->getOperand(0), L, H);
7748 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L);
7749 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H);
7752 case ISD::CONVERT_RNDSAT: {
7753 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
7755 SplitVectorOp(Node->getOperand(0), L, H);
7756 SDValue DTyOpL = DAG.getValueType(NewVT_Lo);
7757 SDValue DTyOpH = DAG.getValueType(NewVT_Hi);
7758 SDValue STyOpL = DAG.getValueType(L.getValueType());
7759 SDValue STyOpH = DAG.getValueType(H.getValueType());
7761 SDValue RndOp = Node->getOperand(3);
7762 SDValue SatOp = Node->getOperand(4);
7764 Lo = DAG.getConvertRndSat(NewVT_Lo, dl, L, DTyOpL, STyOpL,
7765 RndOp, SatOp, CvtCode);
7766 Hi = DAG.getConvertRndSat(NewVT_Hi, dl, H, DTyOpH, STyOpH,
7767 RndOp, SatOp, CvtCode);
7771 LoadSDNode *LD = cast<LoadSDNode>(Node);
7772 SDValue Ch = LD->getChain();
7773 SDValue Ptr = LD->getBasePtr();
7774 ISD::LoadExtType ExtType = LD->getExtensionType();
7775 const Value *SV = LD->getSrcValue();
7776 int SVOffset = LD->getSrcValueOffset();
7777 MVT MemoryVT = LD->getMemoryVT();
7778 unsigned Alignment = LD->getAlignment();
7779 bool isVolatile = LD->isVolatile();
7781 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7782 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
7784 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7785 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7786 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7788 Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7789 NewVT_Lo, Ch, Ptr, Offset,
7790 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7791 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7792 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
7793 DAG.getIntPtrConstant(IncrementSize));
7794 SVOffset += IncrementSize;
7795 Alignment = MinAlign(Alignment, IncrementSize);
7796 Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7797 NewVT_Hi, Ch, Ptr, Offset,
7798 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7800 // Build a factor node to remember that this load is independent of the
7802 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
7805 // Remember that we legalized the chain.
7806 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7809 case ISD::BIT_CONVERT: {
7810 // We know the result is a vector. The input may be either a vector or a
7812 SDValue InOp = Node->getOperand(0);
7813 if (!InOp.getValueType().isVector() ||
7814 InOp.getValueType().getVectorNumElements() == 1) {
7815 // The input is a scalar or single-element vector.
7816 // Lower to a store/load so that it can be split.
7817 // FIXME: this could be improved probably.
7818 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
7819 Op.getValueType().getTypeForMVT());
7820 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7821 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7823 SDValue St = DAG.getStore(DAG.getEntryNode(), dl,
7825 PseudoSourceValue::getFixedStack(FI), 0);
7826 InOp = DAG.getLoad(Op.getValueType(), dl, St, Ptr,
7827 PseudoSourceValue::getFixedStack(FI), 0);
7829 // Split the vector and convert each of the pieces now.
7830 SplitVectorOp(InOp, Lo, Hi);
7831 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Lo, Lo);
7832 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Hi, Hi);
7837 // Remember in a map if the values will be reused later.
7839 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7840 assert(isNew && "Value already split?!?");
7845 /// ScalarizeVectorOp - Given an operand of single-element vector type
7846 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7847 /// scalar (e.g. f32) value.
7848 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7849 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7850 SDNode *Node = Op.getNode();
7851 DebugLoc dl = Node->getDebugLoc();
7852 MVT NewVT = Op.getValueType().getVectorElementType();
7853 assert(Op.getValueType().getVectorNumElements() == 1);
7855 // See if we already scalarized it.
7856 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7857 if (I != ScalarizedNodes.end()) return I->second;
7860 switch (Node->getOpcode()) {
7863 Node->dump(&DAG); cerr << "\n";
7865 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7882 Result = DAG.getNode(Node->getOpcode(), dl,
7884 ScalarizeVectorOp(Node->getOperand(0)),
7885 ScalarizeVectorOp(Node->getOperand(1)));
7897 case ISD::FP_TO_SINT:
7898 case ISD::FP_TO_UINT:
7899 case ISD::SINT_TO_FP:
7900 case ISD::UINT_TO_FP:
7901 case ISD::SIGN_EXTEND:
7902 case ISD::ZERO_EXTEND:
7903 case ISD::ANY_EXTEND:
7905 case ISD::FP_EXTEND:
7906 Result = DAG.getNode(Node->getOpcode(), dl,
7908 ScalarizeVectorOp(Node->getOperand(0)));
7910 case ISD::CONVERT_RNDSAT: {
7911 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
7912 Result = DAG.getConvertRndSat(NewVT, dl, Op0,
7913 DAG.getValueType(NewVT),
7914 DAG.getValueType(Op0.getValueType()),
7915 Node->getOperand(3),
7916 Node->getOperand(4),
7917 cast<CvtRndSatSDNode>(Node)->getCvtCode());
7922 Result = DAG.getNode(Node->getOpcode(), dl,
7924 ScalarizeVectorOp(Node->getOperand(0)),
7925 Node->getOperand(1));
7928 LoadSDNode *LD = cast<LoadSDNode>(Node);
7929 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7930 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7931 ISD::LoadExtType ExtType = LD->getExtensionType();
7932 const Value *SV = LD->getSrcValue();
7933 int SVOffset = LD->getSrcValueOffset();
7934 MVT MemoryVT = LD->getMemoryVT();
7935 unsigned Alignment = LD->getAlignment();
7936 bool isVolatile = LD->isVolatile();
7938 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7939 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
7941 Result = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7942 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7943 MemoryVT.getVectorElementType(),
7944 isVolatile, Alignment);
7946 // Remember that we legalized the chain.
7947 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7950 case ISD::BUILD_VECTOR:
7951 Result = Node->getOperand(0);
7953 case ISD::INSERT_VECTOR_ELT:
7954 // Returning the inserted scalar element.
7955 Result = Node->getOperand(1);
7957 case ISD::CONCAT_VECTORS:
7958 assert(Node->getOperand(0).getValueType() == NewVT &&
7959 "Concat of non-legal vectors not yet supported!");
7960 Result = Node->getOperand(0);
7962 case ISD::VECTOR_SHUFFLE: {
7963 // Figure out if the scalar is the LHS or RHS and return it.
7964 SDValue EltNum = Node->getOperand(2).getOperand(0);
7965 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7966 Result = ScalarizeVectorOp(Node->getOperand(1));
7968 Result = ScalarizeVectorOp(Node->getOperand(0));
7971 case ISD::EXTRACT_SUBVECTOR:
7972 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT,
7973 Node->getOperand(0), Node->getOperand(1));
7975 case ISD::BIT_CONVERT: {
7976 SDValue Op0 = Op.getOperand(0);
7977 if (Op0.getValueType().getVectorNumElements() == 1)
7978 Op0 = ScalarizeVectorOp(Op0);
7979 Result = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, Op0);
7983 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Op.getOperand(0),
7984 ScalarizeVectorOp(Op.getOperand(1)),
7985 ScalarizeVectorOp(Op.getOperand(2)));
7987 case ISD::SELECT_CC:
7988 Result = DAG.getNode(ISD::SELECT_CC, dl, NewVT, Node->getOperand(0),
7989 Node->getOperand(1),
7990 ScalarizeVectorOp(Op.getOperand(2)),
7991 ScalarizeVectorOp(Op.getOperand(3)),
7992 Node->getOperand(4));
7995 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7996 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7997 Result = DAG.getNode(ISD::SETCC, dl,
7998 TLI.getSetCCResultType(Op0.getValueType()),
7999 Op0, Op1, Op.getOperand(2));
8000 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Result,
8001 DAG.getConstant(-1ULL, NewVT),
8002 DAG.getConstant(0ULL, NewVT));
8007 if (TLI.isTypeLegal(NewVT))
8008 Result = LegalizeOp(Result);
8009 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
8010 assert(isNew && "Value already scalarized?");
8016 SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
8017 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op);
8018 if (I != WidenNodes.end()) return I->second;
8020 MVT VT = Op.getValueType();
8021 assert(VT.isVector() && "Cannot widen non-vector type!");
8024 SDNode *Node = Op.getNode();
8025 DebugLoc dl = Node->getDebugLoc();
8026 MVT EVT = VT.getVectorElementType();
8028 unsigned NumElts = VT.getVectorNumElements();
8029 unsigned NewNumElts = WidenVT.getVectorNumElements();
8030 assert(NewNumElts > NumElts && "Cannot widen to smaller type!");
8031 assert(NewNumElts < 17);
8033 // When widen is called, it is assumed that it is more efficient to use a
8034 // wide type. The default action is to widen to operation to a wider legal
8035 // vector type and then do the operation if it is legal by calling LegalizeOp
8036 // again. If there is no vector equivalent, we will unroll the operation, do
8037 // it, and rebuild the vector. If most of the operations are vectorizible to
8038 // the legal type, the resulting code will be more efficient. If this is not
8039 // the case, the resulting code will preform badly as we end up generating
8040 // code to pack/unpack the results. It is the function that calls widen
8041 // that is responsible for seeing this doesn't happen.
8042 switch (Node->getOpcode()) {
8047 assert(0 && "Unexpected operation in WidenVectorOp!");
8049 case ISD::CopyFromReg:
8050 assert(0 && "CopyFromReg doesn't need widening!");
8052 case ISD::ConstantFP:
8053 // To build a vector of these elements, clients should call BuildVector
8054 // and with each element instead of creating a node with a vector type
8055 assert(0 && "Unexpected operation in WidenVectorOp!");
8057 // Variable Arguments with vector types doesn't make any sense to me
8058 assert(0 && "Unexpected operation in WidenVectorOp!");
8061 Result = DAG.getUNDEF(WidenVT);
8063 case ISD::BUILD_VECTOR: {
8064 // Build a vector with undefined for the new nodes
8065 SDValueVector NewOps(Node->op_begin(), Node->op_end());
8066 for (unsigned i = NumElts; i < NewNumElts; ++i) {
8067 NewOps.push_back(DAG.getUNDEF(EVT));
8069 Result = DAG.getBUILD_VECTOR(WidenVT, dl, &NewOps[0], NewOps.size());
8072 case ISD::INSERT_VECTOR_ELT: {
8073 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8074 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WidenVT, Tmp1,
8075 Node->getOperand(1), Node->getOperand(2));
8078 case ISD::VECTOR_SHUFFLE: {
8079 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8080 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8081 // VECTOR_SHUFFLE 3rd operand must be a constant build vector that is
8082 // used as permutation array. We build the vector here instead of widening
8083 // because we don't want to legalize and have it turned to something else.
8084 SDValue PermOp = Node->getOperand(2);
8085 SDValueVector NewOps;
8086 MVT PVT = PermOp.getValueType().getVectorElementType();
8087 for (unsigned i = 0; i < NumElts; ++i) {
8088 if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) {
8089 NewOps.push_back(PermOp.getOperand(i));
8092 cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue();
8093 if (Idx < NumElts) {
8094 NewOps.push_back(PermOp.getOperand(i));
8097 NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts,
8098 PermOp.getOperand(i).getValueType()));
8102 for (unsigned i = NumElts; i < NewNumElts; ++i) {
8103 NewOps.push_back(DAG.getUNDEF(PVT));
8106 SDValue Tmp3 = DAG.getBUILD_VECTOR(MVT::getVectorVT(PVT, NewOps.size()), dl,
8107 &NewOps[0], NewOps.size());
8109 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, WidenVT, Tmp1, Tmp2, Tmp3);
8113 // If the load widen returns true, we can use a single load for the
8114 // vector. Otherwise, it is returning a token factor for multiple
8117 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT))
8118 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1)));
8120 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0)));
8124 case ISD::BIT_CONVERT: {
8125 SDValue Tmp1 = Node->getOperand(0);
8126 // Converts between two different types so we need to determine
8127 // the correct widen type for the input operand.
8128 MVT InVT = Tmp1.getValueType();
8129 unsigned WidenSize = WidenVT.getSizeInBits();
8130 if (InVT.isVector()) {
8131 MVT InEltVT = InVT.getVectorElementType();
8132 unsigned InEltSize = InEltVT.getSizeInBits();
8133 assert(WidenSize % InEltSize == 0 &&
8134 "can not widen bit convert that are not multiple of element type");
8135 MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize);
8136 Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT);
8137 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
8138 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Tmp1);
8140 // If the result size is a multiple of the input size, widen the input
8141 // and then convert.
8142 unsigned InSize = InVT.getSizeInBits();
8143 assert(WidenSize % InSize == 0 &&
8144 "can not widen bit convert that are not multiple of element type");
8145 unsigned NewNumElts = WidenSize / InSize;
8146 SmallVector<SDValue, 16> Ops(NewNumElts);
8147 SDValue UndefVal = DAG.getUNDEF(InVT);
8149 for (unsigned i = 1; i < NewNumElts; ++i)
8152 MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts);
8153 Result = DAG.getBUILD_VECTOR(NewInVT, dl, &Ops[0], NewNumElts);
8154 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Result);
8159 case ISD::SINT_TO_FP:
8160 case ISD::UINT_TO_FP:
8161 case ISD::FP_TO_SINT:
8162 case ISD::FP_TO_UINT:
8163 case ISD::FP_ROUND: {
8164 SDValue Tmp1 = Node->getOperand(0);
8165 // Converts between two different types so we need to determine
8166 // the correct widen type for the input operand.
8167 MVT TVT = Tmp1.getValueType();
8168 assert(TVT.isVector() && "can not widen non vector type");
8169 MVT TEVT = TVT.getVectorElementType();
8170 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts);
8171 Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
8172 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts);
8173 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
8177 case ISD::FP_EXTEND:
8178 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
8180 case ISD::SIGN_EXTEND:
8181 case ISD::ZERO_EXTEND:
8182 case ISD::ANY_EXTEND:
8183 case ISD::SIGN_EXTEND_INREG:
8192 // Unary op widening
8194 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8195 assert(Tmp1.getValueType() == WidenVT);
8196 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
8199 case ISD::CONVERT_RNDSAT: {
8200 SDValue RndOp = Node->getOperand(3);
8201 SDValue SatOp = Node->getOperand(4);
8202 SDValue SrcOp = Node->getOperand(0);
8204 // Converts between two different types so we need to determine
8205 // the correct widen type for the input operand.
8206 MVT SVT = SrcOp.getValueType();
8207 assert(SVT.isVector() && "can not widen non vector type");
8208 MVT SEVT = SVT.getVectorElementType();
8209 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts);
8211 SrcOp = WidenVectorOp(SrcOp, SWidenVT);
8212 assert(SrcOp.getValueType() == WidenVT);
8213 SDValue DTyOp = DAG.getValueType(WidenVT);
8214 SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
8215 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
8217 Result = DAG.getConvertRndSat(WidenVT, dl, SrcOp, DTyOp, STyOp,
8218 RndOp, SatOp, CvtCode);
8238 case ISD::FCOPYSIGN:
8242 // Binary op widening
8243 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8244 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8245 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8246 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2);
8253 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8254 assert(Tmp1.getValueType() == WidenVT);
8255 SDValue ShOp = Node->getOperand(1);
8256 MVT ShVT = ShOp.getValueType();
8257 MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(),
8258 WidenVT.getVectorNumElements());
8259 ShOp = WidenVectorOp(ShOp, NewShVT);
8260 assert(ShOp.getValueType() == NewShVT);
8261 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, ShOp);
8265 case ISD::EXTRACT_VECTOR_ELT: {
8266 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8267 assert(Tmp1.getValueType() == WidenVT);
8268 Result = DAG.getNode(Node->getOpcode(), dl, EVT, Tmp1, Node->getOperand(1));
8271 case ISD::CONCAT_VECTORS: {
8272 // We concurrently support only widen on a multiple of the incoming vector.
8273 // We could widen on a multiple of the incoming operand if necessary.
8274 unsigned NumConcat = NewNumElts / NumElts;
8275 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
8276 SDValue UndefVal = DAG.getUNDEF(VT);
8277 SmallVector<SDValue, 8> MOps;
8279 for (unsigned i = 1; i != NumConcat; ++i) {
8280 MOps.push_back(UndefVal);
8282 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
8283 &MOps[0], MOps.size()));
8286 case ISD::EXTRACT_SUBVECTOR: {
8287 SDValue Tmp1 = Node->getOperand(0);
8288 SDValue Idx = Node->getOperand(1);
8289 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
8290 if (CIdx && CIdx->getZExtValue() == 0) {
8291 // Since we are access the start of the vector, the incoming
8292 // vector type might be the proper.
8293 MVT Tmp1VT = Tmp1.getValueType();
8294 if (Tmp1VT == WidenVT)
8297 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements();
8298 if (Tmp1VTNumElts < NewNumElts)
8299 Result = WidenVectorOp(Tmp1, WidenVT);
8301 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, Tmp1, Idx);
8303 } else if (NewNumElts % NumElts == 0) {
8304 // Widen the extracted subvector.
8305 unsigned NumConcat = NewNumElts / NumElts;
8306 SDValue UndefVal = DAG.getUNDEF(VT);
8307 SmallVector<SDValue, 8> MOps;
8309 for (unsigned i = 1; i != NumConcat; ++i) {
8310 MOps.push_back(UndefVal);
8312 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
8313 &MOps[0], MOps.size()));
8315 assert(0 && "can not widen extract subvector");
8316 // This could be implemented using insert and build vector but I would
8317 // like to see when this happens.
8323 // Determine new condition widen type and widen
8324 SDValue Cond1 = Node->getOperand(0);
8325 MVT CondVT = Cond1.getValueType();
8326 assert(CondVT.isVector() && "can not widen non vector type");
8327 MVT CondEVT = CondVT.getVectorElementType();
8328 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8329 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8330 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen");
8332 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT);
8333 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT);
8334 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8335 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Tmp1, Tmp2);
8339 case ISD::SELECT_CC: {
8340 // Determine new condition widen type and widen
8341 SDValue Cond1 = Node->getOperand(0);
8342 SDValue Cond2 = Node->getOperand(1);
8343 MVT CondVT = Cond1.getValueType();
8344 assert(CondVT.isVector() && "can not widen non vector type");
8345 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs");
8346 MVT CondEVT = CondVT.getVectorElementType();
8347 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8348 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8349 Cond2 = WidenVectorOp(Cond2, CondWidenVT);
8350 assert(Cond1.getValueType() == CondWidenVT &&
8351 Cond2.getValueType() == CondWidenVT && "condition not widen");
8353 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT);
8354 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT);
8355 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT &&
8356 "operands not widen");
8357 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Cond2, Tmp1,
8358 Tmp2, Node->getOperand(4));
8362 // Determine widen for the operand
8363 SDValue Tmp1 = Node->getOperand(0);
8364 MVT TmpVT = Tmp1.getValueType();
8365 assert(TmpVT.isVector() && "can not widen non vector type");
8366 MVT TmpEVT = TmpVT.getVectorElementType();
8367 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts);
8368 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT);
8369 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT);
8370 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2,
8371 Node->getOperand(2));
8374 case ISD::ATOMIC_CMP_SWAP:
8375 case ISD::ATOMIC_LOAD_ADD:
8376 case ISD::ATOMIC_LOAD_SUB:
8377 case ISD::ATOMIC_LOAD_AND:
8378 case ISD::ATOMIC_LOAD_OR:
8379 case ISD::ATOMIC_LOAD_XOR:
8380 case ISD::ATOMIC_LOAD_NAND:
8381 case ISD::ATOMIC_LOAD_MIN:
8382 case ISD::ATOMIC_LOAD_MAX:
8383 case ISD::ATOMIC_LOAD_UMIN:
8384 case ISD::ATOMIC_LOAD_UMAX:
8385 case ISD::ATOMIC_SWAP: {
8386 // For now, we assume that using vectors for these operations don't make
8387 // much sense so we just split it. We return an empty result
8389 SplitVectorOp(Op, X, Y);
8394 } // end switch (Node->getOpcode())
8396 assert(Result.getNode() && "Didn't set a result!");
8398 Result = LegalizeOp(Result);
8400 AddWidenedOperand(Op, Result);
8404 // Utility function to find a legal vector type and its associated element
8405 // type from a preferred width and whose vector type must be the same size
8407 // TLI: Target lowering used to determine legal types
8408 // Width: Preferred width of element type
8409 // VVT: Vector value type whose size we must match.
8410 // Returns VecEVT and EVT - the vector type and its associated element type
8411 static void FindWidenVecType(const TargetLowering &TLI, unsigned Width, MVT VVT,
8412 MVT& EVT, MVT& VecEVT) {
8413 // We start with the preferred width, make it a power of 2 and see if
8414 // we can find a vector type of that width. If not, we reduce it by
8415 // another power of 2. If we have widen the type, a vector of bytes should
8417 assert(TLI.isTypeLegal(VVT));
8418 unsigned EWidth = Width + 1;
8421 EWidth = (1 << Log2_32(EWidth-1));
8422 EVT = MVT::getIntegerVT(EWidth);
8423 unsigned NumEVT = VVT.getSizeInBits()/EWidth;
8424 VecEVT = MVT::getVectorVT(EVT, NumEVT);
8425 } while (!TLI.isTypeLegal(VecEVT) ||
8426 VVT.getSizeInBits() != VecEVT.getSizeInBits());
8429 SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
8439 // We assume that we have good rules to handle loading power of two loads so
8440 // we break down the operations to power of 2 loads. The strategy is to
8441 // load the largest power of 2 that we can easily transform to a legal vector
8442 // and then insert into that vector, and the cast the result into the legal
8443 // vector that we want. This avoids unnecessary stack converts.
8444 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
8445 // the load is nonvolatile, we an use a wider load for the value.
8446 // Find a vector length we can load a large chunk
8449 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8450 EVTWidth = EVT.getSizeInBits();
8452 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV, SVOffset,
8453 isVolatile, Alignment);
8454 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecEVT, LdOp);
8455 LdChain.push_back(LdOp.getValue(1));
8457 // Check if we can load the element with one instruction
8458 if (LdWidth == EVTWidth) {
8459 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
8462 // The vector element order is endianness dependent.
8464 LdWidth -= EVTWidth;
8465 unsigned Offset = 0;
8467 while (LdWidth > 0) {
8468 unsigned Increment = EVTWidth / 8;
8469 Offset += Increment;
8470 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8471 DAG.getIntPtrConstant(Increment));
8473 if (LdWidth < EVTWidth) {
8474 // Our current type we are using is too large, use a smaller size by
8475 // using a smaller power of 2
8476 unsigned oEVTWidth = EVTWidth;
8477 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8478 EVTWidth = EVT.getSizeInBits();
8479 // Readjust position and vector position based on new load type
8480 Idx = Idx * (oEVTWidth/EVTWidth);
8481 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
8484 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV,
8485 SVOffset+Offset, isVolatile,
8486 MinAlign(Alignment, Offset));
8487 LdChain.push_back(LdOp.getValue(1));
8488 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecEVT, VecOp, LdOp,
8489 DAG.getIntPtrConstant(Idx++));
8491 LdWidth -= EVTWidth;
8494 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
8497 bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
8501 // TODO: Add support for ConcatVec and the ability to load many vector
8502 // types (e.g., v4i8). This will not work when a vector register
8503 // to memory mapping is strange (e.g., vector elements are not
8504 // stored in some sequential order).
8506 // It must be true that the widen vector type is bigger than where
8507 // we need to load from.
8508 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
8509 MVT LdVT = LD->getMemoryVT();
8510 DebugLoc dl = LD->getDebugLoc();
8511 assert(LdVT.isVector() && NVT.isVector());
8512 assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
8515 SDValue Chain = LD->getChain();
8516 SDValue BasePtr = LD->getBasePtr();
8517 int SVOffset = LD->getSrcValueOffset();
8518 unsigned Alignment = LD->getAlignment();
8519 bool isVolatile = LD->isVolatile();
8520 const Value *SV = LD->getSrcValue();
8521 unsigned int LdWidth = LdVT.getSizeInBits();
8523 // Load value as a large register
8524 SDValueVector LdChain;
8525 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
8526 Alignment, isVolatile, LdWidth, NVT, dl);
8528 if (LdChain.size() == 1) {
8533 TFOp=DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8534 &LdChain[0], LdChain.size());
8540 void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
8550 // Breaks the stores into a series of power of 2 width stores. For any
8551 // width, we convert the vector to the vector of element size that we
8552 // want to store. This avoids requiring a stack convert.
8554 // Find a width of the element type we can store with
8555 MVT VVT = ValOp.getValueType();
8558 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8559 EVTWidth = EVT.getSizeInBits();
8561 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, ValOp);
8562 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
8563 DAG.getIntPtrConstant(0));
8564 SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset,
8565 isVolatile, Alignment);
8566 StChain.push_back(StOp);
8568 // Check if we are done
8569 if (StWidth == EVTWidth) {
8574 StWidth -= EVTWidth;
8575 unsigned Offset = 0;
8577 while (StWidth > 0) {
8578 unsigned Increment = EVTWidth / 8;
8579 Offset += Increment;
8580 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8581 DAG.getIntPtrConstant(Increment));
8583 if (StWidth < EVTWidth) {
8584 // Our current type we are using is too large, use a smaller size by
8585 // using a smaller power of 2
8586 unsigned oEVTWidth = EVTWidth;
8587 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8588 EVTWidth = EVT.getSizeInBits();
8589 // Readjust position and vector position based on new load type
8590 Idx = Idx * (oEVTWidth/EVTWidth);
8591 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
8594 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
8595 DAG.getIntPtrConstant(Idx++));
8596 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
8597 SVOffset + Offset, isVolatile,
8598 MinAlign(Alignment, Offset)));
8599 StWidth -= EVTWidth;
8604 SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
8607 // TODO: It might be cleaner if we can use SplitVector and have more legal
8608 // vector types that can be stored into memory (e.g., v4xi8 can
8609 // be stored as a word). This will not work when a vector register
8610 // to memory mapping is strange (e.g., vector elements are not
8611 // stored in some sequential order).
8613 MVT StVT = ST->getMemoryVT();
8614 SDValue ValOp = ST->getValue();
8615 DebugLoc dl = ST->getDebugLoc();
8617 // Check if we have widen this node with another value
8618 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
8619 if (I != WidenNodes.end())
8622 MVT VVT = ValOp.getValueType();
8624 // It must be true that we the widen vector type is bigger than where
8625 // we need to store.
8626 assert(StVT.isVector() && VVT.isVector());
8627 assert(StVT.bitsLT(VVT));
8628 assert(StVT.getVectorElementType() == VVT.getVectorElementType());
8631 SDValueVector StChain;
8632 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(),
8633 ST->getSrcValueOffset(), ST->getAlignment(),
8634 ST->isVolatile(), ValOp, StVT.getSizeInBits(), dl);
8635 if (StChain.size() == 1)
8638 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8639 &StChain[0], StChain.size());
8643 // SelectionDAG::Legalize - This is the entry point for the file.
8645 void SelectionDAG::Legalize(bool TypesNeedLegalizing, bool Fast) {
8646 /// run - This is the main entry point to this class.
8648 SelectionDAGLegalize(*this, TypesNeedLegalizing, Fast).LegalizeDAG();