1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/SetVector.h"
16 #include "llvm/ADT/SmallPtrSet.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/Analysis.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineJumpTableInfo.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/DebugInfo.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetSubtargetInfo.h"
40 #define DEBUG_TYPE "legalizedag"
42 //===----------------------------------------------------------------------===//
43 /// This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class SelectionDAGLegalize {
56 const TargetMachine &TM;
57 const TargetLowering &TLI;
60 /// \brief The set of nodes which have already been legalized. We hold a
61 /// reference to it in order to update as necessary on node deletion.
62 SmallPtrSetImpl<SDNode *> &LegalizedNodes;
64 /// \brief A set of all the nodes updated during legalization.
65 SmallSetVector<SDNode *, 16> *UpdatedNodes;
67 EVT getSetCCResultType(EVT VT) const {
68 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
71 // Libcall insertion helpers.
74 SelectionDAGLegalize(SelectionDAG &DAG,
75 SmallPtrSetImpl<SDNode *> &LegalizedNodes,
76 SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
77 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
78 LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
80 /// \brief Legalizes the given operation.
81 void LegalizeOp(SDNode *Node);
84 SDValue OptimizeFloatStore(StoreSDNode *ST);
86 void LegalizeLoadOps(SDNode *Node);
87 void LegalizeStoreOps(SDNode *Node);
89 /// Some targets cannot handle a variable
90 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
91 /// is necessary to spill the vector being inserted into to memory, perform
92 /// the insert there, and then read the result back.
93 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
94 SDValue Idx, SDLoc dl);
95 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
96 SDValue Idx, SDLoc dl);
98 /// Return a vector shuffle operation which
99 /// performs the same shuffe in terms of order or result bytes, but on a type
100 /// whose vector element type is narrower than the original shuffle type.
101 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
102 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
103 SDValue N1, SDValue N2,
104 ArrayRef<int> Mask) const;
106 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
107 bool &NeedInvert, SDLoc dl);
109 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
110 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
111 unsigned NumOps, bool isSigned, SDLoc dl);
113 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
114 SDNode *Node, bool isSigned);
115 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
116 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
117 RTLIB::Libcall Call_F128,
118 RTLIB::Libcall Call_PPCF128);
119 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
120 RTLIB::Libcall Call_I8,
121 RTLIB::Libcall Call_I16,
122 RTLIB::Libcall Call_I32,
123 RTLIB::Libcall Call_I64,
124 RTLIB::Libcall Call_I128);
125 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
126 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
128 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
129 SDValue ExpandBUILD_VECTOR(SDNode *Node);
130 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
131 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
132 SmallVectorImpl<SDValue> &Results);
133 SDValue ExpandFCOPYSIGN(SDNode *Node);
134 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
136 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
138 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
141 SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
142 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
144 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
145 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
146 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
148 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
150 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
152 void ExpandNode(SDNode *Node);
153 void PromoteNode(SDNode *Node);
156 // Node replacement helpers
157 void ReplacedNode(SDNode *N) {
158 LegalizedNodes.erase(N);
160 UpdatedNodes->insert(N);
162 void ReplaceNode(SDNode *Old, SDNode *New) {
163 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
164 dbgs() << " with: "; New->dump(&DAG));
166 assert(Old->getNumValues() == New->getNumValues() &&
167 "Replacing one node with another that produces a different number "
169 DAG.ReplaceAllUsesWith(Old, New);
170 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i)
171 DAG.TransferDbgValues(SDValue(Old, i), SDValue(New, i));
173 UpdatedNodes->insert(New);
176 void ReplaceNode(SDValue Old, SDValue New) {
177 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
178 dbgs() << " with: "; New->dump(&DAG));
180 DAG.ReplaceAllUsesWith(Old, New);
181 DAG.TransferDbgValues(Old, New);
183 UpdatedNodes->insert(New.getNode());
184 ReplacedNode(Old.getNode());
186 void ReplaceNode(SDNode *Old, const SDValue *New) {
187 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
189 DAG.ReplaceAllUsesWith(Old, New);
190 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
191 DEBUG(dbgs() << (i == 0 ? " with: "
194 DAG.TransferDbgValues(SDValue(Old, i), New[i]);
196 UpdatedNodes->insert(New[i].getNode());
203 /// Return a vector shuffle operation which
204 /// performs the same shuffe in terms of order or result bytes, but on a type
205 /// whose vector element type is narrower than the original shuffle type.
206 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
208 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
209 SDValue N1, SDValue N2,
210 ArrayRef<int> Mask) const {
211 unsigned NumMaskElts = VT.getVectorNumElements();
212 unsigned NumDestElts = NVT.getVectorNumElements();
213 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
215 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
217 if (NumEltsGrowth == 1)
218 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
220 SmallVector<int, 8> NewMask;
221 for (unsigned i = 0; i != NumMaskElts; ++i) {
223 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
225 NewMask.push_back(-1);
227 NewMask.push_back(Idx * NumEltsGrowth + j);
230 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
231 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
232 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
235 /// Expands the ConstantFP node to an integer constant or
236 /// a load from the constant pool.
238 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
242 // If a FP immediate is precise when represented as a float and if the
243 // target can do an extending load from float to double, we put it into
244 // the constant pool as a float, even if it's is statically typed as a
245 // double. This shrinks FP constants and canonicalizes them for targets where
246 // an FP extending load is the same cost as a normal load (such as on the x87
247 // fp stack or PPC FP unit).
248 EVT VT = CFP->getValueType(0);
249 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
251 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
252 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), dl,
253 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
258 while (SVT != MVT::f32 && SVT != MVT::f16) {
259 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
260 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
261 // Only do this if the target has a native EXTLOAD instruction from
263 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
264 TLI.ShouldShrinkFPConstant(OrigVT)) {
265 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
266 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
273 DAG.getConstantPool(LLVMC, TLI.getPointerTy(DAG.getDataLayout()));
274 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
276 SDValue Result = DAG.getExtLoad(
277 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx,
278 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), VT,
279 false, false, false, Alignment);
283 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
284 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
285 false, false, false, Alignment);
289 /// Expands an unaligned store to 2 half-size stores.
290 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
291 const TargetLowering &TLI,
292 SelectionDAGLegalize *DAGLegalize) {
293 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
294 "unaligned indexed stores not implemented!");
295 SDValue Chain = ST->getChain();
296 SDValue Ptr = ST->getBasePtr();
297 SDValue Val = ST->getValue();
298 EVT VT = Val.getValueType();
299 int Alignment = ST->getAlignment();
300 unsigned AS = ST->getAddressSpace();
303 if (ST->getMemoryVT().isFloatingPoint() ||
304 ST->getMemoryVT().isVector()) {
305 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
306 if (TLI.isTypeLegal(intVT)) {
307 // Expand to a bitconvert of the value to the integer type of the
308 // same size, then a (misaligned) int store.
309 // FIXME: Does not handle truncating floating point stores!
310 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
311 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
312 ST->isVolatile(), ST->isNonTemporal(), Alignment);
313 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
316 // Do a (aligned) store to a stack slot, then copy from the stack slot
317 // to the final destination using (unaligned) integer loads and stores.
318 EVT StoredVT = ST->getMemoryVT();
320 TLI.getRegisterType(*DAG.getContext(),
321 EVT::getIntegerVT(*DAG.getContext(),
322 StoredVT.getSizeInBits()));
323 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
324 unsigned RegBytes = RegVT.getSizeInBits() / 8;
325 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
327 // Make sure the stack slot is also aligned for the register type.
328 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
330 // Perform the original store, only redirected to the stack slot.
331 SDValue Store = DAG.getTruncStore(Chain, dl,
332 Val, StackPtr, MachinePointerInfo(),
333 StoredVT, false, false, 0);
334 SDValue Increment = DAG.getConstant(
335 RegBytes, dl, TLI.getPointerTy(DAG.getDataLayout(), AS));
336 SmallVector<SDValue, 8> Stores;
339 // Do all but one copies using the full register width.
340 for (unsigned i = 1; i < NumRegs; i++) {
341 // Load one integer register's worth from the stack slot.
342 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
343 MachinePointerInfo(),
344 false, false, false, 0);
345 // Store it to the final location. Remember the store.
346 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
347 ST->getPointerInfo().getWithOffset(Offset),
348 ST->isVolatile(), ST->isNonTemporal(),
349 MinAlign(ST->getAlignment(), Offset)));
350 // Increment the pointers.
352 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
354 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
357 // The last store may be partial. Do a truncating store. On big-endian
358 // machines this requires an extending load from the stack slot to ensure
359 // that the bits are in the right place.
360 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
361 8 * (StoredBytes - Offset));
363 // Load from the stack slot.
364 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
365 MachinePointerInfo(),
366 MemVT, false, false, false, 0);
368 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
370 .getWithOffset(Offset),
371 MemVT, ST->isVolatile(),
373 MinAlign(ST->getAlignment(), Offset),
375 // The order of the stores doesn't matter - say it with a TokenFactor.
376 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
377 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
380 assert(ST->getMemoryVT().isInteger() &&
381 !ST->getMemoryVT().isVector() &&
382 "Unaligned store of unknown type.");
383 // Get the half-size VT
384 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
385 int NumBits = NewStoredVT.getSizeInBits();
386 int IncrementSize = NumBits / 8;
388 // Divide the stored value in two parts.
389 SDValue ShiftAmount =
390 DAG.getConstant(NumBits, dl, TLI.getShiftAmountTy(Val.getValueType(),
391 DAG.getDataLayout()));
393 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
395 // Store the two parts
396 SDValue Store1, Store2;
397 Store1 = DAG.getTruncStore(Chain, dl,
398 DAG.getDataLayout().isLittleEndian() ? Lo : Hi,
399 Ptr, ST->getPointerInfo(), NewStoredVT,
400 ST->isVolatile(), ST->isNonTemporal(), Alignment);
402 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
403 DAG.getConstant(IncrementSize, dl,
404 TLI.getPointerTy(DAG.getDataLayout(), AS)));
405 Alignment = MinAlign(Alignment, IncrementSize);
406 Store2 = DAG.getTruncStore(
407 Chain, dl, DAG.getDataLayout().isLittleEndian() ? Hi : Lo, Ptr,
408 ST->getPointerInfo().getWithOffset(IncrementSize), NewStoredVT,
409 ST->isVolatile(), ST->isNonTemporal(), Alignment, ST->getAAInfo());
412 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
413 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
416 /// Expands an unaligned load to 2 half-size loads.
418 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
419 const TargetLowering &TLI,
420 SDValue &ValResult, SDValue &ChainResult) {
421 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
422 "unaligned indexed loads not implemented!");
423 SDValue Chain = LD->getChain();
424 SDValue Ptr = LD->getBasePtr();
425 EVT VT = LD->getValueType(0);
426 EVT LoadedVT = LD->getMemoryVT();
428 if (VT.isFloatingPoint() || VT.isVector()) {
429 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
430 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
431 // Expand to a (misaligned) integer load of the same size,
432 // then bitconvert to floating point or vector.
433 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
434 LD->getMemOperand());
435 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
437 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
438 ISD::ANY_EXTEND, dl, VT, Result);
441 ChainResult = newLoad.getValue(1);
445 // Copy the value to a (aligned) stack slot using (unaligned) integer
446 // loads and stores, then do a (aligned) load from the stack slot.
447 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
448 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
449 unsigned RegBytes = RegVT.getSizeInBits() / 8;
450 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
452 // Make sure the stack slot is also aligned for the register type.
453 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
456 DAG.getConstant(RegBytes, dl, TLI.getPointerTy(DAG.getDataLayout()));
457 SmallVector<SDValue, 8> Stores;
458 SDValue StackPtr = StackBase;
461 // Do all but one copies using the full register width.
462 for (unsigned i = 1; i < NumRegs; i++) {
463 // Load one integer register's worth from the original location.
464 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
465 LD->getPointerInfo().getWithOffset(Offset),
466 LD->isVolatile(), LD->isNonTemporal(),
468 MinAlign(LD->getAlignment(), Offset),
470 // Follow the load with a store to the stack slot. Remember the store.
471 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
472 MachinePointerInfo(), false, false, 0));
473 // Increment the pointers.
475 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
476 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
480 // The last copy may be partial. Do an extending load.
481 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
482 8 * (LoadedBytes - Offset));
483 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
484 LD->getPointerInfo().getWithOffset(Offset),
485 MemVT, LD->isVolatile(),
488 MinAlign(LD->getAlignment(), Offset),
490 // Follow the load with a store to the stack slot. Remember the store.
491 // On big-endian machines this requires a truncating store to ensure
492 // that the bits end up in the right place.
493 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
494 MachinePointerInfo(), MemVT,
497 // The order of the stores doesn't matter - say it with a TokenFactor.
498 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
500 // Finally, perform the original load only redirected to the stack slot.
501 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
502 MachinePointerInfo(), LoadedVT, false,false, false,
505 // Callers expect a MERGE_VALUES node.
510 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
511 "Unaligned load of unsupported type.");
513 // Compute the new VT that is half the size of the old one. This is an
515 unsigned NumBits = LoadedVT.getSizeInBits();
517 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
520 unsigned Alignment = LD->getAlignment();
521 unsigned IncrementSize = NumBits / 8;
522 ISD::LoadExtType HiExtType = LD->getExtensionType();
524 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
525 if (HiExtType == ISD::NON_EXTLOAD)
526 HiExtType = ISD::ZEXTLOAD;
528 // Load the value in two parts
530 if (DAG.getDataLayout().isLittleEndian()) {
531 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
532 NewLoadedVT, LD->isVolatile(),
533 LD->isNonTemporal(), LD->isInvariant(), Alignment,
535 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
536 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
537 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
538 LD->getPointerInfo().getWithOffset(IncrementSize),
539 NewLoadedVT, LD->isVolatile(),
540 LD->isNonTemporal(),LD->isInvariant(),
541 MinAlign(Alignment, IncrementSize), LD->getAAInfo());
543 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
544 NewLoadedVT, LD->isVolatile(),
545 LD->isNonTemporal(), LD->isInvariant(), Alignment,
547 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
548 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
549 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
550 LD->getPointerInfo().getWithOffset(IncrementSize),
551 NewLoadedVT, LD->isVolatile(),
552 LD->isNonTemporal(), LD->isInvariant(),
553 MinAlign(Alignment, IncrementSize), LD->getAAInfo());
556 // aggregate the two parts
557 SDValue ShiftAmount =
558 DAG.getConstant(NumBits, dl, TLI.getShiftAmountTy(Hi.getValueType(),
559 DAG.getDataLayout()));
560 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
561 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
563 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
570 /// Some target cannot handle a variable insertion index for the
571 /// INSERT_VECTOR_ELT instruction. In this case, it
572 /// is necessary to spill the vector being inserted into to memory, perform
573 /// the insert there, and then read the result back.
574 SDValue SelectionDAGLegalize::
575 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
581 // If the target doesn't support this, we have to spill the input vector
582 // to a temporary stack slot, update the element, then reload it. This is
583 // badness. We could also load the value into a vector register (either
584 // with a "move to register" or "extload into register" instruction, then
585 // permute it into place, if the idx is a constant and if the idx is
586 // supported by the target.
587 EVT VT = Tmp1.getValueType();
588 EVT EltVT = VT.getVectorElementType();
589 EVT IdxVT = Tmp3.getValueType();
590 EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
591 SDValue StackPtr = DAG.CreateStackTemporary(VT);
593 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
596 SDValue Ch = DAG.getStore(
597 DAG.getEntryNode(), dl, Tmp1, StackPtr,
598 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI), false,
601 // Truncate or zero extend offset to target pointer type.
602 Tmp3 = DAG.getZExtOrTrunc(Tmp3, dl, PtrVT);
603 // Add the offset to the index.
604 unsigned EltSize = EltVT.getSizeInBits()/8;
605 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,
606 DAG.getConstant(EltSize, dl, IdxVT));
607 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
608 // Store the scalar value.
609 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
611 // Load the updated vector.
612 return DAG.getLoad(VT, dl, Ch, StackPtr, MachinePointerInfo::getFixedStack(
613 DAG.getMachineFunction(), SPFI),
614 false, false, false, 0);
618 SDValue SelectionDAGLegalize::
619 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
620 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
621 // SCALAR_TO_VECTOR requires that the type of the value being inserted
622 // match the element type of the vector being created, except for
623 // integers in which case the inserted value can be over width.
624 EVT EltVT = Vec.getValueType().getVectorElementType();
625 if (Val.getValueType() == EltVT ||
626 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
627 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
628 Vec.getValueType(), Val);
630 unsigned NumElts = Vec.getValueType().getVectorNumElements();
631 // We generate a shuffle of InVec and ScVec, so the shuffle mask
632 // should be 0,1,2,3,4,5... with the appropriate element replaced with
634 SmallVector<int, 8> ShufOps;
635 for (unsigned i = 0; i != NumElts; ++i)
636 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
638 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
642 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
645 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
646 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
647 // FIXME: We shouldn't do this for TargetConstantFP's.
648 // FIXME: move this to the DAG Combiner! Note that we can't regress due
649 // to phase ordering between legalized code and the dag combiner. This
650 // probably means that we need to integrate dag combiner and legalizer
652 // We generally can't do this one for long doubles.
653 SDValue Chain = ST->getChain();
654 SDValue Ptr = ST->getBasePtr();
655 unsigned Alignment = ST->getAlignment();
656 bool isVolatile = ST->isVolatile();
657 bool isNonTemporal = ST->isNonTemporal();
658 AAMDNodes AAInfo = ST->getAAInfo();
660 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
661 if (CFP->getValueType(0) == MVT::f32 &&
662 TLI.isTypeLegal(MVT::i32)) {
663 SDValue Con = DAG.getConstant(CFP->getValueAPF().
664 bitcastToAPInt().zextOrTrunc(32),
665 SDLoc(CFP), MVT::i32);
666 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
667 isVolatile, isNonTemporal, Alignment, AAInfo);
670 if (CFP->getValueType(0) == MVT::f64) {
671 // If this target supports 64-bit registers, do a single 64-bit store.
672 if (TLI.isTypeLegal(MVT::i64)) {
673 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
674 zextOrTrunc(64), SDLoc(CFP), MVT::i64);
675 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
676 isVolatile, isNonTemporal, Alignment, AAInfo);
679 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
680 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
681 // stores. If the target supports neither 32- nor 64-bits, this
682 // xform is certainly not worth it.
683 const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt();
684 SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32);
685 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32);
686 if (DAG.getDataLayout().isBigEndian())
689 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
690 isNonTemporal, Alignment, AAInfo);
691 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
692 DAG.getConstant(4, dl, Ptr.getValueType()));
693 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
694 ST->getPointerInfo().getWithOffset(4),
695 isVolatile, isNonTemporal, MinAlign(Alignment, 4U),
698 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
702 return SDValue(nullptr, 0);
705 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
706 StoreSDNode *ST = cast<StoreSDNode>(Node);
707 SDValue Chain = ST->getChain();
708 SDValue Ptr = ST->getBasePtr();
711 unsigned Alignment = ST->getAlignment();
712 bool isVolatile = ST->isVolatile();
713 bool isNonTemporal = ST->isNonTemporal();
714 AAMDNodes AAInfo = ST->getAAInfo();
716 if (!ST->isTruncatingStore()) {
717 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
718 ReplaceNode(ST, OptStore);
723 SDValue Value = ST->getValue();
724 MVT VT = Value.getSimpleValueType();
725 switch (TLI.getOperationAction(ISD::STORE, VT)) {
726 default: llvm_unreachable("This action is not supported yet!");
727 case TargetLowering::Legal: {
728 // If this is an unaligned store and the target doesn't support it,
730 EVT MemVT = ST->getMemoryVT();
731 unsigned AS = ST->getAddressSpace();
732 unsigned Align = ST->getAlignment();
733 const DataLayout &DL = DAG.getDataLayout();
734 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
735 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
738 case TargetLowering::Custom: {
739 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
740 if (Res && Res != SDValue(Node, 0))
741 ReplaceNode(SDValue(Node, 0), Res);
744 case TargetLowering::Promote: {
745 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
746 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
747 "Can only promote stores to same size type");
748 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
750 DAG.getStore(Chain, dl, Value, Ptr,
751 ST->getPointerInfo(), isVolatile,
752 isNonTemporal, Alignment, AAInfo);
753 ReplaceNode(SDValue(Node, 0), Result);
760 SDValue Value = ST->getValue();
762 EVT StVT = ST->getMemoryVT();
763 unsigned StWidth = StVT.getSizeInBits();
764 auto &DL = DAG.getDataLayout();
766 if (StWidth != StVT.getStoreSizeInBits()) {
767 // Promote to a byte-sized store with upper bits zero if not
768 // storing an integral number of bytes. For example, promote
769 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
770 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
771 StVT.getStoreSizeInBits());
772 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
774 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
775 NVT, isVolatile, isNonTemporal, Alignment, AAInfo);
776 ReplaceNode(SDValue(Node, 0), Result);
777 } else if (StWidth & (StWidth - 1)) {
778 // If not storing a power-of-2 number of bits, expand as two stores.
779 assert(!StVT.isVector() && "Unsupported truncstore!");
780 unsigned RoundWidth = 1 << Log2_32(StWidth);
781 assert(RoundWidth < StWidth);
782 unsigned ExtraWidth = StWidth - RoundWidth;
783 assert(ExtraWidth < RoundWidth);
784 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
785 "Store size not an integral number of bytes!");
786 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
787 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
789 unsigned IncrementSize;
791 if (DL.isLittleEndian()) {
792 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
793 // Store the bottom RoundWidth bits.
794 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
796 isVolatile, isNonTemporal, Alignment,
799 // Store the remaining ExtraWidth bits.
800 IncrementSize = RoundWidth / 8;
801 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
802 DAG.getConstant(IncrementSize, dl,
803 Ptr.getValueType()));
805 ISD::SRL, dl, Value.getValueType(), Value,
806 DAG.getConstant(RoundWidth, dl,
807 TLI.getShiftAmountTy(Value.getValueType(), DL)));
808 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
809 ST->getPointerInfo().getWithOffset(IncrementSize),
810 ExtraVT, isVolatile, isNonTemporal,
811 MinAlign(Alignment, IncrementSize), AAInfo);
813 // Big endian - avoid unaligned stores.
814 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
815 // Store the top RoundWidth bits.
817 ISD::SRL, dl, Value.getValueType(), Value,
818 DAG.getConstant(ExtraWidth, dl,
819 TLI.getShiftAmountTy(Value.getValueType(), DL)));
820 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
821 RoundVT, isVolatile, isNonTemporal, Alignment,
824 // Store the remaining ExtraWidth bits.
825 IncrementSize = RoundWidth / 8;
826 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
827 DAG.getConstant(IncrementSize, dl,
828 Ptr.getValueType()));
829 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
830 ST->getPointerInfo().getWithOffset(IncrementSize),
831 ExtraVT, isVolatile, isNonTemporal,
832 MinAlign(Alignment, IncrementSize), AAInfo);
835 // The order of the stores doesn't matter.
836 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
837 ReplaceNode(SDValue(Node, 0), Result);
839 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(),
840 StVT.getSimpleVT())) {
841 default: llvm_unreachable("This action is not supported yet!");
842 case TargetLowering::Legal: {
843 EVT MemVT = ST->getMemoryVT();
844 unsigned AS = ST->getAddressSpace();
845 unsigned Align = ST->getAlignment();
846 // If this is an unaligned store and the target doesn't support it,
848 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
849 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
852 case TargetLowering::Custom: {
853 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
854 if (Res && Res != SDValue(Node, 0))
855 ReplaceNode(SDValue(Node, 0), Res);
858 case TargetLowering::Expand:
859 assert(!StVT.isVector() &&
860 "Vector Stores are handled in LegalizeVectorOps");
862 // TRUNCSTORE:i16 i32 -> STORE i16
863 assert(TLI.isTypeLegal(StVT) &&
864 "Do not know how to expand this store!");
865 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
867 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
868 isVolatile, isNonTemporal, Alignment, AAInfo);
869 ReplaceNode(SDValue(Node, 0), Result);
876 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
877 LoadSDNode *LD = cast<LoadSDNode>(Node);
878 SDValue Chain = LD->getChain(); // The chain.
879 SDValue Ptr = LD->getBasePtr(); // The base pointer.
880 SDValue Value; // The value returned by the load op.
883 ISD::LoadExtType ExtType = LD->getExtensionType();
884 if (ExtType == ISD::NON_EXTLOAD) {
885 MVT VT = Node->getSimpleValueType(0);
886 SDValue RVal = SDValue(Node, 0);
887 SDValue RChain = SDValue(Node, 1);
889 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
890 default: llvm_unreachable("This action is not supported yet!");
891 case TargetLowering::Legal: {
892 EVT MemVT = LD->getMemoryVT();
893 unsigned AS = LD->getAddressSpace();
894 unsigned Align = LD->getAlignment();
895 const DataLayout &DL = DAG.getDataLayout();
896 // If this is an unaligned load and the target doesn't support it,
898 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
899 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
902 case TargetLowering::Custom: {
903 SDValue Res = TLI.LowerOperation(RVal, DAG);
906 RChain = Res.getValue(1);
910 case TargetLowering::Promote: {
911 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
912 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
913 "Can only promote loads to same size type");
915 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
916 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
917 RChain = Res.getValue(1);
921 if (RChain.getNode() != Node) {
922 assert(RVal.getNode() != Node && "Load must be completely replaced");
923 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
924 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
926 UpdatedNodes->insert(RVal.getNode());
927 UpdatedNodes->insert(RChain.getNode());
934 EVT SrcVT = LD->getMemoryVT();
935 unsigned SrcWidth = SrcVT.getSizeInBits();
936 unsigned Alignment = LD->getAlignment();
937 bool isVolatile = LD->isVolatile();
938 bool isNonTemporal = LD->isNonTemporal();
939 bool isInvariant = LD->isInvariant();
940 AAMDNodes AAInfo = LD->getAAInfo();
942 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
943 // Some targets pretend to have an i1 loading operation, and actually
944 // load an i8. This trick is correct for ZEXTLOAD because the top 7
945 // bits are guaranteed to be zero; it helps the optimizers understand
946 // that these bits are zero. It is also useful for EXTLOAD, since it
947 // tells the optimizers that those bits are undefined. It would be
948 // nice to have an effective generic way of getting these benefits...
949 // Until such a way is found, don't insist on promoting i1 here.
951 TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
952 TargetLowering::Promote)) {
953 // Promote to a byte-sized load if not loading an integral number of
954 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
955 unsigned NewWidth = SrcVT.getStoreSizeInBits();
956 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
959 // The extra bits are guaranteed to be zero, since we stored them that
960 // way. A zext load from NVT thus automatically gives zext from SrcVT.
962 ISD::LoadExtType NewExtType =
963 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
966 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
967 Chain, Ptr, LD->getPointerInfo(),
968 NVT, isVolatile, isNonTemporal, isInvariant, Alignment,
971 Ch = Result.getValue(1); // The chain.
973 if (ExtType == ISD::SEXTLOAD)
974 // Having the top bits zero doesn't help when sign extending.
975 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
976 Result.getValueType(),
977 Result, DAG.getValueType(SrcVT));
978 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
979 // All the top bits are guaranteed to be zero - inform the optimizers.
980 Result = DAG.getNode(ISD::AssertZext, dl,
981 Result.getValueType(), Result,
982 DAG.getValueType(SrcVT));
986 } else if (SrcWidth & (SrcWidth - 1)) {
987 // If not loading a power-of-2 number of bits, expand as two loads.
988 assert(!SrcVT.isVector() && "Unsupported extload!");
989 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
990 assert(RoundWidth < SrcWidth);
991 unsigned ExtraWidth = SrcWidth - RoundWidth;
992 assert(ExtraWidth < RoundWidth);
993 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
994 "Load size not an integral number of bytes!");
995 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
996 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
998 unsigned IncrementSize;
999 auto &DL = DAG.getDataLayout();
1001 if (DL.isLittleEndian()) {
1002 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1003 // Load the bottom RoundWidth bits.
1004 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1006 LD->getPointerInfo(), RoundVT, isVolatile,
1007 isNonTemporal, isInvariant, Alignment, AAInfo);
1009 // Load the remaining ExtraWidth bits.
1010 IncrementSize = RoundWidth / 8;
1011 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1012 DAG.getConstant(IncrementSize, dl,
1013 Ptr.getValueType()));
1014 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1015 LD->getPointerInfo().getWithOffset(IncrementSize),
1016 ExtraVT, isVolatile, isNonTemporal, isInvariant,
1017 MinAlign(Alignment, IncrementSize), AAInfo);
1019 // Build a factor node to remember that this load is independent of
1021 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1024 // Move the top bits to the right place.
1026 ISD::SHL, dl, Hi.getValueType(), Hi,
1027 DAG.getConstant(RoundWidth, dl,
1028 TLI.getShiftAmountTy(Hi.getValueType(), DL)));
1030 // Join the hi and lo parts.
1031 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1033 // Big endian - avoid unaligned loads.
1034 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1035 // Load the top RoundWidth bits.
1036 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1037 LD->getPointerInfo(), RoundVT, isVolatile,
1038 isNonTemporal, isInvariant, Alignment, AAInfo);
1040 // Load the remaining ExtraWidth bits.
1041 IncrementSize = RoundWidth / 8;
1042 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1043 DAG.getConstant(IncrementSize, dl,
1044 Ptr.getValueType()));
1045 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1046 dl, Node->getValueType(0), Chain, Ptr,
1047 LD->getPointerInfo().getWithOffset(IncrementSize),
1048 ExtraVT, isVolatile, isNonTemporal, isInvariant,
1049 MinAlign(Alignment, IncrementSize), AAInfo);
1051 // Build a factor node to remember that this load is independent of
1053 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1056 // Move the top bits to the right place.
1058 ISD::SHL, dl, Hi.getValueType(), Hi,
1059 DAG.getConstant(ExtraWidth, dl,
1060 TLI.getShiftAmountTy(Hi.getValueType(), DL)));
1062 // Join the hi and lo parts.
1063 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1068 bool isCustom = false;
1069 switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0),
1070 SrcVT.getSimpleVT())) {
1071 default: llvm_unreachable("This action is not supported yet!");
1072 case TargetLowering::Custom:
1075 case TargetLowering::Legal: {
1076 Value = SDValue(Node, 0);
1077 Chain = SDValue(Node, 1);
1080 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1081 if (Res.getNode()) {
1083 Chain = Res.getValue(1);
1086 // If this is an unaligned load and the target doesn't support it,
1088 EVT MemVT = LD->getMemoryVT();
1089 unsigned AS = LD->getAddressSpace();
1090 unsigned Align = LD->getAlignment();
1091 const DataLayout &DL = DAG.getDataLayout();
1092 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
1093 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, Value, Chain);
1097 case TargetLowering::Expand:
1098 EVT DestVT = Node->getValueType(0);
1099 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
1100 // If the source type is not legal, see if there is a legal extload to
1101 // an intermediate type that we can then extend further.
1102 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
1103 if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
1104 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) {
1105 // If we are loading a legal type, this is a non-extload followed by a
1107 ISD::LoadExtType MidExtType =
1108 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
1110 SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr,
1111 SrcVT, LD->getMemOperand());
1113 ISD::getExtForLoadExtType(SrcVT.isFloatingPoint(), ExtType);
1114 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1115 Chain = Load.getValue(1);
1119 // Handle the special case of fp16 extloads. EXTLOAD doesn't have the
1120 // normal undefined upper bits behavior to allow using an in-reg extend
1121 // with the illegal FP type, so load as an integer and do the
1122 // from-integer conversion.
1123 if (SrcVT.getScalarType() == MVT::f16) {
1124 EVT ISrcVT = SrcVT.changeTypeToInteger();
1125 EVT IDestVT = DestVT.changeTypeToInteger();
1126 EVT LoadVT = TLI.getRegisterType(IDestVT.getSimpleVT());
1128 SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, LoadVT,
1130 LD->getMemOperand());
1131 Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result);
1132 Chain = Result.getValue(1);
1137 assert(!SrcVT.isVector() &&
1138 "Vector Loads are handled in LegalizeVectorOps");
1140 // FIXME: This does not work for vectors on most targets. Sign-
1141 // and zero-extend operations are currently folded into extending
1142 // loads, whether they are legal or not, and then we end up here
1143 // without any support for legalizing them.
1144 assert(ExtType != ISD::EXTLOAD &&
1145 "EXTLOAD should always be supported!");
1146 // Turn the unsupported load into an EXTLOAD followed by an
1147 // explicit zero/sign extend inreg.
1148 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1149 Node->getValueType(0),
1151 LD->getMemOperand());
1153 if (ExtType == ISD::SEXTLOAD)
1154 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1155 Result.getValueType(),
1156 Result, DAG.getValueType(SrcVT));
1158 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1160 Chain = Result.getValue(1);
1165 // Since loads produce two values, make sure to remember that we legalized
1167 if (Chain.getNode() != Node) {
1168 assert(Value.getNode() != Node && "Load must be completely replaced");
1169 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1170 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1172 UpdatedNodes->insert(Value.getNode());
1173 UpdatedNodes->insert(Chain.getNode());
1179 /// Return a legal replacement for the given operation, with all legal operands.
1180 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1181 DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
1183 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1187 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1188 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1189 TargetLowering::TypeLegal &&
1190 "Unexpected illegal type!");
1192 for (const SDValue &Op : Node->op_values())
1193 assert((TLI.getTypeAction(*DAG.getContext(),
1194 Op.getValueType()) == TargetLowering::TypeLegal ||
1195 Op.getOpcode() == ISD::TargetConstant) &&
1196 "Unexpected illegal type!");
1199 // Figure out the correct action; the way to query this varies by opcode
1200 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1201 bool SimpleFinishLegalizing = true;
1202 switch (Node->getOpcode()) {
1203 case ISD::INTRINSIC_W_CHAIN:
1204 case ISD::INTRINSIC_WO_CHAIN:
1205 case ISD::INTRINSIC_VOID:
1206 case ISD::STACKSAVE:
1207 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1210 Action = TLI.getOperationAction(Node->getOpcode(),
1211 Node->getValueType(0));
1212 if (Action != TargetLowering::Promote)
1213 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1215 case ISD::FP_TO_FP16:
1216 case ISD::SINT_TO_FP:
1217 case ISD::UINT_TO_FP:
1218 case ISD::EXTRACT_VECTOR_ELT:
1219 Action = TLI.getOperationAction(Node->getOpcode(),
1220 Node->getOperand(0).getValueType());
1222 case ISD::FP_ROUND_INREG:
1223 case ISD::SIGN_EXTEND_INREG: {
1224 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1225 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1228 case ISD::ATOMIC_STORE: {
1229 Action = TLI.getOperationAction(Node->getOpcode(),
1230 Node->getOperand(2).getValueType());
1233 case ISD::SELECT_CC:
1236 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1237 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1238 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1239 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1240 ISD::CondCode CCCode =
1241 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1242 Action = TLI.getCondCodeAction(CCCode, OpVT);
1243 if (Action == TargetLowering::Legal) {
1244 if (Node->getOpcode() == ISD::SELECT_CC)
1245 Action = TLI.getOperationAction(Node->getOpcode(),
1246 Node->getValueType(0));
1248 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1254 // FIXME: Model these properly. LOAD and STORE are complicated, and
1255 // STORE expects the unlegalized operand in some cases.
1256 SimpleFinishLegalizing = false;
1258 case ISD::CALLSEQ_START:
1259 case ISD::CALLSEQ_END:
1260 // FIXME: This shouldn't be necessary. These nodes have special properties
1261 // dealing with the recursive nature of legalization. Removing this
1262 // special case should be done as part of making LegalizeDAG non-recursive.
1263 SimpleFinishLegalizing = false;
1265 case ISD::EXTRACT_ELEMENT:
1266 case ISD::FLT_ROUNDS_:
1268 case ISD::MERGE_VALUES:
1269 case ISD::EH_RETURN:
1270 case ISD::FRAME_TO_ARGS_OFFSET:
1271 case ISD::EH_SJLJ_SETJMP:
1272 case ISD::EH_SJLJ_LONGJMP:
1273 case ISD::EH_SJLJ_SETUP_DISPATCH:
1274 // These operations lie about being legal: when they claim to be legal,
1275 // they should actually be expanded.
1276 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1277 if (Action == TargetLowering::Legal)
1278 Action = TargetLowering::Expand;
1280 case ISD::INIT_TRAMPOLINE:
1281 case ISD::ADJUST_TRAMPOLINE:
1282 case ISD::FRAMEADDR:
1283 case ISD::RETURNADDR:
1284 // These operations lie about being legal: when they claim to be legal,
1285 // they should actually be custom-lowered.
1286 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1287 if (Action == TargetLowering::Legal)
1288 Action = TargetLowering::Custom;
1290 case ISD::READCYCLECOUNTER:
1291 // READCYCLECOUNTER returns an i64, even if type legalization might have
1292 // expanded that to several smaller types.
1293 Action = TLI.getOperationAction(Node->getOpcode(), MVT::i64);
1295 case ISD::READ_REGISTER:
1296 case ISD::WRITE_REGISTER:
1297 // Named register is legal in the DAG, but blocked by register name
1298 // selection if not implemented by target (to chose the correct register)
1299 // They'll be converted to Copy(To/From)Reg.
1300 Action = TargetLowering::Legal;
1302 case ISD::DEBUGTRAP:
1303 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1304 if (Action == TargetLowering::Expand) {
1305 // replace ISD::DEBUGTRAP with ISD::TRAP
1307 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1308 Node->getOperand(0));
1309 ReplaceNode(Node, NewVal.getNode());
1310 LegalizeOp(NewVal.getNode());
1316 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1317 Action = TargetLowering::Legal;
1319 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1324 if (SimpleFinishLegalizing) {
1325 SDNode *NewNode = Node;
1326 switch (Node->getOpcode()) {
1333 // Legalizing shifts/rotates requires adjusting the shift amount
1334 // to the appropriate width.
1335 if (!Node->getOperand(1).getValueType().isVector()) {
1337 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1338 Node->getOperand(1));
1339 HandleSDNode Handle(SAO);
1340 LegalizeOp(SAO.getNode());
1341 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1345 case ISD::SRL_PARTS:
1346 case ISD::SRA_PARTS:
1347 case ISD::SHL_PARTS:
1348 // Legalizing shifts/rotates requires adjusting the shift amount
1349 // to the appropriate width.
1350 if (!Node->getOperand(2).getValueType().isVector()) {
1352 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1353 Node->getOperand(2));
1354 HandleSDNode Handle(SAO);
1355 LegalizeOp(SAO.getNode());
1356 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1357 Node->getOperand(1),
1363 if (NewNode != Node) {
1364 ReplaceNode(Node, NewNode);
1368 case TargetLowering::Legal:
1370 case TargetLowering::Custom: {
1371 // FIXME: The handling for custom lowering with multiple results is
1373 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1374 if (Res.getNode()) {
1375 if (!(Res.getNode() != Node || Res.getResNo() != 0))
1378 if (Node->getNumValues() == 1) {
1379 // We can just directly replace this node with the lowered value.
1380 ReplaceNode(SDValue(Node, 0), Res);
1384 SmallVector<SDValue, 8> ResultVals;
1385 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1386 ResultVals.push_back(Res.getValue(i));
1387 ReplaceNode(Node, ResultVals.data());
1392 case TargetLowering::Expand:
1395 case TargetLowering::Promote:
1401 switch (Node->getOpcode()) {
1408 llvm_unreachable("Do not know how to legalize this operator!");
1410 case ISD::CALLSEQ_START:
1411 case ISD::CALLSEQ_END:
1414 return LegalizeLoadOps(Node);
1417 return LegalizeStoreOps(Node);
1422 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1423 SDValue Vec = Op.getOperand(0);
1424 SDValue Idx = Op.getOperand(1);
1427 // Before we generate a new store to a temporary stack slot, see if there is
1428 // already one that we can use. There often is because when we scalarize
1429 // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1430 // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1431 // the vector. If all are expanded here, we don't want one store per vector
1433 SDValue StackPtr, Ch;
1434 for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1435 UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1437 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1438 if (ST->isIndexed() || ST->isTruncatingStore() ||
1439 ST->getValue() != Vec)
1442 // Make sure that nothing else could have stored into the destination of
1444 if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1447 StackPtr = ST->getBasePtr();
1448 Ch = SDValue(ST, 0);
1453 if (!Ch.getNode()) {
1454 // Store the value to a temporary stack slot, then LOAD the returned part.
1455 StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1456 Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1457 MachinePointerInfo(), false, false, 0);
1460 // Add the offset to the index.
1462 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1463 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1464 DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
1466 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy(DAG.getDataLayout()));
1467 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1471 if (Op.getValueType().isVector())
1472 NewLoad = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,
1473 MachinePointerInfo(), false, false, false, 0);
1475 NewLoad = DAG.getExtLoad(
1476 ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, MachinePointerInfo(),
1477 Vec.getValueType().getVectorElementType(), false, false, false, 0);
1479 // Replace the chain going out of the store, by the one out of the load.
1480 DAG.ReplaceAllUsesOfValueWith(Ch, SDValue(NewLoad.getNode(), 1));
1482 // We introduced a cycle though, so update the loads operands, making sure
1483 // to use the original store's chain as an incoming chain.
1484 SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1486 NewLoadOperands[0] = Ch;
1488 SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0);
1492 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1493 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1495 SDValue Vec = Op.getOperand(0);
1496 SDValue Part = Op.getOperand(1);
1497 SDValue Idx = Op.getOperand(2);
1500 // Store the value to a temporary stack slot, then LOAD the returned part.
1502 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1503 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1504 MachinePointerInfo PtrInfo =
1505 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1507 // First store the whole vector.
1508 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1511 // Then store the inserted part.
1513 // Add the offset to the index.
1515 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1517 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1518 DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
1519 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy(DAG.getDataLayout()));
1521 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1524 // Store the subvector.
1525 Ch = DAG.getStore(Ch, dl, Part, SubStackPtr,
1526 MachinePointerInfo(), false, false, 0);
1528 // Finally, load the updated vector.
1529 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1530 false, false, false, 0);
1533 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1534 // We can't handle this case efficiently. Allocate a sufficiently
1535 // aligned object on the stack, store each element into it, then load
1536 // the result as a vector.
1537 // Create the stack frame object.
1538 EVT VT = Node->getValueType(0);
1539 EVT EltVT = VT.getVectorElementType();
1541 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1542 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1543 MachinePointerInfo PtrInfo =
1544 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1546 // Emit a store of each element to the stack slot.
1547 SmallVector<SDValue, 8> Stores;
1548 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1549 // Store (in the right endianness) the elements to memory.
1550 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1551 // Ignore undef elements.
1552 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1554 unsigned Offset = TypeByteSize*i;
1556 SDValue Idx = DAG.getConstant(Offset, dl, FIPtr.getValueType());
1557 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1559 // If the destination vector element type is narrower than the source
1560 // element type, only store the bits necessary.
1561 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1562 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1563 Node->getOperand(i), Idx,
1564 PtrInfo.getWithOffset(Offset),
1565 EltVT, false, false, 0));
1567 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1568 Node->getOperand(i), Idx,
1569 PtrInfo.getWithOffset(Offset),
1574 if (!Stores.empty()) // Not all undef elements?
1575 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1577 StoreChain = DAG.getEntryNode();
1579 // Result is a load from the stack slot.
1580 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1581 false, false, false, 0);
1584 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1586 SDValue Tmp1 = Node->getOperand(0);
1587 SDValue Tmp2 = Node->getOperand(1);
1589 // Get the sign bit of the RHS. First obtain a value that has the same
1590 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1592 EVT FloatVT = Tmp2.getValueType();
1593 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1594 if (TLI.isTypeLegal(IVT)) {
1595 // Convert to an integer with the same sign bit.
1596 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1598 auto &DL = DAG.getDataLayout();
1599 // Store the float to memory, then load the sign part out as an integer.
1600 MVT LoadTy = TLI.getPointerTy(DL);
1601 // First create a temporary that is aligned for both the load and store.
1602 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1603 // Then store the float to it.
1605 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1607 if (DL.isBigEndian()) {
1608 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1609 // Load out a legal integer with the same sign bit as the float.
1610 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1611 false, false, false, 0);
1612 } else { // Little endian
1613 SDValue LoadPtr = StackPtr;
1614 // The float may be wider than the integer we are going to load. Advance
1615 // the pointer so that the loaded integer will contain the sign bit.
1616 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1617 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1618 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), LoadPtr,
1619 DAG.getConstant(ByteOffset, dl,
1620 LoadPtr.getValueType()));
1621 // Load a legal integer containing the sign bit.
1622 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1623 false, false, false, 0);
1624 // Move the sign bit to the top bit of the loaded integer.
1625 unsigned BitShift = LoadTy.getSizeInBits() -
1626 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1627 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1629 SignBit = DAG.getNode(
1630 ISD::SHL, dl, LoadTy, SignBit,
1631 DAG.getConstant(BitShift, dl,
1632 TLI.getShiftAmountTy(SignBit.getValueType(), DL)));
1635 // Now get the sign bit proper, by seeing whether the value is negative.
1636 SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
1638 DAG.getConstant(0, dl, SignBit.getValueType()),
1640 // Get the absolute value of the result.
1641 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1642 // Select between the nabs and abs value based on the sign bit of
1644 return DAG.getSelect(dl, AbsVal.getValueType(), SignBit,
1645 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1649 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1650 SmallVectorImpl<SDValue> &Results) {
1651 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1652 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1653 " not tell us which reg is the stack pointer!");
1655 EVT VT = Node->getValueType(0);
1656 SDValue Tmp1 = SDValue(Node, 0);
1657 SDValue Tmp2 = SDValue(Node, 1);
1658 SDValue Tmp3 = Node->getOperand(2);
1659 SDValue Chain = Tmp1.getOperand(0);
1661 // Chain the dynamic stack allocation so that it doesn't modify the stack
1662 // pointer when other instructions are using the stack.
1663 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
1665 SDValue Size = Tmp2.getOperand(1);
1666 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1667 Chain = SP.getValue(1);
1668 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1669 unsigned StackAlign =
1670 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
1671 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1672 if (Align > StackAlign)
1673 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1674 DAG.getConstant(-(uint64_t)Align, dl, VT));
1675 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1677 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
1678 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
1680 Results.push_back(Tmp1);
1681 Results.push_back(Tmp2);
1684 /// Legalize a SETCC with given LHS and RHS and condition code CC on the current
1687 /// If the SETCC has been legalized using AND / OR, then the legalized node
1688 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1689 /// will be set to false.
1691 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1692 /// then the values of LHS and RHS will be swapped, CC will be set to the
1693 /// new condition, and NeedInvert will be set to false.
1695 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1696 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1697 /// will be set to true. The caller must invert the result of the SETCC with
1698 /// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1699 /// of a true/false result.
1701 /// \returns true if the SetCC has been legalized, false if it hasn't.
1702 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1703 SDValue &LHS, SDValue &RHS,
1707 MVT OpVT = LHS.getSimpleValueType();
1708 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1710 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1711 default: llvm_unreachable("Unknown condition code action!");
1712 case TargetLowering::Legal:
1715 case TargetLowering::Expand: {
1716 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1717 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1718 std::swap(LHS, RHS);
1719 CC = DAG.getCondCode(InvCC);
1722 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1725 default: llvm_unreachable("Don't know how to expand this condition!");
1727 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1728 == TargetLowering::Legal
1729 && "If SETO is expanded, SETOEQ must be legal!");
1730 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1732 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1733 == TargetLowering::Legal
1734 && "If SETUO is expanded, SETUNE must be legal!");
1735 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1748 // If we are floating point, assign and break, otherwise fall through.
1749 if (!OpVT.isInteger()) {
1750 // We can use the 4th bit to tell if we are the unordered
1751 // or ordered version of the opcode.
1752 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1753 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1754 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1757 // Fallthrough if we are unsigned integer.
1762 // We only support using the inverted operation, which is computed above
1763 // and not a different manner of supporting expanding these cases.
1764 llvm_unreachable("Don't know how to expand this condition!");
1767 // Try inverting the result of the inverse condition.
1768 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1769 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1770 CC = DAG.getCondCode(InvCC);
1774 // If inverting the condition didn't work then we have no means to expand
1776 llvm_unreachable("Don't know how to expand this condition!");
1779 SDValue SetCC1, SetCC2;
1780 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1781 // If we aren't the ordered or unorder operation,
1782 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1783 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1784 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1786 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1787 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1788 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1790 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1799 /// Emit a store/load combination to the stack. This stores
1800 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1801 /// a load from the stack slot to DestVT, extending it if needed.
1802 /// The resultant code need not be legal.
1803 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1807 // Create the stack frame object.
1808 unsigned SrcAlign = DAG.getDataLayout().getPrefTypeAlignment(
1809 SrcOp.getValueType().getTypeForEVT(*DAG.getContext()));
1810 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1812 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1813 int SPFI = StackPtrFI->getIndex();
1814 MachinePointerInfo PtrInfo =
1815 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
1817 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1818 unsigned SlotSize = SlotVT.getSizeInBits();
1819 unsigned DestSize = DestVT.getSizeInBits();
1820 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1821 unsigned DestAlign = DAG.getDataLayout().getPrefTypeAlignment(DestType);
1823 // Emit a store to the stack slot. Use a truncstore if the input value is
1824 // later than DestVT.
1827 if (SrcSize > SlotSize)
1828 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1829 PtrInfo, SlotVT, false, false, SrcAlign);
1831 assert(SrcSize == SlotSize && "Invalid store");
1832 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1833 PtrInfo, false, false, SrcAlign);
1836 // Result is a load from the stack slot.
1837 if (SlotSize == DestSize)
1838 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1839 false, false, false, DestAlign);
1841 assert(SlotSize < DestSize && "Unknown extension!");
1842 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1843 PtrInfo, SlotVT, false, false, false, DestAlign);
1846 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1848 // Create a vector sized/aligned stack slot, store the value to element #0,
1849 // then load the whole vector back out.
1850 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1852 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1853 int SPFI = StackPtrFI->getIndex();
1855 SDValue Ch = DAG.getTruncStore(
1856 DAG.getEntryNode(), dl, Node->getOperand(0), StackPtr,
1857 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI),
1858 Node->getValueType(0).getVectorElementType(), false, false, 0);
1860 Node->getValueType(0), dl, Ch, StackPtr,
1861 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI), false,
1866 ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
1867 const TargetLowering &TLI, SDValue &Res) {
1868 unsigned NumElems = Node->getNumOperands();
1870 EVT VT = Node->getValueType(0);
1872 // Try to group the scalars into pairs, shuffle the pairs together, then
1873 // shuffle the pairs of pairs together, etc. until the vector has
1874 // been built. This will work only if all of the necessary shuffle masks
1877 // We do this in two phases; first to check the legality of the shuffles,
1878 // and next, assuming that all shuffles are legal, to create the new nodes.
1879 for (int Phase = 0; Phase < 2; ++Phase) {
1880 SmallVector<std::pair<SDValue, SmallVector<int, 16> >, 16> IntermedVals,
1882 for (unsigned i = 0; i < NumElems; ++i) {
1883 SDValue V = Node->getOperand(i);
1884 if (V.getOpcode() == ISD::UNDEF)
1889 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1890 IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
1893 while (IntermedVals.size() > 2) {
1894 NewIntermedVals.clear();
1895 for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1896 // This vector and the next vector are shuffled together (simply to
1897 // append the one to the other).
1898 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1900 SmallVector<int, 16> FinalIndices;
1901 FinalIndices.reserve(IntermedVals[i].second.size() +
1902 IntermedVals[i+1].second.size());
1905 for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1908 FinalIndices.push_back(IntermedVals[i].second[j]);
1910 for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1912 ShuffleVec[k] = NumElems + j;
1913 FinalIndices.push_back(IntermedVals[i+1].second[j]);
1918 Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
1919 IntermedVals[i+1].first,
1921 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1923 NewIntermedVals.push_back(
1924 std::make_pair(Shuffle, std::move(FinalIndices)));
1927 // If we had an odd number of defined values, then append the last
1928 // element to the array of new vectors.
1929 if ((IntermedVals.size() & 1) != 0)
1930 NewIntermedVals.push_back(IntermedVals.back());
1932 IntermedVals.swap(NewIntermedVals);
1935 assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1936 "Invalid number of intermediate vectors");
1937 SDValue Vec1 = IntermedVals[0].first;
1939 if (IntermedVals.size() > 1)
1940 Vec2 = IntermedVals[1].first;
1942 Vec2 = DAG.getUNDEF(VT);
1944 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1945 for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1946 ShuffleVec[IntermedVals[0].second[i]] = i;
1947 for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1948 ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1951 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1952 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1959 /// Expand a BUILD_VECTOR node on targets that don't
1960 /// support the operation, but do support the resultant vector type.
1961 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1962 unsigned NumElems = Node->getNumOperands();
1963 SDValue Value1, Value2;
1965 EVT VT = Node->getValueType(0);
1966 EVT OpVT = Node->getOperand(0).getValueType();
1967 EVT EltVT = VT.getVectorElementType();
1969 // If the only non-undef value is the low element, turn this into a
1970 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1971 bool isOnlyLowElement = true;
1972 bool MoreThanTwoValues = false;
1973 bool isConstant = true;
1974 for (unsigned i = 0; i < NumElems; ++i) {
1975 SDValue V = Node->getOperand(i);
1976 if (V.getOpcode() == ISD::UNDEF)
1979 isOnlyLowElement = false;
1980 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1983 if (!Value1.getNode()) {
1985 } else if (!Value2.getNode()) {
1988 } else if (V != Value1 && V != Value2) {
1989 MoreThanTwoValues = true;
1993 if (!Value1.getNode())
1994 return DAG.getUNDEF(VT);
1996 if (isOnlyLowElement)
1997 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1999 // If all elements are constants, create a load from the constant pool.
2001 SmallVector<Constant*, 16> CV;
2002 for (unsigned i = 0, e = NumElems; i != e; ++i) {
2003 if (ConstantFPSDNode *V =
2004 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
2005 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
2006 } else if (ConstantSDNode *V =
2007 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
2009 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
2011 // If OpVT and EltVT don't match, EltVT is not legal and the
2012 // element values have been promoted/truncated earlier. Undo this;
2013 // we don't want a v16i8 to become a v16i32 for example.
2014 const ConstantInt *CI = V->getConstantIntValue();
2015 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
2016 CI->getZExtValue()));
2019 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
2020 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
2021 CV.push_back(UndefValue::get(OpNTy));
2024 Constant *CP = ConstantVector::get(CV);
2026 DAG.getConstantPool(CP, TLI.getPointerTy(DAG.getDataLayout()));
2027 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2029 VT, dl, DAG.getEntryNode(), CPIdx,
2030 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2031 false, false, Alignment);
2034 SmallSet<SDValue, 16> DefinedValues;
2035 for (unsigned i = 0; i < NumElems; ++i) {
2036 if (Node->getOperand(i).getOpcode() == ISD::UNDEF)
2038 DefinedValues.insert(Node->getOperand(i));
2041 if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
2042 if (!MoreThanTwoValues) {
2043 SmallVector<int, 8> ShuffleVec(NumElems, -1);
2044 for (unsigned i = 0; i < NumElems; ++i) {
2045 SDValue V = Node->getOperand(i);
2046 if (V.getOpcode() == ISD::UNDEF)
2048 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2050 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
2051 // Get the splatted value into the low element of a vector register.
2052 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2054 if (Value2.getNode())
2055 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2057 Vec2 = DAG.getUNDEF(VT);
2059 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2060 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2064 if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
2069 // Otherwise, we can't handle this case efficiently.
2070 return ExpandVectorBuildThroughStack(Node);
2073 // Expand a node into a call to a libcall. If the result value
2074 // does not fit into a register, return the lo part and set the hi part to the
2075 // by-reg argument. If it does fit into a single register, return the result
2076 // and leave the Hi part unset.
2077 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2079 TargetLowering::ArgListTy Args;
2080 TargetLowering::ArgListEntry Entry;
2081 for (const SDValue &Op : Node->op_values()) {
2082 EVT ArgVT = Op.getValueType();
2083 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2086 Entry.isSExt = isSigned;
2087 Entry.isZExt = !isSigned;
2088 Args.push_back(Entry);
2090 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2091 TLI.getPointerTy(DAG.getDataLayout()));
2093 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2095 // By default, the input chain to this libcall is the entry node of the
2096 // function. If the libcall is going to be emitted as a tail call then
2097 // TLI.isUsedByReturnOnly will change it to the right chain if the return
2098 // node which is being folded has a non-entry input chain.
2099 SDValue InChain = DAG.getEntryNode();
2101 // isTailCall may be true since the callee does not reference caller stack
2102 // frame. Check if it's in the right position.
2103 SDValue TCChain = InChain;
2104 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
2108 TargetLowering::CallLoweringInfo CLI(DAG);
2109 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2110 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2111 .setTailCall(isTailCall).setSExtResult(isSigned).setZExtResult(!isSigned);
2113 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2115 if (!CallInfo.second.getNode())
2116 // It's a tailcall, return the chain (which is the DAG root).
2117 return DAG.getRoot();
2119 return CallInfo.first;
2122 /// Generate a libcall taking the given operands as arguments
2123 /// and returning a result of type RetVT.
2124 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2125 const SDValue *Ops, unsigned NumOps,
2126 bool isSigned, SDLoc dl) {
2127 TargetLowering::ArgListTy Args;
2128 Args.reserve(NumOps);
2130 TargetLowering::ArgListEntry Entry;
2131 for (unsigned i = 0; i != NumOps; ++i) {
2132 Entry.Node = Ops[i];
2133 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2134 Entry.isSExt = isSigned;
2135 Entry.isZExt = !isSigned;
2136 Args.push_back(Entry);
2138 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2139 TLI.getPointerTy(DAG.getDataLayout()));
2141 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2143 TargetLowering::CallLoweringInfo CLI(DAG);
2144 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
2145 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2146 .setSExtResult(isSigned).setZExtResult(!isSigned);
2148 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
2150 return CallInfo.first;
2153 // Expand a node into a call to a libcall. Similar to
2154 // ExpandLibCall except that the first operand is the in-chain.
2155 std::pair<SDValue, SDValue>
2156 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2159 SDValue InChain = Node->getOperand(0);
2161 TargetLowering::ArgListTy Args;
2162 TargetLowering::ArgListEntry Entry;
2163 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2164 EVT ArgVT = Node->getOperand(i).getValueType();
2165 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2166 Entry.Node = Node->getOperand(i);
2168 Entry.isSExt = isSigned;
2169 Entry.isZExt = !isSigned;
2170 Args.push_back(Entry);
2172 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2173 TLI.getPointerTy(DAG.getDataLayout()));
2175 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2177 TargetLowering::CallLoweringInfo CLI(DAG);
2178 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2179 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2180 .setSExtResult(isSigned).setZExtResult(!isSigned);
2182 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2187 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2188 RTLIB::Libcall Call_F32,
2189 RTLIB::Libcall Call_F64,
2190 RTLIB::Libcall Call_F80,
2191 RTLIB::Libcall Call_F128,
2192 RTLIB::Libcall Call_PPCF128) {
2194 switch (Node->getSimpleValueType(0).SimpleTy) {
2195 default: llvm_unreachable("Unexpected request for libcall!");
2196 case MVT::f32: LC = Call_F32; break;
2197 case MVT::f64: LC = Call_F64; break;
2198 case MVT::f80: LC = Call_F80; break;
2199 case MVT::f128: LC = Call_F128; break;
2200 case MVT::ppcf128: LC = Call_PPCF128; break;
2202 return ExpandLibCall(LC, Node, false);
2205 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2206 RTLIB::Libcall Call_I8,
2207 RTLIB::Libcall Call_I16,
2208 RTLIB::Libcall Call_I32,
2209 RTLIB::Libcall Call_I64,
2210 RTLIB::Libcall Call_I128) {
2212 switch (Node->getSimpleValueType(0).SimpleTy) {
2213 default: llvm_unreachable("Unexpected request for libcall!");
2214 case MVT::i8: LC = Call_I8; break;
2215 case MVT::i16: LC = Call_I16; break;
2216 case MVT::i32: LC = Call_I32; break;
2217 case MVT::i64: LC = Call_I64; break;
2218 case MVT::i128: LC = Call_I128; break;
2220 return ExpandLibCall(LC, Node, isSigned);
2223 /// Return true if divmod libcall is available.
2224 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2225 const TargetLowering &TLI) {
2227 switch (Node->getSimpleValueType(0).SimpleTy) {
2228 default: llvm_unreachable("Unexpected request for libcall!");
2229 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2230 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2231 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2232 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2233 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2236 return TLI.getLibcallName(LC) != nullptr;
2239 /// Only issue divrem libcall if both quotient and remainder are needed.
2240 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2241 // The other use might have been replaced with a divrem already.
2242 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2243 unsigned OtherOpcode = 0;
2245 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2247 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2249 SDValue Op0 = Node->getOperand(0);
2250 SDValue Op1 = Node->getOperand(1);
2251 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2252 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2256 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2257 User->getOperand(0) == Op0 &&
2258 User->getOperand(1) == Op1)
2264 /// Issue libcalls to __{u}divmod to compute div / rem pairs.
2266 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2267 SmallVectorImpl<SDValue> &Results) {
2268 unsigned Opcode = Node->getOpcode();
2269 bool isSigned = Opcode == ISD::SDIVREM;
2272 switch (Node->getSimpleValueType(0).SimpleTy) {
2273 default: llvm_unreachable("Unexpected request for libcall!");
2274 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2275 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2276 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2277 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2278 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2281 // The input chain to this libcall is the entry node of the function.
2282 // Legalizing the call will automatically add the previous call to the
2284 SDValue InChain = DAG.getEntryNode();
2286 EVT RetVT = Node->getValueType(0);
2287 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2289 TargetLowering::ArgListTy Args;
2290 TargetLowering::ArgListEntry Entry;
2291 for (const SDValue &Op : Node->op_values()) {
2292 EVT ArgVT = Op.getValueType();
2293 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2296 Entry.isSExt = isSigned;
2297 Entry.isZExt = !isSigned;
2298 Args.push_back(Entry);
2301 // Also pass the return address of the remainder.
2302 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2304 Entry.Ty = RetTy->getPointerTo();
2305 Entry.isSExt = isSigned;
2306 Entry.isZExt = !isSigned;
2307 Args.push_back(Entry);
2309 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2310 TLI.getPointerTy(DAG.getDataLayout()));
2313 TargetLowering::CallLoweringInfo CLI(DAG);
2314 CLI.setDebugLoc(dl).setChain(InChain)
2315 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2316 .setSExtResult(isSigned).setZExtResult(!isSigned);
2318 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2320 // Remainder is loaded back from the stack frame.
2321 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2322 MachinePointerInfo(), false, false, false, 0);
2323 Results.push_back(CallInfo.first);
2324 Results.push_back(Rem);
2327 /// Return true if sincos libcall is available.
2328 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2330 switch (Node->getSimpleValueType(0).SimpleTy) {
2331 default: llvm_unreachable("Unexpected request for libcall!");
2332 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2333 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2334 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2335 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2336 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2338 return TLI.getLibcallName(LC) != nullptr;
2341 /// Return true if sincos libcall is available and can be used to combine sin
2343 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2344 const TargetMachine &TM) {
2345 if (!isSinCosLibcallAvailable(Node, TLI))
2347 // GNU sin/cos functions set errno while sincos does not. Therefore
2348 // combining sin and cos is only safe if unsafe-fpmath is enabled.
2349 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2350 if (isGNU && !TM.Options.UnsafeFPMath)
2355 /// Only issue sincos libcall if both sin and cos are needed.
2356 static bool useSinCos(SDNode *Node) {
2357 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2358 ? ISD::FCOS : ISD::FSIN;
2360 SDValue Op0 = Node->getOperand(0);
2361 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2362 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2366 // The other user might have been turned into sincos already.
2367 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2373 /// Issue libcalls to sincos to compute sin / cos pairs.
2375 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2376 SmallVectorImpl<SDValue> &Results) {
2378 switch (Node->getSimpleValueType(0).SimpleTy) {
2379 default: llvm_unreachable("Unexpected request for libcall!");
2380 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2381 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2382 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2383 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2384 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2387 // The input chain to this libcall is the entry node of the function.
2388 // Legalizing the call will automatically add the previous call to the
2390 SDValue InChain = DAG.getEntryNode();
2392 EVT RetVT = Node->getValueType(0);
2393 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2395 TargetLowering::ArgListTy Args;
2396 TargetLowering::ArgListEntry Entry;
2398 // Pass the argument.
2399 Entry.Node = Node->getOperand(0);
2401 Entry.isSExt = false;
2402 Entry.isZExt = false;
2403 Args.push_back(Entry);
2405 // Pass the return address of sin.
2406 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2407 Entry.Node = SinPtr;
2408 Entry.Ty = RetTy->getPointerTo();
2409 Entry.isSExt = false;
2410 Entry.isZExt = false;
2411 Args.push_back(Entry);
2413 // Also pass the return address of the cos.
2414 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2415 Entry.Node = CosPtr;
2416 Entry.Ty = RetTy->getPointerTo();
2417 Entry.isSExt = false;
2418 Entry.isZExt = false;
2419 Args.push_back(Entry);
2421 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2422 TLI.getPointerTy(DAG.getDataLayout()));
2425 TargetLowering::CallLoweringInfo CLI(DAG);
2426 CLI.setDebugLoc(dl).setChain(InChain)
2427 .setCallee(TLI.getLibcallCallingConv(LC),
2428 Type::getVoidTy(*DAG.getContext()), Callee, std::move(Args), 0);
2430 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2432 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2433 MachinePointerInfo(), false, false, false, 0));
2434 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2435 MachinePointerInfo(), false, false, false, 0));
2438 /// This function is responsible for legalizing a
2439 /// INT_TO_FP operation of the specified operand when the target requests that
2440 /// we expand it. At this point, we know that the result and operand types are
2441 /// legal for the target.
2442 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2446 // TODO: Should any fast-math-flags be set for the created nodes?
2448 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2449 // simple 32-bit [signed|unsigned] integer to float/double expansion
2451 // Get the stack frame index of a 8 byte buffer.
2452 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2454 // word offset constant for Hi/Lo address computation
2455 SDValue WordOff = DAG.getConstant(sizeof(int), dl,
2456 StackSlot.getValueType());
2457 // set up Hi and Lo (into buffer) address based on endian
2458 SDValue Hi = StackSlot;
2459 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2460 StackSlot, WordOff);
2461 if (DAG.getDataLayout().isLittleEndian())
2464 // if signed map to unsigned space
2467 // constant used to invert sign bit (signed to unsigned mapping)
2468 SDValue SignBit = DAG.getConstant(0x80000000u, dl, MVT::i32);
2469 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2473 // store the lo of the constructed double - based on integer input
2474 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2475 Op0Mapped, Lo, MachinePointerInfo(),
2477 // initial hi portion of constructed double
2478 SDValue InitialHi = DAG.getConstant(0x43300000u, dl, MVT::i32);
2479 // store the hi of the constructed double - biased exponent
2480 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2481 MachinePointerInfo(),
2483 // load the constructed double
2484 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2485 MachinePointerInfo(), false, false, false, 0);
2486 // FP constant to bias correct the final result
2487 SDValue Bias = DAG.getConstantFP(isSigned ?
2488 BitsToDouble(0x4330000080000000ULL) :
2489 BitsToDouble(0x4330000000000000ULL),
2491 // subtract the bias
2492 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2495 // handle final rounding
2496 if (DestVT == MVT::f64) {
2499 } else if (DestVT.bitsLT(MVT::f64)) {
2500 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2501 DAG.getIntPtrConstant(0, dl));
2502 } else if (DestVT.bitsGT(MVT::f64)) {
2503 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2507 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2508 // Code below here assumes !isSigned without checking again.
2510 // Implementation of unsigned i64 to f64 following the algorithm in
2511 // __floatundidf in compiler_rt. This implementation has the advantage
2512 // of performing rounding correctly, both in the default rounding mode
2513 // and in all alternate rounding modes.
2514 // TODO: Generalize this for use with other types.
2515 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2517 DAG.getConstant(UINT64_C(0x4330000000000000), dl, MVT::i64);
2518 SDValue TwoP84PlusTwoP52 =
2519 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), dl,
2522 DAG.getConstant(UINT64_C(0x4530000000000000), dl, MVT::i64);
2524 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2525 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2526 DAG.getConstant(32, dl, MVT::i64));
2527 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2528 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2529 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2530 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2531 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2533 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2536 // Implementation of unsigned i64 to f32.
2537 // TODO: Generalize this for use with other types.
2538 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2539 // For unsigned conversions, convert them to signed conversions using the
2540 // algorithm from the x86_64 __floatundidf in compiler_rt.
2542 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2544 SDValue ShiftConst = DAG.getConstant(
2545 1, dl, TLI.getShiftAmountTy(Op0.getValueType(), DAG.getDataLayout()));
2546 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2547 SDValue AndConst = DAG.getConstant(1, dl, MVT::i64);
2548 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2549 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2551 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2552 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2554 // TODO: This really should be implemented using a branch rather than a
2555 // select. We happen to get lucky and machinesink does the right
2556 // thing most of the time. This would be a good candidate for a
2557 //pseudo-op, or, even better, for whole-function isel.
2558 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2559 Op0, DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
2560 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2563 // Otherwise, implement the fully general conversion.
2565 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2566 DAG.getConstant(UINT64_C(0xfffffffffffff800), dl, MVT::i64));
2567 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2568 DAG.getConstant(UINT64_C(0x800), dl, MVT::i64));
2569 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2570 DAG.getConstant(UINT64_C(0x7ff), dl, MVT::i64));
2571 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), And2,
2572 DAG.getConstant(UINT64_C(0), dl, MVT::i64),
2574 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2575 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), Op0,
2576 DAG.getConstant(UINT64_C(0x0020000000000000), dl,
2579 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2580 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType(), DAG.getDataLayout());
2582 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2583 DAG.getConstant(32, dl, SHVT));
2584 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2585 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2587 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), dl,
2589 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2590 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2591 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2592 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2593 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2594 DAG.getIntPtrConstant(0, dl));
2597 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2599 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2601 DAG.getConstant(0, dl, Op0.getValueType()),
2603 SDValue Zero = DAG.getIntPtrConstant(0, dl),
2604 Four = DAG.getIntPtrConstant(4, dl);
2605 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2606 SignSet, Four, Zero);
2608 // If the sign bit of the integer is set, the large number will be treated
2609 // as a negative number. To counteract this, the dynamic code adds an
2610 // offset depending on the data type.
2612 switch (Op0.getSimpleValueType().SimpleTy) {
2613 default: llvm_unreachable("Unsupported integer type!");
2614 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2615 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2616 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2617 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2619 if (DAG.getDataLayout().isLittleEndian())
2621 Constant *FudgeFactor = ConstantInt::get(
2622 Type::getInt64Ty(*DAG.getContext()), FF);
2625 DAG.getConstantPool(FudgeFactor, TLI.getPointerTy(DAG.getDataLayout()));
2626 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2627 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2628 Alignment = std::min(Alignment, 4u);
2630 if (DestVT == MVT::f32)
2631 FudgeInReg = DAG.getLoad(
2632 MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2633 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2634 false, false, Alignment);
2636 SDValue Load = DAG.getExtLoad(
2637 ISD::EXTLOAD, dl, DestVT, DAG.getEntryNode(), CPIdx,
2638 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
2639 false, false, false, Alignment);
2640 HandleSDNode Handle(Load);
2641 LegalizeOp(Load.getNode());
2642 FudgeInReg = Handle.getValue();
2645 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2648 /// This function is responsible for legalizing a
2649 /// *INT_TO_FP operation of the specified operand when the target requests that
2650 /// we promote it. At this point, we know that the result and operand types are
2651 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2652 /// operation that takes a larger input.
2653 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2657 // First step, figure out the appropriate *INT_TO_FP operation to use.
2658 EVT NewInTy = LegalOp.getValueType();
2660 unsigned OpToUse = 0;
2662 // Scan for the appropriate larger type to use.
2664 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2665 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2667 // If the target supports SINT_TO_FP of this type, use it.
2668 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2669 OpToUse = ISD::SINT_TO_FP;
2672 if (isSigned) continue;
2674 // If the target supports UINT_TO_FP of this type, use it.
2675 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2676 OpToUse = ISD::UINT_TO_FP;
2680 // Otherwise, try a larger type.
2683 // Okay, we found the operation and type to use. Zero extend our input to the
2684 // desired type then run the operation on it.
2685 return DAG.getNode(OpToUse, dl, DestVT,
2686 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2687 dl, NewInTy, LegalOp));
2690 /// This function is responsible for legalizing a
2691 /// FP_TO_*INT operation of the specified operand when the target requests that
2692 /// we promote it. At this point, we know that the result and operand types are
2693 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2694 /// operation that returns a larger result.
2695 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2699 // First step, figure out the appropriate FP_TO*INT operation to use.
2700 EVT NewOutTy = DestVT;
2702 unsigned OpToUse = 0;
2704 // Scan for the appropriate larger type to use.
2706 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2707 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2709 // A larger signed type can hold all unsigned values of the requested type,
2710 // so using FP_TO_SINT is valid
2711 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2712 OpToUse = ISD::FP_TO_SINT;
2716 // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2717 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2718 OpToUse = ISD::FP_TO_UINT;
2722 // Otherwise, try a larger type.
2726 // Okay, we found the operation and type to use.
2727 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2729 // Truncate the result of the extended FP_TO_*INT operation to the desired
2731 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2734 /// Open code the operations for BSWAP of the specified operation.
2735 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2736 EVT VT = Op.getValueType();
2737 EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2738 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2739 switch (VT.getSimpleVT().SimpleTy) {
2740 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2742 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2743 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2744 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2746 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2747 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2748 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2749 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2750 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2751 DAG.getConstant(0xFF0000, dl, VT));
2752 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
2753 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2754 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2755 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2757 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2758 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2759 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2760 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2761 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2762 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2763 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2764 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2765 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7,
2766 DAG.getConstant(255ULL<<48, dl, VT));
2767 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6,
2768 DAG.getConstant(255ULL<<40, dl, VT));
2769 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5,
2770 DAG.getConstant(255ULL<<32, dl, VT));
2771 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4,
2772 DAG.getConstant(255ULL<<24, dl, VT));
2773 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2774 DAG.getConstant(255ULL<<16, dl, VT));
2775 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2,
2776 DAG.getConstant(255ULL<<8 , dl, VT));
2777 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2778 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2779 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2780 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2781 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2782 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2783 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2787 /// Expand the specified bitcount instruction into operations.
2788 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2791 default: llvm_unreachable("Cannot expand this yet!");
2793 EVT VT = Op.getValueType();
2794 EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2795 unsigned Len = VT.getSizeInBits();
2797 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2798 "CTPOP not implemented for this type.");
2800 // This is the "best" algorithm from
2801 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2803 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)),
2805 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)),
2807 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)),
2809 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)),
2812 // v = v - ((v >> 1) & 0x55555555...)
2813 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2814 DAG.getNode(ISD::AND, dl, VT,
2815 DAG.getNode(ISD::SRL, dl, VT, Op,
2816 DAG.getConstant(1, dl, ShVT)),
2818 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2819 Op = DAG.getNode(ISD::ADD, dl, VT,
2820 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2821 DAG.getNode(ISD::AND, dl, VT,
2822 DAG.getNode(ISD::SRL, dl, VT, Op,
2823 DAG.getConstant(2, dl, ShVT)),
2825 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2826 Op = DAG.getNode(ISD::AND, dl, VT,
2827 DAG.getNode(ISD::ADD, dl, VT, Op,
2828 DAG.getNode(ISD::SRL, dl, VT, Op,
2829 DAG.getConstant(4, dl, ShVT))),
2831 // v = (v * 0x01010101...) >> (Len - 8)
2832 Op = DAG.getNode(ISD::SRL, dl, VT,
2833 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2834 DAG.getConstant(Len - 8, dl, ShVT));
2838 case ISD::CTLZ_ZERO_UNDEF:
2839 // This trivially expands to CTLZ.
2840 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2842 // for now, we do this:
2843 // x = x | (x >> 1);
2844 // x = x | (x >> 2);
2846 // x = x | (x >>16);
2847 // x = x | (x >>32); // for 64-bit input
2848 // return popcount(~x);
2850 // Ref: "Hacker's Delight" by Henry Warren
2851 EVT VT = Op.getValueType();
2852 EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2853 unsigned len = VT.getSizeInBits();
2854 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2855 SDValue Tmp3 = DAG.getConstant(1ULL << i, dl, ShVT);
2856 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2857 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2859 Op = DAG.getNOT(dl, Op, VT);
2860 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2862 case ISD::CTTZ_ZERO_UNDEF:
2863 // This trivially expands to CTTZ.
2864 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2866 // for now, we use: { return popcount(~x & (x - 1)); }
2867 // unless the target has ctlz but not ctpop, in which case we use:
2868 // { return 32 - nlz(~x & (x-1)); }
2869 // Ref: "Hacker's Delight" by Henry Warren
2870 EVT VT = Op.getValueType();
2871 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2872 DAG.getNOT(dl, Op, VT),
2873 DAG.getNode(ISD::SUB, dl, VT, Op,
2874 DAG.getConstant(1, dl, VT)));
2875 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2876 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2877 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2878 return DAG.getNode(ISD::SUB, dl, VT,
2879 DAG.getConstant(VT.getSizeInBits(), dl, VT),
2880 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2881 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2886 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2887 unsigned Opc = Node->getOpcode();
2888 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2889 RTLIB::Libcall LC = RTLIB::getATOMIC(Opc, VT);
2890 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
2892 return ExpandChainLibCall(LC, Node, false);
2895 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2896 SmallVector<SDValue, 8> Results;
2898 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2900 switch (Node->getOpcode()) {
2903 case ISD::CTLZ_ZERO_UNDEF:
2905 case ISD::CTTZ_ZERO_UNDEF:
2906 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2907 Results.push_back(Tmp1);
2910 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2912 case ISD::FRAMEADDR:
2913 case ISD::RETURNADDR:
2914 case ISD::FRAME_TO_ARGS_OFFSET:
2915 Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
2917 case ISD::FLT_ROUNDS_:
2918 Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0)));
2920 case ISD::EH_RETURN:
2924 case ISD::EH_SJLJ_LONGJMP:
2925 // If the target didn't expand these, there's nothing to do, so just
2926 // preserve the chain and be done.
2927 Results.push_back(Node->getOperand(0));
2929 case ISD::READCYCLECOUNTER:
2930 // If the target didn't expand this, just return 'zero' and preserve the
2932 Results.append(Node->getNumValues() - 1,
2933 DAG.getConstant(0, dl, Node->getValueType(0)));
2934 Results.push_back(Node->getOperand(0));
2936 case ISD::EH_SJLJ_SETJMP:
2937 // If the target didn't expand this, just return 'zero' and preserve the
2939 Results.push_back(DAG.getConstant(0, dl, MVT::i32));
2940 Results.push_back(Node->getOperand(0));
2942 case ISD::ATOMIC_FENCE: {
2943 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2944 // FIXME: handle "fence singlethread" more efficiently.
2945 TargetLowering::ArgListTy Args;
2947 TargetLowering::CallLoweringInfo CLI(DAG);
2949 .setChain(Node->getOperand(0))
2950 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2951 DAG.getExternalSymbol("__sync_synchronize",
2952 TLI.getPointerTy(DAG.getDataLayout())),
2953 std::move(Args), 0);
2955 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2957 Results.push_back(CallResult.second);
2960 case ISD::ATOMIC_LOAD: {
2961 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2962 SDValue Zero = DAG.getConstant(0, dl, Node->getValueType(0));
2963 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2964 SDValue Swap = DAG.getAtomicCmpSwap(
2965 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2966 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
2967 cast<AtomicSDNode>(Node)->getMemOperand(),
2968 cast<AtomicSDNode>(Node)->getOrdering(),
2969 cast<AtomicSDNode>(Node)->getOrdering(),
2970 cast<AtomicSDNode>(Node)->getSynchScope());
2971 Results.push_back(Swap.getValue(0));
2972 Results.push_back(Swap.getValue(1));
2975 case ISD::ATOMIC_STORE: {
2976 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2977 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2978 cast<AtomicSDNode>(Node)->getMemoryVT(),
2979 Node->getOperand(0),
2980 Node->getOperand(1), Node->getOperand(2),
2981 cast<AtomicSDNode>(Node)->getMemOperand(),
2982 cast<AtomicSDNode>(Node)->getOrdering(),
2983 cast<AtomicSDNode>(Node)->getSynchScope());
2984 Results.push_back(Swap.getValue(1));
2987 // By default, atomic intrinsics are marked Legal and lowered. Targets
2988 // which don't support them directly, however, may want libcalls, in which
2989 // case they mark them Expand, and we get here.
2990 case ISD::ATOMIC_SWAP:
2991 case ISD::ATOMIC_LOAD_ADD:
2992 case ISD::ATOMIC_LOAD_SUB:
2993 case ISD::ATOMIC_LOAD_AND:
2994 case ISD::ATOMIC_LOAD_OR:
2995 case ISD::ATOMIC_LOAD_XOR:
2996 case ISD::ATOMIC_LOAD_NAND:
2997 case ISD::ATOMIC_LOAD_MIN:
2998 case ISD::ATOMIC_LOAD_MAX:
2999 case ISD::ATOMIC_LOAD_UMIN:
3000 case ISD::ATOMIC_LOAD_UMAX:
3001 case ISD::ATOMIC_CMP_SWAP: {
3002 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
3003 Results.push_back(Tmp.first);
3004 Results.push_back(Tmp.second);
3007 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
3008 // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
3009 // splits out the success value as a comparison. Expanding the resulting
3010 // ATOMIC_CMP_SWAP will produce a libcall.
3011 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
3012 SDValue Res = DAG.getAtomicCmpSwap(
3013 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
3014 Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
3015 Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand(),
3016 cast<AtomicSDNode>(Node)->getSuccessOrdering(),
3017 cast<AtomicSDNode>(Node)->getFailureOrdering(),
3018 cast<AtomicSDNode>(Node)->getSynchScope());
3020 SDValue Success = DAG.getSetCC(SDLoc(Node), Node->getValueType(1),
3021 Res, Node->getOperand(2), ISD::SETEQ);
3023 Results.push_back(Res.getValue(0));
3024 Results.push_back(Success);
3025 Results.push_back(Res.getValue(1));
3028 case ISD::DYNAMIC_STACKALLOC:
3029 ExpandDYNAMIC_STACKALLOC(Node, Results);
3031 case ISD::MERGE_VALUES:
3032 for (unsigned i = 0; i < Node->getNumValues(); i++)
3033 Results.push_back(Node->getOperand(i));
3036 EVT VT = Node->getValueType(0);
3038 Results.push_back(DAG.getConstant(0, dl, VT));
3040 assert(VT.isFloatingPoint() && "Unknown value type!");
3041 Results.push_back(DAG.getConstantFP(0, dl, VT));
3046 // If this operation is not supported, lower it to 'abort()' call
3047 TargetLowering::ArgListTy Args;
3048 TargetLowering::CallLoweringInfo CLI(DAG);
3050 .setChain(Node->getOperand(0))
3051 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3052 DAG.getExternalSymbol("abort",
3053 TLI.getPointerTy(DAG.getDataLayout())),
3054 std::move(Args), 0);
3055 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3057 Results.push_back(CallResult.second);
3062 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3063 Node->getValueType(0), dl);
3064 Results.push_back(Tmp1);
3066 case ISD::FP_EXTEND:
3067 Tmp1 = EmitStackConvert(Node->getOperand(0),
3068 Node->getOperand(0).getValueType(),
3069 Node->getValueType(0), dl);
3070 Results.push_back(Tmp1);
3072 case ISD::SIGN_EXTEND_INREG: {
3073 // NOTE: we could fall back on load/store here too for targets without
3074 // SAR. However, it is doubtful that any exist.
3075 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3076 EVT VT = Node->getValueType(0);
3077 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
3080 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
3081 ExtraVT.getScalarType().getSizeInBits();
3082 SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
3083 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3084 Node->getOperand(0), ShiftCst);
3085 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3086 Results.push_back(Tmp1);
3089 case ISD::FP_ROUND_INREG: {
3090 // The only way we can lower this is to turn it into a TRUNCSTORE,
3091 // EXTLOAD pair, targeting a temporary location (a stack slot).
3093 // NOTE: there is a choice here between constantly creating new stack
3094 // slots and always reusing the same one. We currently always create
3095 // new ones, as reuse may inhibit scheduling.
3096 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3097 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
3098 Node->getValueType(0), dl);
3099 Results.push_back(Tmp1);
3102 case ISD::SINT_TO_FP:
3103 case ISD::UINT_TO_FP:
3104 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3105 Node->getOperand(0), Node->getValueType(0), dl);
3106 Results.push_back(Tmp1);
3108 case ISD::FP_TO_SINT:
3109 if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
3110 Results.push_back(Tmp1);
3112 case ISD::FP_TO_UINT: {
3113 SDValue True, False;
3114 EVT VT = Node->getOperand(0).getValueType();
3115 EVT NVT = Node->getValueType(0);
3116 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
3117 APInt::getNullValue(VT.getSizeInBits()));
3118 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3119 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3120 Tmp1 = DAG.getConstantFP(apf, dl, VT);
3121 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
3122 Node->getOperand(0),
3124 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3125 // TODO: Should any fast-math-flags be set for the FSUB?
3126 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3127 DAG.getNode(ISD::FSUB, dl, VT,
3128 Node->getOperand(0), Tmp1));
3129 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3130 DAG.getConstant(x, dl, NVT));
3131 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
3132 Results.push_back(Tmp1);
3136 Results.push_back(DAG.expandVAArg(Node));
3137 Results.push_back(Results[0].getValue(1));
3140 Results.push_back(DAG.expandVACopy(Node));
3142 case ISD::EXTRACT_VECTOR_ELT:
3143 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3144 // This must be an access of the only element. Return it.
3145 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3146 Node->getOperand(0));
3148 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3149 Results.push_back(Tmp1);
3151 case ISD::EXTRACT_SUBVECTOR:
3152 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3154 case ISD::INSERT_SUBVECTOR:
3155 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3157 case ISD::CONCAT_VECTORS: {
3158 Results.push_back(ExpandVectorBuildThroughStack(Node));
3161 case ISD::SCALAR_TO_VECTOR:
3162 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3164 case ISD::INSERT_VECTOR_ELT:
3165 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3166 Node->getOperand(1),
3167 Node->getOperand(2), dl));
3169 case ISD::VECTOR_SHUFFLE: {
3170 SmallVector<int, 32> NewMask;
3171 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3173 EVT VT = Node->getValueType(0);
3174 EVT EltVT = VT.getVectorElementType();
3175 SDValue Op0 = Node->getOperand(0);
3176 SDValue Op1 = Node->getOperand(1);
3177 if (!TLI.isTypeLegal(EltVT)) {
3179 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3181 // BUILD_VECTOR operands are allowed to be wider than the element type.
3182 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3184 if (NewEltVT.bitsLT(EltVT)) {
3186 // Convert shuffle node.
3187 // If original node was v4i64 and the new EltVT is i32,
3188 // cast operands to v8i32 and re-build the mask.
3190 // Calculate new VT, the size of the new VT should be equal to original.
3192 EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3193 VT.getSizeInBits() / NewEltVT.getSizeInBits());
3194 assert(NewVT.bitsEq(VT));
3196 // cast operands to new VT
3197 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3198 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3200 // Convert the shuffle mask
3201 unsigned int factor =
3202 NewVT.getVectorNumElements()/VT.getVectorNumElements();
3204 // EltVT gets smaller
3207 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3209 for (unsigned fi = 0; fi < factor; ++fi)
3210 NewMask.push_back(Mask[i]);
3213 for (unsigned fi = 0; fi < factor; ++fi)
3214 NewMask.push_back(Mask[i]*factor+fi);
3222 unsigned NumElems = VT.getVectorNumElements();
3223 SmallVector<SDValue, 16> Ops;
3224 for (unsigned i = 0; i != NumElems; ++i) {
3226 Ops.push_back(DAG.getUNDEF(EltVT));
3229 unsigned Idx = Mask[i];
3231 Ops.push_back(DAG.getNode(
3232 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
3233 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3235 Ops.push_back(DAG.getNode(
3236 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1,
3237 DAG.getConstant(Idx - NumElems, dl,
3238 TLI.getVectorIdxTy(DAG.getDataLayout()))));
3241 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3242 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3243 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3244 Results.push_back(Tmp1);
3247 case ISD::EXTRACT_ELEMENT: {
3248 EVT OpTy = Node->getOperand(0).getValueType();
3249 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3251 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3252 DAG.getConstant(OpTy.getSizeInBits() / 2, dl,
3253 TLI.getShiftAmountTy(
3254 Node->getOperand(0).getValueType(),
3255 DAG.getDataLayout())));
3256 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3259 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3260 Node->getOperand(0));
3262 Results.push_back(Tmp1);
3265 case ISD::STACKSAVE:
3266 // Expand to CopyFromReg if the target set
3267 // StackPointerRegisterToSaveRestore.
3268 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3269 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3270 Node->getValueType(0)));
3271 Results.push_back(Results[0].getValue(1));
3273 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3274 Results.push_back(Node->getOperand(0));
3277 case ISD::STACKRESTORE:
3278 // Expand to CopyToReg if the target set
3279 // StackPointerRegisterToSaveRestore.
3280 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3281 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3282 Node->getOperand(1)));
3284 Results.push_back(Node->getOperand(0));
3287 case ISD::FCOPYSIGN:
3288 Results.push_back(ExpandFCOPYSIGN(Node));
3291 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3292 Tmp1 = DAG.getConstantFP(-0.0, dl, Node->getValueType(0));
3293 // TODO: If FNEG has fast-math-flags, propagate them to the FSUB.
3294 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3295 Node->getOperand(0));
3296 Results.push_back(Tmp1);
3299 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3300 EVT VT = Node->getValueType(0);
3301 Tmp1 = Node->getOperand(0);
3302 Tmp2 = DAG.getConstantFP(0.0, dl, VT);
3303 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
3304 Tmp1, Tmp2, ISD::SETUGT);
3305 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3306 Tmp1 = DAG.getSelect(dl, VT, Tmp2, Tmp1, Tmp3);
3307 Results.push_back(Tmp1);
3314 // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
3316 switch (Node->getOpcode()) {
3317 default: llvm_unreachable("How did we get here?");
3318 case ISD::SMAX: Pred = ISD::SETGT; break;
3319 case ISD::SMIN: Pred = ISD::SETLT; break;
3320 case ISD::UMAX: Pred = ISD::SETUGT; break;
3321 case ISD::UMIN: Pred = ISD::SETULT; break;
3323 Tmp1 = Node->getOperand(0);
3324 Tmp2 = Node->getOperand(1);
3325 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp1, Tmp2, Pred);
3326 Results.push_back(Tmp1);
3331 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
3332 RTLIB::FMIN_F80, RTLIB::FMIN_F128,
3333 RTLIB::FMIN_PPCF128));
3336 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
3337 RTLIB::FMAX_F80, RTLIB::FMAX_F128,
3338 RTLIB::FMAX_PPCF128));
3341 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3342 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3343 RTLIB::SQRT_PPCF128));
3347 EVT VT = Node->getValueType(0);
3348 bool isSIN = Node->getOpcode() == ISD::FSIN;
3349 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3350 // fcos which share the same operand and both are used.
3351 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3352 canCombineSinCosLibcall(Node, TLI, TM))
3353 && useSinCos(Node)) {
3354 SDVTList VTs = DAG.getVTList(VT, VT);
3355 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3357 Tmp1 = Tmp1.getValue(1);
3358 Results.push_back(Tmp1);
3360 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3361 RTLIB::SIN_F80, RTLIB::SIN_F128,
3362 RTLIB::SIN_PPCF128));
3364 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3365 RTLIB::COS_F80, RTLIB::COS_F128,
3366 RTLIB::COS_PPCF128));
3371 // Expand into sincos libcall.
3372 ExpandSinCosLibCall(Node, Results);
3375 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3376 RTLIB::LOG_F80, RTLIB::LOG_F128,
3377 RTLIB::LOG_PPCF128));
3380 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3381 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3382 RTLIB::LOG2_PPCF128));
3385 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3386 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3387 RTLIB::LOG10_PPCF128));
3390 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3391 RTLIB::EXP_F80, RTLIB::EXP_F128,
3392 RTLIB::EXP_PPCF128));
3395 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3396 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3397 RTLIB::EXP2_PPCF128));
3400 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3401 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3402 RTLIB::TRUNC_PPCF128));
3405 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3406 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3407 RTLIB::FLOOR_PPCF128));
3410 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3411 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3412 RTLIB::CEIL_PPCF128));
3415 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3416 RTLIB::RINT_F80, RTLIB::RINT_F128,
3417 RTLIB::RINT_PPCF128));
3419 case ISD::FNEARBYINT:
3420 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3421 RTLIB::NEARBYINT_F64,
3422 RTLIB::NEARBYINT_F80,
3423 RTLIB::NEARBYINT_F128,
3424 RTLIB::NEARBYINT_PPCF128));
3427 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3431 RTLIB::ROUND_PPCF128));
3434 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3435 RTLIB::POWI_F80, RTLIB::POWI_F128,
3436 RTLIB::POWI_PPCF128));
3439 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3440 RTLIB::POW_F80, RTLIB::POW_F128,
3441 RTLIB::POW_PPCF128));
3444 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3445 RTLIB::DIV_F80, RTLIB::DIV_F128,
3446 RTLIB::DIV_PPCF128));
3449 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3450 RTLIB::REM_F80, RTLIB::REM_F128,
3451 RTLIB::REM_PPCF128));
3454 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3455 RTLIB::FMA_F80, RTLIB::FMA_F128,
3456 RTLIB::FMA_PPCF128));
3459 llvm_unreachable("Illegal fmad should never be formed");
3462 Results.push_back(ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
3463 RTLIB::ADD_F80, RTLIB::ADD_F128,
3464 RTLIB::ADD_PPCF128));
3467 Results.push_back(ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
3468 RTLIB::MUL_F80, RTLIB::MUL_F128,
3469 RTLIB::MUL_PPCF128));
3471 case ISD::FP16_TO_FP: {
3472 if (Node->getValueType(0) == MVT::f32) {
3473 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3477 // We can extend to types bigger than f32 in two steps without changing the
3478 // result. Since "f16 -> f32" is much more commonly available, give CodeGen
3479 // the option of emitting that before resorting to a libcall.
3481 DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3483 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
3486 case ISD::FP_TO_FP16: {
3487 if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {
3488 SDValue Op = Node->getOperand(0);
3489 MVT SVT = Op.getSimpleValueType();
3490 if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3491 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3492 // Under fastmath, we can expand this node into a fround followed by
3493 // a float-half conversion.
3494 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
3495 DAG.getIntPtrConstant(0, dl));
3497 DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, FloatVal));
3503 RTLIB::getFPROUND(Node->getOperand(0).getValueType(), MVT::f16);
3504 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
3505 Results.push_back(ExpandLibCall(LC, Node, false));
3508 case ISD::ConstantFP: {
3509 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3510 // Check to see if this FP immediate is already legal.
3511 // If this is a legal constant, turn it into a TargetConstantFP node.
3512 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3513 Results.push_back(ExpandConstantFP(CFP, true));
3517 EVT VT = Node->getValueType(0);
3518 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3519 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3520 const SDNodeFlags *Flags = &cast<BinaryWithFlagsSDNode>(Node)->Flags;
3521 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3522 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags);
3523 Results.push_back(Tmp1);
3525 Results.push_back(ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
3526 RTLIB::SUB_F80, RTLIB::SUB_F128,
3527 RTLIB::SUB_PPCF128));
3532 EVT VT = Node->getValueType(0);
3533 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3534 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3535 "Don't know how to expand this subtraction!");
3536 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3537 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
3539 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT));
3540 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3545 EVT VT = Node->getValueType(0);
3546 bool isSigned = Node->getOpcode() == ISD::SREM;
3547 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3548 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3549 Tmp2 = Node->getOperand(0);
3550 Tmp3 = Node->getOperand(1);
3551 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3552 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3553 // If div is legal, it's better to do the normal expansion
3554 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
3555 useDivRem(Node, isSigned, false))) {
3556 SDVTList VTs = DAG.getVTList(VT, VT);
3557 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3558 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3560 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3561 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3562 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3563 } else if (isSigned)
3564 Tmp1 = ExpandIntLibCall(Node, true,
3566 RTLIB::SREM_I16, RTLIB::SREM_I32,
3567 RTLIB::SREM_I64, RTLIB::SREM_I128);
3569 Tmp1 = ExpandIntLibCall(Node, false,
3571 RTLIB::UREM_I16, RTLIB::UREM_I32,
3572 RTLIB::UREM_I64, RTLIB::UREM_I128);
3573 Results.push_back(Tmp1);
3578 bool isSigned = Node->getOpcode() == ISD::SDIV;
3579 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3580 EVT VT = Node->getValueType(0);
3581 SDVTList VTs = DAG.getVTList(VT, VT);
3582 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3583 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3584 useDivRem(Node, isSigned, true)))
3585 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3586 Node->getOperand(1));
3588 Tmp1 = ExpandIntLibCall(Node, true,
3590 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3591 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3593 Tmp1 = ExpandIntLibCall(Node, false,
3595 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3596 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3597 Results.push_back(Tmp1);
3602 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3604 EVT VT = Node->getValueType(0);
3605 SDVTList VTs = DAG.getVTList(VT, VT);
3606 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3607 "If this wasn't legal, it shouldn't have been created!");
3608 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3609 Node->getOperand(1));
3610 Results.push_back(Tmp1.getValue(1));
3615 // Expand into divrem libcall
3616 ExpandDivRemLibCall(Node, Results);
3619 EVT VT = Node->getValueType(0);
3620 SDVTList VTs = DAG.getVTList(VT, VT);
3621 // See if multiply or divide can be lowered using two-result operations.
3622 // We just need the low half of the multiply; try both the signed
3623 // and unsigned forms. If the target supports both SMUL_LOHI and
3624 // UMUL_LOHI, form a preference by checking which forms of plain
3625 // MULH it supports.
3626 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3627 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3628 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3629 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3630 unsigned OpToUse = 0;
3631 if (HasSMUL_LOHI && !HasMULHS) {
3632 OpToUse = ISD::SMUL_LOHI;
3633 } else if (HasUMUL_LOHI && !HasMULHU) {
3634 OpToUse = ISD::UMUL_LOHI;
3635 } else if (HasSMUL_LOHI) {
3636 OpToUse = ISD::SMUL_LOHI;
3637 } else if (HasUMUL_LOHI) {
3638 OpToUse = ISD::UMUL_LOHI;
3641 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3642 Node->getOperand(1)));
3647 EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3648 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3649 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3650 TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3651 TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3652 TLI.expandMUL(Node, Lo, Hi, HalfType, DAG)) {
3653 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3654 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3656 DAG.getConstant(HalfType.getSizeInBits(), dl,
3657 TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3658 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3659 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3663 Tmp1 = ExpandIntLibCall(Node, false,
3665 RTLIB::MUL_I16, RTLIB::MUL_I32,
3666 RTLIB::MUL_I64, RTLIB::MUL_I128);
3667 Results.push_back(Tmp1);
3672 SDValue LHS = Node->getOperand(0);
3673 SDValue RHS = Node->getOperand(1);
3674 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3675 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3677 Results.push_back(Sum);
3678 EVT ResultType = Node->getValueType(1);
3679 EVT OType = getSetCCResultType(Node->getValueType(0));
3681 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
3683 // LHSSign -> LHS >= 0
3684 // RHSSign -> RHS >= 0
3685 // SumSign -> Sum >= 0
3688 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3690 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3692 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3693 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3694 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3695 Node->getOpcode() == ISD::SADDO ?
3696 ISD::SETEQ : ISD::SETNE);
3698 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3699 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3701 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3702 Results.push_back(DAG.getBoolExtOrTrunc(Cmp, dl, ResultType, ResultType));
3707 SDValue LHS = Node->getOperand(0);
3708 SDValue RHS = Node->getOperand(1);
3709 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3710 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3712 Results.push_back(Sum);
3714 EVT ResultType = Node->getValueType(1);
3715 EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3717 = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT;
3718 SDValue SetCC = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3720 Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType));
3725 EVT VT = Node->getValueType(0);
3726 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3727 SDValue LHS = Node->getOperand(0);
3728 SDValue RHS = Node->getOperand(1);
3731 static const unsigned Ops[2][3] =
3732 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3733 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3734 bool isSigned = Node->getOpcode() == ISD::SMULO;
3735 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3736 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3737 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3738 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3739 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3741 TopHalf = BottomHalf.getValue(1);
3742 } else if (TLI.isTypeLegal(WideVT)) {
3743 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3744 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3745 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3746 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3747 DAG.getIntPtrConstant(0, dl));
3748 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3749 DAG.getIntPtrConstant(1, dl));
3751 // We can fall back to a libcall with an illegal type for the MUL if we
3752 // have a libcall big enough.
3753 // Also, we can fall back to a division in some cases, but that's a big
3754 // performance hit in the general case.
3755 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3756 if (WideVT == MVT::i16)
3757 LC = RTLIB::MUL_I16;
3758 else if (WideVT == MVT::i32)
3759 LC = RTLIB::MUL_I32;
3760 else if (WideVT == MVT::i64)
3761 LC = RTLIB::MUL_I64;
3762 else if (WideVT == MVT::i128)
3763 LC = RTLIB::MUL_I128;
3764 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3766 // The high part is obtained by SRA'ing all but one of the bits of low
3768 unsigned LoSize = VT.getSizeInBits();
3770 DAG.getNode(ISD::SRA, dl, VT, RHS,
3771 DAG.getConstant(LoSize - 1, dl,
3772 TLI.getPointerTy(DAG.getDataLayout())));
3774 DAG.getNode(ISD::SRA, dl, VT, LHS,
3775 DAG.getConstant(LoSize - 1, dl,
3776 TLI.getPointerTy(DAG.getDataLayout())));
3778 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3779 // pre-lowered to the correct types. This all depends upon WideVT not
3780 // being a legal type for the architecture and thus has to be split to
3782 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3783 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3784 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3785 DAG.getIntPtrConstant(0, dl));
3786 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3787 DAG.getIntPtrConstant(1, dl));
3788 // Ret is a node with an illegal type. Because such things are not
3789 // generally permitted during this phase of legalization, make sure the
3790 // node has no more uses. The above EXTRACT_ELEMENT nodes should have been
3792 assert(Ret->use_empty() &&
3793 "Unexpected uses of illegally type from expanded lib call.");
3797 Tmp1 = DAG.getConstant(
3798 VT.getSizeInBits() - 1, dl,
3799 TLI.getShiftAmountTy(BottomHalf.getValueType(), DAG.getDataLayout()));
3800 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3801 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3804 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3805 DAG.getConstant(0, dl, VT), ISD::SETNE);
3807 Results.push_back(BottomHalf);
3808 Results.push_back(TopHalf);
3811 case ISD::BUILD_PAIR: {
3812 EVT PairTy = Node->getValueType(0);
3813 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3814 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3816 ISD::SHL, dl, PairTy, Tmp2,
3817 DAG.getConstant(PairTy.getSizeInBits() / 2, dl,
3818 TLI.getShiftAmountTy(PairTy, DAG.getDataLayout())));
3819 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3823 Tmp1 = Node->getOperand(0);
3824 Tmp2 = Node->getOperand(1);
3825 Tmp3 = Node->getOperand(2);
3826 if (Tmp1.getOpcode() == ISD::SETCC) {
3827 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3829 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3831 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3832 DAG.getConstant(0, dl, Tmp1.getValueType()),
3833 Tmp2, Tmp3, ISD::SETNE);
3835 Results.push_back(Tmp1);
3838 SDValue Chain = Node->getOperand(0);
3839 SDValue Table = Node->getOperand(1);
3840 SDValue Index = Node->getOperand(2);
3842 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
3844 const DataLayout &TD = DAG.getDataLayout();
3845 unsigned EntrySize =
3846 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3848 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
3849 DAG.getConstant(EntrySize, dl, Index.getValueType()));
3850 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3853 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3854 SDValue LD = DAG.getExtLoad(
3855 ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3856 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), MemVT,
3857 false, false, false, 0);
3859 if (TM.getRelocationModel() == Reloc::PIC_) {
3860 // For PIC, the sequence is:
3861 // BRIND(load(Jumptable + index) + RelocBase)
3862 // RelocBase can be JumpTable, GOT or some sort of global base.
3863 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3864 TLI.getPICJumpTableRelocBase(Table, DAG));
3866 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3867 Results.push_back(Tmp1);
3871 // Expand brcond's setcc into its constituent parts and create a BR_CC
3873 Tmp1 = Node->getOperand(0);
3874 Tmp2 = Node->getOperand(1);
3875 if (Tmp2.getOpcode() == ISD::SETCC) {
3876 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3877 Tmp1, Tmp2.getOperand(2),
3878 Tmp2.getOperand(0), Tmp2.getOperand(1),
3879 Node->getOperand(2));
3881 // We test only the i1 bit. Skip the AND if UNDEF.
3882 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3883 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3884 DAG.getConstant(1, dl, Tmp2.getValueType()));
3885 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3886 DAG.getCondCode(ISD::SETNE), Tmp3,
3887 DAG.getConstant(0, dl, Tmp3.getValueType()),
3888 Node->getOperand(2));
3890 Results.push_back(Tmp1);
3893 Tmp1 = Node->getOperand(0);
3894 Tmp2 = Node->getOperand(1);
3895 Tmp3 = Node->getOperand(2);
3896 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3897 Tmp3, NeedInvert, dl);
3900 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3901 // condition code, create a new SETCC node.
3903 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3906 // If we expanded the SETCC by inverting the condition code, then wrap
3907 // the existing SETCC in a NOT to restore the intended condition.
3909 Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3911 Results.push_back(Tmp1);
3915 // Otherwise, SETCC for the given comparison type must be completely
3916 // illegal; expand it into a SELECT_CC.
3917 EVT VT = Node->getValueType(0);
3919 switch (TLI.getBooleanContents(Tmp1->getValueType(0))) {
3920 case TargetLowering::ZeroOrOneBooleanContent:
3921 case TargetLowering::UndefinedBooleanContent:
3924 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3928 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3929 DAG.getConstant(TrueValue, dl, VT),
3930 DAG.getConstant(0, dl, VT),
3932 Results.push_back(Tmp1);
3935 case ISD::SELECT_CC: {
3936 Tmp1 = Node->getOperand(0); // LHS
3937 Tmp2 = Node->getOperand(1); // RHS
3938 Tmp3 = Node->getOperand(2); // True
3939 Tmp4 = Node->getOperand(3); // False
3940 EVT VT = Node->getValueType(0);
3941 SDValue CC = Node->getOperand(4);
3942 ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3944 if (TLI.isCondCodeLegal(CCOp, Tmp1.getSimpleValueType())) {
3945 // If the condition code is legal, then we need to expand this
3946 // node using SETCC and SELECT.
3947 EVT CmpVT = Tmp1.getValueType();
3948 assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3949 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3952 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), CmpVT);
3953 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
3954 Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
3958 // SELECT_CC is legal, so the condition code must not be.
3959 bool Legalized = false;
3960 // Try to legalize by inverting the condition. This is for targets that
3961 // might support an ordered version of a condition, but not the unordered
3962 // version (or vice versa).
3963 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
3964 Tmp1.getValueType().isInteger());
3965 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
3966 // Use the new condition code and swap true and false
3968 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3970 // If The inverse is not legal, then try to swap the arguments using
3971 // the inverse condition code.
3972 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3973 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
3974 // The swapped inverse condition is legal, so swap true and false,
3977 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3982 Legalized = LegalizeSetCCCondCode(
3983 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3986 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3988 // If we expanded the SETCC by inverting the condition code, then swap
3989 // the True/False operands to match.
3991 std::swap(Tmp3, Tmp4);
3993 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3994 // condition code, create a new SELECT_CC node.
3996 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3997 Tmp1, Tmp2, Tmp3, Tmp4, CC);
3999 Tmp2 = DAG.getConstant(0, dl, Tmp1.getValueType());
4000 CC = DAG.getCondCode(ISD::SETNE);
4001 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
4002 Tmp2, Tmp3, Tmp4, CC);
4005 Results.push_back(Tmp1);
4009 Tmp1 = Node->getOperand(0); // Chain
4010 Tmp2 = Node->getOperand(2); // LHS
4011 Tmp3 = Node->getOperand(3); // RHS
4012 Tmp4 = Node->getOperand(1); // CC
4014 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
4015 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
4017 assert(Legalized && "Can't legalize BR_CC with legal condition!");
4019 // If we expanded the SETCC by inverting the condition code, then wrap
4020 // the existing SETCC in a NOT to restore the intended condition.
4022 Tmp4 = DAG.getNOT(dl, Tmp4, Tmp4->getValueType(0));
4024 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
4026 if (Tmp4.getNode()) {
4027 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
4028 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
4030 Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
4031 Tmp4 = DAG.getCondCode(ISD::SETNE);
4032 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
4033 Tmp2, Tmp3, Node->getOperand(4));
4035 Results.push_back(Tmp1);
4038 case ISD::BUILD_VECTOR:
4039 Results.push_back(ExpandBUILD_VECTOR(Node));
4044 // Scalarize vector SRA/SRL/SHL.
4045 EVT VT = Node->getValueType(0);
4046 assert(VT.isVector() && "Unable to legalize non-vector shift");
4047 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
4048 unsigned NumElem = VT.getVectorNumElements();
4050 SmallVector<SDValue, 8> Scalars;
4051 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
4052 SDValue Ex = DAG.getNode(
4053 ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(0),
4054 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4055 SDValue Sh = DAG.getNode(
4056 ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(1),
4057 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4058 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
4059 VT.getScalarType(), Ex, Sh));
4062 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Scalars);
4063 ReplaceNode(SDValue(Node, 0), Result);
4066 case ISD::GLOBAL_OFFSET_TABLE:
4067 case ISD::GlobalAddress:
4068 case ISD::GlobalTLSAddress:
4069 case ISD::ExternalSymbol:
4070 case ISD::ConstantPool:
4071 case ISD::JumpTable:
4072 case ISD::INTRINSIC_W_CHAIN:
4073 case ISD::INTRINSIC_WO_CHAIN:
4074 case ISD::INTRINSIC_VOID:
4075 // FIXME: Custom lowering for these operations shouldn't return null!
4079 // Replace the original node with the legalized result.
4080 if (!Results.empty())
4081 ReplaceNode(Node, Results.data());
4084 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4085 SmallVector<SDValue, 8> Results;
4086 MVT OVT = Node->getSimpleValueType(0);
4087 if (Node->getOpcode() == ISD::UINT_TO_FP ||
4088 Node->getOpcode() == ISD::SINT_TO_FP ||
4089 Node->getOpcode() == ISD::SETCC) {
4090 OVT = Node->getOperand(0).getSimpleValueType();
4092 if (Node->getOpcode() == ISD::BR_CC)
4093 OVT = Node->getOperand(2).getSimpleValueType();
4094 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4096 SDValue Tmp1, Tmp2, Tmp3;
4097 switch (Node->getOpcode()) {
4099 case ISD::CTTZ_ZERO_UNDEF:
4101 case ISD::CTLZ_ZERO_UNDEF:
4103 // Zero extend the argument.
4104 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4105 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4106 // already the correct result.
4107 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4108 if (Node->getOpcode() == ISD::CTTZ) {
4109 // FIXME: This should set a bit in the zero extended value instead.
4110 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
4111 Tmp1, DAG.getConstant(NVT.getSizeInBits(), dl, NVT),
4113 Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
4114 DAG.getConstant(OVT.getSizeInBits(), dl, NVT), Tmp1);
4115 } else if (Node->getOpcode() == ISD::CTLZ ||
4116 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4117 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4118 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4119 DAG.getConstant(NVT.getSizeInBits() -
4120 OVT.getSizeInBits(), dl, NVT));
4122 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4125 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4126 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4127 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4129 ISD::SRL, dl, NVT, Tmp1,
4130 DAG.getConstant(DiffBits, dl,
4131 TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
4132 Results.push_back(Tmp1);
4135 case ISD::FP_TO_UINT:
4136 case ISD::FP_TO_SINT:
4137 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4138 Node->getOpcode() == ISD::FP_TO_SINT, dl);
4139 Results.push_back(Tmp1);
4141 case ISD::UINT_TO_FP:
4142 case ISD::SINT_TO_FP:
4143 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4144 Node->getOpcode() == ISD::SINT_TO_FP, dl);
4145 Results.push_back(Tmp1);
4148 SDValue Chain = Node->getOperand(0); // Get the chain.
4149 SDValue Ptr = Node->getOperand(1); // Get the pointer.
4152 if (OVT.isVector()) {
4153 TruncOp = ISD::BITCAST;
4155 assert(OVT.isInteger()
4156 && "VAARG promotion is supported only for vectors or integer types");
4157 TruncOp = ISD::TRUNCATE;
4160 // Perform the larger operation, then convert back
4161 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4162 Node->getConstantOperandVal(3));
4163 Chain = Tmp1.getValue(1);
4165 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4167 // Modified the chain result - switch anything that used the old chain to
4169 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4170 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4172 UpdatedNodes->insert(Tmp2.getNode());
4173 UpdatedNodes->insert(Chain.getNode());
4181 unsigned ExtOp, TruncOp;
4182 if (OVT.isVector()) {
4183 ExtOp = ISD::BITCAST;
4184 TruncOp = ISD::BITCAST;
4186 assert(OVT.isInteger() && "Cannot promote logic operation");
4187 ExtOp = ISD::ANY_EXTEND;
4188 TruncOp = ISD::TRUNCATE;
4190 // Promote each of the values to the new type.
4191 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4192 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4193 // Perform the larger operation, then convert back
4194 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4195 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4199 unsigned ExtOp, TruncOp;
4200 if (Node->getValueType(0).isVector() ||
4201 Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4202 ExtOp = ISD::BITCAST;
4203 TruncOp = ISD::BITCAST;
4204 } else if (Node->getValueType(0).isInteger()) {
4205 ExtOp = ISD::ANY_EXTEND;
4206 TruncOp = ISD::TRUNCATE;
4208 ExtOp = ISD::FP_EXTEND;
4209 TruncOp = ISD::FP_ROUND;
4211 Tmp1 = Node->getOperand(0);
4212 // Promote each of the values to the new type.
4213 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4214 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4215 // Perform the larger operation, then round down.
4216 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4217 if (TruncOp != ISD::FP_ROUND)
4218 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4220 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4221 DAG.getIntPtrConstant(0, dl));
4222 Results.push_back(Tmp1);
4225 case ISD::VECTOR_SHUFFLE: {
4226 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4228 // Cast the two input vectors.
4229 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4230 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4232 // Convert the shuffle mask to the right # elements.
4233 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4234 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4235 Results.push_back(Tmp1);
4239 unsigned ExtOp = ISD::FP_EXTEND;
4240 if (NVT.isInteger()) {
4241 ISD::CondCode CCCode =
4242 cast<CondCodeSDNode>(Node->getOperand(2))->get();
4243 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4245 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4246 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4247 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4248 Tmp1, Tmp2, Node->getOperand(2)));
4252 unsigned ExtOp = ISD::FP_EXTEND;
4253 if (NVT.isInteger()) {
4254 ISD::CondCode CCCode =
4255 cast<CondCodeSDNode>(Node->getOperand(1))->get();
4256 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4258 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4259 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
4260 Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0),
4261 Node->getOperand(0), Node->getOperand(1),
4262 Tmp1, Tmp2, Node->getOperand(4)));
4273 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4274 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4275 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2,
4277 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4278 Tmp3, DAG.getIntPtrConstant(0, dl)));
4282 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4283 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4284 Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
4286 DAG.getNode(ISD::FP_ROUND, dl, OVT,
4287 DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
4288 DAG.getIntPtrConstant(0, dl)));
4291 case ISD::FCOPYSIGN:
4293 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4294 Tmp2 = Node->getOperand(1);
4295 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4297 // fcopysign doesn't change anything but the sign bit, so
4298 // (fp_round (fcopysign (fpext a), b))
4300 // (fp_round (fpext a))
4301 // which is a no-op. Mark it as a TRUNCating FP_ROUND.
4302 const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN);
4303 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4304 Tmp3, DAG.getIntPtrConstant(isTrunc, dl)));
4310 case ISD::FNEARBYINT:
4323 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4324 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4325 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4326 Tmp2, DAG.getIntPtrConstant(0, dl)));
4331 // Replace the original node with the legalized result.
4332 if (!Results.empty())
4333 ReplaceNode(Node, Results.data());
4336 /// This is the entry point for the file.
4337 void SelectionDAG::Legalize() {
4338 AssignTopologicalOrder();
4340 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4341 SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
4343 // Visit all the nodes. We start in topological order, so that we see
4344 // nodes with their original operands intact. Legalization can produce
4345 // new nodes which may themselves need to be legalized. Iterate until all
4346 // nodes have been legalized.
4348 bool AnyLegalized = false;
4349 for (auto NI = allnodes_end(); NI != allnodes_begin();) {
4353 if (N->use_empty() && N != getRoot().getNode()) {
4359 if (LegalizedNodes.insert(N).second) {
4360 AnyLegalized = true;
4361 Legalizer.LegalizeOp(N);
4363 if (N->use_empty() && N != getRoot().getNode()) {
4374 // Remove dead nodes now.
4378 bool SelectionDAG::LegalizeOp(SDNode *N,
4379 SmallSetVector<SDNode *, 16> &UpdatedNodes) {
4380 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4381 SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
4383 // Directly insert the node in question, and legalize it. This will recurse
4384 // as needed through operands.
4385 LegalizedNodes.insert(N);
4386 Legalizer.LegalizeOp(N);
4388 return LegalizedNodes.count(N);