1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Support/MathExtras.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
27 //===----------------------------------------------------------------------===//
28 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
29 /// hacks on it until the target machine can handle it. This involves
30 /// eliminating value sizes the machine cannot handle (promoting small sizes to
31 /// large sizes or splitting up large values into small values) as well as
32 /// eliminating operations the machine cannot handle.
34 /// This code also does a small amount of optimization and recognition of idioms
35 /// as part of its processing. For example, if a target does not support a
36 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
37 /// will attempt merge setcc and brc instructions into brcc's.
40 class SelectionDAGLegalize {
44 /// LegalizeAction - This enum indicates what action we should take for each
45 /// value type the can occur in the program.
47 Legal, // The target natively supports this value type.
48 Promote, // This should be promoted to the next larger type.
49 Expand, // This integer type should be broken into smaller pieces.
52 /// ValueTypeActions - This is a bitvector that contains two bits for each
53 /// value type, where the two bits correspond to the LegalizeAction enum.
54 /// This can be queried with "getTypeAction(VT)".
55 unsigned long long ValueTypeActions;
57 /// NeedsAnotherIteration - This is set when we expand a large integer
58 /// operation into smaller integer operations, but the smaller operations are
59 /// not set. This occurs only rarely in practice, for targets that don't have
60 /// 32-bit or larger integer registers.
61 bool NeedsAnotherIteration;
63 /// LegalizedNodes - For nodes that are of legal width, and that have more
64 /// than one use, this map indicates what regularized operand to use. This
65 /// allows us to avoid legalizing the same thing more than once.
66 std::map<SDOperand, SDOperand> LegalizedNodes;
68 /// PromotedNodes - For nodes that are below legal width, and that have more
69 /// than one use, this map indicates what promoted value to use. This allows
70 /// us to avoid promoting the same thing more than once.
71 std::map<SDOperand, SDOperand> PromotedNodes;
73 /// ExpandedNodes - For nodes that need to be expanded, and which have more
74 /// than one use, this map indicates which which operands are the expanded
75 /// version of the input. This allows us to avoid expanding the same node
77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
79 void AddLegalizedOperand(SDOperand From, SDOperand To) {
80 LegalizedNodes.insert(std::make_pair(From, To));
81 // If someone requests legalization of the new node, return itself.
83 LegalizedNodes.insert(std::make_pair(To, To));
85 void AddPromotedOperand(SDOperand From, SDOperand To) {
86 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
87 assert(isNew && "Got into the map somehow?");
88 // If someone requests legalization of the new node, return itself.
89 LegalizedNodes.insert(std::make_pair(To, To));
94 SelectionDAGLegalize(SelectionDAG &DAG);
96 /// Run - While there is still lowering to do, perform a pass over the DAG.
97 /// Most regularization can be done in a single pass, but targets that require
98 /// large values to be split into registers multiple times (e.g. i64 -> 4x
99 /// i16) require iteration for these values (the first iteration will demote
100 /// to i32, the second will demote to i16).
103 NeedsAnotherIteration = false;
105 } while (NeedsAnotherIteration);
108 /// getTypeAction - Return how we should legalize values of this type, either
109 /// it is already legal or we need to expand it into multiple registers of
110 /// smaller integer type, or we need to promote it to a larger type.
111 LegalizeAction getTypeAction(MVT::ValueType VT) const {
112 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3);
115 /// isTypeLegal - Return true if this type is legal on this target.
117 bool isTypeLegal(MVT::ValueType VT) const {
118 return getTypeAction(VT) == Legal;
124 SDOperand LegalizeOp(SDOperand O);
125 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
126 SDOperand PromoteOp(SDOperand O);
128 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
130 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
133 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
134 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
136 MVT::ValueType DestVT);
137 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
139 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
142 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
143 SDOperand &Lo, SDOperand &Hi);
144 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
145 SDOperand &Lo, SDOperand &Hi);
146 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
147 SDOperand &Lo, SDOperand &Hi);
149 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain);
151 SDOperand getIntPtrConstant(uint64_t Val) {
152 return DAG.getConstant(Val, TLI.getPointerTy());
157 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
159 default: assert(0 && "Don't know how to scalarize this opcode!");
160 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
161 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
162 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
166 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
167 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
168 ValueTypeActions(TLI.getValueTypeActions()) {
169 assert(MVT::LAST_VALUETYPE <= 32 &&
170 "Too many value types for ValueTypeActions to hold!");
173 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
174 /// INT_TO_FP operation of the specified operand when the target requests that
175 /// we expand it. At this point, we know that the result and operand types are
176 /// legal for the target.
177 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
179 MVT::ValueType DestVT) {
180 if (Op0.getValueType() == MVT::i32) {
181 // simple 32-bit [signed|unsigned] integer to float/double expansion
183 // get the stack frame index of a 8 byte buffer
184 MachineFunction &MF = DAG.getMachineFunction();
185 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
186 // get address of 8 byte buffer
187 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
188 // word offset constant for Hi/Lo address computation
189 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
190 // set up Hi and Lo (into buffer) address based on endian
192 if (TLI.isLittleEndian()) {
193 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
197 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
199 // if signed map to unsigned space
202 // constant used to invert sign bit (signed to unsigned mapping)
203 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
204 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
208 // store the lo of the constructed double - based on integer input
209 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
210 Op0Mapped, Lo, DAG.getSrcValue(NULL));
211 // initial hi portion of constructed double
212 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
213 // store the hi of the constructed double - biased exponent
214 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
215 InitialHi, Hi, DAG.getSrcValue(NULL));
216 // load the constructed double
217 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
218 DAG.getSrcValue(NULL));
219 // FP constant to bias correct the final result
220 SDOperand Bias = DAG.getConstantFP(isSigned ?
221 BitsToDouble(0x4330000080000000ULL)
222 : BitsToDouble(0x4330000000000000ULL),
225 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
228 // handle final rounding
229 if (DestVT == MVT::f64) {
233 // if f32 then cast to f32
234 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
236 return LegalizeOp(Result);
238 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
239 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
241 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
242 DAG.getConstant(0, Op0.getValueType()),
244 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
245 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
246 SignSet, Four, Zero);
248 // If the sign bit of the integer is set, the large number will be treated
249 // as a negative number. To counteract this, the dynamic code adds an
250 // offset depending on the data type.
252 switch (Op0.getValueType()) {
253 default: assert(0 && "Unsupported integer type!");
254 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
255 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
256 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
257 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
259 if (TLI.isLittleEndian()) FF <<= 32;
260 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
262 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
263 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
264 SDOperand FudgeInReg;
265 if (DestVT == MVT::f32)
266 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
267 DAG.getSrcValue(NULL));
269 assert(DestVT == MVT::f64 && "Unexpected conversion");
270 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
271 DAG.getEntryNode(), CPIdx,
272 DAG.getSrcValue(NULL), MVT::f32));
275 return LegalizeOp(DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg));
278 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
279 /// *INT_TO_FP operation of the specified operand when the target requests that
280 /// we promote it. At this point, we know that the result and operand types are
281 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
282 /// operation that takes a larger input.
283 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
284 MVT::ValueType DestVT,
286 // First step, figure out the appropriate *INT_TO_FP operation to use.
287 MVT::ValueType NewInTy = LegalOp.getValueType();
289 unsigned OpToUse = 0;
291 // Scan for the appropriate larger type to use.
293 NewInTy = (MVT::ValueType)(NewInTy+1);
294 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
296 // If the target supports SINT_TO_FP of this type, use it.
297 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
299 case TargetLowering::Legal:
300 if (!TLI.isTypeLegal(NewInTy))
301 break; // Can't use this datatype.
303 case TargetLowering::Custom:
304 OpToUse = ISD::SINT_TO_FP;
308 if (isSigned) continue;
310 // If the target supports UINT_TO_FP of this type, use it.
311 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
313 case TargetLowering::Legal:
314 if (!TLI.isTypeLegal(NewInTy))
315 break; // Can't use this datatype.
317 case TargetLowering::Custom:
318 OpToUse = ISD::UINT_TO_FP;
323 // Otherwise, try a larger type.
326 // Okay, we found the operation and type to use. Zero extend our input to the
327 // desired type then run the operation on it.
328 SDOperand N = DAG.getNode(OpToUse, DestVT,
329 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
331 // Make sure to legalize any nodes we create here.
332 return LegalizeOp(N);
335 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
336 /// FP_TO_*INT operation of the specified operand when the target requests that
337 /// we promote it. At this point, we know that the result and operand types are
338 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
339 /// operation that returns a larger result.
340 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
341 MVT::ValueType DestVT,
343 // First step, figure out the appropriate FP_TO*INT operation to use.
344 MVT::ValueType NewOutTy = DestVT;
346 unsigned OpToUse = 0;
348 // Scan for the appropriate larger type to use.
350 NewOutTy = (MVT::ValueType)(NewOutTy+1);
351 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
353 // If the target supports FP_TO_SINT returning this type, use it.
354 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
356 case TargetLowering::Legal:
357 if (!TLI.isTypeLegal(NewOutTy))
358 break; // Can't use this datatype.
360 case TargetLowering::Custom:
361 OpToUse = ISD::FP_TO_SINT;
366 // If the target supports FP_TO_UINT of this type, use it.
367 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
369 case TargetLowering::Legal:
370 if (!TLI.isTypeLegal(NewOutTy))
371 break; // Can't use this datatype.
373 case TargetLowering::Custom:
374 OpToUse = ISD::FP_TO_UINT;
379 // Otherwise, try a larger type.
382 // Okay, we found the operation and type to use. Truncate the result of the
383 // extended FP_TO_*INT operation to the desired size.
384 SDOperand N = DAG.getNode(ISD::TRUNCATE, DestVT,
385 DAG.getNode(OpToUse, NewOutTy, LegalOp));
386 // Make sure to legalize any nodes we create here in the next pass.
387 return LegalizeOp(N);
390 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
391 /// not been visited yet and if all of its operands have already been visited.
392 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
393 std::map<SDNode*, unsigned> &Visited) {
394 if (++Visited[N] != N->getNumOperands())
395 return; // Haven't visited all operands yet
399 if (N->hasOneUse()) { // Tail recurse in common case.
400 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
404 // Now that we have N in, add anything that uses it if all of their operands
406 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
407 ComputeTopDownOrdering(*UI, Order, Visited);
411 void SelectionDAGLegalize::LegalizeDAG() {
412 // The legalize process is inherently a bottom-up recursive process (users
413 // legalize their uses before themselves). Given infinite stack space, we
414 // could just start legalizing on the root and traverse the whole graph. In
415 // practice however, this causes us to run out of stack space on large basic
416 // blocks. To avoid this problem, compute an ordering of the nodes where each
417 // node is only legalized after all of its operands are legalized.
418 std::map<SDNode*, unsigned> Visited;
419 std::vector<SDNode*> Order;
421 // Compute ordering from all of the leaves in the graphs, those (like the
422 // entry node) that have no operands.
423 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
424 E = DAG.allnodes_end(); I != E; ++I) {
425 if (I->getNumOperands() == 0) {
427 ComputeTopDownOrdering(I, Order, Visited);
431 assert(Order.size() == Visited.size() &&
433 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
434 "Error: DAG is cyclic!");
437 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
438 SDNode *N = Order[i];
439 switch (getTypeAction(N->getValueType(0))) {
440 default: assert(0 && "Bad type action!");
442 LegalizeOp(SDOperand(N, 0));
445 PromoteOp(SDOperand(N, 0));
449 ExpandOp(SDOperand(N, 0), X, Y);
455 // Finally, it's possible the root changed. Get the new root.
456 SDOperand OldRoot = DAG.getRoot();
457 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
458 DAG.setRoot(LegalizedNodes[OldRoot]);
460 ExpandedNodes.clear();
461 LegalizedNodes.clear();
462 PromotedNodes.clear();
464 // Remove dead nodes now.
465 DAG.RemoveDeadNodes(OldRoot.Val);
468 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
469 assert(isTypeLegal(Op.getValueType()) &&
470 "Caller should expand or promote operands that are not legal!");
471 SDNode *Node = Op.Val;
473 // If this operation defines any values that cannot be represented in a
474 // register on this target, make sure to expand or promote them.
475 if (Node->getNumValues() > 1) {
476 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
477 switch (getTypeAction(Node->getValueType(i))) {
478 case Legal: break; // Nothing to do.
481 ExpandOp(Op.getValue(i), T1, T2);
482 assert(LegalizedNodes.count(Op) &&
483 "Expansion didn't add legal operands!");
484 return LegalizedNodes[Op];
487 PromoteOp(Op.getValue(i));
488 assert(LegalizedNodes.count(Op) &&
489 "Expansion didn't add legal operands!");
490 return LegalizedNodes[Op];
494 // Note that LegalizeOp may be reentered even from single-use nodes, which
495 // means that we always must cache transformed nodes.
496 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
497 if (I != LegalizedNodes.end()) return I->second;
499 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
501 SDOperand Result = Op;
503 switch (Node->getOpcode()) {
505 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
506 // If this is a target node, legalize it by legalizing the operands then
507 // passing it through.
508 std::vector<SDOperand> Ops;
509 bool Changed = false;
510 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
511 Ops.push_back(LegalizeOp(Node->getOperand(i)));
512 Changed = Changed || Node->getOperand(i) != Ops.back();
515 if (Node->getNumValues() == 1)
516 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops);
518 std::vector<MVT::ValueType> VTs(Node->value_begin(),
520 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
523 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
524 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
525 return Result.getValue(Op.ResNo);
527 // Otherwise this is an unhandled builtin node. splat.
528 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
529 assert(0 && "Do not know how to legalize this operator!");
531 case ISD::EntryToken:
532 case ISD::FrameIndex:
533 case ISD::TargetFrameIndex:
535 case ISD::TargetConstant:
536 case ISD::TargetConstantPool:
537 case ISD::GlobalAddress:
538 case ISD::TargetGlobalAddress:
539 case ISD::ExternalSymbol:
540 case ISD::TargetExternalSymbol:
541 case ISD::ConstantPool: // Nothing to do.
542 case ISD::BasicBlock:
547 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
548 default: assert(0 && "This action is not supported yet!");
549 case TargetLowering::Custom: {
550 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
552 Result = LegalizeOp(Tmp);
555 } // FALLTHROUGH if the target doesn't want to lower this op after all.
556 case TargetLowering::Legal:
557 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!");
561 case ISD::AssertSext:
562 case ISD::AssertZext:
563 Tmp1 = LegalizeOp(Node->getOperand(0));
564 if (Tmp1 != Node->getOperand(0))
565 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
566 Node->getOperand(1));
568 case ISD::MERGE_VALUES:
569 return LegalizeOp(Node->getOperand(Op.ResNo));
570 case ISD::CopyFromReg:
571 Tmp1 = LegalizeOp(Node->getOperand(0));
572 Result = Op.getValue(0);
573 if (Node->getNumValues() == 2) {
574 if (Tmp1 != Node->getOperand(0))
575 Result = DAG.getCopyFromReg(Tmp1,
576 cast<RegisterSDNode>(Node->getOperand(1))->getReg(),
577 Node->getValueType(0));
579 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
580 if (Node->getNumOperands() == 3)
581 Tmp2 = LegalizeOp(Node->getOperand(2));
582 if (Tmp1 != Node->getOperand(0) ||
583 (Node->getNumOperands() == 3 && Tmp2 != Node->getOperand(2)))
584 Result = DAG.getCopyFromReg(Tmp1,
585 cast<RegisterSDNode>(Node->getOperand(1))->getReg(),
586 Node->getValueType(0), Tmp2);
587 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
589 // Since CopyFromReg produces two values, make sure to remember that we
590 // legalized both of them.
591 AddLegalizedOperand(Op.getValue(0), Result);
592 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
593 return Result.getValue(Op.ResNo);
595 MVT::ValueType VT = Op.getValueType();
596 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
597 default: assert(0 && "This action is not supported yet!");
598 case TargetLowering::Expand:
599 case TargetLowering::Promote:
600 if (MVT::isInteger(VT))
601 Result = DAG.getConstant(0, VT);
602 else if (MVT::isFloatingPoint(VT))
603 Result = DAG.getConstantFP(0, VT);
605 assert(0 && "Unknown value type!");
607 case TargetLowering::Legal:
614 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
615 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
617 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
618 case TargetLowering::Promote:
619 default: assert(0 && "This action is not supported yet!");
620 case TargetLowering::Expand: {
621 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
622 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
623 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
625 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
626 const std::string &FName =
627 cast<StringSDNode>(Node->getOperand(3))->getValue();
628 const std::string &DirName =
629 cast<StringSDNode>(Node->getOperand(4))->getValue();
630 unsigned SrcFile = DebugInfo->getUniqueSourceID(FName, DirName);
632 std::vector<SDOperand> Ops;
633 Ops.push_back(Tmp1); // chain
634 SDOperand LineOp = Node->getOperand(1);
635 SDOperand ColOp = Node->getOperand(2);
638 Ops.push_back(LineOp); // line #
639 Ops.push_back(ColOp); // col #
640 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
641 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
643 unsigned Line = dyn_cast<ConstantSDNode>(LineOp)->getValue();
644 unsigned Col = dyn_cast<ConstantSDNode>(ColOp)->getValue();
645 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
646 Ops.push_back(DAG.getConstant(ID, MVT::i32));
647 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops);
650 Result = Tmp1; // chain
652 Result = LegalizeOp(Result); // Relegalize new nodes.
655 case TargetLowering::Legal:
656 if (Tmp1 != Node->getOperand(0) ||
657 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
658 std::vector<SDOperand> Ops;
660 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
661 Ops.push_back(Node->getOperand(1)); // line # must be legal.
662 Ops.push_back(Node->getOperand(2)); // col # must be legal.
664 // Otherwise promote them.
665 Ops.push_back(PromoteOp(Node->getOperand(1)));
666 Ops.push_back(PromoteOp(Node->getOperand(2)));
668 Ops.push_back(Node->getOperand(3)); // filename must be legal.
669 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
670 Result = DAG.getNode(ISD::LOCATION, MVT::Other, Ops);
677 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
678 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
679 case TargetLowering::Promote:
680 case TargetLowering::Expand:
681 default: assert(0 && "This action is not supported yet!");
682 case TargetLowering::Legal:
683 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
684 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
685 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
686 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
688 if (Tmp1 != Node->getOperand(0) ||
689 Tmp2 != Node->getOperand(1) ||
690 Tmp3 != Node->getOperand(2) ||
691 Tmp4 != Node->getOperand(3)) {
692 Result = DAG.getNode(ISD::DEBUG_LOC,MVT::Other, Tmp1, Tmp2, Tmp3, Tmp4);
698 case ISD::DEBUG_LABEL:
699 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
700 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
701 case TargetLowering::Promote:
702 case TargetLowering::Expand:
703 default: assert(0 && "This action is not supported yet!");
704 case TargetLowering::Legal:
705 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
706 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
708 if (Tmp1 != Node->getOperand(0) ||
709 Tmp2 != Node->getOperand(1)) {
710 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Tmp1, Tmp2);
717 // We know we don't need to expand constants here, constants only have one
718 // value and we check that it is fine above.
720 // FIXME: Maybe we should handle things like targets that don't support full
721 // 32-bit immediates?
723 case ISD::ConstantFP: {
724 // Spill FP immediates to the constant pool if the target cannot directly
725 // codegen them. Targets often have some immediate values that can be
726 // efficiently generated into an FP register without a load. We explicitly
727 // leave these constants as ConstantFP nodes for the target to deal with.
729 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
731 // Check to see if this FP immediate is already legal.
732 bool isLegal = false;
733 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
734 E = TLI.legal_fpimm_end(); I != E; ++I)
735 if (CFP->isExactlyValue(*I)) {
741 // Otherwise we need to spill the constant to memory.
744 // If a FP immediate is precise when represented as a float, we put it
745 // into the constant pool as a float, even if it's is statically typed
747 MVT::ValueType VT = CFP->getValueType(0);
748 bool isDouble = VT == MVT::f64;
749 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
750 Type::FloatTy, CFP->getValue());
751 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
752 // Only do this if the target has a native EXTLOAD instruction from
754 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
755 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
761 LegalizeOp(DAG.getConstantPool(LLVMC, TLI.getPointerTy()));
763 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
764 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
766 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
767 DAG.getSrcValue(NULL));
772 case ISD::ConstantVec: {
773 // We assume that vector constants are not legal, and will be immediately
774 // spilled to the constant pool.
776 // FIXME: revisit this when we have some kind of mechanism by which targets
777 // can decided legality of vector constants, of which there may be very
780 // Create a ConstantPacked, and put it in the constant pool.
781 std::vector<Constant*> CV;
782 MVT::ValueType VT = Node->getValueType(0);
783 for (unsigned I = 0, E = Node->getNumOperands(); I < E; ++I) {
784 SDOperand OpN = Node->getOperand(I);
785 const Type* OpNTy = MVT::getTypeForValueType(OpN.getValueType());
786 if (MVT::isFloatingPoint(VT))
787 CV.push_back(ConstantFP::get(OpNTy,
788 cast<ConstantFPSDNode>(OpN)->getValue()));
790 CV.push_back(ConstantUInt::get(OpNTy,
791 cast<ConstantSDNode>(OpN)->getValue()));
793 Constant *CP = ConstantPacked::get(CV);
794 SDOperand CPIdx = LegalizeOp(DAG.getConstantPool(CP, TLI.getPointerTy()));
795 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
798 case ISD::TokenFactor:
799 if (Node->getNumOperands() == 2) {
800 bool Changed = false;
801 SDOperand Op0 = LegalizeOp(Node->getOperand(0));
802 SDOperand Op1 = LegalizeOp(Node->getOperand(1));
803 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1))
804 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
806 std::vector<SDOperand> Ops;
807 bool Changed = false;
808 // Legalize the operands.
809 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
810 SDOperand Op = Node->getOperand(i);
811 Ops.push_back(LegalizeOp(Op));
812 Changed |= Ops[i] != Op;
815 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
819 case ISD::CALLSEQ_START:
820 case ISD::CALLSEQ_END:
821 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
822 // Do not try to legalize the target-specific arguments (#1+)
823 Tmp2 = Node->getOperand(0);
825 Node->setAdjCallChain(Tmp1);
827 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These
828 // nodes are treated specially and are mutated in place. This makes the dag
829 // legalization process more efficient and also makes libcall insertion
832 case ISD::DYNAMIC_STACKALLOC:
833 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
834 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
835 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
836 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
837 Tmp3 != Node->getOperand(2)) {
838 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
839 std::vector<SDOperand> Ops;
840 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
841 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
843 Result = Op.getValue(0);
845 // Since this op produces two values, make sure to remember that we
846 // legalized both of them.
847 AddLegalizedOperand(SDOperand(Node, 0), Result);
848 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
849 return Result.getValue(Op.ResNo);
853 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
854 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
856 bool Changed = false;
857 std::vector<SDOperand> Ops;
858 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
859 Ops.push_back(LegalizeOp(Node->getOperand(i)));
860 Changed |= Ops.back() != Node->getOperand(i);
863 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) {
864 std::vector<MVT::ValueType> RetTyVTs;
865 RetTyVTs.reserve(Node->getNumValues());
866 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
867 RetTyVTs.push_back(Node->getValueType(i));
868 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
869 Node->getOpcode() == ISD::TAILCALL), 0);
871 Result = Result.getValue(0);
873 // Since calls produce multiple values, make sure to remember that we
874 // legalized all of them.
875 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
876 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
877 return Result.getValue(Op.ResNo);
880 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
881 if (Tmp1 != Node->getOperand(0))
882 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1));
886 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
888 switch (getTypeAction(Node->getOperand(1).getValueType())) {
889 case Expand: assert(0 && "It's impossible to expand bools");
891 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
894 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
898 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
899 default: assert(0 && "This action is not supported yet!");
900 case TargetLowering::Expand:
901 // Expand brcond's setcc into its constituent parts and create a BR_CC
903 if (Tmp2.getOpcode() == ISD::SETCC) {
904 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
905 Tmp2.getOperand(0), Tmp2.getOperand(1),
906 Node->getOperand(2));
908 // Make sure the condition is either zero or one. It may have been
909 // promoted from something else.
910 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
912 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
913 DAG.getCondCode(ISD::SETNE), Tmp2,
914 DAG.getConstant(0, Tmp2.getValueType()),
915 Node->getOperand(2));
917 Result = LegalizeOp(Result); // Relegalize new nodes.
919 case TargetLowering::Custom: {
921 TLI.LowerOperation(DAG.getNode(ISD::BRCOND, Node->getValueType(0),
922 Tmp1, Tmp2, Node->getOperand(2)), DAG);
924 Result = LegalizeOp(Tmp);
927 // FALLTHROUGH if the target thinks it is legal.
929 case TargetLowering::Legal:
930 // Basic block destination (Op#2) is always legal.
931 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
932 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
933 Node->getOperand(2));
938 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
939 if (!isTypeLegal(Node->getOperand(2).getValueType())) {
940 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
941 Node->getOperand(2), // LHS
942 Node->getOperand(3), // RHS
943 Node->getOperand(1)));
944 // If we get a SETCC back from legalizing the SETCC node we just
945 // created, then use its LHS, RHS, and CC directly in creating a new
946 // node. Otherwise, select between the true and false value based on
947 // comparing the result of the legalized with zero.
948 if (Tmp2.getOpcode() == ISD::SETCC) {
949 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
950 Tmp2.getOperand(0), Tmp2.getOperand(1),
951 Node->getOperand(4));
953 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
954 DAG.getCondCode(ISD::SETNE),
955 Tmp2, DAG.getConstant(0, Tmp2.getValueType()),
956 Node->getOperand(4));
961 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
962 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
964 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
965 default: assert(0 && "Unexpected action for BR_CC!");
966 case TargetLowering::Custom: {
967 Tmp4 = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1),
968 Tmp2, Tmp3, Node->getOperand(4));
969 Tmp4 = TLI.LowerOperation(Tmp4, DAG);
971 Result = LegalizeOp(Tmp4);
974 } // FALLTHROUGH if the target doesn't want to lower this op after all.
975 case TargetLowering::Legal:
976 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
977 Tmp3 != Node->getOperand(3)) {
978 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1),
979 Tmp2, Tmp3, Node->getOperand(4));
984 case ISD::BRCONDTWOWAY:
985 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
986 switch (getTypeAction(Node->getOperand(1).getValueType())) {
987 case Expand: assert(0 && "It's impossible to expand bools");
989 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
992 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
995 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR
997 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) {
998 case TargetLowering::Promote:
999 default: assert(0 && "This action is not supported yet!");
1000 case TargetLowering::Legal:
1001 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1002 std::vector<SDOperand> Ops;
1003 Ops.push_back(Tmp1);
1004 Ops.push_back(Tmp2);
1005 Ops.push_back(Node->getOperand(2));
1006 Ops.push_back(Node->getOperand(3));
1007 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops);
1010 case TargetLowering::Expand:
1011 // If BRTWOWAY_CC is legal for this target, then simply expand this node
1012 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a
1014 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
1015 if (Tmp2.getOpcode() == ISD::SETCC) {
1016 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
1017 Tmp2.getOperand(0), Tmp2.getOperand(1),
1018 Node->getOperand(2), Node->getOperand(3));
1020 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
1021 DAG.getConstant(0, Tmp2.getValueType()),
1022 Node->getOperand(2), Node->getOperand(3));
1025 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
1026 Node->getOperand(2));
1027 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3));
1029 Result = LegalizeOp(Result); // Relegalize new nodes.
1033 case ISD::BRTWOWAY_CC:
1034 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1035 if (isTypeLegal(Node->getOperand(2).getValueType())) {
1036 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
1037 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
1038 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
1039 Tmp3 != Node->getOperand(3)) {
1040 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3,
1041 Node->getOperand(4), Node->getOperand(5));
1045 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
1046 Node->getOperand(2), // LHS
1047 Node->getOperand(3), // RHS
1048 Node->getOperand(1)));
1049 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR
1051 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) {
1052 default: assert(0 && "This action is not supported yet!");
1053 case TargetLowering::Legal:
1054 // If we get a SETCC back from legalizing the SETCC node we just
1055 // created, then use its LHS, RHS, and CC directly in creating a new
1056 // node. Otherwise, select between the true and false value based on
1057 // comparing the result of the legalized with zero.
1058 if (Tmp2.getOpcode() == ISD::SETCC) {
1059 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
1060 Tmp2.getOperand(0), Tmp2.getOperand(1),
1061 Node->getOperand(4), Node->getOperand(5));
1063 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
1064 DAG.getConstant(0, Tmp2.getValueType()),
1065 Node->getOperand(4), Node->getOperand(5));
1068 case TargetLowering::Expand:
1069 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
1070 Node->getOperand(4));
1071 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5));
1074 Result = LegalizeOp(Result); // Relegalize new nodes.
1078 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1079 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1081 MVT::ValueType VT = Node->getValueType(0);
1082 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1083 default: assert(0 && "This action is not supported yet!");
1084 case TargetLowering::Custom: {
1085 SDOperand Op = DAG.getLoad(Node->getValueType(0),
1086 Tmp1, Tmp2, Node->getOperand(2));
1087 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
1089 Result = LegalizeOp(Tmp);
1090 // Since loads produce two values, make sure to remember that we legalized
1092 AddLegalizedOperand(SDOperand(Node, 0), Result);
1093 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1094 return Result.getValue(Op.ResNo);
1096 // FALLTHROUGH if the target thinks it is legal.
1098 case TargetLowering::Legal:
1099 if (Tmp1 != Node->getOperand(0) ||
1100 Tmp2 != Node->getOperand(1))
1101 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2,
1102 Node->getOperand(2));
1104 Result = SDOperand(Node, 0);
1106 // Since loads produce two values, make sure to remember that we legalized
1108 AddLegalizedOperand(SDOperand(Node, 0), Result);
1109 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1110 return Result.getValue(Op.ResNo);
1112 assert(0 && "Unreachable");
1116 case ISD::ZEXTLOAD: {
1117 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1118 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1120 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
1121 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
1122 default: assert(0 && "This action is not supported yet!");
1123 case TargetLowering::Promote:
1124 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
1125 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
1126 Tmp1, Tmp2, Node->getOperand(2), MVT::i8);
1127 // Since loads produce two values, make sure to remember that we legalized
1129 AddLegalizedOperand(SDOperand(Node, 0), Result);
1130 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1131 return Result.getValue(Op.ResNo);
1133 case TargetLowering::Custom: {
1134 SDOperand Op = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
1135 Tmp1, Tmp2, Node->getOperand(2),
1137 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
1139 Result = LegalizeOp(Tmp);
1140 // Since loads produce two values, make sure to remember that we legalized
1142 AddLegalizedOperand(SDOperand(Node, 0), Result);
1143 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1144 return Result.getValue(Op.ResNo);
1146 // FALLTHROUGH if the target thinks it is legal.
1148 case TargetLowering::Legal:
1149 if (Tmp1 != Node->getOperand(0) ||
1150 Tmp2 != Node->getOperand(1))
1151 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
1152 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1154 Result = SDOperand(Node, 0);
1156 // Since loads produce two values, make sure to remember that we legalized
1158 AddLegalizedOperand(SDOperand(Node, 0), Result);
1159 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1160 return Result.getValue(Op.ResNo);
1161 case TargetLowering::Expand:
1162 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1163 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1164 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
1165 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1166 Result = LegalizeOp(Result); // Relegalize new nodes.
1167 Load = LegalizeOp(Load);
1168 AddLegalizedOperand(SDOperand(Node, 0), Result);
1169 AddLegalizedOperand(SDOperand(Node, 1), Load.getValue(1));
1171 return Load.getValue(1);
1174 assert(Node->getOpcode() != ISD::EXTLOAD &&
1175 "EXTLOAD should always be supported!");
1176 // Turn the unsupported load into an EXTLOAD followed by an explicit
1177 // zero/sign extend inreg.
1178 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1179 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1181 if (Node->getOpcode() == ISD::SEXTLOAD)
1182 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1183 Result, DAG.getValueType(SrcVT));
1185 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1186 Result = LegalizeOp(Result); // Relegalize new nodes.
1187 ValRes = LegalizeOp(ValRes); // Relegalize new nodes.
1188 AddLegalizedOperand(SDOperand(Node, 0), ValRes);
1189 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1191 return Result.getValue(1);
1194 assert(0 && "Unreachable");
1196 case ISD::EXTRACT_ELEMENT: {
1197 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1198 switch (getTypeAction(OpTy)) {
1200 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1203 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1205 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1206 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1207 TLI.getShiftAmountTy()));
1208 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1211 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1212 Node->getOperand(0));
1214 Result = LegalizeOp(Result);
1217 // Get both the low and high parts.
1218 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1219 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1220 Result = Tmp2; // 1 -> Hi
1222 Result = Tmp1; // 0 -> Lo
1228 case ISD::CopyToReg:
1229 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1231 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1232 "Register type must be legal!");
1233 // Legalize the incoming value (must be a legal type).
1234 Tmp2 = LegalizeOp(Node->getOperand(2));
1235 if (Node->getNumValues() == 1) {
1236 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2))
1237 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1,
1238 Node->getOperand(1), Tmp2);
1240 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1241 if (Node->getNumOperands() == 4)
1242 Tmp3 = LegalizeOp(Node->getOperand(3));
1243 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
1244 (Node->getNumOperands() == 4 && Tmp3 != Node->getOperand(3))) {
1245 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1246 Result = DAG.getCopyToReg(Tmp1, Reg, Tmp2, Tmp3);
1249 // Since this produces two values, make sure to remember that we legalized
1251 AddLegalizedOperand(SDOperand(Node, 0), Result);
1252 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1253 return Result.getValue(Op.ResNo);
1258 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1259 switch (Node->getNumOperands()) {
1261 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1263 Tmp2 = LegalizeOp(Node->getOperand(1));
1264 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1265 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
1269 ExpandOp(Node->getOperand(1), Lo, Hi);
1270 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
1274 Tmp2 = PromoteOp(Node->getOperand(1));
1275 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
1280 if (Tmp1 != Node->getOperand(0))
1281 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1);
1283 default: { // ret <values>
1284 std::vector<SDOperand> NewValues;
1285 NewValues.push_back(Tmp1);
1286 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1287 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1289 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1293 ExpandOp(Node->getOperand(i), Lo, Hi);
1294 NewValues.push_back(Lo);
1295 NewValues.push_back(Hi);
1299 assert(0 && "Can't promote multiple return value yet!");
1301 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
1306 switch (TLI.getOperationAction(Node->getOpcode(),
1307 Node->getValueType(0))) {
1308 default: assert(0 && "This action is not supported yet!");
1309 case TargetLowering::Custom: {
1310 SDOperand Tmp = TLI.LowerOperation(Result, DAG);
1312 Result = LegalizeOp(Tmp);
1315 // FALLTHROUGH if the target thinks it is legal.
1317 case TargetLowering::Legal:
1323 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1324 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1326 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1327 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1328 if (CFP->getValueType(0) == MVT::f32) {
1329 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
1330 DAG.getConstant(FloatToBits(CFP->getValue()),
1333 Node->getOperand(3));
1335 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1336 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
1337 DAG.getConstant(DoubleToBits(CFP->getValue()),
1340 Node->getOperand(3));
1345 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1347 SDOperand Val = LegalizeOp(Node->getOperand(1));
1348 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) ||
1349 Tmp2 != Node->getOperand(2))
1350 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2,
1351 Node->getOperand(3));
1353 MVT::ValueType VT = Result.Val->getOperand(1).getValueType();
1354 switch (TLI.getOperationAction(Result.Val->getOpcode(), VT)) {
1355 default: assert(0 && "This action is not supported yet!");
1356 case TargetLowering::Custom: {
1357 SDOperand Tmp = TLI.LowerOperation(Result, DAG);
1359 Result = LegalizeOp(Tmp);
1362 // FALLTHROUGH if the target thinks it is legal.
1364 case TargetLowering::Legal:
1371 // Truncate the value and store the result.
1372 Tmp3 = PromoteOp(Node->getOperand(1));
1373 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1374 Node->getOperand(3),
1375 DAG.getValueType(Node->getOperand(1).getValueType()));
1380 unsigned IncrementSize;
1381 ExpandOp(Node->getOperand(1), Lo, Hi);
1383 if (!TLI.isLittleEndian())
1386 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1387 Node->getOperand(3));
1388 // If this is a vector type, then we have to calculate the increment as
1389 // the product of the element size in bytes, and the number of elements
1390 // in the high half of the vector.
1391 if (MVT::Vector == Hi.getValueType()) {
1392 unsigned NumElems = cast<ConstantSDNode>(Hi.getOperand(2))->getValue();
1393 MVT::ValueType EVT = cast<VTSDNode>(Hi.getOperand(3))->getVT();
1394 IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8;
1396 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1398 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1399 getIntPtrConstant(IncrementSize));
1400 assert(isTypeLegal(Tmp2.getValueType()) &&
1401 "Pointers must be legal!");
1402 //Again, claiming both parts of the store came form the same Instr
1403 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1404 Node->getOperand(3));
1405 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1411 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1412 if (Tmp1 != Node->getOperand(0))
1413 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1));
1415 case ISD::READCYCLECOUNTER:
1416 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1417 if (Tmp1 != Node->getOperand(0)) {
1418 std::vector<MVT::ValueType> rtypes;
1419 std::vector<SDOperand> rvals;
1420 rtypes.push_back(MVT::i64);
1421 rtypes.push_back(MVT::Other);
1422 rvals.push_back(Tmp1);
1423 Result = DAG.getNode(ISD::READCYCLECOUNTER, rtypes, rvals);
1426 // Since rdcc produce two values, make sure to remember that we legalized
1428 AddLegalizedOperand(SDOperand(Node, 0), Result);
1429 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1430 return Result.getValue(Op.ResNo);
1432 case ISD::TRUNCSTORE: {
1433 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1434 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1436 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1439 assert(0 && "Cannot handle illegal TRUNCSTORE yet!");
1441 Tmp2 = LegalizeOp(Node->getOperand(1));
1443 // The only promote case we handle is TRUNCSTORE:i1 X into
1444 // -> TRUNCSTORE:i8 (and X, 1)
1445 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1446 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1447 TargetLowering::Promote) {
1448 // Promote the bool to a mask then store.
1449 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1450 DAG.getConstant(1, Tmp2.getValueType()));
1451 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1452 Node->getOperand(3), DAG.getValueType(MVT::i8));
1454 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1455 Tmp3 != Node->getOperand(2)) {
1456 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1457 Node->getOperand(3), Node->getOperand(4));
1460 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT();
1461 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) {
1462 default: assert(0 && "This action is not supported yet!");
1463 case TargetLowering::Custom: {
1464 SDOperand Tmp = TLI.LowerOperation(Result, DAG);
1466 Result = LegalizeOp(Tmp);
1469 // FALLTHROUGH if the target thinks it is legal.
1471 case TargetLowering::Legal:
1480 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1481 case Expand: assert(0 && "It's impossible to expand bools");
1483 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1486 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1489 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1490 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1492 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1493 default: assert(0 && "This action is not supported yet!");
1494 case TargetLowering::Expand:
1495 if (Tmp1.getOpcode() == ISD::SETCC) {
1496 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1498 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1500 // Make sure the condition is either zero or one. It may have been
1501 // promoted from something else.
1502 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1503 Result = DAG.getSelectCC(Tmp1,
1504 DAG.getConstant(0, Tmp1.getValueType()),
1505 Tmp2, Tmp3, ISD::SETNE);
1507 Result = LegalizeOp(Result); // Relegalize new nodes.
1509 case TargetLowering::Custom: {
1511 TLI.LowerOperation(DAG.getNode(ISD::SELECT, Node->getValueType(0),
1512 Tmp1, Tmp2, Tmp3), DAG);
1514 Result = LegalizeOp(Tmp);
1517 // FALLTHROUGH if the target thinks it is legal.
1519 case TargetLowering::Legal:
1520 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1521 Tmp3 != Node->getOperand(2))
1522 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0),
1525 case TargetLowering::Promote: {
1526 MVT::ValueType NVT =
1527 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1528 unsigned ExtOp, TruncOp;
1529 if (MVT::isInteger(Tmp2.getValueType())) {
1530 ExtOp = ISD::ANY_EXTEND;
1531 TruncOp = ISD::TRUNCATE;
1533 ExtOp = ISD::FP_EXTEND;
1534 TruncOp = ISD::FP_ROUND;
1536 // Promote each of the values to the new type.
1537 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1538 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1539 // Perform the larger operation, then round down.
1540 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1541 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1546 case ISD::SELECT_CC:
1547 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1548 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1550 if (isTypeLegal(Node->getOperand(0).getValueType())) {
1551 // Everything is legal, see if we should expand this op or something.
1552 switch (TLI.getOperationAction(ISD::SELECT_CC,
1553 Node->getOperand(0).getValueType())) {
1554 default: assert(0 && "This action is not supported yet!");
1555 case TargetLowering::Custom: {
1557 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0),
1558 Node->getOperand(0),
1559 Node->getOperand(1), Tmp3, Tmp4,
1560 Node->getOperand(4)), DAG);
1562 Result = LegalizeOp(Tmp);
1565 } // FALLTHROUGH if the target can't lower this operation after all.
1566 case TargetLowering::Legal:
1567 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1568 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1569 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1570 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) {
1571 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1,Tmp2,
1572 Tmp3, Tmp4, Node->getOperand(4));
1578 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
1579 Node->getOperand(0), // LHS
1580 Node->getOperand(1), // RHS
1581 Node->getOperand(4)));
1582 // If we get a SETCC back from legalizing the SETCC node we just
1583 // created, then use its LHS, RHS, and CC directly in creating a new
1584 // node. Otherwise, select between the true and false value based on
1585 // comparing the result of the legalized with zero.
1586 if (Tmp1.getOpcode() == ISD::SETCC) {
1587 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(),
1588 Tmp1.getOperand(0), Tmp1.getOperand(1),
1589 Tmp3, Tmp4, Tmp1.getOperand(2));
1591 Result = DAG.getSelectCC(Tmp1,
1592 DAG.getConstant(0, Tmp1.getValueType()),
1593 Tmp3, Tmp4, ISD::SETNE);
1598 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1600 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1601 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1604 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS
1605 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS
1607 // If this is an FP compare, the operands have already been extended.
1608 if (MVT::isInteger(Node->getOperand(0).getValueType())) {
1609 MVT::ValueType VT = Node->getOperand(0).getValueType();
1610 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
1612 // Otherwise, we have to insert explicit sign or zero extends. Note
1613 // that we could insert sign extends for ALL conditions, but zero extend
1614 // is cheaper on many machines (an AND instead of two shifts), so prefer
1616 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1617 default: assert(0 && "Unknown integer comparison!");
1624 // ALL of these operations will work if we either sign or zero extend
1625 // the operands (including the unsigned comparisons!). Zero extend is
1626 // usually a simpler/cheaper operation, so prefer it.
1627 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
1628 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
1634 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
1635 DAG.getValueType(VT));
1636 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
1637 DAG.getValueType(VT));
1643 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
1644 ExpandOp(Node->getOperand(0), LHSLo, LHSHi);
1645 ExpandOp(Node->getOperand(1), RHSLo, RHSHi);
1646 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1650 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
1651 if (RHSCST->isAllOnesValue()) {
1652 // Comparison to -1.
1653 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1658 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1659 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1660 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
1661 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1664 // If this is a comparison of the sign bit, just look at the top part.
1666 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
1667 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT &&
1668 CST->getValue() == 0) || // X < 0
1669 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT &&
1670 (CST->isAllOnesValue()))) { // X > -1
1676 // FIXME: This generated code sucks.
1677 ISD::CondCode LowCC;
1678 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1679 default: assert(0 && "Unknown integer setcc!");
1681 case ISD::SETULT: LowCC = ISD::SETULT; break;
1683 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1685 case ISD::SETULE: LowCC = ISD::SETULE; break;
1687 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1690 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1691 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1692 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1694 // NOTE: on targets without efficient SELECT of bools, we can always use
1695 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1696 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC);
1697 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi,
1698 Node->getOperand(2));
1699 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ);
1700 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1701 Result, Tmp1, Tmp2));
1702 AddLegalizedOperand(SDOperand(Node, 0), Result);
1707 switch(TLI.getOperationAction(ISD::SETCC,
1708 Node->getOperand(0).getValueType())) {
1710 assert(0 && "Cannot handle this action for SETCC yet!");
1712 case TargetLowering::Promote: {
1713 // First step, figure out the appropriate operation to use.
1714 // Allow SETCC to not be supported for all legal data types
1715 // Mostly this targets FP
1716 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1717 MVT::ValueType OldVT = NewInTy;
1719 // Scan for the appropriate larger type to use.
1721 NewInTy = (MVT::ValueType)(NewInTy+1);
1723 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1724 "Fell off of the edge of the integer world");
1725 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1726 "Fell off of the edge of the floating point world");
1728 // If the target supports SETCC of this type, use it.
1729 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
1732 if (MVT::isInteger(NewInTy))
1733 assert(0 && "Cannot promote Legal Integer SETCC yet");
1735 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1736 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
1739 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1740 Node->getOperand(2));
1743 case TargetLowering::Custom: {
1745 TLI.LowerOperation(DAG.getNode(ISD::SETCC, Node->getValueType(0),
1746 Tmp1, Tmp2, Node->getOperand(2)), DAG);
1748 Result = LegalizeOp(Tmp);
1751 // FALLTHROUGH if the target thinks it is legal.
1753 case TargetLowering::Legal:
1754 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1755 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1756 Node->getOperand(2));
1758 case TargetLowering::Expand:
1759 // Expand a setcc node into a select_cc of the same condition, lhs, and
1760 // rhs that selects between const 1 (true) and const 0 (false).
1761 MVT::ValueType VT = Node->getValueType(0);
1762 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1763 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1764 Node->getOperand(2));
1765 Result = LegalizeOp(Result);
1772 case ISD::MEMMOVE: {
1773 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1774 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1776 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1777 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1778 case Expand: assert(0 && "Cannot expand a byte!");
1780 Tmp3 = LegalizeOp(Node->getOperand(2));
1783 Tmp3 = PromoteOp(Node->getOperand(2));
1787 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1791 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1793 // Length is too big, just take the lo-part of the length.
1795 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
1799 Tmp4 = LegalizeOp(Node->getOperand(3));
1802 Tmp4 = PromoteOp(Node->getOperand(3));
1807 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
1808 case Expand: assert(0 && "Cannot expand this yet!");
1810 Tmp5 = LegalizeOp(Node->getOperand(4));
1813 Tmp5 = PromoteOp(Node->getOperand(4));
1817 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1818 default: assert(0 && "This action not implemented for this operation!");
1819 case TargetLowering::Custom: {
1821 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1,
1822 Tmp2, Tmp3, Tmp4, Tmp5), DAG);
1824 Result = LegalizeOp(Tmp);
1827 // FALLTHROUGH if the target thinks it is legal.
1829 case TargetLowering::Legal:
1830 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1831 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) ||
1832 Tmp5 != Node->getOperand(4)) {
1833 std::vector<SDOperand> Ops;
1834 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
1835 Ops.push_back(Tmp4); Ops.push_back(Tmp5);
1836 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops);
1839 case TargetLowering::Expand: {
1840 // Otherwise, the target does not support this operation. Lower the
1841 // operation to an explicit libcall as appropriate.
1842 MVT::ValueType IntPtr = TLI.getPointerTy();
1843 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType();
1844 std::vector<std::pair<SDOperand, const Type*> > Args;
1846 const char *FnName = 0;
1847 if (Node->getOpcode() == ISD::MEMSET) {
1848 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1849 // Extend the ubyte argument to be an int value for the call.
1850 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
1851 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
1852 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1855 } else if (Node->getOpcode() == ISD::MEMCPY ||
1856 Node->getOpcode() == ISD::MEMMOVE) {
1857 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1858 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
1859 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1860 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
1862 assert(0 && "Unknown op!");
1865 std::pair<SDOperand,SDOperand> CallResult =
1866 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
1867 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
1868 Result = LegalizeOp(CallResult.second);
1876 Tmp1 = LegalizeOp(Node->getOperand(0));
1877 Tmp2 = LegalizeOp(Node->getOperand(1));
1879 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1880 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1881 std::vector<SDOperand> Ops;
1882 Ops.push_back(Tmp1);
1883 Ops.push_back(Tmp2);
1884 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1886 Result = SDOperand(Node, 0);
1887 // Since these produce two values, make sure to remember that we legalized
1889 AddLegalizedOperand(SDOperand(Node, 0), Result);
1890 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1891 return Result.getValue(Op.ResNo);
1892 case ISD::WRITEPORT:
1893 Tmp1 = LegalizeOp(Node->getOperand(0));
1894 Tmp2 = LegalizeOp(Node->getOperand(1));
1895 Tmp3 = LegalizeOp(Node->getOperand(2));
1896 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1897 Tmp3 != Node->getOperand(2))
1898 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1902 Tmp1 = LegalizeOp(Node->getOperand(0));
1903 Tmp2 = LegalizeOp(Node->getOperand(1));
1905 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1906 case TargetLowering::Custom:
1907 default: assert(0 && "This action not implemented for this operation!");
1908 case TargetLowering::Legal:
1909 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1910 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1911 std::vector<SDOperand> Ops;
1912 Ops.push_back(Tmp1);
1913 Ops.push_back(Tmp2);
1914 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1916 Result = SDOperand(Node, 0);
1918 case TargetLowering::Expand:
1919 // Replace this with a load from memory.
1920 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0),
1921 Node->getOperand(1), DAG.getSrcValue(NULL));
1922 Result = LegalizeOp(Result);
1926 // Since these produce two values, make sure to remember that we legalized
1928 AddLegalizedOperand(SDOperand(Node, 0), Result);
1929 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1930 return Result.getValue(Op.ResNo);
1933 Tmp1 = LegalizeOp(Node->getOperand(0));
1934 Tmp2 = LegalizeOp(Node->getOperand(1));
1935 Tmp3 = LegalizeOp(Node->getOperand(2));
1937 switch (TLI.getOperationAction(Node->getOpcode(),
1938 Node->getOperand(1).getValueType())) {
1939 case TargetLowering::Custom:
1940 default: assert(0 && "This action not implemented for this operation!");
1941 case TargetLowering::Legal:
1942 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1943 Tmp3 != Node->getOperand(2))
1944 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1946 case TargetLowering::Expand:
1947 // Replace this with a store to memory.
1948 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0),
1949 Node->getOperand(1), Node->getOperand(2),
1950 DAG.getSrcValue(NULL));
1951 Result = LegalizeOp(Result);
1956 case ISD::ADD_PARTS:
1957 case ISD::SUB_PARTS:
1958 case ISD::SHL_PARTS:
1959 case ISD::SRA_PARTS:
1960 case ISD::SRL_PARTS: {
1961 std::vector<SDOperand> Ops;
1962 bool Changed = false;
1963 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1964 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1965 Changed |= Ops.back() != Node->getOperand(i);
1968 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1969 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
1972 switch (TLI.getOperationAction(Node->getOpcode(),
1973 Node->getValueType(0))) {
1974 default: assert(0 && "This action is not supported yet!");
1975 case TargetLowering::Custom: {
1976 SDOperand Tmp = TLI.LowerOperation(Result, DAG);
1978 SDOperand Tmp2, RetVal(0,0);
1979 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1980 Tmp2 = LegalizeOp(Tmp.getValue(i));
1981 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
1985 assert(RetVal.Val && "Illegal result number");
1988 // FALLTHROUGH if the target thinks it is legal.
1990 case TargetLowering::Legal:
1995 // Since these produce multiple values, make sure to remember that we
1996 // legalized all of them.
1997 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1998 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
1999 return Result.getValue(Op.ResNo);
2020 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2021 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2022 case Expand: assert(0 && "Not possible");
2024 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2027 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2030 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2031 case TargetLowering::Custom: {
2032 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2);
2033 SDOperand Tmp = TLI.LowerOperation(Result, DAG);
2035 Tmp = LegalizeOp(Tmp); // Relegalize input.
2036 AddLegalizedOperand(Op, Tmp);
2038 } //else it was considered legal and we fall through
2040 case TargetLowering::Legal:
2041 if (Tmp1 != Node->getOperand(0) ||
2042 Tmp2 != Node->getOperand(1))
2043 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
2046 assert(0 && "Operation not supported");
2050 case ISD::BUILD_PAIR: {
2051 MVT::ValueType PairTy = Node->getValueType(0);
2052 // TODO: handle the case where the Lo and Hi operands are not of legal type
2053 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2054 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2055 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2056 case TargetLowering::Legal:
2057 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2058 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2060 case TargetLowering::Promote:
2061 case TargetLowering::Custom:
2062 assert(0 && "Cannot promote/custom this yet!");
2063 case TargetLowering::Expand:
2064 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2065 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2066 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2067 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2068 TLI.getShiftAmountTy()));
2069 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2));
2078 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2079 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2080 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2081 case TargetLowering::Custom: {
2082 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2);
2083 SDOperand Tmp = TLI.LowerOperation(Result, DAG);
2085 Tmp = LegalizeOp(Tmp); // Relegalize input.
2086 AddLegalizedOperand(Op, Tmp);
2088 } //else it was considered legal and we fall through
2090 case TargetLowering::Legal:
2091 if (Tmp1 != Node->getOperand(0) ||
2092 Tmp2 != Node->getOperand(1))
2093 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
2096 case TargetLowering::Promote:
2097 assert(0 && "Cannot promote handle this yet!");
2098 case TargetLowering::Expand:
2099 if (MVT::isInteger(Node->getValueType(0))) {
2100 MVT::ValueType VT = Node->getValueType(0);
2101 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2102 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
2103 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2104 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2106 // Floating point mod -> fmod libcall.
2107 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
2109 Result = ExpandLibCall(FnName, Node, Dummy);
2118 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2119 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2120 case TargetLowering::Legal:
2121 if (Tmp1 != Node->getOperand(0))
2122 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2124 case TargetLowering::Promote: {
2125 MVT::ValueType OVT = Tmp1.getValueType();
2126 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2128 // Zero extend the argument.
2129 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2130 // Perform the larger operation, then subtract if needed.
2131 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2132 switch(Node->getOpcode())
2138 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2139 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2140 DAG.getConstant(getSizeInBits(NVT), NVT),
2142 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2143 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2146 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2147 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2148 DAG.getConstant(getSizeInBits(NVT) -
2149 getSizeInBits(OVT), NVT));
2154 case TargetLowering::Custom:
2155 assert(0 && "Cannot custom handle this yet!");
2156 case TargetLowering::Expand:
2157 switch(Node->getOpcode())
2160 static const uint64_t mask[6] = {
2161 0x5555555555555555ULL, 0x3333333333333333ULL,
2162 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
2163 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
2165 MVT::ValueType VT = Tmp1.getValueType();
2166 MVT::ValueType ShVT = TLI.getShiftAmountTy();
2167 unsigned len = getSizeInBits(VT);
2168 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2169 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
2170 Tmp2 = DAG.getConstant(mask[i], VT);
2171 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2172 Tmp1 = DAG.getNode(ISD::ADD, VT,
2173 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2),
2174 DAG.getNode(ISD::AND, VT,
2175 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3),
2182 /* for now, we do this:
2187 x = x | (x >>32); // for 64-bit input
2188 return popcount(~x);
2190 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */
2191 MVT::ValueType VT = Tmp1.getValueType();
2192 MVT::ValueType ShVT = TLI.getShiftAmountTy();
2193 unsigned len = getSizeInBits(VT);
2194 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2195 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2196 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1,
2197 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3));
2199 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT));
2200 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
2204 // for now, we use: { return popcount(~x & (x - 1)); }
2205 // unless the target has ctlz but not ctpop, in which case we use:
2206 // { return 32 - nlz(~x & (x-1)); }
2207 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2208 MVT::ValueType VT = Tmp1.getValueType();
2209 Tmp2 = DAG.getConstant(~0ULL, VT);
2210 Tmp3 = DAG.getNode(ISD::AND, VT,
2211 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2),
2212 DAG.getNode(ISD::SUB, VT, Tmp1,
2213 DAG.getConstant(1, VT)));
2214 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead
2215 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
2216 TLI.isOperationLegal(ISD::CTLZ, VT)) {
2217 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT,
2218 DAG.getConstant(getSizeInBits(VT), VT),
2219 DAG.getNode(ISD::CTLZ, VT, Tmp3)));
2221 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
2226 assert(0 && "Cannot expand this yet!");
2239 Tmp1 = LegalizeOp(Node->getOperand(0));
2240 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2241 case TargetLowering::Legal:
2242 if (Tmp1 != Node->getOperand(0))
2243 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2245 case TargetLowering::Promote:
2246 case TargetLowering::Custom:
2247 assert(0 && "Cannot promote/custom handle this yet!");
2248 case TargetLowering::Expand:
2249 switch(Node->getOpcode()) {
2251 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2252 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2253 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0),
2258 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2259 MVT::ValueType VT = Node->getValueType(0);
2260 Tmp2 = DAG.getConstantFP(0.0, VT);
2261 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2262 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2263 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2264 Result = LegalizeOp(Result);
2270 MVT::ValueType VT = Node->getValueType(0);
2271 const char *FnName = 0;
2272 switch(Node->getOpcode()) {
2273 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2274 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2275 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2276 default: assert(0 && "Unreachable!");
2279 Result = ExpandLibCall(FnName, Node, Dummy);
2283 assert(0 && "Unreachable!");
2289 case ISD::BIT_CONVERT:
2290 if (!isTypeLegal(Node->getOperand(0).getValueType()))
2291 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2293 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2294 Node->getOperand(0).getValueType())) {
2295 default: assert(0 && "Unknown operation action!");
2296 case TargetLowering::Expand:
2297 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2299 case TargetLowering::Legal:
2300 Tmp1 = LegalizeOp(Node->getOperand(0));
2301 if (Tmp1 != Node->getOperand(0))
2302 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Tmp1);
2307 // Conversion operators. The source and destination have different types.
2308 case ISD::SINT_TO_FP:
2309 case ISD::UINT_TO_FP: {
2310 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2311 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2313 switch (TLI.getOperationAction(Node->getOpcode(),
2314 Node->getOperand(0).getValueType())) {
2315 default: assert(0 && "Unknown operation action!");
2316 case TargetLowering::Expand:
2317 Result = ExpandLegalINT_TO_FP(isSigned,
2318 LegalizeOp(Node->getOperand(0)),
2319 Node->getValueType(0));
2320 AddLegalizedOperand(Op, Result);
2322 case TargetLowering::Promote:
2323 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2324 Node->getValueType(0),
2326 AddLegalizedOperand(Op, Result);
2328 case TargetLowering::Legal:
2330 case TargetLowering::Custom: {
2331 Tmp1 = LegalizeOp(Node->getOperand(0));
2333 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2334 Tmp = TLI.LowerOperation(Tmp, DAG);
2336 Tmp = LegalizeOp(Tmp); // Relegalize input.
2337 AddLegalizedOperand(Op, Tmp);
2340 assert(0 && "Target Must Lower this");
2345 Tmp1 = LegalizeOp(Node->getOperand(0));
2346 if (Tmp1 != Node->getOperand(0))
2347 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2350 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2351 Node->getValueType(0), Node->getOperand(0));
2355 Result = PromoteOp(Node->getOperand(0));
2356 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2357 Result, DAG.getValueType(Node->getOperand(0).getValueType()));
2358 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result);
2360 Result = PromoteOp(Node->getOperand(0));
2361 Result = DAG.getZeroExtendInReg(Result,
2362 Node->getOperand(0).getValueType());
2363 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result);
2370 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2372 Tmp1 = LegalizeOp(Node->getOperand(0));
2373 if (Tmp1 != Node->getOperand(0))
2374 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2377 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2379 // Since the result is legal, we should just be able to truncate the low
2380 // part of the source.
2381 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2384 Result = PromoteOp(Node->getOperand(0));
2385 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2390 case ISD::FP_TO_SINT:
2391 case ISD::FP_TO_UINT:
2392 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2394 Tmp1 = LegalizeOp(Node->getOperand(0));
2396 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2397 default: assert(0 && "Unknown operation action!");
2398 case TargetLowering::Expand:
2399 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2400 SDOperand True, False;
2401 MVT::ValueType VT = Node->getOperand(0).getValueType();
2402 MVT::ValueType NVT = Node->getValueType(0);
2403 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2404 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2405 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2406 Node->getOperand(0), Tmp2, ISD::SETLT);
2407 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2408 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2409 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2411 False = DAG.getNode(ISD::XOR, NVT, False,
2412 DAG.getConstant(1ULL << ShiftAmt, NVT));
2413 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False));
2414 AddLegalizedOperand(SDOperand(Node, 0), Result);
2417 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2420 case TargetLowering::Promote:
2421 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2422 Node->getOpcode() == ISD::FP_TO_SINT);
2423 AddLegalizedOperand(Op, Result);
2425 case TargetLowering::Custom: {
2427 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2428 Tmp = TLI.LowerOperation(Tmp, DAG);
2430 Tmp = LegalizeOp(Tmp);
2431 AddLegalizedOperand(Op, Tmp);
2434 // The target thinks this is legal afterall.
2438 case TargetLowering::Legal:
2442 if (Tmp1 != Node->getOperand(0))
2443 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2446 assert(0 && "Shouldn't need to expand other operators here!");
2448 Result = PromoteOp(Node->getOperand(0));
2449 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2454 case ISD::ANY_EXTEND:
2455 case ISD::ZERO_EXTEND:
2456 case ISD::SIGN_EXTEND:
2457 case ISD::FP_EXTEND:
2459 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2461 Tmp1 = LegalizeOp(Node->getOperand(0));
2462 if (Tmp1 != Node->getOperand(0))
2463 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2466 assert(0 && "Shouldn't need to expand other operators here!");
2469 switch (Node->getOpcode()) {
2470 case ISD::ANY_EXTEND:
2471 Result = PromoteOp(Node->getOperand(0));
2472 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2474 case ISD::ZERO_EXTEND:
2475 Result = PromoteOp(Node->getOperand(0));
2476 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2477 Result = DAG.getZeroExtendInReg(Result,
2478 Node->getOperand(0).getValueType());
2480 case ISD::SIGN_EXTEND:
2481 Result = PromoteOp(Node->getOperand(0));
2482 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2483 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2485 DAG.getValueType(Node->getOperand(0).getValueType()));
2487 case ISD::FP_EXTEND:
2488 Result = PromoteOp(Node->getOperand(0));
2489 if (Result.getValueType() != Op.getValueType())
2490 // Dynamically dead while we have only 2 FP types.
2491 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2494 Result = PromoteOp(Node->getOperand(0));
2495 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2500 case ISD::FP_ROUND_INREG:
2501 case ISD::SIGN_EXTEND_INREG: {
2502 Tmp1 = LegalizeOp(Node->getOperand(0));
2503 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2505 // If this operation is not supported, convert it to a shl/shr or load/store
2507 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2508 default: assert(0 && "This action not supported for this op yet!");
2509 case TargetLowering::Legal:
2510 if (Tmp1 != Node->getOperand(0))
2511 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
2512 DAG.getValueType(ExtraVT));
2514 case TargetLowering::Expand:
2515 // If this is an integer extend and shifts are supported, do that.
2516 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2517 // NOTE: we could fall back on load/store here too for targets without
2518 // SAR. However, it is doubtful that any exist.
2519 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2520 MVT::getSizeInBits(ExtraVT);
2521 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2522 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2523 Node->getOperand(0), ShiftCst);
2524 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2526 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2527 // The only way we can lower this is to turn it into a STORETRUNC,
2528 // EXTLOAD pair, targetting a temporary location (a stack slot).
2530 // NOTE: there is a choice here between constantly creating new stack
2531 // slots and always reusing the same one. We currently always create
2532 // new ones, as reuse may inhibit scheduling.
2533 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2534 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
2535 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
2536 MachineFunction &MF = DAG.getMachineFunction();
2538 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2539 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2540 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2541 Node->getOperand(0), StackSlot,
2542 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2543 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2544 Result, StackSlot, DAG.getSrcValue(NULL),
2547 assert(0 && "Unknown op");
2549 Result = LegalizeOp(Result);
2556 // Note that LegalizeOp may be reentered even from single-use nodes, which
2557 // means that we always must cache transformed nodes.
2558 AddLegalizedOperand(Op, Result);
2562 /// PromoteOp - Given an operation that produces a value in an invalid type,
2563 /// promote it to compute the value into a larger type. The produced value will
2564 /// have the correct bits for the low portion of the register, but no guarantee
2565 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2566 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2567 MVT::ValueType VT = Op.getValueType();
2568 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2569 assert(getTypeAction(VT) == Promote &&
2570 "Caller should expand or legalize operands that are not promotable!");
2571 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2572 "Cannot promote to smaller type!");
2574 SDOperand Tmp1, Tmp2, Tmp3;
2577 SDNode *Node = Op.Val;
2579 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2580 if (I != PromotedNodes.end()) return I->second;
2582 // Promotion needs an optimization step to clean up after it, and is not
2583 // careful to avoid operations the target does not support. Make sure that
2584 // all generated operations are legalized in the next iteration.
2585 NeedsAnotherIteration = true;
2587 switch (Node->getOpcode()) {
2588 case ISD::CopyFromReg:
2589 assert(0 && "CopyFromReg must be legal!");
2591 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2592 assert(0 && "Do not know how to promote this operator!");
2595 Result = DAG.getNode(ISD::UNDEF, NVT);
2599 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2601 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2602 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2604 case ISD::ConstantFP:
2605 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2606 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2610 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2611 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2612 Node->getOperand(1), Node->getOperand(2));
2613 Result = LegalizeOp(Result);
2617 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2619 Result = LegalizeOp(Node->getOperand(0));
2620 assert(Result.getValueType() >= NVT &&
2621 "This truncation doesn't make sense!");
2622 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2623 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2626 // The truncation is not required, because we don't guarantee anything
2627 // about high bits anyway.
2628 Result = PromoteOp(Node->getOperand(0));
2631 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2632 // Truncate the low part of the expanded value to the result type
2633 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2636 case ISD::SIGN_EXTEND:
2637 case ISD::ZERO_EXTEND:
2638 case ISD::ANY_EXTEND:
2639 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2640 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2642 // Input is legal? Just do extend all the way to the larger type.
2643 Result = LegalizeOp(Node->getOperand(0));
2644 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2647 // Promote the reg if it's smaller.
2648 Result = PromoteOp(Node->getOperand(0));
2649 // The high bits are not guaranteed to be anything. Insert an extend.
2650 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2651 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2652 DAG.getValueType(Node->getOperand(0).getValueType()));
2653 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2654 Result = DAG.getZeroExtendInReg(Result,
2655 Node->getOperand(0).getValueType());
2659 case ISD::BIT_CONVERT:
2660 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2661 Result = PromoteOp(Result);
2664 case ISD::FP_EXTEND:
2665 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2667 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2668 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2669 case Promote: assert(0 && "Unreachable with 2 FP types!");
2671 // Input is legal? Do an FP_ROUND_INREG.
2672 Result = LegalizeOp(Node->getOperand(0));
2673 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2674 DAG.getValueType(VT));
2679 case ISD::SINT_TO_FP:
2680 case ISD::UINT_TO_FP:
2681 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2683 Result = LegalizeOp(Node->getOperand(0));
2684 // No extra round required here.
2685 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2689 Result = PromoteOp(Node->getOperand(0));
2690 if (Node->getOpcode() == ISD::SINT_TO_FP)
2691 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2693 DAG.getValueType(Node->getOperand(0).getValueType()));
2695 Result = DAG.getZeroExtendInReg(Result,
2696 Node->getOperand(0).getValueType());
2697 // No extra round required here.
2698 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2701 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
2702 Node->getOperand(0));
2703 // Round if we cannot tolerate excess precision.
2704 if (NoExcessFPPrecision)
2705 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2706 DAG.getValueType(VT));
2711 case ISD::SIGN_EXTEND_INREG:
2712 Result = PromoteOp(Node->getOperand(0));
2713 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2714 Node->getOperand(1));
2716 case ISD::FP_TO_SINT:
2717 case ISD::FP_TO_UINT:
2718 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2720 Tmp1 = LegalizeOp(Node->getOperand(0));
2723 // The input result is prerounded, so we don't have to do anything
2725 Tmp1 = PromoteOp(Node->getOperand(0));
2728 assert(0 && "not implemented");
2730 // If we're promoting a UINT to a larger size, check to see if the new node
2731 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
2732 // we can use that instead. This allows us to generate better code for
2733 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
2734 // legal, such as PowerPC.
2735 if (Node->getOpcode() == ISD::FP_TO_UINT &&
2736 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
2737 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
2738 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
2739 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
2741 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2747 Tmp1 = PromoteOp(Node->getOperand(0));
2748 assert(Tmp1.getValueType() == NVT);
2749 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2750 // NOTE: we do not have to do any extra rounding here for
2751 // NoExcessFPPrecision, because we know the input will have the appropriate
2752 // precision, and these operations don't modify precision at all.
2758 Tmp1 = PromoteOp(Node->getOperand(0));
2759 assert(Tmp1.getValueType() == NVT);
2760 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2761 if(NoExcessFPPrecision)
2762 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2763 DAG.getValueType(VT));
2772 // The input may have strange things in the top bits of the registers, but
2773 // these operations don't care. They may have weird bits going out, but
2774 // that too is okay if they are integer operations.
2775 Tmp1 = PromoteOp(Node->getOperand(0));
2776 Tmp2 = PromoteOp(Node->getOperand(1));
2777 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2778 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2783 // The input may have strange things in the top bits of the registers, but
2784 // these operations don't care.
2785 Tmp1 = PromoteOp(Node->getOperand(0));
2786 Tmp2 = PromoteOp(Node->getOperand(1));
2787 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2788 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2790 // Floating point operations will give excess precision that we may not be
2791 // able to tolerate. If we DO allow excess precision, just leave it,
2792 // otherwise excise it.
2793 // FIXME: Why would we need to round FP ops more than integer ones?
2794 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
2795 if (NoExcessFPPrecision)
2796 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2797 DAG.getValueType(VT));
2802 // These operators require that their input be sign extended.
2803 Tmp1 = PromoteOp(Node->getOperand(0));
2804 Tmp2 = PromoteOp(Node->getOperand(1));
2805 if (MVT::isInteger(NVT)) {
2806 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2807 DAG.getValueType(VT));
2808 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
2809 DAG.getValueType(VT));
2811 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2813 // Perform FP_ROUND: this is probably overly pessimistic.
2814 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
2815 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2816 DAG.getValueType(VT));
2820 // These operators require that their input be fp extended.
2821 Tmp1 = PromoteOp(Node->getOperand(0));
2822 Tmp2 = PromoteOp(Node->getOperand(1));
2823 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2825 // Perform FP_ROUND: this is probably overly pessimistic.
2826 if (NoExcessFPPrecision)
2827 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2828 DAG.getValueType(VT));
2833 // These operators require that their input be zero extended.
2834 Tmp1 = PromoteOp(Node->getOperand(0));
2835 Tmp2 = PromoteOp(Node->getOperand(1));
2836 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
2837 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2838 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
2839 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2843 Tmp1 = PromoteOp(Node->getOperand(0));
2844 Tmp2 = LegalizeOp(Node->getOperand(1));
2845 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2);
2848 // The input value must be properly sign extended.
2849 Tmp1 = PromoteOp(Node->getOperand(0));
2850 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2851 DAG.getValueType(VT));
2852 Tmp2 = LegalizeOp(Node->getOperand(1));
2853 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2);
2856 // The input value must be properly zero extended.
2857 Tmp1 = PromoteOp(Node->getOperand(0));
2858 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2859 Tmp2 = LegalizeOp(Node->getOperand(1));
2860 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2);
2863 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2864 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2865 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2,
2866 Node->getOperand(2), VT);
2867 // Remember that we legalized the chain.
2868 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2873 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2874 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2875 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2,
2876 Node->getOperand(2),
2877 cast<VTSDNode>(Node->getOperand(3))->getVT());
2878 // Remember that we legalized the chain.
2879 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2882 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2883 case Expand: assert(0 && "It's impossible to expand bools");
2885 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition.
2888 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2891 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
2892 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
2893 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3);
2895 case ISD::SELECT_CC:
2896 Tmp2 = PromoteOp(Node->getOperand(2)); // True
2897 Tmp3 = PromoteOp(Node->getOperand(3)); // False
2898 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
2899 Node->getOperand(1), Tmp2, Tmp3,
2900 Node->getOperand(4));
2904 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2905 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
2907 std::vector<SDOperand> Ops;
2908 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i)
2909 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2911 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
2912 "Can only promote single result calls");
2913 std::vector<MVT::ValueType> RetTyVTs;
2914 RetTyVTs.reserve(2);
2915 RetTyVTs.push_back(NVT);
2916 RetTyVTs.push_back(MVT::Other);
2917 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
2918 Node->getOpcode() == ISD::TAILCALL);
2919 Result = SDOperand(NC, 0);
2921 // Insert the new chain mapping.
2922 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2928 Tmp1 = Node->getOperand(0);
2929 //Zero extend the argument
2930 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2931 // Perform the larger operation, then subtract if needed.
2932 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2933 switch(Node->getOpcode())
2939 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2940 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2941 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
2942 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2943 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1);
2946 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2947 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2948 DAG.getConstant(getSizeInBits(NVT) -
2949 getSizeInBits(VT), NVT));
2955 assert(Result.Val && "Didn't set a result!");
2956 AddPromotedOperand(Op, Result);
2960 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
2961 /// The resultant code need not be legal. Note that SrcOp is the input operand
2962 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
2963 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
2965 // Create the stack frame object.
2966 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2967 unsigned ByteSize = MVT::getSizeInBits(DestVT)/8;
2968 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
2969 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
2971 // Emit a store to the stack slot.
2972 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
2973 SrcOp, FIPtr, DAG.getSrcValue(NULL));
2974 // Result is a load from the stack slot.
2975 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0));
2978 /// ExpandAddSub - Find a clever way to expand this add operation into
2980 void SelectionDAGLegalize::
2981 ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
2982 SDOperand &Lo, SDOperand &Hi) {
2983 // Expand the subcomponents.
2984 SDOperand LHSL, LHSH, RHSL, RHSH;
2985 ExpandOp(LHS, LHSL, LHSH);
2986 ExpandOp(RHS, RHSL, RHSH);
2988 std::vector<SDOperand> Ops;
2989 Ops.push_back(LHSL);
2990 Ops.push_back(LHSH);
2991 Ops.push_back(RHSL);
2992 Ops.push_back(RHSH);
2993 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
2994 Lo = DAG.getNode(NodeOp, VTs, Ops);
2995 Hi = Lo.getValue(1);
2998 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
2999 SDOperand Op, SDOperand Amt,
3000 SDOperand &Lo, SDOperand &Hi) {
3001 // Expand the subcomponents.
3002 SDOperand LHSL, LHSH;
3003 ExpandOp(Op, LHSL, LHSH);
3005 std::vector<SDOperand> Ops;
3006 Ops.push_back(LHSL);
3007 Ops.push_back(LHSH);
3009 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
3010 Lo = DAG.getNode(NodeOp, VTs, Ops);
3011 Hi = Lo.getValue(1);
3015 /// ExpandShift - Try to find a clever way to expand this shift operation out to
3016 /// smaller elements. If we can't find a way that is more efficient than a
3017 /// libcall on this target, return false. Otherwise, return true with the
3018 /// low-parts expanded into Lo and Hi.
3019 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3020 SDOperand &Lo, SDOperand &Hi) {
3021 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3022 "This is not a shift!");
3024 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3025 SDOperand ShAmt = LegalizeOp(Amt);
3026 MVT::ValueType ShTy = ShAmt.getValueType();
3027 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3028 unsigned NVTBits = MVT::getSizeInBits(NVT);
3030 // Handle the case when Amt is an immediate. Other cases are currently broken
3031 // and are disabled.
3032 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3033 unsigned Cst = CN->getValue();
3034 // Expand the incoming operand to be shifted, so that we have its parts
3036 ExpandOp(Op, InL, InH);
3040 Lo = DAG.getConstant(0, NVT);
3041 Hi = DAG.getConstant(0, NVT);
3042 } else if (Cst > NVTBits) {
3043 Lo = DAG.getConstant(0, NVT);
3044 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
3045 } else if (Cst == NVTBits) {
3046 Lo = DAG.getConstant(0, NVT);
3049 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
3050 Hi = DAG.getNode(ISD::OR, NVT,
3051 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
3052 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
3057 Lo = DAG.getConstant(0, NVT);
3058 Hi = DAG.getConstant(0, NVT);
3059 } else if (Cst > NVTBits) {
3060 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
3061 Hi = DAG.getConstant(0, NVT);
3062 } else if (Cst == NVTBits) {
3064 Hi = DAG.getConstant(0, NVT);
3066 Lo = DAG.getNode(ISD::OR, NVT,
3067 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3068 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3069 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
3074 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
3075 DAG.getConstant(NVTBits-1, ShTy));
3076 } else if (Cst > NVTBits) {
3077 Lo = DAG.getNode(ISD::SRA, NVT, InH,
3078 DAG.getConstant(Cst-NVTBits, ShTy));
3079 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3080 DAG.getConstant(NVTBits-1, ShTy));
3081 } else if (Cst == NVTBits) {
3083 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3084 DAG.getConstant(NVTBits-1, ShTy));
3086 Lo = DAG.getNode(ISD::OR, NVT,
3087 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3088 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3089 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
3094 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy,
3095 // so disable it for now. Currently targets are handling this via SHL_PARTS
3099 // If we have an efficient select operation (or if the selects will all fold
3100 // away), lower to some complex code, otherwise just emit the libcall.
3101 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt))
3105 ExpandOp(Op, InL, InH);
3106 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt
3107 DAG.getConstant(NVTBits, ShTy), ShAmt);
3109 // Compare the unmasked shift amount against 32.
3110 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt,
3111 DAG.getConstant(NVTBits, ShTy), ISD::SETGE);
3113 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) {
3114 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31
3115 DAG.getConstant(NVTBits-1, ShTy));
3116 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31
3117 DAG.getConstant(NVTBits-1, ShTy));
3120 if (Opc == ISD::SHL) {
3121 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt)
3122 DAG.getNode(ISD::SHL, NVT, InH, ShAmt),
3123 DAG.getNode(ISD::SRL, NVT, InL, NAmt));
3124 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31
3126 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
3127 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2);
3129 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT,
3130 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt,
3131 DAG.getConstant(32, ShTy),
3133 DAG.getConstant(0, NVT),
3134 DAG.getNode(ISD::SHL, NVT, InH, NAmt));
3135 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt)
3137 DAG.getNode(ISD::SRL, NVT, InL, ShAmt));
3138 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31
3141 if (Opc == ISD::SRA)
3142 HiPart = DAG.getNode(ISD::SRA, NVT, InH,
3143 DAG.getConstant(NVTBits-1, ShTy));
3145 HiPart = DAG.getConstant(0, NVT);
3146 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
3147 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2);
3152 /// FindLatestCallSeqStart - Scan up the dag to find the latest (highest
3153 /// NodeDepth) node that is an CallSeqStart operation and occurs later than
3155 static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found,
3156 std::set<SDNode*> &Visited) {
3157 if (Node->getNodeDepth() <= Found->getNodeDepth() ||
3158 !Visited.insert(Node).second) return;
3160 // If we found an CALLSEQ_START, we already know this node occurs later
3161 // than the Found node. Just remember this node and return.
3162 if (Node->getOpcode() == ISD::CALLSEQ_START) {
3167 // Otherwise, scan the operands of Node to see if any of them is a call.
3168 assert(Node->getNumOperands() != 0 &&
3169 "All leaves should have depth equal to the entry node!");
3170 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i)
3171 FindLatestCallSeqStart(Node->getOperand(i).Val, Found, Visited);
3173 // Tail recurse for the last iteration.
3174 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val,
3179 /// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest
3180 /// NodeDepth) node that is an CallSeqEnd operation and occurs more recent
3182 static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found,
3183 std::set<SDNode*> &Visited) {
3184 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) ||
3185 !Visited.insert(Node).second) return;
3187 // If we found an CALLSEQ_END, we already know this node occurs earlier
3188 // than the Found node. Just remember this node and return.
3189 if (Node->getOpcode() == ISD::CALLSEQ_END) {
3194 // Otherwise, scan the operands of Node to see if any of them is a call.
3195 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
3196 if (UI == E) return;
3197 for (--E; UI != E; ++UI)
3198 FindEarliestCallSeqEnd(*UI, Found, Visited);
3200 // Tail recurse for the last iteration.
3201 FindEarliestCallSeqEnd(*UI, Found, Visited);
3204 /// FindCallSeqEnd - Given a chained node that is part of a call sequence,
3205 /// find the CALLSEQ_END node that terminates the call sequence.
3206 static SDNode *FindCallSeqEnd(SDNode *Node) {
3207 if (Node->getOpcode() == ISD::CALLSEQ_END)
3209 if (Node->use_empty())
3210 return 0; // No CallSeqEnd
3212 SDOperand TheChain(Node, Node->getNumValues()-1);
3213 if (TheChain.getValueType() != MVT::Other)
3214 TheChain = SDOperand(Node, 0);
3215 if (TheChain.getValueType() != MVT::Other)
3218 for (SDNode::use_iterator UI = Node->use_begin(),
3219 E = Node->use_end(); UI != E; ++UI) {
3221 // Make sure to only follow users of our token chain.
3223 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
3224 if (User->getOperand(i) == TheChain)
3225 if (SDNode *Result = FindCallSeqEnd(User))
3231 /// FindCallSeqStart - Given a chained node that is part of a call sequence,
3232 /// find the CALLSEQ_START node that initiates the call sequence.
3233 static SDNode *FindCallSeqStart(SDNode *Node) {
3234 assert(Node && "Didn't find callseq_start for a call??");
3235 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
3237 assert(Node->getOperand(0).getValueType() == MVT::Other &&
3238 "Node doesn't have a token chain argument!");
3239 return FindCallSeqStart(Node->getOperand(0).Val);
3243 /// FindInputOutputChains - If we are replacing an operation with a call we need
3244 /// to find the call that occurs before and the call that occurs after it to
3245 /// properly serialize the calls in the block. The returned operand is the
3246 /// input chain value for the new call (e.g. the entry node or the previous
3247 /// call), and OutChain is set to be the chain node to update to point to the
3248 /// end of the call chain.
3249 static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain,
3251 SDNode *LatestCallSeqStart = Entry.Val;
3252 SDNode *LatestCallSeqEnd = 0;
3253 std::set<SDNode*> Visited;
3254 FindLatestCallSeqStart(OpNode, LatestCallSeqStart, Visited);
3256 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n";
3258 // It is possible that no ISD::CALLSEQ_START was found because there is no
3259 // previous call in the function. LatestCallStackDown may in that case be
3260 // the entry node itself. Do not attempt to find a matching CALLSEQ_END
3261 // unless LatestCallStackDown is an CALLSEQ_START.
3262 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) {
3263 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart);
3264 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n";
3266 LatestCallSeqEnd = Entry.Val;
3268 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd");
3270 // Finally, find the first call that this must come before, first we find the
3271 // CallSeqEnd that ends the call.
3273 FindEarliestCallSeqEnd(OpNode, OutChain, Visited);
3276 // If we found one, translate from the adj up to the callseq_start.
3278 OutChain = FindCallSeqStart(OutChain);
3280 return SDOperand(LatestCallSeqEnd, 0);
3283 /// SpliceCallInto - Given the result chain of a libcall (CallResult), and a
3284 void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult,
3286 // Nothing to splice it into?
3287 if (OutChain == 0) return;
3289 assert(OutChain->getOperand(0).getValueType() == MVT::Other);
3292 // Form a token factor node merging the old inval and the new inval.
3293 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult,
3294 OutChain->getOperand(0));
3295 // Change the node to refer to the new token.
3296 OutChain->setAdjCallChain(InToken);
3300 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
3301 // does not fit into a register, return the lo part and set the hi part to the
3302 // by-reg argument. If it does fit into a single register, return the result
3303 // and leave the Hi part unset.
3304 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3307 SDOperand InChain = FindInputOutputChains(Node, OutChain,
3308 DAG.getEntryNode());
3309 if (InChain.Val == 0)
3310 InChain = DAG.getEntryNode();
3312 TargetLowering::ArgListTy Args;
3313 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3314 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3315 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3316 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3318 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3320 // Splice the libcall in wherever FindInputOutputChains tells us to.
3321 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3322 std::pair<SDOperand,SDOperand> CallInfo =
3323 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3327 switch (getTypeAction(CallInfo.first.getValueType())) {
3328 default: assert(0 && "Unknown thing");
3330 Result = CallInfo.first;
3333 assert(0 && "Cannot promote this yet!");
3335 ExpandOp(CallInfo.first, Result, Hi);
3336 CallInfo.second = LegalizeOp(CallInfo.second);
3340 SpliceCallInto(CallInfo.second, OutChain);
3341 NeedsAnotherIteration = true;
3346 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3347 /// destination type is legal.
3348 SDOperand SelectionDAGLegalize::
3349 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3350 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3351 assert(getTypeAction(Source.getValueType()) == Expand &&
3352 "This is not an expansion!");
3353 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3356 assert(Source.getValueType() == MVT::i64 &&
3357 "This only works for 64-bit -> FP");
3358 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3359 // incoming integer is set. To handle this, we dynamically test to see if
3360 // it is set, and, if so, add a fudge factor.
3362 ExpandOp(Source, Lo, Hi);
3364 // If this is unsigned, and not supported, first perform the conversion to
3365 // signed, then adjust the result if the sign bit is set.
3366 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3367 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3369 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3370 DAG.getConstant(0, Hi.getValueType()),
3372 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3373 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3374 SignSet, Four, Zero);
3375 uint64_t FF = 0x5f800000ULL;
3376 if (TLI.isLittleEndian()) FF <<= 32;
3377 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3379 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3380 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3381 SDOperand FudgeInReg;
3382 if (DestTy == MVT::f32)
3383 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3384 DAG.getSrcValue(NULL));
3386 assert(DestTy == MVT::f64 && "Unexpected conversion");
3387 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3388 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
3390 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3393 // Check to see if the target has a custom way to lower this. If so, use it.
3394 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3395 default: assert(0 && "This action not implemented for this operation!");
3396 case TargetLowering::Legal:
3397 case TargetLowering::Expand:
3398 break; // This case is handled below.
3399 case TargetLowering::Custom: {
3400 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3403 return LegalizeOp(NV);
3404 break; // The target decided this was legal after all
3408 // Expand the source, then glue it back together for the call. We must expand
3409 // the source in case it is shared (this pass of legalize must traverse it).
3410 SDOperand SrcLo, SrcHi;
3411 ExpandOp(Source, SrcLo, SrcHi);
3412 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
3414 SDNode *OutChain = 0;
3415 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain,
3416 DAG.getEntryNode());
3417 const char *FnName = 0;
3418 if (DestTy == MVT::f32)
3419 FnName = "__floatdisf";
3421 assert(DestTy == MVT::f64 && "Unknown fp value type!");
3422 FnName = "__floatdidf";
3425 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy());
3427 TargetLowering::ArgListTy Args;
3428 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType());
3430 Args.push_back(std::make_pair(Source, ArgTy));
3432 // We don't care about token chains for libcalls. We just use the entry
3433 // node as our input and ignore the output chain. This allows us to place
3434 // calls wherever we need them to satisfy data dependences.
3435 const Type *RetTy = MVT::getTypeForValueType(DestTy);
3437 std::pair<SDOperand,SDOperand> CallResult =
3438 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true,
3441 SpliceCallInto(CallResult.second, OutChain);
3442 return CallResult.first;
3447 /// ExpandOp - Expand the specified SDOperand into its two component pieces
3448 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
3449 /// LegalizeNodes map is filled in for any results that are not expanded, the
3450 /// ExpandedNodes map is filled in for any results that are expanded, and the
3451 /// Lo/Hi values are returned.
3452 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
3453 MVT::ValueType VT = Op.getValueType();
3454 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3455 SDNode *Node = Op.Val;
3456 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
3457 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
3458 "Cannot expand FP values!");
3459 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
3460 "Cannot expand to FP value or to larger int value!");
3462 // See if we already expanded it.
3463 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
3464 = ExpandedNodes.find(Op);
3465 if (I != ExpandedNodes.end()) {
3466 Lo = I->second.first;
3467 Hi = I->second.second;
3471 // Expanding to multiple registers needs to perform an optimization step, and
3472 // is not careful to avoid operations the target does not support. Make sure
3473 // that all generated operations are legalized in the next iteration.
3474 NeedsAnotherIteration = true;
3476 switch (Node->getOpcode()) {
3477 case ISD::CopyFromReg:
3478 assert(0 && "CopyFromReg must be legal!");
3480 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
3481 assert(0 && "Do not know how to expand this operator!");
3484 Lo = DAG.getNode(ISD::UNDEF, NVT);
3485 Hi = DAG.getNode(ISD::UNDEF, NVT);
3487 case ISD::Constant: {
3488 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
3489 Lo = DAG.getConstant(Cst, NVT);
3490 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
3493 case ISD::ConstantVec: {
3494 unsigned NumElements = Node->getNumOperands();
3495 // If we only have two elements left in the constant vector, just break it
3496 // apart into the two scalar constants it contains. Otherwise, bisect the
3497 // ConstantVec, and return each half as a new ConstantVec.
3498 // FIXME: this is hard coded as big endian, it may have to change to support
3499 // SSE and Alpha MVI
3500 if (NumElements == 2) {
3501 Hi = Node->getOperand(0);
3502 Lo = Node->getOperand(1);
3505 std::vector<SDOperand> LoOps, HiOps;
3506 for (unsigned I = 0, E = NumElements; I < E; ++I) {
3507 HiOps.push_back(Node->getOperand(I));
3508 LoOps.push_back(Node->getOperand(I+NumElements));
3510 Lo = DAG.getNode(ISD::ConstantVec, MVT::Vector, LoOps);
3511 Hi = DAG.getNode(ISD::ConstantVec, MVT::Vector, HiOps);
3516 case ISD::BUILD_PAIR:
3517 // Legalize both operands. FIXME: in the future we should handle the case
3518 // where the two elements are not legal.
3519 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
3520 Lo = LegalizeOp(Node->getOperand(0));
3521 Hi = LegalizeOp(Node->getOperand(1));
3524 case ISD::SIGN_EXTEND_INREG:
3525 ExpandOp(Node->getOperand(0), Lo, Hi);
3526 // Sign extend the lo-part.
3527 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
3528 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
3529 TLI.getShiftAmountTy()));
3530 // sext_inreg the low part if needed.
3531 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
3535 ExpandOp(Node->getOperand(0), Lo, Hi);
3536 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
3537 DAG.getNode(ISD::CTPOP, NVT, Lo),
3538 DAG.getNode(ISD::CTPOP, NVT, Hi));
3539 Hi = DAG.getConstant(0, NVT);
3543 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
3544 ExpandOp(Node->getOperand(0), Lo, Hi);
3545 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3546 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
3547 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
3549 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
3550 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
3552 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
3553 Hi = DAG.getConstant(0, NVT);
3558 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
3559 ExpandOp(Node->getOperand(0), Lo, Hi);
3560 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3561 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
3562 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
3564 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
3565 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
3567 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
3568 Hi = DAG.getConstant(0, NVT);
3573 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3574 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3575 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3577 // Increment the pointer to the other half.
3578 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
3579 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3580 getIntPtrConstant(IncrementSize));
3581 //Is this safe? declaring that the two parts of the split load
3582 //are from the same instruction?
3583 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3585 // Build a factor node to remember that this load is independent of the
3587 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3590 // Remember that we legalized the chain.
3591 AddLegalizedOperand(Op.getValue(1), TF);
3592 if (!TLI.isLittleEndian())
3597 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3598 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3599 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue();
3600 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3602 // If we only have two elements, turn into a pair of scalar loads.
3603 // FIXME: handle case where a vector of two elements is fine, such as
3604 // 2 x double on SSE2.
3605 if (NumElements == 2) {
3606 Lo = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4));
3607 // Increment the pointer to the other half.
3608 unsigned IncrementSize = MVT::getSizeInBits(EVT)/8;
3609 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3610 getIntPtrConstant(IncrementSize));
3611 //Is this safe? declaring that the two parts of the split load
3612 //are from the same instruction?
3613 Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4));
3615 NumElements /= 2; // Split the vector in half
3616 Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4));
3617 unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8;
3618 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3619 getIntPtrConstant(IncrementSize));
3620 //Is this safe? declaring that the two parts of the split load
3621 //are from the same instruction?
3622 Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4));
3625 // Build a factor node to remember that this load is independent of the
3627 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3630 // Remember that we legalized the chain.
3631 AddLegalizedOperand(Op.getValue(1), TF);
3632 if (!TLI.isLittleEndian())
3639 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue();
3640 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3641 SDOperand LL, LH, RL, RH;
3643 ExpandOp(Node->getOperand(0), LL, LH);
3644 ExpandOp(Node->getOperand(1), RL, RH);
3646 // If we only have two elements, turn into a pair of scalar loads.
3647 // FIXME: handle case where a vector of two elements is fine, such as
3648 // 2 x double on SSE2.
3649 if (NumElements == 2) {
3650 unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT);
3651 Lo = DAG.getNode(Opc, EVT, LL, RL);
3652 Hi = DAG.getNode(Opc, EVT, LH, RH);
3654 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, LL.getOperand(2),
3656 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, LH.getOperand(2),
3663 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3664 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
3666 bool Changed = false;
3667 std::vector<SDOperand> Ops;
3668 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
3669 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3670 Changed |= Ops.back() != Node->getOperand(i);
3673 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
3674 "Can only expand a call once so far, not i64 -> i16!");
3676 std::vector<MVT::ValueType> RetTyVTs;
3677 RetTyVTs.reserve(3);
3678 RetTyVTs.push_back(NVT);
3679 RetTyVTs.push_back(NVT);
3680 RetTyVTs.push_back(MVT::Other);
3681 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops,
3682 Node->getOpcode() == ISD::TAILCALL);
3683 Lo = SDOperand(NC, 0);
3684 Hi = SDOperand(NC, 1);
3686 // Insert the new chain mapping.
3687 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2));
3692 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
3693 SDOperand LL, LH, RL, RH;
3694 ExpandOp(Node->getOperand(0), LL, LH);
3695 ExpandOp(Node->getOperand(1), RL, RH);
3696 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
3697 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
3701 SDOperand C, LL, LH, RL, RH;
3703 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3704 case Expand: assert(0 && "It's impossible to expand bools");
3706 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
3709 C = PromoteOp(Node->getOperand(0)); // Promote the condition.
3712 ExpandOp(Node->getOperand(1), LL, LH);
3713 ExpandOp(Node->getOperand(2), RL, RH);
3714 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL);
3715 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH);
3718 case ISD::SELECT_CC: {
3719 SDOperand TL, TH, FL, FH;
3720 ExpandOp(Node->getOperand(2), TL, TH);
3721 ExpandOp(Node->getOperand(3), FL, FH);
3722 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3723 Node->getOperand(1), TL, FL, Node->getOperand(4));
3724 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3725 Node->getOperand(1), TH, FH, Node->getOperand(4));
3726 Lo = LegalizeOp(Lo);
3727 Hi = LegalizeOp(Hi);
3730 case ISD::SEXTLOAD: {
3731 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3732 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3733 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3736 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3738 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3741 // Remember that we legalized the chain.
3742 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3744 // The high part is obtained by SRA'ing all but one of the bits of the lo
3746 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3747 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3748 TLI.getShiftAmountTy()));
3749 Lo = LegalizeOp(Lo);
3750 Hi = LegalizeOp(Hi);
3753 case ISD::ZEXTLOAD: {
3754 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3755 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3756 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3759 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3761 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3764 // Remember that we legalized the chain.
3765 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3767 // The high part is just a zero.
3768 Hi = LegalizeOp(DAG.getConstant(0, NVT));
3769 Lo = LegalizeOp(Lo);
3772 case ISD::EXTLOAD: {
3773 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3774 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3775 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3778 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3780 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3783 // Remember that we legalized the chain.
3784 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3786 // The high part is undefined.
3787 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT));
3788 Lo = LegalizeOp(Lo);
3791 case ISD::ANY_EXTEND: {
3793 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3794 case Expand: assert(0 && "expand-expand not implemented yet!");
3795 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3797 In = PromoteOp(Node->getOperand(0));
3801 // The low part is any extension of the input (which degenerates to a copy).
3802 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In);
3803 // The high part is undefined.
3804 Hi = DAG.getNode(ISD::UNDEF, NVT);
3807 case ISD::SIGN_EXTEND: {
3809 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3810 case Expand: assert(0 && "expand-expand not implemented yet!");
3811 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3813 In = PromoteOp(Node->getOperand(0));
3814 // Emit the appropriate sign_extend_inreg to get the value we want.
3815 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In,
3816 DAG.getValueType(Node->getOperand(0).getValueType()));
3820 // The low part is just a sign extension of the input (which degenerates to
3822 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In);
3824 // The high part is obtained by SRA'ing all but one of the bits of the lo
3826 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3827 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3828 TLI.getShiftAmountTy()));
3831 case ISD::ZERO_EXTEND: {
3833 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3834 case Expand: assert(0 && "expand-expand not implemented yet!");
3835 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3837 In = PromoteOp(Node->getOperand(0));
3838 // Emit the appropriate zero_extend_inreg to get the value we want.
3839 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType());
3843 // The low part is just a zero extension of the input (which degenerates to
3845 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In);
3847 // The high part is just a zero.
3848 Hi = DAG.getConstant(0, NVT);
3852 case ISD::BIT_CONVERT: {
3853 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0),
3854 Node->getOperand(0));
3855 ExpandOp(Tmp, Lo, Hi);
3859 case ISD::READCYCLECOUNTER: {
3860 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
3861 TargetLowering::Custom &&
3862 "Must custom expand ReadCycleCounter");
3863 SDOperand T = TLI.LowerOperation(Op, DAG);
3864 assert(T.Val && "Node must be custom expanded!");
3865 Lo = LegalizeOp(T.getValue(0));
3866 Hi = LegalizeOp(T.getValue(1));
3867 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
3868 LegalizeOp(T.getValue(2)));
3872 // These operators cannot be expanded directly, emit them as calls to
3873 // library functions.
3874 case ISD::FP_TO_SINT:
3875 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
3877 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3878 case Expand: assert(0 && "cannot expand FP!");
3879 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
3880 case Promote: Op = PromoteOp(Node->getOperand(0)); break;
3883 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
3885 // Now that the custom expander is done, expand the result, which is still
3888 ExpandOp(Op, Lo, Hi);
3893 if (Node->getOperand(0).getValueType() == MVT::f32)
3894 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
3896 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
3899 case ISD::FP_TO_UINT:
3900 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
3901 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT,
3902 LegalizeOp(Node->getOperand(0)));
3903 // Now that the custom expander is done, expand the result, which is still
3905 Op = TLI.LowerOperation(Op, DAG);
3907 ExpandOp(Op, Lo, Hi);
3912 if (Node->getOperand(0).getValueType() == MVT::f32)
3913 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
3915 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
3919 // If the target wants custom lowering, do so.
3920 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
3921 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0),
3922 LegalizeOp(Node->getOperand(1)));
3923 Op = TLI.LowerOperation(Op, DAG);
3925 // Now that the custom expander is done, expand the result, which is
3927 ExpandOp(Op, Lo, Hi);
3932 // If we can emit an efficient shift operation, do so now.
3933 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3936 // If this target supports SHL_PARTS, use it.
3937 TargetLowering::LegalizeAction Action =
3938 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
3939 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
3940 Action == TargetLowering::Custom) {
3941 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1),
3946 // Otherwise, emit a libcall.
3947 Lo = ExpandLibCall("__ashldi3", Node, Hi);
3952 // If the target wants custom lowering, do so.
3953 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
3954 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0),
3955 LegalizeOp(Node->getOperand(1)));
3956 Op = TLI.LowerOperation(Op, DAG);
3958 // Now that the custom expander is done, expand the result, which is
3960 ExpandOp(Op, Lo, Hi);
3965 // If we can emit an efficient shift operation, do so now.
3966 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3969 // If this target supports SRA_PARTS, use it.
3970 TargetLowering::LegalizeAction Action =
3971 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
3972 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
3973 Action == TargetLowering::Custom) {
3974 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1),
3979 // Otherwise, emit a libcall.
3980 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
3985 // If the target wants custom lowering, do so.
3986 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
3987 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0),
3988 LegalizeOp(Node->getOperand(1)));
3989 Op = TLI.LowerOperation(Op, DAG);
3991 // Now that the custom expander is done, expand the result, which is
3993 ExpandOp(Op, Lo, Hi);
3998 // If we can emit an efficient shift operation, do so now.
3999 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
4002 // If this target supports SRL_PARTS, use it.
4003 TargetLowering::LegalizeAction Action =
4004 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
4005 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4006 Action == TargetLowering::Custom) {
4007 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1),
4012 // Otherwise, emit a libcall.
4013 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
4018 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1),
4022 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1),
4026 if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
4027 SDOperand LL, LH, RL, RH;
4028 ExpandOp(Node->getOperand(0), LL, LH);
4029 ExpandOp(Node->getOperand(1), RL, RH);
4030 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
4031 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
4032 // extended the sign bit of the low half through the upper half, and if so
4033 // emit a MULHS instead of the alternate sequence that is valid for any
4034 // i64 x i64 multiply.
4035 if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
4036 // is RH an extension of the sign bit of RL?
4037 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
4038 RH.getOperand(1).getOpcode() == ISD::Constant &&
4039 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
4040 // is LH an extension of the sign bit of LL?
4041 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
4042 LH.getOperand(1).getOpcode() == ISD::Constant &&
4043 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
4044 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
4046 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
4047 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
4048 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
4049 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
4050 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
4052 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4054 Lo = ExpandLibCall("__muldi3" , Node, Hi); break;
4058 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
4059 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
4060 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
4061 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
4064 // Make sure the resultant values have been legalized themselves, unless this
4065 // is a type that requires multi-step expansion.
4066 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
4067 Lo = LegalizeOp(Lo);
4068 Hi = LegalizeOp(Hi);
4071 // Remember in a map if the values will be reused later.
4073 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4074 assert(isNew && "Value already expanded?!?");
4078 // SelectionDAG::Legalize - This is the entry point for the file.
4080 void SelectionDAG::Legalize() {
4081 /// run - This is the main entry point to this class.
4083 SelectionDAGLegalize(*this).Run();