1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Analysis/DebugInfo.h"
15 #include "llvm/CodeGen/Analysis.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineJumpTableInfo.h"
19 #include "llvm/CodeGen/MachineModuleInfo.h"
20 #include "llvm/CodeGen/PseudoSourceValue.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/Target/TargetFrameLowering.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/DerivedTypes.h"
30 #include "llvm/Function.h"
31 #include "llvm/GlobalVariable.h"
32 #include "llvm/LLVMContext.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/ADT/DenseMap.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/ADT/SmallPtrSet.h"
43 //===----------------------------------------------------------------------===//
44 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
45 /// hacks on it until the target machine can handle it. This involves
46 /// eliminating value sizes the machine cannot handle (promoting small sizes to
47 /// large sizes or splitting up large values into small values) as well as
48 /// eliminating operations the machine cannot handle.
50 /// This code also does a small amount of optimization and recognition of idioms
51 /// as part of its processing. For example, if a target does not support a
52 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
53 /// will attempt merge setcc and brc instructions into brcc's.
56 class SelectionDAGLegalize {
57 const TargetMachine &TM;
58 const TargetLowering &TLI;
60 CodeGenOpt::Level OptLevel;
62 // Libcall insertion helpers.
64 /// LastCALLSEQ - This keeps track of the CALLSEQ_END node that has been
65 /// legalized. We use this to ensure that calls are properly serialized
66 /// against each other, including inserted libcalls.
67 SmallVector<SDValue, 8> LastCALLSEQ;
70 Legal, // The target natively supports this operation.
71 Promote, // This operation should be executed in a larger type.
72 Expand // Try to expand this to other ops, otherwise use a libcall.
75 /// ValueTypeActions - This is a bitvector that contains two bits for each
76 /// value type, where the two bits correspond to the LegalizeAction enum.
77 /// This can be queried with "getTypeAction(VT)".
78 TargetLowering::ValueTypeActionImpl ValueTypeActions;
80 /// LegalizedNodes - For nodes that are of legal width, and that have more
81 /// than one use, this map indicates what regularized operand to use. This
82 /// allows us to avoid legalizing the same thing more than once.
83 DenseMap<SDValue, SDValue> LegalizedNodes;
85 void AddLegalizedOperand(SDValue From, SDValue To) {
86 LegalizedNodes.insert(std::make_pair(From, To));
87 // If someone requests legalization of the new node, return itself.
89 LegalizedNodes.insert(std::make_pair(To, To));
91 // Transfer SDDbgValues.
92 DAG.TransferDbgValues(From, To);
96 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol);
98 /// getTypeAction - Return how we should legalize values of this type, either
99 /// it is already legal or we need to expand it into multiple registers of
100 /// smaller integer type, or we need to promote it to a larger type.
101 LegalizeAction getTypeAction(EVT VT) const {
102 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
105 /// isTypeLegal - Return true if this type is legal on this target.
107 bool isTypeLegal(EVT VT) const {
108 return getTypeAction(VT) == Legal;
114 /// LegalizeOp - We know that the specified value has a legal type.
115 /// Recursively ensure that the operands have legal types, then return the
117 SDValue LegalizeOp(SDValue O);
119 SDValue OptimizeFloatStore(StoreSDNode *ST);
121 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
122 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
123 /// is necessary to spill the vector being inserted into to memory, perform
124 /// the insert there, and then read the result back.
125 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
126 SDValue Idx, DebugLoc dl);
127 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
128 SDValue Idx, DebugLoc dl);
130 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
131 /// performs the same shuffe in terms of order or result bytes, but on a type
132 /// whose vector element type is narrower than the original shuffle type.
133 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
134 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
135 SDValue N1, SDValue N2,
136 SmallVectorImpl<int> &Mask) const;
138 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
139 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
141 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
144 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
145 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
146 SDNode *Node, bool isSigned);
147 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
148 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
149 RTLIB::Libcall Call_PPCF128);
150 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
151 RTLIB::Libcall Call_I8,
152 RTLIB::Libcall Call_I16,
153 RTLIB::Libcall Call_I32,
154 RTLIB::Libcall Call_I64,
155 RTLIB::Libcall Call_I128);
156 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
158 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
159 SDValue ExpandBUILD_VECTOR(SDNode *Node);
160 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
161 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
162 SmallVectorImpl<SDValue> &Results);
163 SDValue ExpandFCOPYSIGN(SDNode *Node);
164 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
166 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
168 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
171 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
172 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
174 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
175 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
176 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
178 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
180 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
181 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
183 SDValue getLastCALLSEQ() { return LastCALLSEQ.back(); }
184 void setLastCALLSEQ(const SDValue s) { LastCALLSEQ.back() = s; }
185 void pushLastCALLSEQ(SDValue s) {
186 LastCALLSEQ.push_back(s);
188 void popLastCALLSEQ() {
189 LastCALLSEQ.pop_back();
194 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
195 /// performs the same shuffe in terms of order or result bytes, but on a type
196 /// whose vector element type is narrower than the original shuffle type.
197 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
199 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
200 SDValue N1, SDValue N2,
201 SmallVectorImpl<int> &Mask) const {
202 unsigned NumMaskElts = VT.getVectorNumElements();
203 unsigned NumDestElts = NVT.getVectorNumElements();
204 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
206 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
208 if (NumEltsGrowth == 1)
209 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
211 SmallVector<int, 8> NewMask;
212 for (unsigned i = 0; i != NumMaskElts; ++i) {
214 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
216 NewMask.push_back(-1);
218 NewMask.push_back(Idx * NumEltsGrowth + j);
221 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
222 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
223 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
226 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
227 CodeGenOpt::Level ol)
228 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
229 DAG(dag), OptLevel(ol),
230 ValueTypeActions(TLI.getValueTypeActions()) {
231 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
232 "Too many value types for ValueTypeActions to hold!");
235 void SelectionDAGLegalize::LegalizeDAG() {
236 pushLastCALLSEQ(DAG.getEntryNode());
238 // The legalize process is inherently a bottom-up recursive process (users
239 // legalize their uses before themselves). Given infinite stack space, we
240 // could just start legalizing on the root and traverse the whole graph. In
241 // practice however, this causes us to run out of stack space on large basic
242 // blocks. To avoid this problem, compute an ordering of the nodes where each
243 // node is only legalized after all of its operands are legalized.
244 DAG.AssignTopologicalOrder();
245 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
246 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
247 LegalizeOp(SDValue(I, 0));
249 // Finally, it's possible the root changed. Get the new root.
250 SDValue OldRoot = DAG.getRoot();
251 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
252 DAG.setRoot(LegalizedNodes[OldRoot]);
254 LegalizedNodes.clear();
256 // Remove dead nodes now.
257 DAG.RemoveDeadNodes();
261 /// FindCallEndFromCallStart - Given a chained node that is part of a call
262 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
263 static SDNode *FindCallEndFromCallStart(SDNode *Node, int depth = 0) {
264 int next_depth = depth;
265 if (Node->getOpcode() == ISD::CALLSEQ_START)
266 next_depth = depth + 1;
267 if (Node->getOpcode() == ISD::CALLSEQ_END) {
268 assert(depth > 0 && "negative depth!");
272 next_depth = depth - 1;
274 if (Node->use_empty())
275 return 0; // No CallSeqEnd
277 // The chain is usually at the end.
278 SDValue TheChain(Node, Node->getNumValues()-1);
279 if (TheChain.getValueType() != MVT::Other) {
280 // Sometimes it's at the beginning.
281 TheChain = SDValue(Node, 0);
282 if (TheChain.getValueType() != MVT::Other) {
283 // Otherwise, hunt for it.
284 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
285 if (Node->getValueType(i) == MVT::Other) {
286 TheChain = SDValue(Node, i);
290 // Otherwise, we walked into a node without a chain.
291 if (TheChain.getValueType() != MVT::Other)
296 for (SDNode::use_iterator UI = Node->use_begin(),
297 E = Node->use_end(); UI != E; ++UI) {
299 // Make sure to only follow users of our token chain.
301 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
302 if (User->getOperand(i) == TheChain)
303 if (SDNode *Result = FindCallEndFromCallStart(User, next_depth))
309 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
310 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
311 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
313 assert(Node && "Didn't find callseq_start for a call??");
314 while (Node->getOpcode() != ISD::CALLSEQ_START || nested) {
315 Node = Node->getOperand(0).getNode();
316 assert(Node->getOperand(0).getValueType() == MVT::Other &&
317 "Node doesn't have a token chain argument!");
318 switch (Node->getOpcode()) {
321 case ISD::CALLSEQ_START:
326 case ISD::CALLSEQ_END:
334 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
335 /// see if any uses can reach Dest. If no dest operands can get to dest,
336 /// legalize them, legalize ourself, and return false, otherwise, return true.
338 /// Keep track of the nodes we fine that actually do lead to Dest in
339 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
341 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
342 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
343 if (N == Dest) return true; // N certainly leads to Dest :)
345 // If we've already processed this node and it does lead to Dest, there is no
346 // need to reprocess it.
347 if (NodesLeadingTo.count(N)) return true;
349 // If the first result of this node has been already legalized, then it cannot
351 if (LegalizedNodes.count(SDValue(N, 0))) return false;
353 // Okay, this node has not already been legalized. Check and legalize all
354 // operands. If none lead to Dest, then we can legalize this node.
355 bool OperandsLeadToDest = false;
356 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
357 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
358 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest,
361 if (OperandsLeadToDest) {
362 NodesLeadingTo.insert(N);
366 // Okay, this node looks safe, legalize it and return false.
367 LegalizeOp(SDValue(N, 0));
371 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
372 /// a load from the constant pool.
373 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
374 SelectionDAG &DAG, const TargetLowering &TLI) {
376 DebugLoc dl = CFP->getDebugLoc();
378 // If a FP immediate is precise when represented as a float and if the
379 // target can do an extending load from float to double, we put it into
380 // the constant pool as a float, even if it's is statically typed as a
381 // double. This shrinks FP constants and canonicalizes them for targets where
382 // an FP extending load is the same cost as a normal load (such as on the x87
383 // fp stack or PPC FP unit).
384 EVT VT = CFP->getValueType(0);
385 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
387 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
388 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
389 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
394 while (SVT != MVT::f32) {
395 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
396 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
397 // Only do this if the target has a native EXTLOAD instruction from
399 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
400 TLI.ShouldShrinkFPConstant(OrigVT)) {
401 const Type *SType = SVT.getTypeForEVT(*DAG.getContext());
402 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
408 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
409 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
411 return DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
413 CPIdx, MachinePointerInfo::getConstantPool(),
414 VT, false, false, Alignment);
415 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
416 MachinePointerInfo::getConstantPool(), false, false,
420 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
422 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
423 const TargetLowering &TLI) {
424 SDValue Chain = ST->getChain();
425 SDValue Ptr = ST->getBasePtr();
426 SDValue Val = ST->getValue();
427 EVT VT = Val.getValueType();
428 int Alignment = ST->getAlignment();
429 DebugLoc dl = ST->getDebugLoc();
430 if (ST->getMemoryVT().isFloatingPoint() ||
431 ST->getMemoryVT().isVector()) {
432 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
433 if (TLI.isTypeLegal(intVT)) {
434 // Expand to a bitconvert of the value to the integer type of the
435 // same size, then a (misaligned) int store.
436 // FIXME: Does not handle truncating floating point stores!
437 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
438 return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
439 ST->isVolatile(), ST->isNonTemporal(), Alignment);
441 // Do a (aligned) store to a stack slot, then copy from the stack slot
442 // to the final destination using (unaligned) integer loads and stores.
443 EVT StoredVT = ST->getMemoryVT();
445 TLI.getRegisterType(*DAG.getContext(),
446 EVT::getIntegerVT(*DAG.getContext(),
447 StoredVT.getSizeInBits()));
448 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
449 unsigned RegBytes = RegVT.getSizeInBits() / 8;
450 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
452 // Make sure the stack slot is also aligned for the register type.
453 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
455 // Perform the original store, only redirected to the stack slot.
456 SDValue Store = DAG.getTruncStore(Chain, dl,
457 Val, StackPtr, MachinePointerInfo(),
458 StoredVT, false, false, 0);
459 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
460 SmallVector<SDValue, 8> Stores;
463 // Do all but one copies using the full register width.
464 for (unsigned i = 1; i < NumRegs; i++) {
465 // Load one integer register's worth from the stack slot.
466 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
467 MachinePointerInfo(),
469 // Store it to the final location. Remember the store.
470 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
471 ST->getPointerInfo().getWithOffset(Offset),
472 ST->isVolatile(), ST->isNonTemporal(),
473 MinAlign(ST->getAlignment(), Offset)));
474 // Increment the pointers.
476 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
478 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
481 // The last store may be partial. Do a truncating store. On big-endian
482 // machines this requires an extending load from the stack slot to ensure
483 // that the bits are in the right place.
484 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
485 8 * (StoredBytes - Offset));
487 // Load from the stack slot.
488 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
489 MachinePointerInfo(),
490 MemVT, false, false, 0);
492 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
494 .getWithOffset(Offset),
495 MemVT, ST->isVolatile(),
497 MinAlign(ST->getAlignment(), Offset)));
498 // The order of the stores doesn't matter - say it with a TokenFactor.
499 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
503 assert(ST->getMemoryVT().isInteger() &&
504 !ST->getMemoryVT().isVector() &&
505 "Unaligned store of unknown type.");
506 // Get the half-size VT
507 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
508 int NumBits = NewStoredVT.getSizeInBits();
509 int IncrementSize = NumBits / 8;
511 // Divide the stored value in two parts.
512 SDValue ShiftAmount = DAG.getConstant(NumBits,
513 TLI.getShiftAmountTy(Val.getValueType()));
515 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
517 // Store the two parts
518 SDValue Store1, Store2;
519 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
520 ST->getPointerInfo(), NewStoredVT,
521 ST->isVolatile(), ST->isNonTemporal(), Alignment);
522 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
523 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
524 Alignment = MinAlign(Alignment, IncrementSize);
525 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
526 ST->getPointerInfo().getWithOffset(IncrementSize),
527 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
530 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
533 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
535 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
536 const TargetLowering &TLI) {
537 SDValue Chain = LD->getChain();
538 SDValue Ptr = LD->getBasePtr();
539 EVT VT = LD->getValueType(0);
540 EVT LoadedVT = LD->getMemoryVT();
541 DebugLoc dl = LD->getDebugLoc();
542 if (VT.isFloatingPoint() || VT.isVector()) {
543 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
544 if (TLI.isTypeLegal(intVT)) {
545 // Expand to a (misaligned) integer load of the same size,
546 // then bitconvert to floating point or vector.
547 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
549 LD->isNonTemporal(), LD->getAlignment());
550 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
551 if (VT.isFloatingPoint() && LoadedVT != VT)
552 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
554 SDValue Ops[] = { Result, Chain };
555 return DAG.getMergeValues(Ops, 2, dl);
558 // Copy the value to a (aligned) stack slot using (unaligned) integer
559 // loads and stores, then do a (aligned) load from the stack slot.
560 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
561 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
562 unsigned RegBytes = RegVT.getSizeInBits() / 8;
563 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
565 // Make sure the stack slot is also aligned for the register type.
566 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
568 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
569 SmallVector<SDValue, 8> Stores;
570 SDValue StackPtr = StackBase;
573 // Do all but one copies using the full register width.
574 for (unsigned i = 1; i < NumRegs; i++) {
575 // Load one integer register's worth from the original location.
576 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
577 LD->getPointerInfo().getWithOffset(Offset),
578 LD->isVolatile(), LD->isNonTemporal(),
579 MinAlign(LD->getAlignment(), Offset));
580 // Follow the load with a store to the stack slot. Remember the store.
581 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
582 MachinePointerInfo(), false, false, 0));
583 // Increment the pointers.
585 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
586 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
590 // The last copy may be partial. Do an extending load.
591 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
592 8 * (LoadedBytes - Offset));
593 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
594 LD->getPointerInfo().getWithOffset(Offset),
595 MemVT, LD->isVolatile(),
597 MinAlign(LD->getAlignment(), Offset));
598 // Follow the load with a store to the stack slot. Remember the store.
599 // On big-endian machines this requires a truncating store to ensure
600 // that the bits end up in the right place.
601 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
602 MachinePointerInfo(), MemVT,
605 // The order of the stores doesn't matter - say it with a TokenFactor.
606 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
609 // Finally, perform the original load only redirected to the stack slot.
610 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
611 MachinePointerInfo(), LoadedVT, false, false, 0);
613 // Callers expect a MERGE_VALUES node.
614 SDValue Ops[] = { Load, TF };
615 return DAG.getMergeValues(Ops, 2, dl);
617 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
618 "Unaligned load of unsupported type.");
620 // Compute the new VT that is half the size of the old one. This is an
622 unsigned NumBits = LoadedVT.getSizeInBits();
624 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
627 unsigned Alignment = LD->getAlignment();
628 unsigned IncrementSize = NumBits / 8;
629 ISD::LoadExtType HiExtType = LD->getExtensionType();
631 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
632 if (HiExtType == ISD::NON_EXTLOAD)
633 HiExtType = ISD::ZEXTLOAD;
635 // Load the value in two parts
637 if (TLI.isLittleEndian()) {
638 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
639 NewLoadedVT, LD->isVolatile(),
640 LD->isNonTemporal(), Alignment);
641 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
642 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
643 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
644 LD->getPointerInfo().getWithOffset(IncrementSize),
645 NewLoadedVT, LD->isVolatile(),
646 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
648 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
649 NewLoadedVT, LD->isVolatile(),
650 LD->isNonTemporal(), Alignment);
651 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
652 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
653 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
654 LD->getPointerInfo().getWithOffset(IncrementSize),
655 NewLoadedVT, LD->isVolatile(),
656 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
659 // aggregate the two parts
660 SDValue ShiftAmount = DAG.getConstant(NumBits,
661 TLI.getShiftAmountTy(Hi.getValueType()));
662 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
663 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
665 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
668 SDValue Ops[] = { Result, TF };
669 return DAG.getMergeValues(Ops, 2, dl);
672 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
673 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
674 /// is necessary to spill the vector being inserted into to memory, perform
675 /// the insert there, and then read the result back.
676 SDValue SelectionDAGLegalize::
677 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
683 // If the target doesn't support this, we have to spill the input vector
684 // to a temporary stack slot, update the element, then reload it. This is
685 // badness. We could also load the value into a vector register (either
686 // with a "move to register" or "extload into register" instruction, then
687 // permute it into place, if the idx is a constant and if the idx is
688 // supported by the target.
689 EVT VT = Tmp1.getValueType();
690 EVT EltVT = VT.getVectorElementType();
691 EVT IdxVT = Tmp3.getValueType();
692 EVT PtrVT = TLI.getPointerTy();
693 SDValue StackPtr = DAG.CreateStackTemporary(VT);
695 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
698 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
699 MachinePointerInfo::getFixedStack(SPFI),
702 // Truncate or zero extend offset to target pointer type.
703 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
704 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
705 // Add the offset to the index.
706 unsigned EltSize = EltVT.getSizeInBits()/8;
707 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
708 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
709 // Store the scalar value.
710 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
712 // Load the updated vector.
713 return DAG.getLoad(VT, dl, Ch, StackPtr,
714 MachinePointerInfo::getFixedStack(SPFI), false, false, 0);
718 SDValue SelectionDAGLegalize::
719 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
720 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
721 // SCALAR_TO_VECTOR requires that the type of the value being inserted
722 // match the element type of the vector being created, except for
723 // integers in which case the inserted value can be over width.
724 EVT EltVT = Vec.getValueType().getVectorElementType();
725 if (Val.getValueType() == EltVT ||
726 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
727 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
728 Vec.getValueType(), Val);
730 unsigned NumElts = Vec.getValueType().getVectorNumElements();
731 // We generate a shuffle of InVec and ScVec, so the shuffle mask
732 // should be 0,1,2,3,4,5... with the appropriate element replaced with
734 SmallVector<int, 8> ShufOps;
735 for (unsigned i = 0; i != NumElts; ++i)
736 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
738 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
742 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
745 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
746 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
747 // FIXME: We shouldn't do this for TargetConstantFP's.
748 // FIXME: move this to the DAG Combiner! Note that we can't regress due
749 // to phase ordering between legalized code and the dag combiner. This
750 // probably means that we need to integrate dag combiner and legalizer
752 // We generally can't do this one for long doubles.
753 SDValue Tmp1 = ST->getChain();
754 SDValue Tmp2 = ST->getBasePtr();
756 unsigned Alignment = ST->getAlignment();
757 bool isVolatile = ST->isVolatile();
758 bool isNonTemporal = ST->isNonTemporal();
759 DebugLoc dl = ST->getDebugLoc();
760 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
761 if (CFP->getValueType(0) == MVT::f32 &&
762 getTypeAction(MVT::i32) == Legal) {
763 Tmp3 = DAG.getConstant(CFP->getValueAPF().
764 bitcastToAPInt().zextOrTrunc(32),
766 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
767 isVolatile, isNonTemporal, Alignment);
770 if (CFP->getValueType(0) == MVT::f64) {
771 // If this target supports 64-bit registers, do a single 64-bit store.
772 if (getTypeAction(MVT::i64) == Legal) {
773 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
774 zextOrTrunc(64), MVT::i64);
775 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
776 isVolatile, isNonTemporal, Alignment);
779 if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
780 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
781 // stores. If the target supports neither 32- nor 64-bits, this
782 // xform is certainly not worth it.
783 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
784 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
785 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
786 if (TLI.isBigEndian()) std::swap(Lo, Hi);
788 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getPointerInfo(), isVolatile,
789 isNonTemporal, Alignment);
790 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
791 DAG.getIntPtrConstant(4));
792 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2,
793 ST->getPointerInfo().getWithOffset(4),
794 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
796 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
800 return SDValue(0, 0);
803 /// LegalizeOp - We know that the specified value has a legal type, and
804 /// that its operands are legal. Now ensure that the operation itself
805 /// is legal, recursively ensuring that the operands' operations remain
807 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
808 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
811 SDNode *Node = Op.getNode();
812 DebugLoc dl = Node->getDebugLoc();
814 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
815 assert(getTypeAction(Node->getValueType(i)) == Legal &&
816 "Unexpected illegal type!");
818 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
819 assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
820 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
821 "Unexpected illegal type!");
823 // Note that LegalizeOp may be reentered even from single-use nodes, which
824 // means that we always must cache transformed nodes.
825 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
826 if (I != LegalizedNodes.end()) return I->second;
828 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
830 bool isCustom = false;
832 // Figure out the correct action; the way to query this varies by opcode
833 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
834 bool SimpleFinishLegalizing = true;
835 switch (Node->getOpcode()) {
836 case ISD::INTRINSIC_W_CHAIN:
837 case ISD::INTRINSIC_WO_CHAIN:
838 case ISD::INTRINSIC_VOID:
841 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
843 case ISD::SINT_TO_FP:
844 case ISD::UINT_TO_FP:
845 case ISD::EXTRACT_VECTOR_ELT:
846 Action = TLI.getOperationAction(Node->getOpcode(),
847 Node->getOperand(0).getValueType());
849 case ISD::FP_ROUND_INREG:
850 case ISD::SIGN_EXTEND_INREG: {
851 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
852 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
858 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
859 Node->getOpcode() == ISD::SETCC ? 2 : 1;
860 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
861 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
862 ISD::CondCode CCCode =
863 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
864 Action = TLI.getCondCodeAction(CCCode, OpVT);
865 if (Action == TargetLowering::Legal) {
866 if (Node->getOpcode() == ISD::SELECT_CC)
867 Action = TLI.getOperationAction(Node->getOpcode(),
868 Node->getValueType(0));
870 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
876 // FIXME: Model these properly. LOAD and STORE are complicated, and
877 // STORE expects the unlegalized operand in some cases.
878 SimpleFinishLegalizing = false;
880 case ISD::CALLSEQ_START:
881 case ISD::CALLSEQ_END:
882 // FIXME: This shouldn't be necessary. These nodes have special properties
883 // dealing with the recursive nature of legalization. Removing this
884 // special case should be done as part of making LegalizeDAG non-recursive.
885 SimpleFinishLegalizing = false;
887 case ISD::EXTRACT_ELEMENT:
888 case ISD::FLT_ROUNDS_:
896 case ISD::MERGE_VALUES:
898 case ISD::FRAME_TO_ARGS_OFFSET:
899 case ISD::EH_SJLJ_SETJMP:
900 case ISD::EH_SJLJ_LONGJMP:
901 case ISD::EH_SJLJ_DISPATCHSETUP:
902 // These operations lie about being legal: when they claim to be legal,
903 // they should actually be expanded.
904 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
905 if (Action == TargetLowering::Legal)
906 Action = TargetLowering::Expand;
908 case ISD::TRAMPOLINE:
910 case ISD::RETURNADDR:
911 // These operations lie about being legal: when they claim to be legal,
912 // they should actually be custom-lowered.
913 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
914 if (Action == TargetLowering::Legal)
915 Action = TargetLowering::Custom;
917 case ISD::BUILD_VECTOR:
918 // A weird case: legalization for BUILD_VECTOR never legalizes the
920 // FIXME: This really sucks... changing it isn't semantically incorrect,
921 // but it massively pessimizes the code for floating-point BUILD_VECTORs
922 // because ConstantFP operands get legalized into constant pool loads
923 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
924 // though, because BUILD_VECTORS usually get lowered into other nodes
925 // which get legalized properly.
926 SimpleFinishLegalizing = false;
929 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
930 Action = TargetLowering::Legal;
932 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
937 if (SimpleFinishLegalizing) {
938 SmallVector<SDValue, 8> Ops, ResultVals;
939 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
940 Ops.push_back(LegalizeOp(Node->getOperand(i)));
941 switch (Node->getOpcode()) {
948 assert(LastCALLSEQ.size() == 1 && "branch inside CALLSEQ_BEGIN/END?");
949 // Branches tweak the chain to include LastCALLSEQ
950 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
952 Ops[0] = LegalizeOp(Ops[0]);
953 setLastCALLSEQ(DAG.getEntryNode());
960 // Legalizing shifts/rotates requires adjusting the shift amount
961 // to the appropriate width.
962 if (!Ops[1].getValueType().isVector())
963 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
969 // Legalizing shifts/rotates requires adjusting the shift amount
970 // to the appropriate width.
971 if (!Ops[2].getValueType().isVector())
972 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
977 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(),
980 case TargetLowering::Legal:
981 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
982 ResultVals.push_back(Result.getValue(i));
984 case TargetLowering::Custom:
985 // FIXME: The handling for custom lowering with multiple results is
987 Tmp1 = TLI.LowerOperation(Result, DAG);
988 if (Tmp1.getNode()) {
989 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
991 ResultVals.push_back(Tmp1);
993 ResultVals.push_back(Tmp1.getValue(i));
999 case TargetLowering::Expand:
1000 ExpandNode(Result.getNode(), ResultVals);
1002 case TargetLowering::Promote:
1003 PromoteNode(Result.getNode(), ResultVals);
1006 if (!ResultVals.empty()) {
1007 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
1008 if (ResultVals[i] != SDValue(Node, i))
1009 ResultVals[i] = LegalizeOp(ResultVals[i]);
1010 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
1012 return ResultVals[Op.getResNo()];
1016 switch (Node->getOpcode()) {
1023 assert(0 && "Do not know how to legalize this operator!");
1025 case ISD::BUILD_VECTOR:
1026 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1027 default: assert(0 && "This action is not supported yet!");
1028 case TargetLowering::Custom:
1029 Tmp3 = TLI.LowerOperation(Result, DAG);
1030 if (Tmp3.getNode()) {
1035 case TargetLowering::Expand:
1036 Result = ExpandBUILD_VECTOR(Result.getNode());
1040 case ISD::CALLSEQ_START: {
1041 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1042 assert(CallEnd && "didn't find CALLSEQ_END!");
1044 // Recursively Legalize all of the inputs of the call end that do not lead
1045 // to this call start. This ensures that any libcalls that need be inserted
1046 // are inserted *before* the CALLSEQ_START.
1047 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1048 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1049 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1053 // Now that we have legalized all of the inputs (which may have inserted
1054 // libcalls), create the new CALLSEQ_START node.
1055 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1057 // Merge in the last call to ensure that this call starts after the last
1059 if (getLastCALLSEQ().getOpcode() != ISD::EntryToken) {
1060 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1061 Tmp1, getLastCALLSEQ());
1062 Tmp1 = LegalizeOp(Tmp1);
1065 // Do not try to legalize the target-specific arguments (#1+).
1066 if (Tmp1 != Node->getOperand(0)) {
1067 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1069 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0],
1070 Ops.size()), Result.getResNo());
1073 // Remember that the CALLSEQ_START is legalized.
1074 AddLegalizedOperand(Op.getValue(0), Result);
1075 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1076 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1078 // Now that the callseq_start and all of the non-call nodes above this call
1079 // sequence have been legalized, legalize the call itself. During this
1080 // process, no libcalls can/will be inserted, guaranteeing that no calls
1082 // Note that we are selecting this call!
1083 setLastCALLSEQ(SDValue(CallEnd, 0));
1085 // Legalize the call, starting from the CALLSEQ_END.
1086 LegalizeOp(getLastCALLSEQ());
1089 case ISD::CALLSEQ_END:
1091 SDNode *myCALLSEQ_BEGIN = FindCallStartFromCallEnd(Node);
1093 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1094 // will cause this node to be legalized as well as handling libcalls right.
1095 if (getLastCALLSEQ().getNode() != Node) {
1096 LegalizeOp(SDValue(myCALLSEQ_BEGIN, 0));
1097 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1098 assert(I != LegalizedNodes.end() &&
1099 "Legalizing the call start should have legalized this node!");
1103 pushLastCALLSEQ(SDValue(myCALLSEQ_BEGIN, 0));
1106 // Otherwise, the call start has been legalized and everything is going
1107 // according to plan. Just legalize ourselves normally here.
1108 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1109 // Do not try to legalize the target-specific arguments (#1+), except for
1110 // an optional flag input.
1111 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Glue){
1112 if (Tmp1 != Node->getOperand(0)) {
1113 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1115 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1116 &Ops[0], Ops.size()),
1120 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1121 if (Tmp1 != Node->getOperand(0) ||
1122 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1123 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1126 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1127 &Ops[0], Ops.size()),
1131 // This finishes up call legalization.
1134 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1135 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1136 if (Node->getNumValues() == 2)
1137 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1138 return Result.getValue(Op.getResNo());
1140 LoadSDNode *LD = cast<LoadSDNode>(Node);
1141 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1142 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1144 ISD::LoadExtType ExtType = LD->getExtensionType();
1145 if (ExtType == ISD::NON_EXTLOAD) {
1146 EVT VT = Node->getValueType(0);
1147 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1148 Tmp1, Tmp2, LD->getOffset()),
1150 Tmp3 = Result.getValue(0);
1151 Tmp4 = Result.getValue(1);
1153 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1154 default: assert(0 && "This action is not supported yet!");
1155 case TargetLowering::Legal:
1156 // If this is an unaligned load and the target doesn't support it,
1158 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1159 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1160 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1161 if (LD->getAlignment() < ABIAlignment){
1162 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1164 Tmp3 = Result.getOperand(0);
1165 Tmp4 = Result.getOperand(1);
1166 Tmp3 = LegalizeOp(Tmp3);
1167 Tmp4 = LegalizeOp(Tmp4);
1171 case TargetLowering::Custom:
1172 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1173 if (Tmp1.getNode()) {
1174 Tmp3 = LegalizeOp(Tmp1);
1175 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1178 case TargetLowering::Promote: {
1179 // Only promote a load of vector type to another.
1180 assert(VT.isVector() && "Cannot promote this load!");
1181 // Change base type to a different vector type.
1182 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1184 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
1185 LD->isVolatile(), LD->isNonTemporal(),
1186 LD->getAlignment());
1187 Tmp3 = LegalizeOp(DAG.getNode(ISD::BITCAST, dl, VT, Tmp1));
1188 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1192 // Since loads produce two values, make sure to remember that we
1193 // legalized both of them.
1194 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1195 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1196 return Op.getResNo() ? Tmp4 : Tmp3;
1199 EVT SrcVT = LD->getMemoryVT();
1200 unsigned SrcWidth = SrcVT.getSizeInBits();
1201 unsigned Alignment = LD->getAlignment();
1202 bool isVolatile = LD->isVolatile();
1203 bool isNonTemporal = LD->isNonTemporal();
1205 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1206 // Some targets pretend to have an i1 loading operation, and actually
1207 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1208 // bits are guaranteed to be zero; it helps the optimizers understand
1209 // that these bits are zero. It is also useful for EXTLOAD, since it
1210 // tells the optimizers that those bits are undefined. It would be
1211 // nice to have an effective generic way of getting these benefits...
1212 // Until such a way is found, don't insist on promoting i1 here.
1213 (SrcVT != MVT::i1 ||
1214 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1215 // Promote to a byte-sized load if not loading an integral number of
1216 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1217 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1218 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
1221 // The extra bits are guaranteed to be zero, since we stored them that
1222 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1224 ISD::LoadExtType NewExtType =
1225 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1227 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
1228 Tmp1, Tmp2, LD->getPointerInfo(),
1229 NVT, isVolatile, isNonTemporal, Alignment);
1231 Ch = Result.getValue(1); // The chain.
1233 if (ExtType == ISD::SEXTLOAD)
1234 // Having the top bits zero doesn't help when sign extending.
1235 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1236 Result.getValueType(),
1237 Result, DAG.getValueType(SrcVT));
1238 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1239 // All the top bits are guaranteed to be zero - inform the optimizers.
1240 Result = DAG.getNode(ISD::AssertZext, dl,
1241 Result.getValueType(), Result,
1242 DAG.getValueType(SrcVT));
1244 Tmp1 = LegalizeOp(Result);
1245 Tmp2 = LegalizeOp(Ch);
1246 } else if (SrcWidth & (SrcWidth - 1)) {
1247 // If not loading a power-of-2 number of bits, expand as two loads.
1248 assert(!SrcVT.isVector() && "Unsupported extload!");
1249 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1250 assert(RoundWidth < SrcWidth);
1251 unsigned ExtraWidth = SrcWidth - RoundWidth;
1252 assert(ExtraWidth < RoundWidth);
1253 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1254 "Load size not an integral number of bytes!");
1255 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1256 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1258 unsigned IncrementSize;
1260 if (TLI.isLittleEndian()) {
1261 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1262 // Load the bottom RoundWidth bits.
1263 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1265 LD->getPointerInfo(), RoundVT, isVolatile,
1266 isNonTemporal, Alignment);
1268 // Load the remaining ExtraWidth bits.
1269 IncrementSize = RoundWidth / 8;
1270 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1271 DAG.getIntPtrConstant(IncrementSize));
1272 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1273 LD->getPointerInfo().getWithOffset(IncrementSize),
1274 ExtraVT, isVolatile, isNonTemporal,
1275 MinAlign(Alignment, IncrementSize));
1277 // Build a factor node to remember that this load is independent of
1279 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1282 // Move the top bits to the right place.
1283 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1284 DAG.getConstant(RoundWidth,
1285 TLI.getShiftAmountTy(Hi.getValueType())));
1287 // Join the hi and lo parts.
1288 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1290 // Big endian - avoid unaligned loads.
1291 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1292 // Load the top RoundWidth bits.
1293 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1294 LD->getPointerInfo(), RoundVT, isVolatile,
1295 isNonTemporal, Alignment);
1297 // Load the remaining ExtraWidth bits.
1298 IncrementSize = RoundWidth / 8;
1299 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1300 DAG.getIntPtrConstant(IncrementSize));
1301 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1302 dl, Node->getValueType(0), Tmp1, Tmp2,
1303 LD->getPointerInfo().getWithOffset(IncrementSize),
1304 ExtraVT, isVolatile, isNonTemporal,
1305 MinAlign(Alignment, IncrementSize));
1307 // Build a factor node to remember that this load is independent of
1309 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1312 // Move the top bits to the right place.
1313 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1314 DAG.getConstant(ExtraWidth,
1315 TLI.getShiftAmountTy(Hi.getValueType())));
1317 // Join the hi and lo parts.
1318 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1321 Tmp1 = LegalizeOp(Result);
1322 Tmp2 = LegalizeOp(Ch);
1324 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1325 default: assert(0 && "This action is not supported yet!");
1326 case TargetLowering::Custom:
1329 case TargetLowering::Legal:
1330 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1331 Tmp1, Tmp2, LD->getOffset()),
1333 Tmp1 = Result.getValue(0);
1334 Tmp2 = Result.getValue(1);
1337 Tmp3 = TLI.LowerOperation(Result, DAG);
1338 if (Tmp3.getNode()) {
1339 Tmp1 = LegalizeOp(Tmp3);
1340 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1343 // If this is an unaligned load and the target doesn't support it,
1345 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1347 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1348 unsigned ABIAlignment =
1349 TLI.getTargetData()->getABITypeAlignment(Ty);
1350 if (LD->getAlignment() < ABIAlignment){
1351 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1353 Tmp1 = Result.getOperand(0);
1354 Tmp2 = Result.getOperand(1);
1355 Tmp1 = LegalizeOp(Tmp1);
1356 Tmp2 = LegalizeOp(Tmp2);
1361 case TargetLowering::Expand:
1362 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && isTypeLegal(SrcVT)) {
1363 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2,
1364 LD->getPointerInfo(),
1365 LD->isVolatile(), LD->isNonTemporal(),
1366 LD->getAlignment());
1370 ExtendOp = (SrcVT.isFloatingPoint() ?
1371 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1373 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1374 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1375 default: llvm_unreachable("Unexpected extend load type!");
1377 Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1378 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1379 Tmp2 = LegalizeOp(Load.getValue(1));
1382 // FIXME: This does not work for vectors on most targets. Sign- and
1383 // zero-extend operations are currently folded into extending loads,
1384 // whether they are legal or not, and then we end up here without any
1385 // support for legalizing them.
1386 assert(ExtType != ISD::EXTLOAD &&
1387 "EXTLOAD should always be supported!");
1388 // Turn the unsupported load into an EXTLOAD followed by an explicit
1389 // zero/sign extend inreg.
1390 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1391 Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
1392 LD->isVolatile(), LD->isNonTemporal(),
1393 LD->getAlignment());
1395 if (ExtType == ISD::SEXTLOAD)
1396 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1397 Result.getValueType(),
1398 Result, DAG.getValueType(SrcVT));
1400 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1401 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1402 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1407 // Since loads produce two values, make sure to remember that we legalized
1409 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1410 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1411 return Op.getResNo() ? Tmp2 : Tmp1;
1414 StoreSDNode *ST = cast<StoreSDNode>(Node);
1415 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1416 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1417 unsigned Alignment = ST->getAlignment();
1418 bool isVolatile = ST->isVolatile();
1419 bool isNonTemporal = ST->isNonTemporal();
1421 if (!ST->isTruncatingStore()) {
1422 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1423 Result = SDValue(OptStore, 0);
1428 Tmp3 = LegalizeOp(ST->getValue());
1429 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1434 EVT VT = Tmp3.getValueType();
1435 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1436 default: assert(0 && "This action is not supported yet!");
1437 case TargetLowering::Legal:
1438 // If this is an unaligned store and the target doesn't support it,
1440 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1441 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1442 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1443 if (ST->getAlignment() < ABIAlignment)
1444 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1448 case TargetLowering::Custom:
1449 Tmp1 = TLI.LowerOperation(Result, DAG);
1450 if (Tmp1.getNode()) Result = Tmp1;
1452 case TargetLowering::Promote:
1453 assert(VT.isVector() && "Unknown legal promote case!");
1454 Tmp3 = DAG.getNode(ISD::BITCAST, dl,
1455 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1456 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1457 ST->getPointerInfo(), isVolatile,
1458 isNonTemporal, Alignment);
1464 Tmp3 = LegalizeOp(ST->getValue());
1466 EVT StVT = ST->getMemoryVT();
1467 unsigned StWidth = StVT.getSizeInBits();
1469 if (StWidth != StVT.getStoreSizeInBits()) {
1470 // Promote to a byte-sized store with upper bits zero if not
1471 // storing an integral number of bytes. For example, promote
1472 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1473 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
1474 StVT.getStoreSizeInBits());
1475 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1476 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1477 NVT, isVolatile, isNonTemporal, Alignment);
1478 } else if (StWidth & (StWidth - 1)) {
1479 // If not storing a power-of-2 number of bits, expand as two stores.
1480 assert(!StVT.isVector() && "Unsupported truncstore!");
1481 unsigned RoundWidth = 1 << Log2_32(StWidth);
1482 assert(RoundWidth < StWidth);
1483 unsigned ExtraWidth = StWidth - RoundWidth;
1484 assert(ExtraWidth < RoundWidth);
1485 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1486 "Store size not an integral number of bytes!");
1487 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1488 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1490 unsigned IncrementSize;
1492 if (TLI.isLittleEndian()) {
1493 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1494 // Store the bottom RoundWidth bits.
1495 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1497 isVolatile, isNonTemporal, Alignment);
1499 // Store the remaining ExtraWidth bits.
1500 IncrementSize = RoundWidth / 8;
1501 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1502 DAG.getIntPtrConstant(IncrementSize));
1503 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1504 DAG.getConstant(RoundWidth,
1505 TLI.getShiftAmountTy(Tmp3.getValueType())));
1506 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2,
1507 ST->getPointerInfo().getWithOffset(IncrementSize),
1508 ExtraVT, isVolatile, isNonTemporal,
1509 MinAlign(Alignment, IncrementSize));
1511 // Big endian - avoid unaligned stores.
1512 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1513 // Store the top RoundWidth bits.
1514 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1515 DAG.getConstant(ExtraWidth,
1516 TLI.getShiftAmountTy(Tmp3.getValueType())));
1517 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(),
1518 RoundVT, isVolatile, isNonTemporal, Alignment);
1520 // Store the remaining ExtraWidth bits.
1521 IncrementSize = RoundWidth / 8;
1522 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1523 DAG.getIntPtrConstant(IncrementSize));
1524 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
1525 ST->getPointerInfo().getWithOffset(IncrementSize),
1526 ExtraVT, isVolatile, isNonTemporal,
1527 MinAlign(Alignment, IncrementSize));
1530 // The order of the stores doesn't matter.
1531 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1533 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1534 Tmp2 != ST->getBasePtr())
1535 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1540 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1541 default: assert(0 && "This action is not supported yet!");
1542 case TargetLowering::Legal:
1543 // If this is an unaligned store and the target doesn't support it,
1545 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1546 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1547 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1548 if (ST->getAlignment() < ABIAlignment)
1549 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1553 case TargetLowering::Custom:
1554 Result = TLI.LowerOperation(Result, DAG);
1557 // TRUNCSTORE:i16 i32 -> STORE i16
1558 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
1559 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1560 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1561 isVolatile, isNonTemporal, Alignment);
1569 assert(Result.getValueType() == Op.getValueType() &&
1570 "Bad legalization!");
1572 // Make sure that the generated code is itself legal.
1574 Result = LegalizeOp(Result);
1576 // Note that LegalizeOp may be reentered even from single-use nodes, which
1577 // means that we always must cache transformed nodes.
1578 AddLegalizedOperand(Op, Result);
1582 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1583 SDValue Vec = Op.getOperand(0);
1584 SDValue Idx = Op.getOperand(1);
1585 DebugLoc dl = Op.getDebugLoc();
1586 // Store the value to a temporary stack slot, then LOAD the returned part.
1587 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1588 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1589 MachinePointerInfo(), false, false, 0);
1591 // Add the offset to the index.
1593 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1594 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1595 DAG.getConstant(EltSize, Idx.getValueType()));
1597 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1598 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1600 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1602 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1604 if (Op.getValueType().isVector())
1605 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1607 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1608 MachinePointerInfo(),
1609 Vec.getValueType().getVectorElementType(),
1613 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1614 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1616 SDValue Vec = Op.getOperand(0);
1617 SDValue Part = Op.getOperand(1);
1618 SDValue Idx = Op.getOperand(2);
1619 DebugLoc dl = Op.getDebugLoc();
1621 // Store the value to a temporary stack slot, then LOAD the returned part.
1623 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1624 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1625 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1627 // First store the whole vector.
1628 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1631 // Then store the inserted part.
1633 // Add the offset to the index.
1635 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1637 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1638 DAG.getConstant(EltSize, Idx.getValueType()));
1640 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1641 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1643 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1645 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1648 // Store the subvector.
1649 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1650 MachinePointerInfo(), false, false, 0);
1652 // Finally, load the updated vector.
1653 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1657 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1658 // We can't handle this case efficiently. Allocate a sufficiently
1659 // aligned object on the stack, store each element into it, then load
1660 // the result as a vector.
1661 // Create the stack frame object.
1662 EVT VT = Node->getValueType(0);
1663 EVT EltVT = VT.getVectorElementType();
1664 DebugLoc dl = Node->getDebugLoc();
1665 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1666 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1667 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1669 // Emit a store of each element to the stack slot.
1670 SmallVector<SDValue, 8> Stores;
1671 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1672 // Store (in the right endianness) the elements to memory.
1673 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1674 // Ignore undef elements.
1675 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1677 unsigned Offset = TypeByteSize*i;
1679 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1680 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1682 // If the destination vector element type is narrower than the source
1683 // element type, only store the bits necessary.
1684 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1685 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1686 Node->getOperand(i), Idx,
1687 PtrInfo.getWithOffset(Offset),
1688 EltVT, false, false, 0));
1690 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1691 Node->getOperand(i), Idx,
1692 PtrInfo.getWithOffset(Offset),
1697 if (!Stores.empty()) // Not all undef elements?
1698 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1699 &Stores[0], Stores.size());
1701 StoreChain = DAG.getEntryNode();
1703 // Result is a load from the stack slot.
1704 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, false, false, 0);
1707 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1708 DebugLoc dl = Node->getDebugLoc();
1709 SDValue Tmp1 = Node->getOperand(0);
1710 SDValue Tmp2 = Node->getOperand(1);
1712 // Get the sign bit of the RHS. First obtain a value that has the same
1713 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1715 EVT FloatVT = Tmp2.getValueType();
1716 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1717 if (isTypeLegal(IVT)) {
1718 // Convert to an integer with the same sign bit.
1719 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1721 // Store the float to memory, then load the sign part out as an integer.
1722 MVT LoadTy = TLI.getPointerTy();
1723 // First create a temporary that is aligned for both the load and store.
1724 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1725 // Then store the float to it.
1727 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1729 if (TLI.isBigEndian()) {
1730 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1731 // Load out a legal integer with the same sign bit as the float.
1732 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1734 } else { // Little endian
1735 SDValue LoadPtr = StackPtr;
1736 // The float may be wider than the integer we are going to load. Advance
1737 // the pointer so that the loaded integer will contain the sign bit.
1738 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1739 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1740 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1741 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1742 // Load a legal integer containing the sign bit.
1743 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1745 // Move the sign bit to the top bit of the loaded integer.
1746 unsigned BitShift = LoadTy.getSizeInBits() -
1747 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1748 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1750 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1751 DAG.getConstant(BitShift,
1752 TLI.getShiftAmountTy(SignBit.getValueType())));
1755 // Now get the sign bit proper, by seeing whether the value is negative.
1756 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1757 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1759 // Get the absolute value of the result.
1760 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1761 // Select between the nabs and abs value based on the sign bit of
1763 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1764 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1768 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1769 SmallVectorImpl<SDValue> &Results) {
1770 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1771 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1772 " not tell us which reg is the stack pointer!");
1773 DebugLoc dl = Node->getDebugLoc();
1774 EVT VT = Node->getValueType(0);
1775 SDValue Tmp1 = SDValue(Node, 0);
1776 SDValue Tmp2 = SDValue(Node, 1);
1777 SDValue Tmp3 = Node->getOperand(2);
1778 SDValue Chain = Tmp1.getOperand(0);
1780 // Chain the dynamic stack allocation so that it doesn't modify the stack
1781 // pointer when other instructions are using the stack.
1782 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1784 SDValue Size = Tmp2.getOperand(1);
1785 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1786 Chain = SP.getValue(1);
1787 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1788 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1789 if (Align > StackAlign)
1790 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1791 DAG.getConstant(-(uint64_t)Align, VT));
1792 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1793 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1795 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1796 DAG.getIntPtrConstant(0, true), SDValue());
1798 Results.push_back(Tmp1);
1799 Results.push_back(Tmp2);
1802 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1803 /// condition code CC on the current target. This routine expands SETCC with
1804 /// illegal condition code into AND / OR of multiple SETCC values.
1805 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1806 SDValue &LHS, SDValue &RHS,
1809 EVT OpVT = LHS.getValueType();
1810 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1811 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1812 default: assert(0 && "Unknown condition code action!");
1813 case TargetLowering::Legal:
1816 case TargetLowering::Expand: {
1817 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1820 default: assert(0 && "Don't know how to expand this condition!");
1821 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1822 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1823 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1824 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1825 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1826 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1827 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1828 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1829 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1830 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1831 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1832 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1833 // FIXME: Implement more expansions.
1836 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1837 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1838 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1846 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1847 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1848 /// a load from the stack slot to DestVT, extending it if needed.
1849 /// The resultant code need not be legal.
1850 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1854 // Create the stack frame object.
1856 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1857 getTypeForEVT(*DAG.getContext()));
1858 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1860 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1861 int SPFI = StackPtrFI->getIndex();
1862 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1864 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1865 unsigned SlotSize = SlotVT.getSizeInBits();
1866 unsigned DestSize = DestVT.getSizeInBits();
1867 const Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1868 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType);
1870 // Emit a store to the stack slot. Use a truncstore if the input value is
1871 // later than DestVT.
1874 if (SrcSize > SlotSize)
1875 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1876 PtrInfo, SlotVT, false, false, SrcAlign);
1878 assert(SrcSize == SlotSize && "Invalid store");
1879 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1880 PtrInfo, false, false, SrcAlign);
1883 // Result is a load from the stack slot.
1884 if (SlotSize == DestSize)
1885 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1886 false, false, DestAlign);
1888 assert(SlotSize < DestSize && "Unknown extension!");
1889 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1890 PtrInfo, SlotVT, false, false, DestAlign);
1893 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1894 DebugLoc dl = Node->getDebugLoc();
1895 // Create a vector sized/aligned stack slot, store the value to element #0,
1896 // then load the whole vector back out.
1897 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1899 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1900 int SPFI = StackPtrFI->getIndex();
1902 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1904 MachinePointerInfo::getFixedStack(SPFI),
1905 Node->getValueType(0).getVectorElementType(),
1907 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1908 MachinePointerInfo::getFixedStack(SPFI),
1913 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1914 /// support the operation, but do support the resultant vector type.
1915 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1916 unsigned NumElems = Node->getNumOperands();
1917 SDValue Value1, Value2;
1918 DebugLoc dl = Node->getDebugLoc();
1919 EVT VT = Node->getValueType(0);
1920 EVT OpVT = Node->getOperand(0).getValueType();
1921 EVT EltVT = VT.getVectorElementType();
1923 // If the only non-undef value is the low element, turn this into a
1924 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1925 bool isOnlyLowElement = true;
1926 bool MoreThanTwoValues = false;
1927 bool isConstant = true;
1928 for (unsigned i = 0; i < NumElems; ++i) {
1929 SDValue V = Node->getOperand(i);
1930 if (V.getOpcode() == ISD::UNDEF)
1933 isOnlyLowElement = false;
1934 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1937 if (!Value1.getNode()) {
1939 } else if (!Value2.getNode()) {
1942 } else if (V != Value1 && V != Value2) {
1943 MoreThanTwoValues = true;
1947 if (!Value1.getNode())
1948 return DAG.getUNDEF(VT);
1950 if (isOnlyLowElement)
1951 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1953 // If all elements are constants, create a load from the constant pool.
1955 std::vector<Constant*> CV;
1956 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1957 if (ConstantFPSDNode *V =
1958 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1959 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1960 } else if (ConstantSDNode *V =
1961 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1963 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1965 // If OpVT and EltVT don't match, EltVT is not legal and the
1966 // element values have been promoted/truncated earlier. Undo this;
1967 // we don't want a v16i8 to become a v16i32 for example.
1968 const ConstantInt *CI = V->getConstantIntValue();
1969 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1970 CI->getZExtValue()));
1973 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1974 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1975 CV.push_back(UndefValue::get(OpNTy));
1978 Constant *CP = ConstantVector::get(CV);
1979 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1980 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1981 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1982 MachinePointerInfo::getConstantPool(),
1983 false, false, Alignment);
1986 if (!MoreThanTwoValues) {
1987 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1988 for (unsigned i = 0; i < NumElems; ++i) {
1989 SDValue V = Node->getOperand(i);
1990 if (V.getOpcode() == ISD::UNDEF)
1992 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1994 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1995 // Get the splatted value into the low element of a vector register.
1996 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1998 if (Value2.getNode())
1999 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2001 Vec2 = DAG.getUNDEF(VT);
2003 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2004 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2008 // Otherwise, we can't handle this case efficiently.
2009 return ExpandVectorBuildThroughStack(Node);
2012 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
2013 // does not fit into a register, return the lo part and set the hi part to the
2014 // by-reg argument. If it does fit into a single register, return the result
2015 // and leave the Hi part unset.
2016 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2018 // The input chain to this libcall is the entry node of the function.
2019 // Legalizing the call will automatically add the previous call to the
2021 SDValue InChain = DAG.getEntryNode();
2023 TargetLowering::ArgListTy Args;
2024 TargetLowering::ArgListEntry Entry;
2025 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2026 EVT ArgVT = Node->getOperand(i).getValueType();
2027 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2028 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2029 Entry.isSExt = isSigned;
2030 Entry.isZExt = !isSigned;
2031 Args.push_back(Entry);
2033 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2034 TLI.getPointerTy());
2036 // Splice the libcall in wherever FindInputOutputChains tells us to.
2037 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2039 // isTailCall may be true since the callee does not reference caller stack
2040 // frame. Check if it's in the right position.
2041 bool isTailCall = isInTailCallPosition(DAG, Node, TLI);
2042 std::pair<SDValue, SDValue> CallInfo =
2043 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2044 0, TLI.getLibcallCallingConv(LC), isTailCall,
2045 /*isReturnValueUsed=*/true,
2046 Callee, Args, DAG, Node->getDebugLoc());
2048 if (!CallInfo.second.getNode())
2049 // It's a tailcall, return the chain (which is the DAG root).
2050 return DAG.getRoot();
2052 // Legalize the call sequence, starting with the chain. This will advance
2053 // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
2054 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2055 LegalizeOp(CallInfo.second);
2056 return CallInfo.first;
2059 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
2060 // ExpandLibCall except that the first operand is the in-chain.
2061 std::pair<SDValue, SDValue>
2062 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2065 SDValue InChain = Node->getOperand(0);
2067 TargetLowering::ArgListTy Args;
2068 TargetLowering::ArgListEntry Entry;
2069 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2070 EVT ArgVT = Node->getOperand(i).getValueType();
2071 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2072 Entry.Node = Node->getOperand(i);
2074 Entry.isSExt = isSigned;
2075 Entry.isZExt = !isSigned;
2076 Args.push_back(Entry);
2078 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2079 TLI.getPointerTy());
2081 // Splice the libcall in wherever FindInputOutputChains tells us to.
2082 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2083 std::pair<SDValue, SDValue> CallInfo =
2084 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2085 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2086 /*isReturnValueUsed=*/true,
2087 Callee, Args, DAG, Node->getDebugLoc());
2089 // Legalize the call sequence, starting with the chain. This will advance
2090 // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
2091 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2092 LegalizeOp(CallInfo.second);
2096 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2097 RTLIB::Libcall Call_F32,
2098 RTLIB::Libcall Call_F64,
2099 RTLIB::Libcall Call_F80,
2100 RTLIB::Libcall Call_PPCF128) {
2102 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2103 default: assert(0 && "Unexpected request for libcall!");
2104 case MVT::f32: LC = Call_F32; break;
2105 case MVT::f64: LC = Call_F64; break;
2106 case MVT::f80: LC = Call_F80; break;
2107 case MVT::ppcf128: LC = Call_PPCF128; break;
2109 return ExpandLibCall(LC, Node, false);
2112 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2113 RTLIB::Libcall Call_I8,
2114 RTLIB::Libcall Call_I16,
2115 RTLIB::Libcall Call_I32,
2116 RTLIB::Libcall Call_I64,
2117 RTLIB::Libcall Call_I128) {
2119 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2120 default: assert(0 && "Unexpected request for libcall!");
2121 case MVT::i8: LC = Call_I8; break;
2122 case MVT::i16: LC = Call_I16; break;
2123 case MVT::i32: LC = Call_I32; break;
2124 case MVT::i64: LC = Call_I64; break;
2125 case MVT::i128: LC = Call_I128; break;
2127 return ExpandLibCall(LC, Node, isSigned);
2130 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
2131 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2132 const TargetLowering &TLI) {
2134 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2135 default: assert(0 && "Unexpected request for libcall!");
2136 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2137 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2138 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2139 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2140 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2143 return TLI.getLibcallName(LC) != 0;
2146 /// UseDivRem - Only issue divrem libcall if both quotient and remainder are
2148 static bool UseDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2149 unsigned OtherOpcode = 0;
2151 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2153 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2155 SDValue Op0 = Node->getOperand(0);
2156 SDValue Op1 = Node->getOperand(1);
2157 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2158 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2162 if (User->getOpcode() == OtherOpcode &&
2163 User->getOperand(0) == Op0 &&
2164 User->getOperand(1) == Op1)
2170 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2173 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2174 SmallVectorImpl<SDValue> &Results) {
2175 unsigned Opcode = Node->getOpcode();
2176 bool isSigned = Opcode == ISD::SDIVREM;
2179 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2180 default: assert(0 && "Unexpected request for libcall!");
2181 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2182 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2183 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2184 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2185 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2188 // The input chain to this libcall is the entry node of the function.
2189 // Legalizing the call will automatically add the previous call to the
2191 SDValue InChain = DAG.getEntryNode();
2193 EVT RetVT = Node->getValueType(0);
2194 const Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2196 TargetLowering::ArgListTy Args;
2197 TargetLowering::ArgListEntry Entry;
2198 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2199 EVT ArgVT = Node->getOperand(i).getValueType();
2200 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2201 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2202 Entry.isSExt = isSigned;
2203 Entry.isZExt = !isSigned;
2204 Args.push_back(Entry);
2207 // Also pass the return address of the remainder.
2208 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2210 Entry.Ty = RetTy->getPointerTo();
2211 Entry.isSExt = isSigned;
2212 Entry.isZExt = !isSigned;
2213 Args.push_back(Entry);
2215 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2216 TLI.getPointerTy());
2218 // Splice the libcall in wherever FindInputOutputChains tells us to.
2219 DebugLoc dl = Node->getDebugLoc();
2220 std::pair<SDValue, SDValue> CallInfo =
2221 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2222 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2223 /*isReturnValueUsed=*/true, Callee, Args, DAG, dl);
2225 // Legalize the call sequence, starting with the chain. This will advance
2226 // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
2227 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2228 LegalizeOp(CallInfo.second);
2230 // Remainder is loaded back from the stack frame.
2231 SDValue Rem = DAG.getLoad(RetVT, dl, getLastCALLSEQ(), FIPtr,
2232 MachinePointerInfo(), false, false, 0);
2233 Results.push_back(CallInfo.first);
2234 Results.push_back(Rem);
2237 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2238 /// INT_TO_FP operation of the specified operand when the target requests that
2239 /// we expand it. At this point, we know that the result and operand types are
2240 /// legal for the target.
2241 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2245 if (Op0.getValueType() == MVT::i32) {
2246 // simple 32-bit [signed|unsigned] integer to float/double expansion
2248 // Get the stack frame index of a 8 byte buffer.
2249 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2251 // word offset constant for Hi/Lo address computation
2252 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2253 // set up Hi and Lo (into buffer) address based on endian
2254 SDValue Hi = StackSlot;
2255 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2256 TLI.getPointerTy(), StackSlot, WordOff);
2257 if (TLI.isLittleEndian())
2260 // if signed map to unsigned space
2263 // constant used to invert sign bit (signed to unsigned mapping)
2264 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2265 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2269 // store the lo of the constructed double - based on integer input
2270 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2271 Op0Mapped, Lo, MachinePointerInfo(),
2273 // initial hi portion of constructed double
2274 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2275 // store the hi of the constructed double - biased exponent
2276 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2277 MachinePointerInfo(),
2279 // load the constructed double
2280 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2281 MachinePointerInfo(), false, false, 0);
2282 // FP constant to bias correct the final result
2283 SDValue Bias = DAG.getConstantFP(isSigned ?
2284 BitsToDouble(0x4330000080000000ULL) :
2285 BitsToDouble(0x4330000000000000ULL),
2287 // subtract the bias
2288 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2291 // handle final rounding
2292 if (DestVT == MVT::f64) {
2295 } else if (DestVT.bitsLT(MVT::f64)) {
2296 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2297 DAG.getIntPtrConstant(0));
2298 } else if (DestVT.bitsGT(MVT::f64)) {
2299 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2303 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2304 // Code below here assumes !isSigned without checking again.
2306 // Implementation of unsigned i64 to f64 following the algorithm in
2307 // __floatundidf in compiler_rt. This implementation has the advantage
2308 // of performing rounding correctly, both in the default rounding mode
2309 // and in all alternate rounding modes.
2310 // TODO: Generalize this for use with other types.
2311 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2313 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2314 SDValue TwoP84PlusTwoP52 =
2315 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2317 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2319 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2320 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2321 DAG.getConstant(32, MVT::i64));
2322 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2323 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2324 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2325 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2326 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2328 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2331 // Implementation of unsigned i64 to f32.
2332 // TODO: Generalize this for use with other types.
2333 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2334 // For unsigned conversions, convert them to signed conversions using the
2335 // algorithm from the x86_64 __floatundidf in compiler_rt.
2337 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2339 SDValue ShiftConst =
2340 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2341 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2342 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2343 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2344 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2346 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2347 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2349 // TODO: This really should be implemented using a branch rather than a
2350 // select. We happen to get lucky and machinesink does the right
2351 // thing most of the time. This would be a good candidate for a
2352 //pseudo-op, or, even better, for whole-function isel.
2353 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2354 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2355 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast);
2358 // Otherwise, implement the fully general conversion.
2360 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2361 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2362 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2363 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2364 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2365 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2366 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2367 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2368 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2369 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2370 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2372 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2373 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2375 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2376 DAG.getConstant(32, SHVT));
2377 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2378 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2380 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2381 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2382 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2383 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2384 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2385 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2386 DAG.getIntPtrConstant(0));
2389 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2391 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2392 Op0, DAG.getConstant(0, Op0.getValueType()),
2394 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2395 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2396 SignSet, Four, Zero);
2398 // If the sign bit of the integer is set, the large number will be treated
2399 // as a negative number. To counteract this, the dynamic code adds an
2400 // offset depending on the data type.
2402 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2403 default: assert(0 && "Unsupported integer type!");
2404 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2405 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2406 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2407 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2409 if (TLI.isLittleEndian()) FF <<= 32;
2410 Constant *FudgeFactor = ConstantInt::get(
2411 Type::getInt64Ty(*DAG.getContext()), FF);
2413 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2414 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2415 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2416 Alignment = std::min(Alignment, 4u);
2418 if (DestVT == MVT::f32)
2419 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2420 MachinePointerInfo::getConstantPool(),
2421 false, false, Alignment);
2424 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2425 DAG.getEntryNode(), CPIdx,
2426 MachinePointerInfo::getConstantPool(),
2427 MVT::f32, false, false, Alignment));
2430 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2433 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2434 /// *INT_TO_FP operation of the specified operand when the target requests that
2435 /// we promote it. At this point, we know that the result and operand types are
2436 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2437 /// operation that takes a larger input.
2438 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2442 // First step, figure out the appropriate *INT_TO_FP operation to use.
2443 EVT NewInTy = LegalOp.getValueType();
2445 unsigned OpToUse = 0;
2447 // Scan for the appropriate larger type to use.
2449 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2450 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2452 // If the target supports SINT_TO_FP of this type, use it.
2453 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2454 OpToUse = ISD::SINT_TO_FP;
2457 if (isSigned) continue;
2459 // If the target supports UINT_TO_FP of this type, use it.
2460 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2461 OpToUse = ISD::UINT_TO_FP;
2465 // Otherwise, try a larger type.
2468 // Okay, we found the operation and type to use. Zero extend our input to the
2469 // desired type then run the operation on it.
2470 return DAG.getNode(OpToUse, dl, DestVT,
2471 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2472 dl, NewInTy, LegalOp));
2475 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2476 /// FP_TO_*INT operation of the specified operand when the target requests that
2477 /// we promote it. At this point, we know that the result and operand types are
2478 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2479 /// operation that returns a larger result.
2480 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2484 // First step, figure out the appropriate FP_TO*INT operation to use.
2485 EVT NewOutTy = DestVT;
2487 unsigned OpToUse = 0;
2489 // Scan for the appropriate larger type to use.
2491 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2492 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2494 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2495 OpToUse = ISD::FP_TO_SINT;
2499 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2500 OpToUse = ISD::FP_TO_UINT;
2504 // Otherwise, try a larger type.
2508 // Okay, we found the operation and type to use.
2509 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2511 // Truncate the result of the extended FP_TO_*INT operation to the desired
2513 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2516 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2518 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2519 EVT VT = Op.getValueType();
2520 EVT SHVT = TLI.getShiftAmountTy(VT);
2521 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2522 switch (VT.getSimpleVT().SimpleTy) {
2523 default: assert(0 && "Unhandled Expand type in BSWAP!");
2525 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2526 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2527 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2529 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2530 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2531 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2532 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2533 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2534 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2535 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2536 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2537 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2539 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2540 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2541 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2542 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2543 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2544 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2545 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2546 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2547 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2548 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2549 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2550 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2551 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2552 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2553 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2554 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2555 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2556 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2557 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2558 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2559 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2563 /// SplatByte - Distribute ByteVal over NumBits bits.
2564 // FIXME: Move this helper to a common place.
2565 static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) {
2566 APInt Val = APInt(NumBits, ByteVal);
2568 for (unsigned i = NumBits; i > 8; i >>= 1) {
2569 Val = (Val << Shift) | Val;
2575 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2577 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2580 default: assert(0 && "Cannot expand this yet!");
2582 EVT VT = Op.getValueType();
2583 EVT ShVT = TLI.getShiftAmountTy(VT);
2584 unsigned Len = VT.getSizeInBits();
2586 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2587 "CTPOP not implemented for this type.");
2589 // This is the "best" algorithm from
2590 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2592 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT);
2593 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT);
2594 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT);
2595 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT);
2597 // v = v - ((v >> 1) & 0x55555555...)
2598 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2599 DAG.getNode(ISD::AND, dl, VT,
2600 DAG.getNode(ISD::SRL, dl, VT, Op,
2601 DAG.getConstant(1, ShVT)),
2603 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2604 Op = DAG.getNode(ISD::ADD, dl, VT,
2605 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2606 DAG.getNode(ISD::AND, dl, VT,
2607 DAG.getNode(ISD::SRL, dl, VT, Op,
2608 DAG.getConstant(2, ShVT)),
2610 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2611 Op = DAG.getNode(ISD::AND, dl, VT,
2612 DAG.getNode(ISD::ADD, dl, VT, Op,
2613 DAG.getNode(ISD::SRL, dl, VT, Op,
2614 DAG.getConstant(4, ShVT))),
2616 // v = (v * 0x01010101...) >> (Len - 8)
2617 Op = DAG.getNode(ISD::SRL, dl, VT,
2618 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2619 DAG.getConstant(Len - 8, ShVT));
2624 // for now, we do this:
2625 // x = x | (x >> 1);
2626 // x = x | (x >> 2);
2628 // x = x | (x >>16);
2629 // x = x | (x >>32); // for 64-bit input
2630 // return popcount(~x);
2632 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2633 EVT VT = Op.getValueType();
2634 EVT ShVT = TLI.getShiftAmountTy(VT);
2635 unsigned len = VT.getSizeInBits();
2636 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2637 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2638 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2639 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2641 Op = DAG.getNOT(dl, Op, VT);
2642 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2645 // for now, we use: { return popcount(~x & (x - 1)); }
2646 // unless the target has ctlz but not ctpop, in which case we use:
2647 // { return 32 - nlz(~x & (x-1)); }
2648 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2649 EVT VT = Op.getValueType();
2650 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2651 DAG.getNOT(dl, Op, VT),
2652 DAG.getNode(ISD::SUB, dl, VT, Op,
2653 DAG.getConstant(1, VT)));
2654 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2655 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2656 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2657 return DAG.getNode(ISD::SUB, dl, VT,
2658 DAG.getConstant(VT.getSizeInBits(), VT),
2659 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2660 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2665 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2666 unsigned Opc = Node->getOpcode();
2667 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2672 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2674 case ISD::ATOMIC_SWAP:
2675 switch (VT.SimpleTy) {
2676 default: llvm_unreachable("Unexpected value type for atomic!");
2677 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2678 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2679 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2680 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2683 case ISD::ATOMIC_CMP_SWAP:
2684 switch (VT.SimpleTy) {
2685 default: llvm_unreachable("Unexpected value type for atomic!");
2686 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2687 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2688 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2689 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2692 case ISD::ATOMIC_LOAD_ADD:
2693 switch (VT.SimpleTy) {
2694 default: llvm_unreachable("Unexpected value type for atomic!");
2695 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2696 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2697 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2698 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2701 case ISD::ATOMIC_LOAD_SUB:
2702 switch (VT.SimpleTy) {
2703 default: llvm_unreachable("Unexpected value type for atomic!");
2704 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2705 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2706 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2707 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2710 case ISD::ATOMIC_LOAD_AND:
2711 switch (VT.SimpleTy) {
2712 default: llvm_unreachable("Unexpected value type for atomic!");
2713 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2714 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2715 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2716 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2719 case ISD::ATOMIC_LOAD_OR:
2720 switch (VT.SimpleTy) {
2721 default: llvm_unreachable("Unexpected value type for atomic!");
2722 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2723 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2724 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2725 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2728 case ISD::ATOMIC_LOAD_XOR:
2729 switch (VT.SimpleTy) {
2730 default: llvm_unreachable("Unexpected value type for atomic!");
2731 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2732 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2733 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2734 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2737 case ISD::ATOMIC_LOAD_NAND:
2738 switch (VT.SimpleTy) {
2739 default: llvm_unreachable("Unexpected value type for atomic!");
2740 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2741 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2742 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2743 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2748 return ExpandChainLibCall(LC, Node, false);
2751 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2752 SmallVectorImpl<SDValue> &Results) {
2753 DebugLoc dl = Node->getDebugLoc();
2754 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2755 switch (Node->getOpcode()) {
2759 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2760 Results.push_back(Tmp1);
2763 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2765 case ISD::FRAMEADDR:
2766 case ISD::RETURNADDR:
2767 case ISD::FRAME_TO_ARGS_OFFSET:
2768 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2770 case ISD::FLT_ROUNDS_:
2771 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2773 case ISD::EH_RETURN:
2777 case ISD::EH_SJLJ_LONGJMP:
2778 case ISD::EH_SJLJ_DISPATCHSETUP:
2779 // If the target didn't expand these, there's nothing to do, so just
2780 // preserve the chain and be done.
2781 Results.push_back(Node->getOperand(0));
2783 case ISD::EH_SJLJ_SETJMP:
2784 // If the target didn't expand this, just return 'zero' and preserve the
2786 Results.push_back(DAG.getConstant(0, MVT::i32));
2787 Results.push_back(Node->getOperand(0));
2789 case ISD::MEMBARRIER: {
2790 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2791 TargetLowering::ArgListTy Args;
2792 std::pair<SDValue, SDValue> CallResult =
2793 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2794 false, false, false, false, 0, CallingConv::C,
2795 /*isTailCall=*/false,
2796 /*isReturnValueUsed=*/true,
2797 DAG.getExternalSymbol("__sync_synchronize",
2798 TLI.getPointerTy()),
2800 Results.push_back(CallResult.second);
2803 // By default, atomic intrinsics are marked Legal and lowered. Targets
2804 // which don't support them directly, however, may want libcalls, in which
2805 // case they mark them Expand, and we get here.
2806 case ISD::ATOMIC_SWAP:
2807 case ISD::ATOMIC_LOAD_ADD:
2808 case ISD::ATOMIC_LOAD_SUB:
2809 case ISD::ATOMIC_LOAD_AND:
2810 case ISD::ATOMIC_LOAD_OR:
2811 case ISD::ATOMIC_LOAD_XOR:
2812 case ISD::ATOMIC_LOAD_NAND:
2813 case ISD::ATOMIC_LOAD_MIN:
2814 case ISD::ATOMIC_LOAD_MAX:
2815 case ISD::ATOMIC_LOAD_UMIN:
2816 case ISD::ATOMIC_LOAD_UMAX:
2817 case ISD::ATOMIC_CMP_SWAP: {
2818 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2819 Results.push_back(Tmp.first);
2820 Results.push_back(Tmp.second);
2823 case ISD::DYNAMIC_STACKALLOC:
2824 ExpandDYNAMIC_STACKALLOC(Node, Results);
2826 case ISD::MERGE_VALUES:
2827 for (unsigned i = 0; i < Node->getNumValues(); i++)
2828 Results.push_back(Node->getOperand(i));
2831 EVT VT = Node->getValueType(0);
2833 Results.push_back(DAG.getConstant(0, VT));
2835 assert(VT.isFloatingPoint() && "Unknown value type!");
2836 Results.push_back(DAG.getConstantFP(0, VT));
2841 // If this operation is not supported, lower it to 'abort()' call
2842 TargetLowering::ArgListTy Args;
2843 std::pair<SDValue, SDValue> CallResult =
2844 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2845 false, false, false, false, 0, CallingConv::C,
2846 /*isTailCall=*/false,
2847 /*isReturnValueUsed=*/true,
2848 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2850 Results.push_back(CallResult.second);
2855 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2856 Node->getValueType(0), dl);
2857 Results.push_back(Tmp1);
2859 case ISD::FP_EXTEND:
2860 Tmp1 = EmitStackConvert(Node->getOperand(0),
2861 Node->getOperand(0).getValueType(),
2862 Node->getValueType(0), dl);
2863 Results.push_back(Tmp1);
2865 case ISD::SIGN_EXTEND_INREG: {
2866 // NOTE: we could fall back on load/store here too for targets without
2867 // SAR. However, it is doubtful that any exist.
2868 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2869 EVT VT = Node->getValueType(0);
2870 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
2873 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2874 ExtraVT.getScalarType().getSizeInBits();
2875 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2876 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2877 Node->getOperand(0), ShiftCst);
2878 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2879 Results.push_back(Tmp1);
2882 case ISD::FP_ROUND_INREG: {
2883 // The only way we can lower this is to turn it into a TRUNCSTORE,
2884 // EXTLOAD pair, targeting a temporary location (a stack slot).
2886 // NOTE: there is a choice here between constantly creating new stack
2887 // slots and always reusing the same one. We currently always create
2888 // new ones, as reuse may inhibit scheduling.
2889 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2890 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2891 Node->getValueType(0), dl);
2892 Results.push_back(Tmp1);
2895 case ISD::SINT_TO_FP:
2896 case ISD::UINT_TO_FP:
2897 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2898 Node->getOperand(0), Node->getValueType(0), dl);
2899 Results.push_back(Tmp1);
2901 case ISD::FP_TO_UINT: {
2902 SDValue True, False;
2903 EVT VT = Node->getOperand(0).getValueType();
2904 EVT NVT = Node->getValueType(0);
2905 APFloat apf(APInt::getNullValue(VT.getSizeInBits()));
2906 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2907 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2908 Tmp1 = DAG.getConstantFP(apf, VT);
2909 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2910 Node->getOperand(0),
2912 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2913 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2914 DAG.getNode(ISD::FSUB, dl, VT,
2915 Node->getOperand(0), Tmp1));
2916 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2917 DAG.getConstant(x, NVT));
2918 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2919 Results.push_back(Tmp1);
2923 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2924 EVT VT = Node->getValueType(0);
2925 Tmp1 = Node->getOperand(0);
2926 Tmp2 = Node->getOperand(1);
2927 unsigned Align = Node->getConstantOperandVal(3);
2929 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
2930 MachinePointerInfo(V), false, false, 0);
2931 SDValue VAList = VAListLoad;
2933 if (Align > TLI.getMinStackArgumentAlignment()) {
2934 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2936 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2937 DAG.getConstant(Align - 1,
2938 TLI.getPointerTy()));
2940 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
2941 DAG.getConstant(-(int64_t)Align,
2942 TLI.getPointerTy()));
2945 // Increment the pointer, VAList, to the next vaarg
2946 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2947 DAG.getConstant(TLI.getTargetData()->
2948 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2949 TLI.getPointerTy()));
2950 // Store the incremented VAList to the legalized pointer
2951 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
2952 MachinePointerInfo(V), false, false, 0);
2953 // Load the actual argument out of the pointer VAList
2954 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
2956 Results.push_back(Results[0].getValue(1));
2960 // This defaults to loading a pointer from the input and storing it to the
2961 // output, returning the chain.
2962 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2963 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2964 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2965 Node->getOperand(2), MachinePointerInfo(VS),
2967 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
2968 MachinePointerInfo(VD), false, false, 0);
2969 Results.push_back(Tmp1);
2972 case ISD::EXTRACT_VECTOR_ELT:
2973 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2974 // This must be an access of the only element. Return it.
2975 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
2976 Node->getOperand(0));
2978 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2979 Results.push_back(Tmp1);
2981 case ISD::EXTRACT_SUBVECTOR:
2982 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2984 case ISD::INSERT_SUBVECTOR:
2985 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
2987 case ISD::CONCAT_VECTORS: {
2988 Results.push_back(ExpandVectorBuildThroughStack(Node));
2991 case ISD::SCALAR_TO_VECTOR:
2992 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2994 case ISD::INSERT_VECTOR_ELT:
2995 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2996 Node->getOperand(1),
2997 Node->getOperand(2), dl));
2999 case ISD::VECTOR_SHUFFLE: {
3000 SmallVector<int, 8> Mask;
3001 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3003 EVT VT = Node->getValueType(0);
3004 EVT EltVT = VT.getVectorElementType();
3005 if (getTypeAction(EltVT) == Promote)
3006 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3007 unsigned NumElems = VT.getVectorNumElements();
3008 SmallVector<SDValue, 8> Ops;
3009 for (unsigned i = 0; i != NumElems; ++i) {
3011 Ops.push_back(DAG.getUNDEF(EltVT));
3014 unsigned Idx = Mask[i];
3016 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3017 Node->getOperand(0),
3018 DAG.getIntPtrConstant(Idx)));
3020 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3021 Node->getOperand(1),
3022 DAG.getIntPtrConstant(Idx - NumElems)));
3024 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
3025 Results.push_back(Tmp1);
3028 case ISD::EXTRACT_ELEMENT: {
3029 EVT OpTy = Node->getOperand(0).getValueType();
3030 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3032 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3033 DAG.getConstant(OpTy.getSizeInBits()/2,
3034 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3035 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3038 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3039 Node->getOperand(0));
3041 Results.push_back(Tmp1);
3044 case ISD::STACKSAVE:
3045 // Expand to CopyFromReg if the target set
3046 // StackPointerRegisterToSaveRestore.
3047 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3048 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3049 Node->getValueType(0)));
3050 Results.push_back(Results[0].getValue(1));
3052 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3053 Results.push_back(Node->getOperand(0));
3056 case ISD::STACKRESTORE:
3057 // Expand to CopyToReg if the target set
3058 // StackPointerRegisterToSaveRestore.
3059 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3060 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3061 Node->getOperand(1)));
3063 Results.push_back(Node->getOperand(0));
3066 case ISD::FCOPYSIGN:
3067 Results.push_back(ExpandFCOPYSIGN(Node));
3070 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3071 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3072 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3073 Node->getOperand(0));
3074 Results.push_back(Tmp1);
3077 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3078 EVT VT = Node->getValueType(0);
3079 Tmp1 = Node->getOperand(0);
3080 Tmp2 = DAG.getConstantFP(0.0, VT);
3081 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3082 Tmp1, Tmp2, ISD::SETUGT);
3083 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3084 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3085 Results.push_back(Tmp1);
3089 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3090 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
3093 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3094 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
3097 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3098 RTLIB::COS_F80, RTLIB::COS_PPCF128));
3101 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3102 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
3105 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3106 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
3109 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3110 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
3113 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3114 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
3117 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3118 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
3121 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3122 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
3125 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3126 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
3129 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3130 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
3133 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3134 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
3136 case ISD::FNEARBYINT:
3137 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3138 RTLIB::NEARBYINT_F64,
3139 RTLIB::NEARBYINT_F80,
3140 RTLIB::NEARBYINT_PPCF128));
3143 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3144 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
3147 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3148 RTLIB::POW_F80, RTLIB::POW_PPCF128));
3151 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3152 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
3155 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3156 RTLIB::REM_F80, RTLIB::REM_PPCF128));
3158 case ISD::FP16_TO_FP32:
3159 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3161 case ISD::FP32_TO_FP16:
3162 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3164 case ISD::ConstantFP: {
3165 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3166 // Check to see if this FP immediate is already legal.
3167 // If this is a legal constant, turn it into a TargetConstantFP node.
3168 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3169 Results.push_back(SDValue(Node, 0));
3171 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
3174 case ISD::EHSELECTION: {
3175 unsigned Reg = TLI.getExceptionSelectorRegister();
3176 assert(Reg && "Can't expand to unknown register!");
3177 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
3178 Node->getValueType(0)));
3179 Results.push_back(Results[0].getValue(1));
3182 case ISD::EXCEPTIONADDR: {
3183 unsigned Reg = TLI.getExceptionAddressRegister();
3184 assert(Reg && "Can't expand to unknown register!");
3185 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
3186 Node->getValueType(0)));
3187 Results.push_back(Results[0].getValue(1));
3191 EVT VT = Node->getValueType(0);
3192 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3193 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3194 "Don't know how to expand this subtraction!");
3195 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3196 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3197 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
3198 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3203 EVT VT = Node->getValueType(0);
3204 SDVTList VTs = DAG.getVTList(VT, VT);
3205 bool isSigned = Node->getOpcode() == ISD::SREM;
3206 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3207 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3208 Tmp2 = Node->getOperand(0);
3209 Tmp3 = Node->getOperand(1);
3210 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3211 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3212 UseDivRem(Node, isSigned, false))) {
3213 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3214 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3216 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3217 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3218 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3219 } else if (isSigned)
3220 Tmp1 = ExpandIntLibCall(Node, true,
3222 RTLIB::SREM_I16, RTLIB::SREM_I32,
3223 RTLIB::SREM_I64, RTLIB::SREM_I128);
3225 Tmp1 = ExpandIntLibCall(Node, false,
3227 RTLIB::UREM_I16, RTLIB::UREM_I32,
3228 RTLIB::UREM_I64, RTLIB::UREM_I128);
3229 Results.push_back(Tmp1);
3234 bool isSigned = Node->getOpcode() == ISD::SDIV;
3235 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3236 EVT VT = Node->getValueType(0);
3237 SDVTList VTs = DAG.getVTList(VT, VT);
3238 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3239 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3240 UseDivRem(Node, isSigned, true)))
3241 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3242 Node->getOperand(1));
3244 Tmp1 = ExpandIntLibCall(Node, true,
3246 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3247 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3249 Tmp1 = ExpandIntLibCall(Node, false,
3251 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3252 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3253 Results.push_back(Tmp1);
3258 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3260 EVT VT = Node->getValueType(0);
3261 SDVTList VTs = DAG.getVTList(VT, VT);
3262 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3263 "If this wasn't legal, it shouldn't have been created!");
3264 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3265 Node->getOperand(1));
3266 Results.push_back(Tmp1.getValue(1));
3271 // Expand into divrem libcall
3272 ExpandDivRemLibCall(Node, Results);
3275 EVT VT = Node->getValueType(0);
3276 SDVTList VTs = DAG.getVTList(VT, VT);
3277 // See if multiply or divide can be lowered using two-result operations.
3278 // We just need the low half of the multiply; try both the signed
3279 // and unsigned forms. If the target supports both SMUL_LOHI and
3280 // UMUL_LOHI, form a preference by checking which forms of plain
3281 // MULH it supports.
3282 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3283 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3284 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3285 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3286 unsigned OpToUse = 0;
3287 if (HasSMUL_LOHI && !HasMULHS) {
3288 OpToUse = ISD::SMUL_LOHI;
3289 } else if (HasUMUL_LOHI && !HasMULHU) {
3290 OpToUse = ISD::UMUL_LOHI;
3291 } else if (HasSMUL_LOHI) {
3292 OpToUse = ISD::SMUL_LOHI;
3293 } else if (HasUMUL_LOHI) {
3294 OpToUse = ISD::UMUL_LOHI;
3297 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3298 Node->getOperand(1)));
3301 Tmp1 = ExpandIntLibCall(Node, false,
3303 RTLIB::MUL_I16, RTLIB::MUL_I32,
3304 RTLIB::MUL_I64, RTLIB::MUL_I128);
3305 Results.push_back(Tmp1);
3310 SDValue LHS = Node->getOperand(0);
3311 SDValue RHS = Node->getOperand(1);
3312 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3313 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3315 Results.push_back(Sum);
3316 EVT OType = Node->getValueType(1);
3318 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3320 // LHSSign -> LHS >= 0
3321 // RHSSign -> RHS >= 0
3322 // SumSign -> Sum >= 0
3325 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3327 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3329 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3330 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3331 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3332 Node->getOpcode() == ISD::SADDO ?
3333 ISD::SETEQ : ISD::SETNE);
3335 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3336 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3338 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3339 Results.push_back(Cmp);
3344 SDValue LHS = Node->getOperand(0);
3345 SDValue RHS = Node->getOperand(1);
3346 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3347 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3349 Results.push_back(Sum);
3350 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3351 Node->getOpcode () == ISD::UADDO ?
3352 ISD::SETULT : ISD::SETUGT));
3357 EVT VT = Node->getValueType(0);
3358 SDValue LHS = Node->getOperand(0);
3359 SDValue RHS = Node->getOperand(1);
3362 static const unsigned Ops[2][3] =
3363 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3364 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3365 bool isSigned = Node->getOpcode() == ISD::SMULO;
3366 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3367 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3368 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3369 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3370 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3372 TopHalf = BottomHalf.getValue(1);
3373 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3374 VT.getSizeInBits() * 2))) {
3375 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3376 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3377 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3378 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3379 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3380 DAG.getIntPtrConstant(0));
3381 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3382 DAG.getIntPtrConstant(1));
3384 // We can fall back to a libcall with an illegal type for the MUL if we
3385 // have a libcall big enough.
3386 // Also, we can fall back to a division in some cases, but that's a big
3387 // performance hit in the general case.
3388 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3389 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3390 if (WideVT == MVT::i16)
3391 LC = RTLIB::MUL_I16;
3392 else if (WideVT == MVT::i32)
3393 LC = RTLIB::MUL_I32;
3394 else if (WideVT == MVT::i64)
3395 LC = RTLIB::MUL_I64;
3396 else if (WideVT == MVT::i128)
3397 LC = RTLIB::MUL_I128;
3398 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3399 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3400 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3402 SDValue Ret = ExpandLibCall(LC, Node, isSigned);
3403 BottomHalf = DAG.getNode(ISD::TRUNCATE, dl, VT, Ret);
3404 TopHalf = DAG.getNode(ISD::SRL, dl, Ret.getValueType(), Ret,
3405 DAG.getConstant(VT.getSizeInBits(), TLI.getPointerTy()));
3406 TopHalf = DAG.getNode(ISD::TRUNCATE, dl, VT, TopHalf);
3409 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3410 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3411 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3412 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3415 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3416 DAG.getConstant(0, VT), ISD::SETNE);
3418 Results.push_back(BottomHalf);
3419 Results.push_back(TopHalf);
3422 case ISD::BUILD_PAIR: {
3423 EVT PairTy = Node->getValueType(0);
3424 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3425 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3426 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3427 DAG.getConstant(PairTy.getSizeInBits()/2,
3428 TLI.getShiftAmountTy(PairTy)));
3429 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3433 Tmp1 = Node->getOperand(0);
3434 Tmp2 = Node->getOperand(1);
3435 Tmp3 = Node->getOperand(2);
3436 if (Tmp1.getOpcode() == ISD::SETCC) {
3437 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3439 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3441 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3442 DAG.getConstant(0, Tmp1.getValueType()),
3443 Tmp2, Tmp3, ISD::SETNE);
3445 Results.push_back(Tmp1);
3448 SDValue Chain = Node->getOperand(0);
3449 SDValue Table = Node->getOperand(1);
3450 SDValue Index = Node->getOperand(2);
3452 EVT PTy = TLI.getPointerTy();
3454 const TargetData &TD = *TLI.getTargetData();
3455 unsigned EntrySize =
3456 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3458 Index = DAG.getNode(ISD::MUL, dl, PTy,
3459 Index, DAG.getConstant(EntrySize, PTy));
3460 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3462 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3463 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3464 MachinePointerInfo::getJumpTable(), MemVT,
3467 if (TM.getRelocationModel() == Reloc::PIC_) {
3468 // For PIC, the sequence is:
3469 // BRIND(load(Jumptable + index) + RelocBase)
3470 // RelocBase can be JumpTable, GOT or some sort of global base.
3471 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3472 TLI.getPICJumpTableRelocBase(Table, DAG));
3474 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3475 Results.push_back(Tmp1);
3479 // Expand brcond's setcc into its constituent parts and create a BR_CC
3481 Tmp1 = Node->getOperand(0);
3482 Tmp2 = Node->getOperand(1);
3483 if (Tmp2.getOpcode() == ISD::SETCC) {
3484 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3485 Tmp1, Tmp2.getOperand(2),
3486 Tmp2.getOperand(0), Tmp2.getOperand(1),
3487 Node->getOperand(2));
3489 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3490 DAG.getCondCode(ISD::SETNE), Tmp2,
3491 DAG.getConstant(0, Tmp2.getValueType()),
3492 Node->getOperand(2));
3494 Results.push_back(Tmp1);
3497 Tmp1 = Node->getOperand(0);
3498 Tmp2 = Node->getOperand(1);
3499 Tmp3 = Node->getOperand(2);
3500 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3502 // If we expanded the SETCC into an AND/OR, return the new node
3503 if (Tmp2.getNode() == 0) {
3504 Results.push_back(Tmp1);
3508 // Otherwise, SETCC for the given comparison type must be completely
3509 // illegal; expand it into a SELECT_CC.
3510 EVT VT = Node->getValueType(0);
3511 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3512 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3513 Results.push_back(Tmp1);
3516 case ISD::SELECT_CC: {
3517 Tmp1 = Node->getOperand(0); // LHS
3518 Tmp2 = Node->getOperand(1); // RHS
3519 Tmp3 = Node->getOperand(2); // True
3520 Tmp4 = Node->getOperand(3); // False
3521 SDValue CC = Node->getOperand(4);
3523 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3524 Tmp1, Tmp2, CC, dl);
3526 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3527 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3528 CC = DAG.getCondCode(ISD::SETNE);
3529 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3531 Results.push_back(Tmp1);
3535 Tmp1 = Node->getOperand(0); // Chain
3536 Tmp2 = Node->getOperand(2); // LHS
3537 Tmp3 = Node->getOperand(3); // RHS
3538 Tmp4 = Node->getOperand(1); // CC
3540 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3541 Tmp2, Tmp3, Tmp4, dl);
3542 assert(LastCALLSEQ.size() == 1 && "branch inside CALLSEQ_BEGIN/END?");
3543 setLastCALLSEQ(DAG.getEntryNode());
3545 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3546 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3547 Tmp4 = DAG.getCondCode(ISD::SETNE);
3548 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3549 Tmp3, Node->getOperand(4));
3550 Results.push_back(Tmp1);
3553 case ISD::GLOBAL_OFFSET_TABLE:
3554 case ISD::GlobalAddress:
3555 case ISD::GlobalTLSAddress:
3556 case ISD::ExternalSymbol:
3557 case ISD::ConstantPool:
3558 case ISD::JumpTable:
3559 case ISD::INTRINSIC_W_CHAIN:
3560 case ISD::INTRINSIC_WO_CHAIN:
3561 case ISD::INTRINSIC_VOID:
3562 // FIXME: Custom lowering for these operations shouldn't return null!
3563 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3564 Results.push_back(SDValue(Node, i));
3568 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
3569 SmallVectorImpl<SDValue> &Results) {
3570 EVT OVT = Node->getValueType(0);
3571 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3572 Node->getOpcode() == ISD::SINT_TO_FP ||
3573 Node->getOpcode() == ISD::SETCC) {
3574 OVT = Node->getOperand(0).getValueType();
3576 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3577 DebugLoc dl = Node->getDebugLoc();
3578 SDValue Tmp1, Tmp2, Tmp3;
3579 switch (Node->getOpcode()) {
3583 // Zero extend the argument.
3584 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3585 // Perform the larger operation.
3586 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3587 if (Node->getOpcode() == ISD::CTTZ) {
3588 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3589 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3590 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3592 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3593 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3594 } else if (Node->getOpcode() == ISD::CTLZ) {
3595 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3596 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3597 DAG.getConstant(NVT.getSizeInBits() -
3598 OVT.getSizeInBits(), NVT));
3600 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3603 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3604 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3605 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3606 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3607 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3608 Results.push_back(Tmp1);
3611 case ISD::FP_TO_UINT:
3612 case ISD::FP_TO_SINT:
3613 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3614 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3615 Results.push_back(Tmp1);
3617 case ISD::UINT_TO_FP:
3618 case ISD::SINT_TO_FP:
3619 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3620 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3621 Results.push_back(Tmp1);
3626 unsigned ExtOp, TruncOp;
3627 if (OVT.isVector()) {
3628 ExtOp = ISD::BITCAST;
3629 TruncOp = ISD::BITCAST;
3631 assert(OVT.isInteger() && "Cannot promote logic operation");
3632 ExtOp = ISD::ANY_EXTEND;
3633 TruncOp = ISD::TRUNCATE;
3635 // Promote each of the values to the new type.
3636 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3637 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3638 // Perform the larger operation, then convert back
3639 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3640 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3644 unsigned ExtOp, TruncOp;
3645 if (Node->getValueType(0).isVector()) {
3646 ExtOp = ISD::BITCAST;
3647 TruncOp = ISD::BITCAST;
3648 } else if (Node->getValueType(0).isInteger()) {
3649 ExtOp = ISD::ANY_EXTEND;
3650 TruncOp = ISD::TRUNCATE;
3652 ExtOp = ISD::FP_EXTEND;
3653 TruncOp = ISD::FP_ROUND;
3655 Tmp1 = Node->getOperand(0);
3656 // Promote each of the values to the new type.
3657 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3658 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3659 // Perform the larger operation, then round down.
3660 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3661 if (TruncOp != ISD::FP_ROUND)
3662 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3664 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3665 DAG.getIntPtrConstant(0));
3666 Results.push_back(Tmp1);
3669 case ISD::VECTOR_SHUFFLE: {
3670 SmallVector<int, 8> Mask;
3671 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3673 // Cast the two input vectors.
3674 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3675 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3677 // Convert the shuffle mask to the right # elements.
3678 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3679 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3680 Results.push_back(Tmp1);
3684 unsigned ExtOp = ISD::FP_EXTEND;
3685 if (NVT.isInteger()) {
3686 ISD::CondCode CCCode =
3687 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3688 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3690 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3691 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3692 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3693 Tmp1, Tmp2, Node->getOperand(2)));
3699 // SelectionDAG::Legalize - This is the entry point for the file.
3701 void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) {
3702 /// run - This is the main entry point to this class.
3704 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG();