1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/Target/TargetFrameInfo.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetData.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/CallingConv.h"
25 #include "llvm/Constants.h"
26 #include "llvm/DerivedTypes.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/ADT/SmallPtrSet.h"
38 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
39 cl::desc("Pop up a window to show dags before legalize"));
41 static const bool ViewLegalizeDAGs = 0;
44 //===----------------------------------------------------------------------===//
45 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
46 /// hacks on it until the target machine can handle it. This involves
47 /// eliminating value sizes the machine cannot handle (promoting small sizes to
48 /// large sizes or splitting up large values into small values) as well as
49 /// eliminating operations the machine cannot handle.
51 /// This code also does a small amount of optimization and recognition of idioms
52 /// as part of its processing. For example, if a target does not support a
53 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
54 /// will attempt merge setcc and brc instructions into brcc's.
57 class VISIBILITY_HIDDEN SelectionDAGLegalize {
61 // Libcall insertion helpers.
63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
64 /// legalized. We use this to ensure that calls are properly serialized
65 /// against each other, including inserted libcalls.
66 SDOperand LastCALLSEQ_END;
68 /// IsLegalizingCall - This member is used *only* for purposes of providing
69 /// helpful assertions that a libcall isn't created while another call is
70 /// being legalized (which could lead to non-serialized call sequences).
71 bool IsLegalizingCall;
74 Legal, // The target natively supports this operation.
75 Promote, // This operation should be executed in a larger type.
76 Expand // Try to expand this to other ops, otherwise use a libcall.
79 /// ValueTypeActions - This is a bitvector that contains two bits for each
80 /// value type, where the two bits correspond to the LegalizeAction enum.
81 /// This can be queried with "getTypeAction(VT)".
82 TargetLowering::ValueTypeActionImpl ValueTypeActions;
84 /// LegalizedNodes - For nodes that are of legal width, and that have more
85 /// than one use, this map indicates what regularized operand to use. This
86 /// allows us to avoid legalizing the same thing more than once.
87 DenseMap<SDOperand, SDOperand> LegalizedNodes;
89 /// PromotedNodes - For nodes that are below legal width, and that have more
90 /// than one use, this map indicates what promoted value to use. This allows
91 /// us to avoid promoting the same thing more than once.
92 DenseMap<SDOperand, SDOperand> PromotedNodes;
94 /// ExpandedNodes - For nodes that need to be expanded this map indicates
95 /// which which operands are the expanded version of the input. This allows
96 /// us to avoid expanding the same node more than once.
97 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
99 /// SplitNodes - For vector nodes that need to be split, this map indicates
100 /// which which operands are the split version of the input. This allows us
101 /// to avoid splitting the same node more than once.
102 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
104 /// ScalarizedNodes - For nodes that need to be converted from vector types to
105 /// scalar types, this contains the mapping of ones we have already
106 /// processed to the result.
107 std::map<SDOperand, SDOperand> ScalarizedNodes;
109 void AddLegalizedOperand(SDOperand From, SDOperand To) {
110 LegalizedNodes.insert(std::make_pair(From, To));
111 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
115 void AddPromotedOperand(SDOperand From, SDOperand To) {
116 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
117 assert(isNew && "Got into the map somehow?");
118 // If someone requests legalization of the new node, return itself.
119 LegalizedNodes.insert(std::make_pair(To, To));
124 SelectionDAGLegalize(SelectionDAG &DAG);
126 /// getTypeAction - Return how we should legalize values of this type, either
127 /// it is already legal or we need to expand it into multiple registers of
128 /// smaller integer type, or we need to promote it to a larger type.
129 LegalizeAction getTypeAction(MVT::ValueType VT) const {
130 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
133 /// isTypeLegal - Return true if this type is legal on this target.
135 bool isTypeLegal(MVT::ValueType VT) const {
136 return getTypeAction(VT) == Legal;
142 /// HandleOp - Legalize, Promote, or Expand the specified operand as
143 /// appropriate for its type.
144 void HandleOp(SDOperand Op);
146 /// LegalizeOp - We know that the specified value has a legal type.
147 /// Recursively ensure that the operands have legal types, then return the
149 SDOperand LegalizeOp(SDOperand O);
151 /// UnrollVectorOp - We know that the given vector has a legal type, however
152 /// the operation it performs is not legal and is an operation that we have
153 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
154 /// operating on each element individually.
155 SDOperand UnrollVectorOp(SDOperand O);
157 /// PromoteOp - Given an operation that produces a value in an invalid type,
158 /// promote it to compute the value into a larger type. The produced value
159 /// will have the correct bits for the low portion of the register, but no
160 /// guarantee is made about the top bits: it may be zero, sign-extended, or
162 SDOperand PromoteOp(SDOperand O);
164 /// ExpandOp - Expand the specified SDOperand into its two component pieces
165 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
166 /// the LegalizeNodes map is filled in for any results that are not expanded,
167 /// the ExpandedNodes map is filled in for any results that are expanded, and
168 /// the Lo/Hi values are returned. This applies to integer types and Vector
170 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
172 /// SplitVectorOp - Given an operand of vector type, break it down into
173 /// two smaller values.
174 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
176 /// ScalarizeVectorOp - Given an operand of single-element vector type
177 /// (e.g. v1f32), convert it into the equivalent operation that returns a
178 /// scalar (e.g. f32) value.
179 SDOperand ScalarizeVectorOp(SDOperand O);
181 /// isShuffleLegal - Return true if a vector shuffle is legal with the
182 /// specified mask and type. Targets can specify exactly which masks they
183 /// support and the code generator is tasked with not creating illegal masks.
185 /// Note that this will also return true for shuffles that are promoted to a
188 /// If this is a legal shuffle, this method returns the (possibly promoted)
189 /// build_vector Mask. If it's not a legal shuffle, it returns null.
190 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
192 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
193 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
195 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
197 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
199 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
202 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT,
203 MVT::ValueType DestVT);
204 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
205 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
206 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
208 MVT::ValueType DestVT);
209 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
211 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
214 SDOperand ExpandBSWAP(SDOperand Op);
215 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
216 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
217 SDOperand &Lo, SDOperand &Hi);
218 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
219 SDOperand &Lo, SDOperand &Hi);
221 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
222 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
224 SDOperand getIntPtrConstant(uint64_t Val) {
225 return DAG.getConstant(Val, TLI.getPointerTy());
230 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
231 /// specified mask and type. Targets can specify exactly which masks they
232 /// support and the code generator is tasked with not creating illegal masks.
234 /// Note that this will also return true for shuffles that are promoted to a
236 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
237 SDOperand Mask) const {
238 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
240 case TargetLowering::Legal:
241 case TargetLowering::Custom:
243 case TargetLowering::Promote: {
244 // If this is promoted to a different type, convert the shuffle mask and
245 // ask if it is legal in the promoted type!
246 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
248 // If we changed # elements, change the shuffle mask.
249 unsigned NumEltsGrowth =
250 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
251 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
252 if (NumEltsGrowth > 1) {
253 // Renumber the elements.
254 SmallVector<SDOperand, 8> Ops;
255 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
256 SDOperand InOp = Mask.getOperand(i);
257 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
258 if (InOp.getOpcode() == ISD::UNDEF)
259 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
261 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
262 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
266 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
272 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
275 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
276 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
277 ValueTypeActions(TLI.getValueTypeActions()) {
278 assert(MVT::LAST_VALUETYPE <= 32 &&
279 "Too many value types for ValueTypeActions to hold!");
282 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
283 /// contains all of a nodes operands before it contains the node.
284 static void ComputeTopDownOrdering(SelectionDAG &DAG,
285 SmallVector<SDNode*, 64> &Order) {
287 DenseMap<SDNode*, unsigned> Visited;
288 std::vector<SDNode*> Worklist;
289 Worklist.reserve(128);
291 // Compute ordering from all of the leaves in the graphs, those (like the
292 // entry node) that have no operands.
293 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
294 E = DAG.allnodes_end(); I != E; ++I) {
295 if (I->getNumOperands() == 0) {
297 Worklist.push_back(I);
301 while (!Worklist.empty()) {
302 SDNode *N = Worklist.back();
305 if (++Visited[N] != N->getNumOperands())
306 continue; // Haven't visited all operands yet
310 // Now that we have N in, add anything that uses it if all of their operands
312 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
314 Worklist.push_back(*UI);
317 assert(Order.size() == Visited.size() &&
319 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
320 "Error: DAG is cyclic!");
324 void SelectionDAGLegalize::LegalizeDAG() {
325 LastCALLSEQ_END = DAG.getEntryNode();
326 IsLegalizingCall = false;
328 // The legalize process is inherently a bottom-up recursive process (users
329 // legalize their uses before themselves). Given infinite stack space, we
330 // could just start legalizing on the root and traverse the whole graph. In
331 // practice however, this causes us to run out of stack space on large basic
332 // blocks. To avoid this problem, compute an ordering of the nodes where each
333 // node is only legalized after all of its operands are legalized.
334 SmallVector<SDNode*, 64> Order;
335 ComputeTopDownOrdering(DAG, Order);
337 for (unsigned i = 0, e = Order.size(); i != e; ++i)
338 HandleOp(SDOperand(Order[i], 0));
340 // Finally, it's possible the root changed. Get the new root.
341 SDOperand OldRoot = DAG.getRoot();
342 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
343 DAG.setRoot(LegalizedNodes[OldRoot]);
345 ExpandedNodes.clear();
346 LegalizedNodes.clear();
347 PromotedNodes.clear();
349 ScalarizedNodes.clear();
351 // Remove dead nodes now.
352 DAG.RemoveDeadNodes();
356 /// FindCallEndFromCallStart - Given a chained node that is part of a call
357 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
358 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
359 if (Node->getOpcode() == ISD::CALLSEQ_END)
361 if (Node->use_empty())
362 return 0; // No CallSeqEnd
364 // The chain is usually at the end.
365 SDOperand TheChain(Node, Node->getNumValues()-1);
366 if (TheChain.getValueType() != MVT::Other) {
367 // Sometimes it's at the beginning.
368 TheChain = SDOperand(Node, 0);
369 if (TheChain.getValueType() != MVT::Other) {
370 // Otherwise, hunt for it.
371 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
372 if (Node->getValueType(i) == MVT::Other) {
373 TheChain = SDOperand(Node, i);
377 // Otherwise, we walked into a node without a chain.
378 if (TheChain.getValueType() != MVT::Other)
383 for (SDNode::use_iterator UI = Node->use_begin(),
384 E = Node->use_end(); UI != E; ++UI) {
386 // Make sure to only follow users of our token chain.
388 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
389 if (User->getOperand(i) == TheChain)
390 if (SDNode *Result = FindCallEndFromCallStart(User))
396 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
397 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
398 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
399 assert(Node && "Didn't find callseq_start for a call??");
400 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
402 assert(Node->getOperand(0).getValueType() == MVT::Other &&
403 "Node doesn't have a token chain argument!");
404 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
407 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
408 /// see if any uses can reach Dest. If no dest operands can get to dest,
409 /// legalize them, legalize ourself, and return false, otherwise, return true.
411 /// Keep track of the nodes we fine that actually do lead to Dest in
412 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
414 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
415 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
416 if (N == Dest) return true; // N certainly leads to Dest :)
418 // If we've already processed this node and it does lead to Dest, there is no
419 // need to reprocess it.
420 if (NodesLeadingTo.count(N)) return true;
422 // If the first result of this node has been already legalized, then it cannot
424 switch (getTypeAction(N->getValueType(0))) {
426 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
429 if (PromotedNodes.count(SDOperand(N, 0))) return false;
432 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
436 // Okay, this node has not already been legalized. Check and legalize all
437 // operands. If none lead to Dest, then we can legalize this node.
438 bool OperandsLeadToDest = false;
439 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
440 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
441 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
443 if (OperandsLeadToDest) {
444 NodesLeadingTo.insert(N);
448 // Okay, this node looks safe, legalize it and return false.
449 HandleOp(SDOperand(N, 0));
453 /// HandleOp - Legalize, Promote, or Expand the specified operand as
454 /// appropriate for its type.
455 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
456 MVT::ValueType VT = Op.getValueType();
457 switch (getTypeAction(VT)) {
458 default: assert(0 && "Bad type action!");
459 case Legal: (void)LegalizeOp(Op); break;
460 case Promote: (void)PromoteOp(Op); break;
462 if (!MVT::isVector(VT)) {
463 // If this is an illegal scalar, expand it into its two component
466 if (Op.getOpcode() == ISD::TargetConstant)
467 break; // Allow illegal target nodes.
469 } else if (MVT::getVectorNumElements(VT) == 1) {
470 // If this is an illegal single element vector, convert it to a
472 (void)ScalarizeVectorOp(Op);
474 // Otherwise, this is an illegal multiple element vector.
475 // Split it in half and legalize both parts.
477 SplitVectorOp(Op, X, Y);
483 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
484 /// a load from the constant pool.
485 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
486 SelectionDAG &DAG, TargetLowering &TLI) {
489 // If a FP immediate is precise when represented as a float and if the
490 // target can do an extending load from float to double, we put it into
491 // the constant pool as a float, even if it's is statically typed as a
493 MVT::ValueType VT = CFP->getValueType(0);
494 bool isDouble = VT == MVT::f64;
495 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
498 if (VT!=MVT::f64 && VT!=MVT::f32)
499 assert(0 && "Invalid type expansion");
500 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(),
501 isDouble ? MVT::i64 : MVT::i32);
504 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) &&
505 // Only do this if the target has a native EXTLOAD instruction from f32.
506 // Do not try to be clever about long doubles (so far)
507 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
508 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
513 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
515 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
516 CPIdx, NULL, 0, MVT::f32);
518 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
523 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
526 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
527 SelectionDAG &DAG, TargetLowering &TLI) {
528 MVT::ValueType VT = Node->getValueType(0);
529 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
530 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
531 "fcopysign expansion only supported for f32 and f64");
532 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
534 // First get the sign bit of second operand.
535 SDOperand Mask1 = (SrcVT == MVT::f64)
536 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
537 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
538 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
539 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
540 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
541 // Shift right or sign-extend it if the two operands have different types.
542 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
544 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
545 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
546 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
547 } else if (SizeDiff < 0)
548 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
550 // Clear the sign bit of first operand.
551 SDOperand Mask2 = (VT == MVT::f64)
552 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
553 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
554 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
555 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
556 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
558 // Or the value with the sign bit.
559 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
563 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
565 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
566 TargetLowering &TLI) {
567 SDOperand Chain = ST->getChain();
568 SDOperand Ptr = ST->getBasePtr();
569 SDOperand Val = ST->getValue();
570 MVT::ValueType VT = Val.getValueType();
571 int Alignment = ST->getAlignment();
572 int SVOffset = ST->getSrcValueOffset();
573 if (MVT::isFloatingPoint(ST->getStoredVT())) {
574 // Expand to a bitconvert of the value to the integer type of the
575 // same size, then a (misaligned) int store.
576 MVT::ValueType intVT;
579 else if (VT==MVT::f32)
582 assert(0 && "Unaligned load of unsupported floating point type");
584 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
585 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
586 SVOffset, ST->isVolatile(), Alignment);
588 assert(MVT::isInteger(ST->getStoredVT()) &&
589 "Unaligned store of unknown type.");
590 // Get the half-size VT
591 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1;
592 int NumBits = MVT::getSizeInBits(NewStoredVT);
593 int IncrementSize = NumBits / 8;
595 // Divide the stored value in two parts.
596 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
598 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
600 // Store the two parts
601 SDOperand Store1, Store2;
602 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
603 ST->getSrcValue(), SVOffset, NewStoredVT,
604 ST->isVolatile(), Alignment);
605 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
606 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
607 Alignment = MinAlign(Alignment, IncrementSize);
608 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
609 ST->getSrcValue(), SVOffset + IncrementSize,
610 NewStoredVT, ST->isVolatile(), Alignment);
612 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
615 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
617 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
618 TargetLowering &TLI) {
619 int SVOffset = LD->getSrcValueOffset();
620 SDOperand Chain = LD->getChain();
621 SDOperand Ptr = LD->getBasePtr();
622 MVT::ValueType VT = LD->getValueType(0);
623 MVT::ValueType LoadedVT = LD->getLoadedVT();
624 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT)) {
625 // Expand to a (misaligned) integer load of the same size,
626 // then bitconvert to floating point.
627 MVT::ValueType intVT;
628 if (LoadedVT == MVT::f64)
630 else if (LoadedVT == MVT::f32)
633 assert(0 && "Unaligned load of unsupported floating point type");
635 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
636 SVOffset, LD->isVolatile(),
638 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
640 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
642 SDOperand Ops[] = { Result, Chain };
643 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
646 assert((MVT::isInteger(LoadedVT) || MVT::isVector(LoadedVT)) &&
647 "Unaligned load of unsupported type.");
649 // Compute the new VT that is half the size of the old one. We either have an
650 // integer MVT or we have a vector MVT.
651 unsigned NumBits = MVT::getSizeInBits(LoadedVT);
652 MVT::ValueType NewLoadedVT;
653 if (!MVT::isVector(LoadedVT)) {
654 NewLoadedVT = MVT::getIntegerType(NumBits/2);
656 // FIXME: This is not right for <1 x anything> it is also not right for
657 // non-power-of-two vectors.
658 NewLoadedVT = MVT::getVectorType(MVT::getVectorElementType(LoadedVT),
659 MVT::getVectorNumElements(LoadedVT)/2);
663 unsigned Alignment = LD->getAlignment();
664 unsigned IncrementSize = NumBits / 8;
665 ISD::LoadExtType HiExtType = LD->getExtensionType();
667 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
668 if (HiExtType == ISD::NON_EXTLOAD)
669 HiExtType = ISD::ZEXTLOAD;
671 // Load the value in two parts
673 if (TLI.isLittleEndian()) {
674 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
675 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
676 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
677 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
678 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
679 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
680 MinAlign(Alignment, IncrementSize));
682 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
683 NewLoadedVT,LD->isVolatile(), Alignment);
684 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
685 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
686 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
687 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
688 MinAlign(Alignment, IncrementSize));
691 // aggregate the two parts
692 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
693 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
694 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
696 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
699 SDOperand Ops[] = { Result, TF };
700 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
703 /// UnrollVectorOp - We know that the given vector has a legal type, however
704 /// the operation it performs is not legal and is an operation that we have
705 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
706 /// operating on each element individually.
707 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
708 MVT::ValueType VT = Op.getValueType();
709 assert(isTypeLegal(VT) &&
710 "Caller should expand or promote operands that are not legal!");
711 assert(Op.Val->getNumValues() == 1 &&
712 "Can't unroll a vector with multiple results!");
713 unsigned NE = MVT::getVectorNumElements(VT);
714 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
716 SmallVector<SDOperand, 8> Scalars;
717 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
718 for (unsigned i = 0; i != NE; ++i) {
719 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
720 SDOperand Operand = Op.getOperand(j);
721 MVT::ValueType OperandVT = Operand.getValueType();
722 if (MVT::isVector(OperandVT)) {
723 // A vector operand; extract a single element.
724 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
725 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
728 DAG.getConstant(i, MVT::i32));
730 // A scalar operand; just use it as is.
731 Operands[j] = Operand;
734 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
735 &Operands[0], Operands.size()));
738 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
741 /// GetFPLibCall - Return the right libcall for the given floating point type.
742 static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
743 RTLIB::Libcall Call_F32,
744 RTLIB::Libcall Call_F64,
745 RTLIB::Libcall Call_F80,
746 RTLIB::Libcall Call_PPCF128) {
748 VT == MVT::f32 ? Call_F32 :
749 VT == MVT::f64 ? Call_F64 :
750 VT == MVT::f80 ? Call_F80 :
751 VT == MVT::ppcf128 ? Call_PPCF128 :
752 RTLIB::UNKNOWN_LIBCALL;
755 /// LegalizeOp - We know that the specified value has a legal type, and
756 /// that its operands are legal. Now ensure that the operation itself
757 /// is legal, recursively ensuring that the operands' operations remain
759 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
760 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
763 assert(isTypeLegal(Op.getValueType()) &&
764 "Caller should expand or promote operands that are not legal!");
765 SDNode *Node = Op.Val;
767 // If this operation defines any values that cannot be represented in a
768 // register on this target, make sure to expand or promote them.
769 if (Node->getNumValues() > 1) {
770 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
771 if (getTypeAction(Node->getValueType(i)) != Legal) {
772 HandleOp(Op.getValue(i));
773 assert(LegalizedNodes.count(Op) &&
774 "Handling didn't add legal operands!");
775 return LegalizedNodes[Op];
779 // Note that LegalizeOp may be reentered even from single-use nodes, which
780 // means that we always must cache transformed nodes.
781 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
782 if (I != LegalizedNodes.end()) return I->second;
784 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
785 SDOperand Result = Op;
786 bool isCustom = false;
788 switch (Node->getOpcode()) {
789 case ISD::FrameIndex:
790 case ISD::EntryToken:
792 case ISD::BasicBlock:
793 case ISD::TargetFrameIndex:
794 case ISD::TargetJumpTable:
795 case ISD::TargetConstant:
796 case ISD::TargetConstantFP:
797 case ISD::TargetConstantPool:
798 case ISD::TargetGlobalAddress:
799 case ISD::TargetGlobalTLSAddress:
800 case ISD::TargetExternalSymbol:
805 // Primitives must all be legal.
806 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
807 "This must be legal!");
810 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
811 // If this is a target node, legalize it by legalizing the operands then
812 // passing it through.
813 SmallVector<SDOperand, 8> Ops;
814 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
815 Ops.push_back(LegalizeOp(Node->getOperand(i)));
817 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
819 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
820 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
821 return Result.getValue(Op.ResNo);
823 // Otherwise this is an unhandled builtin node. splat.
825 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
827 assert(0 && "Do not know how to legalize this operator!");
829 case ISD::GLOBAL_OFFSET_TABLE:
830 case ISD::GlobalAddress:
831 case ISD::GlobalTLSAddress:
832 case ISD::ExternalSymbol:
833 case ISD::ConstantPool:
834 case ISD::JumpTable: // Nothing to do.
835 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
836 default: assert(0 && "This action is not supported yet!");
837 case TargetLowering::Custom:
838 Tmp1 = TLI.LowerOperation(Op, DAG);
839 if (Tmp1.Val) Result = Tmp1;
840 // FALLTHROUGH if the target doesn't want to lower this op after all.
841 case TargetLowering::Legal:
846 case ISD::RETURNADDR:
847 // The only option for these nodes is to custom lower them. If the target
848 // does not custom lower them, then return zero.
849 Tmp1 = TLI.LowerOperation(Op, DAG);
853 Result = DAG.getConstant(0, TLI.getPointerTy());
855 case ISD::FRAME_TO_ARGS_OFFSET: {
856 MVT::ValueType VT = Node->getValueType(0);
857 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
858 default: assert(0 && "This action is not supported yet!");
859 case TargetLowering::Custom:
860 Result = TLI.LowerOperation(Op, DAG);
861 if (Result.Val) break;
863 case TargetLowering::Legal:
864 Result = DAG.getConstant(0, VT);
869 case ISD::EXCEPTIONADDR: {
870 Tmp1 = LegalizeOp(Node->getOperand(0));
871 MVT::ValueType VT = Node->getValueType(0);
872 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
873 default: assert(0 && "This action is not supported yet!");
874 case TargetLowering::Expand: {
875 unsigned Reg = TLI.getExceptionAddressRegister();
876 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
879 case TargetLowering::Custom:
880 Result = TLI.LowerOperation(Op, DAG);
881 if (Result.Val) break;
883 case TargetLowering::Legal: {
884 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
885 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
891 if (Result.Val->getNumValues() == 1) break;
893 assert(Result.Val->getNumValues() == 2 &&
894 "Cannot return more than two values!");
896 // Since we produced two values, make sure to remember that we
897 // legalized both of them.
898 Tmp1 = LegalizeOp(Result);
899 Tmp2 = LegalizeOp(Result.getValue(1));
900 AddLegalizedOperand(Op.getValue(0), Tmp1);
901 AddLegalizedOperand(Op.getValue(1), Tmp2);
902 return Op.ResNo ? Tmp2 : Tmp1;
903 case ISD::EHSELECTION: {
904 Tmp1 = LegalizeOp(Node->getOperand(0));
905 Tmp2 = LegalizeOp(Node->getOperand(1));
906 MVT::ValueType VT = Node->getValueType(0);
907 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
908 default: assert(0 && "This action is not supported yet!");
909 case TargetLowering::Expand: {
910 unsigned Reg = TLI.getExceptionSelectorRegister();
911 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
914 case TargetLowering::Custom:
915 Result = TLI.LowerOperation(Op, DAG);
916 if (Result.Val) break;
918 case TargetLowering::Legal: {
919 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
920 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
926 if (Result.Val->getNumValues() == 1) break;
928 assert(Result.Val->getNumValues() == 2 &&
929 "Cannot return more than two values!");
931 // Since we produced two values, make sure to remember that we
932 // legalized both of them.
933 Tmp1 = LegalizeOp(Result);
934 Tmp2 = LegalizeOp(Result.getValue(1));
935 AddLegalizedOperand(Op.getValue(0), Tmp1);
936 AddLegalizedOperand(Op.getValue(1), Tmp2);
937 return Op.ResNo ? Tmp2 : Tmp1;
938 case ISD::EH_RETURN: {
939 MVT::ValueType VT = Node->getValueType(0);
940 // The only "good" option for this node is to custom lower it.
941 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
942 default: assert(0 && "This action is not supported at all!");
943 case TargetLowering::Custom:
944 Result = TLI.LowerOperation(Op, DAG);
945 if (Result.Val) break;
947 case TargetLowering::Legal:
948 // Target does not know, how to lower this, lower to noop
949 Result = LegalizeOp(Node->getOperand(0));
954 case ISD::AssertSext:
955 case ISD::AssertZext:
956 Tmp1 = LegalizeOp(Node->getOperand(0));
957 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
959 case ISD::MERGE_VALUES:
960 // Legalize eliminates MERGE_VALUES nodes.
961 Result = Node->getOperand(Op.ResNo);
963 case ISD::CopyFromReg:
964 Tmp1 = LegalizeOp(Node->getOperand(0));
965 Result = Op.getValue(0);
966 if (Node->getNumValues() == 2) {
967 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
969 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
970 if (Node->getNumOperands() == 3) {
971 Tmp2 = LegalizeOp(Node->getOperand(2));
972 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
974 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
976 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
978 // Since CopyFromReg produces two values, make sure to remember that we
979 // legalized both of them.
980 AddLegalizedOperand(Op.getValue(0), Result);
981 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
982 return Result.getValue(Op.ResNo);
984 MVT::ValueType VT = Op.getValueType();
985 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
986 default: assert(0 && "This action is not supported yet!");
987 case TargetLowering::Expand:
988 if (MVT::isInteger(VT))
989 Result = DAG.getConstant(0, VT);
990 else if (MVT::isFloatingPoint(VT))
991 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
994 assert(0 && "Unknown value type!");
996 case TargetLowering::Legal:
1002 case ISD::INTRINSIC_W_CHAIN:
1003 case ISD::INTRINSIC_WO_CHAIN:
1004 case ISD::INTRINSIC_VOID: {
1005 SmallVector<SDOperand, 8> Ops;
1006 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1007 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1008 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1010 // Allow the target to custom lower its intrinsics if it wants to.
1011 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1012 TargetLowering::Custom) {
1013 Tmp3 = TLI.LowerOperation(Result, DAG);
1014 if (Tmp3.Val) Result = Tmp3;
1017 if (Result.Val->getNumValues() == 1) break;
1019 // Must have return value and chain result.
1020 assert(Result.Val->getNumValues() == 2 &&
1021 "Cannot return more than two values!");
1023 // Since loads produce two values, make sure to remember that we
1024 // legalized both of them.
1025 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1026 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1027 return Result.getValue(Op.ResNo);
1031 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
1032 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1034 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
1035 case TargetLowering::Promote:
1036 default: assert(0 && "This action is not supported yet!");
1037 case TargetLowering::Expand: {
1038 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1039 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1040 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
1042 if (MMI && (useDEBUG_LOC || useLABEL)) {
1043 const std::string &FName =
1044 cast<StringSDNode>(Node->getOperand(3))->getValue();
1045 const std::string &DirName =
1046 cast<StringSDNode>(Node->getOperand(4))->getValue();
1047 unsigned SrcFile = MMI->RecordSource(DirName, FName);
1049 SmallVector<SDOperand, 8> Ops;
1050 Ops.push_back(Tmp1); // chain
1051 SDOperand LineOp = Node->getOperand(1);
1052 SDOperand ColOp = Node->getOperand(2);
1055 Ops.push_back(LineOp); // line #
1056 Ops.push_back(ColOp); // col #
1057 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1058 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1060 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
1061 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
1062 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
1063 Ops.push_back(DAG.getConstant(ID, MVT::i32));
1064 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
1067 Result = Tmp1; // chain
1071 case TargetLowering::Legal:
1072 if (Tmp1 != Node->getOperand(0) ||
1073 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1074 SmallVector<SDOperand, 8> Ops;
1075 Ops.push_back(Tmp1);
1076 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1077 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1078 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1080 // Otherwise promote them.
1081 Ops.push_back(PromoteOp(Node->getOperand(1)));
1082 Ops.push_back(PromoteOp(Node->getOperand(2)));
1084 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1085 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1086 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1092 case ISD::DEBUG_LOC:
1093 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1094 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1095 default: assert(0 && "This action is not supported yet!");
1096 case TargetLowering::Legal:
1097 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1098 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1099 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1100 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1101 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1107 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
1108 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1109 default: assert(0 && "This action is not supported yet!");
1110 case TargetLowering::Legal:
1111 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1112 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1113 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1115 case TargetLowering::Expand:
1116 Result = LegalizeOp(Node->getOperand(0));
1121 case ISD::Constant: {
1122 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1124 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1126 // We know we don't need to expand constants here, constants only have one
1127 // value and we check that it is fine above.
1129 if (opAction == TargetLowering::Custom) {
1130 Tmp1 = TLI.LowerOperation(Result, DAG);
1136 case ISD::ConstantFP: {
1137 // Spill FP immediates to the constant pool if the target cannot directly
1138 // codegen them. Targets often have some immediate values that can be
1139 // efficiently generated into an FP register without a load. We explicitly
1140 // leave these constants as ConstantFP nodes for the target to deal with.
1141 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1143 // Check to see if this FP immediate is already legal.
1144 bool isLegal = false;
1145 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1146 E = TLI.legal_fpimm_end(); I != E; ++I)
1147 if (CFP->isExactlyValue(*I)) {
1152 // If this is a legal constant, turn it into a TargetConstantFP node.
1154 Result = DAG.getTargetConstantFP(CFP->getValueAPF(),
1155 CFP->getValueType(0));
1159 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1160 default: assert(0 && "This action is not supported yet!");
1161 case TargetLowering::Custom:
1162 Tmp3 = TLI.LowerOperation(Result, DAG);
1168 case TargetLowering::Expand:
1169 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1173 case ISD::TokenFactor:
1174 if (Node->getNumOperands() == 2) {
1175 Tmp1 = LegalizeOp(Node->getOperand(0));
1176 Tmp2 = LegalizeOp(Node->getOperand(1));
1177 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1178 } else if (Node->getNumOperands() == 3) {
1179 Tmp1 = LegalizeOp(Node->getOperand(0));
1180 Tmp2 = LegalizeOp(Node->getOperand(1));
1181 Tmp3 = LegalizeOp(Node->getOperand(2));
1182 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1184 SmallVector<SDOperand, 8> Ops;
1185 // Legalize the operands.
1186 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1187 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1188 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1192 case ISD::FORMAL_ARGUMENTS:
1194 // The only option for this is to custom lower it.
1195 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1196 assert(Tmp3.Val && "Target didn't custom lower this node!");
1198 // The number of incoming and outgoing values should match; unless the final
1199 // outgoing value is a flag.
1200 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1201 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1202 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1204 "Lowering call/formal_arguments produced unexpected # results!");
1206 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1207 // remember that we legalized all of them, so it doesn't get relegalized.
1208 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1209 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1211 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1214 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1217 case ISD::EXTRACT_SUBREG: {
1218 Tmp1 = LegalizeOp(Node->getOperand(0));
1219 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1220 assert(idx && "Operand must be a constant");
1221 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1222 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1225 case ISD::INSERT_SUBREG: {
1226 Tmp1 = LegalizeOp(Node->getOperand(0));
1227 Tmp2 = LegalizeOp(Node->getOperand(1));
1228 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1229 assert(idx && "Operand must be a constant");
1230 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1231 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1234 case ISD::BUILD_VECTOR:
1235 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1236 default: assert(0 && "This action is not supported yet!");
1237 case TargetLowering::Custom:
1238 Tmp3 = TLI.LowerOperation(Result, DAG);
1244 case TargetLowering::Expand:
1245 Result = ExpandBUILD_VECTOR(Result.Val);
1249 case ISD::INSERT_VECTOR_ELT:
1250 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1251 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
1252 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1253 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1255 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1256 Node->getValueType(0))) {
1257 default: assert(0 && "This action is not supported yet!");
1258 case TargetLowering::Legal:
1260 case TargetLowering::Custom:
1261 Tmp4 = TLI.LowerOperation(Result, DAG);
1267 case TargetLowering::Expand: {
1268 // If the insert index is a constant, codegen this as a scalar_to_vector,
1269 // then a shuffle that inserts it into the right position in the vector.
1270 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1271 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1272 Tmp1.getValueType(), Tmp2);
1274 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1275 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1276 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1278 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
1279 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
1281 SmallVector<SDOperand, 8> ShufOps;
1282 for (unsigned i = 0; i != NumElts; ++i) {
1283 if (i != InsertPos->getValue())
1284 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1286 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1288 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1289 &ShufOps[0], ShufOps.size());
1291 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1292 Tmp1, ScVec, ShufMask);
1293 Result = LegalizeOp(Result);
1297 // If the target doesn't support this, we have to spill the input vector
1298 // to a temporary stack slot, update the element, then reload it. This is
1299 // badness. We could also load the value into a vector register (either
1300 // with a "move to register" or "extload into register" instruction, then
1301 // permute it into place, if the idx is a constant and if the idx is
1302 // supported by the target.
1303 MVT::ValueType VT = Tmp1.getValueType();
1304 MVT::ValueType EltVT = Tmp2.getValueType();
1305 MVT::ValueType IdxVT = Tmp3.getValueType();
1306 MVT::ValueType PtrVT = TLI.getPointerTy();
1307 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
1308 // Store the vector.
1309 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
1311 // Truncate or zero extend offset to target pointer type.
1312 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1313 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1314 // Add the offset to the index.
1315 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1316 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1317 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1318 // Store the scalar value.
1319 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
1320 // Load the updated vector.
1321 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1326 case ISD::SCALAR_TO_VECTOR:
1327 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1328 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1332 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1333 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1334 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1335 Node->getValueType(0))) {
1336 default: assert(0 && "This action is not supported yet!");
1337 case TargetLowering::Legal:
1339 case TargetLowering::Custom:
1340 Tmp3 = TLI.LowerOperation(Result, DAG);
1346 case TargetLowering::Expand:
1347 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1351 case ISD::VECTOR_SHUFFLE:
1352 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1353 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1354 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1356 // Allow targets to custom lower the SHUFFLEs they support.
1357 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1358 default: assert(0 && "Unknown operation action!");
1359 case TargetLowering::Legal:
1360 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1361 "vector shuffle should not be created if not legal!");
1363 case TargetLowering::Custom:
1364 Tmp3 = TLI.LowerOperation(Result, DAG);
1370 case TargetLowering::Expand: {
1371 MVT::ValueType VT = Node->getValueType(0);
1372 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1373 MVT::ValueType PtrVT = TLI.getPointerTy();
1374 SDOperand Mask = Node->getOperand(2);
1375 unsigned NumElems = Mask.getNumOperands();
1376 SmallVector<SDOperand,8> Ops;
1377 for (unsigned i = 0; i != NumElems; ++i) {
1378 SDOperand Arg = Mask.getOperand(i);
1379 if (Arg.getOpcode() == ISD::UNDEF) {
1380 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1382 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1383 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1385 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1386 DAG.getConstant(Idx, PtrVT)));
1388 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1389 DAG.getConstant(Idx - NumElems, PtrVT)));
1392 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1395 case TargetLowering::Promote: {
1396 // Change base type to a different vector type.
1397 MVT::ValueType OVT = Node->getValueType(0);
1398 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1400 // Cast the two input vectors.
1401 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1402 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1404 // Convert the shuffle mask to the right # elements.
1405 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1406 assert(Tmp3.Val && "Shuffle not legal?");
1407 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1408 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1414 case ISD::EXTRACT_VECTOR_ELT:
1415 Tmp1 = Node->getOperand(0);
1416 Tmp2 = LegalizeOp(Node->getOperand(1));
1417 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1418 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1421 case ISD::EXTRACT_SUBVECTOR:
1422 Tmp1 = Node->getOperand(0);
1423 Tmp2 = LegalizeOp(Node->getOperand(1));
1424 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1425 Result = ExpandEXTRACT_SUBVECTOR(Result);
1428 case ISD::CALLSEQ_START: {
1429 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1431 // Recursively Legalize all of the inputs of the call end that do not lead
1432 // to this call start. This ensures that any libcalls that need be inserted
1433 // are inserted *before* the CALLSEQ_START.
1434 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1435 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1436 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1440 // Now that we legalized all of the inputs (which may have inserted
1441 // libcalls) create the new CALLSEQ_START node.
1442 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1444 // Merge in the last call, to ensure that this call start after the last
1446 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1447 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1448 Tmp1 = LegalizeOp(Tmp1);
1451 // Do not try to legalize the target-specific arguments (#1+).
1452 if (Tmp1 != Node->getOperand(0)) {
1453 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1455 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1458 // Remember that the CALLSEQ_START is legalized.
1459 AddLegalizedOperand(Op.getValue(0), Result);
1460 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1461 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1463 // Now that the callseq_start and all of the non-call nodes above this call
1464 // sequence have been legalized, legalize the call itself. During this
1465 // process, no libcalls can/will be inserted, guaranteeing that no calls
1467 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1468 SDOperand InCallSEQ = LastCALLSEQ_END;
1469 // Note that we are selecting this call!
1470 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1471 IsLegalizingCall = true;
1473 // Legalize the call, starting from the CALLSEQ_END.
1474 LegalizeOp(LastCALLSEQ_END);
1475 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1478 case ISD::CALLSEQ_END:
1479 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1480 // will cause this node to be legalized as well as handling libcalls right.
1481 if (LastCALLSEQ_END.Val != Node) {
1482 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1483 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1484 assert(I != LegalizedNodes.end() &&
1485 "Legalizing the call start should have legalized this node!");
1489 // Otherwise, the call start has been legalized and everything is going
1490 // according to plan. Just legalize ourselves normally here.
1491 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1492 // Do not try to legalize the target-specific arguments (#1+), except for
1493 // an optional flag input.
1494 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1495 if (Tmp1 != Node->getOperand(0)) {
1496 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1498 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1501 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1502 if (Tmp1 != Node->getOperand(0) ||
1503 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1504 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1507 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1510 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1511 // This finishes up call legalization.
1512 IsLegalizingCall = false;
1514 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1515 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1516 if (Node->getNumValues() == 2)
1517 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1518 return Result.getValue(Op.ResNo);
1519 case ISD::DYNAMIC_STACKALLOC: {
1520 MVT::ValueType VT = Node->getValueType(0);
1521 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1522 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1523 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1524 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1526 Tmp1 = Result.getValue(0);
1527 Tmp2 = Result.getValue(1);
1528 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1529 default: assert(0 && "This action is not supported yet!");
1530 case TargetLowering::Expand: {
1531 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1532 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1533 " not tell us which reg is the stack pointer!");
1534 SDOperand Chain = Tmp1.getOperand(0);
1536 // Chain the dynamic stack allocation so that it doesn't modify the stack
1537 // pointer when other instructions are using the stack.
1538 Chain = DAG.getCALLSEQ_START(Chain,
1539 DAG.getConstant(0, TLI.getPointerTy()));
1541 SDOperand Size = Tmp2.getOperand(1);
1542 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1543 Chain = SP.getValue(1);
1544 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1545 unsigned StackAlign =
1546 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1547 if (Align > StackAlign)
1548 SP = DAG.getNode(ISD::AND, VT, SP,
1549 DAG.getConstant(-(uint64_t)Align, VT));
1550 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1551 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1554 DAG.getCALLSEQ_END(Chain,
1555 DAG.getConstant(0, TLI.getPointerTy()),
1556 DAG.getConstant(0, TLI.getPointerTy()),
1559 Tmp1 = LegalizeOp(Tmp1);
1560 Tmp2 = LegalizeOp(Tmp2);
1563 case TargetLowering::Custom:
1564 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1566 Tmp1 = LegalizeOp(Tmp3);
1567 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1570 case TargetLowering::Legal:
1573 // Since this op produce two values, make sure to remember that we
1574 // legalized both of them.
1575 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1576 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1577 return Op.ResNo ? Tmp2 : Tmp1;
1579 case ISD::INLINEASM: {
1580 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1581 bool Changed = false;
1582 // Legalize all of the operands of the inline asm, in case they are nodes
1583 // that need to be expanded or something. Note we skip the asm string and
1584 // all of the TargetConstant flags.
1585 SDOperand Op = LegalizeOp(Ops[0]);
1586 Changed = Op != Ops[0];
1589 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1590 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1591 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1592 for (++i; NumVals; ++i, --NumVals) {
1593 SDOperand Op = LegalizeOp(Ops[i]);
1602 Op = LegalizeOp(Ops.back());
1603 Changed |= Op != Ops.back();
1608 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1610 // INLINE asm returns a chain and flag, make sure to add both to the map.
1611 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1612 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1613 return Result.getValue(Op.ResNo);
1616 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1617 // Ensure that libcalls are emitted before a branch.
1618 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1619 Tmp1 = LegalizeOp(Tmp1);
1620 LastCALLSEQ_END = DAG.getEntryNode();
1622 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1625 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1626 // Ensure that libcalls are emitted before a branch.
1627 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1628 Tmp1 = LegalizeOp(Tmp1);
1629 LastCALLSEQ_END = DAG.getEntryNode();
1631 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1632 default: assert(0 && "Indirect target must be legal type (pointer)!");
1634 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1637 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1640 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1641 // Ensure that libcalls are emitted before a branch.
1642 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1643 Tmp1 = LegalizeOp(Tmp1);
1644 LastCALLSEQ_END = DAG.getEntryNode();
1646 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1647 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1649 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1650 default: assert(0 && "This action is not supported yet!");
1651 case TargetLowering::Legal: break;
1652 case TargetLowering::Custom:
1653 Tmp1 = TLI.LowerOperation(Result, DAG);
1654 if (Tmp1.Val) Result = Tmp1;
1656 case TargetLowering::Expand: {
1657 SDOperand Chain = Result.getOperand(0);
1658 SDOperand Table = Result.getOperand(1);
1659 SDOperand Index = Result.getOperand(2);
1661 MVT::ValueType PTy = TLI.getPointerTy();
1662 MachineFunction &MF = DAG.getMachineFunction();
1663 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1664 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1665 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1668 switch (EntrySize) {
1669 default: assert(0 && "Size of jump table not supported yet."); break;
1670 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1671 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1675 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1676 // For PIC, the sequence is:
1677 // BRIND(load(Jumptable + index) + RelocBase)
1678 // RelocBase can be JumpTable, GOT or some sort of global base.
1679 if (PTy != MVT::i32)
1680 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1681 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1682 TLI.getPICJumpTableRelocBase(Table, DAG));
1684 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1689 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1690 // Ensure that libcalls are emitted before a return.
1691 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1692 Tmp1 = LegalizeOp(Tmp1);
1693 LastCALLSEQ_END = DAG.getEntryNode();
1695 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1696 case Expand: assert(0 && "It's impossible to expand bools");
1698 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1701 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1703 // The top bits of the promoted condition are not necessarily zero, ensure
1704 // that the value is properly zero extended.
1705 if (!DAG.MaskedValueIsZero(Tmp2,
1706 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1707 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1711 // Basic block destination (Op#2) is always legal.
1712 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1714 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1715 default: assert(0 && "This action is not supported yet!");
1716 case TargetLowering::Legal: break;
1717 case TargetLowering::Custom:
1718 Tmp1 = TLI.LowerOperation(Result, DAG);
1719 if (Tmp1.Val) Result = Tmp1;
1721 case TargetLowering::Expand:
1722 // Expand brcond's setcc into its constituent parts and create a BR_CC
1724 if (Tmp2.getOpcode() == ISD::SETCC) {
1725 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1726 Tmp2.getOperand(0), Tmp2.getOperand(1),
1727 Node->getOperand(2));
1729 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1730 DAG.getCondCode(ISD::SETNE), Tmp2,
1731 DAG.getConstant(0, Tmp2.getValueType()),
1732 Node->getOperand(2));
1738 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1739 // Ensure that libcalls are emitted before a branch.
1740 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1741 Tmp1 = LegalizeOp(Tmp1);
1742 Tmp2 = Node->getOperand(2); // LHS
1743 Tmp3 = Node->getOperand(3); // RHS
1744 Tmp4 = Node->getOperand(1); // CC
1746 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1747 LastCALLSEQ_END = DAG.getEntryNode();
1749 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1750 // the LHS is a legal SETCC itself. In this case, we need to compare
1751 // the result against zero to select between true and false values.
1752 if (Tmp3.Val == 0) {
1753 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1754 Tmp4 = DAG.getCondCode(ISD::SETNE);
1757 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1758 Node->getOperand(4));
1760 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1761 default: assert(0 && "Unexpected action for BR_CC!");
1762 case TargetLowering::Legal: break;
1763 case TargetLowering::Custom:
1764 Tmp4 = TLI.LowerOperation(Result, DAG);
1765 if (Tmp4.Val) Result = Tmp4;
1770 LoadSDNode *LD = cast<LoadSDNode>(Node);
1771 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1772 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1774 ISD::LoadExtType ExtType = LD->getExtensionType();
1775 if (ExtType == ISD::NON_EXTLOAD) {
1776 MVT::ValueType VT = Node->getValueType(0);
1777 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1778 Tmp3 = Result.getValue(0);
1779 Tmp4 = Result.getValue(1);
1781 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1782 default: assert(0 && "This action is not supported yet!");
1783 case TargetLowering::Legal:
1784 // If this is an unaligned load and the target doesn't support it,
1786 if (!TLI.allowsUnalignedMemoryAccesses()) {
1787 unsigned ABIAlignment = TLI.getTargetData()->
1788 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1789 if (LD->getAlignment() < ABIAlignment){
1790 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1792 Tmp3 = Result.getOperand(0);
1793 Tmp4 = Result.getOperand(1);
1794 Tmp3 = LegalizeOp(Tmp3);
1795 Tmp4 = LegalizeOp(Tmp4);
1799 case TargetLowering::Custom:
1800 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1802 Tmp3 = LegalizeOp(Tmp1);
1803 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1806 case TargetLowering::Promote: {
1807 // Only promote a load of vector type to another.
1808 assert(MVT::isVector(VT) && "Cannot promote this load!");
1809 // Change base type to a different vector type.
1810 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1812 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1813 LD->getSrcValueOffset(),
1814 LD->isVolatile(), LD->getAlignment());
1815 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1816 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1820 // Since loads produce two values, make sure to remember that we
1821 // legalized both of them.
1822 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1823 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1824 return Op.ResNo ? Tmp4 : Tmp3;
1826 MVT::ValueType SrcVT = LD->getLoadedVT();
1827 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1828 default: assert(0 && "This action is not supported yet!");
1829 case TargetLowering::Promote:
1830 assert(SrcVT == MVT::i1 &&
1831 "Can only promote extending LOAD from i1 -> i8!");
1832 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1833 LD->getSrcValue(), LD->getSrcValueOffset(),
1834 MVT::i8, LD->isVolatile(), LD->getAlignment());
1835 Tmp1 = Result.getValue(0);
1836 Tmp2 = Result.getValue(1);
1838 case TargetLowering::Custom:
1841 case TargetLowering::Legal:
1842 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1843 Tmp1 = Result.getValue(0);
1844 Tmp2 = Result.getValue(1);
1847 Tmp3 = TLI.LowerOperation(Result, DAG);
1849 Tmp1 = LegalizeOp(Tmp3);
1850 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1853 // If this is an unaligned load and the target doesn't support it,
1855 if (!TLI.allowsUnalignedMemoryAccesses()) {
1856 unsigned ABIAlignment = TLI.getTargetData()->
1857 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1858 if (LD->getAlignment() < ABIAlignment){
1859 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1861 Tmp1 = Result.getOperand(0);
1862 Tmp2 = Result.getOperand(1);
1863 Tmp1 = LegalizeOp(Tmp1);
1864 Tmp2 = LegalizeOp(Tmp2);
1869 case TargetLowering::Expand:
1870 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1871 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1872 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1873 LD->getSrcValueOffset(),
1874 LD->isVolatile(), LD->getAlignment());
1875 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1876 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1877 Tmp2 = LegalizeOp(Load.getValue(1));
1880 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1881 // Turn the unsupported load into an EXTLOAD followed by an explicit
1882 // zero/sign extend inreg.
1883 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1884 Tmp1, Tmp2, LD->getSrcValue(),
1885 LD->getSrcValueOffset(), SrcVT,
1886 LD->isVolatile(), LD->getAlignment());
1888 if (ExtType == ISD::SEXTLOAD)
1889 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1890 Result, DAG.getValueType(SrcVT));
1892 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1893 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1894 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1897 // Since loads produce two values, make sure to remember that we legalized
1899 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1900 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1901 return Op.ResNo ? Tmp2 : Tmp1;
1904 case ISD::EXTRACT_ELEMENT: {
1905 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1906 switch (getTypeAction(OpTy)) {
1907 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1909 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1911 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1912 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1913 TLI.getShiftAmountTy()));
1914 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1917 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1918 Node->getOperand(0));
1922 // Get both the low and high parts.
1923 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1924 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1925 Result = Tmp2; // 1 -> Hi
1927 Result = Tmp1; // 0 -> Lo
1933 case ISD::CopyToReg:
1934 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1936 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1937 "Register type must be legal!");
1938 // Legalize the incoming value (must be a legal type).
1939 Tmp2 = LegalizeOp(Node->getOperand(2));
1940 if (Node->getNumValues() == 1) {
1941 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1943 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1944 if (Node->getNumOperands() == 4) {
1945 Tmp3 = LegalizeOp(Node->getOperand(3));
1946 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1949 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1952 // Since this produces two values, make sure to remember that we legalized
1954 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1955 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1961 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1963 // Ensure that libcalls are emitted before a return.
1964 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1965 Tmp1 = LegalizeOp(Tmp1);
1966 LastCALLSEQ_END = DAG.getEntryNode();
1968 switch (Node->getNumOperands()) {
1970 Tmp2 = Node->getOperand(1);
1971 Tmp3 = Node->getOperand(2); // Signness
1972 switch (getTypeAction(Tmp2.getValueType())) {
1974 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1977 if (!MVT::isVector(Tmp2.getValueType())) {
1979 ExpandOp(Tmp2, Lo, Hi);
1981 // Big endian systems want the hi reg first.
1982 if (!TLI.isLittleEndian())
1986 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1988 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1989 Result = LegalizeOp(Result);
1991 SDNode *InVal = Tmp2.Val;
1992 int InIx = Tmp2.ResNo;
1993 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
1994 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
1996 // Figure out if there is a simple type corresponding to this Vector
1997 // type. If so, convert to the vector type.
1998 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1999 if (TLI.isTypeLegal(TVT)) {
2000 // Turn this into a return of the vector type.
2001 Tmp2 = LegalizeOp(Tmp2);
2002 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2003 } else if (NumElems == 1) {
2004 // Turn this into a return of the scalar type.
2005 Tmp2 = ScalarizeVectorOp(Tmp2);
2006 Tmp2 = LegalizeOp(Tmp2);
2007 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2009 // FIXME: Returns of gcc generic vectors smaller than a legal type
2010 // should be returned in integer registers!
2012 // The scalarized value type may not be legal, e.g. it might require
2013 // promotion or expansion. Relegalize the return.
2014 Result = LegalizeOp(Result);
2016 // FIXME: Returns of gcc generic vectors larger than a legal vector
2017 // type should be returned by reference!
2019 SplitVectorOp(Tmp2, Lo, Hi);
2020 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2021 Result = LegalizeOp(Result);
2026 Tmp2 = PromoteOp(Node->getOperand(1));
2027 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2028 Result = LegalizeOp(Result);
2033 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2035 default: { // ret <values>
2036 SmallVector<SDOperand, 8> NewValues;
2037 NewValues.push_back(Tmp1);
2038 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2039 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2041 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2042 NewValues.push_back(Node->getOperand(i+1));
2046 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
2047 "FIXME: TODO: implement returning non-legal vector types!");
2048 ExpandOp(Node->getOperand(i), Lo, Hi);
2049 NewValues.push_back(Lo);
2050 NewValues.push_back(Node->getOperand(i+1));
2052 NewValues.push_back(Hi);
2053 NewValues.push_back(Node->getOperand(i+1));
2058 assert(0 && "Can't promote multiple return value yet!");
2061 if (NewValues.size() == Node->getNumOperands())
2062 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2064 Result = DAG.getNode(ISD::RET, MVT::Other,
2065 &NewValues[0], NewValues.size());
2070 if (Result.getOpcode() == ISD::RET) {
2071 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2072 default: assert(0 && "This action is not supported yet!");
2073 case TargetLowering::Legal: break;
2074 case TargetLowering::Custom:
2075 Tmp1 = TLI.LowerOperation(Result, DAG);
2076 if (Tmp1.Val) Result = Tmp1;
2082 StoreSDNode *ST = cast<StoreSDNode>(Node);
2083 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2084 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2085 int SVOffset = ST->getSrcValueOffset();
2086 unsigned Alignment = ST->getAlignment();
2087 bool isVolatile = ST->isVolatile();
2089 if (!ST->isTruncatingStore()) {
2090 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2091 // FIXME: We shouldn't do this for TargetConstantFP's.
2092 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2093 // to phase ordering between legalized code and the dag combiner. This
2094 // probably means that we need to integrate dag combiner and legalizer
2096 // We generally can't do this one for long doubles.
2097 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2098 if (CFP->getValueType(0) == MVT::f32 &&
2099 getTypeAction(MVT::i32) == Legal) {
2100 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF().
2101 convertToAPInt().getZExtValue(),
2103 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2104 SVOffset, isVolatile, Alignment);
2106 } else if (CFP->getValueType(0) == MVT::f64) {
2107 // If this target supports 64-bit registers, do a single 64-bit store.
2108 if (getTypeAction(MVT::i64) == Legal) {
2109 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2110 getZExtValue(), MVT::i64);
2111 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2112 SVOffset, isVolatile, Alignment);
2114 } else if (getTypeAction(MVT::i32) == Legal) {
2115 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2116 // stores. If the target supports neither 32- nor 64-bits, this
2117 // xform is certainly not worth it.
2118 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue();
2119 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32);
2120 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32);
2121 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
2123 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2124 SVOffset, isVolatile, Alignment);
2125 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2126 getIntPtrConstant(4));
2127 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2128 isVolatile, MinAlign(Alignment, 4U));
2130 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2136 switch (getTypeAction(ST->getStoredVT())) {
2138 Tmp3 = LegalizeOp(ST->getValue());
2139 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2142 MVT::ValueType VT = Tmp3.getValueType();
2143 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2144 default: assert(0 && "This action is not supported yet!");
2145 case TargetLowering::Legal:
2146 // If this is an unaligned store and the target doesn't support it,
2148 if (!TLI.allowsUnalignedMemoryAccesses()) {
2149 unsigned ABIAlignment = TLI.getTargetData()->
2150 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
2151 if (ST->getAlignment() < ABIAlignment)
2152 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2156 case TargetLowering::Custom:
2157 Tmp1 = TLI.LowerOperation(Result, DAG);
2158 if (Tmp1.Val) Result = Tmp1;
2160 case TargetLowering::Promote:
2161 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2162 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2163 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2164 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2165 ST->getSrcValue(), SVOffset, isVolatile,
2172 // Truncate the value and store the result.
2173 Tmp3 = PromoteOp(ST->getValue());
2174 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2175 SVOffset, ST->getStoredVT(),
2176 isVolatile, Alignment);
2180 unsigned IncrementSize = 0;
2183 // If this is a vector type, then we have to calculate the increment as
2184 // the product of the element size in bytes, and the number of elements
2185 // in the high half of the vector.
2186 if (MVT::isVector(ST->getValue().getValueType())) {
2187 SDNode *InVal = ST->getValue().Val;
2188 int InIx = ST->getValue().ResNo;
2189 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
2190 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
2192 // Figure out if there is a simple type corresponding to this Vector
2193 // type. If so, convert to the vector type.
2194 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2195 if (TLI.isTypeLegal(TVT)) {
2196 // Turn this into a normal store of the vector type.
2197 Tmp3 = LegalizeOp(Node->getOperand(1));
2198 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2199 SVOffset, isVolatile, Alignment);
2200 Result = LegalizeOp(Result);
2202 } else if (NumElems == 1) {
2203 // Turn this into a normal store of the scalar type.
2204 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
2205 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2206 SVOffset, isVolatile, Alignment);
2207 // The scalarized value type may not be legal, e.g. it might require
2208 // promotion or expansion. Relegalize the scalar store.
2209 Result = LegalizeOp(Result);
2212 SplitVectorOp(Node->getOperand(1), Lo, Hi);
2213 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
2214 MVT::getSizeInBits(EVT)/8;
2217 ExpandOp(Node->getOperand(1), Lo, Hi);
2218 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2220 if (!TLI.isLittleEndian())
2224 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2225 SVOffset, isVolatile, Alignment);
2227 if (Hi.Val == NULL) {
2228 // Must be int <-> float one-to-one expansion.
2233 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2234 getIntPtrConstant(IncrementSize));
2235 assert(isTypeLegal(Tmp2.getValueType()) &&
2236 "Pointers must be legal!");
2237 SVOffset += IncrementSize;
2238 Alignment = MinAlign(Alignment, IncrementSize);
2239 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2240 SVOffset, isVolatile, Alignment);
2241 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2246 assert(isTypeLegal(ST->getValue().getValueType()) &&
2247 "Cannot handle illegal TRUNCSTORE yet!");
2248 Tmp3 = LegalizeOp(ST->getValue());
2250 // The only promote case we handle is TRUNCSTORE:i1 X into
2251 // -> TRUNCSTORE:i8 (and X, 1)
2252 if (ST->getStoredVT() == MVT::i1 &&
2253 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
2254 // Promote the bool to a mask then store.
2255 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
2256 DAG.getConstant(1, Tmp3.getValueType()));
2257 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2259 isVolatile, Alignment);
2260 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2261 Tmp2 != ST->getBasePtr()) {
2262 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2266 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
2267 switch (TLI.getStoreXAction(StVT)) {
2268 default: assert(0 && "This action is not supported yet!");
2269 case TargetLowering::Legal:
2270 // If this is an unaligned store and the target doesn't support it,
2272 if (!TLI.allowsUnalignedMemoryAccesses()) {
2273 unsigned ABIAlignment = TLI.getTargetData()->
2274 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
2275 if (ST->getAlignment() < ABIAlignment)
2276 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2280 case TargetLowering::Custom:
2281 Tmp1 = TLI.LowerOperation(Result, DAG);
2282 if (Tmp1.Val) Result = Tmp1;
2289 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2290 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2292 case ISD::STACKSAVE:
2293 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2294 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2295 Tmp1 = Result.getValue(0);
2296 Tmp2 = Result.getValue(1);
2298 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2299 default: assert(0 && "This action is not supported yet!");
2300 case TargetLowering::Legal: break;
2301 case TargetLowering::Custom:
2302 Tmp3 = TLI.LowerOperation(Result, DAG);
2304 Tmp1 = LegalizeOp(Tmp3);
2305 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2308 case TargetLowering::Expand:
2309 // Expand to CopyFromReg if the target set
2310 // StackPointerRegisterToSaveRestore.
2311 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2312 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2313 Node->getValueType(0));
2314 Tmp2 = Tmp1.getValue(1);
2316 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2317 Tmp2 = Node->getOperand(0);
2322 // Since stacksave produce two values, make sure to remember that we
2323 // legalized both of them.
2324 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2325 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2326 return Op.ResNo ? Tmp2 : Tmp1;
2328 case ISD::STACKRESTORE:
2329 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2330 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2331 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2333 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2334 default: assert(0 && "This action is not supported yet!");
2335 case TargetLowering::Legal: break;
2336 case TargetLowering::Custom:
2337 Tmp1 = TLI.LowerOperation(Result, DAG);
2338 if (Tmp1.Val) Result = Tmp1;
2340 case TargetLowering::Expand:
2341 // Expand to CopyToReg if the target set
2342 // StackPointerRegisterToSaveRestore.
2343 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2344 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2352 case ISD::READCYCLECOUNTER:
2353 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2354 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2355 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2356 Node->getValueType(0))) {
2357 default: assert(0 && "This action is not supported yet!");
2358 case TargetLowering::Legal:
2359 Tmp1 = Result.getValue(0);
2360 Tmp2 = Result.getValue(1);
2362 case TargetLowering::Custom:
2363 Result = TLI.LowerOperation(Result, DAG);
2364 Tmp1 = LegalizeOp(Result.getValue(0));
2365 Tmp2 = LegalizeOp(Result.getValue(1));
2369 // Since rdcc produce two values, make sure to remember that we legalized
2371 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2372 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2376 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2377 case Expand: assert(0 && "It's impossible to expand bools");
2379 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2382 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2383 // Make sure the condition is either zero or one.
2384 if (!DAG.MaskedValueIsZero(Tmp1,
2385 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2386 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2389 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2390 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2392 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2394 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2395 default: assert(0 && "This action is not supported yet!");
2396 case TargetLowering::Legal: break;
2397 case TargetLowering::Custom: {
2398 Tmp1 = TLI.LowerOperation(Result, DAG);
2399 if (Tmp1.Val) Result = Tmp1;
2402 case TargetLowering::Expand:
2403 if (Tmp1.getOpcode() == ISD::SETCC) {
2404 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2406 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2408 Result = DAG.getSelectCC(Tmp1,
2409 DAG.getConstant(0, Tmp1.getValueType()),
2410 Tmp2, Tmp3, ISD::SETNE);
2413 case TargetLowering::Promote: {
2414 MVT::ValueType NVT =
2415 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2416 unsigned ExtOp, TruncOp;
2417 if (MVT::isVector(Tmp2.getValueType())) {
2418 ExtOp = ISD::BIT_CONVERT;
2419 TruncOp = ISD::BIT_CONVERT;
2420 } else if (MVT::isInteger(Tmp2.getValueType())) {
2421 ExtOp = ISD::ANY_EXTEND;
2422 TruncOp = ISD::TRUNCATE;
2424 ExtOp = ISD::FP_EXTEND;
2425 TruncOp = ISD::FP_ROUND;
2427 // Promote each of the values to the new type.
2428 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2429 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2430 // Perform the larger operation, then round down.
2431 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2432 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2437 case ISD::SELECT_CC: {
2438 Tmp1 = Node->getOperand(0); // LHS
2439 Tmp2 = Node->getOperand(1); // RHS
2440 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2441 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2442 SDOperand CC = Node->getOperand(4);
2444 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2446 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2447 // the LHS is a legal SETCC itself. In this case, we need to compare
2448 // the result against zero to select between true and false values.
2449 if (Tmp2.Val == 0) {
2450 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2451 CC = DAG.getCondCode(ISD::SETNE);
2453 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2455 // Everything is legal, see if we should expand this op or something.
2456 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2457 default: assert(0 && "This action is not supported yet!");
2458 case TargetLowering::Legal: break;
2459 case TargetLowering::Custom:
2460 Tmp1 = TLI.LowerOperation(Result, DAG);
2461 if (Tmp1.Val) Result = Tmp1;
2467 Tmp1 = Node->getOperand(0);
2468 Tmp2 = Node->getOperand(1);
2469 Tmp3 = Node->getOperand(2);
2470 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2472 // If we had to Expand the SetCC operands into a SELECT node, then it may
2473 // not always be possible to return a true LHS & RHS. In this case, just
2474 // return the value we legalized, returned in the LHS
2475 if (Tmp2.Val == 0) {
2480 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2481 default: assert(0 && "Cannot handle this action for SETCC yet!");
2482 case TargetLowering::Custom:
2485 case TargetLowering::Legal:
2486 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2488 Tmp4 = TLI.LowerOperation(Result, DAG);
2489 if (Tmp4.Val) Result = Tmp4;
2492 case TargetLowering::Promote: {
2493 // First step, figure out the appropriate operation to use.
2494 // Allow SETCC to not be supported for all legal data types
2495 // Mostly this targets FP
2496 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2497 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2499 // Scan for the appropriate larger type to use.
2501 NewInTy = (MVT::ValueType)(NewInTy+1);
2503 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2504 "Fell off of the edge of the integer world");
2505 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2506 "Fell off of the edge of the floating point world");
2508 // If the target supports SETCC of this type, use it.
2509 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2512 if (MVT::isInteger(NewInTy))
2513 assert(0 && "Cannot promote Legal Integer SETCC yet");
2515 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2516 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2518 Tmp1 = LegalizeOp(Tmp1);
2519 Tmp2 = LegalizeOp(Tmp2);
2520 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2521 Result = LegalizeOp(Result);
2524 case TargetLowering::Expand:
2525 // Expand a setcc node into a select_cc of the same condition, lhs, and
2526 // rhs that selects between const 1 (true) and const 0 (false).
2527 MVT::ValueType VT = Node->getValueType(0);
2528 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2529 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2536 case ISD::MEMMOVE: {
2537 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2538 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2540 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2541 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2542 case Expand: assert(0 && "Cannot expand a byte!");
2544 Tmp3 = LegalizeOp(Node->getOperand(2));
2547 Tmp3 = PromoteOp(Node->getOperand(2));
2551 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2555 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2557 // Length is too big, just take the lo-part of the length.
2559 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2563 Tmp4 = LegalizeOp(Node->getOperand(3));
2566 Tmp4 = PromoteOp(Node->getOperand(3));
2571 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2572 case Expand: assert(0 && "Cannot expand this yet!");
2574 Tmp5 = LegalizeOp(Node->getOperand(4));
2577 Tmp5 = PromoteOp(Node->getOperand(4));
2582 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool
2583 case Expand: assert(0 && "Cannot expand this yet!");
2585 Tmp6 = LegalizeOp(Node->getOperand(5));
2588 Tmp6 = PromoteOp(Node->getOperand(5));
2592 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2593 default: assert(0 && "This action not implemented for this operation!");
2594 case TargetLowering::Custom:
2597 case TargetLowering::Legal: {
2598 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 };
2599 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
2601 Tmp1 = TLI.LowerOperation(Result, DAG);
2602 if (Tmp1.Val) Result = Tmp1;
2606 case TargetLowering::Expand: {
2607 // Otherwise, the target does not support this operation. Lower the
2608 // operation to an explicit libcall as appropriate.
2609 MVT::ValueType IntPtr = TLI.getPointerTy();
2610 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2611 TargetLowering::ArgListTy Args;
2612 TargetLowering::ArgListEntry Entry;
2614 const char *FnName = 0;
2615 if (Node->getOpcode() == ISD::MEMSET) {
2616 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2617 Args.push_back(Entry);
2618 // Extend the (previously legalized) ubyte argument to be an int value
2620 if (Tmp3.getValueType() > MVT::i32)
2621 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2623 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2624 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2625 Args.push_back(Entry);
2626 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2627 Args.push_back(Entry);
2630 } else if (Node->getOpcode() == ISD::MEMCPY ||
2631 Node->getOpcode() == ISD::MEMMOVE) {
2632 Entry.Ty = IntPtrTy;
2633 Entry.Node = Tmp2; Args.push_back(Entry);
2634 Entry.Node = Tmp3; Args.push_back(Entry);
2635 Entry.Node = Tmp4; Args.push_back(Entry);
2636 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2638 assert(0 && "Unknown op!");
2641 std::pair<SDOperand,SDOperand> CallResult =
2642 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2643 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2644 Result = CallResult.second;
2651 case ISD::SHL_PARTS:
2652 case ISD::SRA_PARTS:
2653 case ISD::SRL_PARTS: {
2654 SmallVector<SDOperand, 8> Ops;
2655 bool Changed = false;
2656 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2657 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2658 Changed |= Ops.back() != Node->getOperand(i);
2661 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2663 switch (TLI.getOperationAction(Node->getOpcode(),
2664 Node->getValueType(0))) {
2665 default: assert(0 && "This action is not supported yet!");
2666 case TargetLowering::Legal: break;
2667 case TargetLowering::Custom:
2668 Tmp1 = TLI.LowerOperation(Result, DAG);
2670 SDOperand Tmp2, RetVal(0, 0);
2671 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2672 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2673 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2677 assert(RetVal.Val && "Illegal result number");
2683 // Since these produce multiple values, make sure to remember that we
2684 // legalized all of them.
2685 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2686 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2687 return Result.getValue(Op.ResNo);
2709 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2710 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2711 case Expand: assert(0 && "Not possible");
2713 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2716 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2720 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2722 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2723 default: assert(0 && "BinOp legalize operation not supported");
2724 case TargetLowering::Legal: break;
2725 case TargetLowering::Custom:
2726 Tmp1 = TLI.LowerOperation(Result, DAG);
2727 if (Tmp1.Val) Result = Tmp1;
2729 case TargetLowering::Expand: {
2730 MVT::ValueType VT = Op.getValueType();
2732 // See if multiply or divide can be lowered using two-result operations.
2733 SDVTList VTs = DAG.getVTList(VT, VT);
2734 if (Node->getOpcode() == ISD::MUL) {
2735 // We just need the low half of the multiply; try both the signed
2736 // and unsigned forms. If the target supports both SMUL_LOHI and
2737 // UMUL_LOHI, form a preference by checking which forms of plain
2738 // MULH it supports.
2739 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2740 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2741 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2742 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2743 unsigned OpToUse = 0;
2744 if (HasSMUL_LOHI && !HasMULHS) {
2745 OpToUse = ISD::SMUL_LOHI;
2746 } else if (HasUMUL_LOHI && !HasMULHU) {
2747 OpToUse = ISD::UMUL_LOHI;
2748 } else if (HasSMUL_LOHI) {
2749 OpToUse = ISD::SMUL_LOHI;
2750 } else if (HasUMUL_LOHI) {
2751 OpToUse = ISD::UMUL_LOHI;
2754 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
2758 if (Node->getOpcode() == ISD::MULHS &&
2759 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
2760 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2763 if (Node->getOpcode() == ISD::MULHU &&
2764 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
2765 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2768 if (Node->getOpcode() == ISD::SDIV &&
2769 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
2770 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2773 if (Node->getOpcode() == ISD::UDIV &&
2774 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
2775 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2779 // Check to see if we have a libcall for this operator.
2780 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2781 bool isSigned = false;
2782 switch (Node->getOpcode()) {
2785 if (VT == MVT::i32) {
2786 LC = Node->getOpcode() == ISD::UDIV
2787 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2788 isSigned = Node->getOpcode() == ISD::SDIV;
2792 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
2793 RTLIB::POW_PPCF128);
2797 if (LC != RTLIB::UNKNOWN_LIBCALL) {
2799 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2803 assert(MVT::isVector(Node->getValueType(0)) &&
2804 "Cannot expand this binary operator!");
2805 // Expand the operation into a bunch of nasty scalar code.
2806 Result = LegalizeOp(UnrollVectorOp(Op));
2809 case TargetLowering::Promote: {
2810 switch (Node->getOpcode()) {
2811 default: assert(0 && "Do not know how to promote this BinOp!");
2815 MVT::ValueType OVT = Node->getValueType(0);
2816 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2817 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2818 // Bit convert each of the values to the new type.
2819 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2820 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2821 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2822 // Bit convert the result back the original type.
2823 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2831 case ISD::SMUL_LOHI:
2832 case ISD::UMUL_LOHI:
2835 // These nodes will only be produced by target-specific lowering, so
2836 // they shouldn't be here if they aren't legal.
2837 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2838 "This must be legal!");
2840 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2841 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2842 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2845 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2846 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2847 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2848 case Expand: assert(0 && "Not possible");
2850 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2853 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2857 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2859 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2860 default: assert(0 && "Operation not supported");
2861 case TargetLowering::Custom:
2862 Tmp1 = TLI.LowerOperation(Result, DAG);
2863 if (Tmp1.Val) Result = Tmp1;
2865 case TargetLowering::Legal: break;
2866 case TargetLowering::Expand: {
2867 // If this target supports fabs/fneg natively and select is cheap,
2868 // do this efficiently.
2869 if (!TLI.isSelectExpensive() &&
2870 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
2871 TargetLowering::Legal &&
2872 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
2873 TargetLowering::Legal) {
2874 // Get the sign bit of the RHS.
2875 MVT::ValueType IVT =
2876 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2877 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2878 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2879 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2880 // Get the absolute value of the result.
2881 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2882 // Select between the nabs and abs value based on the sign bit of
2884 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2885 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2888 Result = LegalizeOp(Result);
2892 // Otherwise, do bitwise ops!
2893 MVT::ValueType NVT =
2894 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
2895 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
2896 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
2897 Result = LegalizeOp(Result);
2905 Tmp1 = LegalizeOp(Node->getOperand(0));
2906 Tmp2 = LegalizeOp(Node->getOperand(1));
2907 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2908 // Since this produces two values, make sure to remember that we legalized
2910 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2911 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2916 Tmp1 = LegalizeOp(Node->getOperand(0));
2917 Tmp2 = LegalizeOp(Node->getOperand(1));
2918 Tmp3 = LegalizeOp(Node->getOperand(2));
2919 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2920 // Since this produces two values, make sure to remember that we legalized
2922 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2923 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2926 case ISD::BUILD_PAIR: {
2927 MVT::ValueType PairTy = Node->getValueType(0);
2928 // TODO: handle the case where the Lo and Hi operands are not of legal type
2929 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2930 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2931 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2932 case TargetLowering::Promote:
2933 case TargetLowering::Custom:
2934 assert(0 && "Cannot promote/custom this yet!");
2935 case TargetLowering::Legal:
2936 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2937 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2939 case TargetLowering::Expand:
2940 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2941 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2942 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2943 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2944 TLI.getShiftAmountTy()));
2945 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2954 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2955 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2957 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2958 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2959 case TargetLowering::Custom:
2962 case TargetLowering::Legal:
2963 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2965 Tmp1 = TLI.LowerOperation(Result, DAG);
2966 if (Tmp1.Val) Result = Tmp1;
2969 case TargetLowering::Expand: {
2970 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2971 bool isSigned = DivOpc == ISD::SDIV;
2972 MVT::ValueType VT = Node->getValueType(0);
2974 // See if remainder can be lowered using two-result operations.
2975 SDVTList VTs = DAG.getVTList(VT, VT);
2976 if (Node->getOpcode() == ISD::SREM &&
2977 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
2978 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
2981 if (Node->getOpcode() == ISD::UREM &&
2982 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
2983 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
2987 if (MVT::isInteger(VT)) {
2988 if (TLI.getOperationAction(DivOpc, VT) ==
2989 TargetLowering::Legal) {
2991 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2992 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2993 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2994 } else if (MVT::isVector(VT)) {
2995 Result = LegalizeOp(UnrollVectorOp(Op));
2997 assert(VT == MVT::i32 &&
2998 "Cannot expand this binary operator!");
2999 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3000 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3002 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3005 assert(MVT::isFloatingPoint(VT) &&
3006 "remainder op must have integer or floating-point type");
3007 if (MVT::isVector(VT)) {
3008 Result = LegalizeOp(UnrollVectorOp(Op));
3010 // Floating point mod -> fmod libcall.
3011 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3012 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3014 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3015 false/*sign irrelevant*/, Dummy);
3023 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3024 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3026 MVT::ValueType VT = Node->getValueType(0);
3027 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3028 default: assert(0 && "This action is not supported yet!");
3029 case TargetLowering::Custom:
3032 case TargetLowering::Legal:
3033 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3034 Result = Result.getValue(0);
3035 Tmp1 = Result.getValue(1);
3038 Tmp2 = TLI.LowerOperation(Result, DAG);
3040 Result = LegalizeOp(Tmp2);
3041 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3045 case TargetLowering::Expand: {
3046 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3047 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3048 SV->getValue(), SV->getOffset());
3049 // Increment the pointer, VAList, to the next vaarg
3050 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3051 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3052 TLI.getPointerTy()));
3053 // Store the incremented VAList to the legalized pointer
3054 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3056 // Load the actual argument out of the pointer VAList
3057 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3058 Tmp1 = LegalizeOp(Result.getValue(1));
3059 Result = LegalizeOp(Result);
3063 // Since VAARG produces two values, make sure to remember that we
3064 // legalized both of them.
3065 AddLegalizedOperand(SDOperand(Node, 0), Result);
3066 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3067 return Op.ResNo ? Tmp1 : Result;
3071 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3072 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3073 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3075 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3076 default: assert(0 && "This action is not supported yet!");
3077 case TargetLowering::Custom:
3080 case TargetLowering::Legal:
3081 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3082 Node->getOperand(3), Node->getOperand(4));
3084 Tmp1 = TLI.LowerOperation(Result, DAG);
3085 if (Tmp1.Val) Result = Tmp1;
3088 case TargetLowering::Expand:
3089 // This defaults to loading a pointer from the input and storing it to the
3090 // output, returning the chain.
3091 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
3092 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
3093 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
3095 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
3102 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3103 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3105 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3106 default: assert(0 && "This action is not supported yet!");
3107 case TargetLowering::Custom:
3110 case TargetLowering::Legal:
3111 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3113 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3114 if (Tmp1.Val) Result = Tmp1;
3117 case TargetLowering::Expand:
3118 Result = Tmp1; // Default to a no-op, return the chain
3124 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3125 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3127 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3129 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3130 default: assert(0 && "This action is not supported yet!");
3131 case TargetLowering::Legal: break;
3132 case TargetLowering::Custom:
3133 Tmp1 = TLI.LowerOperation(Result, DAG);
3134 if (Tmp1.Val) Result = Tmp1;
3141 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3142 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3143 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3144 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3146 assert(0 && "ROTL/ROTR legalize operation not supported");
3148 case TargetLowering::Legal:
3150 case TargetLowering::Custom:
3151 Tmp1 = TLI.LowerOperation(Result, DAG);
3152 if (Tmp1.Val) Result = Tmp1;
3154 case TargetLowering::Promote:
3155 assert(0 && "Do not know how to promote ROTL/ROTR");
3157 case TargetLowering::Expand:
3158 assert(0 && "Do not know how to expand ROTL/ROTR");
3164 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3165 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3166 case TargetLowering::Custom:
3167 assert(0 && "Cannot custom legalize this yet!");
3168 case TargetLowering::Legal:
3169 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3171 case TargetLowering::Promote: {
3172 MVT::ValueType OVT = Tmp1.getValueType();
3173 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3174 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
3176 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3177 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3178 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3179 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3182 case TargetLowering::Expand:
3183 Result = ExpandBSWAP(Tmp1);
3191 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3192 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3193 case TargetLowering::Custom:
3194 case TargetLowering::Legal:
3195 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3196 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3197 TargetLowering::Custom) {
3198 Tmp1 = TLI.LowerOperation(Result, DAG);
3204 case TargetLowering::Promote: {
3205 MVT::ValueType OVT = Tmp1.getValueType();
3206 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3208 // Zero extend the argument.
3209 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3210 // Perform the larger operation, then subtract if needed.
3211 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3212 switch (Node->getOpcode()) {
3217 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3218 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3219 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3221 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3222 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
3225 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3226 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3227 DAG.getConstant(MVT::getSizeInBits(NVT) -
3228 MVT::getSizeInBits(OVT), NVT));
3233 case TargetLowering::Expand:
3234 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3245 Tmp1 = LegalizeOp(Node->getOperand(0));
3246 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3247 case TargetLowering::Promote:
3248 case TargetLowering::Custom:
3251 case TargetLowering::Legal:
3252 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3254 Tmp1 = TLI.LowerOperation(Result, DAG);
3255 if (Tmp1.Val) Result = Tmp1;
3258 case TargetLowering::Expand:
3259 switch (Node->getOpcode()) {
3260 default: assert(0 && "Unreachable!");
3262 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3263 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3264 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3267 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3268 MVT::ValueType VT = Node->getValueType(0);
3269 Tmp2 = DAG.getConstantFP(0.0, VT);
3270 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
3271 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3272 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3278 MVT::ValueType VT = Node->getValueType(0);
3280 // Expand unsupported unary vector operators by unrolling them.
3281 if (MVT::isVector(VT)) {
3282 Result = LegalizeOp(UnrollVectorOp(Op));
3286 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3287 switch(Node->getOpcode()) {
3289 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3290 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3293 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3294 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3297 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3298 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3300 default: assert(0 && "Unreachable!");
3303 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3304 false/*sign irrelevant*/, Dummy);
3312 MVT::ValueType VT = Node->getValueType(0);
3314 // Expand unsupported unary vector operators by unrolling them.
3315 if (MVT::isVector(VT)) {
3316 Result = LegalizeOp(UnrollVectorOp(Op));
3320 // We always lower FPOWI into a libcall. No target support for it yet.
3321 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3322 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3324 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3325 false/*sign irrelevant*/, Dummy);
3328 case ISD::BIT_CONVERT:
3329 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3330 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3331 Node->getValueType(0));
3332 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3333 // The input has to be a vector type, we have to either scalarize it, pack
3334 // it, or convert it based on whether the input vector type is legal.
3335 SDNode *InVal = Node->getOperand(0).Val;
3336 int InIx = Node->getOperand(0).ResNo;
3337 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
3338 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
3340 // Figure out if there is a simple type corresponding to this Vector
3341 // type. If so, convert to the vector type.
3342 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3343 if (TLI.isTypeLegal(TVT)) {
3344 // Turn this into a bit convert of the vector input.
3345 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3346 LegalizeOp(Node->getOperand(0)));
3348 } else if (NumElems == 1) {
3349 // Turn this into a bit convert of the scalar input.
3350 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3351 ScalarizeVectorOp(Node->getOperand(0)));
3354 // FIXME: UNIMP! Store then reload
3355 assert(0 && "Cast from unsupported vector type not implemented yet!");
3358 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3359 Node->getOperand(0).getValueType())) {
3360 default: assert(0 && "Unknown operation action!");
3361 case TargetLowering::Expand:
3362 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3363 Node->getValueType(0));
3365 case TargetLowering::Legal:
3366 Tmp1 = LegalizeOp(Node->getOperand(0));
3367 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3373 // Conversion operators. The source and destination have different types.
3374 case ISD::SINT_TO_FP:
3375 case ISD::UINT_TO_FP: {
3376 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3377 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3379 switch (TLI.getOperationAction(Node->getOpcode(),
3380 Node->getOperand(0).getValueType())) {
3381 default: assert(0 && "Unknown operation action!");
3382 case TargetLowering::Custom:
3385 case TargetLowering::Legal:
3386 Tmp1 = LegalizeOp(Node->getOperand(0));
3387 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3389 Tmp1 = TLI.LowerOperation(Result, DAG);
3390 if (Tmp1.Val) Result = Tmp1;
3393 case TargetLowering::Expand:
3394 Result = ExpandLegalINT_TO_FP(isSigned,
3395 LegalizeOp(Node->getOperand(0)),
3396 Node->getValueType(0));
3398 case TargetLowering::Promote:
3399 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3400 Node->getValueType(0),
3406 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3407 Node->getValueType(0), Node->getOperand(0));
3410 Tmp1 = PromoteOp(Node->getOperand(0));
3412 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3413 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3415 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3416 Node->getOperand(0).getValueType());
3418 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3419 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3425 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3427 Tmp1 = LegalizeOp(Node->getOperand(0));
3428 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3431 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3433 // Since the result is legal, we should just be able to truncate the low
3434 // part of the source.
3435 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3438 Result = PromoteOp(Node->getOperand(0));
3439 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3444 case ISD::FP_TO_SINT:
3445 case ISD::FP_TO_UINT:
3446 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3448 Tmp1 = LegalizeOp(Node->getOperand(0));
3450 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3451 default: assert(0 && "Unknown operation action!");
3452 case TargetLowering::Custom:
3455 case TargetLowering::Legal:
3456 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3458 Tmp1 = TLI.LowerOperation(Result, DAG);
3459 if (Tmp1.Val) Result = Tmp1;
3462 case TargetLowering::Promote:
3463 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3464 Node->getOpcode() == ISD::FP_TO_SINT);
3466 case TargetLowering::Expand:
3467 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3468 SDOperand True, False;
3469 MVT::ValueType VT = Node->getOperand(0).getValueType();
3470 MVT::ValueType NVT = Node->getValueType(0);
3471 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1;
3472 const uint64_t zero[] = {0, 0};
3473 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3474 uint64_t x = 1ULL << ShiftAmt;
3475 (void)apf.convertFromZeroExtendedInteger
3476 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven);
3477 Tmp2 = DAG.getConstantFP(apf, VT);
3478 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3479 Node->getOperand(0), Tmp2, ISD::SETLT);
3480 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3481 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3482 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3484 False = DAG.getNode(ISD::XOR, NVT, False,
3485 DAG.getConstant(1ULL << ShiftAmt, NVT));
3486 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3489 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3495 MVT::ValueType VT = Op.getValueType();
3496 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3497 // Convert ppcf128 to i32
3498 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3499 if (Node->getOpcode()==ISD::FP_TO_SINT)
3500 Result = DAG.getNode(ISD::FP_TO_SINT, VT,
3501 DAG.getNode(ISD::FP_ROUND, MVT::f64,
3502 (DAG.getNode(ISD::FP_ROUND_INREG,
3503 MVT::ppcf128, Node->getOperand(0),
3504 DAG.getValueType(MVT::f64)))));
3506 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3507 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3508 Tmp2 = DAG.getConstantFP(apf, OVT);
3509 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3510 // FIXME: generated code sucks.
3511 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3512 DAG.getNode(ISD::ADD, MVT::i32,
3513 DAG.getNode(ISD::FP_TO_SINT, VT,
3514 DAG.getNode(ISD::FSUB, OVT,
3515 Node->getOperand(0), Tmp2)),
3516 DAG.getConstant(0x80000000, MVT::i32)),
3517 DAG.getNode(ISD::FP_TO_SINT, VT,
3518 Node->getOperand(0)),
3519 DAG.getCondCode(ISD::SETGE));
3523 // Convert f32 / f64 to i32 / i64.
3524 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3525 switch (Node->getOpcode()) {
3526 case ISD::FP_TO_SINT: {
3527 if (OVT == MVT::f32)
3528 LC = (VT == MVT::i32)
3529 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3530 else if (OVT == MVT::f64)
3531 LC = (VT == MVT::i32)
3532 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3533 else if (OVT == MVT::f80) {
3534 assert(VT == MVT::i64);
3535 LC = RTLIB::FPTOSINT_F80_I64;
3537 else if (OVT == MVT::ppcf128) {
3538 assert(VT == MVT::i64);
3539 LC = RTLIB::FPTOSINT_PPCF128_I64;
3543 case ISD::FP_TO_UINT: {
3544 if (OVT == MVT::f32)
3545 LC = (VT == MVT::i32)
3546 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3547 else if (OVT == MVT::f64)
3548 LC = (VT == MVT::i32)
3549 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3550 else if (OVT == MVT::f80) {
3551 LC = (VT == MVT::i32)
3552 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64;
3554 else if (OVT == MVT::ppcf128) {
3555 assert(VT == MVT::i64);
3556 LC = RTLIB::FPTOUINT_PPCF128_I64;
3560 default: assert(0 && "Unreachable!");
3563 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3564 false/*sign irrelevant*/, Dummy);
3568 Tmp1 = PromoteOp(Node->getOperand(0));
3569 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3570 Result = LegalizeOp(Result);
3575 case ISD::FP_EXTEND: {
3576 MVT::ValueType DstVT = Op.getValueType();
3577 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3578 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3579 // The only other way we can lower this is to turn it into a STORE,
3580 // LOAD pair, targetting a temporary location (a stack slot).
3581 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3585 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3586 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3588 Tmp1 = LegalizeOp(Node->getOperand(0));
3589 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3592 Tmp1 = PromoteOp(Node->getOperand(0));
3593 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3597 case ISD::FP_ROUND: {
3598 MVT::ValueType DstVT = Op.getValueType();
3599 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3600 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3601 if (SrcVT == MVT::ppcf128) {
3603 ExpandOp(Node->getOperand(0), Lo, Hi);
3604 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Hi);
3607 // The only other way we can lower this is to turn it into a STORE,
3608 // LOAD pair, targetting a temporary location (a stack slot).
3609 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3614 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3615 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3617 Tmp1 = LegalizeOp(Node->getOperand(0));
3618 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3621 Tmp1 = PromoteOp(Node->getOperand(0));
3622 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1);
3626 case ISD::ANY_EXTEND:
3627 case ISD::ZERO_EXTEND:
3628 case ISD::SIGN_EXTEND:
3629 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3630 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3632 Tmp1 = LegalizeOp(Node->getOperand(0));
3633 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3636 switch (Node->getOpcode()) {
3637 case ISD::ANY_EXTEND:
3638 Tmp1 = PromoteOp(Node->getOperand(0));
3639 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3641 case ISD::ZERO_EXTEND:
3642 Result = PromoteOp(Node->getOperand(0));
3643 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3644 Result = DAG.getZeroExtendInReg(Result,
3645 Node->getOperand(0).getValueType());
3647 case ISD::SIGN_EXTEND:
3648 Result = PromoteOp(Node->getOperand(0));
3649 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3650 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3652 DAG.getValueType(Node->getOperand(0).getValueType()));
3657 case ISD::FP_ROUND_INREG:
3658 case ISD::SIGN_EXTEND_INREG: {
3659 Tmp1 = LegalizeOp(Node->getOperand(0));
3660 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3662 // If this operation is not supported, convert it to a shl/shr or load/store
3664 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3665 default: assert(0 && "This action not supported for this op yet!");
3666 case TargetLowering::Legal:
3667 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3669 case TargetLowering::Expand:
3670 // If this is an integer extend and shifts are supported, do that.
3671 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3672 // NOTE: we could fall back on load/store here too for targets without
3673 // SAR. However, it is doubtful that any exist.
3674 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3675 MVT::getSizeInBits(ExtraVT);
3676 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3677 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3678 Node->getOperand(0), ShiftCst);
3679 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3681 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3682 // The only way we can lower this is to turn it into a TRUNCSTORE,
3683 // EXTLOAD pair, targetting a temporary location (a stack slot).
3685 // NOTE: there is a choice here between constantly creating new stack
3686 // slots and always reusing the same one. We currently always create
3687 // new ones, as reuse may inhibit scheduling.
3688 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3689 Node->getValueType(0));
3691 assert(0 && "Unknown op");
3697 case ISD::TRAMPOLINE: {
3699 for (unsigned i = 0; i != 6; ++i)
3700 Ops[i] = LegalizeOp(Node->getOperand(i));
3701 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3702 // The only option for this node is to custom lower it.
3703 Result = TLI.LowerOperation(Result, DAG);
3704 assert(Result.Val && "Should always custom lower!");
3706 // Since trampoline produces two values, make sure to remember that we
3707 // legalized both of them.
3708 Tmp1 = LegalizeOp(Result.getValue(1));
3709 Result = LegalizeOp(Result);
3710 AddLegalizedOperand(SDOperand(Node, 0), Result);
3711 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3712 return Op.ResNo ? Tmp1 : Result;
3714 case ISD::FLT_ROUNDS: {
3715 MVT::ValueType VT = Node->getValueType(0);
3716 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3717 default: assert(0 && "This action not supported for this op yet!");
3718 case TargetLowering::Custom:
3719 Result = TLI.LowerOperation(Op, DAG);
3720 if (Result.Val) break;
3722 case TargetLowering::Legal:
3723 // If this operation is not supported, lower it to constant 1
3724 Result = DAG.getConstant(1, VT);
3729 MVT::ValueType VT = Node->getValueType(0);
3730 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3731 default: assert(0 && "This action not supported for this op yet!");
3732 case TargetLowering::Legal:
3733 Tmp1 = LegalizeOp(Node->getOperand(0));
3734 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3736 case TargetLowering::Custom:
3737 Result = TLI.LowerOperation(Op, DAG);
3738 if (Result.Val) break;
3740 case TargetLowering::Expand:
3741 // If this operation is not supported, lower it to 'abort()' call
3742 Tmp1 = LegalizeOp(Node->getOperand(0));
3743 TargetLowering::ArgListTy Args;
3744 std::pair<SDOperand,SDOperand> CallResult =
3745 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
3746 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3748 Result = CallResult.second;
3755 assert(Result.getValueType() == Op.getValueType() &&
3756 "Bad legalization!");
3758 // Make sure that the generated code is itself legal.
3760 Result = LegalizeOp(Result);
3762 // Note that LegalizeOp may be reentered even from single-use nodes, which
3763 // means that we always must cache transformed nodes.
3764 AddLegalizedOperand(Op, Result);
3768 /// PromoteOp - Given an operation that produces a value in an invalid type,
3769 /// promote it to compute the value into a larger type. The produced value will
3770 /// have the correct bits for the low portion of the register, but no guarantee
3771 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3772 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3773 MVT::ValueType VT = Op.getValueType();
3774 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3775 assert(getTypeAction(VT) == Promote &&
3776 "Caller should expand or legalize operands that are not promotable!");
3777 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3778 "Cannot promote to smaller type!");
3780 SDOperand Tmp1, Tmp2, Tmp3;
3782 SDNode *Node = Op.Val;
3784 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3785 if (I != PromotedNodes.end()) return I->second;
3787 switch (Node->getOpcode()) {
3788 case ISD::CopyFromReg:
3789 assert(0 && "CopyFromReg must be legal!");
3792 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
3794 assert(0 && "Do not know how to promote this operator!");
3797 Result = DAG.getNode(ISD::UNDEF, NVT);
3801 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3803 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3804 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3806 case ISD::ConstantFP:
3807 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3808 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3812 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3813 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3814 Node->getOperand(1), Node->getOperand(2));
3818 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3820 Result = LegalizeOp(Node->getOperand(0));
3821 assert(Result.getValueType() >= NVT &&
3822 "This truncation doesn't make sense!");
3823 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3824 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3827 // The truncation is not required, because we don't guarantee anything
3828 // about high bits anyway.
3829 Result = PromoteOp(Node->getOperand(0));
3832 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3833 // Truncate the low part of the expanded value to the result type
3834 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3837 case ISD::SIGN_EXTEND:
3838 case ISD::ZERO_EXTEND:
3839 case ISD::ANY_EXTEND:
3840 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3841 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3843 // Input is legal? Just do extend all the way to the larger type.
3844 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3847 // Promote the reg if it's smaller.
3848 Result = PromoteOp(Node->getOperand(0));
3849 // The high bits are not guaranteed to be anything. Insert an extend.
3850 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3851 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3852 DAG.getValueType(Node->getOperand(0).getValueType()));
3853 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3854 Result = DAG.getZeroExtendInReg(Result,
3855 Node->getOperand(0).getValueType());
3859 case ISD::BIT_CONVERT:
3860 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3861 Node->getValueType(0));
3862 Result = PromoteOp(Result);
3865 case ISD::FP_EXTEND:
3866 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3868 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3869 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3870 case Promote: assert(0 && "Unreachable with 2 FP types!");
3872 // Input is legal? Do an FP_ROUND_INREG.
3873 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3874 DAG.getValueType(VT));
3879 case ISD::SINT_TO_FP:
3880 case ISD::UINT_TO_FP:
3881 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3883 // No extra round required here.
3884 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3888 Result = PromoteOp(Node->getOperand(0));
3889 if (Node->getOpcode() == ISD::SINT_TO_FP)
3890 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3892 DAG.getValueType(Node->getOperand(0).getValueType()));
3894 Result = DAG.getZeroExtendInReg(Result,
3895 Node->getOperand(0).getValueType());
3896 // No extra round required here.
3897 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3900 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3901 Node->getOperand(0));
3902 // Round if we cannot tolerate excess precision.
3903 if (NoExcessFPPrecision)
3904 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3905 DAG.getValueType(VT));
3910 case ISD::SIGN_EXTEND_INREG:
3911 Result = PromoteOp(Node->getOperand(0));
3912 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3913 Node->getOperand(1));
3915 case ISD::FP_TO_SINT:
3916 case ISD::FP_TO_UINT:
3917 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3920 Tmp1 = Node->getOperand(0);
3923 // The input result is prerounded, so we don't have to do anything
3925 Tmp1 = PromoteOp(Node->getOperand(0));
3928 // If we're promoting a UINT to a larger size, check to see if the new node
3929 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3930 // we can use that instead. This allows us to generate better code for
3931 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3932 // legal, such as PowerPC.
3933 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3934 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3935 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3936 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3937 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3939 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3945 Tmp1 = PromoteOp(Node->getOperand(0));
3946 assert(Tmp1.getValueType() == NVT);
3947 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3948 // NOTE: we do not have to do any extra rounding here for
3949 // NoExcessFPPrecision, because we know the input will have the appropriate
3950 // precision, and these operations don't modify precision at all.
3956 Tmp1 = PromoteOp(Node->getOperand(0));
3957 assert(Tmp1.getValueType() == NVT);
3958 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3959 if (NoExcessFPPrecision)
3960 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3961 DAG.getValueType(VT));
3965 // Promote f32 powi to f64 powi. Note that this could insert a libcall
3966 // directly as well, which may be better.
3967 Tmp1 = PromoteOp(Node->getOperand(0));
3968 assert(Tmp1.getValueType() == NVT);
3969 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
3970 if (NoExcessFPPrecision)
3971 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3972 DAG.getValueType(VT));
3982 // The input may have strange things in the top bits of the registers, but
3983 // these operations don't care. They may have weird bits going out, but
3984 // that too is okay if they are integer operations.
3985 Tmp1 = PromoteOp(Node->getOperand(0));
3986 Tmp2 = PromoteOp(Node->getOperand(1));
3987 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3988 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3993 Tmp1 = PromoteOp(Node->getOperand(0));
3994 Tmp2 = PromoteOp(Node->getOperand(1));
3995 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3996 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3998 // Floating point operations will give excess precision that we may not be
3999 // able to tolerate. If we DO allow excess precision, just leave it,
4000 // otherwise excise it.
4001 // FIXME: Why would we need to round FP ops more than integer ones?
4002 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4003 if (NoExcessFPPrecision)
4004 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4005 DAG.getValueType(VT));
4010 // These operators require that their input be sign extended.
4011 Tmp1 = PromoteOp(Node->getOperand(0));
4012 Tmp2 = PromoteOp(Node->getOperand(1));
4013 if (MVT::isInteger(NVT)) {
4014 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4015 DAG.getValueType(VT));
4016 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4017 DAG.getValueType(VT));
4019 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4021 // Perform FP_ROUND: this is probably overly pessimistic.
4022 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
4023 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4024 DAG.getValueType(VT));
4028 case ISD::FCOPYSIGN:
4029 // These operators require that their input be fp extended.
4030 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4032 Tmp1 = LegalizeOp(Node->getOperand(0));
4035 Tmp1 = PromoteOp(Node->getOperand(0));
4038 assert(0 && "not implemented");
4040 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4042 Tmp2 = LegalizeOp(Node->getOperand(1));
4045 Tmp2 = PromoteOp(Node->getOperand(1));
4048 assert(0 && "not implemented");
4050 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4052 // Perform FP_ROUND: this is probably overly pessimistic.
4053 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4054 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4055 DAG.getValueType(VT));
4060 // These operators require that their input be zero extended.
4061 Tmp1 = PromoteOp(Node->getOperand(0));
4062 Tmp2 = PromoteOp(Node->getOperand(1));
4063 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
4064 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4065 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4066 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4070 Tmp1 = PromoteOp(Node->getOperand(0));
4071 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4074 // The input value must be properly sign extended.
4075 Tmp1 = PromoteOp(Node->getOperand(0));
4076 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4077 DAG.getValueType(VT));
4078 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4081 // The input value must be properly zero extended.
4082 Tmp1 = PromoteOp(Node->getOperand(0));
4083 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4084 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4088 Tmp1 = Node->getOperand(0); // Get the chain.
4089 Tmp2 = Node->getOperand(1); // Get the pointer.
4090 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4091 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4092 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
4094 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
4095 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
4096 SV->getValue(), SV->getOffset());
4097 // Increment the pointer, VAList, to the next vaarg
4098 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4099 DAG.getConstant(MVT::getSizeInBits(VT)/8,
4100 TLI.getPointerTy()));
4101 // Store the incremented VAList to the legalized pointer
4102 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
4104 // Load the actual argument out of the pointer VAList
4105 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4107 // Remember that we legalized the chain.
4108 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4112 LoadSDNode *LD = cast<LoadSDNode>(Node);
4113 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4114 ? ISD::EXTLOAD : LD->getExtensionType();
4115 Result = DAG.getExtLoad(ExtType, NVT,
4116 LD->getChain(), LD->getBasePtr(),
4117 LD->getSrcValue(), LD->getSrcValueOffset(),
4120 LD->getAlignment());
4121 // Remember that we legalized the chain.
4122 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4126 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4127 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4128 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
4130 case ISD::SELECT_CC:
4131 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4132 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4133 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4134 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4137 Tmp1 = Node->getOperand(0);
4138 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4139 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4140 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4141 DAG.getConstant(MVT::getSizeInBits(NVT) -
4142 MVT::getSizeInBits(VT),
4143 TLI.getShiftAmountTy()));
4148 // Zero extend the argument
4149 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4150 // Perform the larger operation, then subtract if needed.
4151 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4152 switch(Node->getOpcode()) {
4157 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4158 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
4159 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
4161 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4162 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
4165 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4166 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4167 DAG.getConstant(MVT::getSizeInBits(NVT) -
4168 MVT::getSizeInBits(VT), NVT));
4172 case ISD::EXTRACT_SUBVECTOR:
4173 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4175 case ISD::EXTRACT_VECTOR_ELT:
4176 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4180 assert(Result.Val && "Didn't set a result!");
4182 // Make sure the result is itself legal.
4183 Result = LegalizeOp(Result);
4185 // Remember that we promoted this!
4186 AddPromotedOperand(Op, Result);
4190 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4191 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4192 /// based on the vector type. The return type of this matches the element type
4193 /// of the vector, which may not be legal for the target.
4194 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4195 // We know that operand #0 is the Vec vector. If the index is a constant
4196 // or if the invec is a supported hardware type, we can use it. Otherwise,
4197 // lower to a store then an indexed load.
4198 SDOperand Vec = Op.getOperand(0);
4199 SDOperand Idx = Op.getOperand(1);
4201 MVT::ValueType TVT = Vec.getValueType();
4202 unsigned NumElems = MVT::getVectorNumElements(TVT);
4204 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4205 default: assert(0 && "This action is not supported yet!");
4206 case TargetLowering::Custom: {
4207 Vec = LegalizeOp(Vec);
4208 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4209 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4214 case TargetLowering::Legal:
4215 if (isTypeLegal(TVT)) {
4216 Vec = LegalizeOp(Vec);
4217 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4221 case TargetLowering::Expand:
4225 if (NumElems == 1) {
4226 // This must be an access of the only element. Return it.
4227 Op = ScalarizeVectorOp(Vec);
4228 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4229 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4231 SplitVectorOp(Vec, Lo, Hi);
4232 if (CIdx->getValue() < NumElems/2) {
4236 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2,
4237 Idx.getValueType());
4240 // It's now an extract from the appropriate high or low part. Recurse.
4241 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4242 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4244 // Store the value to a temporary stack slot, then LOAD the scalar
4245 // element back out.
4246 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4247 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4249 // Add the offset to the index.
4250 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
4251 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4252 DAG.getConstant(EltSize, Idx.getValueType()));
4254 if (MVT::getSizeInBits(Idx.getValueType()) >
4255 MVT::getSizeInBits(TLI.getPointerTy()))
4256 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4258 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4260 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4262 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4267 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4268 /// we assume the operation can be split if it is not already legal.
4269 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4270 // We know that operand #0 is the Vec vector. For now we assume the index
4271 // is a constant and that the extracted result is a supported hardware type.
4272 SDOperand Vec = Op.getOperand(0);
4273 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4275 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
4277 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
4278 // This must be an access of the desired vector length. Return it.
4282 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4284 SplitVectorOp(Vec, Lo, Hi);
4285 if (CIdx->getValue() < NumElems/2) {
4289 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4292 // It's now an extract from the appropriate high or low part. Recurse.
4293 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4294 return ExpandEXTRACT_SUBVECTOR(Op);
4297 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4298 /// with condition CC on the current target. This usually involves legalizing
4299 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4300 /// there may be no choice but to create a new SetCC node to represent the
4301 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4302 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4303 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4306 SDOperand Tmp1, Tmp2, Tmp3, Result;
4308 switch (getTypeAction(LHS.getValueType())) {
4310 Tmp1 = LegalizeOp(LHS); // LHS
4311 Tmp2 = LegalizeOp(RHS); // RHS
4314 Tmp1 = PromoteOp(LHS); // LHS
4315 Tmp2 = PromoteOp(RHS); // RHS
4317 // If this is an FP compare, the operands have already been extended.
4318 if (MVT::isInteger(LHS.getValueType())) {
4319 MVT::ValueType VT = LHS.getValueType();
4320 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4322 // Otherwise, we have to insert explicit sign or zero extends. Note
4323 // that we could insert sign extends for ALL conditions, but zero extend
4324 // is cheaper on many machines (an AND instead of two shifts), so prefer
4326 switch (cast<CondCodeSDNode>(CC)->get()) {
4327 default: assert(0 && "Unknown integer comparison!");
4334 // ALL of these operations will work if we either sign or zero extend
4335 // the operands (including the unsigned comparisons!). Zero extend is
4336 // usually a simpler/cheaper operation, so prefer it.
4337 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4338 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4344 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4345 DAG.getValueType(VT));
4346 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4347 DAG.getValueType(VT));
4353 MVT::ValueType VT = LHS.getValueType();
4354 if (VT == MVT::f32 || VT == MVT::f64) {
4355 // Expand into one or more soft-fp libcall(s).
4356 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4357 switch (cast<CondCodeSDNode>(CC)->get()) {
4360 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4364 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4368 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4372 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4376 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4380 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4383 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4386 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4389 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4390 switch (cast<CondCodeSDNode>(CC)->get()) {
4392 // SETONE = SETOLT | SETOGT
4393 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4396 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4399 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4402 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4405 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4408 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4410 default: assert(0 && "Unsupported FP setcc!");
4415 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4416 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4417 false /*sign irrelevant*/, Dummy);
4418 Tmp2 = DAG.getConstant(0, MVT::i32);
4419 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4420 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4421 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4422 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4423 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4424 false /*sign irrelevant*/, Dummy);
4425 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4426 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4427 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4435 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4436 ExpandOp(LHS, LHSLo, LHSHi);
4437 ExpandOp(RHS, RHSLo, RHSHi);
4438 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4440 if (VT==MVT::ppcf128) {
4441 // FIXME: This generated code sucks. We want to generate
4442 // FCMP crN, hi1, hi2
4444 // FCMP crN, lo1, lo2
4445 // The following can be improved, but not that much.
4446 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4447 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
4448 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4449 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
4450 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
4451 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4452 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4461 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4462 if (RHSCST->isAllOnesValue()) {
4463 // Comparison to -1.
4464 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4469 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4470 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4471 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4472 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4475 // If this is a comparison of the sign bit, just look at the top part.
4477 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4478 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4479 CST->getValue() == 0) || // X < 0
4480 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4481 CST->isAllOnesValue())) { // X > -1
4487 // FIXME: This generated code sucks.
4488 ISD::CondCode LowCC;
4490 default: assert(0 && "Unknown integer setcc!");
4492 case ISD::SETULT: LowCC = ISD::SETULT; break;
4494 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4496 case ISD::SETULE: LowCC = ISD::SETULE; break;
4498 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4501 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4502 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4503 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4505 // NOTE: on targets without efficient SELECT of bools, we can always use
4506 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4507 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4508 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4509 false, DagCombineInfo);
4511 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4512 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4513 CCCode, false, DagCombineInfo);
4515 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC);
4517 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4518 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4519 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4520 (Tmp2C && Tmp2C->getValue() == 0 &&
4521 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4522 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4523 (Tmp2C && Tmp2C->getValue() == 1 &&
4524 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4525 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4526 // low part is known false, returns high part.
4527 // For LE / GE, if high part is known false, ignore the low part.
4528 // For LT / GT, if high part is known true, ignore the low part.
4532 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4533 ISD::SETEQ, false, DagCombineInfo);
4535 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4536 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4537 Result, Tmp1, Tmp2));
4548 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4549 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4550 /// a load from the stack slot to DestVT, extending it if needed.
4551 /// The resultant code need not be legal.
4552 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4553 MVT::ValueType SlotVT,
4554 MVT::ValueType DestVT) {
4555 // Create the stack frame object.
4556 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
4558 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType());
4559 unsigned SlotSize = MVT::getSizeInBits(SlotVT);
4560 unsigned DestSize = MVT::getSizeInBits(DestVT);
4562 // Emit a store to the stack slot. Use a truncstore if the input value is
4563 // later than DestVT.
4565 if (SrcSize > SlotSize)
4566 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0,SlotVT);
4568 assert(SrcSize == SlotSize && "Invalid store");
4569 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
4572 // Result is a load from the stack slot.
4573 if (SlotSize == DestSize)
4574 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4576 assert(SlotSize < DestSize && "Unknown extension!");
4577 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT);
4580 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4581 // Create a vector sized/aligned stack slot, store the value to element #0,
4582 // then load the whole vector back out.
4583 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4584 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4586 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
4590 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4591 /// support the operation, but do support the resultant vector type.
4592 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4594 // If the only non-undef value is the low element, turn this into a
4595 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4596 unsigned NumElems = Node->getNumOperands();
4597 bool isOnlyLowElement = true;
4598 SDOperand SplatValue = Node->getOperand(0);
4599 std::map<SDOperand, std::vector<unsigned> > Values;
4600 Values[SplatValue].push_back(0);
4601 bool isConstant = true;
4602 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4603 SplatValue.getOpcode() != ISD::UNDEF)
4606 for (unsigned i = 1; i < NumElems; ++i) {
4607 SDOperand V = Node->getOperand(i);
4608 Values[V].push_back(i);
4609 if (V.getOpcode() != ISD::UNDEF)
4610 isOnlyLowElement = false;
4611 if (SplatValue != V)
4612 SplatValue = SDOperand(0,0);
4614 // If this isn't a constant element or an undef, we can't use a constant
4616 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4617 V.getOpcode() != ISD::UNDEF)
4621 if (isOnlyLowElement) {
4622 // If the low element is an undef too, then this whole things is an undef.
4623 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4624 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4625 // Otherwise, turn this into a scalar_to_vector node.
4626 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4627 Node->getOperand(0));
4630 // If all elements are constants, create a load from the constant pool.
4632 MVT::ValueType VT = Node->getValueType(0);
4634 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4635 std::vector<Constant*> CV;
4636 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4637 if (ConstantFPSDNode *V =
4638 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4639 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4640 } else if (ConstantSDNode *V =
4641 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4642 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4644 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4645 CV.push_back(UndefValue::get(OpNTy));
4648 Constant *CP = ConstantVector::get(CV);
4649 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4650 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
4653 if (SplatValue.Val) { // Splat of one value?
4654 // Build the shuffle constant vector: <0, 0, 0, 0>
4655 MVT::ValueType MaskVT =
4656 MVT::getIntVectorWithNumElements(NumElems);
4657 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4658 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4659 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4660 &ZeroVec[0], ZeroVec.size());
4662 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4663 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4664 // Get the splatted value into the low element of a vector register.
4665 SDOperand LowValVec =
4666 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4668 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4669 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4670 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4675 // If there are only two unique elements, we may be able to turn this into a
4677 if (Values.size() == 2) {
4678 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4679 MVT::ValueType MaskVT =
4680 MVT::getIntVectorWithNumElements(NumElems);
4681 std::vector<SDOperand> MaskVec(NumElems);
4683 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4684 E = Values.end(); I != E; ++I) {
4685 for (std::vector<unsigned>::iterator II = I->second.begin(),
4686 EE = I->second.end(); II != EE; ++II)
4687 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4690 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4691 &MaskVec[0], MaskVec.size());
4693 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4694 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4695 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4696 SmallVector<SDOperand, 8> Ops;
4697 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4698 E = Values.end(); I != E; ++I) {
4699 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4703 Ops.push_back(ShuffleMask);
4705 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4706 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4707 &Ops[0], Ops.size());
4711 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4712 // aligned object on the stack, store each element into it, then load
4713 // the result as a vector.
4714 MVT::ValueType VT = Node->getValueType(0);
4715 // Create the stack frame object.
4716 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
4718 // Emit a store of each element to the stack slot.
4719 SmallVector<SDOperand, 8> Stores;
4720 unsigned TypeByteSize =
4721 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4722 // Store (in the right endianness) the elements to memory.
4723 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4724 // Ignore undef elements.
4725 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4727 unsigned Offset = TypeByteSize*i;
4729 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4730 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4732 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4736 SDOperand StoreChain;
4737 if (!Stores.empty()) // Not all undef elements?
4738 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4739 &Stores[0], Stores.size());
4741 StoreChain = DAG.getEntryNode();
4743 // Result is a load from the stack slot.
4744 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4747 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4748 SDOperand Op, SDOperand Amt,
4749 SDOperand &Lo, SDOperand &Hi) {
4750 // Expand the subcomponents.
4751 SDOperand LHSL, LHSH;
4752 ExpandOp(Op, LHSL, LHSH);
4754 SDOperand Ops[] = { LHSL, LHSH, Amt };
4755 MVT::ValueType VT = LHSL.getValueType();
4756 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4757 Hi = Lo.getValue(1);
4761 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4762 /// smaller elements. If we can't find a way that is more efficient than a
4763 /// libcall on this target, return false. Otherwise, return true with the
4764 /// low-parts expanded into Lo and Hi.
4765 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4766 SDOperand &Lo, SDOperand &Hi) {
4767 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4768 "This is not a shift!");
4770 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4771 SDOperand ShAmt = LegalizeOp(Amt);
4772 MVT::ValueType ShTy = ShAmt.getValueType();
4773 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4774 unsigned NVTBits = MVT::getSizeInBits(NVT);
4776 // Handle the case when Amt is an immediate.
4777 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4778 unsigned Cst = CN->getValue();
4779 // Expand the incoming operand to be shifted, so that we have its parts
4781 ExpandOp(Op, InL, InH);
4785 Lo = DAG.getConstant(0, NVT);
4786 Hi = DAG.getConstant(0, NVT);
4787 } else if (Cst > NVTBits) {
4788 Lo = DAG.getConstant(0, NVT);
4789 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4790 } else if (Cst == NVTBits) {
4791 Lo = DAG.getConstant(0, NVT);
4794 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4795 Hi = DAG.getNode(ISD::OR, NVT,
4796 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4797 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4802 Lo = DAG.getConstant(0, NVT);
4803 Hi = DAG.getConstant(0, NVT);
4804 } else if (Cst > NVTBits) {
4805 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
4806 Hi = DAG.getConstant(0, NVT);
4807 } else if (Cst == NVTBits) {
4809 Hi = DAG.getConstant(0, NVT);
4811 Lo = DAG.getNode(ISD::OR, NVT,
4812 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4813 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4814 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
4819 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
4820 DAG.getConstant(NVTBits-1, ShTy));
4821 } else if (Cst > NVTBits) {
4822 Lo = DAG.getNode(ISD::SRA, NVT, InH,
4823 DAG.getConstant(Cst-NVTBits, ShTy));
4824 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4825 DAG.getConstant(NVTBits-1, ShTy));
4826 } else if (Cst == NVTBits) {
4828 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4829 DAG.getConstant(NVTBits-1, ShTy));
4831 Lo = DAG.getNode(ISD::OR, NVT,
4832 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4833 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4834 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
4840 // Okay, the shift amount isn't constant. However, if we can tell that it is
4841 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
4842 uint64_t Mask = NVTBits, KnownZero, KnownOne;
4843 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
4845 // If we know that the high bit of the shift amount is one, then we can do
4846 // this as a couple of simple shifts.
4847 if (KnownOne & Mask) {
4848 // Mask out the high bit, which we know is set.
4849 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
4850 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4852 // Expand the incoming operand to be shifted, so that we have its parts
4854 ExpandOp(Op, InL, InH);
4857 Lo = DAG.getConstant(0, NVT); // Low part is zero.
4858 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
4861 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
4862 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
4865 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
4866 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4867 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
4872 // If we know that the high bit of the shift amount is zero, then we can do
4873 // this as a couple of simple shifts.
4874 if (KnownZero & Mask) {
4876 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
4877 DAG.getConstant(NVTBits, Amt.getValueType()),
4880 // Expand the incoming operand to be shifted, so that we have its parts
4882 ExpandOp(Op, InL, InH);
4885 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
4886 Hi = DAG.getNode(ISD::OR, NVT,
4887 DAG.getNode(ISD::SHL, NVT, InH, Amt),
4888 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
4891 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
4892 Lo = DAG.getNode(ISD::OR, NVT,
4893 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4894 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4897 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
4898 Lo = DAG.getNode(ISD::OR, NVT,
4899 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4900 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4909 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
4910 // does not fit into a register, return the lo part and set the hi part to the
4911 // by-reg argument. If it does fit into a single register, return the result
4912 // and leave the Hi part unset.
4913 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
4914 bool isSigned, SDOperand &Hi) {
4915 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
4916 // The input chain to this libcall is the entry node of the function.
4917 // Legalizing the call will automatically add the previous call to the
4919 SDOperand InChain = DAG.getEntryNode();
4921 TargetLowering::ArgListTy Args;
4922 TargetLowering::ArgListEntry Entry;
4923 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4924 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
4925 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
4926 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
4927 Entry.isSExt = isSigned;
4928 Args.push_back(Entry);
4930 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
4932 // Splice the libcall in wherever FindInputOutputChains tells us to.
4933 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
4934 std::pair<SDOperand,SDOperand> CallInfo =
4935 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
4938 // Legalize the call sequence, starting with the chain. This will advance
4939 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
4940 // was added by LowerCallTo (guaranteeing proper serialization of calls).
4941 LegalizeOp(CallInfo.second);
4943 switch (getTypeAction(CallInfo.first.getValueType())) {
4944 default: assert(0 && "Unknown thing");
4946 Result = CallInfo.first;
4949 ExpandOp(CallInfo.first, Result, Hi);
4956 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
4958 SDOperand SelectionDAGLegalize::
4959 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
4960 assert(getTypeAction(Source.getValueType()) == Expand &&
4961 "This is not an expansion!");
4962 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
4965 assert(Source.getValueType() == MVT::i64 &&
4966 "This only works for 64-bit -> FP");
4967 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
4968 // incoming integer is set. To handle this, we dynamically test to see if
4969 // it is set, and, if so, add a fudge factor.
4971 ExpandOp(Source, Lo, Hi);
4973 // If this is unsigned, and not supported, first perform the conversion to
4974 // signed, then adjust the result if the sign bit is set.
4975 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
4976 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
4978 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
4979 DAG.getConstant(0, Hi.getValueType()),
4981 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4982 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4983 SignSet, Four, Zero);
4984 uint64_t FF = 0x5f800000ULL;
4985 if (TLI.isLittleEndian()) FF <<= 32;
4986 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4988 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4989 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4990 SDOperand FudgeInReg;
4991 if (DestTy == MVT::f32)
4992 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4993 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
4994 // FIXME: Avoid the extend by construction the right constantpool?
4995 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
4996 CPIdx, NULL, 0, MVT::f32);
4998 assert(0 && "Unexpected conversion");
5000 MVT::ValueType SCVT = SignedConv.getValueType();
5001 if (SCVT != DestTy) {
5002 // Destination type needs to be expanded as well. The FADD now we are
5003 // constructing will be expanded into a libcall.
5004 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
5005 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
5006 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
5007 SignedConv, SignedConv.getValue(1));
5009 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5011 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5014 // Check to see if the target has a custom way to lower this. If so, use it.
5015 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
5016 default: assert(0 && "This action not implemented for this operation!");
5017 case TargetLowering::Legal:
5018 case TargetLowering::Expand:
5019 break; // This case is handled below.
5020 case TargetLowering::Custom: {
5021 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5024 return LegalizeOp(NV);
5025 break; // The target decided this was legal after all
5029 // Expand the source, then glue it back together for the call. We must expand
5030 // the source in case it is shared (this pass of legalize must traverse it).
5031 SDOperand SrcLo, SrcHi;
5032 ExpandOp(Source, SrcLo, SrcHi);
5033 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
5036 if (DestTy == MVT::f32)
5037 LC = RTLIB::SINTTOFP_I64_F32;
5039 assert(DestTy == MVT::f64 && "Unknown fp value type!");
5040 LC = RTLIB::SINTTOFP_I64_F64;
5043 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
5044 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5045 SDOperand UnusedHiPart;
5046 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
5050 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5051 /// INT_TO_FP operation of the specified operand when the target requests that
5052 /// we expand it. At this point, we know that the result and operand types are
5053 /// legal for the target.
5054 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5056 MVT::ValueType DestVT) {
5057 if (Op0.getValueType() == MVT::i32) {
5058 // simple 32-bit [signed|unsigned] integer to float/double expansion
5060 // Get the stack frame index of a 8 byte buffer.
5061 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5063 // word offset constant for Hi/Lo address computation
5064 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5065 // set up Hi and Lo (into buffer) address based on endian
5066 SDOperand Hi = StackSlot;
5067 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5068 if (TLI.isLittleEndian())
5071 // if signed map to unsigned space
5072 SDOperand Op0Mapped;
5074 // constant used to invert sign bit (signed to unsigned mapping)
5075 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5076 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5080 // store the lo of the constructed double - based on integer input
5081 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5082 Op0Mapped, Lo, NULL, 0);
5083 // initial hi portion of constructed double
5084 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5085 // store the hi of the constructed double - biased exponent
5086 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5087 // load the constructed double
5088 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5089 // FP constant to bias correct the final result
5090 SDOperand Bias = DAG.getConstantFP(isSigned ?
5091 BitsToDouble(0x4330000080000000ULL)
5092 : BitsToDouble(0x4330000000000000ULL),
5094 // subtract the bias
5095 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5098 // handle final rounding
5099 if (DestVT == MVT::f64) {
5102 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
5103 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub);
5104 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
5105 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5109 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5110 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5112 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
5113 DAG.getConstant(0, Op0.getValueType()),
5115 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
5116 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5117 SignSet, Four, Zero);
5119 // If the sign bit of the integer is set, the large number will be treated
5120 // as a negative number. To counteract this, the dynamic code adds an
5121 // offset depending on the data type.
5123 switch (Op0.getValueType()) {
5124 default: assert(0 && "Unsupported integer type!");
5125 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5126 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5127 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5128 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5130 if (TLI.isLittleEndian()) FF <<= 32;
5131 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5133 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5134 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5135 SDOperand FudgeInReg;
5136 if (DestVT == MVT::f32)
5137 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
5139 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5140 DAG.getEntryNode(), CPIdx,
5141 NULL, 0, MVT::f32));
5144 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5147 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5148 /// *INT_TO_FP operation of the specified operand when the target requests that
5149 /// we promote it. At this point, we know that the result and operand types are
5150 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5151 /// operation that takes a larger input.
5152 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5153 MVT::ValueType DestVT,
5155 // First step, figure out the appropriate *INT_TO_FP operation to use.
5156 MVT::ValueType NewInTy = LegalOp.getValueType();
5158 unsigned OpToUse = 0;
5160 // Scan for the appropriate larger type to use.
5162 NewInTy = (MVT::ValueType)(NewInTy+1);
5163 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
5165 // If the target supports SINT_TO_FP of this type, use it.
5166 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5168 case TargetLowering::Legal:
5169 if (!TLI.isTypeLegal(NewInTy))
5170 break; // Can't use this datatype.
5172 case TargetLowering::Custom:
5173 OpToUse = ISD::SINT_TO_FP;
5177 if (isSigned) continue;
5179 // If the target supports UINT_TO_FP of this type, use it.
5180 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5182 case TargetLowering::Legal:
5183 if (!TLI.isTypeLegal(NewInTy))
5184 break; // Can't use this datatype.
5186 case TargetLowering::Custom:
5187 OpToUse = ISD::UINT_TO_FP;
5192 // Otherwise, try a larger type.
5195 // Okay, we found the operation and type to use. Zero extend our input to the
5196 // desired type then run the operation on it.
5197 return DAG.getNode(OpToUse, DestVT,
5198 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5202 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5203 /// FP_TO_*INT operation of the specified operand when the target requests that
5204 /// we promote it. At this point, we know that the result and operand types are
5205 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5206 /// operation that returns a larger result.
5207 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5208 MVT::ValueType DestVT,
5210 // First step, figure out the appropriate FP_TO*INT operation to use.
5211 MVT::ValueType NewOutTy = DestVT;
5213 unsigned OpToUse = 0;
5215 // Scan for the appropriate larger type to use.
5217 NewOutTy = (MVT::ValueType)(NewOutTy+1);
5218 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
5220 // If the target supports FP_TO_SINT returning this type, use it.
5221 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5223 case TargetLowering::Legal:
5224 if (!TLI.isTypeLegal(NewOutTy))
5225 break; // Can't use this datatype.
5227 case TargetLowering::Custom:
5228 OpToUse = ISD::FP_TO_SINT;
5233 // If the target supports FP_TO_UINT of this type, use it.
5234 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5236 case TargetLowering::Legal:
5237 if (!TLI.isTypeLegal(NewOutTy))
5238 break; // Can't use this datatype.
5240 case TargetLowering::Custom:
5241 OpToUse = ISD::FP_TO_UINT;
5246 // Otherwise, try a larger type.
5250 // Okay, we found the operation and type to use.
5251 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5253 // If the operation produces an invalid type, it must be custom lowered. Use
5254 // the target lowering hooks to expand it. Just keep the low part of the
5255 // expanded operation, we know that we're truncating anyway.
5256 if (getTypeAction(NewOutTy) == Expand) {
5257 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
5258 assert(Operation.Val && "Didn't return anything");
5261 // Truncate the result of the extended FP_TO_*INT operation to the desired
5263 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5266 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5268 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5269 MVT::ValueType VT = Op.getValueType();
5270 MVT::ValueType SHVT = TLI.getShiftAmountTy();
5271 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5273 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5275 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5276 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5277 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5279 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5280 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5281 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5282 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5283 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5284 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5285 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5286 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5287 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5289 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5290 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5291 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5292 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5293 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5294 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5295 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5296 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5297 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5298 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5299 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5300 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5301 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5302 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5303 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5304 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5305 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5306 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5307 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5308 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5309 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5313 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5315 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5317 default: assert(0 && "Cannot expand this yet!");
5319 static const uint64_t mask[6] = {
5320 0x5555555555555555ULL, 0x3333333333333333ULL,
5321 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5322 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5324 MVT::ValueType VT = Op.getValueType();
5325 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5326 unsigned len = MVT::getSizeInBits(VT);
5327 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5328 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5329 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5330 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5331 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5332 DAG.getNode(ISD::AND, VT,
5333 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5338 // for now, we do this:
5339 // x = x | (x >> 1);
5340 // x = x | (x >> 2);
5342 // x = x | (x >>16);
5343 // x = x | (x >>32); // for 64-bit input
5344 // return popcount(~x);
5346 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5347 MVT::ValueType VT = Op.getValueType();
5348 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5349 unsigned len = MVT::getSizeInBits(VT);
5350 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5351 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5352 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5354 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5355 return DAG.getNode(ISD::CTPOP, VT, Op);
5358 // for now, we use: { return popcount(~x & (x - 1)); }
5359 // unless the target has ctlz but not ctpop, in which case we use:
5360 // { return 32 - nlz(~x & (x-1)); }
5361 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5362 MVT::ValueType VT = Op.getValueType();
5363 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5364 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5365 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5366 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5367 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5368 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5369 TLI.isOperationLegal(ISD::CTLZ, VT))
5370 return DAG.getNode(ISD::SUB, VT,
5371 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5372 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5373 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5378 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5379 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5380 /// LegalizeNodes map is filled in for any results that are not expanded, the
5381 /// ExpandedNodes map is filled in for any results that are expanded, and the
5382 /// Lo/Hi values are returned.
5383 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5384 MVT::ValueType VT = Op.getValueType();
5385 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5386 SDNode *Node = Op.Val;
5387 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5388 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5389 MVT::isVector(VT)) &&
5390 "Cannot expand to FP value or to larger int value!");
5392 // See if we already expanded it.
5393 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5394 = ExpandedNodes.find(Op);
5395 if (I != ExpandedNodes.end()) {
5396 Lo = I->second.first;
5397 Hi = I->second.second;
5401 switch (Node->getOpcode()) {
5402 case ISD::CopyFromReg:
5403 assert(0 && "CopyFromReg must be legal!");
5404 case ISD::FP_ROUND_INREG:
5405 if (VT == MVT::ppcf128 &&
5406 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5407 TargetLowering::Custom) {
5408 SDOperand SrcLo, SrcHi, Src;
5409 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5410 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5411 SDOperand Result = TLI.LowerOperation(
5412 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5413 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5414 Lo = Result.Val->getOperand(0);
5415 Hi = Result.Val->getOperand(1);
5421 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5423 assert(0 && "Do not know how to expand this operator!");
5425 case ISD::EXTRACT_VECTOR_ELT:
5426 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5427 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5428 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5429 return ExpandOp(Lo, Lo, Hi);
5431 NVT = TLI.getTypeToExpandTo(VT);
5432 Lo = DAG.getNode(ISD::UNDEF, NVT);
5433 Hi = DAG.getNode(ISD::UNDEF, NVT);
5435 case ISD::Constant: {
5436 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
5437 Lo = DAG.getConstant(Cst, NVT);
5438 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
5441 case ISD::ConstantFP: {
5442 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5443 if (CFP->getValueType(0) == MVT::ppcf128) {
5444 APInt api = CFP->getValueAPF().convertToAPInt();
5445 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5447 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5451 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5452 if (getTypeAction(Lo.getValueType()) == Expand)
5453 ExpandOp(Lo, Lo, Hi);
5456 case ISD::BUILD_PAIR:
5457 // Return the operands.
5458 Lo = Node->getOperand(0);
5459 Hi = Node->getOperand(1);
5462 case ISD::MERGE_VALUES:
5463 if (Node->getNumValues() == 1) {
5464 ExpandOp(Op.getOperand(0), Lo, Hi);
5467 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5468 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5469 Op.getValue(1).getValueType() == MVT::Other &&
5470 "unhandled MERGE_VALUES");
5471 ExpandOp(Op.getOperand(0), Lo, Hi);
5472 // Remember that we legalized the chain.
5473 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5476 case ISD::SIGN_EXTEND_INREG:
5477 ExpandOp(Node->getOperand(0), Lo, Hi);
5478 // sext_inreg the low part if needed.
5479 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5481 // The high part gets the sign extension from the lo-part. This handles
5482 // things like sextinreg V:i64 from i8.
5483 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5484 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5485 TLI.getShiftAmountTy()));
5489 ExpandOp(Node->getOperand(0), Lo, Hi);
5490 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5491 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5497 ExpandOp(Node->getOperand(0), Lo, Hi);
5498 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5499 DAG.getNode(ISD::CTPOP, NVT, Lo),
5500 DAG.getNode(ISD::CTPOP, NVT, Hi));
5501 Hi = DAG.getConstant(0, NVT);
5505 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5506 ExpandOp(Node->getOperand(0), Lo, Hi);
5507 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5508 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5509 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5511 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5512 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5514 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5515 Hi = DAG.getConstant(0, NVT);
5520 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5521 ExpandOp(Node->getOperand(0), Lo, Hi);
5522 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5523 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5524 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5526 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5527 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5529 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5530 Hi = DAG.getConstant(0, NVT);
5535 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5536 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5537 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5538 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5540 // Remember that we legalized the chain.
5541 Hi = LegalizeOp(Hi);
5542 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5543 if (!TLI.isLittleEndian())
5549 LoadSDNode *LD = cast<LoadSDNode>(Node);
5550 SDOperand Ch = LD->getChain(); // Legalize the chain.
5551 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5552 ISD::LoadExtType ExtType = LD->getExtensionType();
5553 int SVOffset = LD->getSrcValueOffset();
5554 unsigned Alignment = LD->getAlignment();
5555 bool isVolatile = LD->isVolatile();
5557 if (ExtType == ISD::NON_EXTLOAD) {
5558 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5559 isVolatile, Alignment);
5560 if (VT == MVT::f32 || VT == MVT::f64) {
5561 // f32->i32 or f64->i64 one to one expansion.
5562 // Remember that we legalized the chain.
5563 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5564 // Recursively expand the new load.
5565 if (getTypeAction(NVT) == Expand)
5566 ExpandOp(Lo, Lo, Hi);
5570 // Increment the pointer to the other half.
5571 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5572 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5573 getIntPtrConstant(IncrementSize));
5574 SVOffset += IncrementSize;
5575 Alignment = MinAlign(Alignment, IncrementSize);
5576 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5577 isVolatile, Alignment);
5579 // Build a factor node to remember that this load is independent of the
5581 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5584 // Remember that we legalized the chain.
5585 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5586 if (!TLI.isLittleEndian())
5589 MVT::ValueType EVT = LD->getLoadedVT();
5591 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5592 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5593 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5594 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5595 SVOffset, isVolatile, Alignment);
5596 // Remember that we legalized the chain.
5597 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5598 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5603 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5604 SVOffset, isVolatile, Alignment);
5606 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5607 SVOffset, EVT, isVolatile,
5610 // Remember that we legalized the chain.
5611 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5613 if (ExtType == ISD::SEXTLOAD) {
5614 // The high part is obtained by SRA'ing all but one of the bits of the
5616 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5617 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5618 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5619 } else if (ExtType == ISD::ZEXTLOAD) {
5620 // The high part is just a zero.
5621 Hi = DAG.getConstant(0, NVT);
5622 } else /* if (ExtType == ISD::EXTLOAD) */ {
5623 // The high part is undefined.
5624 Hi = DAG.getNode(ISD::UNDEF, NVT);
5631 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5632 SDOperand LL, LH, RL, RH;
5633 ExpandOp(Node->getOperand(0), LL, LH);
5634 ExpandOp(Node->getOperand(1), RL, RH);
5635 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5636 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5640 SDOperand LL, LH, RL, RH;
5641 ExpandOp(Node->getOperand(1), LL, LH);
5642 ExpandOp(Node->getOperand(2), RL, RH);
5643 if (getTypeAction(NVT) == Expand)
5644 NVT = TLI.getTypeToExpandTo(NVT);
5645 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5647 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5650 case ISD::SELECT_CC: {
5651 SDOperand TL, TH, FL, FH;
5652 ExpandOp(Node->getOperand(2), TL, TH);
5653 ExpandOp(Node->getOperand(3), FL, FH);
5654 if (getTypeAction(NVT) == Expand)
5655 NVT = TLI.getTypeToExpandTo(NVT);
5656 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5657 Node->getOperand(1), TL, FL, Node->getOperand(4));
5659 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5660 Node->getOperand(1), TH, FH, Node->getOperand(4));
5663 case ISD::ANY_EXTEND:
5664 // The low part is any extension of the input (which degenerates to a copy).
5665 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5666 // The high part is undefined.
5667 Hi = DAG.getNode(ISD::UNDEF, NVT);
5669 case ISD::SIGN_EXTEND: {
5670 // The low part is just a sign extension of the input (which degenerates to
5672 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5674 // The high part is obtained by SRA'ing all but one of the bits of the lo
5676 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5677 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5678 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5681 case ISD::ZERO_EXTEND:
5682 // The low part is just a zero extension of the input (which degenerates to
5684 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5686 // The high part is just a zero.
5687 Hi = DAG.getConstant(0, NVT);
5690 case ISD::TRUNCATE: {
5691 // The input value must be larger than this value. Expand *it*.
5693 ExpandOp(Node->getOperand(0), NewLo, Hi);
5695 // The low part is now either the right size, or it is closer. If not the
5696 // right size, make an illegal truncate so we recursively expand it.
5697 if (NewLo.getValueType() != Node->getValueType(0))
5698 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
5699 ExpandOp(NewLo, Lo, Hi);
5703 case ISD::BIT_CONVERT: {
5705 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
5706 // If the target wants to, allow it to lower this itself.
5707 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5708 case Expand: assert(0 && "cannot expand FP!");
5709 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
5710 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
5712 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
5715 // f32 / f64 must be expanded to i32 / i64.
5716 if (VT == MVT::f32 || VT == MVT::f64) {
5717 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5718 if (getTypeAction(NVT) == Expand)
5719 ExpandOp(Lo, Lo, Hi);
5723 // If source operand will be expanded to the same type as VT, i.e.
5724 // i64 <- f64, i32 <- f32, expand the source operand instead.
5725 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
5726 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
5727 ExpandOp(Node->getOperand(0), Lo, Hi);
5731 // Turn this into a load/store pair by default.
5733 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
5735 ExpandOp(Tmp, Lo, Hi);
5739 case ISD::READCYCLECOUNTER: {
5740 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5741 TargetLowering::Custom &&
5742 "Must custom expand ReadCycleCounter");
5743 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
5744 assert(Tmp.Val && "Node must be custom expanded!");
5745 ExpandOp(Tmp.getValue(0), Lo, Hi);
5746 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5747 LegalizeOp(Tmp.getValue(1)));
5751 // These operators cannot be expanded directly, emit them as calls to
5752 // library functions.
5753 case ISD::FP_TO_SINT: {
5754 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5756 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5757 case Expand: assert(0 && "cannot expand FP!");
5758 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5759 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5762 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5764 // Now that the custom expander is done, expand the result, which is still
5767 ExpandOp(Op, Lo, Hi);
5772 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5773 if (Node->getOperand(0).getValueType() == MVT::f32)
5774 LC = RTLIB::FPTOSINT_F32_I64;
5775 else if (Node->getOperand(0).getValueType() == MVT::f64)
5776 LC = RTLIB::FPTOSINT_F64_I64;
5777 else if (Node->getOperand(0).getValueType() == MVT::f80)
5778 LC = RTLIB::FPTOSINT_F80_I64;
5779 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
5780 LC = RTLIB::FPTOSINT_PPCF128_I64;
5781 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5782 false/*sign irrelevant*/, Hi);
5786 case ISD::FP_TO_UINT: {
5787 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
5789 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5790 case Expand: assert(0 && "cannot expand FP!");
5791 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5792 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5795 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
5797 // Now that the custom expander is done, expand the result.
5799 ExpandOp(Op, Lo, Hi);
5804 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5805 if (Node->getOperand(0).getValueType() == MVT::f32)
5806 LC = RTLIB::FPTOUINT_F32_I64;
5807 else if (Node->getOperand(0).getValueType() == MVT::f64)
5808 LC = RTLIB::FPTOUINT_F64_I64;
5809 else if (Node->getOperand(0).getValueType() == MVT::f80)
5810 LC = RTLIB::FPTOUINT_F80_I64;
5811 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
5812 LC = RTLIB::FPTOUINT_PPCF128_I64;
5813 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5814 false/*sign irrelevant*/, Hi);
5819 // If the target wants custom lowering, do so.
5820 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5821 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
5822 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
5823 Op = TLI.LowerOperation(Op, DAG);
5825 // Now that the custom expander is done, expand the result, which is
5827 ExpandOp(Op, Lo, Hi);
5832 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
5833 // this X << 1 as X+X.
5834 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
5835 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
5836 TLI.isOperationLegal(ISD::ADDE, NVT)) {
5837 SDOperand LoOps[2], HiOps[3];
5838 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
5839 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
5840 LoOps[1] = LoOps[0];
5841 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5843 HiOps[1] = HiOps[0];
5844 HiOps[2] = Lo.getValue(1);
5845 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5850 // If we can emit an efficient shift operation, do so now.
5851 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5854 // If this target supports SHL_PARTS, use it.
5855 TargetLowering::LegalizeAction Action =
5856 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
5857 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5858 Action == TargetLowering::Custom) {
5859 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5863 // Otherwise, emit a libcall.
5864 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
5865 false/*left shift=unsigned*/, Hi);
5870 // If the target wants custom lowering, do so.
5871 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5872 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
5873 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
5874 Op = TLI.LowerOperation(Op, DAG);
5876 // Now that the custom expander is done, expand the result, which is
5878 ExpandOp(Op, Lo, Hi);
5883 // If we can emit an efficient shift operation, do so now.
5884 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
5887 // If this target supports SRA_PARTS, use it.
5888 TargetLowering::LegalizeAction Action =
5889 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
5890 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5891 Action == TargetLowering::Custom) {
5892 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5896 // Otherwise, emit a libcall.
5897 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
5898 true/*ashr is signed*/, Hi);
5903 // If the target wants custom lowering, do so.
5904 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5905 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
5906 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
5907 Op = TLI.LowerOperation(Op, DAG);
5909 // Now that the custom expander is done, expand the result, which is
5911 ExpandOp(Op, Lo, Hi);
5916 // If we can emit an efficient shift operation, do so now.
5917 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5920 // If this target supports SRL_PARTS, use it.
5921 TargetLowering::LegalizeAction Action =
5922 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
5923 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5924 Action == TargetLowering::Custom) {
5925 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5929 // Otherwise, emit a libcall.
5930 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
5931 false/*lshr is unsigned*/, Hi);
5937 // If the target wants to custom expand this, let them.
5938 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
5939 TargetLowering::Custom) {
5940 Op = TLI.LowerOperation(Op, DAG);
5942 ExpandOp(Op, Lo, Hi);
5947 // Expand the subcomponents.
5948 SDOperand LHSL, LHSH, RHSL, RHSH;
5949 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5950 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5951 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5952 SDOperand LoOps[2], HiOps[3];
5957 if (Node->getOpcode() == ISD::ADD) {
5958 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5959 HiOps[2] = Lo.getValue(1);
5960 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5962 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5963 HiOps[2] = Lo.getValue(1);
5964 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5971 // Expand the subcomponents.
5972 SDOperand LHSL, LHSH, RHSL, RHSH;
5973 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5974 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5975 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5976 SDOperand LoOps[2] = { LHSL, RHSL };
5977 SDOperand HiOps[3] = { LHSH, RHSH };
5979 if (Node->getOpcode() == ISD::ADDC) {
5980 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5981 HiOps[2] = Lo.getValue(1);
5982 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5984 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5985 HiOps[2] = Lo.getValue(1);
5986 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5988 // Remember that we legalized the flag.
5989 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5994 // Expand the subcomponents.
5995 SDOperand LHSL, LHSH, RHSL, RHSH;
5996 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5997 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5998 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5999 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6000 SDOperand HiOps[3] = { LHSH, RHSH };
6002 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6003 HiOps[2] = Lo.getValue(1);
6004 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6006 // Remember that we legalized the flag.
6007 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6011 // If the target wants to custom expand this, let them.
6012 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6013 SDOperand New = TLI.LowerOperation(Op, DAG);
6015 ExpandOp(New, Lo, Hi);
6020 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6021 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6022 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6023 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6024 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6025 SDOperand LL, LH, RL, RH;
6026 ExpandOp(Node->getOperand(0), LL, LH);
6027 ExpandOp(Node->getOperand(1), RL, RH);
6028 unsigned BitSize = MVT::getSizeInBits(RH.getValueType());
6029 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6030 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6031 // FIXME: generalize this to handle other bit sizes
6032 if (LHSSB == 32 && RHSSB == 32 &&
6033 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) &&
6034 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) {
6035 // The inputs are both zero-extended.
6037 // We can emit a umul_lohi.
6038 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6039 Hi = SDOperand(Lo.Val, 1);
6043 // We can emit a mulhu+mul.
6044 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6045 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6049 if (LHSSB > BitSize && RHSSB > BitSize) {
6050 // The input values are both sign-extended.
6052 // We can emit a smul_lohi.
6053 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6054 Hi = SDOperand(Lo.Val, 1);
6058 // We can emit a mulhs+mul.
6059 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6060 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6065 // Lo,Hi = umul LHS, RHS.
6066 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6067 DAG.getVTList(NVT, NVT), LL, RL);
6069 Hi = UMulLOHI.getValue(1);
6070 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6071 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6072 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6073 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6077 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6078 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6079 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6080 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6081 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6082 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6087 // If nothing else, we can make a libcall.
6088 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
6089 false/*sign irrelevant*/, Hi);
6093 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
6096 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
6099 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
6102 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
6106 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32,
6109 RTLIB::ADD_PPCF128)),
6113 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32,
6116 RTLIB::SUB_PPCF128)),
6120 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32,
6123 RTLIB::MUL_PPCF128)),
6127 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32,
6130 RTLIB::DIV_PPCF128)),
6133 case ISD::FP_EXTEND:
6134 if (VT == MVT::ppcf128) {
6135 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6136 Node->getOperand(0).getValueType()==MVT::f64);
6137 const uint64_t zero = 0;
6138 if (Node->getOperand(0).getValueType()==MVT::f32)
6139 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6141 Hi = Node->getOperand(0);
6142 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6145 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
6148 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
6151 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32,
6154 RTLIB::POWI_PPCF128)),
6160 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6161 switch(Node->getOpcode()) {
6163 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6164 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6167 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6168 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6171 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6172 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6174 default: assert(0 && "Unreachable!");
6176 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
6180 if (VT == MVT::ppcf128) {
6182 ExpandOp(Node->getOperand(0), Lo, Tmp);
6183 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6184 // lo = hi==fabs(hi) ? lo : -lo;
6185 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6186 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6187 DAG.getCondCode(ISD::SETEQ));
6190 SDOperand Mask = (VT == MVT::f64)
6191 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6192 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6193 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6194 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6195 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6196 if (getTypeAction(NVT) == Expand)
6197 ExpandOp(Lo, Lo, Hi);
6201 if (VT == MVT::ppcf128) {
6202 ExpandOp(Node->getOperand(0), Lo, Hi);
6203 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6204 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6207 SDOperand Mask = (VT == MVT::f64)
6208 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6209 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6210 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6211 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6212 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6213 if (getTypeAction(NVT) == Expand)
6214 ExpandOp(Lo, Lo, Hi);
6217 case ISD::FCOPYSIGN: {
6218 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6219 if (getTypeAction(NVT) == Expand)
6220 ExpandOp(Lo, Lo, Hi);
6223 case ISD::SINT_TO_FP:
6224 case ISD::UINT_TO_FP: {
6225 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6226 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
6227 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) {
6228 static uint64_t zero = 0;
6230 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6231 Node->getOperand(0)));
6232 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6234 static uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6235 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6236 Node->getOperand(0)));
6237 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6238 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6239 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6240 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6241 DAG.getConstant(0, MVT::i32),
6242 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6244 APFloat(APInt(128, 2, TwoE32)),
6247 DAG.getCondCode(ISD::SETLT)),
6252 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6253 // si64->ppcf128 done by libcall, below
6254 static uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6255 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6257 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6258 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6259 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6260 DAG.getConstant(0, MVT::i64),
6261 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6263 APFloat(APInt(128, 2, TwoE64)),
6266 DAG.getCondCode(ISD::SETLT)),
6270 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6271 if (Node->getOperand(0).getValueType() == MVT::i64) {
6273 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
6274 else if (VT == MVT::f64)
6275 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
6276 else if (VT == MVT::f80) {
6278 LC = RTLIB::SINTTOFP_I64_F80;
6280 else if (VT == MVT::ppcf128) {
6282 LC = RTLIB::SINTTOFP_I64_PPCF128;
6286 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
6288 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
6291 // Promote the operand if needed.
6292 if (getTypeAction(SrcVT) == Promote) {
6293 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6295 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6296 DAG.getValueType(SrcVT))
6297 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6298 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6301 const char *LibCall = TLI.getLibcallName(LC);
6303 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
6305 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6306 Node->getOperand(0));
6307 if (getTypeAction(Lo.getValueType()) == Expand)
6308 ExpandOp(Lo, Lo, Hi);
6314 // Make sure the resultant values have been legalized themselves, unless this
6315 // is a type that requires multi-step expansion.
6316 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6317 Lo = LegalizeOp(Lo);
6319 // Don't legalize the high part if it is expanded to a single node.
6320 Hi = LegalizeOp(Hi);
6323 // Remember in a map if the values will be reused later.
6324 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6325 assert(isNew && "Value already expanded?!?");
6328 /// SplitVectorOp - Given an operand of vector type, break it down into
6329 /// two smaller values, still of vector type.
6330 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6332 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
6333 SDNode *Node = Op.Val;
6334 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
6335 assert(NumElements > 1 && "Cannot split a single element vector!");
6337 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
6339 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6340 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6342 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
6343 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
6345 // See if we already split it.
6346 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6347 = SplitNodes.find(Op);
6348 if (I != SplitNodes.end()) {
6349 Lo = I->second.first;
6350 Hi = I->second.second;
6354 switch (Node->getOpcode()) {
6359 assert(0 && "Unhandled operation in SplitVectorOp!");
6361 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6362 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6364 case ISD::BUILD_PAIR:
6365 Lo = Node->getOperand(0);
6366 Hi = Node->getOperand(1);
6368 case ISD::INSERT_VECTOR_ELT: {
6369 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6370 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
6371 SDOperand ScalarOp = Node->getOperand(1);
6372 if (Index < NewNumElts_Lo)
6373 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6374 DAG.getConstant(Index, TLI.getPointerTy()));
6376 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6377 DAG.getConstant(Index - NewNumElts_Lo,
6378 TLI.getPointerTy()));
6381 case ISD::VECTOR_SHUFFLE: {
6382 // Build the low part.
6383 SDOperand Mask = Node->getOperand(2);
6384 SmallVector<SDOperand, 8> Ops;
6385 MVT::ValueType PtrVT = TLI.getPointerTy();
6387 // Insert all of the elements from the input that are needed. We use
6388 // buildvector of extractelement here because the input vectors will have
6389 // to be legalized, so this makes the code simpler.
6390 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6391 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6392 SDOperand InVec = Node->getOperand(0);
6393 if (Idx >= NumElements) {
6394 InVec = Node->getOperand(1);
6397 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6398 DAG.getConstant(Idx, PtrVT)));
6400 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6403 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6404 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6405 SDOperand InVec = Node->getOperand(0);
6406 if (Idx >= NumElements) {
6407 InVec = Node->getOperand(1);
6410 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6411 DAG.getConstant(Idx, PtrVT)));
6413 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6416 case ISD::BUILD_VECTOR: {
6417 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6418 Node->op_begin()+NewNumElts_Lo);
6419 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6421 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6423 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6426 case ISD::CONCAT_VECTORS: {
6427 // FIXME: Handle non-power-of-two vectors?
6428 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6429 if (NewNumSubvectors == 1) {
6430 Lo = Node->getOperand(0);
6431 Hi = Node->getOperand(1);
6433 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6434 Node->op_begin()+NewNumSubvectors);
6435 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6437 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6439 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6444 SDOperand Cond = Node->getOperand(0);
6446 SDOperand LL, LH, RL, RH;
6447 SplitVectorOp(Node->getOperand(1), LL, LH);
6448 SplitVectorOp(Node->getOperand(2), RL, RH);
6450 if (MVT::isVector(Cond.getValueType())) {
6451 // Handle a vector merge.
6453 SplitVectorOp(Cond, CL, CH);
6454 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6455 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6457 // Handle a simple select with vector operands.
6458 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6459 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6479 SDOperand LL, LH, RL, RH;
6480 SplitVectorOp(Node->getOperand(0), LL, LH);
6481 SplitVectorOp(Node->getOperand(1), RL, RH);
6483 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6484 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6489 SplitVectorOp(Node->getOperand(0), L, H);
6491 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6492 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6503 case ISD::FP_TO_SINT:
6504 case ISD::FP_TO_UINT:
6505 case ISD::SINT_TO_FP:
6506 case ISD::UINT_TO_FP: {
6508 SplitVectorOp(Node->getOperand(0), L, H);
6510 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6511 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6515 LoadSDNode *LD = cast<LoadSDNode>(Node);
6516 SDOperand Ch = LD->getChain();
6517 SDOperand Ptr = LD->getBasePtr();
6518 const Value *SV = LD->getSrcValue();
6519 int SVOffset = LD->getSrcValueOffset();
6520 unsigned Alignment = LD->getAlignment();
6521 bool isVolatile = LD->isVolatile();
6523 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6524 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
6525 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6526 getIntPtrConstant(IncrementSize));
6527 SVOffset += IncrementSize;
6528 Alignment = MinAlign(Alignment, IncrementSize);
6529 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6531 // Build a factor node to remember that this load is independent of the
6533 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6536 // Remember that we legalized the chain.
6537 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6540 case ISD::BIT_CONVERT: {
6541 // We know the result is a vector. The input may be either a vector or a
6543 SDOperand InOp = Node->getOperand(0);
6544 if (!MVT::isVector(InOp.getValueType()) ||
6545 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
6546 // The input is a scalar or single-element vector.
6547 // Lower to a store/load so that it can be split.
6548 // FIXME: this could be improved probably.
6549 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6551 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6552 InOp, Ptr, NULL, 0);
6553 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0);
6555 // Split the vector and convert each of the pieces now.
6556 SplitVectorOp(InOp, Lo, Hi);
6557 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6558 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6563 // Remember in a map if the values will be reused later.
6565 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6566 assert(isNew && "Value already split?!?");
6570 /// ScalarizeVectorOp - Given an operand of single-element vector type
6571 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6572 /// scalar (e.g. f32) value.
6573 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6574 assert(MVT::isVector(Op.getValueType()) &&
6575 "Bad ScalarizeVectorOp invocation!");
6576 SDNode *Node = Op.Val;
6577 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
6578 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
6580 // See if we already scalarized it.
6581 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
6582 if (I != ScalarizedNodes.end()) return I->second;
6585 switch (Node->getOpcode()) {
6588 Node->dump(&DAG); cerr << "\n";
6590 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
6607 Result = DAG.getNode(Node->getOpcode(),
6609 ScalarizeVectorOp(Node->getOperand(0)),
6610 ScalarizeVectorOp(Node->getOperand(1)));
6617 Result = DAG.getNode(Node->getOpcode(),
6619 ScalarizeVectorOp(Node->getOperand(0)));
6622 Result = DAG.getNode(Node->getOpcode(),
6624 ScalarizeVectorOp(Node->getOperand(0)),
6625 Node->getOperand(1));
6628 LoadSDNode *LD = cast<LoadSDNode>(Node);
6629 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
6630 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
6632 const Value *SV = LD->getSrcValue();
6633 int SVOffset = LD->getSrcValueOffset();
6634 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
6635 LD->isVolatile(), LD->getAlignment());
6637 // Remember that we legalized the chain.
6638 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
6641 case ISD::BUILD_VECTOR:
6642 Result = Node->getOperand(0);
6644 case ISD::INSERT_VECTOR_ELT:
6645 // Returning the inserted scalar element.
6646 Result = Node->getOperand(1);
6648 case ISD::CONCAT_VECTORS:
6649 assert(Node->getOperand(0).getValueType() == NewVT &&
6650 "Concat of non-legal vectors not yet supported!");
6651 Result = Node->getOperand(0);
6653 case ISD::VECTOR_SHUFFLE: {
6654 // Figure out if the scalar is the LHS or RHS and return it.
6655 SDOperand EltNum = Node->getOperand(2).getOperand(0);
6656 if (cast<ConstantSDNode>(EltNum)->getValue())
6657 Result = ScalarizeVectorOp(Node->getOperand(1));
6659 Result = ScalarizeVectorOp(Node->getOperand(0));
6662 case ISD::EXTRACT_SUBVECTOR:
6663 Result = Node->getOperand(0);
6664 assert(Result.getValueType() == NewVT);
6666 case ISD::BIT_CONVERT:
6667 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
6670 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
6671 ScalarizeVectorOp(Op.getOperand(1)),
6672 ScalarizeVectorOp(Op.getOperand(2)));
6676 if (TLI.isTypeLegal(NewVT))
6677 Result = LegalizeOp(Result);
6678 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
6679 assert(isNew && "Value already scalarized?");
6684 // SelectionDAG::Legalize - This is the entry point for the file.
6686 void SelectionDAG::Legalize() {
6687 if (ViewLegalizeDAGs) viewGraph();
6689 /// run - This is the main entry point to this class.
6691 SelectionDAGLegalize(*this).LegalizeDAG();