1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Target/TargetLowering.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/CommandLine.h"
30 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
31 cl::desc("Pop up a window to show dags before legalize"));
33 static const bool ViewLegalizeDAGs = 0;
36 //===----------------------------------------------------------------------===//
37 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
38 /// hacks on it until the target machine can handle it. This involves
39 /// eliminating value sizes the machine cannot handle (promoting small sizes to
40 /// large sizes or splitting up large values into small values) as well as
41 /// eliminating operations the machine cannot handle.
43 /// This code also does a small amount of optimization and recognition of idioms
44 /// as part of its processing. For example, if a target does not support a
45 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
46 /// will attempt merge setcc and brc instructions into brcc's.
49 class SelectionDAGLegalize {
53 // Libcall insertion helpers.
55 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
56 /// legalized. We use this to ensure that calls are properly serialized
57 /// against each other, including inserted libcalls.
58 SDOperand LastCALLSEQ_END;
60 /// IsLegalizingCall - This member is used *only* for purposes of providing
61 /// helpful assertions that a libcall isn't created while another call is
62 /// being legalized (which could lead to non-serialized call sequences).
63 bool IsLegalizingCall;
66 Legal, // The target natively supports this operation.
67 Promote, // This operation should be executed in a larger type.
68 Expand // Try to expand this to other ops, otherwise use a libcall.
71 /// ValueTypeActions - This is a bitvector that contains two bits for each
72 /// value type, where the two bits correspond to the LegalizeAction enum.
73 /// This can be queried with "getTypeAction(VT)".
74 TargetLowering::ValueTypeActionImpl ValueTypeActions;
76 /// LegalizedNodes - For nodes that are of legal width, and that have more
77 /// than one use, this map indicates what regularized operand to use. This
78 /// allows us to avoid legalizing the same thing more than once.
79 std::map<SDOperand, SDOperand> LegalizedNodes;
81 /// PromotedNodes - For nodes that are below legal width, and that have more
82 /// than one use, this map indicates what promoted value to use. This allows
83 /// us to avoid promoting the same thing more than once.
84 std::map<SDOperand, SDOperand> PromotedNodes;
86 /// ExpandedNodes - For nodes that need to be expanded this map indicates
87 /// which which operands are the expanded version of the input. This allows
88 /// us to avoid expanding the same node more than once.
89 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
91 /// SplitNodes - For vector nodes that need to be split, this map indicates
92 /// which which operands are the split version of the input. This allows us
93 /// to avoid splitting the same node more than once.
94 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
96 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
97 /// concrete packed types, this contains the mapping of ones we have already
98 /// processed to the result.
99 std::map<SDOperand, SDOperand> PackedNodes;
101 void AddLegalizedOperand(SDOperand From, SDOperand To) {
102 LegalizedNodes.insert(std::make_pair(From, To));
103 // If someone requests legalization of the new node, return itself.
105 LegalizedNodes.insert(std::make_pair(To, To));
107 void AddPromotedOperand(SDOperand From, SDOperand To) {
108 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
109 assert(isNew && "Got into the map somehow?");
110 // If someone requests legalization of the new node, return itself.
111 LegalizedNodes.insert(std::make_pair(To, To));
116 SelectionDAGLegalize(SelectionDAG &DAG);
118 /// getTypeAction - Return how we should legalize values of this type, either
119 /// it is already legal or we need to expand it into multiple registers of
120 /// smaller integer type, or we need to promote it to a larger type.
121 LegalizeAction getTypeAction(MVT::ValueType VT) const {
122 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
125 /// isTypeLegal - Return true if this type is legal on this target.
127 bool isTypeLegal(MVT::ValueType VT) const {
128 return getTypeAction(VT) == Legal;
134 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
135 /// appropriate for its type.
136 void HandleOp(SDOperand Op);
138 /// LegalizeOp - We know that the specified value has a legal type.
139 /// Recursively ensure that the operands have legal types, then return the
141 SDOperand LegalizeOp(SDOperand O);
143 /// PromoteOp - Given an operation that produces a value in an invalid type,
144 /// promote it to compute the value into a larger type. The produced value
145 /// will have the correct bits for the low portion of the register, but no
146 /// guarantee is made about the top bits: it may be zero, sign-extended, or
148 SDOperand PromoteOp(SDOperand O);
150 /// ExpandOp - Expand the specified SDOperand into its two component pieces
151 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
152 /// the LegalizeNodes map is filled in for any results that are not expanded,
153 /// the ExpandedNodes map is filled in for any results that are expanded, and
154 /// the Lo/Hi values are returned. This applies to integer types and Vector
156 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
158 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
159 /// two smaller values of MVT::Vector type.
160 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
162 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
163 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
164 /// this is called, we know that PackedVT is the right type for the result and
165 /// we know that this type is legal for the target.
166 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
168 /// isShuffleLegal - Return true if a vector shuffle is legal with the
169 /// specified mask and type. Targets can specify exactly which masks they
170 /// support and the code generator is tasked with not creating illegal masks.
172 /// Note that this will also return true for shuffles that are promoted to a
175 /// If this is a legal shuffle, this method returns the (possibly promoted)
176 /// build_vector Mask. If it's not a legal shuffle, it returns null.
177 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
179 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest);
181 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
183 SDOperand CreateStackTemporary(MVT::ValueType VT);
185 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
187 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
190 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
191 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
192 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
193 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
195 MVT::ValueType DestVT);
196 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
198 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
201 SDOperand ExpandBSWAP(SDOperand Op);
202 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
203 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
204 SDOperand &Lo, SDOperand &Hi);
205 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
206 SDOperand &Lo, SDOperand &Hi);
208 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
209 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
211 SDOperand getIntPtrConstant(uint64_t Val) {
212 return DAG.getConstant(Val, TLI.getPointerTy());
217 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
218 /// specified mask and type. Targets can specify exactly which masks they
219 /// support and the code generator is tasked with not creating illegal masks.
221 /// Note that this will also return true for shuffles that are promoted to a
223 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
224 SDOperand Mask) const {
225 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
227 case TargetLowering::Legal:
228 case TargetLowering::Custom:
230 case TargetLowering::Promote: {
231 // If this is promoted to a different type, convert the shuffle mask and
232 // ask if it is legal in the promoted type!
233 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
235 // If we changed # elements, change the shuffle mask.
236 unsigned NumEltsGrowth =
237 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
238 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
239 if (NumEltsGrowth > 1) {
240 // Renumber the elements.
241 std::vector<SDOperand> Ops;
242 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
243 SDOperand InOp = Mask.getOperand(i);
244 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
245 if (InOp.getOpcode() == ISD::UNDEF)
246 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
248 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
249 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
253 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, Ops);
259 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
262 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
263 /// specified vector opcode.
264 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
266 default: assert(0 && "Don't know how to scalarize this opcode!");
267 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
268 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
269 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
270 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
271 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
272 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
273 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
274 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
278 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
279 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
280 ValueTypeActions(TLI.getValueTypeActions()) {
281 assert(MVT::LAST_VALUETYPE <= 32 &&
282 "Too many value types for ValueTypeActions to hold!");
285 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
286 /// not been visited yet and if all of its operands have already been visited.
287 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
288 std::map<SDNode*, unsigned> &Visited) {
289 if (++Visited[N] != N->getNumOperands())
290 return; // Haven't visited all operands yet
294 if (N->hasOneUse()) { // Tail recurse in common case.
295 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
299 // Now that we have N in, add anything that uses it if all of their operands
301 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
302 ComputeTopDownOrdering(*UI, Order, Visited);
306 void SelectionDAGLegalize::LegalizeDAG() {
307 LastCALLSEQ_END = DAG.getEntryNode();
308 IsLegalizingCall = false;
310 // The legalize process is inherently a bottom-up recursive process (users
311 // legalize their uses before themselves). Given infinite stack space, we
312 // could just start legalizing on the root and traverse the whole graph. In
313 // practice however, this causes us to run out of stack space on large basic
314 // blocks. To avoid this problem, compute an ordering of the nodes where each
315 // node is only legalized after all of its operands are legalized.
316 std::map<SDNode*, unsigned> Visited;
317 std::vector<SDNode*> Order;
319 // Compute ordering from all of the leaves in the graphs, those (like the
320 // entry node) that have no operands.
321 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
322 E = DAG.allnodes_end(); I != E; ++I) {
323 if (I->getNumOperands() == 0) {
325 ComputeTopDownOrdering(I, Order, Visited);
329 assert(Order.size() == Visited.size() &&
331 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
332 "Error: DAG is cyclic!");
335 for (unsigned i = 0, e = Order.size(); i != e; ++i)
336 HandleOp(SDOperand(Order[i], 0));
338 // Finally, it's possible the root changed. Get the new root.
339 SDOperand OldRoot = DAG.getRoot();
340 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
341 DAG.setRoot(LegalizedNodes[OldRoot]);
343 ExpandedNodes.clear();
344 LegalizedNodes.clear();
345 PromotedNodes.clear();
349 // Remove dead nodes now.
350 DAG.RemoveDeadNodes(OldRoot.Val);
354 /// FindCallEndFromCallStart - Given a chained node that is part of a call
355 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
356 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
357 if (Node->getOpcode() == ISD::CALLSEQ_END)
359 if (Node->use_empty())
360 return 0; // No CallSeqEnd
362 // The chain is usually at the end.
363 SDOperand TheChain(Node, Node->getNumValues()-1);
364 if (TheChain.getValueType() != MVT::Other) {
365 // Sometimes it's at the beginning.
366 TheChain = SDOperand(Node, 0);
367 if (TheChain.getValueType() != MVT::Other) {
368 // Otherwise, hunt for it.
369 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
370 if (Node->getValueType(i) == MVT::Other) {
371 TheChain = SDOperand(Node, i);
375 // Otherwise, we walked into a node without a chain.
376 if (TheChain.getValueType() != MVT::Other)
381 for (SDNode::use_iterator UI = Node->use_begin(),
382 E = Node->use_end(); UI != E; ++UI) {
384 // Make sure to only follow users of our token chain.
386 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
387 if (User->getOperand(i) == TheChain)
388 if (SDNode *Result = FindCallEndFromCallStart(User))
394 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
395 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
396 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
397 assert(Node && "Didn't find callseq_start for a call??");
398 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
400 assert(Node->getOperand(0).getValueType() == MVT::Other &&
401 "Node doesn't have a token chain argument!");
402 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
405 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
406 /// see if any uses can reach Dest. If no dest operands can get to dest,
407 /// legalize them, legalize ourself, and return false, otherwise, return true.
408 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N,
410 if (N == Dest) return true; // N certainly leads to Dest :)
412 // If the first result of this node has been already legalized, then it cannot
414 switch (getTypeAction(N->getValueType(0))) {
416 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
419 if (PromotedNodes.count(SDOperand(N, 0))) return false;
422 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
426 // Okay, this node has not already been legalized. Check and legalize all
427 // operands. If none lead to Dest, then we can legalize this node.
428 bool OperandsLeadToDest = false;
429 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
430 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
431 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest);
433 if (OperandsLeadToDest) return true;
435 // Okay, this node looks safe, legalize it and return false.
436 HandleOp(SDOperand(N, 0));
440 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
441 /// appropriate for its type.
442 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
443 switch (getTypeAction(Op.getValueType())) {
444 default: assert(0 && "Bad type action!");
445 case Legal: LegalizeOp(Op); break;
446 case Promote: PromoteOp(Op); break;
448 if (Op.getValueType() != MVT::Vector) {
453 unsigned NumOps = N->getNumOperands();
454 unsigned NumElements =
455 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
456 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
457 MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
458 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
459 // In the common case, this is a legal vector type, convert it to the
460 // packed operation and type now.
461 PackVectorOp(Op, PackedVT);
462 } else if (NumElements == 1) {
463 // Otherwise, if this is a single element vector, convert it to a
465 PackVectorOp(Op, EVT);
467 // Otherwise, this is a multiple element vector that isn't supported.
468 // Split it in half and legalize both parts.
470 SplitVectorOp(Op, X, Y);
478 /// LegalizeOp - We know that the specified value has a legal type.
479 /// Recursively ensure that the operands have legal types, then return the
481 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
482 assert(isTypeLegal(Op.getValueType()) &&
483 "Caller should expand or promote operands that are not legal!");
484 SDNode *Node = Op.Val;
486 // If this operation defines any values that cannot be represented in a
487 // register on this target, make sure to expand or promote them.
488 if (Node->getNumValues() > 1) {
489 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
490 if (getTypeAction(Node->getValueType(i)) != Legal) {
491 HandleOp(Op.getValue(i));
492 assert(LegalizedNodes.count(Op) &&
493 "Handling didn't add legal operands!");
494 return LegalizedNodes[Op];
498 // Note that LegalizeOp may be reentered even from single-use nodes, which
499 // means that we always must cache transformed nodes.
500 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
501 if (I != LegalizedNodes.end()) return I->second;
503 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
504 SDOperand Result = Op;
505 bool isCustom = false;
507 switch (Node->getOpcode()) {
508 case ISD::FrameIndex:
509 case ISD::EntryToken:
511 case ISD::BasicBlock:
512 case ISD::TargetFrameIndex:
513 case ISD::TargetJumpTable:
514 case ISD::TargetConstant:
515 case ISD::TargetConstantFP:
516 case ISD::TargetConstantPool:
517 case ISD::TargetGlobalAddress:
518 case ISD::TargetExternalSymbol:
523 // Primitives must all be legal.
524 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
525 "This must be legal!");
528 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
529 // If this is a target node, legalize it by legalizing the operands then
530 // passing it through.
531 std::vector<SDOperand> Ops;
532 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
533 Ops.push_back(LegalizeOp(Node->getOperand(i)));
535 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops);
537 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
538 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
539 return Result.getValue(Op.ResNo);
541 // Otherwise this is an unhandled builtin node. splat.
542 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
543 assert(0 && "Do not know how to legalize this operator!");
545 case ISD::GlobalAddress:
546 case ISD::ExternalSymbol:
547 case ISD::ConstantPool:
548 case ISD::JumpTable: // Nothing to do.
549 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
550 default: assert(0 && "This action is not supported yet!");
551 case TargetLowering::Custom:
552 Tmp1 = TLI.LowerOperation(Op, DAG);
553 if (Tmp1.Val) Result = Tmp1;
554 // FALLTHROUGH if the target doesn't want to lower this op after all.
555 case TargetLowering::Legal:
559 case ISD::AssertSext:
560 case ISD::AssertZext:
561 Tmp1 = LegalizeOp(Node->getOperand(0));
562 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
564 case ISD::MERGE_VALUES:
565 // Legalize eliminates MERGE_VALUES nodes.
566 Result = Node->getOperand(Op.ResNo);
568 case ISD::CopyFromReg:
569 Tmp1 = LegalizeOp(Node->getOperand(0));
570 Result = Op.getValue(0);
571 if (Node->getNumValues() == 2) {
572 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
574 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
575 if (Node->getNumOperands() == 3) {
576 Tmp2 = LegalizeOp(Node->getOperand(2));
577 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
579 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
581 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
583 // Since CopyFromReg produces two values, make sure to remember that we
584 // legalized both of them.
585 AddLegalizedOperand(Op.getValue(0), Result);
586 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
587 return Result.getValue(Op.ResNo);
589 MVT::ValueType VT = Op.getValueType();
590 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
591 default: assert(0 && "This action is not supported yet!");
592 case TargetLowering::Expand:
593 if (MVT::isInteger(VT))
594 Result = DAG.getConstant(0, VT);
595 else if (MVT::isFloatingPoint(VT))
596 Result = DAG.getConstantFP(0, VT);
598 assert(0 && "Unknown value type!");
600 case TargetLowering::Legal:
606 case ISD::INTRINSIC_W_CHAIN:
607 case ISD::INTRINSIC_WO_CHAIN:
608 case ISD::INTRINSIC_VOID: {
609 std::vector<SDOperand> Ops;
610 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
611 Ops.push_back(LegalizeOp(Node->getOperand(i)));
612 Result = DAG.UpdateNodeOperands(Result, Ops);
614 // Allow the target to custom lower its intrinsics if it wants to.
615 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
616 TargetLowering::Custom) {
617 Tmp3 = TLI.LowerOperation(Result, DAG);
618 if (Tmp3.Val) Result = Tmp3;
621 if (Result.Val->getNumValues() == 1) break;
623 // Must have return value and chain result.
624 assert(Result.Val->getNumValues() == 2 &&
625 "Cannot return more than two values!");
627 // Since loads produce two values, make sure to remember that we
628 // legalized both of them.
629 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
630 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
631 return Result.getValue(Op.ResNo);
635 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
636 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
638 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
639 case TargetLowering::Promote:
640 default: assert(0 && "This action is not supported yet!");
641 case TargetLowering::Expand: {
642 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
643 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
644 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
646 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
647 const std::string &FName =
648 cast<StringSDNode>(Node->getOperand(3))->getValue();
649 const std::string &DirName =
650 cast<StringSDNode>(Node->getOperand(4))->getValue();
651 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
653 std::vector<SDOperand> Ops;
654 Ops.push_back(Tmp1); // chain
655 SDOperand LineOp = Node->getOperand(1);
656 SDOperand ColOp = Node->getOperand(2);
659 Ops.push_back(LineOp); // line #
660 Ops.push_back(ColOp); // col #
661 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
662 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
664 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
665 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
666 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
667 Ops.push_back(DAG.getConstant(ID, MVT::i32));
668 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops);
671 Result = Tmp1; // chain
675 case TargetLowering::Legal:
676 if (Tmp1 != Node->getOperand(0) ||
677 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
678 std::vector<SDOperand> Ops;
680 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
681 Ops.push_back(Node->getOperand(1)); // line # must be legal.
682 Ops.push_back(Node->getOperand(2)); // col # must be legal.
684 // Otherwise promote them.
685 Ops.push_back(PromoteOp(Node->getOperand(1)));
686 Ops.push_back(PromoteOp(Node->getOperand(2)));
688 Ops.push_back(Node->getOperand(3)); // filename must be legal.
689 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
690 Result = DAG.UpdateNodeOperands(Result, Ops);
697 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
698 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
699 default: assert(0 && "This action is not supported yet!");
700 case TargetLowering::Legal:
701 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
702 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
703 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
704 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
705 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
710 case ISD::DEBUG_LABEL:
711 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
712 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
713 default: assert(0 && "This action is not supported yet!");
714 case TargetLowering::Legal:
715 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
716 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
717 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
723 // We know we don't need to expand constants here, constants only have one
724 // value and we check that it is fine above.
726 // FIXME: Maybe we should handle things like targets that don't support full
727 // 32-bit immediates?
729 case ISD::ConstantFP: {
730 // Spill FP immediates to the constant pool if the target cannot directly
731 // codegen them. Targets often have some immediate values that can be
732 // efficiently generated into an FP register without a load. We explicitly
733 // leave these constants as ConstantFP nodes for the target to deal with.
734 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
736 // Check to see if this FP immediate is already legal.
737 bool isLegal = false;
738 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
739 E = TLI.legal_fpimm_end(); I != E; ++I)
740 if (CFP->isExactlyValue(*I)) {
745 // If this is a legal constant, turn it into a TargetConstantFP node.
747 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
751 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
752 default: assert(0 && "This action is not supported yet!");
753 case TargetLowering::Custom:
754 Tmp3 = TLI.LowerOperation(Result, DAG);
760 case TargetLowering::Expand:
761 // Otherwise we need to spill the constant to memory.
764 // If a FP immediate is precise when represented as a float and if the
765 // target can do an extending load from float to double, we put it into
766 // the constant pool as a float, even if it's is statically typed as a
768 MVT::ValueType VT = CFP->getValueType(0);
769 bool isDouble = VT == MVT::f64;
770 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
771 Type::FloatTy, CFP->getValue());
772 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
773 // Only do this if the target has a native EXTLOAD instruction from
775 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
776 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
781 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
783 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
784 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
786 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
787 DAG.getSrcValue(NULL));
792 case ISD::TokenFactor:
793 if (Node->getNumOperands() == 2) {
794 Tmp1 = LegalizeOp(Node->getOperand(0));
795 Tmp2 = LegalizeOp(Node->getOperand(1));
796 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
797 } else if (Node->getNumOperands() == 3) {
798 Tmp1 = LegalizeOp(Node->getOperand(0));
799 Tmp2 = LegalizeOp(Node->getOperand(1));
800 Tmp3 = LegalizeOp(Node->getOperand(2));
801 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
803 std::vector<SDOperand> Ops;
804 // Legalize the operands.
805 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
806 Ops.push_back(LegalizeOp(Node->getOperand(i)));
807 Result = DAG.UpdateNodeOperands(Result, Ops);
811 case ISD::FORMAL_ARGUMENTS:
813 // The only option for this is to custom lower it.
814 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
815 assert(Tmp3.Val && "Target didn't custom lower this node!");
816 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
817 "Lowering call/formal_arguments produced unexpected # results!");
819 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
820 // remember that we legalized all of them, so it doesn't get relegalized.
821 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
822 Tmp1 = LegalizeOp(Tmp3.getValue(i));
825 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
829 case ISD::BUILD_VECTOR:
830 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
831 default: assert(0 && "This action is not supported yet!");
832 case TargetLowering::Custom:
833 Tmp3 = TLI.LowerOperation(Result, DAG);
839 case TargetLowering::Expand:
840 Result = ExpandBUILD_VECTOR(Result.Val);
844 case ISD::INSERT_VECTOR_ELT:
845 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
846 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
847 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
848 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
850 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
851 Node->getValueType(0))) {
852 default: assert(0 && "This action is not supported yet!");
853 case TargetLowering::Legal:
855 case TargetLowering::Custom:
856 Tmp3 = TLI.LowerOperation(Result, DAG);
862 case TargetLowering::Expand: {
863 // If the insert index is a constant, codegen this as a scalar_to_vector,
864 // then a shuffle that inserts it into the right position in the vector.
865 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
866 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
867 Tmp1.getValueType(), Tmp2);
869 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
870 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
871 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT);
873 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
874 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
876 std::vector<SDOperand> ShufOps;
877 for (unsigned i = 0; i != NumElts; ++i) {
878 if (i != InsertPos->getValue())
879 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
881 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
883 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,ShufOps);
885 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
886 Tmp1, ScVec, ShufMask);
887 Result = LegalizeOp(Result);
891 // If the target doesn't support this, we have to spill the input vector
892 // to a temporary stack slot, update the element, then reload it. This is
893 // badness. We could also load the value into a vector register (either
894 // with a "move to register" or "extload into register" instruction, then
895 // permute it into place, if the idx is a constant and if the idx is
896 // supported by the target.
897 MVT::ValueType VT = Tmp1.getValueType();
898 MVT::ValueType EltVT = Tmp2.getValueType();
899 MVT::ValueType IdxVT = Tmp3.getValueType();
900 MVT::ValueType PtrVT = TLI.getPointerTy();
901 SDOperand StackPtr = CreateStackTemporary(VT);
903 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
904 Tmp1, StackPtr, DAG.getSrcValue(NULL));
906 // Truncate or zero extend offset to target pointer type.
907 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
908 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
909 // Add the offset to the index.
910 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
911 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
912 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
913 // Store the scalar value.
914 Ch = DAG.getNode(ISD::STORE, MVT::Other, Ch,
915 Tmp2, StackPtr2, DAG.getSrcValue(NULL));
916 // Load the updated vector.
917 Result = DAG.getLoad(VT, Ch, StackPtr, DAG.getSrcValue(NULL));
922 case ISD::SCALAR_TO_VECTOR:
923 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
924 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
928 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
929 Result = DAG.UpdateNodeOperands(Result, Tmp1);
930 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
931 Node->getValueType(0))) {
932 default: assert(0 && "This action is not supported yet!");
933 case TargetLowering::Legal:
935 case TargetLowering::Custom:
936 Tmp3 = TLI.LowerOperation(Result, DAG);
942 case TargetLowering::Expand:
943 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
947 case ISD::VECTOR_SHUFFLE:
948 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
949 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
950 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
952 // Allow targets to custom lower the SHUFFLEs they support.
953 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
954 default: assert(0 && "Unknown operation action!");
955 case TargetLowering::Legal:
956 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
957 "vector shuffle should not be created if not legal!");
959 case TargetLowering::Custom:
960 Tmp3 = TLI.LowerOperation(Result, DAG);
966 case TargetLowering::Expand: {
967 MVT::ValueType VT = Node->getValueType(0);
968 MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
969 MVT::ValueType PtrVT = TLI.getPointerTy();
970 SDOperand Mask = Node->getOperand(2);
971 unsigned NumElems = Mask.getNumOperands();
972 std::vector<SDOperand> Ops;
973 for (unsigned i = 0; i != NumElems; ++i) {
974 SDOperand Arg = Mask.getOperand(i);
975 if (Arg.getOpcode() == ISD::UNDEF) {
976 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
978 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
979 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
981 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
982 DAG.getConstant(Idx, PtrVT)));
984 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
985 DAG.getConstant(Idx - NumElems, PtrVT)));
988 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, Ops);
991 case TargetLowering::Promote: {
992 // Change base type to a different vector type.
993 MVT::ValueType OVT = Node->getValueType(0);
994 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
996 // Cast the two input vectors.
997 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
998 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1000 // Convert the shuffle mask to the right # elements.
1001 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1002 assert(Tmp3.Val && "Shuffle not legal?");
1003 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1004 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1010 case ISD::EXTRACT_VECTOR_ELT:
1011 Tmp1 = LegalizeOp(Node->getOperand(0));
1012 Tmp2 = LegalizeOp(Node->getOperand(1));
1013 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1015 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
1016 Tmp1.getValueType())) {
1017 default: assert(0 && "This action is not supported yet!");
1018 case TargetLowering::Legal:
1020 case TargetLowering::Custom:
1021 Tmp3 = TLI.LowerOperation(Result, DAG);
1027 case TargetLowering::Expand:
1028 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1033 case ISD::VEXTRACT_VECTOR_ELT:
1034 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
1037 case ISD::CALLSEQ_START: {
1038 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1040 // Recursively Legalize all of the inputs of the call end that do not lead
1041 // to this call start. This ensures that any libcalls that need be inserted
1042 // are inserted *before* the CALLSEQ_START.
1043 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1044 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node);
1046 // Now that we legalized all of the inputs (which may have inserted
1047 // libcalls) create the new CALLSEQ_START node.
1048 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1050 // Merge in the last call, to ensure that this call start after the last
1052 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1053 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1054 Tmp1 = LegalizeOp(Tmp1);
1057 // Do not try to legalize the target-specific arguments (#1+).
1058 if (Tmp1 != Node->getOperand(0)) {
1059 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
1061 Result = DAG.UpdateNodeOperands(Result, Ops);
1064 // Remember that the CALLSEQ_START is legalized.
1065 AddLegalizedOperand(Op.getValue(0), Result);
1066 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1067 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1069 // Now that the callseq_start and all of the non-call nodes above this call
1070 // sequence have been legalized, legalize the call itself. During this
1071 // process, no libcalls can/will be inserted, guaranteeing that no calls
1073 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1074 SDOperand InCallSEQ = LastCALLSEQ_END;
1075 // Note that we are selecting this call!
1076 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1077 IsLegalizingCall = true;
1079 // Legalize the call, starting from the CALLSEQ_END.
1080 LegalizeOp(LastCALLSEQ_END);
1081 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1084 case ISD::CALLSEQ_END:
1085 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1086 // will cause this node to be legalized as well as handling libcalls right.
1087 if (LastCALLSEQ_END.Val != Node) {
1088 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1089 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1090 assert(I != LegalizedNodes.end() &&
1091 "Legalizing the call start should have legalized this node!");
1095 // Otherwise, the call start has been legalized and everything is going
1096 // according to plan. Just legalize ourselves normally here.
1097 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1098 // Do not try to legalize the target-specific arguments (#1+), except for
1099 // an optional flag input.
1100 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1101 if (Tmp1 != Node->getOperand(0)) {
1102 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
1104 Result = DAG.UpdateNodeOperands(Result, Ops);
1107 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1108 if (Tmp1 != Node->getOperand(0) ||
1109 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1110 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
1113 Result = DAG.UpdateNodeOperands(Result, Ops);
1116 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1117 // This finishes up call legalization.
1118 IsLegalizingCall = false;
1120 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1121 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1122 if (Node->getNumValues() == 2)
1123 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1124 return Result.getValue(Op.ResNo);
1125 case ISD::DYNAMIC_STACKALLOC: {
1126 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1127 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1128 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1129 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1131 Tmp1 = Result.getValue(0);
1132 Tmp2 = Result.getValue(1);
1133 switch (TLI.getOperationAction(Node->getOpcode(),
1134 Node->getValueType(0))) {
1135 default: assert(0 && "This action is not supported yet!");
1136 case TargetLowering::Expand: {
1137 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1138 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1139 " not tell us which reg is the stack pointer!");
1140 SDOperand Chain = Tmp1.getOperand(0);
1141 SDOperand Size = Tmp2.getOperand(1);
1142 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1143 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1144 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1145 Tmp1 = LegalizeOp(Tmp1);
1146 Tmp2 = LegalizeOp(Tmp2);
1149 case TargetLowering::Custom:
1150 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1152 Tmp1 = LegalizeOp(Tmp3);
1153 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1156 case TargetLowering::Legal:
1159 // Since this op produce two values, make sure to remember that we
1160 // legalized both of them.
1161 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1162 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1163 return Op.ResNo ? Tmp2 : Tmp1;
1165 case ISD::INLINEASM:
1166 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize Chain.
1167 Tmp2 = Node->getOperand(Node->getNumOperands()-1);
1168 if (Tmp2.getValueType() == MVT::Flag) // Legalize Flag if it exists.
1169 Tmp2 = Tmp3 = SDOperand(0, 0);
1171 Tmp3 = LegalizeOp(Tmp2);
1173 if (Tmp1 != Node->getOperand(0) || Tmp2 != Tmp3) {
1174 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
1176 if (Tmp3.Val) Ops.back() = Tmp3;
1177 Result = DAG.UpdateNodeOperands(Result, Ops);
1180 // INLINE asm returns a chain and flag, make sure to add both to the map.
1181 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1182 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1183 return Result.getValue(Op.ResNo);
1185 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1186 // Ensure that libcalls are emitted before a branch.
1187 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1188 Tmp1 = LegalizeOp(Tmp1);
1189 LastCALLSEQ_END = DAG.getEntryNode();
1191 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1194 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1195 // Ensure that libcalls are emitted before a branch.
1196 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1197 Tmp1 = LegalizeOp(Tmp1);
1198 LastCALLSEQ_END = DAG.getEntryNode();
1200 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1201 default: assert(0 && "Indirect target must be legal type (pointer)!");
1203 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1206 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1209 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1210 // Ensure that libcalls are emitted before a return.
1211 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1212 Tmp1 = LegalizeOp(Tmp1);
1213 LastCALLSEQ_END = DAG.getEntryNode();
1215 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1216 case Expand: assert(0 && "It's impossible to expand bools");
1218 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1221 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1225 // Basic block destination (Op#2) is always legal.
1226 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1228 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1229 default: assert(0 && "This action is not supported yet!");
1230 case TargetLowering::Legal: break;
1231 case TargetLowering::Custom:
1232 Tmp1 = TLI.LowerOperation(Result, DAG);
1233 if (Tmp1.Val) Result = Tmp1;
1235 case TargetLowering::Expand:
1236 // Expand brcond's setcc into its constituent parts and create a BR_CC
1238 if (Tmp2.getOpcode() == ISD::SETCC) {
1239 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1240 Tmp2.getOperand(0), Tmp2.getOperand(1),
1241 Node->getOperand(2));
1243 // Make sure the condition is either zero or one. It may have been
1244 // promoted from something else.
1245 unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType());
1246 if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1))
1247 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1249 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1250 DAG.getCondCode(ISD::SETNE), Tmp2,
1251 DAG.getConstant(0, Tmp2.getValueType()),
1252 Node->getOperand(2));
1258 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1259 // Ensure that libcalls are emitted before a branch.
1260 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1261 Tmp1 = LegalizeOp(Tmp1);
1262 LastCALLSEQ_END = DAG.getEntryNode();
1264 Tmp2 = Node->getOperand(2); // LHS
1265 Tmp3 = Node->getOperand(3); // RHS
1266 Tmp4 = Node->getOperand(1); // CC
1268 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1270 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1271 // the LHS is a legal SETCC itself. In this case, we need to compare
1272 // the result against zero to select between true and false values.
1273 if (Tmp3.Val == 0) {
1274 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1275 Tmp4 = DAG.getCondCode(ISD::SETNE);
1278 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1279 Node->getOperand(4));
1281 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1282 default: assert(0 && "Unexpected action for BR_CC!");
1283 case TargetLowering::Legal: break;
1284 case TargetLowering::Custom:
1285 Tmp4 = TLI.LowerOperation(Result, DAG);
1286 if (Tmp4.Val) Result = Tmp4;
1291 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1292 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1294 MVT::ValueType VT = Node->getValueType(0);
1295 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1296 Tmp3 = Result.getValue(0);
1297 Tmp4 = Result.getValue(1);
1299 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1300 default: assert(0 && "This action is not supported yet!");
1301 case TargetLowering::Legal: break;
1302 case TargetLowering::Custom:
1303 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1305 Tmp3 = LegalizeOp(Tmp1);
1306 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1309 case TargetLowering::Promote: {
1310 // Only promote a load of vector type to another.
1311 assert(MVT::isVector(VT) && "Cannot promote this load!");
1312 // Change base type to a different vector type.
1313 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1315 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, Node->getOperand(2));
1316 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1317 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1321 // Since loads produce two values, make sure to remember that we
1322 // legalized both of them.
1323 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1324 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1325 return Op.ResNo ? Tmp4 : Tmp3;
1329 case ISD::ZEXTLOAD: {
1330 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1331 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1333 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
1334 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
1335 default: assert(0 && "This action is not supported yet!");
1336 case TargetLowering::Promote:
1337 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
1338 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1339 DAG.getValueType(MVT::i8));
1340 Tmp1 = Result.getValue(0);
1341 Tmp2 = Result.getValue(1);
1343 case TargetLowering::Custom:
1346 case TargetLowering::Legal:
1347 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1348 Node->getOperand(3));
1349 Tmp1 = Result.getValue(0);
1350 Tmp2 = Result.getValue(1);
1353 Tmp3 = TLI.LowerOperation(Tmp3, DAG);
1355 Tmp1 = LegalizeOp(Tmp3);
1356 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1360 case TargetLowering::Expand:
1361 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1362 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1363 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
1364 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1365 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1366 Tmp2 = LegalizeOp(Load.getValue(1));
1369 assert(Node->getOpcode() != ISD::EXTLOAD &&
1370 "EXTLOAD should always be supported!");
1371 // Turn the unsupported load into an EXTLOAD followed by an explicit
1372 // zero/sign extend inreg.
1373 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1374 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1376 if (Node->getOpcode() == ISD::SEXTLOAD)
1377 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1378 Result, DAG.getValueType(SrcVT));
1380 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1381 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1382 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1385 // Since loads produce two values, make sure to remember that we legalized
1387 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1388 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1389 return Op.ResNo ? Tmp2 : Tmp1;
1391 case ISD::EXTRACT_ELEMENT: {
1392 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1393 switch (getTypeAction(OpTy)) {
1394 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1396 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1398 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1399 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1400 TLI.getShiftAmountTy()));
1401 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1404 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1405 Node->getOperand(0));
1409 // Get both the low and high parts.
1410 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1411 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1412 Result = Tmp2; // 1 -> Hi
1414 Result = Tmp1; // 0 -> Lo
1420 case ISD::CopyToReg:
1421 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1423 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1424 "Register type must be legal!");
1425 // Legalize the incoming value (must be a legal type).
1426 Tmp2 = LegalizeOp(Node->getOperand(2));
1427 if (Node->getNumValues() == 1) {
1428 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1430 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1431 if (Node->getNumOperands() == 4) {
1432 Tmp3 = LegalizeOp(Node->getOperand(3));
1433 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1436 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1439 // Since this produces two values, make sure to remember that we legalized
1441 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1442 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1448 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1450 // Ensure that libcalls are emitted before a return.
1451 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1452 Tmp1 = LegalizeOp(Tmp1);
1453 LastCALLSEQ_END = DAG.getEntryNode();
1455 switch (Node->getNumOperands()) {
1457 Tmp2 = Node->getOperand(1);
1458 Tmp3 = Node->getOperand(2); // Signness
1459 switch (getTypeAction(Tmp2.getValueType())) {
1461 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1464 if (Tmp2.getValueType() != MVT::Vector) {
1466 ExpandOp(Tmp2, Lo, Hi);
1467 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1469 SDNode *InVal = Tmp2.Val;
1471 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1472 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1474 // Figure out if there is a Packed type corresponding to this Vector
1475 // type. If so, convert to the packed type.
1476 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1477 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1478 // Turn this into a return of the packed type.
1479 Tmp2 = PackVectorOp(Tmp2, TVT);
1480 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1481 } else if (NumElems == 1) {
1482 // Turn this into a return of the scalar type.
1483 Tmp2 = PackVectorOp(Tmp2, EVT);
1484 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1486 // FIXME: Returns of gcc generic vectors smaller than a legal type
1487 // should be returned in integer registers!
1489 // The scalarized value type may not be legal, e.g. it might require
1490 // promotion or expansion. Relegalize the return.
1491 Result = LegalizeOp(Result);
1493 // FIXME: Returns of gcc generic vectors larger than a legal vector
1494 // type should be returned by reference!
1496 SplitVectorOp(Tmp2, Lo, Hi);
1497 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1498 Result = LegalizeOp(Result);
1503 Tmp2 = PromoteOp(Node->getOperand(1));
1504 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1505 Result = LegalizeOp(Result);
1510 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1512 default: { // ret <values>
1513 std::vector<SDOperand> NewValues;
1514 NewValues.push_back(Tmp1);
1515 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1516 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1518 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1519 NewValues.push_back(Node->getOperand(i+1));
1523 assert(Node->getOperand(i).getValueType() != MVT::Vector &&
1524 "FIXME: TODO: implement returning non-legal vector types!");
1525 ExpandOp(Node->getOperand(i), Lo, Hi);
1526 NewValues.push_back(Lo);
1527 NewValues.push_back(Node->getOperand(i+1));
1528 NewValues.push_back(Hi);
1529 NewValues.push_back(Node->getOperand(i+1));
1533 assert(0 && "Can't promote multiple return value yet!");
1536 if (NewValues.size() == Node->getNumOperands())
1537 Result = DAG.UpdateNodeOperands(Result, NewValues);
1539 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
1544 if (Result.getOpcode() == ISD::RET) {
1545 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1546 default: assert(0 && "This action is not supported yet!");
1547 case TargetLowering::Legal: break;
1548 case TargetLowering::Custom:
1549 Tmp1 = TLI.LowerOperation(Result, DAG);
1550 if (Tmp1.Val) Result = Tmp1;
1556 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1557 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1559 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1560 // FIXME: We shouldn't do this for TargetConstantFP's.
1561 // FIXME: move this to the DAG Combiner!
1562 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1563 if (CFP->getValueType(0) == MVT::f32) {
1564 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1566 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1567 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1569 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1570 Node->getOperand(3));
1574 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1576 Tmp3 = LegalizeOp(Node->getOperand(1));
1577 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1578 Node->getOperand(3));
1580 MVT::ValueType VT = Tmp3.getValueType();
1581 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1582 default: assert(0 && "This action is not supported yet!");
1583 case TargetLowering::Legal: break;
1584 case TargetLowering::Custom:
1585 Tmp1 = TLI.LowerOperation(Result, DAG);
1586 if (Tmp1.Val) Result = Tmp1;
1588 case TargetLowering::Promote:
1589 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1590 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1591 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1592 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1593 Node->getOperand(3));
1599 // Truncate the value and store the result.
1600 Tmp3 = PromoteOp(Node->getOperand(1));
1601 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1602 Node->getOperand(3),
1603 DAG.getValueType(Node->getOperand(1).getValueType()));
1607 unsigned IncrementSize = 0;
1610 // If this is a vector type, then we have to calculate the increment as
1611 // the product of the element size in bytes, and the number of elements
1612 // in the high half of the vector.
1613 if (Node->getOperand(1).getValueType() == MVT::Vector) {
1614 SDNode *InVal = Node->getOperand(1).Val;
1616 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1617 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1619 // Figure out if there is a Packed type corresponding to this Vector
1620 // type. If so, convert to the packed type.
1621 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1622 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1623 // Turn this into a normal store of the packed type.
1624 Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1625 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1626 Node->getOperand(3));
1627 Result = LegalizeOp(Result);
1629 } else if (NumElems == 1) {
1630 // Turn this into a normal store of the scalar type.
1631 Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1632 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1633 Node->getOperand(3));
1634 // The scalarized value type may not be legal, e.g. it might require
1635 // promotion or expansion. Relegalize the scalar store.
1636 Result = LegalizeOp(Result);
1639 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1640 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1643 ExpandOp(Node->getOperand(1), Lo, Hi);
1644 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1646 if (!TLI.isLittleEndian())
1650 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1651 Node->getOperand(3));
1652 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1653 getIntPtrConstant(IncrementSize));
1654 assert(isTypeLegal(Tmp2.getValueType()) &&
1655 "Pointers must be legal!");
1656 // FIXME: This sets the srcvalue of both halves to be the same, which is
1658 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1659 Node->getOperand(3));
1660 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1666 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1667 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1669 case ISD::STACKSAVE:
1670 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1671 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1672 Tmp1 = Result.getValue(0);
1673 Tmp2 = Result.getValue(1);
1675 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1676 default: assert(0 && "This action is not supported yet!");
1677 case TargetLowering::Legal: break;
1678 case TargetLowering::Custom:
1679 Tmp3 = TLI.LowerOperation(Result, DAG);
1681 Tmp1 = LegalizeOp(Tmp3);
1682 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1685 case TargetLowering::Expand:
1686 // Expand to CopyFromReg if the target set
1687 // StackPointerRegisterToSaveRestore.
1688 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1689 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1690 Node->getValueType(0));
1691 Tmp2 = Tmp1.getValue(1);
1693 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1694 Tmp2 = Node->getOperand(0);
1699 // Since stacksave produce two values, make sure to remember that we
1700 // legalized both of them.
1701 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1702 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1703 return Op.ResNo ? Tmp2 : Tmp1;
1705 case ISD::STACKRESTORE:
1706 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1707 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1708 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1710 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1711 default: assert(0 && "This action is not supported yet!");
1712 case TargetLowering::Legal: break;
1713 case TargetLowering::Custom:
1714 Tmp1 = TLI.LowerOperation(Result, DAG);
1715 if (Tmp1.Val) Result = Tmp1;
1717 case TargetLowering::Expand:
1718 // Expand to CopyToReg if the target set
1719 // StackPointerRegisterToSaveRestore.
1720 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1721 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1729 case ISD::READCYCLECOUNTER:
1730 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1731 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1733 // Since rdcc produce two values, make sure to remember that we legalized
1735 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1736 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1739 case ISD::TRUNCSTORE: {
1740 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1741 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1743 assert(isTypeLegal(Node->getOperand(1).getValueType()) &&
1744 "Cannot handle illegal TRUNCSTORE yet!");
1745 Tmp2 = LegalizeOp(Node->getOperand(1));
1747 // The only promote case we handle is TRUNCSTORE:i1 X into
1748 // -> TRUNCSTORE:i8 (and X, 1)
1749 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1750 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1751 TargetLowering::Promote) {
1752 // Promote the bool to a mask then store.
1753 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1754 DAG.getConstant(1, Tmp2.getValueType()));
1755 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1756 Node->getOperand(3), DAG.getValueType(MVT::i8));
1758 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1759 Tmp3 != Node->getOperand(2)) {
1760 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
1761 Node->getOperand(3), Node->getOperand(4));
1764 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT();
1765 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) {
1766 default: assert(0 && "This action is not supported yet!");
1767 case TargetLowering::Legal: break;
1768 case TargetLowering::Custom:
1769 Tmp1 = TLI.LowerOperation(Result, DAG);
1770 if (Tmp1.Val) Result = Tmp1;
1776 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1777 case Expand: assert(0 && "It's impossible to expand bools");
1779 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1782 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1785 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1786 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1788 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1790 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1791 default: assert(0 && "This action is not supported yet!");
1792 case TargetLowering::Legal: break;
1793 case TargetLowering::Custom: {
1794 Tmp1 = TLI.LowerOperation(Result, DAG);
1795 if (Tmp1.Val) Result = Tmp1;
1798 case TargetLowering::Expand:
1799 if (Tmp1.getOpcode() == ISD::SETCC) {
1800 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1802 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1804 // Make sure the condition is either zero or one. It may have been
1805 // promoted from something else.
1806 unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType());
1807 if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1))
1808 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1809 Result = DAG.getSelectCC(Tmp1,
1810 DAG.getConstant(0, Tmp1.getValueType()),
1811 Tmp2, Tmp3, ISD::SETNE);
1814 case TargetLowering::Promote: {
1815 MVT::ValueType NVT =
1816 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1817 unsigned ExtOp, TruncOp;
1818 if (MVT::isVector(Tmp2.getValueType())) {
1819 ExtOp = ISD::BIT_CONVERT;
1820 TruncOp = ISD::BIT_CONVERT;
1821 } else if (MVT::isInteger(Tmp2.getValueType())) {
1822 ExtOp = ISD::ANY_EXTEND;
1823 TruncOp = ISD::TRUNCATE;
1825 ExtOp = ISD::FP_EXTEND;
1826 TruncOp = ISD::FP_ROUND;
1828 // Promote each of the values to the new type.
1829 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1830 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1831 // Perform the larger operation, then round down.
1832 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1833 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1838 case ISD::SELECT_CC: {
1839 Tmp1 = Node->getOperand(0); // LHS
1840 Tmp2 = Node->getOperand(1); // RHS
1841 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1842 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1843 SDOperand CC = Node->getOperand(4);
1845 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
1847 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1848 // the LHS is a legal SETCC itself. In this case, we need to compare
1849 // the result against zero to select between true and false values.
1850 if (Tmp2.Val == 0) {
1851 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1852 CC = DAG.getCondCode(ISD::SETNE);
1854 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
1856 // Everything is legal, see if we should expand this op or something.
1857 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
1858 default: assert(0 && "This action is not supported yet!");
1859 case TargetLowering::Legal: break;
1860 case TargetLowering::Custom:
1861 Tmp1 = TLI.LowerOperation(Result, DAG);
1862 if (Tmp1.Val) Result = Tmp1;
1868 Tmp1 = Node->getOperand(0);
1869 Tmp2 = Node->getOperand(1);
1870 Tmp3 = Node->getOperand(2);
1871 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
1873 // If we had to Expand the SetCC operands into a SELECT node, then it may
1874 // not always be possible to return a true LHS & RHS. In this case, just
1875 // return the value we legalized, returned in the LHS
1876 if (Tmp2.Val == 0) {
1881 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
1882 default: assert(0 && "Cannot handle this action for SETCC yet!");
1883 case TargetLowering::Custom:
1886 case TargetLowering::Legal:
1887 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1889 Tmp3 = TLI.LowerOperation(Result, DAG);
1890 if (Tmp3.Val) Result = Tmp3;
1893 case TargetLowering::Promote: {
1894 // First step, figure out the appropriate operation to use.
1895 // Allow SETCC to not be supported for all legal data types
1896 // Mostly this targets FP
1897 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1898 MVT::ValueType OldVT = NewInTy;
1900 // Scan for the appropriate larger type to use.
1902 NewInTy = (MVT::ValueType)(NewInTy+1);
1904 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1905 "Fell off of the edge of the integer world");
1906 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1907 "Fell off of the edge of the floating point world");
1909 // If the target supports SETCC of this type, use it.
1910 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
1913 if (MVT::isInteger(NewInTy))
1914 assert(0 && "Cannot promote Legal Integer SETCC yet");
1916 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1917 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
1919 Tmp1 = LegalizeOp(Tmp1);
1920 Tmp2 = LegalizeOp(Tmp2);
1921 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1922 Result = LegalizeOp(Result);
1925 case TargetLowering::Expand:
1926 // Expand a setcc node into a select_cc of the same condition, lhs, and
1927 // rhs that selects between const 1 (true) and const 0 (false).
1928 MVT::ValueType VT = Node->getValueType(0);
1929 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1930 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1931 Node->getOperand(2));
1937 case ISD::MEMMOVE: {
1938 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1939 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1941 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1942 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1943 case Expand: assert(0 && "Cannot expand a byte!");
1945 Tmp3 = LegalizeOp(Node->getOperand(2));
1948 Tmp3 = PromoteOp(Node->getOperand(2));
1952 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1956 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1958 // Length is too big, just take the lo-part of the length.
1960 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
1964 Tmp4 = LegalizeOp(Node->getOperand(3));
1967 Tmp4 = PromoteOp(Node->getOperand(3));
1972 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
1973 case Expand: assert(0 && "Cannot expand this yet!");
1975 Tmp5 = LegalizeOp(Node->getOperand(4));
1978 Tmp5 = PromoteOp(Node->getOperand(4));
1982 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1983 default: assert(0 && "This action not implemented for this operation!");
1984 case TargetLowering::Custom:
1987 case TargetLowering::Legal:
1988 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
1990 Tmp1 = TLI.LowerOperation(Result, DAG);
1991 if (Tmp1.Val) Result = Tmp1;
1994 case TargetLowering::Expand: {
1995 // Otherwise, the target does not support this operation. Lower the
1996 // operation to an explicit libcall as appropriate.
1997 MVT::ValueType IntPtr = TLI.getPointerTy();
1998 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
1999 std::vector<std::pair<SDOperand, const Type*> > Args;
2001 const char *FnName = 0;
2002 if (Node->getOpcode() == ISD::MEMSET) {
2003 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2004 // Extend the (previously legalized) ubyte argument to be an int value
2006 if (Tmp3.getValueType() > MVT::i32)
2007 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2009 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2010 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
2011 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2014 } else if (Node->getOpcode() == ISD::MEMCPY ||
2015 Node->getOpcode() == ISD::MEMMOVE) {
2016 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2017 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
2018 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2019 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2021 assert(0 && "Unknown op!");
2024 std::pair<SDOperand,SDOperand> CallResult =
2025 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
2026 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2027 Result = CallResult.second;
2034 case ISD::SHL_PARTS:
2035 case ISD::SRA_PARTS:
2036 case ISD::SRL_PARTS: {
2037 std::vector<SDOperand> Ops;
2038 bool Changed = false;
2039 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2040 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2041 Changed |= Ops.back() != Node->getOperand(i);
2044 Result = DAG.UpdateNodeOperands(Result, Ops);
2046 switch (TLI.getOperationAction(Node->getOpcode(),
2047 Node->getValueType(0))) {
2048 default: assert(0 && "This action is not supported yet!");
2049 case TargetLowering::Legal: break;
2050 case TargetLowering::Custom:
2051 Tmp1 = TLI.LowerOperation(Result, DAG);
2053 SDOperand Tmp2, RetVal(0, 0);
2054 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2055 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2056 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2060 assert(RetVal.Val && "Illegal result number");
2066 // Since these produce multiple values, make sure to remember that we
2067 // legalized all of them.
2068 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2069 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2070 return Result.getValue(Op.ResNo);
2091 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2092 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2093 case Expand: assert(0 && "Not possible");
2095 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2098 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2102 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2104 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2105 default: assert(0 && "BinOp legalize operation not supported");
2106 case TargetLowering::Legal: break;
2107 case TargetLowering::Custom:
2108 Tmp1 = TLI.LowerOperation(Result, DAG);
2109 if (Tmp1.Val) Result = Tmp1;
2111 case TargetLowering::Expand: {
2112 assert(MVT::isVector(Node->getValueType(0)) &&
2113 "Cannot expand this binary operator!");
2114 // Expand the operation into a bunch of nasty scalar code.
2115 std::vector<SDOperand> Ops;
2116 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
2117 MVT::ValueType PtrVT = TLI.getPointerTy();
2118 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2120 SDOperand Idx = DAG.getConstant(i, PtrVT);
2121 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2122 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2123 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2125 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), Ops);
2128 case TargetLowering::Promote: {
2129 switch (Node->getOpcode()) {
2130 default: assert(0 && "Do not know how to promote this BinOp!");
2134 MVT::ValueType OVT = Node->getValueType(0);
2135 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2136 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2137 // Bit convert each of the values to the new type.
2138 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2139 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2140 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2141 // Bit convert the result back the original type.
2142 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2150 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2151 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2152 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2153 case Expand: assert(0 && "Not possible");
2155 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2158 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2162 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2164 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2165 default: assert(0 && "Operation not supported");
2166 case TargetLowering::Custom:
2167 Tmp1 = TLI.LowerOperation(Result, DAG);
2168 if (Tmp1.Val) Result = Tmp1;
2170 case TargetLowering::Legal: break;
2171 case TargetLowering::Expand:
2172 // If this target supports fabs/fneg natively, do this efficiently.
2173 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
2174 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
2175 // Get the sign bit of the RHS.
2176 MVT::ValueType IVT =
2177 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2178 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2179 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2180 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2181 // Get the absolute value of the result.
2182 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2183 // Select between the nabs and abs value based on the sign bit of
2185 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2186 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2189 Result = LegalizeOp(Result);
2193 // Otherwise, do bitwise ops!
2195 // copysign -> copysignf/copysign libcall.
2197 if (Node->getValueType(0) == MVT::f32) {
2198 FnName = "copysignf";
2199 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type.
2200 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2201 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2));
2203 FnName = "copysign";
2204 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type.
2205 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2206 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2));
2209 Result = ExpandLibCall(FnName, Node, Dummy);
2216 Tmp1 = LegalizeOp(Node->getOperand(0));
2217 Tmp2 = LegalizeOp(Node->getOperand(1));
2218 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2219 // Since this produces two values, make sure to remember that we legalized
2221 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2222 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2227 Tmp1 = LegalizeOp(Node->getOperand(0));
2228 Tmp2 = LegalizeOp(Node->getOperand(1));
2229 Tmp3 = LegalizeOp(Node->getOperand(2));
2230 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2231 // Since this produces two values, make sure to remember that we legalized
2233 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2234 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2237 case ISD::BUILD_PAIR: {
2238 MVT::ValueType PairTy = Node->getValueType(0);
2239 // TODO: handle the case where the Lo and Hi operands are not of legal type
2240 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2241 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2242 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2243 case TargetLowering::Promote:
2244 case TargetLowering::Custom:
2245 assert(0 && "Cannot promote/custom this yet!");
2246 case TargetLowering::Legal:
2247 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2248 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2250 case TargetLowering::Expand:
2251 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2252 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2253 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2254 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2255 TLI.getShiftAmountTy()));
2256 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2265 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2266 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2268 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2269 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2270 case TargetLowering::Custom:
2273 case TargetLowering::Legal:
2274 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2276 Tmp1 = TLI.LowerOperation(Result, DAG);
2277 if (Tmp1.Val) Result = Tmp1;
2280 case TargetLowering::Expand:
2281 if (MVT::isInteger(Node->getValueType(0))) {
2283 MVT::ValueType VT = Node->getValueType(0);
2284 unsigned Opc = Node->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
2285 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
2286 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2287 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2289 // Floating point mod -> fmod libcall.
2290 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
2292 Result = ExpandLibCall(FnName, Node, Dummy);
2298 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2299 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2301 MVT::ValueType VT = Node->getValueType(0);
2302 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2303 default: assert(0 && "This action is not supported yet!");
2304 case TargetLowering::Custom:
2307 case TargetLowering::Legal:
2308 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2309 Result = Result.getValue(0);
2310 Tmp1 = Result.getValue(1);
2313 Tmp2 = TLI.LowerOperation(Result, DAG);
2315 Result = LegalizeOp(Tmp2);
2316 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2320 case TargetLowering::Expand: {
2321 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2322 Node->getOperand(2));
2323 // Increment the pointer, VAList, to the next vaarg
2324 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2325 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2326 TLI.getPointerTy()));
2327 // Store the incremented VAList to the legalized pointer
2328 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2,
2329 Node->getOperand(2));
2330 // Load the actual argument out of the pointer VAList
2331 Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0));
2332 Tmp1 = LegalizeOp(Result.getValue(1));
2333 Result = LegalizeOp(Result);
2337 // Since VAARG produces two values, make sure to remember that we
2338 // legalized both of them.
2339 AddLegalizedOperand(SDOperand(Node, 0), Result);
2340 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2341 return Op.ResNo ? Tmp1 : Result;
2345 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2346 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2347 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2349 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2350 default: assert(0 && "This action is not supported yet!");
2351 case TargetLowering::Custom:
2354 case TargetLowering::Legal:
2355 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2356 Node->getOperand(3), Node->getOperand(4));
2358 Tmp1 = TLI.LowerOperation(Result, DAG);
2359 if (Tmp1.Val) Result = Tmp1;
2362 case TargetLowering::Expand:
2363 // This defaults to loading a pointer from the input and storing it to the
2364 // output, returning the chain.
2365 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, Node->getOperand(3));
2366 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp4.getValue(1), Tmp4, Tmp2,
2367 Node->getOperand(4));
2373 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2374 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2376 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2377 default: assert(0 && "This action is not supported yet!");
2378 case TargetLowering::Custom:
2381 case TargetLowering::Legal:
2382 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2384 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2385 if (Tmp1.Val) Result = Tmp1;
2388 case TargetLowering::Expand:
2389 Result = Tmp1; // Default to a no-op, return the chain
2395 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2396 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2398 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2400 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2401 default: assert(0 && "This action is not supported yet!");
2402 case TargetLowering::Legal: break;
2403 case TargetLowering::Custom:
2404 Tmp1 = TLI.LowerOperation(Result, DAG);
2405 if (Tmp1.Val) Result = Tmp1;
2412 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2413 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2415 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2416 "Cannot handle this yet!");
2417 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2421 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2422 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2423 case TargetLowering::Custom:
2424 assert(0 && "Cannot custom legalize this yet!");
2425 case TargetLowering::Legal:
2426 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2428 case TargetLowering::Promote: {
2429 MVT::ValueType OVT = Tmp1.getValueType();
2430 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2431 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2433 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2434 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2435 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2436 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2439 case TargetLowering::Expand:
2440 Result = ExpandBSWAP(Tmp1);
2448 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2449 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2450 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2451 case TargetLowering::Legal:
2452 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2454 case TargetLowering::Promote: {
2455 MVT::ValueType OVT = Tmp1.getValueType();
2456 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2458 // Zero extend the argument.
2459 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2460 // Perform the larger operation, then subtract if needed.
2461 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2462 switch (Node->getOpcode()) {
2467 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2468 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2469 DAG.getConstant(getSizeInBits(NVT), NVT),
2471 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2472 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2475 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2476 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2477 DAG.getConstant(getSizeInBits(NVT) -
2478 getSizeInBits(OVT), NVT));
2483 case TargetLowering::Expand:
2484 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2495 Tmp1 = LegalizeOp(Node->getOperand(0));
2496 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2497 case TargetLowering::Promote:
2498 case TargetLowering::Custom:
2501 case TargetLowering::Legal:
2502 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2504 Tmp1 = TLI.LowerOperation(Result, DAG);
2505 if (Tmp1.Val) Result = Tmp1;
2508 case TargetLowering::Expand:
2509 switch (Node->getOpcode()) {
2510 default: assert(0 && "Unreachable!");
2512 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2513 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2514 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2517 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2518 MVT::ValueType VT = Node->getValueType(0);
2519 Tmp2 = DAG.getConstantFP(0.0, VT);
2520 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2521 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2522 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2528 MVT::ValueType VT = Node->getValueType(0);
2529 const char *FnName = 0;
2530 switch(Node->getOpcode()) {
2531 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2532 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2533 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2534 default: assert(0 && "Unreachable!");
2537 Result = ExpandLibCall(FnName, Node, Dummy);
2545 case ISD::BIT_CONVERT:
2546 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2547 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2549 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2550 Node->getOperand(0).getValueType())) {
2551 default: assert(0 && "Unknown operation action!");
2552 case TargetLowering::Expand:
2553 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2555 case TargetLowering::Legal:
2556 Tmp1 = LegalizeOp(Node->getOperand(0));
2557 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2562 case ISD::VBIT_CONVERT: {
2563 assert(Op.getOperand(0).getValueType() == MVT::Vector &&
2564 "Can only have VBIT_CONVERT where input or output is MVT::Vector!");
2566 // The input has to be a vector type, we have to either scalarize it, pack
2567 // it, or convert it based on whether the input vector type is legal.
2568 SDNode *InVal = Node->getOperand(0).Val;
2570 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
2571 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
2573 // Figure out if there is a Packed type corresponding to this Vector
2574 // type. If so, convert to the packed type.
2575 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2576 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
2577 // Turn this into a bit convert of the packed input.
2578 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2579 PackVectorOp(Node->getOperand(0), TVT));
2581 } else if (NumElems == 1) {
2582 // Turn this into a bit convert of the scalar input.
2583 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2584 PackVectorOp(Node->getOperand(0), EVT));
2587 // FIXME: UNIMP! Store then reload
2588 assert(0 && "Cast from unsupported vector type not implemented yet!");
2592 // Conversion operators. The source and destination have different types.
2593 case ISD::SINT_TO_FP:
2594 case ISD::UINT_TO_FP: {
2595 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2596 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2598 switch (TLI.getOperationAction(Node->getOpcode(),
2599 Node->getOperand(0).getValueType())) {
2600 default: assert(0 && "Unknown operation action!");
2601 case TargetLowering::Custom:
2604 case TargetLowering::Legal:
2605 Tmp1 = LegalizeOp(Node->getOperand(0));
2606 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2608 Tmp1 = TLI.LowerOperation(Result, DAG);
2609 if (Tmp1.Val) Result = Tmp1;
2612 case TargetLowering::Expand:
2613 Result = ExpandLegalINT_TO_FP(isSigned,
2614 LegalizeOp(Node->getOperand(0)),
2615 Node->getValueType(0));
2617 case TargetLowering::Promote:
2618 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2619 Node->getValueType(0),
2625 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2626 Node->getValueType(0), Node->getOperand(0));
2629 Tmp1 = PromoteOp(Node->getOperand(0));
2631 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2632 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2634 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2635 Node->getOperand(0).getValueType());
2637 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2638 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2644 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2646 Tmp1 = LegalizeOp(Node->getOperand(0));
2647 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2650 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2652 // Since the result is legal, we should just be able to truncate the low
2653 // part of the source.
2654 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2657 Result = PromoteOp(Node->getOperand(0));
2658 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2663 case ISD::FP_TO_SINT:
2664 case ISD::FP_TO_UINT:
2665 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2667 Tmp1 = LegalizeOp(Node->getOperand(0));
2669 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2670 default: assert(0 && "Unknown operation action!");
2671 case TargetLowering::Custom:
2674 case TargetLowering::Legal:
2675 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2677 Tmp1 = TLI.LowerOperation(Result, DAG);
2678 if (Tmp1.Val) Result = Tmp1;
2681 case TargetLowering::Promote:
2682 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2683 Node->getOpcode() == ISD::FP_TO_SINT);
2685 case TargetLowering::Expand:
2686 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2687 SDOperand True, False;
2688 MVT::ValueType VT = Node->getOperand(0).getValueType();
2689 MVT::ValueType NVT = Node->getValueType(0);
2690 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2691 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2692 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2693 Node->getOperand(0), Tmp2, ISD::SETLT);
2694 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2695 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2696 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2698 False = DAG.getNode(ISD::XOR, NVT, False,
2699 DAG.getConstant(1ULL << ShiftAmt, NVT));
2700 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2703 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2709 assert(0 && "Shouldn't need to expand other operators here!");
2711 Tmp1 = PromoteOp(Node->getOperand(0));
2712 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
2713 Result = LegalizeOp(Result);
2718 case ISD::ANY_EXTEND:
2719 case ISD::ZERO_EXTEND:
2720 case ISD::SIGN_EXTEND:
2721 case ISD::FP_EXTEND:
2723 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2724 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
2726 Tmp1 = LegalizeOp(Node->getOperand(0));
2727 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2730 switch (Node->getOpcode()) {
2731 case ISD::ANY_EXTEND:
2732 Tmp1 = PromoteOp(Node->getOperand(0));
2733 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
2735 case ISD::ZERO_EXTEND:
2736 Result = PromoteOp(Node->getOperand(0));
2737 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2738 Result = DAG.getZeroExtendInReg(Result,
2739 Node->getOperand(0).getValueType());
2741 case ISD::SIGN_EXTEND:
2742 Result = PromoteOp(Node->getOperand(0));
2743 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2744 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2746 DAG.getValueType(Node->getOperand(0).getValueType()));
2748 case ISD::FP_EXTEND:
2749 Result = PromoteOp(Node->getOperand(0));
2750 if (Result.getValueType() != Op.getValueType())
2751 // Dynamically dead while we have only 2 FP types.
2752 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2755 Result = PromoteOp(Node->getOperand(0));
2756 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2761 case ISD::FP_ROUND_INREG:
2762 case ISD::SIGN_EXTEND_INREG: {
2763 Tmp1 = LegalizeOp(Node->getOperand(0));
2764 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2766 // If this operation is not supported, convert it to a shl/shr or load/store
2768 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2769 default: assert(0 && "This action not supported for this op yet!");
2770 case TargetLowering::Legal:
2771 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2773 case TargetLowering::Expand:
2774 // If this is an integer extend and shifts are supported, do that.
2775 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2776 // NOTE: we could fall back on load/store here too for targets without
2777 // SAR. However, it is doubtful that any exist.
2778 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2779 MVT::getSizeInBits(ExtraVT);
2780 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2781 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2782 Node->getOperand(0), ShiftCst);
2783 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2785 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2786 // The only way we can lower this is to turn it into a STORETRUNC,
2787 // EXTLOAD pair, targetting a temporary location (a stack slot).
2789 // NOTE: there is a choice here between constantly creating new stack
2790 // slots and always reusing the same one. We currently always create
2791 // new ones, as reuse may inhibit scheduling.
2792 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2793 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty);
2794 unsigned Align = TLI.getTargetData()->getTypeAlignment(Ty);
2795 MachineFunction &MF = DAG.getMachineFunction();
2797 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2798 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2799 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2800 Node->getOperand(0), StackSlot,
2801 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2802 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2803 Result, StackSlot, DAG.getSrcValue(NULL),
2806 assert(0 && "Unknown op");
2814 assert(Result.getValueType() == Op.getValueType() &&
2815 "Bad legalization!");
2817 // Make sure that the generated code is itself legal.
2819 Result = LegalizeOp(Result);
2821 // Note that LegalizeOp may be reentered even from single-use nodes, which
2822 // means that we always must cache transformed nodes.
2823 AddLegalizedOperand(Op, Result);
2827 /// PromoteOp - Given an operation that produces a value in an invalid type,
2828 /// promote it to compute the value into a larger type. The produced value will
2829 /// have the correct bits for the low portion of the register, but no guarantee
2830 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2831 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2832 MVT::ValueType VT = Op.getValueType();
2833 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2834 assert(getTypeAction(VT) == Promote &&
2835 "Caller should expand or legalize operands that are not promotable!");
2836 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2837 "Cannot promote to smaller type!");
2839 SDOperand Tmp1, Tmp2, Tmp3;
2841 SDNode *Node = Op.Val;
2843 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2844 if (I != PromotedNodes.end()) return I->second;
2846 switch (Node->getOpcode()) {
2847 case ISD::CopyFromReg:
2848 assert(0 && "CopyFromReg must be legal!");
2850 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2851 assert(0 && "Do not know how to promote this operator!");
2854 Result = DAG.getNode(ISD::UNDEF, NVT);
2858 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2860 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2861 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2863 case ISD::ConstantFP:
2864 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2865 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2869 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2870 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2871 Node->getOperand(1), Node->getOperand(2));
2875 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2877 Result = LegalizeOp(Node->getOperand(0));
2878 assert(Result.getValueType() >= NVT &&
2879 "This truncation doesn't make sense!");
2880 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2881 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2884 // The truncation is not required, because we don't guarantee anything
2885 // about high bits anyway.
2886 Result = PromoteOp(Node->getOperand(0));
2889 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2890 // Truncate the low part of the expanded value to the result type
2891 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2894 case ISD::SIGN_EXTEND:
2895 case ISD::ZERO_EXTEND:
2896 case ISD::ANY_EXTEND:
2897 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2898 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2900 // Input is legal? Just do extend all the way to the larger type.
2901 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2904 // Promote the reg if it's smaller.
2905 Result = PromoteOp(Node->getOperand(0));
2906 // The high bits are not guaranteed to be anything. Insert an extend.
2907 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2908 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2909 DAG.getValueType(Node->getOperand(0).getValueType()));
2910 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2911 Result = DAG.getZeroExtendInReg(Result,
2912 Node->getOperand(0).getValueType());
2916 case ISD::BIT_CONVERT:
2917 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2918 Result = PromoteOp(Result);
2921 case ISD::FP_EXTEND:
2922 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2924 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2925 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2926 case Promote: assert(0 && "Unreachable with 2 FP types!");
2928 // Input is legal? Do an FP_ROUND_INREG.
2929 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
2930 DAG.getValueType(VT));
2935 case ISD::SINT_TO_FP:
2936 case ISD::UINT_TO_FP:
2937 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2939 // No extra round required here.
2940 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2944 Result = PromoteOp(Node->getOperand(0));
2945 if (Node->getOpcode() == ISD::SINT_TO_FP)
2946 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2948 DAG.getValueType(Node->getOperand(0).getValueType()));
2950 Result = DAG.getZeroExtendInReg(Result,
2951 Node->getOperand(0).getValueType());
2952 // No extra round required here.
2953 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2956 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
2957 Node->getOperand(0));
2958 // Round if we cannot tolerate excess precision.
2959 if (NoExcessFPPrecision)
2960 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2961 DAG.getValueType(VT));
2966 case ISD::SIGN_EXTEND_INREG:
2967 Result = PromoteOp(Node->getOperand(0));
2968 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2969 Node->getOperand(1));
2971 case ISD::FP_TO_SINT:
2972 case ISD::FP_TO_UINT:
2973 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2975 Tmp1 = Node->getOperand(0);
2978 // The input result is prerounded, so we don't have to do anything
2980 Tmp1 = PromoteOp(Node->getOperand(0));
2983 assert(0 && "not implemented");
2985 // If we're promoting a UINT to a larger size, check to see if the new node
2986 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
2987 // we can use that instead. This allows us to generate better code for
2988 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
2989 // legal, such as PowerPC.
2990 if (Node->getOpcode() == ISD::FP_TO_UINT &&
2991 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
2992 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
2993 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
2994 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
2996 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3002 Tmp1 = PromoteOp(Node->getOperand(0));
3003 assert(Tmp1.getValueType() == NVT);
3004 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3005 // NOTE: we do not have to do any extra rounding here for
3006 // NoExcessFPPrecision, because we know the input will have the appropriate
3007 // precision, and these operations don't modify precision at all.
3013 Tmp1 = PromoteOp(Node->getOperand(0));
3014 assert(Tmp1.getValueType() == NVT);
3015 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3016 if (NoExcessFPPrecision)
3017 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3018 DAG.getValueType(VT));
3027 // The input may have strange things in the top bits of the registers, but
3028 // these operations don't care. They may have weird bits going out, but
3029 // that too is okay if they are integer operations.
3030 Tmp1 = PromoteOp(Node->getOperand(0));
3031 Tmp2 = PromoteOp(Node->getOperand(1));
3032 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3033 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3038 Tmp1 = PromoteOp(Node->getOperand(0));
3039 Tmp2 = PromoteOp(Node->getOperand(1));
3040 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3041 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3043 // Floating point operations will give excess precision that we may not be
3044 // able to tolerate. If we DO allow excess precision, just leave it,
3045 // otherwise excise it.
3046 // FIXME: Why would we need to round FP ops more than integer ones?
3047 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3048 if (NoExcessFPPrecision)
3049 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3050 DAG.getValueType(VT));
3055 // These operators require that their input be sign extended.
3056 Tmp1 = PromoteOp(Node->getOperand(0));
3057 Tmp2 = PromoteOp(Node->getOperand(1));
3058 if (MVT::isInteger(NVT)) {
3059 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3060 DAG.getValueType(VT));
3061 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3062 DAG.getValueType(VT));
3064 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3066 // Perform FP_ROUND: this is probably overly pessimistic.
3067 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3068 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3069 DAG.getValueType(VT));
3073 case ISD::FCOPYSIGN:
3074 // These operators require that their input be fp extended.
3075 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3077 Tmp1 = LegalizeOp(Node->getOperand(0));
3080 Tmp1 = PromoteOp(Node->getOperand(0));
3083 assert(0 && "not implemented");
3085 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3087 Tmp2 = LegalizeOp(Node->getOperand(1));
3090 Tmp2 = PromoteOp(Node->getOperand(1));
3093 assert(0 && "not implemented");
3095 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3097 // Perform FP_ROUND: this is probably overly pessimistic.
3098 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3099 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3100 DAG.getValueType(VT));
3105 // These operators require that their input be zero extended.
3106 Tmp1 = PromoteOp(Node->getOperand(0));
3107 Tmp2 = PromoteOp(Node->getOperand(1));
3108 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3109 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3110 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3111 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3115 Tmp1 = PromoteOp(Node->getOperand(0));
3116 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3119 // The input value must be properly sign extended.
3120 Tmp1 = PromoteOp(Node->getOperand(0));
3121 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3122 DAG.getValueType(VT));
3123 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3126 // The input value must be properly zero extended.
3127 Tmp1 = PromoteOp(Node->getOperand(0));
3128 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3129 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3133 Tmp1 = Node->getOperand(0); // Get the chain.
3134 Tmp2 = Node->getOperand(1); // Get the pointer.
3135 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3136 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3137 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3139 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3140 Node->getOperand(2));
3141 // Increment the pointer, VAList, to the next vaarg
3142 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3143 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3144 TLI.getPointerTy()));
3145 // Store the incremented VAList to the legalized pointer
3146 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2,
3147 Node->getOperand(2));
3148 // Load the actual argument out of the pointer VAList
3149 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList,
3150 DAG.getSrcValue(0), VT);
3152 // Remember that we legalized the chain.
3153 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3157 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Node->getOperand(0),
3158 Node->getOperand(1), Node->getOperand(2), VT);
3159 // Remember that we legalized the chain.
3160 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3165 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Node->getOperand(0),
3166 Node->getOperand(1), Node->getOperand(2),
3167 cast<VTSDNode>(Node->getOperand(3))->getVT());
3168 // Remember that we legalized the chain.
3169 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3172 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3173 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3174 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3176 case ISD::SELECT_CC:
3177 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3178 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3179 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3180 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3183 Tmp1 = Node->getOperand(0);
3184 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3185 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3186 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3187 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
3188 TLI.getShiftAmountTy()));
3193 // Zero extend the argument
3194 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3195 // Perform the larger operation, then subtract if needed.
3196 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3197 switch(Node->getOpcode()) {
3202 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3203 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3204 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
3205 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3206 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
3209 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3210 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3211 DAG.getConstant(getSizeInBits(NVT) -
3212 getSizeInBits(VT), NVT));
3216 case ISD::VEXTRACT_VECTOR_ELT:
3217 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
3219 case ISD::EXTRACT_VECTOR_ELT:
3220 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3224 assert(Result.Val && "Didn't set a result!");
3226 // Make sure the result is itself legal.
3227 Result = LegalizeOp(Result);
3229 // Remember that we promoted this!
3230 AddPromotedOperand(Op, Result);
3234 /// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
3235 /// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
3236 /// on the vector type. The return type of this matches the element type of the
3237 /// vector, which may not be legal for the target.
3238 SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
3239 // We know that operand #0 is the Vec vector. If the index is a constant
3240 // or if the invec is a supported hardware type, we can use it. Otherwise,
3241 // lower to a store then an indexed load.
3242 SDOperand Vec = Op.getOperand(0);
3243 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3245 SDNode *InVal = Vec.Val;
3246 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
3247 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
3249 // Figure out if there is a Packed type corresponding to this Vector
3250 // type. If so, convert to the packed type.
3251 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3252 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
3253 // Turn this into a packed extract_vector_elt operation.
3254 Vec = PackVectorOp(Vec, TVT);
3255 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
3256 } else if (NumElems == 1) {
3257 // This must be an access of the only element. Return it.
3258 return PackVectorOp(Vec, EVT);
3259 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
3261 SplitVectorOp(Vec, Lo, Hi);
3262 if (CIdx->getValue() < NumElems/2) {
3266 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3269 // It's now an extract from the appropriate high or low part. Recurse.
3270 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3271 return LowerVEXTRACT_VECTOR_ELT(Op);
3273 // Variable index case for extract element.
3274 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
3275 assert(0 && "unimp!");
3280 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3282 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3283 SDOperand Vector = Op.getOperand(0);
3284 SDOperand Idx = Op.getOperand(1);
3286 // If the target doesn't support this, store the value to a temporary
3287 // stack slot, then LOAD the scalar element back out.
3288 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
3289 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3290 Vector, StackPtr, DAG.getSrcValue(NULL));
3292 // Add the offset to the index.
3293 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3294 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3295 DAG.getConstant(EltSize, Idx.getValueType()));
3296 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3298 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, DAG.getSrcValue(NULL));
3302 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3303 /// with condition CC on the current target. This usually involves legalizing
3304 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3305 /// there may be no choice but to create a new SetCC node to represent the
3306 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3307 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3308 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3311 SDOperand Tmp1, Tmp2, Result;
3313 switch (getTypeAction(LHS.getValueType())) {
3315 Tmp1 = LegalizeOp(LHS); // LHS
3316 Tmp2 = LegalizeOp(RHS); // RHS
3319 Tmp1 = PromoteOp(LHS); // LHS
3320 Tmp2 = PromoteOp(RHS); // RHS
3322 // If this is an FP compare, the operands have already been extended.
3323 if (MVT::isInteger(LHS.getValueType())) {
3324 MVT::ValueType VT = LHS.getValueType();
3325 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3327 // Otherwise, we have to insert explicit sign or zero extends. Note
3328 // that we could insert sign extends for ALL conditions, but zero extend
3329 // is cheaper on many machines (an AND instead of two shifts), so prefer
3331 switch (cast<CondCodeSDNode>(CC)->get()) {
3332 default: assert(0 && "Unknown integer comparison!");
3339 // ALL of these operations will work if we either sign or zero extend
3340 // the operands (including the unsigned comparisons!). Zero extend is
3341 // usually a simpler/cheaper operation, so prefer it.
3342 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3343 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3349 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3350 DAG.getValueType(VT));
3351 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3352 DAG.getValueType(VT));
3358 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3359 ExpandOp(LHS, LHSLo, LHSHi);
3360 ExpandOp(RHS, RHSLo, RHSHi);
3361 switch (cast<CondCodeSDNode>(CC)->get()) {
3365 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3366 if (RHSCST->isAllOnesValue()) {
3367 // Comparison to -1.
3368 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3373 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3374 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3375 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3376 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3379 // If this is a comparison of the sign bit, just look at the top part.
3381 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3382 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3383 CST->getValue() == 0) || // X < 0
3384 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3385 CST->isAllOnesValue())) { // X > -1
3391 // FIXME: This generated code sucks.
3392 ISD::CondCode LowCC;
3393 switch (cast<CondCodeSDNode>(CC)->get()) {
3394 default: assert(0 && "Unknown integer setcc!");
3396 case ISD::SETULT: LowCC = ISD::SETULT; break;
3398 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3400 case ISD::SETULE: LowCC = ISD::SETULE; break;
3402 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3405 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3406 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3407 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3409 // NOTE: on targets without efficient SELECT of bools, we can always use
3410 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3411 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3412 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3413 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3414 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3415 Result, Tmp1, Tmp2));
3424 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3425 /// The resultant code need not be legal. Note that SrcOp is the input operand
3426 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3427 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3429 // Create the stack frame object.
3430 SDOperand FIPtr = CreateStackTemporary(DestVT);
3432 // Emit a store to the stack slot.
3433 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3434 SrcOp, FIPtr, DAG.getSrcValue(NULL));
3435 // Result is a load from the stack slot.
3436 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0));
3439 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3440 // Create a vector sized/aligned stack slot, store the value to element #0,
3441 // then load the whole vector back out.
3442 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3443 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3444 Node->getOperand(0), StackPtr,
3445 DAG.getSrcValue(NULL));
3446 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,DAG.getSrcValue(NULL));
3450 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3451 /// support the operation, but do support the resultant packed vector type.
3452 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3454 // If the only non-undef value is the low element, turn this into a
3455 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3456 unsigned NumElems = Node->getNumOperands();
3457 bool isOnlyLowElement = true;
3458 SDOperand SplatValue = Node->getOperand(0);
3459 std::map<SDOperand, std::vector<unsigned> > Values;
3460 Values[SplatValue].push_back(0);
3461 bool isConstant = true;
3462 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3463 SplatValue.getOpcode() != ISD::UNDEF)
3466 for (unsigned i = 1; i < NumElems; ++i) {
3467 SDOperand V = Node->getOperand(i);
3468 Values[V].push_back(i);
3469 if (V.getOpcode() != ISD::UNDEF)
3470 isOnlyLowElement = false;
3471 if (SplatValue != V)
3472 SplatValue = SDOperand(0,0);
3474 // If this isn't a constant element or an undef, we can't use a constant
3476 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3477 V.getOpcode() != ISD::UNDEF)
3481 if (isOnlyLowElement) {
3482 // If the low element is an undef too, then this whole things is an undef.
3483 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3484 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3485 // Otherwise, turn this into a scalar_to_vector node.
3486 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3487 Node->getOperand(0));
3490 // If all elements are constants, create a load from the constant pool.
3492 MVT::ValueType VT = Node->getValueType(0);
3494 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3495 std::vector<Constant*> CV;
3496 for (unsigned i = 0, e = NumElems; i != e; ++i) {
3497 if (ConstantFPSDNode *V =
3498 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3499 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3500 } else if (ConstantSDNode *V =
3501 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3502 CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
3504 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3505 CV.push_back(UndefValue::get(OpNTy));
3508 Constant *CP = ConstantPacked::get(CV);
3509 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3510 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
3511 DAG.getSrcValue(NULL));
3514 if (SplatValue.Val) { // Splat of one value?
3515 // Build the shuffle constant vector: <0, 0, 0, 0>
3516 MVT::ValueType MaskVT =
3517 MVT::getIntVectorWithNumElements(NumElems);
3518 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
3519 std::vector<SDOperand> ZeroVec(NumElems, Zero);
3520 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, ZeroVec);
3522 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3523 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
3524 // Get the splatted value into the low element of a vector register.
3525 SDOperand LowValVec =
3526 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3528 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3529 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3530 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3535 // If there are only two unique elements, we may be able to turn this into a
3537 if (Values.size() == 2) {
3538 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
3539 MVT::ValueType MaskVT =
3540 MVT::getIntVectorWithNumElements(NumElems);
3541 std::vector<SDOperand> MaskVec(NumElems);
3543 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3544 E = Values.end(); I != E; ++I) {
3545 for (std::vector<unsigned>::iterator II = I->second.begin(),
3546 EE = I->second.end(); II != EE; ++II)
3547 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
3550 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
3552 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3553 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
3554 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
3555 std::vector<SDOperand> Ops;
3556 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3557 E = Values.end(); I != E; ++I) {
3558 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3562 Ops.push_back(ShuffleMask);
3564 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
3565 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops);
3569 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
3570 // aligned object on the stack, store each element into it, then load
3571 // the result as a vector.
3572 MVT::ValueType VT = Node->getValueType(0);
3573 // Create the stack frame object.
3574 SDOperand FIPtr = CreateStackTemporary(VT);
3576 // Emit a store of each element to the stack slot.
3577 std::vector<SDOperand> Stores;
3578 unsigned TypeByteSize =
3579 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
3580 unsigned VectorSize = MVT::getSizeInBits(VT)/8;
3581 // Store (in the right endianness) the elements to memory.
3582 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3583 // Ignore undef elements.
3584 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3586 unsigned Offset = TypeByteSize*i;
3588 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
3589 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
3591 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3592 Node->getOperand(i), Idx,
3593 DAG.getSrcValue(NULL)));
3596 SDOperand StoreChain;
3597 if (!Stores.empty()) // Not all undef elements?
3598 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
3600 StoreChain = DAG.getEntryNode();
3602 // Result is a load from the stack slot.
3603 return DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0));
3606 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
3607 /// specified value type.
3608 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
3609 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3610 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
3611 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
3612 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
3615 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
3616 SDOperand Op, SDOperand Amt,
3617 SDOperand &Lo, SDOperand &Hi) {
3618 // Expand the subcomponents.
3619 SDOperand LHSL, LHSH;
3620 ExpandOp(Op, LHSL, LHSH);
3622 std::vector<SDOperand> Ops;
3623 Ops.push_back(LHSL);
3624 Ops.push_back(LHSH);
3626 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
3627 Lo = DAG.getNode(NodeOp, VTs, Ops);
3628 Hi = Lo.getValue(1);
3632 /// ExpandShift - Try to find a clever way to expand this shift operation out to
3633 /// smaller elements. If we can't find a way that is more efficient than a
3634 /// libcall on this target, return false. Otherwise, return true with the
3635 /// low-parts expanded into Lo and Hi.
3636 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3637 SDOperand &Lo, SDOperand &Hi) {
3638 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3639 "This is not a shift!");
3641 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3642 SDOperand ShAmt = LegalizeOp(Amt);
3643 MVT::ValueType ShTy = ShAmt.getValueType();
3644 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3645 unsigned NVTBits = MVT::getSizeInBits(NVT);
3647 // Handle the case when Amt is an immediate. Other cases are currently broken
3648 // and are disabled.
3649 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3650 unsigned Cst = CN->getValue();
3651 // Expand the incoming operand to be shifted, so that we have its parts
3653 ExpandOp(Op, InL, InH);
3657 Lo = DAG.getConstant(0, NVT);
3658 Hi = DAG.getConstant(0, NVT);
3659 } else if (Cst > NVTBits) {
3660 Lo = DAG.getConstant(0, NVT);
3661 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
3662 } else if (Cst == NVTBits) {
3663 Lo = DAG.getConstant(0, NVT);
3666 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
3667 Hi = DAG.getNode(ISD::OR, NVT,
3668 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
3669 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
3674 Lo = DAG.getConstant(0, NVT);
3675 Hi = DAG.getConstant(0, NVT);
3676 } else if (Cst > NVTBits) {
3677 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
3678 Hi = DAG.getConstant(0, NVT);
3679 } else if (Cst == NVTBits) {
3681 Hi = DAG.getConstant(0, NVT);
3683 Lo = DAG.getNode(ISD::OR, NVT,
3684 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3685 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3686 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
3691 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
3692 DAG.getConstant(NVTBits-1, ShTy));
3693 } else if (Cst > NVTBits) {
3694 Lo = DAG.getNode(ISD::SRA, NVT, InH,
3695 DAG.getConstant(Cst-NVTBits, ShTy));
3696 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3697 DAG.getConstant(NVTBits-1, ShTy));
3698 } else if (Cst == NVTBits) {
3700 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3701 DAG.getConstant(NVTBits-1, ShTy));
3703 Lo = DAG.getNode(ISD::OR, NVT,
3704 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3705 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3706 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
3715 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
3716 // does not fit into a register, return the lo part and set the hi part to the
3717 // by-reg argument. If it does fit into a single register, return the result
3718 // and leave the Hi part unset.
3719 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3721 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
3722 // The input chain to this libcall is the entry node of the function.
3723 // Legalizing the call will automatically add the previous call to the
3725 SDOperand InChain = DAG.getEntryNode();
3727 TargetLowering::ArgListTy Args;
3728 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3729 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3730 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3731 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3733 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3735 // Splice the libcall in wherever FindInputOutputChains tells us to.
3736 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3737 std::pair<SDOperand,SDOperand> CallInfo =
3738 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3741 // Legalize the call sequence, starting with the chain. This will advance
3742 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
3743 // was added by LowerCallTo (guaranteeing proper serialization of calls).
3744 LegalizeOp(CallInfo.second);
3746 switch (getTypeAction(CallInfo.first.getValueType())) {
3747 default: assert(0 && "Unknown thing");
3749 Result = CallInfo.first;
3752 ExpandOp(CallInfo.first, Result, Hi);
3759 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3760 /// destination type is legal.
3761 SDOperand SelectionDAGLegalize::
3762 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3763 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3764 assert(getTypeAction(Source.getValueType()) == Expand &&
3765 "This is not an expansion!");
3766 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3769 assert(Source.getValueType() == MVT::i64 &&
3770 "This only works for 64-bit -> FP");
3771 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3772 // incoming integer is set. To handle this, we dynamically test to see if
3773 // it is set, and, if so, add a fudge factor.
3775 ExpandOp(Source, Lo, Hi);
3777 // If this is unsigned, and not supported, first perform the conversion to
3778 // signed, then adjust the result if the sign bit is set.
3779 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3780 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3782 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3783 DAG.getConstant(0, Hi.getValueType()),
3785 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3786 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3787 SignSet, Four, Zero);
3788 uint64_t FF = 0x5f800000ULL;
3789 if (TLI.isLittleEndian()) FF <<= 32;
3790 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3792 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3793 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3794 SDOperand FudgeInReg;
3795 if (DestTy == MVT::f32)
3796 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3797 DAG.getSrcValue(NULL));
3799 assert(DestTy == MVT::f64 && "Unexpected conversion");
3800 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3801 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
3803 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3806 // Check to see if the target has a custom way to lower this. If so, use it.
3807 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3808 default: assert(0 && "This action not implemented for this operation!");
3809 case TargetLowering::Legal:
3810 case TargetLowering::Expand:
3811 break; // This case is handled below.
3812 case TargetLowering::Custom: {
3813 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3816 return LegalizeOp(NV);
3817 break; // The target decided this was legal after all
3821 // Expand the source, then glue it back together for the call. We must expand
3822 // the source in case it is shared (this pass of legalize must traverse it).
3823 SDOperand SrcLo, SrcHi;
3824 ExpandOp(Source, SrcLo, SrcHi);
3825 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
3827 const char *FnName = 0;
3828 if (DestTy == MVT::f32)
3829 FnName = "__floatdisf";
3831 assert(DestTy == MVT::f64 && "Unknown fp value type!");
3832 FnName = "__floatdidf";
3835 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
3836 SDOperand UnusedHiPart;
3837 return ExpandLibCall(FnName, Source.Val, UnusedHiPart);
3840 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
3841 /// INT_TO_FP operation of the specified operand when the target requests that
3842 /// we expand it. At this point, we know that the result and operand types are
3843 /// legal for the target.
3844 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
3846 MVT::ValueType DestVT) {
3847 if (Op0.getValueType() == MVT::i32) {
3848 // simple 32-bit [signed|unsigned] integer to float/double expansion
3850 // get the stack frame index of a 8 byte buffer
3851 MachineFunction &MF = DAG.getMachineFunction();
3852 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3853 // get address of 8 byte buffer
3854 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3855 // word offset constant for Hi/Lo address computation
3856 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
3857 // set up Hi and Lo (into buffer) address based on endian
3858 SDOperand Hi = StackSlot;
3859 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
3860 if (TLI.isLittleEndian())
3863 // if signed map to unsigned space
3864 SDOperand Op0Mapped;
3866 // constant used to invert sign bit (signed to unsigned mapping)
3867 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
3868 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
3872 // store the lo of the constructed double - based on integer input
3873 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3874 Op0Mapped, Lo, DAG.getSrcValue(NULL));
3875 // initial hi portion of constructed double
3876 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
3877 // store the hi of the constructed double - biased exponent
3878 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
3879 InitialHi, Hi, DAG.getSrcValue(NULL));
3880 // load the constructed double
3881 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
3882 DAG.getSrcValue(NULL));
3883 // FP constant to bias correct the final result
3884 SDOperand Bias = DAG.getConstantFP(isSigned ?
3885 BitsToDouble(0x4330000080000000ULL)
3886 : BitsToDouble(0x4330000000000000ULL),
3888 // subtract the bias
3889 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
3892 // handle final rounding
3893 if (DestVT == MVT::f64) {
3897 // if f32 then cast to f32
3898 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
3902 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
3903 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
3905 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
3906 DAG.getConstant(0, Op0.getValueType()),
3908 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3909 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3910 SignSet, Four, Zero);
3912 // If the sign bit of the integer is set, the large number will be treated
3913 // as a negative number. To counteract this, the dynamic code adds an
3914 // offset depending on the data type.
3916 switch (Op0.getValueType()) {
3917 default: assert(0 && "Unsupported integer type!");
3918 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
3919 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
3920 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
3921 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
3923 if (TLI.isLittleEndian()) FF <<= 32;
3924 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3926 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3927 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3928 SDOperand FudgeInReg;
3929 if (DestVT == MVT::f32)
3930 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3931 DAG.getSrcValue(NULL));
3933 assert(DestVT == MVT::f64 && "Unexpected conversion");
3934 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
3935 DAG.getEntryNode(), CPIdx,
3936 DAG.getSrcValue(NULL), MVT::f32));
3939 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
3942 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
3943 /// *INT_TO_FP operation of the specified operand when the target requests that
3944 /// we promote it. At this point, we know that the result and operand types are
3945 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
3946 /// operation that takes a larger input.
3947 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
3948 MVT::ValueType DestVT,
3950 // First step, figure out the appropriate *INT_TO_FP operation to use.
3951 MVT::ValueType NewInTy = LegalOp.getValueType();
3953 unsigned OpToUse = 0;
3955 // Scan for the appropriate larger type to use.
3957 NewInTy = (MVT::ValueType)(NewInTy+1);
3958 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
3960 // If the target supports SINT_TO_FP of this type, use it.
3961 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
3963 case TargetLowering::Legal:
3964 if (!TLI.isTypeLegal(NewInTy))
3965 break; // Can't use this datatype.
3967 case TargetLowering::Custom:
3968 OpToUse = ISD::SINT_TO_FP;
3972 if (isSigned) continue;
3974 // If the target supports UINT_TO_FP of this type, use it.
3975 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
3977 case TargetLowering::Legal:
3978 if (!TLI.isTypeLegal(NewInTy))
3979 break; // Can't use this datatype.
3981 case TargetLowering::Custom:
3982 OpToUse = ISD::UINT_TO_FP;
3987 // Otherwise, try a larger type.
3990 // Okay, we found the operation and type to use. Zero extend our input to the
3991 // desired type then run the operation on it.
3992 return DAG.getNode(OpToUse, DestVT,
3993 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
3997 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
3998 /// FP_TO_*INT operation of the specified operand when the target requests that
3999 /// we promote it. At this point, we know that the result and operand types are
4000 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4001 /// operation that returns a larger result.
4002 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4003 MVT::ValueType DestVT,
4005 // First step, figure out the appropriate FP_TO*INT operation to use.
4006 MVT::ValueType NewOutTy = DestVT;
4008 unsigned OpToUse = 0;
4010 // Scan for the appropriate larger type to use.
4012 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4013 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4015 // If the target supports FP_TO_SINT returning this type, use it.
4016 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4018 case TargetLowering::Legal:
4019 if (!TLI.isTypeLegal(NewOutTy))
4020 break; // Can't use this datatype.
4022 case TargetLowering::Custom:
4023 OpToUse = ISD::FP_TO_SINT;
4028 // If the target supports FP_TO_UINT of this type, use it.
4029 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4031 case TargetLowering::Legal:
4032 if (!TLI.isTypeLegal(NewOutTy))
4033 break; // Can't use this datatype.
4035 case TargetLowering::Custom:
4036 OpToUse = ISD::FP_TO_UINT;
4041 // Otherwise, try a larger type.
4044 // Okay, we found the operation and type to use. Truncate the result of the
4045 // extended FP_TO_*INT operation to the desired size.
4046 return DAG.getNode(ISD::TRUNCATE, DestVT,
4047 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4050 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4052 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4053 MVT::ValueType VT = Op.getValueType();
4054 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4055 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4057 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4059 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4060 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4061 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4063 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4064 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4065 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4066 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4067 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4068 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4069 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4070 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4071 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4073 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4074 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4075 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4076 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4077 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4078 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4079 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4080 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4081 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4082 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4083 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4084 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4085 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4086 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4087 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4088 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4089 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4090 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4091 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4092 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4093 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4097 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4099 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4101 default: assert(0 && "Cannot expand this yet!");
4103 static const uint64_t mask[6] = {
4104 0x5555555555555555ULL, 0x3333333333333333ULL,
4105 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4106 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4108 MVT::ValueType VT = Op.getValueType();
4109 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4110 unsigned len = getSizeInBits(VT);
4111 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4112 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4113 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4114 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4115 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4116 DAG.getNode(ISD::AND, VT,
4117 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4122 // for now, we do this:
4123 // x = x | (x >> 1);
4124 // x = x | (x >> 2);
4126 // x = x | (x >>16);
4127 // x = x | (x >>32); // for 64-bit input
4128 // return popcount(~x);
4130 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4131 MVT::ValueType VT = Op.getValueType();
4132 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4133 unsigned len = getSizeInBits(VT);
4134 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4135 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4136 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4138 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4139 return DAG.getNode(ISD::CTPOP, VT, Op);
4142 // for now, we use: { return popcount(~x & (x - 1)); }
4143 // unless the target has ctlz but not ctpop, in which case we use:
4144 // { return 32 - nlz(~x & (x-1)); }
4145 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4146 MVT::ValueType VT = Op.getValueType();
4147 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4148 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4149 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4150 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4151 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4152 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4153 TLI.isOperationLegal(ISD::CTLZ, VT))
4154 return DAG.getNode(ISD::SUB, VT,
4155 DAG.getConstant(getSizeInBits(VT), VT),
4156 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4157 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4162 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4163 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4164 /// LegalizeNodes map is filled in for any results that are not expanded, the
4165 /// ExpandedNodes map is filled in for any results that are expanded, and the
4166 /// Lo/Hi values are returned.
4167 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4168 MVT::ValueType VT = Op.getValueType();
4169 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4170 SDNode *Node = Op.Val;
4171 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4172 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
4173 "Cannot expand FP values!");
4174 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
4175 "Cannot expand to FP value or to larger int value!");
4177 // See if we already expanded it.
4178 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4179 = ExpandedNodes.find(Op);
4180 if (I != ExpandedNodes.end()) {
4181 Lo = I->second.first;
4182 Hi = I->second.second;
4186 switch (Node->getOpcode()) {
4187 case ISD::CopyFromReg:
4188 assert(0 && "CopyFromReg must be legal!");
4190 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
4191 assert(0 && "Do not know how to expand this operator!");
4194 Lo = DAG.getNode(ISD::UNDEF, NVT);
4195 Hi = DAG.getNode(ISD::UNDEF, NVT);
4197 case ISD::Constant: {
4198 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4199 Lo = DAG.getConstant(Cst, NVT);
4200 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4203 case ISD::BUILD_PAIR:
4204 // Return the operands.
4205 Lo = Node->getOperand(0);
4206 Hi = Node->getOperand(1);
4209 case ISD::SIGN_EXTEND_INREG:
4210 ExpandOp(Node->getOperand(0), Lo, Hi);
4211 // Sign extend the lo-part.
4212 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4213 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4214 TLI.getShiftAmountTy()));
4215 // sext_inreg the low part if needed.
4216 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4220 ExpandOp(Node->getOperand(0), Lo, Hi);
4221 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4222 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4228 ExpandOp(Node->getOperand(0), Lo, Hi);
4229 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4230 DAG.getNode(ISD::CTPOP, NVT, Lo),
4231 DAG.getNode(ISD::CTPOP, NVT, Hi));
4232 Hi = DAG.getConstant(0, NVT);
4236 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4237 ExpandOp(Node->getOperand(0), Lo, Hi);
4238 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4239 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4240 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4242 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4243 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4245 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4246 Hi = DAG.getConstant(0, NVT);
4251 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4252 ExpandOp(Node->getOperand(0), Lo, Hi);
4253 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4254 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4255 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4257 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4258 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4260 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4261 Hi = DAG.getConstant(0, NVT);
4266 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4267 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4268 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4269 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4271 // Remember that we legalized the chain.
4272 Hi = LegalizeOp(Hi);
4273 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4274 if (!TLI.isLittleEndian())
4280 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4281 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4282 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
4284 // Increment the pointer to the other half.
4285 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4286 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4287 getIntPtrConstant(IncrementSize));
4288 // FIXME: This creates a bogus srcvalue!
4289 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
4291 // Build a factor node to remember that this load is independent of the
4293 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4296 // Remember that we legalized the chain.
4297 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4298 if (!TLI.isLittleEndian())
4304 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
4305 SDOperand LL, LH, RL, RH;
4306 ExpandOp(Node->getOperand(0), LL, LH);
4307 ExpandOp(Node->getOperand(1), RL, RH);
4308 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4309 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4313 SDOperand LL, LH, RL, RH;
4314 ExpandOp(Node->getOperand(1), LL, LH);
4315 ExpandOp(Node->getOperand(2), RL, RH);
4316 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4317 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4320 case ISD::SELECT_CC: {
4321 SDOperand TL, TH, FL, FH;
4322 ExpandOp(Node->getOperand(2), TL, TH);
4323 ExpandOp(Node->getOperand(3), FL, FH);
4324 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4325 Node->getOperand(1), TL, FL, Node->getOperand(4));
4326 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4327 Node->getOperand(1), TH, FH, Node->getOperand(4));
4330 case ISD::SEXTLOAD: {
4331 SDOperand Chain = Node->getOperand(0);
4332 SDOperand Ptr = Node->getOperand(1);
4333 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4336 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4338 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4341 // Remember that we legalized the chain.
4342 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4344 // The high part is obtained by SRA'ing all but one of the bits of the lo
4346 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4347 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
4348 TLI.getShiftAmountTy()));
4351 case ISD::ZEXTLOAD: {
4352 SDOperand Chain = Node->getOperand(0);
4353 SDOperand Ptr = Node->getOperand(1);
4354 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4357 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4359 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4362 // Remember that we legalized the chain.
4363 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4365 // The high part is just a zero.
4366 Hi = DAG.getConstant(0, NVT);
4369 case ISD::EXTLOAD: {
4370 SDOperand Chain = Node->getOperand(0);
4371 SDOperand Ptr = Node->getOperand(1);
4372 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4375 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4377 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4380 // Remember that we legalized the chain.
4381 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4383 // The high part is undefined.
4384 Hi = DAG.getNode(ISD::UNDEF, NVT);
4387 case ISD::ANY_EXTEND:
4388 // The low part is any extension of the input (which degenerates to a copy).
4389 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4390 // The high part is undefined.
4391 Hi = DAG.getNode(ISD::UNDEF, NVT);
4393 case ISD::SIGN_EXTEND: {
4394 // The low part is just a sign extension of the input (which degenerates to
4396 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4398 // The high part is obtained by SRA'ing all but one of the bits of the lo
4400 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4401 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4402 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4405 case ISD::ZERO_EXTEND:
4406 // The low part is just a zero extension of the input (which degenerates to
4408 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4410 // The high part is just a zero.
4411 Hi = DAG.getConstant(0, NVT);
4414 case ISD::BIT_CONVERT: {
4415 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0),
4416 Node->getOperand(0));
4417 ExpandOp(Tmp, Lo, Hi);
4421 case ISD::READCYCLECOUNTER:
4422 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
4423 TargetLowering::Custom &&
4424 "Must custom expand ReadCycleCounter");
4425 Lo = TLI.LowerOperation(Op, DAG);
4426 assert(Lo.Val && "Node must be custom expanded!");
4427 Hi = Lo.getValue(1);
4428 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
4429 LegalizeOp(Lo.getValue(2)));
4432 // These operators cannot be expanded directly, emit them as calls to
4433 // library functions.
4434 case ISD::FP_TO_SINT:
4435 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
4437 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4438 case Expand: assert(0 && "cannot expand FP!");
4439 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4440 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4443 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
4445 // Now that the custom expander is done, expand the result, which is still
4448 ExpandOp(Op, Lo, Hi);
4453 if (Node->getOperand(0).getValueType() == MVT::f32)
4454 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
4456 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
4459 case ISD::FP_TO_UINT:
4460 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
4462 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4463 case Expand: assert(0 && "cannot expand FP!");
4464 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4465 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4468 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
4470 // Now that the custom expander is done, expand the result.
4472 ExpandOp(Op, Lo, Hi);
4477 if (Node->getOperand(0).getValueType() == MVT::f32)
4478 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
4480 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
4484 // If the target wants custom lowering, do so.
4485 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4486 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
4487 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
4488 Op = TLI.LowerOperation(Op, DAG);
4490 // Now that the custom expander is done, expand the result, which is
4492 ExpandOp(Op, Lo, Hi);
4497 // If we can emit an efficient shift operation, do so now.
4498 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4501 // If this target supports SHL_PARTS, use it.
4502 TargetLowering::LegalizeAction Action =
4503 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
4504 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4505 Action == TargetLowering::Custom) {
4506 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4510 // Otherwise, emit a libcall.
4511 Lo = ExpandLibCall("__ashldi3", Node, Hi);
4516 // If the target wants custom lowering, do so.
4517 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4518 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
4519 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
4520 Op = TLI.LowerOperation(Op, DAG);
4522 // Now that the custom expander is done, expand the result, which is
4524 ExpandOp(Op, Lo, Hi);
4529 // If we can emit an efficient shift operation, do so now.
4530 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
4533 // If this target supports SRA_PARTS, use it.
4534 TargetLowering::LegalizeAction Action =
4535 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
4536 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4537 Action == TargetLowering::Custom) {
4538 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4542 // Otherwise, emit a libcall.
4543 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
4548 // If the target wants custom lowering, do so.
4549 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4550 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
4551 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
4552 Op = TLI.LowerOperation(Op, DAG);
4554 // Now that the custom expander is done, expand the result, which is
4556 ExpandOp(Op, Lo, Hi);
4561 // If we can emit an efficient shift operation, do so now.
4562 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4565 // If this target supports SRL_PARTS, use it.
4566 TargetLowering::LegalizeAction Action =
4567 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
4568 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4569 Action == TargetLowering::Custom) {
4570 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4574 // Otherwise, emit a libcall.
4575 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
4581 // If the target wants to custom expand this, let them.
4582 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
4583 TargetLowering::Custom) {
4584 Op = TLI.LowerOperation(Op, DAG);
4586 ExpandOp(Op, Lo, Hi);
4591 // Expand the subcomponents.
4592 SDOperand LHSL, LHSH, RHSL, RHSH;
4593 ExpandOp(Node->getOperand(0), LHSL, LHSH);
4594 ExpandOp(Node->getOperand(1), RHSL, RHSH);
4595 std::vector<MVT::ValueType> VTs;
4596 std::vector<SDOperand> LoOps, HiOps;
4597 VTs.push_back(LHSL.getValueType());
4598 VTs.push_back(MVT::Flag);
4599 LoOps.push_back(LHSL);
4600 LoOps.push_back(RHSL);
4601 HiOps.push_back(LHSH);
4602 HiOps.push_back(RHSH);
4603 if (Node->getOpcode() == ISD::ADD) {
4604 Lo = DAG.getNode(ISD::ADDC, VTs, LoOps);
4605 HiOps.push_back(Lo.getValue(1));
4606 Hi = DAG.getNode(ISD::ADDE, VTs, HiOps);
4608 Lo = DAG.getNode(ISD::SUBC, VTs, LoOps);
4609 HiOps.push_back(Lo.getValue(1));
4610 Hi = DAG.getNode(ISD::SUBE, VTs, HiOps);
4615 if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
4616 SDOperand LL, LH, RL, RH;
4617 ExpandOp(Node->getOperand(0), LL, LH);
4618 ExpandOp(Node->getOperand(1), RL, RH);
4619 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
4620 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
4621 // extended the sign bit of the low half through the upper half, and if so
4622 // emit a MULHS instead of the alternate sequence that is valid for any
4623 // i64 x i64 multiply.
4624 if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
4625 // is RH an extension of the sign bit of RL?
4626 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
4627 RH.getOperand(1).getOpcode() == ISD::Constant &&
4628 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
4629 // is LH an extension of the sign bit of LL?
4630 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
4631 LH.getOperand(1).getOpcode() == ISD::Constant &&
4632 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
4633 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
4635 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
4636 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
4637 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
4638 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
4639 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
4641 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4643 Lo = ExpandLibCall("__muldi3" , Node, Hi);
4647 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
4648 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
4649 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
4650 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
4653 // Make sure the resultant values have been legalized themselves, unless this
4654 // is a type that requires multi-step expansion.
4655 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
4656 Lo = LegalizeOp(Lo);
4657 Hi = LegalizeOp(Hi);
4660 // Remember in a map if the values will be reused later.
4662 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4663 assert(isNew && "Value already expanded?!?");
4666 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
4667 /// two smaller values of MVT::Vector type.
4668 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
4670 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
4671 SDNode *Node = Op.Val;
4672 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
4673 assert(NumElements > 1 && "Cannot split a single element vector!");
4674 unsigned NewNumElts = NumElements/2;
4675 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
4676 SDOperand TypeNode = *(Node->op_end()-1);
4678 // See if we already split it.
4679 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4680 = SplitNodes.find(Op);
4681 if (I != SplitNodes.end()) {
4682 Lo = I->second.first;
4683 Hi = I->second.second;
4687 switch (Node->getOpcode()) {
4688 default: Node->dump(); assert(0 && "Unhandled operation in SplitVectorOp!");
4689 case ISD::VBUILD_VECTOR: {
4690 std::vector<SDOperand> LoOps(Node->op_begin(), Node->op_begin()+NewNumElts);
4691 LoOps.push_back(NewNumEltsNode);
4692 LoOps.push_back(TypeNode);
4693 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, LoOps);
4695 std::vector<SDOperand> HiOps(Node->op_begin()+NewNumElts, Node->op_end()-2);
4696 HiOps.push_back(NewNumEltsNode);
4697 HiOps.push_back(TypeNode);
4698 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, HiOps);
4709 SDOperand LL, LH, RL, RH;
4710 SplitVectorOp(Node->getOperand(0), LL, LH);
4711 SplitVectorOp(Node->getOperand(1), RL, RH);
4713 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
4714 NewNumEltsNode, TypeNode);
4715 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
4716 NewNumEltsNode, TypeNode);
4720 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4721 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4722 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4724 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4725 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
4726 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4727 getIntPtrConstant(IncrementSize));
4728 // FIXME: This creates a bogus srcvalue!
4729 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4731 // Build a factor node to remember that this load is independent of the
4733 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4736 // Remember that we legalized the chain.
4737 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4740 case ISD::VBIT_CONVERT: {
4741 // We know the result is a vector. The input may be either a vector or a
4743 if (Op.getOperand(0).getValueType() != MVT::Vector) {
4744 // Lower to a store/load. FIXME: this could be improved probably.
4745 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
4747 SDOperand St = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
4748 Op.getOperand(0), Ptr, DAG.getSrcValue(0));
4749 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4750 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0));
4751 SplitVectorOp(St, Lo, Hi);
4753 // If the input is a vector type, we have to either scalarize it, pack it
4754 // or convert it based on whether the input vector type is legal.
4755 SDNode *InVal = Node->getOperand(0).Val;
4757 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
4758 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
4760 // If the input is from a single element vector, scalarize the vector,
4761 // then treat like a scalar.
4762 if (NumElems == 1) {
4763 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT);
4764 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar,
4765 Op.getOperand(1), Op.getOperand(2));
4766 SplitVectorOp(Scalar, Lo, Hi);
4768 // Split the input vector.
4769 SplitVectorOp(Op.getOperand(0), Lo, Hi);
4771 // Convert each of the pieces now.
4772 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo,
4773 NewNumEltsNode, TypeNode);
4774 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi,
4775 NewNumEltsNode, TypeNode);
4782 // Remember in a map if the values will be reused later.
4784 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4785 assert(isNew && "Value already expanded?!?");
4789 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
4790 /// equivalent operation that returns a scalar (e.g. F32) or packed value
4791 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
4792 /// type for the result.
4793 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
4794 MVT::ValueType NewVT) {
4795 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
4796 SDNode *Node = Op.Val;
4798 // See if we already packed it.
4799 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
4800 if (I != PackedNodes.end()) return I->second;
4803 switch (Node->getOpcode()) {
4805 Node->dump(); std::cerr << "\n";
4806 assert(0 && "Unknown vector operation in PackVectorOp!");
4815 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
4817 PackVectorOp(Node->getOperand(0), NewVT),
4818 PackVectorOp(Node->getOperand(1), NewVT));
4821 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
4822 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
4824 Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(2));
4826 // Remember that we legalized the chain.
4827 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4830 case ISD::VBUILD_VECTOR:
4831 if (Node->getOperand(0).getValueType() == NewVT) {
4832 // Returning a scalar?
4833 Result = Node->getOperand(0);
4835 // Returning a BUILD_VECTOR?
4837 // If all elements of the build_vector are undefs, return an undef.
4838 bool AllUndef = true;
4839 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i)
4840 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) {
4845 Result = DAG.getNode(ISD::UNDEF, NewVT);
4847 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()-2);
4848 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops);
4852 case ISD::VINSERT_VECTOR_ELT:
4853 if (!MVT::isVector(NewVT)) {
4854 // Returning a scalar? Must be the inserted element.
4855 Result = Node->getOperand(1);
4857 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
4858 PackVectorOp(Node->getOperand(0), NewVT),
4859 Node->getOperand(1), Node->getOperand(2));
4862 case ISD::VVECTOR_SHUFFLE:
4863 if (!MVT::isVector(NewVT)) {
4864 // Returning a scalar? Figure out if it is the LHS or RHS and return it.
4865 SDOperand EltNum = Node->getOperand(2).getOperand(0);
4866 if (cast<ConstantSDNode>(EltNum)->getValue())
4867 Result = PackVectorOp(Node->getOperand(1), NewVT);
4869 Result = PackVectorOp(Node->getOperand(0), NewVT);
4871 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index
4872 // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
4873 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
4874 Node->getOperand(2).Val->op_end()-2);
4875 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
4876 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT, BuildVecIdx);
4878 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
4879 PackVectorOp(Node->getOperand(0), NewVT),
4880 PackVectorOp(Node->getOperand(1), NewVT), BV);
4883 case ISD::VBIT_CONVERT:
4884 if (Op.getOperand(0).getValueType() != MVT::Vector)
4885 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
4887 // If the input is a vector type, we have to either scalarize it, pack it
4888 // or convert it based on whether the input vector type is legal.
4889 SDNode *InVal = Node->getOperand(0).Val;
4891 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
4892 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
4894 // Figure out if there is a Packed type corresponding to this Vector
4895 // type. If so, convert to the packed type.
4896 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
4897 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
4898 // Turn this into a bit convert of the packed input.
4899 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
4900 PackVectorOp(Node->getOperand(0), TVT));
4902 } else if (NumElems == 1) {
4903 // Turn this into a bit convert of the scalar input.
4904 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
4905 PackVectorOp(Node->getOperand(0), EVT));
4909 assert(0 && "Cast from unsupported vector type not implemented yet!");
4914 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
4915 PackVectorOp(Op.getOperand(1), NewVT),
4916 PackVectorOp(Op.getOperand(2), NewVT));
4920 if (TLI.isTypeLegal(NewVT))
4921 Result = LegalizeOp(Result);
4922 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
4923 assert(isNew && "Value already packed?");
4928 // SelectionDAG::Legalize - This is the entry point for the file.
4930 void SelectionDAG::Legalize() {
4931 if (ViewLegalizeDAGs) viewGraph();
4933 /// run - This is the main entry point to this class.
4935 SelectionDAGLegalize(*this).LegalizeDAG();