1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/DwarfWriter.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetSubtarget.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/DerivedTypes.h"
31 #include "llvm/Function.h"
32 #include "llvm/GlobalVariable.h"
33 #include "llvm/LLVMContext.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/ADT/DenseMap.h"
40 #include "llvm/ADT/SmallVector.h"
41 #include "llvm/ADT/SmallPtrSet.h"
45 //===----------------------------------------------------------------------===//
46 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
47 /// hacks on it until the target machine can handle it. This involves
48 /// eliminating value sizes the machine cannot handle (promoting small sizes to
49 /// large sizes or splitting up large values into small values) as well as
50 /// eliminating operations the machine cannot handle.
52 /// This code also does a small amount of optimization and recognition of idioms
53 /// as part of its processing. For example, if a target does not support a
54 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
55 /// will attempt merge setcc and brc instructions into brcc's.
58 class SelectionDAGLegalize {
61 CodeGenOpt::Level OptLevel;
63 // Libcall insertion helpers.
65 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
66 /// legalized. We use this to ensure that calls are properly serialized
67 /// against each other, including inserted libcalls.
68 SDValue LastCALLSEQ_END;
70 /// IsLegalizingCall - This member is used *only* for purposes of providing
71 /// helpful assertions that a libcall isn't created while another call is
72 /// being legalized (which could lead to non-serialized call sequences).
73 bool IsLegalizingCall;
76 Legal, // The target natively supports this operation.
77 Promote, // This operation should be executed in a larger type.
78 Expand // Try to expand this to other ops, otherwise use a libcall.
81 /// ValueTypeActions - This is a bitvector that contains two bits for each
82 /// value type, where the two bits correspond to the LegalizeAction enum.
83 /// This can be queried with "getTypeAction(VT)".
84 TargetLowering::ValueTypeActionImpl ValueTypeActions;
86 /// LegalizedNodes - For nodes that are of legal width, and that have more
87 /// than one use, this map indicates what regularized operand to use. This
88 /// allows us to avoid legalizing the same thing more than once.
89 DenseMap<SDValue, SDValue> LegalizedNodes;
91 void AddLegalizedOperand(SDValue From, SDValue To) {
92 LegalizedNodes.insert(std::make_pair(From, To));
93 // If someone requests legalization of the new node, return itself.
95 LegalizedNodes.insert(std::make_pair(To, To));
99 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol);
101 /// getTypeAction - Return how we should legalize values of this type, either
102 /// it is already legal or we need to expand it into multiple registers of
103 /// smaller integer type, or we need to promote it to a larger type.
104 LegalizeAction getTypeAction(EVT VT) const {
106 (LegalizeAction)ValueTypeActions.getTypeAction(*DAG.getContext(), VT);
109 /// isTypeLegal - Return true if this type is legal on this target.
111 bool isTypeLegal(EVT VT) const {
112 return getTypeAction(VT) == Legal;
118 /// LegalizeOp - We know that the specified value has a legal type.
119 /// Recursively ensure that the operands have legal types, then return the
121 SDValue LegalizeOp(SDValue O);
123 SDValue OptimizeFloatStore(StoreSDNode *ST);
125 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
126 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
127 /// is necessary to spill the vector being inserted into to memory, perform
128 /// the insert there, and then read the result back.
129 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
130 SDValue Idx, DebugLoc dl);
131 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
132 SDValue Idx, DebugLoc dl);
134 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
135 /// performs the same shuffe in terms of order or result bytes, but on a type
136 /// whose vector element type is narrower than the original shuffle type.
137 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
138 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
139 SDValue N1, SDValue N2,
140 SmallVectorImpl<int> &Mask) const;
142 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
143 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
145 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
148 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
149 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
150 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
151 RTLIB::Libcall Call_PPCF128);
152 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
153 RTLIB::Libcall Call_I8,
154 RTLIB::Libcall Call_I16,
155 RTLIB::Libcall Call_I32,
156 RTLIB::Libcall Call_I64,
157 RTLIB::Libcall Call_I128);
159 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
160 SDValue ExpandBUILD_VECTOR(SDNode *Node);
161 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
162 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
163 SmallVectorImpl<SDValue> &Results);
164 SDValue ExpandFCOPYSIGN(SDNode *Node);
165 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
167 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
169 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
172 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
173 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
175 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
176 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
178 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
179 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
183 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
184 /// performs the same shuffe in terms of order or result bytes, but on a type
185 /// whose vector element type is narrower than the original shuffle type.
186 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
188 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
189 SDValue N1, SDValue N2,
190 SmallVectorImpl<int> &Mask) const {
191 unsigned NumMaskElts = VT.getVectorNumElements();
192 unsigned NumDestElts = NVT.getVectorNumElements();
193 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
195 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
197 if (NumEltsGrowth == 1)
198 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
200 SmallVector<int, 8> NewMask;
201 for (unsigned i = 0; i != NumMaskElts; ++i) {
203 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
205 NewMask.push_back(-1);
207 NewMask.push_back(Idx * NumEltsGrowth + j);
210 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
211 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
212 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
215 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
216 CodeGenOpt::Level ol)
217 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
218 ValueTypeActions(TLI.getValueTypeActions()) {
219 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
220 "Too many value types for ValueTypeActions to hold!");
223 void SelectionDAGLegalize::LegalizeDAG() {
224 LastCALLSEQ_END = DAG.getEntryNode();
225 IsLegalizingCall = false;
227 // The legalize process is inherently a bottom-up recursive process (users
228 // legalize their uses before themselves). Given infinite stack space, we
229 // could just start legalizing on the root and traverse the whole graph. In
230 // practice however, this causes us to run out of stack space on large basic
231 // blocks. To avoid this problem, compute an ordering of the nodes where each
232 // node is only legalized after all of its operands are legalized.
233 DAG.AssignTopologicalOrder();
234 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
235 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
236 LegalizeOp(SDValue(I, 0));
238 // Finally, it's possible the root changed. Get the new root.
239 SDValue OldRoot = DAG.getRoot();
240 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
241 DAG.setRoot(LegalizedNodes[OldRoot]);
243 LegalizedNodes.clear();
245 // Remove dead nodes now.
246 DAG.RemoveDeadNodes();
250 /// FindCallEndFromCallStart - Given a chained node that is part of a call
251 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
252 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
253 if (Node->getOpcode() == ISD::CALLSEQ_END)
255 if (Node->use_empty())
256 return 0; // No CallSeqEnd
258 // The chain is usually at the end.
259 SDValue TheChain(Node, Node->getNumValues()-1);
260 if (TheChain.getValueType() != MVT::Other) {
261 // Sometimes it's at the beginning.
262 TheChain = SDValue(Node, 0);
263 if (TheChain.getValueType() != MVT::Other) {
264 // Otherwise, hunt for it.
265 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
266 if (Node->getValueType(i) == MVT::Other) {
267 TheChain = SDValue(Node, i);
271 // Otherwise, we walked into a node without a chain.
272 if (TheChain.getValueType() != MVT::Other)
277 for (SDNode::use_iterator UI = Node->use_begin(),
278 E = Node->use_end(); UI != E; ++UI) {
280 // Make sure to only follow users of our token chain.
282 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
283 if (User->getOperand(i) == TheChain)
284 if (SDNode *Result = FindCallEndFromCallStart(User))
290 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
291 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
292 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
293 assert(Node && "Didn't find callseq_start for a call??");
294 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
296 assert(Node->getOperand(0).getValueType() == MVT::Other &&
297 "Node doesn't have a token chain argument!");
298 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
301 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
302 /// see if any uses can reach Dest. If no dest operands can get to dest,
303 /// legalize them, legalize ourself, and return false, otherwise, return true.
305 /// Keep track of the nodes we fine that actually do lead to Dest in
306 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
308 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
309 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
310 if (N == Dest) return true; // N certainly leads to Dest :)
312 // If we've already processed this node and it does lead to Dest, there is no
313 // need to reprocess it.
314 if (NodesLeadingTo.count(N)) return true;
316 // If the first result of this node has been already legalized, then it cannot
318 if (LegalizedNodes.count(SDValue(N, 0))) return false;
320 // Okay, this node has not already been legalized. Check and legalize all
321 // operands. If none lead to Dest, then we can legalize this node.
322 bool OperandsLeadToDest = false;
323 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
324 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
325 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
327 if (OperandsLeadToDest) {
328 NodesLeadingTo.insert(N);
332 // Okay, this node looks safe, legalize it and return false.
333 LegalizeOp(SDValue(N, 0));
337 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
338 /// a load from the constant pool.
339 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
340 SelectionDAG &DAG, const TargetLowering &TLI) {
342 DebugLoc dl = CFP->getDebugLoc();
344 // If a FP immediate is precise when represented as a float and if the
345 // target can do an extending load from float to double, we put it into
346 // the constant pool as a float, even if it's is statically typed as a
347 // double. This shrinks FP constants and canonicalizes them for targets where
348 // an FP extending load is the same cost as a normal load (such as on the x87
349 // fp stack or PPC FP unit).
350 EVT VT = CFP->getValueType(0);
351 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
353 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
354 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
355 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
360 while (SVT != MVT::f32) {
361 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
362 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
363 // Only do this if the target has a native EXTLOAD instruction from
365 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
366 TLI.ShouldShrinkFPConstant(OrigVT)) {
367 const Type *SType = SVT.getTypeForEVT(*DAG.getContext());
368 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
374 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
375 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
377 return DAG.getExtLoad(ISD::EXTLOAD, dl,
378 OrigVT, DAG.getEntryNode(),
379 CPIdx, PseudoSourceValue::getConstantPool(),
380 0, VT, false, false, Alignment);
381 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
382 PseudoSourceValue::getConstantPool(), 0, false, false,
386 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
388 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
389 const TargetLowering &TLI) {
390 SDValue Chain = ST->getChain();
391 SDValue Ptr = ST->getBasePtr();
392 SDValue Val = ST->getValue();
393 EVT VT = Val.getValueType();
394 int Alignment = ST->getAlignment();
395 int SVOffset = ST->getSrcValueOffset();
396 DebugLoc dl = ST->getDebugLoc();
397 if (ST->getMemoryVT().isFloatingPoint() ||
398 ST->getMemoryVT().isVector()) {
399 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
400 if (TLI.isTypeLegal(intVT)) {
401 // Expand to a bitconvert of the value to the integer type of the
402 // same size, then a (misaligned) int store.
403 // FIXME: Does not handle truncating floating point stores!
404 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
405 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
406 SVOffset, ST->isVolatile(), ST->isNonTemporal(),
409 // Do a (aligned) store to a stack slot, then copy from the stack slot
410 // to the final destination using (unaligned) integer loads and stores.
411 EVT StoredVT = ST->getMemoryVT();
413 TLI.getRegisterType(*DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(), StoredVT.getSizeInBits()));
414 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
415 unsigned RegBytes = RegVT.getSizeInBits() / 8;
416 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
418 // Make sure the stack slot is also aligned for the register type.
419 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
421 // Perform the original store, only redirected to the stack slot.
422 SDValue Store = DAG.getTruncStore(Chain, dl,
423 Val, StackPtr, NULL, 0, StoredVT,
425 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
426 SmallVector<SDValue, 8> Stores;
429 // Do all but one copies using the full register width.
430 for (unsigned i = 1; i < NumRegs; i++) {
431 // Load one integer register's worth from the stack slot.
432 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0,
434 // Store it to the final location. Remember the store.
435 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
436 ST->getSrcValue(), SVOffset + Offset,
437 ST->isVolatile(), ST->isNonTemporal(),
438 MinAlign(ST->getAlignment(), Offset)));
439 // Increment the pointers.
441 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
443 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
446 // The last store may be partial. Do a truncating store. On big-endian
447 // machines this requires an extending load from the stack slot to ensure
448 // that the bits are in the right place.
449 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (StoredBytes - Offset));
451 // Load from the stack slot.
452 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
453 NULL, 0, MemVT, false, false, 0);
455 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
456 ST->getSrcValue(), SVOffset + Offset,
457 MemVT, ST->isVolatile(),
459 MinAlign(ST->getAlignment(), Offset)));
460 // The order of the stores doesn't matter - say it with a TokenFactor.
461 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
465 assert(ST->getMemoryVT().isInteger() &&
466 !ST->getMemoryVT().isVector() &&
467 "Unaligned store of unknown type.");
468 // Get the half-size VT
469 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
470 int NumBits = NewStoredVT.getSizeInBits();
471 int IncrementSize = NumBits / 8;
473 // Divide the stored value in two parts.
474 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
476 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
478 // Store the two parts
479 SDValue Store1, Store2;
480 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
481 ST->getSrcValue(), SVOffset, NewStoredVT,
482 ST->isVolatile(), ST->isNonTemporal(), Alignment);
483 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
484 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
485 Alignment = MinAlign(Alignment, IncrementSize);
486 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
487 ST->getSrcValue(), SVOffset + IncrementSize,
488 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
491 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
494 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
496 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
497 const TargetLowering &TLI) {
498 int SVOffset = LD->getSrcValueOffset();
499 SDValue Chain = LD->getChain();
500 SDValue Ptr = LD->getBasePtr();
501 EVT VT = LD->getValueType(0);
502 EVT LoadedVT = LD->getMemoryVT();
503 DebugLoc dl = LD->getDebugLoc();
504 if (VT.isFloatingPoint() || VT.isVector()) {
505 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
506 if (TLI.isTypeLegal(intVT)) {
507 // Expand to a (misaligned) integer load of the same size,
508 // then bitconvert to floating point or vector.
509 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
510 SVOffset, LD->isVolatile(),
511 LD->isNonTemporal(), LD->getAlignment());
512 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
513 if (VT.isFloatingPoint() && LoadedVT != VT)
514 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
516 SDValue Ops[] = { Result, Chain };
517 return DAG.getMergeValues(Ops, 2, dl);
519 // Copy the value to a (aligned) stack slot using (unaligned) integer
520 // loads and stores, then do a (aligned) load from the stack slot.
521 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
522 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
523 unsigned RegBytes = RegVT.getSizeInBits() / 8;
524 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
526 // Make sure the stack slot is also aligned for the register type.
527 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
529 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
530 SmallVector<SDValue, 8> Stores;
531 SDValue StackPtr = StackBase;
534 // Do all but one copies using the full register width.
535 for (unsigned i = 1; i < NumRegs; i++) {
536 // Load one integer register's worth from the original location.
537 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
538 SVOffset + Offset, LD->isVolatile(),
540 MinAlign(LD->getAlignment(), Offset));
541 // Follow the load with a store to the stack slot. Remember the store.
542 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
543 NULL, 0, false, false, 0));
544 // Increment the pointers.
546 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
547 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
551 // The last copy may be partial. Do an extending load.
552 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (LoadedBytes - Offset));
553 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
554 LD->getSrcValue(), SVOffset + Offset,
555 MemVT, LD->isVolatile(),
557 MinAlign(LD->getAlignment(), Offset));
558 // Follow the load with a store to the stack slot. Remember the store.
559 // On big-endian machines this requires a truncating store to ensure
560 // that the bits end up in the right place.
561 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
562 NULL, 0, MemVT, false, false, 0));
564 // The order of the stores doesn't matter - say it with a TokenFactor.
565 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
568 // Finally, perform the original load only redirected to the stack slot.
569 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
570 NULL, 0, LoadedVT, false, false, 0);
572 // Callers expect a MERGE_VALUES node.
573 SDValue Ops[] = { Load, TF };
574 return DAG.getMergeValues(Ops, 2, dl);
577 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
578 "Unaligned load of unsupported type.");
580 // Compute the new VT that is half the size of the old one. This is an
582 unsigned NumBits = LoadedVT.getSizeInBits();
584 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
587 unsigned Alignment = LD->getAlignment();
588 unsigned IncrementSize = NumBits / 8;
589 ISD::LoadExtType HiExtType = LD->getExtensionType();
591 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
592 if (HiExtType == ISD::NON_EXTLOAD)
593 HiExtType = ISD::ZEXTLOAD;
595 // Load the value in two parts
597 if (TLI.isLittleEndian()) {
598 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
599 SVOffset, NewLoadedVT, LD->isVolatile(),
600 LD->isNonTemporal(), Alignment);
601 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
602 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
603 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
604 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
605 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize));
607 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
608 SVOffset, NewLoadedVT, LD->isVolatile(),
609 LD->isNonTemporal(), Alignment);
610 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
611 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
612 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
613 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
614 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize));
617 // aggregate the two parts
618 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
619 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
620 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
622 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
625 SDValue Ops[] = { Result, TF };
626 return DAG.getMergeValues(Ops, 2, dl);
629 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
630 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
631 /// is necessary to spill the vector being inserted into to memory, perform
632 /// the insert there, and then read the result back.
633 SDValue SelectionDAGLegalize::
634 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
640 // If the target doesn't support this, we have to spill the input vector
641 // to a temporary stack slot, update the element, then reload it. This is
642 // badness. We could also load the value into a vector register (either
643 // with a "move to register" or "extload into register" instruction, then
644 // permute it into place, if the idx is a constant and if the idx is
645 // supported by the target.
646 EVT VT = Tmp1.getValueType();
647 EVT EltVT = VT.getVectorElementType();
648 EVT IdxVT = Tmp3.getValueType();
649 EVT PtrVT = TLI.getPointerTy();
650 SDValue StackPtr = DAG.CreateStackTemporary(VT);
652 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
655 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
656 PseudoSourceValue::getFixedStack(SPFI), 0,
659 // Truncate or zero extend offset to target pointer type.
660 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
661 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
662 // Add the offset to the index.
663 unsigned EltSize = EltVT.getSizeInBits()/8;
664 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
665 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
666 // Store the scalar value.
667 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
668 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT,
670 // Load the updated vector.
671 return DAG.getLoad(VT, dl, Ch, StackPtr,
672 PseudoSourceValue::getFixedStack(SPFI), 0,
677 SDValue SelectionDAGLegalize::
678 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
679 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
680 // SCALAR_TO_VECTOR requires that the type of the value being inserted
681 // match the element type of the vector being created, except for
682 // integers in which case the inserted value can be over width.
683 EVT EltVT = Vec.getValueType().getVectorElementType();
684 if (Val.getValueType() == EltVT ||
685 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
686 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
687 Vec.getValueType(), Val);
689 unsigned NumElts = Vec.getValueType().getVectorNumElements();
690 // We generate a shuffle of InVec and ScVec, so the shuffle mask
691 // should be 0,1,2,3,4,5... with the appropriate element replaced with
693 SmallVector<int, 8> ShufOps;
694 for (unsigned i = 0; i != NumElts; ++i)
695 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
697 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
701 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
704 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
705 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
706 // FIXME: We shouldn't do this for TargetConstantFP's.
707 // FIXME: move this to the DAG Combiner! Note that we can't regress due
708 // to phase ordering between legalized code and the dag combiner. This
709 // probably means that we need to integrate dag combiner and legalizer
711 // We generally can't do this one for long doubles.
712 SDValue Tmp1 = ST->getChain();
713 SDValue Tmp2 = ST->getBasePtr();
715 int SVOffset = ST->getSrcValueOffset();
716 unsigned Alignment = ST->getAlignment();
717 bool isVolatile = ST->isVolatile();
718 bool isNonTemporal = ST->isNonTemporal();
719 DebugLoc dl = ST->getDebugLoc();
720 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
721 if (CFP->getValueType(0) == MVT::f32 &&
722 getTypeAction(MVT::i32) == Legal) {
723 Tmp3 = DAG.getConstant(CFP->getValueAPF().
724 bitcastToAPInt().zextOrTrunc(32),
726 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
727 SVOffset, isVolatile, isNonTemporal, Alignment);
728 } else if (CFP->getValueType(0) == MVT::f64) {
729 // If this target supports 64-bit registers, do a single 64-bit store.
730 if (getTypeAction(MVT::i64) == Legal) {
731 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
732 zextOrTrunc(64), MVT::i64);
733 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
734 SVOffset, isVolatile, isNonTemporal, Alignment);
735 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
736 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
737 // stores. If the target supports neither 32- nor 64-bits, this
738 // xform is certainly not worth it.
739 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
740 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
741 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
742 if (TLI.isBigEndian()) std::swap(Lo, Hi);
744 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
745 SVOffset, isVolatile, isNonTemporal, Alignment);
746 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
747 DAG.getIntPtrConstant(4));
748 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
749 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
751 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
758 /// LegalizeOp - We know that the specified value has a legal type, and
759 /// that its operands are legal. Now ensure that the operation itself
760 /// is legal, recursively ensuring that the operands' operations remain
762 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
763 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
766 SDNode *Node = Op.getNode();
767 DebugLoc dl = Node->getDebugLoc();
769 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
770 assert(getTypeAction(Node->getValueType(i)) == Legal &&
771 "Unexpected illegal type!");
773 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
774 assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
775 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
776 "Unexpected illegal type!");
778 // Note that LegalizeOp may be reentered even from single-use nodes, which
779 // means that we always must cache transformed nodes.
780 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
781 if (I != LegalizedNodes.end()) return I->second;
783 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
785 bool isCustom = false;
787 // Figure out the correct action; the way to query this varies by opcode
788 TargetLowering::LegalizeAction Action;
789 bool SimpleFinishLegalizing = true;
790 switch (Node->getOpcode()) {
791 case ISD::INTRINSIC_W_CHAIN:
792 case ISD::INTRINSIC_WO_CHAIN:
793 case ISD::INTRINSIC_VOID:
796 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
798 case ISD::SINT_TO_FP:
799 case ISD::UINT_TO_FP:
800 case ISD::EXTRACT_VECTOR_ELT:
801 Action = TLI.getOperationAction(Node->getOpcode(),
802 Node->getOperand(0).getValueType());
804 case ISD::FP_ROUND_INREG:
805 case ISD::SIGN_EXTEND_INREG: {
806 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
807 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
813 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
814 Node->getOpcode() == ISD::SETCC ? 2 : 1;
815 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
816 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
817 ISD::CondCode CCCode =
818 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
819 Action = TLI.getCondCodeAction(CCCode, OpVT);
820 if (Action == TargetLowering::Legal) {
821 if (Node->getOpcode() == ISD::SELECT_CC)
822 Action = TLI.getOperationAction(Node->getOpcode(),
823 Node->getValueType(0));
825 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
831 // FIXME: Model these properly. LOAD and STORE are complicated, and
832 // STORE expects the unlegalized operand in some cases.
833 SimpleFinishLegalizing = false;
835 case ISD::CALLSEQ_START:
836 case ISD::CALLSEQ_END:
837 // FIXME: This shouldn't be necessary. These nodes have special properties
838 // dealing with the recursive nature of legalization. Removing this
839 // special case should be done as part of making LegalizeDAG non-recursive.
840 SimpleFinishLegalizing = false;
842 case ISD::EXTRACT_ELEMENT:
843 case ISD::FLT_ROUNDS_:
851 case ISD::MERGE_VALUES:
853 case ISD::FRAME_TO_ARGS_OFFSET:
854 // These operations lie about being legal: when they claim to be legal,
855 // they should actually be expanded.
856 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
857 if (Action == TargetLowering::Legal)
858 Action = TargetLowering::Expand;
860 case ISD::TRAMPOLINE:
862 case ISD::RETURNADDR:
863 // These operations lie about being legal: when they claim to be legal,
864 // they should actually be custom-lowered.
865 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
866 if (Action == TargetLowering::Legal)
867 Action = TargetLowering::Custom;
869 case ISD::BUILD_VECTOR:
870 // A weird case: legalization for BUILD_VECTOR never legalizes the
872 // FIXME: This really sucks... changing it isn't semantically incorrect,
873 // but it massively pessimizes the code for floating-point BUILD_VECTORs
874 // because ConstantFP operands get legalized into constant pool loads
875 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
876 // though, because BUILD_VECTORS usually get lowered into other nodes
877 // which get legalized properly.
878 SimpleFinishLegalizing = false;
881 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
882 Action = TargetLowering::Legal;
884 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
889 if (SimpleFinishLegalizing) {
890 SmallVector<SDValue, 8> Ops, ResultVals;
891 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
892 Ops.push_back(LegalizeOp(Node->getOperand(i)));
893 switch (Node->getOpcode()) {
900 // Branches tweak the chain to include LastCALLSEQ_END
901 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
903 Ops[0] = LegalizeOp(Ops[0]);
904 LastCALLSEQ_END = DAG.getEntryNode();
911 // Legalizing shifts/rotates requires adjusting the shift amount
912 // to the appropriate width.
913 if (!Ops[1].getValueType().isVector())
914 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1]));
919 // Legalizing shifts/rotates requires adjusting the shift amount
920 // to the appropriate width.
921 if (!Ops[2].getValueType().isVector())
922 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2]));
926 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(),
929 case TargetLowering::Legal:
930 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
931 ResultVals.push_back(Result.getValue(i));
933 case TargetLowering::Custom:
934 // FIXME: The handling for custom lowering with multiple results is
936 Tmp1 = TLI.LowerOperation(Result, DAG);
937 if (Tmp1.getNode()) {
938 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
940 ResultVals.push_back(Tmp1);
942 ResultVals.push_back(Tmp1.getValue(i));
948 case TargetLowering::Expand:
949 ExpandNode(Result.getNode(), ResultVals);
951 case TargetLowering::Promote:
952 PromoteNode(Result.getNode(), ResultVals);
955 if (!ResultVals.empty()) {
956 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
957 if (ResultVals[i] != SDValue(Node, i))
958 ResultVals[i] = LegalizeOp(ResultVals[i]);
959 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
961 return ResultVals[Op.getResNo()];
965 switch (Node->getOpcode()) {
972 llvm_unreachable("Do not know how to legalize this operator!");
974 case ISD::BUILD_VECTOR:
975 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
976 default: llvm_unreachable("This action is not supported yet!");
977 case TargetLowering::Custom:
978 Tmp3 = TLI.LowerOperation(Result, DAG);
979 if (Tmp3.getNode()) {
984 case TargetLowering::Expand:
985 Result = ExpandBUILD_VECTOR(Result.getNode());
989 case ISD::CALLSEQ_START: {
990 SDNode *CallEnd = FindCallEndFromCallStart(Node);
992 // Recursively Legalize all of the inputs of the call end that do not lead
993 // to this call start. This ensures that any libcalls that need be inserted
994 // are inserted *before* the CALLSEQ_START.
995 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
996 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
997 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1001 // Now that we legalized all of the inputs (which may have inserted
1002 // libcalls) create the new CALLSEQ_START node.
1003 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1005 // Merge in the last call, to ensure that this call start after the last
1007 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1008 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1009 Tmp1, LastCALLSEQ_END);
1010 Tmp1 = LegalizeOp(Tmp1);
1013 // Do not try to legalize the target-specific arguments (#1+).
1014 if (Tmp1 != Node->getOperand(0)) {
1015 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1017 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1020 // Remember that the CALLSEQ_START is legalized.
1021 AddLegalizedOperand(Op.getValue(0), Result);
1022 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1023 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1025 // Now that the callseq_start and all of the non-call nodes above this call
1026 // sequence have been legalized, legalize the call itself. During this
1027 // process, no libcalls can/will be inserted, guaranteeing that no calls
1029 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1030 // Note that we are selecting this call!
1031 LastCALLSEQ_END = SDValue(CallEnd, 0);
1032 IsLegalizingCall = true;
1034 // Legalize the call, starting from the CALLSEQ_END.
1035 LegalizeOp(LastCALLSEQ_END);
1036 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1039 case ISD::CALLSEQ_END:
1040 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1041 // will cause this node to be legalized as well as handling libcalls right.
1042 if (LastCALLSEQ_END.getNode() != Node) {
1043 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1044 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1045 assert(I != LegalizedNodes.end() &&
1046 "Legalizing the call start should have legalized this node!");
1050 // Otherwise, the call start has been legalized and everything is going
1051 // according to plan. Just legalize ourselves normally here.
1052 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1053 // Do not try to legalize the target-specific arguments (#1+), except for
1054 // an optional flag input.
1055 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1056 if (Tmp1 != Node->getOperand(0)) {
1057 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1059 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1062 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1063 if (Tmp1 != Node->getOperand(0) ||
1064 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1065 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1068 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1071 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1072 // This finishes up call legalization.
1073 IsLegalizingCall = false;
1075 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1076 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1077 if (Node->getNumValues() == 2)
1078 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1079 return Result.getValue(Op.getResNo());
1081 LoadSDNode *LD = cast<LoadSDNode>(Node);
1082 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1083 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1085 ISD::LoadExtType ExtType = LD->getExtensionType();
1086 if (ExtType == ISD::NON_EXTLOAD) {
1087 EVT VT = Node->getValueType(0);
1088 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1089 Tmp3 = Result.getValue(0);
1090 Tmp4 = Result.getValue(1);
1092 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1093 default: llvm_unreachable("This action is not supported yet!");
1094 case TargetLowering::Legal:
1095 // If this is an unaligned load and the target doesn't support it,
1097 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1098 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1099 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1100 if (LD->getAlignment() < ABIAlignment){
1101 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1103 Tmp3 = Result.getOperand(0);
1104 Tmp4 = Result.getOperand(1);
1105 Tmp3 = LegalizeOp(Tmp3);
1106 Tmp4 = LegalizeOp(Tmp4);
1110 case TargetLowering::Custom:
1111 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1112 if (Tmp1.getNode()) {
1113 Tmp3 = LegalizeOp(Tmp1);
1114 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1117 case TargetLowering::Promote: {
1118 // Only promote a load of vector type to another.
1119 assert(VT.isVector() && "Cannot promote this load!");
1120 // Change base type to a different vector type.
1121 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1123 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1124 LD->getSrcValueOffset(),
1125 LD->isVolatile(), LD->isNonTemporal(),
1126 LD->getAlignment());
1127 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
1128 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1132 // Since loads produce two values, make sure to remember that we
1133 // legalized both of them.
1134 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1135 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1136 return Op.getResNo() ? Tmp4 : Tmp3;
1138 EVT SrcVT = LD->getMemoryVT();
1139 unsigned SrcWidth = SrcVT.getSizeInBits();
1140 int SVOffset = LD->getSrcValueOffset();
1141 unsigned Alignment = LD->getAlignment();
1142 bool isVolatile = LD->isVolatile();
1143 bool isNonTemporal = LD->isNonTemporal();
1145 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1146 // Some targets pretend to have an i1 loading operation, and actually
1147 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1148 // bits are guaranteed to be zero; it helps the optimizers understand
1149 // that these bits are zero. It is also useful for EXTLOAD, since it
1150 // tells the optimizers that those bits are undefined. It would be
1151 // nice to have an effective generic way of getting these benefits...
1152 // Until such a way is found, don't insist on promoting i1 here.
1153 (SrcVT != MVT::i1 ||
1154 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1155 // Promote to a byte-sized load if not loading an integral number of
1156 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1157 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1158 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
1161 // The extra bits are guaranteed to be zero, since we stored them that
1162 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1164 ISD::LoadExtType NewExtType =
1165 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1167 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
1168 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1169 NVT, isVolatile, isNonTemporal, Alignment);
1171 Ch = Result.getValue(1); // The chain.
1173 if (ExtType == ISD::SEXTLOAD)
1174 // Having the top bits zero doesn't help when sign extending.
1175 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1176 Result.getValueType(),
1177 Result, DAG.getValueType(SrcVT));
1178 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1179 // All the top bits are guaranteed to be zero - inform the optimizers.
1180 Result = DAG.getNode(ISD::AssertZext, dl,
1181 Result.getValueType(), Result,
1182 DAG.getValueType(SrcVT));
1184 Tmp1 = LegalizeOp(Result);
1185 Tmp2 = LegalizeOp(Ch);
1186 } else if (SrcWidth & (SrcWidth - 1)) {
1187 // If not loading a power-of-2 number of bits, expand as two loads.
1188 assert(!SrcVT.isVector() && "Unsupported extload!");
1189 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1190 assert(RoundWidth < SrcWidth);
1191 unsigned ExtraWidth = SrcWidth - RoundWidth;
1192 assert(ExtraWidth < RoundWidth);
1193 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1194 "Load size not an integral number of bytes!");
1195 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1196 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1198 unsigned IncrementSize;
1200 if (TLI.isLittleEndian()) {
1201 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1202 // Load the bottom RoundWidth bits.
1203 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
1204 Node->getValueType(0), Tmp1, Tmp2,
1205 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1206 isNonTemporal, Alignment);
1208 // Load the remaining ExtraWidth bits.
1209 IncrementSize = RoundWidth / 8;
1210 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1211 DAG.getIntPtrConstant(IncrementSize));
1212 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1213 LD->getSrcValue(), SVOffset + IncrementSize,
1214 ExtraVT, isVolatile, isNonTemporal,
1215 MinAlign(Alignment, IncrementSize));
1217 // Build a factor node to remember that this load is independent of the
1219 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1222 // Move the top bits to the right place.
1223 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1224 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1226 // Join the hi and lo parts.
1227 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1229 // Big endian - avoid unaligned loads.
1230 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1231 // Load the top RoundWidth bits.
1232 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1233 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1234 isNonTemporal, Alignment);
1236 // Load the remaining ExtraWidth bits.
1237 IncrementSize = RoundWidth / 8;
1238 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1239 DAG.getIntPtrConstant(IncrementSize));
1240 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
1241 Node->getValueType(0), Tmp1, Tmp2,
1242 LD->getSrcValue(), SVOffset + IncrementSize,
1243 ExtraVT, isVolatile, isNonTemporal,
1244 MinAlign(Alignment, IncrementSize));
1246 // Build a factor node to remember that this load is independent of the
1248 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1251 // Move the top bits to the right place.
1252 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1253 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1255 // Join the hi and lo parts.
1256 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1259 Tmp1 = LegalizeOp(Result);
1260 Tmp2 = LegalizeOp(Ch);
1262 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1263 default: llvm_unreachable("This action is not supported yet!");
1264 case TargetLowering::Custom:
1267 case TargetLowering::Legal:
1268 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1269 Tmp1 = Result.getValue(0);
1270 Tmp2 = Result.getValue(1);
1273 Tmp3 = TLI.LowerOperation(Result, DAG);
1274 if (Tmp3.getNode()) {
1275 Tmp1 = LegalizeOp(Tmp3);
1276 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1279 // If this is an unaligned load and the target doesn't support it,
1281 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1282 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1283 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1284 if (LD->getAlignment() < ABIAlignment){
1285 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1287 Tmp1 = Result.getOperand(0);
1288 Tmp2 = Result.getOperand(1);
1289 Tmp1 = LegalizeOp(Tmp1);
1290 Tmp2 = LegalizeOp(Tmp2);
1295 case TargetLowering::Expand:
1296 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1297 // f128 = EXTLOAD {f32,f64} too
1298 if ((SrcVT == MVT::f32 && (Node->getValueType(0) == MVT::f64 ||
1299 Node->getValueType(0) == MVT::f128)) ||
1300 (SrcVT == MVT::f64 && Node->getValueType(0) == MVT::f128)) {
1301 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1302 LD->getSrcValueOffset(),
1303 LD->isVolatile(), LD->isNonTemporal(),
1304 LD->getAlignment());
1305 Result = DAG.getNode(ISD::FP_EXTEND, dl,
1306 Node->getValueType(0), Load);
1307 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1308 Tmp2 = LegalizeOp(Load.getValue(1));
1311 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1312 // Turn the unsupported load into an EXTLOAD followed by an explicit
1313 // zero/sign extend inreg.
1314 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1315 Tmp1, Tmp2, LD->getSrcValue(),
1316 LD->getSrcValueOffset(), SrcVT,
1317 LD->isVolatile(), LD->isNonTemporal(),
1318 LD->getAlignment());
1320 if (ExtType == ISD::SEXTLOAD)
1321 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1322 Result.getValueType(),
1323 Result, DAG.getValueType(SrcVT));
1325 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
1326 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1327 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1332 // Since loads produce two values, make sure to remember that we legalized
1334 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1335 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1336 return Op.getResNo() ? Tmp2 : Tmp1;
1340 StoreSDNode *ST = cast<StoreSDNode>(Node);
1341 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1342 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1343 int SVOffset = ST->getSrcValueOffset();
1344 unsigned Alignment = ST->getAlignment();
1345 bool isVolatile = ST->isVolatile();
1346 bool isNonTemporal = ST->isNonTemporal();
1348 if (!ST->isTruncatingStore()) {
1349 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1350 Result = SDValue(OptStore, 0);
1355 Tmp3 = LegalizeOp(ST->getValue());
1356 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1359 EVT VT = Tmp3.getValueType();
1360 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1361 default: llvm_unreachable("This action is not supported yet!");
1362 case TargetLowering::Legal:
1363 // If this is an unaligned store and the target doesn't support it,
1365 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1366 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1367 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1368 if (ST->getAlignment() < ABIAlignment)
1369 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1373 case TargetLowering::Custom:
1374 Tmp1 = TLI.LowerOperation(Result, DAG);
1375 if (Tmp1.getNode()) Result = Tmp1;
1377 case TargetLowering::Promote:
1378 assert(VT.isVector() && "Unknown legal promote case!");
1379 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
1380 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1381 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1382 ST->getSrcValue(), SVOffset, isVolatile,
1383 isNonTemporal, Alignment);
1389 Tmp3 = LegalizeOp(ST->getValue());
1391 EVT StVT = ST->getMemoryVT();
1392 unsigned StWidth = StVT.getSizeInBits();
1394 if (StWidth != StVT.getStoreSizeInBits()) {
1395 // Promote to a byte-sized store with upper bits zero if not
1396 // storing an integral number of bytes. For example, promote
1397 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1398 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), StVT.getStoreSizeInBits());
1399 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1400 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1401 SVOffset, NVT, isVolatile, isNonTemporal,
1403 } else if (StWidth & (StWidth - 1)) {
1404 // If not storing a power-of-2 number of bits, expand as two stores.
1405 assert(!StVT.isVector() && "Unsupported truncstore!");
1406 unsigned RoundWidth = 1 << Log2_32(StWidth);
1407 assert(RoundWidth < StWidth);
1408 unsigned ExtraWidth = StWidth - RoundWidth;
1409 assert(ExtraWidth < RoundWidth);
1410 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1411 "Store size not an integral number of bytes!");
1412 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1413 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1415 unsigned IncrementSize;
1417 if (TLI.isLittleEndian()) {
1418 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1419 // Store the bottom RoundWidth bits.
1420 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1422 isVolatile, isNonTemporal, Alignment);
1424 // Store the remaining ExtraWidth bits.
1425 IncrementSize = RoundWidth / 8;
1426 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1427 DAG.getIntPtrConstant(IncrementSize));
1428 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1429 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1430 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1431 SVOffset + IncrementSize, ExtraVT, isVolatile,
1433 MinAlign(Alignment, IncrementSize));
1435 // Big endian - avoid unaligned stores.
1436 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1437 // Store the top RoundWidth bits.
1438 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1439 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1440 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1441 SVOffset, RoundVT, isVolatile, isNonTemporal,
1444 // Store the remaining ExtraWidth bits.
1445 IncrementSize = RoundWidth / 8;
1446 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1447 DAG.getIntPtrConstant(IncrementSize));
1448 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1449 SVOffset + IncrementSize, ExtraVT, isVolatile,
1451 MinAlign(Alignment, IncrementSize));
1454 // The order of the stores doesn't matter.
1455 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1457 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1458 Tmp2 != ST->getBasePtr())
1459 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1462 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1463 default: llvm_unreachable("This action is not supported yet!");
1464 case TargetLowering::Legal:
1465 // If this is an unaligned store and the target doesn't support it,
1467 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1468 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1469 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1470 if (ST->getAlignment() < ABIAlignment)
1471 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1475 case TargetLowering::Custom:
1476 Result = TLI.LowerOperation(Result, DAG);
1479 // TRUNCSTORE:i16 i32 -> STORE i16
1480 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
1481 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1482 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1483 SVOffset, isVolatile, isNonTemporal,
1492 assert(Result.getValueType() == Op.getValueType() &&
1493 "Bad legalization!");
1495 // Make sure that the generated code is itself legal.
1497 Result = LegalizeOp(Result);
1499 // Note that LegalizeOp may be reentered even from single-use nodes, which
1500 // means that we always must cache transformed nodes.
1501 AddLegalizedOperand(Op, Result);
1505 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1506 SDValue Vec = Op.getOperand(0);
1507 SDValue Idx = Op.getOperand(1);
1508 DebugLoc dl = Op.getDebugLoc();
1509 // Store the value to a temporary stack slot, then LOAD the returned part.
1510 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1511 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0,
1514 // Add the offset to the index.
1516 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1517 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1518 DAG.getConstant(EltSize, Idx.getValueType()));
1520 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1521 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1523 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1525 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1527 if (Op.getValueType().isVector())
1528 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0,
1531 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1532 NULL, 0, Vec.getValueType().getVectorElementType(),
1536 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1537 // We can't handle this case efficiently. Allocate a sufficiently
1538 // aligned object on the stack, store each element into it, then load
1539 // the result as a vector.
1540 // Create the stack frame object.
1541 EVT VT = Node->getValueType(0);
1542 EVT OpVT = Node->getOperand(0).getValueType();
1543 EVT EltVT = VT.getVectorElementType();
1544 DebugLoc dl = Node->getDebugLoc();
1545 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1546 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1547 const Value *SV = PseudoSourceValue::getFixedStack(FI);
1549 // Emit a store of each element to the stack slot.
1550 SmallVector<SDValue, 8> Stores;
1551 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1552 // Store (in the right endianness) the elements to memory.
1553 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1554 // Ignore undef elements.
1555 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1557 unsigned Offset = TypeByteSize*i;
1559 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1560 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1562 // If EltVT smaller than OpVT, only store the bits necessary.
1563 if (!OpVT.isVector() && EltVT.bitsLT(OpVT)) {
1564 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1565 Node->getOperand(i), Idx, SV, Offset,
1566 EltVT, false, false, 0));
1568 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1569 Node->getOperand(i), Idx, SV, Offset,
1574 if (!Stores.empty()) // Not all undef elements?
1575 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1576 &Stores[0], Stores.size());
1578 StoreChain = DAG.getEntryNode();
1580 // Result is a load from the stack slot.
1581 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0, false, false, 0);
1584 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1585 DebugLoc dl = Node->getDebugLoc();
1586 SDValue Tmp1 = Node->getOperand(0);
1587 SDValue Tmp2 = Node->getOperand(1);
1588 assert((Tmp2.getValueType() == MVT::f32 ||
1589 Tmp2.getValueType() == MVT::f64) &&
1590 "Ugly special-cased code!");
1591 // Get the sign bit of the RHS.
1593 EVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32;
1594 if (isTypeLegal(IVT)) {
1595 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
1597 assert(isTypeLegal(TLI.getPointerTy()) &&
1598 (TLI.getPointerTy() == MVT::i32 ||
1599 TLI.getPointerTy() == MVT::i64) &&
1600 "Legal type for load?!");
1601 SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType());
1602 SDValue StorePtr = StackPtr, LoadPtr = StackPtr;
1604 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0,
1606 if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian())
1607 LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(),
1608 LoadPtr, DAG.getIntPtrConstant(4));
1609 SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(),
1610 Ch, LoadPtr, NULL, 0, MVT::i32,
1614 DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1615 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1617 // Get the absolute value of the result.
1618 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1619 // Select between the nabs and abs value based on the sign bit of
1621 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1622 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1626 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1627 SmallVectorImpl<SDValue> &Results) {
1628 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1629 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1630 " not tell us which reg is the stack pointer!");
1631 DebugLoc dl = Node->getDebugLoc();
1632 EVT VT = Node->getValueType(0);
1633 SDValue Tmp1 = SDValue(Node, 0);
1634 SDValue Tmp2 = SDValue(Node, 1);
1635 SDValue Tmp3 = Node->getOperand(2);
1636 SDValue Chain = Tmp1.getOperand(0);
1638 // Chain the dynamic stack allocation so that it doesn't modify the stack
1639 // pointer when other instructions are using the stack.
1640 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1642 SDValue Size = Tmp2.getOperand(1);
1643 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1644 Chain = SP.getValue(1);
1645 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1646 unsigned StackAlign =
1647 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1648 if (Align > StackAlign)
1649 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1650 DAG.getConstant(-(uint64_t)Align, VT));
1651 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1652 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1654 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1655 DAG.getIntPtrConstant(0, true), SDValue());
1657 Results.push_back(Tmp1);
1658 Results.push_back(Tmp2);
1661 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1662 /// condition code CC on the current target. This routine expands SETCC with
1663 /// illegal condition code into AND / OR of multiple SETCC values.
1664 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1665 SDValue &LHS, SDValue &RHS,
1668 EVT OpVT = LHS.getValueType();
1669 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1670 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1671 default: llvm_unreachable("Unknown condition code action!");
1672 case TargetLowering::Legal:
1675 case TargetLowering::Expand: {
1676 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1679 default: llvm_unreachable("Don't know how to expand this condition!");
1680 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1681 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1682 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1683 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1684 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1685 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1686 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1687 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1688 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1689 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1690 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1691 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1692 // FIXME: Implement more expansions.
1695 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1696 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1697 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1705 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1706 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1707 /// a load from the stack slot to DestVT, extending it if needed.
1708 /// The resultant code need not be legal.
1709 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1713 // Create the stack frame object.
1715 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1716 getTypeForEVT(*DAG.getContext()));
1717 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1719 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1720 int SPFI = StackPtrFI->getIndex();
1721 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
1723 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1724 unsigned SlotSize = SlotVT.getSizeInBits();
1725 unsigned DestSize = DestVT.getSizeInBits();
1726 unsigned DestAlign =
1727 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForEVT(*DAG.getContext()));
1729 // Emit a store to the stack slot. Use a truncstore if the input value is
1730 // later than DestVT.
1733 if (SrcSize > SlotSize)
1734 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1735 SV, 0, SlotVT, false, false, SrcAlign);
1737 assert(SrcSize == SlotSize && "Invalid store");
1738 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1739 SV, 0, false, false, SrcAlign);
1742 // Result is a load from the stack slot.
1743 if (SlotSize == DestSize)
1744 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, false,
1747 assert(SlotSize < DestSize && "Unknown extension!");
1748 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
1749 false, false, DestAlign);
1752 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1753 DebugLoc dl = Node->getDebugLoc();
1754 // Create a vector sized/aligned stack slot, store the value to element #0,
1755 // then load the whole vector back out.
1756 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1758 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1759 int SPFI = StackPtrFI->getIndex();
1761 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1763 PseudoSourceValue::getFixedStack(SPFI), 0,
1764 Node->getValueType(0).getVectorElementType(),
1766 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1767 PseudoSourceValue::getFixedStack(SPFI), 0,
1772 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1773 /// support the operation, but do support the resultant vector type.
1774 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1775 unsigned NumElems = Node->getNumOperands();
1776 SDValue Value1, Value2;
1777 DebugLoc dl = Node->getDebugLoc();
1778 EVT VT = Node->getValueType(0);
1779 EVT OpVT = Node->getOperand(0).getValueType();
1780 EVT EltVT = VT.getVectorElementType();
1782 // If the only non-undef value is the low element, turn this into a
1783 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1784 bool isOnlyLowElement = true;
1785 bool MoreThanTwoValues = false;
1786 bool isConstant = true;
1787 for (unsigned i = 0; i < NumElems; ++i) {
1788 SDValue V = Node->getOperand(i);
1789 if (V.getOpcode() == ISD::UNDEF)
1792 isOnlyLowElement = false;
1793 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1796 if (!Value1.getNode()) {
1798 } else if (!Value2.getNode()) {
1801 } else if (V != Value1 && V != Value2) {
1802 MoreThanTwoValues = true;
1806 if (!Value1.getNode())
1807 return DAG.getUNDEF(VT);
1809 if (isOnlyLowElement)
1810 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1812 // If all elements are constants, create a load from the constant pool.
1814 std::vector<Constant*> CV;
1815 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1816 if (ConstantFPSDNode *V =
1817 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1818 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1819 } else if (ConstantSDNode *V =
1820 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1822 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1824 // If OpVT and EltVT don't match, EltVT is not legal and the
1825 // element values have been promoted/truncated earlier. Undo this;
1826 // we don't want a v16i8 to become a v16i32 for example.
1827 const ConstantInt *CI = V->getConstantIntValue();
1828 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1829 CI->getZExtValue()));
1832 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1833 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1834 CV.push_back(UndefValue::get(OpNTy));
1837 Constant *CP = ConstantVector::get(CV);
1838 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1839 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1840 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1841 PseudoSourceValue::getConstantPool(), 0,
1842 false, false, Alignment);
1845 if (!MoreThanTwoValues) {
1846 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1847 for (unsigned i = 0; i < NumElems; ++i) {
1848 SDValue V = Node->getOperand(i);
1849 if (V.getOpcode() == ISD::UNDEF)
1851 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1853 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1854 // Get the splatted value into the low element of a vector register.
1855 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1857 if (Value2.getNode())
1858 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1860 Vec2 = DAG.getUNDEF(VT);
1862 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1863 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1867 // Otherwise, we can't handle this case efficiently.
1868 return ExpandVectorBuildThroughStack(Node);
1871 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1872 // does not fit into a register, return the lo part and set the hi part to the
1873 // by-reg argument. If it does fit into a single register, return the result
1874 // and leave the Hi part unset.
1875 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1877 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
1878 // The input chain to this libcall is the entry node of the function.
1879 // Legalizing the call will automatically add the previous call to the
1881 SDValue InChain = DAG.getEntryNode();
1883 TargetLowering::ArgListTy Args;
1884 TargetLowering::ArgListEntry Entry;
1885 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1886 EVT ArgVT = Node->getOperand(i).getValueType();
1887 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1888 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1889 Entry.isSExt = isSigned;
1890 Entry.isZExt = !isSigned;
1891 Args.push_back(Entry);
1893 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1894 TLI.getPointerTy());
1896 // Splice the libcall in wherever FindInputOutputChains tells us to.
1897 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1898 std::pair<SDValue, SDValue> CallInfo =
1899 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
1900 0, TLI.getLibcallCallingConv(LC), false,
1901 /*isReturnValueUsed=*/true,
1903 Node->getDebugLoc(), DAG.GetOrdering(Node));
1905 // Legalize the call sequence, starting with the chain. This will advance
1906 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
1907 // was added by LowerCallTo (guaranteeing proper serialization of calls).
1908 LegalizeOp(CallInfo.second);
1909 return CallInfo.first;
1912 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1913 RTLIB::Libcall Call_F32,
1914 RTLIB::Libcall Call_F64,
1915 RTLIB::Libcall Call_F80,
1916 RTLIB::Libcall Call_PPCF128) {
1918 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1919 default: llvm_unreachable("Unexpected request for libcall!");
1920 case MVT::f32: LC = Call_F32; break;
1921 case MVT::f64: LC = Call_F64; break;
1922 case MVT::f80: LC = Call_F80; break;
1923 case MVT::ppcf128: LC = Call_PPCF128; break;
1925 return ExpandLibCall(LC, Node, false);
1928 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1929 RTLIB::Libcall Call_I8,
1930 RTLIB::Libcall Call_I16,
1931 RTLIB::Libcall Call_I32,
1932 RTLIB::Libcall Call_I64,
1933 RTLIB::Libcall Call_I128) {
1935 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1936 default: llvm_unreachable("Unexpected request for libcall!");
1937 case MVT::i8: LC = Call_I8; break;
1938 case MVT::i16: LC = Call_I16; break;
1939 case MVT::i32: LC = Call_I32; break;
1940 case MVT::i64: LC = Call_I64; break;
1941 case MVT::i128: LC = Call_I128; break;
1943 return ExpandLibCall(LC, Node, isSigned);
1946 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
1947 /// INT_TO_FP operation of the specified operand when the target requests that
1948 /// we expand it. At this point, we know that the result and operand types are
1949 /// legal for the target.
1950 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
1954 if (Op0.getValueType() == MVT::i32) {
1955 // simple 32-bit [signed|unsigned] integer to float/double expansion
1957 // Get the stack frame index of a 8 byte buffer.
1958 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
1960 // word offset constant for Hi/Lo address computation
1961 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
1962 // set up Hi and Lo (into buffer) address based on endian
1963 SDValue Hi = StackSlot;
1964 SDValue Lo = DAG.getNode(ISD::ADD, dl,
1965 TLI.getPointerTy(), StackSlot, WordOff);
1966 if (TLI.isLittleEndian())
1969 // if signed map to unsigned space
1972 // constant used to invert sign bit (signed to unsigned mapping)
1973 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
1974 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
1978 // store the lo of the constructed double - based on integer input
1979 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
1980 Op0Mapped, Lo, NULL, 0,
1982 // initial hi portion of constructed double
1983 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
1984 // store the hi of the constructed double - biased exponent
1985 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0,
1987 // load the constructed double
1988 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0,
1990 // FP constant to bias correct the final result
1991 SDValue Bias = DAG.getConstantFP(isSigned ?
1992 BitsToDouble(0x4330000080000000ULL) :
1993 BitsToDouble(0x4330000000000000ULL),
1995 // subtract the bias
1996 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
1999 // handle final rounding
2000 if (DestVT == MVT::f64) {
2003 } else if (DestVT.bitsLT(MVT::f64)) {
2004 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2005 DAG.getIntPtrConstant(0));
2006 } else if (DestVT.bitsGT(MVT::f64)) {
2007 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2011 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2012 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2014 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2015 Op0, DAG.getConstant(0, Op0.getValueType()),
2017 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2018 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2019 SignSet, Four, Zero);
2021 // If the sign bit of the integer is set, the large number will be treated
2022 // as a negative number. To counteract this, the dynamic code adds an
2023 // offset depending on the data type.
2025 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2026 default: llvm_unreachable("Unsupported integer type!");
2027 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2028 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2029 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2030 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2032 if (TLI.isLittleEndian()) FF <<= 32;
2033 Constant *FudgeFactor = ConstantInt::get(
2034 Type::getInt64Ty(*DAG.getContext()), FF);
2036 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2037 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2038 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2039 Alignment = std::min(Alignment, 4u);
2041 if (DestVT == MVT::f32)
2042 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2043 PseudoSourceValue::getConstantPool(), 0,
2044 false, false, Alignment);
2047 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2048 DAG.getEntryNode(), CPIdx,
2049 PseudoSourceValue::getConstantPool(), 0,
2050 MVT::f32, false, false, Alignment));
2053 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2056 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2057 /// *INT_TO_FP operation of the specified operand when the target requests that
2058 /// we promote it. At this point, we know that the result and operand types are
2059 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2060 /// operation that takes a larger input.
2061 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2065 // First step, figure out the appropriate *INT_TO_FP operation to use.
2066 EVT NewInTy = LegalOp.getValueType();
2068 unsigned OpToUse = 0;
2070 // Scan for the appropriate larger type to use.
2072 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2073 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2075 // If the target supports SINT_TO_FP of this type, use it.
2076 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2077 OpToUse = ISD::SINT_TO_FP;
2080 if (isSigned) continue;
2082 // If the target supports UINT_TO_FP of this type, use it.
2083 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2084 OpToUse = ISD::UINT_TO_FP;
2088 // Otherwise, try a larger type.
2091 // Okay, we found the operation and type to use. Zero extend our input to the
2092 // desired type then run the operation on it.
2093 return DAG.getNode(OpToUse, dl, DestVT,
2094 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2095 dl, NewInTy, LegalOp));
2098 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2099 /// FP_TO_*INT operation of the specified operand when the target requests that
2100 /// we promote it. At this point, we know that the result and operand types are
2101 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2102 /// operation that returns a larger result.
2103 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2107 // First step, figure out the appropriate FP_TO*INT operation to use.
2108 EVT NewOutTy = DestVT;
2110 unsigned OpToUse = 0;
2112 // Scan for the appropriate larger type to use.
2114 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2115 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2117 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2118 OpToUse = ISD::FP_TO_SINT;
2122 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2123 OpToUse = ISD::FP_TO_UINT;
2127 // Otherwise, try a larger type.
2131 // Okay, we found the operation and type to use.
2132 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2134 // Truncate the result of the extended FP_TO_*INT operation to the desired
2136 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2139 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2141 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2142 EVT VT = Op.getValueType();
2143 EVT SHVT = TLI.getShiftAmountTy();
2144 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2145 switch (VT.getSimpleVT().SimpleTy) {
2146 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2148 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2149 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2150 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2152 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2153 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2154 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2155 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2156 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2157 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2158 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2159 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2160 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2162 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2163 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2164 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2165 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2166 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2167 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2168 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2169 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2170 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2171 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2172 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2173 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2174 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2175 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2176 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2177 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2178 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2179 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2180 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2181 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2182 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2186 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2188 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2191 default: llvm_unreachable("Cannot expand this yet!");
2193 static const uint64_t mask[6] = {
2194 0x5555555555555555ULL, 0x3333333333333333ULL,
2195 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
2196 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
2198 EVT VT = Op.getValueType();
2199 EVT ShVT = TLI.getShiftAmountTy();
2200 unsigned len = VT.getSizeInBits();
2201 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2202 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
2203 unsigned EltSize = VT.isVector() ?
2204 VT.getVectorElementType().getSizeInBits() : len;
2205 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
2206 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2207 Op = DAG.getNode(ISD::ADD, dl, VT,
2208 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
2209 DAG.getNode(ISD::AND, dl, VT,
2210 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
2216 // for now, we do this:
2217 // x = x | (x >> 1);
2218 // x = x | (x >> 2);
2220 // x = x | (x >>16);
2221 // x = x | (x >>32); // for 64-bit input
2222 // return popcount(~x);
2224 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2225 EVT VT = Op.getValueType();
2226 EVT ShVT = TLI.getShiftAmountTy();
2227 unsigned len = VT.getSizeInBits();
2228 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2229 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2230 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2231 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2233 Op = DAG.getNOT(dl, Op, VT);
2234 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2237 // for now, we use: { return popcount(~x & (x - 1)); }
2238 // unless the target has ctlz but not ctpop, in which case we use:
2239 // { return 32 - nlz(~x & (x-1)); }
2240 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2241 EVT VT = Op.getValueType();
2242 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2243 DAG.getNOT(dl, Op, VT),
2244 DAG.getNode(ISD::SUB, dl, VT, Op,
2245 DAG.getConstant(1, VT)));
2246 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2247 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2248 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2249 return DAG.getNode(ISD::SUB, dl, VT,
2250 DAG.getConstant(VT.getSizeInBits(), VT),
2251 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2252 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2257 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2258 SmallVectorImpl<SDValue> &Results) {
2259 DebugLoc dl = Node->getDebugLoc();
2260 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2261 switch (Node->getOpcode()) {
2265 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2266 Results.push_back(Tmp1);
2269 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2271 case ISD::FRAMEADDR:
2272 case ISD::RETURNADDR:
2273 case ISD::FRAME_TO_ARGS_OFFSET:
2274 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2276 case ISD::FLT_ROUNDS_:
2277 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2279 case ISD::EH_RETURN:
2282 case ISD::MEMBARRIER:
2284 Results.push_back(Node->getOperand(0));
2286 case ISD::DYNAMIC_STACKALLOC:
2287 ExpandDYNAMIC_STACKALLOC(Node, Results);
2289 case ISD::MERGE_VALUES:
2290 for (unsigned i = 0; i < Node->getNumValues(); i++)
2291 Results.push_back(Node->getOperand(i));
2294 EVT VT = Node->getValueType(0);
2296 Results.push_back(DAG.getConstant(0, VT));
2297 else if (VT.isFloatingPoint())
2298 Results.push_back(DAG.getConstantFP(0, VT));
2300 llvm_unreachable("Unknown value type!");
2304 // If this operation is not supported, lower it to 'abort()' call
2305 TargetLowering::ArgListTy Args;
2306 std::pair<SDValue, SDValue> CallResult =
2307 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2308 false, false, false, false, 0, CallingConv::C, false,
2309 /*isReturnValueUsed=*/true,
2310 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2311 Args, DAG, dl, DAG.GetOrdering(Node));
2312 Results.push_back(CallResult.second);
2316 case ISD::BIT_CONVERT:
2317 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2318 Node->getValueType(0), dl);
2319 Results.push_back(Tmp1);
2321 case ISD::FP_EXTEND:
2322 Tmp1 = EmitStackConvert(Node->getOperand(0),
2323 Node->getOperand(0).getValueType(),
2324 Node->getValueType(0), dl);
2325 Results.push_back(Tmp1);
2327 case ISD::SIGN_EXTEND_INREG: {
2328 // NOTE: we could fall back on load/store here too for targets without
2329 // SAR. However, it is doubtful that any exist.
2330 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2331 EVT VT = Node->getValueType(0);
2332 EVT ShiftAmountTy = TLI.getShiftAmountTy();
2335 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2336 ExtraVT.getScalarType().getSizeInBits();
2337 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2338 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2339 Node->getOperand(0), ShiftCst);
2340 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2341 Results.push_back(Tmp1);
2344 case ISD::FP_ROUND_INREG: {
2345 // The only way we can lower this is to turn it into a TRUNCSTORE,
2346 // EXTLOAD pair, targetting a temporary location (a stack slot).
2348 // NOTE: there is a choice here between constantly creating new stack
2349 // slots and always reusing the same one. We currently always create
2350 // new ones, as reuse may inhibit scheduling.
2351 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2352 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2353 Node->getValueType(0), dl);
2354 Results.push_back(Tmp1);
2357 case ISD::SINT_TO_FP:
2358 case ISD::UINT_TO_FP:
2359 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2360 Node->getOperand(0), Node->getValueType(0), dl);
2361 Results.push_back(Tmp1);
2363 case ISD::FP_TO_UINT: {
2364 SDValue True, False;
2365 EVT VT = Node->getOperand(0).getValueType();
2366 EVT NVT = Node->getValueType(0);
2367 const uint64_t zero[] = {0, 0};
2368 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
2369 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2370 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2371 Tmp1 = DAG.getConstantFP(apf, VT);
2372 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2373 Node->getOperand(0),
2375 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2376 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2377 DAG.getNode(ISD::FSUB, dl, VT,
2378 Node->getOperand(0), Tmp1));
2379 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2380 DAG.getConstant(x, NVT));
2381 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2382 Results.push_back(Tmp1);
2386 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2387 EVT VT = Node->getValueType(0);
2388 Tmp1 = Node->getOperand(0);
2389 Tmp2 = Node->getOperand(1);
2390 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0,
2392 // Increment the pointer, VAList, to the next vaarg
2393 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2394 DAG.getConstant(TLI.getTargetData()->
2395 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2396 TLI.getPointerTy()));
2397 // Store the incremented VAList to the legalized pointer
2398 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0,
2400 // Load the actual argument out of the pointer VAList
2401 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0,
2403 Results.push_back(Results[0].getValue(1));
2407 // This defaults to loading a pointer from the input and storing it to the
2408 // output, returning the chain.
2409 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2410 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2411 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2412 Node->getOperand(2), VS, 0, false, false, 0);
2413 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0,
2415 Results.push_back(Tmp1);
2418 case ISD::EXTRACT_VECTOR_ELT:
2419 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2420 // This must be an access of the only element. Return it.
2421 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
2422 Node->getOperand(0));
2424 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2425 Results.push_back(Tmp1);
2427 case ISD::EXTRACT_SUBVECTOR:
2428 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2430 case ISD::CONCAT_VECTORS: {
2431 Results.push_back(ExpandVectorBuildThroughStack(Node));
2434 case ISD::SCALAR_TO_VECTOR:
2435 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2437 case ISD::INSERT_VECTOR_ELT:
2438 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2439 Node->getOperand(1),
2440 Node->getOperand(2), dl));
2442 case ISD::VECTOR_SHUFFLE: {
2443 SmallVector<int, 8> Mask;
2444 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
2446 EVT VT = Node->getValueType(0);
2447 EVT EltVT = VT.getVectorElementType();
2448 unsigned NumElems = VT.getVectorNumElements();
2449 SmallVector<SDValue, 8> Ops;
2450 for (unsigned i = 0; i != NumElems; ++i) {
2452 Ops.push_back(DAG.getUNDEF(EltVT));
2455 unsigned Idx = Mask[i];
2457 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2458 Node->getOperand(0),
2459 DAG.getIntPtrConstant(Idx)));
2461 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2462 Node->getOperand(1),
2463 DAG.getIntPtrConstant(Idx - NumElems)));
2465 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2466 Results.push_back(Tmp1);
2469 case ISD::EXTRACT_ELEMENT: {
2470 EVT OpTy = Node->getOperand(0).getValueType();
2471 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2473 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2474 DAG.getConstant(OpTy.getSizeInBits()/2,
2475 TLI.getShiftAmountTy()));
2476 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2479 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2480 Node->getOperand(0));
2482 Results.push_back(Tmp1);
2485 case ISD::STACKSAVE:
2486 // Expand to CopyFromReg if the target set
2487 // StackPointerRegisterToSaveRestore.
2488 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2489 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2490 Node->getValueType(0)));
2491 Results.push_back(Results[0].getValue(1));
2493 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2494 Results.push_back(Node->getOperand(0));
2497 case ISD::STACKRESTORE:
2498 // Expand to CopyToReg if the target set
2499 // StackPointerRegisterToSaveRestore.
2500 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2501 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2502 Node->getOperand(1)));
2504 Results.push_back(Node->getOperand(0));
2507 case ISD::FCOPYSIGN:
2508 Results.push_back(ExpandFCOPYSIGN(Node));
2511 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2512 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2513 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
2514 Node->getOperand(0));
2515 Results.push_back(Tmp1);
2518 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2519 EVT VT = Node->getValueType(0);
2520 Tmp1 = Node->getOperand(0);
2521 Tmp2 = DAG.getConstantFP(0.0, VT);
2522 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2523 Tmp1, Tmp2, ISD::SETUGT);
2524 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
2525 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
2526 Results.push_back(Tmp1);
2530 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
2531 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
2534 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
2535 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
2538 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
2539 RTLIB::COS_F80, RTLIB::COS_PPCF128));
2542 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
2543 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
2546 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
2547 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
2550 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
2551 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
2554 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
2555 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
2558 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
2559 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
2562 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
2563 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
2566 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
2567 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
2570 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
2571 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
2574 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
2575 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
2577 case ISD::FNEARBYINT:
2578 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
2579 RTLIB::NEARBYINT_F64,
2580 RTLIB::NEARBYINT_F80,
2581 RTLIB::NEARBYINT_PPCF128));
2584 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
2585 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
2588 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
2589 RTLIB::POW_F80, RTLIB::POW_PPCF128));
2592 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
2593 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
2596 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
2597 RTLIB::REM_F80, RTLIB::REM_PPCF128));
2599 case ISD::ConstantFP: {
2600 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
2601 // Check to see if this FP immediate is already legal.
2602 // If this is a legal constant, turn it into a TargetConstantFP node.
2603 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
2604 Results.push_back(SDValue(Node, 0));
2606 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
2609 case ISD::EHSELECTION: {
2610 unsigned Reg = TLI.getExceptionSelectorRegister();
2611 assert(Reg && "Can't expand to unknown register!");
2612 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
2613 Node->getValueType(0)));
2614 Results.push_back(Results[0].getValue(1));
2617 case ISD::EXCEPTIONADDR: {
2618 unsigned Reg = TLI.getExceptionAddressRegister();
2619 assert(Reg && "Can't expand to unknown register!");
2620 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
2621 Node->getValueType(0)));
2622 Results.push_back(Results[0].getValue(1));
2626 EVT VT = Node->getValueType(0);
2627 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
2628 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
2629 "Don't know how to expand this subtraction!");
2630 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
2631 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
2632 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
2633 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
2638 EVT VT = Node->getValueType(0);
2639 SDVTList VTs = DAG.getVTList(VT, VT);
2640 bool isSigned = Node->getOpcode() == ISD::SREM;
2641 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
2642 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2643 Tmp2 = Node->getOperand(0);
2644 Tmp3 = Node->getOperand(1);
2645 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
2646 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
2647 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
2649 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
2650 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
2651 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
2652 } else if (isSigned) {
2653 Tmp1 = ExpandIntLibCall(Node, true,
2655 RTLIB::SREM_I16, RTLIB::SREM_I32,
2656 RTLIB::SREM_I64, RTLIB::SREM_I128);
2658 Tmp1 = ExpandIntLibCall(Node, false,
2660 RTLIB::UREM_I16, RTLIB::UREM_I32,
2661 RTLIB::UREM_I64, RTLIB::UREM_I128);
2663 Results.push_back(Tmp1);
2668 bool isSigned = Node->getOpcode() == ISD::SDIV;
2669 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2670 EVT VT = Node->getValueType(0);
2671 SDVTList VTs = DAG.getVTList(VT, VT);
2672 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT))
2673 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
2674 Node->getOperand(1));
2676 Tmp1 = ExpandIntLibCall(Node, true,
2678 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
2679 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
2681 Tmp1 = ExpandIntLibCall(Node, false,
2683 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
2684 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
2685 Results.push_back(Tmp1);
2690 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
2692 EVT VT = Node->getValueType(0);
2693 SDVTList VTs = DAG.getVTList(VT, VT);
2694 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
2695 "If this wasn't legal, it shouldn't have been created!");
2696 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
2697 Node->getOperand(1));
2698 Results.push_back(Tmp1.getValue(1));
2702 EVT VT = Node->getValueType(0);
2703 SDVTList VTs = DAG.getVTList(VT, VT);
2704 // See if multiply or divide can be lowered using two-result operations.
2705 // We just need the low half of the multiply; try both the signed
2706 // and unsigned forms. If the target supports both SMUL_LOHI and
2707 // UMUL_LOHI, form a preference by checking which forms of plain
2708 // MULH it supports.
2709 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
2710 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
2711 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
2712 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
2713 unsigned OpToUse = 0;
2714 if (HasSMUL_LOHI && !HasMULHS) {
2715 OpToUse = ISD::SMUL_LOHI;
2716 } else if (HasUMUL_LOHI && !HasMULHU) {
2717 OpToUse = ISD::UMUL_LOHI;
2718 } else if (HasSMUL_LOHI) {
2719 OpToUse = ISD::SMUL_LOHI;
2720 } else if (HasUMUL_LOHI) {
2721 OpToUse = ISD::UMUL_LOHI;
2724 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
2725 Node->getOperand(1)));
2728 Tmp1 = ExpandIntLibCall(Node, false,
2730 RTLIB::MUL_I16, RTLIB::MUL_I32,
2731 RTLIB::MUL_I64, RTLIB::MUL_I128);
2732 Results.push_back(Tmp1);
2737 SDValue LHS = Node->getOperand(0);
2738 SDValue RHS = Node->getOperand(1);
2739 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2740 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2742 Results.push_back(Sum);
2743 EVT OType = Node->getValueType(1);
2745 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2747 // LHSSign -> LHS >= 0
2748 // RHSSign -> RHS >= 0
2749 // SumSign -> Sum >= 0
2752 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2754 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2756 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2757 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2758 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2759 Node->getOpcode() == ISD::SADDO ?
2760 ISD::SETEQ : ISD::SETNE);
2762 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2763 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2765 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2766 Results.push_back(Cmp);
2771 SDValue LHS = Node->getOperand(0);
2772 SDValue RHS = Node->getOperand(1);
2773 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
2774 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2776 Results.push_back(Sum);
2777 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
2778 Node->getOpcode () == ISD::UADDO ?
2779 ISD::SETULT : ISD::SETUGT));
2784 EVT VT = Node->getValueType(0);
2785 SDValue LHS = Node->getOperand(0);
2786 SDValue RHS = Node->getOperand(1);
2789 static const unsigned Ops[2][3] =
2790 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
2791 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
2792 bool isSigned = Node->getOpcode() == ISD::SMULO;
2793 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
2794 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
2795 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
2796 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
2797 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
2799 TopHalf = BottomHalf.getValue(1);
2800 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2))) {
2801 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
2802 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
2803 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
2804 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
2805 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
2806 DAG.getIntPtrConstant(0));
2807 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
2808 DAG.getIntPtrConstant(1));
2810 // FIXME: We should be able to fall back to a libcall with an illegal
2811 // type in some cases.
2812 // Also, we can fall back to a division in some cases, but that's a big
2813 // performance hit in the general case.
2814 llvm_unreachable("Don't know how to expand this operation yet!");
2817 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy());
2818 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
2819 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
2822 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
2823 DAG.getConstant(0, VT), ISD::SETNE);
2825 Results.push_back(BottomHalf);
2826 Results.push_back(TopHalf);
2829 case ISD::BUILD_PAIR: {
2830 EVT PairTy = Node->getValueType(0);
2831 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
2832 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
2833 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
2834 DAG.getConstant(PairTy.getSizeInBits()/2,
2835 TLI.getShiftAmountTy()));
2836 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
2840 Tmp1 = Node->getOperand(0);
2841 Tmp2 = Node->getOperand(1);
2842 Tmp3 = Node->getOperand(2);
2843 if (Tmp1.getOpcode() == ISD::SETCC) {
2844 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
2846 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2848 Tmp1 = DAG.getSelectCC(dl, Tmp1,
2849 DAG.getConstant(0, Tmp1.getValueType()),
2850 Tmp2, Tmp3, ISD::SETNE);
2852 Results.push_back(Tmp1);
2855 SDValue Chain = Node->getOperand(0);
2856 SDValue Table = Node->getOperand(1);
2857 SDValue Index = Node->getOperand(2);
2859 EVT PTy = TLI.getPointerTy();
2861 const TargetData &TD = *TLI.getTargetData();
2862 unsigned EntrySize =
2863 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
2865 Index = DAG.getNode(ISD::MUL, dl, PTy,
2866 Index, DAG.getConstant(EntrySize, PTy));
2867 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2869 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
2870 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
2871 PseudoSourceValue::getJumpTable(), 0, MemVT,
2874 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2875 // For PIC, the sequence is:
2876 // BRIND(load(Jumptable + index) + RelocBase)
2877 // RelocBase can be JumpTable, GOT or some sort of global base.
2878 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
2879 TLI.getPICJumpTableRelocBase(Table, DAG));
2881 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
2882 Results.push_back(Tmp1);
2886 // Expand brcond's setcc into its constituent parts and create a BR_CC
2888 Tmp1 = Node->getOperand(0);
2889 Tmp2 = Node->getOperand(1);
2890 if (Tmp2.getOpcode() == ISD::SETCC) {
2891 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
2892 Tmp1, Tmp2.getOperand(2),
2893 Tmp2.getOperand(0), Tmp2.getOperand(1),
2894 Node->getOperand(2));
2896 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
2897 DAG.getCondCode(ISD::SETNE), Tmp2,
2898 DAG.getConstant(0, Tmp2.getValueType()),
2899 Node->getOperand(2));
2901 Results.push_back(Tmp1);
2904 Tmp1 = Node->getOperand(0);
2905 Tmp2 = Node->getOperand(1);
2906 Tmp3 = Node->getOperand(2);
2907 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
2909 // If we expanded the SETCC into an AND/OR, return the new node
2910 if (Tmp2.getNode() == 0) {
2911 Results.push_back(Tmp1);
2915 // Otherwise, SETCC for the given comparison type must be completely
2916 // illegal; expand it into a SELECT_CC.
2917 EVT VT = Node->getValueType(0);
2918 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
2919 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
2920 Results.push_back(Tmp1);
2923 case ISD::SELECT_CC: {
2924 Tmp1 = Node->getOperand(0); // LHS
2925 Tmp2 = Node->getOperand(1); // RHS
2926 Tmp3 = Node->getOperand(2); // True
2927 Tmp4 = Node->getOperand(3); // False
2928 SDValue CC = Node->getOperand(4);
2930 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
2931 Tmp1, Tmp2, CC, dl);
2933 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
2934 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2935 CC = DAG.getCondCode(ISD::SETNE);
2936 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
2938 Results.push_back(Tmp1);
2942 Tmp1 = Node->getOperand(0); // Chain
2943 Tmp2 = Node->getOperand(2); // LHS
2944 Tmp3 = Node->getOperand(3); // RHS
2945 Tmp4 = Node->getOperand(1); // CC
2947 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
2948 Tmp2, Tmp3, Tmp4, dl);
2949 LastCALLSEQ_END = DAG.getEntryNode();
2951 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
2952 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2953 Tmp4 = DAG.getCondCode(ISD::SETNE);
2954 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
2955 Tmp3, Node->getOperand(4));
2956 Results.push_back(Tmp1);
2959 case ISD::GLOBAL_OFFSET_TABLE:
2960 case ISD::GlobalAddress:
2961 case ISD::GlobalTLSAddress:
2962 case ISD::ExternalSymbol:
2963 case ISD::ConstantPool:
2964 case ISD::JumpTable:
2965 case ISD::INTRINSIC_W_CHAIN:
2966 case ISD::INTRINSIC_WO_CHAIN:
2967 case ISD::INTRINSIC_VOID:
2968 // FIXME: Custom lowering for these operations shouldn't return null!
2969 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2970 Results.push_back(SDValue(Node, i));
2974 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
2975 SmallVectorImpl<SDValue> &Results) {
2976 EVT OVT = Node->getValueType(0);
2977 if (Node->getOpcode() == ISD::UINT_TO_FP ||
2978 Node->getOpcode() == ISD::SINT_TO_FP ||
2979 Node->getOpcode() == ISD::SETCC) {
2980 OVT = Node->getOperand(0).getValueType();
2982 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2983 DebugLoc dl = Node->getDebugLoc();
2984 SDValue Tmp1, Tmp2, Tmp3;
2985 switch (Node->getOpcode()) {
2989 // Zero extend the argument.
2990 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
2991 // Perform the larger operation.
2992 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
2993 if (Node->getOpcode() == ISD::CTTZ) {
2994 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2995 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
2996 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
2998 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
2999 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3000 } else if (Node->getOpcode() == ISD::CTLZ) {
3001 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3002 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3003 DAG.getConstant(NVT.getSizeInBits() -
3004 OVT.getSizeInBits(), NVT));
3006 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3009 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3010 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3011 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3012 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3013 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3014 Results.push_back(Tmp1);
3017 case ISD::FP_TO_UINT:
3018 case ISD::FP_TO_SINT:
3019 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3020 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3021 Results.push_back(Tmp1);
3023 case ISD::UINT_TO_FP:
3024 case ISD::SINT_TO_FP:
3025 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3026 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3027 Results.push_back(Tmp1);
3032 unsigned ExtOp, TruncOp;
3033 if (OVT.isVector()) {
3034 ExtOp = ISD::BIT_CONVERT;
3035 TruncOp = ISD::BIT_CONVERT;
3036 } else if (OVT.isInteger()) {
3037 ExtOp = ISD::ANY_EXTEND;
3038 TruncOp = ISD::TRUNCATE;
3040 llvm_report_error("Cannot promote logic operation");
3042 // Promote each of the values to the new type.
3043 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3044 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3045 // Perform the larger operation, then convert back
3046 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3047 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3051 unsigned ExtOp, TruncOp;
3052 if (Node->getValueType(0).isVector()) {
3053 ExtOp = ISD::BIT_CONVERT;
3054 TruncOp = ISD::BIT_CONVERT;
3055 } else if (Node->getValueType(0).isInteger()) {
3056 ExtOp = ISD::ANY_EXTEND;
3057 TruncOp = ISD::TRUNCATE;
3059 ExtOp = ISD::FP_EXTEND;
3060 TruncOp = ISD::FP_ROUND;
3062 Tmp1 = Node->getOperand(0);
3063 // Promote each of the values to the new type.
3064 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3065 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3066 // Perform the larger operation, then round down.
3067 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3068 if (TruncOp != ISD::FP_ROUND)
3069 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3071 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3072 DAG.getIntPtrConstant(0));
3073 Results.push_back(Tmp1);
3076 case ISD::VECTOR_SHUFFLE: {
3077 SmallVector<int, 8> Mask;
3078 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3080 // Cast the two input vectors.
3081 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
3082 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1));
3084 // Convert the shuffle mask to the right # elements.
3085 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3086 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1);
3087 Results.push_back(Tmp1);
3091 unsigned ExtOp = ISD::FP_EXTEND;
3092 if (NVT.isInteger()) {
3093 ISD::CondCode CCCode =
3094 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3095 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3097 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3098 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3099 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3100 Tmp1, Tmp2, Node->getOperand(2)));
3106 // SelectionDAG::Legalize - This is the entry point for the file.
3108 void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) {
3109 /// run - This is the main entry point to this class.
3111 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG();