1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/DwarfWriter.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetSubtarget.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/DerivedTypes.h"
31 #include "llvm/GlobalVariable.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/ADT/DenseMap.h"
36 #include "llvm/ADT/SmallVector.h"
37 #include "llvm/ADT/SmallPtrSet.h"
41 //===----------------------------------------------------------------------===//
42 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
43 /// hacks on it until the target machine can handle it. This involves
44 /// eliminating value sizes the machine cannot handle (promoting small sizes to
45 /// large sizes or splitting up large values into small values) as well as
46 /// eliminating operations the machine cannot handle.
48 /// This code also does a small amount of optimization and recognition of idioms
49 /// as part of its processing. For example, if a target does not support a
50 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
51 /// will attempt merge setcc and brc instructions into brcc's.
54 class VISIBILITY_HIDDEN SelectionDAGLegalize {
57 bool TypesNeedLegalizing;
59 // Libcall insertion helpers.
61 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
62 /// legalized. We use this to ensure that calls are properly serialized
63 /// against each other, including inserted libcalls.
64 SDValue LastCALLSEQ_END;
66 /// IsLegalizingCall - This member is used *only* for purposes of providing
67 /// helpful assertions that a libcall isn't created while another call is
68 /// being legalized (which could lead to non-serialized call sequences).
69 bool IsLegalizingCall;
72 Legal, // The target natively supports this operation.
73 Promote, // This operation should be executed in a larger type.
74 Expand // Try to expand this to other ops, otherwise use a libcall.
77 /// ValueTypeActions - This is a bitvector that contains two bits for each
78 /// value type, where the two bits correspond to the LegalizeAction enum.
79 /// This can be queried with "getTypeAction(VT)".
80 TargetLowering::ValueTypeActionImpl ValueTypeActions;
82 /// LegalizedNodes - For nodes that are of legal width, and that have more
83 /// than one use, this map indicates what regularized operand to use. This
84 /// allows us to avoid legalizing the same thing more than once.
85 DenseMap<SDValue, SDValue> LegalizedNodes;
87 /// PromotedNodes - For nodes that are below legal width, and that have more
88 /// than one use, this map indicates what promoted value to use. This allows
89 /// us to avoid promoting the same thing more than once.
90 DenseMap<SDValue, SDValue> PromotedNodes;
92 /// ExpandedNodes - For nodes that need to be expanded this map indicates
93 /// which operands are the expanded version of the input. This allows
94 /// us to avoid expanding the same node more than once.
95 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
97 /// SplitNodes - For vector nodes that need to be split, this map indicates
98 /// which operands are the split version of the input. This allows us
99 /// to avoid splitting the same node more than once.
100 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
102 /// ScalarizedNodes - For nodes that need to be converted from vector types to
103 /// scalar types, this contains the mapping of ones we have already
104 /// processed to the result.
105 std::map<SDValue, SDValue> ScalarizedNodes;
107 /// WidenNodes - For nodes that need to be widened from one vector type to
108 /// another, this contains the mapping of those that we have already widen.
109 /// This allows us to avoid widening more than once.
110 std::map<SDValue, SDValue> WidenNodes;
112 void AddLegalizedOperand(SDValue From, SDValue To) {
113 LegalizedNodes.insert(std::make_pair(From, To));
114 // If someone requests legalization of the new node, return itself.
116 LegalizedNodes.insert(std::make_pair(To, To));
118 void AddPromotedOperand(SDValue From, SDValue To) {
119 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
120 assert(isNew && "Got into the map somehow?");
122 // If someone requests legalization of the new node, return itself.
123 LegalizedNodes.insert(std::make_pair(To, To));
125 void AddWidenedOperand(SDValue From, SDValue To) {
126 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second;
127 assert(isNew && "Got into the map somehow?");
129 // If someone requests legalization of the new node, return itself.
130 LegalizedNodes.insert(std::make_pair(To, To));
134 explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing);
136 /// getTypeAction - Return how we should legalize values of this type, either
137 /// it is already legal or we need to expand it into multiple registers of
138 /// smaller integer type, or we need to promote it to a larger type.
139 LegalizeAction getTypeAction(MVT VT) const {
140 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
143 /// isTypeLegal - Return true if this type is legal on this target.
145 bool isTypeLegal(MVT VT) const {
146 return getTypeAction(VT) == Legal;
152 /// HandleOp - Legalize, Promote, or Expand the specified operand as
153 /// appropriate for its type.
154 void HandleOp(SDValue Op);
156 /// LegalizeOp - We know that the specified value has a legal type.
157 /// Recursively ensure that the operands have legal types, then return the
159 SDValue LegalizeOp(SDValue O);
161 /// UnrollVectorOp - We know that the given vector has a legal type, however
162 /// the operation it performs is not legal and is an operation that we have
163 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
164 /// operating on each element individually.
165 SDValue UnrollVectorOp(SDValue O);
167 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
168 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
169 /// is necessary to spill the vector being inserted into to memory, perform
170 /// the insert there, and then read the result back.
171 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
172 SDValue Idx, DebugLoc dl);
174 /// PromoteOp - Given an operation that produces a value in an invalid type,
175 /// promote it to compute the value into a larger type. The produced value
176 /// will have the correct bits for the low portion of the register, but no
177 /// guarantee is made about the top bits: it may be zero, sign-extended, or
179 SDValue PromoteOp(SDValue O);
181 /// ExpandOp - Expand the specified SDValue into its two component pieces
182 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
183 /// the LegalizedNodes map is filled in for any results that are not expanded,
184 /// the ExpandedNodes map is filled in for any results that are expanded, and
185 /// the Lo/Hi values are returned. This applies to integer types and Vector
187 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
189 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
190 /// (e.g., v3i32 to v4i32). The produced value will have the correct value
191 /// for the existing elements but no guarantee is made about the new elements
192 /// at the end of the vector: it may be zero, ones, or garbage. This is useful
193 /// when we have an instruction operating on an illegal vector type and we
194 /// want to widen it to do the computation on a legal wider vector type.
195 SDValue WidenVectorOp(SDValue Op, MVT WidenVT);
197 /// SplitVectorOp - Given an operand of vector type, break it down into
198 /// two smaller values.
199 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
201 /// ScalarizeVectorOp - Given an operand of single-element vector type
202 /// (e.g. v1f32), convert it into the equivalent operation that returns a
203 /// scalar (e.g. f32) value.
204 SDValue ScalarizeVectorOp(SDValue O);
206 /// Useful 16 element vector type that is used to pass operands for widening.
207 typedef SmallVector<SDValue, 16> SDValueVector;
209 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if
210 /// the LdChain contains a single load and false if it contains a token
211 /// factor for multiple loads. It takes
212 /// Result: location to return the result
213 /// LdChain: location to return the load chain
214 /// Op: load operation to widen
215 /// NVT: widen vector result type we want for the load
216 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
217 SDValue Op, MVT NVT);
219 /// Helper genWidenVectorLoads - Helper function to generate a set of
220 /// loads to load a vector with a resulting wider type. It takes
221 /// LdChain: list of chains for the load we have generated
222 /// Chain: incoming chain for the ld vector
223 /// BasePtr: base pointer to load from
224 /// SV: memory disambiguation source value
225 /// SVOffset: memory disambiugation offset
226 /// Alignment: alignment of the memory
227 /// isVolatile: volatile load
228 /// LdWidth: width of memory that we want to load
229 /// ResType: the wider result result type for the resulting loaded vector
230 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain,
231 SDValue BasePtr, const Value *SV,
232 int SVOffset, unsigned Alignment,
233 bool isVolatile, unsigned LdWidth,
234 MVT ResType, DebugLoc dl);
236 /// StoreWidenVectorOp - Stores a widen vector into non widen memory
237 /// location. It takes
238 /// ST: store node that we want to replace
239 /// Chain: incoming store chain
240 /// BasePtr: base address of where we want to store into
241 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
244 /// Helper genWidenVectorStores - Helper function to generate a set of
245 /// stores to store a widen vector into non widen memory
247 // StChain: list of chains for the stores we have generated
248 // Chain: incoming chain for the ld vector
249 // BasePtr: base pointer to load from
250 // SV: memory disambiguation source value
251 // SVOffset: memory disambiugation offset
252 // Alignment: alignment of the memory
253 // isVolatile: volatile lod
254 // ValOp: value to store
255 // StWidth: width of memory that we want to store
256 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain,
257 SDValue BasePtr, const Value *SV,
258 int SVOffset, unsigned Alignment,
259 bool isVolatile, SDValue ValOp,
260 unsigned StWidth, DebugLoc dl);
262 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
263 /// specified mask and type. Targets can specify exactly which masks they
264 /// support and the code generator is tasked with not creating illegal masks.
266 /// Note that this will also return true for shuffles that are promoted to a
269 /// If this is a legal shuffle, this method returns the (possibly promoted)
270 /// build_vector Mask. If it's not a legal shuffle, it returns null.
271 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
273 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
274 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
276 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC,
278 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
280 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
282 LegalizeSetCCOperands(LHS, RHS, CC, dl);
283 LegalizeSetCCCondCode(VT, LHS, RHS, CC, dl);
286 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
288 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl);
290 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl);
291 SDValue ExpandBUILD_VECTOR(SDNode *Node);
292 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
293 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy,
294 SDValue Op, DebugLoc dl);
295 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT,
297 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned,
299 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned,
302 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
303 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
304 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
305 SDValue &Lo, SDValue &Hi, DebugLoc dl);
306 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
307 SDValue &Lo, SDValue &Hi, DebugLoc dl);
309 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
310 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
314 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
315 /// specified mask and type. Targets can specify exactly which masks they
316 /// support and the code generator is tasked with not creating illegal masks.
318 /// Note that this will also return true for shuffles that are promoted to a
320 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
321 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
323 case TargetLowering::Legal:
324 case TargetLowering::Custom:
326 case TargetLowering::Promote: {
327 // If this is promoted to a different type, convert the shuffle mask and
328 // ask if it is legal in the promoted type!
329 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
330 MVT EltVT = NVT.getVectorElementType();
332 // If we changed # elements, change the shuffle mask.
333 unsigned NumEltsGrowth =
334 NVT.getVectorNumElements() / VT.getVectorNumElements();
335 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
336 if (NumEltsGrowth > 1) {
337 // Renumber the elements.
338 SmallVector<SDValue, 8> Ops;
339 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
340 SDValue InOp = Mask.getOperand(i);
341 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
342 if (InOp.getOpcode() == ISD::UNDEF)
343 Ops.push_back(DAG.getNode(ISD::UNDEF,
344 InOp.getNode()->getDebugLoc(), EltVT));
346 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
347 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
351 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getNode()->getDebugLoc(),
352 NVT, &Ops[0], Ops.size());
358 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
361 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, bool types)
362 : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types),
363 ValueTypeActions(TLI.getValueTypeActions()) {
364 assert(MVT::LAST_VALUETYPE <= 32 &&
365 "Too many value types for ValueTypeActions to hold!");
368 void SelectionDAGLegalize::LegalizeDAG() {
369 LastCALLSEQ_END = DAG.getEntryNode();
370 IsLegalizingCall = false;
372 // The legalize process is inherently a bottom-up recursive process (users
373 // legalize their uses before themselves). Given infinite stack space, we
374 // could just start legalizing on the root and traverse the whole graph. In
375 // practice however, this causes us to run out of stack space on large basic
376 // blocks. To avoid this problem, compute an ordering of the nodes where each
377 // node is only legalized after all of its operands are legalized.
378 DAG.AssignTopologicalOrder();
379 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
380 E = prior(DAG.allnodes_end()); I != next(E); ++I)
381 HandleOp(SDValue(I, 0));
383 // Finally, it's possible the root changed. Get the new root.
384 SDValue OldRoot = DAG.getRoot();
385 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
386 DAG.setRoot(LegalizedNodes[OldRoot]);
388 ExpandedNodes.clear();
389 LegalizedNodes.clear();
390 PromotedNodes.clear();
392 ScalarizedNodes.clear();
395 // Remove dead nodes now.
396 DAG.RemoveDeadNodes();
400 /// FindCallEndFromCallStart - Given a chained node that is part of a call
401 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
402 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
403 if (Node->getOpcode() == ISD::CALLSEQ_END)
405 if (Node->use_empty())
406 return 0; // No CallSeqEnd
408 // The chain is usually at the end.
409 SDValue TheChain(Node, Node->getNumValues()-1);
410 if (TheChain.getValueType() != MVT::Other) {
411 // Sometimes it's at the beginning.
412 TheChain = SDValue(Node, 0);
413 if (TheChain.getValueType() != MVT::Other) {
414 // Otherwise, hunt for it.
415 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
416 if (Node->getValueType(i) == MVT::Other) {
417 TheChain = SDValue(Node, i);
421 // Otherwise, we walked into a node without a chain.
422 if (TheChain.getValueType() != MVT::Other)
427 for (SDNode::use_iterator UI = Node->use_begin(),
428 E = Node->use_end(); UI != E; ++UI) {
430 // Make sure to only follow users of our token chain.
432 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
433 if (User->getOperand(i) == TheChain)
434 if (SDNode *Result = FindCallEndFromCallStart(User))
440 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
441 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
442 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
443 assert(Node && "Didn't find callseq_start for a call??");
444 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
446 assert(Node->getOperand(0).getValueType() == MVT::Other &&
447 "Node doesn't have a token chain argument!");
448 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
451 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
452 /// see if any uses can reach Dest. If no dest operands can get to dest,
453 /// legalize them, legalize ourself, and return false, otherwise, return true.
455 /// Keep track of the nodes we fine that actually do lead to Dest in
456 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
458 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
459 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
460 if (N == Dest) return true; // N certainly leads to Dest :)
462 // If we've already processed this node and it does lead to Dest, there is no
463 // need to reprocess it.
464 if (NodesLeadingTo.count(N)) return true;
466 // If the first result of this node has been already legalized, then it cannot
468 switch (getTypeAction(N->getValueType(0))) {
470 if (LegalizedNodes.count(SDValue(N, 0))) return false;
473 if (PromotedNodes.count(SDValue(N, 0))) return false;
476 if (ExpandedNodes.count(SDValue(N, 0))) return false;
480 // Okay, this node has not already been legalized. Check and legalize all
481 // operands. If none lead to Dest, then we can legalize this node.
482 bool OperandsLeadToDest = false;
483 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
484 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
485 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
487 if (OperandsLeadToDest) {
488 NodesLeadingTo.insert(N);
492 // Okay, this node looks safe, legalize it and return false.
493 HandleOp(SDValue(N, 0));
497 /// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as
498 /// appropriate for its type.
499 void SelectionDAGLegalize::HandleOp(SDValue Op) {
500 MVT VT = Op.getValueType();
501 // If the type legalizer was run then we should never see any illegal result
502 // types here except for target constants (the type legalizer does not touch
503 // those) or for build vector used as a mask for a vector shuffle.
504 // FIXME: We can removed the BUILD_VECTOR case when we fix PR2957.
505 assert((TypesNeedLegalizing || getTypeAction(VT) == Legal ||
506 Op.getOpcode() == ISD::TargetConstant ||
507 Op.getOpcode() == ISD::BUILD_VECTOR) &&
508 "Illegal type introduced after type legalization?");
509 switch (getTypeAction(VT)) {
510 default: assert(0 && "Bad type action!");
511 case Legal: (void)LegalizeOp(Op); break;
513 if (!VT.isVector()) {
518 // See if we can widen otherwise use Expand to either scalarize or split
519 MVT WidenVT = TLI.getWidenVectorType(VT);
520 if (WidenVT != MVT::Other) {
521 (void) WidenVectorOp(Op, WidenVT);
524 // else fall thru to expand since we can't widen the vector
527 if (!VT.isVector()) {
528 // If this is an illegal scalar, expand it into its two component
531 if (Op.getOpcode() == ISD::TargetConstant)
532 break; // Allow illegal target nodes.
534 } else if (VT.getVectorNumElements() == 1) {
535 // If this is an illegal single element vector, convert it to a
537 (void)ScalarizeVectorOp(Op);
539 // This is an illegal multiple element vector.
540 // Split it in half and legalize both parts.
542 SplitVectorOp(Op, X, Y);
548 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
549 /// a load from the constant pool.
550 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
551 SelectionDAG &DAG, const TargetLowering &TLI) {
554 // If a FP immediate is precise when represented as a float and if the
555 // target can do an extending load from float to double, we put it into
556 // the constant pool as a float, even if it's is statically typed as a
557 // double. This shrinks FP constants and canonicalizes them for targets where
558 // an FP extending load is the same cost as a normal load (such as on the x87
559 // fp stack or PPC FP unit).
560 MVT VT = CFP->getValueType(0);
561 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
563 if (VT!=MVT::f64 && VT!=MVT::f32)
564 assert(0 && "Invalid type expansion");
565 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
566 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
571 while (SVT != MVT::f32) {
572 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
573 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
574 // Only do this if the target has a native EXTLOAD instruction from
576 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
577 TLI.ShouldShrinkFPConstant(OrigVT)) {
578 const Type *SType = SVT.getTypeForMVT();
579 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
585 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
586 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
588 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
589 CPIdx, PseudoSourceValue::getConstantPool(),
590 0, VT, false, Alignment);
591 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
592 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
596 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
599 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
601 const TargetLowering &TLI) {
602 DebugLoc dl = Node->getDebugLoc();
603 MVT VT = Node->getValueType(0);
604 MVT SrcVT = Node->getOperand(1).getValueType();
605 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
606 "fcopysign expansion only supported for f32 and f64");
607 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
609 // First get the sign bit of second operand.
610 SDValue Mask1 = (SrcVT == MVT::f64)
611 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
612 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
613 Mask1 = DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT, Mask1);
614 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT,
615 Node->getOperand(1));
616 SignBit = DAG.getNode(ISD::AND, dl, SrcNVT, SignBit, Mask1);
617 // Shift right or sign-extend it if the two operands have different types.
618 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
620 SignBit = DAG.getNode(ISD::SRL, dl, SrcNVT, SignBit,
621 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
622 SignBit = DAG.getNode(ISD::TRUNCATE, dl, NVT, SignBit);
623 } else if (SizeDiff < 0) {
624 SignBit = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, SignBit);
625 SignBit = DAG.getNode(ISD::SHL, dl, NVT, SignBit,
626 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
629 // Clear the sign bit of first operand.
630 SDValue Mask2 = (VT == MVT::f64)
631 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
632 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
633 Mask2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask2);
634 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
635 Result = DAG.getNode(ISD::AND, dl, NVT, Result, Mask2);
637 // Or the value with the sign bit.
638 Result = DAG.getNode(ISD::OR, dl, NVT, Result, SignBit);
642 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
644 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
645 const TargetLowering &TLI) {
646 SDValue Chain = ST->getChain();
647 SDValue Ptr = ST->getBasePtr();
648 SDValue Val = ST->getValue();
649 MVT VT = Val.getValueType();
650 int Alignment = ST->getAlignment();
651 int SVOffset = ST->getSrcValueOffset();
652 DebugLoc dl = ST->getDebugLoc();
653 if (ST->getMemoryVT().isFloatingPoint() ||
654 ST->getMemoryVT().isVector()) {
655 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
656 if (TLI.isTypeLegal(intVT)) {
657 // Expand to a bitconvert of the value to the integer type of the
658 // same size, then a (misaligned) int store.
659 // FIXME: Does not handle truncating floating point stores!
660 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
661 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
662 SVOffset, ST->isVolatile(), Alignment);
664 // Do a (aligned) store to a stack slot, then copy from the stack slot
665 // to the final destination using (unaligned) integer loads and stores.
666 MVT StoredVT = ST->getMemoryVT();
668 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
669 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
670 unsigned RegBytes = RegVT.getSizeInBits() / 8;
671 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
673 // Make sure the stack slot is also aligned for the register type.
674 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
676 // Perform the original store, only redirected to the stack slot.
677 SDValue Store = DAG.getTruncStore(Chain, dl,
678 Val, StackPtr, NULL, 0,StoredVT);
679 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
680 SmallVector<SDValue, 8> Stores;
683 // Do all but one copies using the full register width.
684 for (unsigned i = 1; i < NumRegs; i++) {
685 // Load one integer register's worth from the stack slot.
686 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0);
687 // Store it to the final location. Remember the store.
688 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
689 ST->getSrcValue(), SVOffset + Offset,
691 MinAlign(ST->getAlignment(), Offset)));
692 // Increment the pointers.
694 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
696 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
699 // The last store may be partial. Do a truncating store. On big-endian
700 // machines this requires an extending load from the stack slot to ensure
701 // that the bits are in the right place.
702 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
704 // Load from the stack slot.
705 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
708 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
709 ST->getSrcValue(), SVOffset + Offset,
710 MemVT, ST->isVolatile(),
711 MinAlign(ST->getAlignment(), Offset)));
712 // The order of the stores doesn't matter - say it with a TokenFactor.
713 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
717 assert(ST->getMemoryVT().isInteger() &&
718 !ST->getMemoryVT().isVector() &&
719 "Unaligned store of unknown type.");
720 // Get the half-size VT
722 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
723 int NumBits = NewStoredVT.getSizeInBits();
724 int IncrementSize = NumBits / 8;
726 // Divide the stored value in two parts.
727 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
729 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
731 // Store the two parts
732 SDValue Store1, Store2;
733 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
734 ST->getSrcValue(), SVOffset, NewStoredVT,
735 ST->isVolatile(), Alignment);
736 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
737 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
738 Alignment = MinAlign(Alignment, IncrementSize);
739 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
740 ST->getSrcValue(), SVOffset + IncrementSize,
741 NewStoredVT, ST->isVolatile(), Alignment);
743 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
746 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
748 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
749 const TargetLowering &TLI) {
750 int SVOffset = LD->getSrcValueOffset();
751 SDValue Chain = LD->getChain();
752 SDValue Ptr = LD->getBasePtr();
753 MVT VT = LD->getValueType(0);
754 MVT LoadedVT = LD->getMemoryVT();
755 DebugLoc dl = LD->getDebugLoc();
756 if (VT.isFloatingPoint() || VT.isVector()) {
757 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
758 if (TLI.isTypeLegal(intVT)) {
759 // Expand to a (misaligned) integer load of the same size,
760 // then bitconvert to floating point or vector.
761 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
762 SVOffset, LD->isVolatile(),
764 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
765 if (VT.isFloatingPoint() && LoadedVT != VT)
766 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
768 SDValue Ops[] = { Result, Chain };
769 return DAG.getMergeValues(Ops, 2, dl);
771 // Copy the value to a (aligned) stack slot using (unaligned) integer
772 // loads and stores, then do a (aligned) load from the stack slot.
773 MVT RegVT = TLI.getRegisterType(intVT);
774 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
775 unsigned RegBytes = RegVT.getSizeInBits() / 8;
776 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
778 // Make sure the stack slot is also aligned for the register type.
779 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
781 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
782 SmallVector<SDValue, 8> Stores;
783 SDValue StackPtr = StackBase;
786 // Do all but one copies using the full register width.
787 for (unsigned i = 1; i < NumRegs; i++) {
788 // Load one integer register's worth from the original location.
789 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
790 SVOffset + Offset, LD->isVolatile(),
791 MinAlign(LD->getAlignment(), Offset));
792 // Follow the load with a store to the stack slot. Remember the store.
793 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
795 // Increment the pointers.
797 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
798 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
802 // The last copy may be partial. Do an extending load.
803 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
804 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
805 LD->getSrcValue(), SVOffset + Offset,
806 MemVT, LD->isVolatile(),
807 MinAlign(LD->getAlignment(), Offset));
808 // Follow the load with a store to the stack slot. Remember the store.
809 // On big-endian machines this requires a truncating store to ensure
810 // that the bits end up in the right place.
811 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
814 // The order of the stores doesn't matter - say it with a TokenFactor.
815 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
818 // Finally, perform the original load only redirected to the stack slot.
819 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
822 // Callers expect a MERGE_VALUES node.
823 SDValue Ops[] = { Load, TF };
824 return DAG.getMergeValues(Ops, 2, dl);
827 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
828 "Unaligned load of unsupported type.");
830 // Compute the new VT that is half the size of the old one. This is an
832 unsigned NumBits = LoadedVT.getSizeInBits();
834 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
837 unsigned Alignment = LD->getAlignment();
838 unsigned IncrementSize = NumBits / 8;
839 ISD::LoadExtType HiExtType = LD->getExtensionType();
841 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
842 if (HiExtType == ISD::NON_EXTLOAD)
843 HiExtType = ISD::ZEXTLOAD;
845 // Load the value in two parts
847 if (TLI.isLittleEndian()) {
848 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
849 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
850 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
851 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
852 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
853 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
854 MinAlign(Alignment, IncrementSize));
856 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
857 SVOffset, NewLoadedVT,LD->isVolatile(), Alignment);
858 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
859 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
860 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
861 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
862 MinAlign(Alignment, IncrementSize));
865 // aggregate the two parts
866 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
867 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
868 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
870 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
873 SDValue Ops[] = { Result, TF };
874 return DAG.getMergeValues(Ops, 2, dl);
877 /// UnrollVectorOp - We know that the given vector has a legal type, however
878 /// the operation it performs is not legal and is an operation that we have
879 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
880 /// operating on each element individually.
881 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
882 MVT VT = Op.getValueType();
883 assert(isTypeLegal(VT) &&
884 "Caller should expand or promote operands that are not legal!");
885 assert(Op.getNode()->getNumValues() == 1 &&
886 "Can't unroll a vector with multiple results!");
887 unsigned NE = VT.getVectorNumElements();
888 MVT EltVT = VT.getVectorElementType();
889 DebugLoc dl = Op.getNode()->getDebugLoc();
891 SmallVector<SDValue, 8> Scalars;
892 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
893 for (unsigned i = 0; i != NE; ++i) {
894 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
895 SDValue Operand = Op.getOperand(j);
896 MVT OperandVT = Operand.getValueType();
897 if (OperandVT.isVector()) {
898 // A vector operand; extract a single element.
899 MVT OperandEltVT = OperandVT.getVectorElementType();
900 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
903 DAG.getConstant(i, MVT::i32));
905 // A scalar operand; just use it as is.
906 Operands[j] = Operand;
910 switch (Op.getOpcode()) {
912 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT,
913 &Operands[0], Operands.size()));
920 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, Operands[0],
921 DAG.getShiftAmountOperand(Operands[1])));
926 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Scalars[0], Scalars.size());
929 /// GetFPLibCall - Return the right libcall for the given floating point type.
930 static RTLIB::Libcall GetFPLibCall(MVT VT,
931 RTLIB::Libcall Call_F32,
932 RTLIB::Libcall Call_F64,
933 RTLIB::Libcall Call_F80,
934 RTLIB::Libcall Call_PPCF128) {
936 VT == MVT::f32 ? Call_F32 :
937 VT == MVT::f64 ? Call_F64 :
938 VT == MVT::f80 ? Call_F80 :
939 VT == MVT::ppcf128 ? Call_PPCF128 :
940 RTLIB::UNKNOWN_LIBCALL;
943 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
944 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
945 /// is necessary to spill the vector being inserted into to memory, perform
946 /// the insert there, and then read the result back.
947 SDValue SelectionDAGLegalize::
948 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
954 // If the target doesn't support this, we have to spill the input vector
955 // to a temporary stack slot, update the element, then reload it. This is
956 // badness. We could also load the value into a vector register (either
957 // with a "move to register" or "extload into register" instruction, then
958 // permute it into place, if the idx is a constant and if the idx is
959 // supported by the target.
960 MVT VT = Tmp1.getValueType();
961 MVT EltVT = VT.getVectorElementType();
962 MVT IdxVT = Tmp3.getValueType();
963 MVT PtrVT = TLI.getPointerTy();
964 SDValue StackPtr = DAG.CreateStackTemporary(VT);
966 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
969 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
970 PseudoSourceValue::getFixedStack(SPFI), 0);
972 // Truncate or zero extend offset to target pointer type.
973 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
974 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
975 // Add the offset to the index.
976 unsigned EltSize = EltVT.getSizeInBits()/8;
977 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
978 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
979 // Store the scalar value.
980 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
981 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
982 // Load the updated vector.
983 return DAG.getLoad(VT, dl, Ch, StackPtr,
984 PseudoSourceValue::getFixedStack(SPFI), 0);
988 /// LegalizeOp - We know that the specified value has a legal type, and
989 /// that its operands are legal. Now ensure that the operation itself
990 /// is legal, recursively ensuring that the operands' operations remain
992 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
993 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
996 assert(isTypeLegal(Op.getValueType()) &&
997 "Caller should expand or promote operands that are not legal!");
998 SDNode *Node = Op.getNode();
999 DebugLoc dl = Node->getDebugLoc();
1001 // If this operation defines any values that cannot be represented in a
1002 // register on this target, make sure to expand or promote them.
1003 if (Node->getNumValues() > 1) {
1004 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1005 if (getTypeAction(Node->getValueType(i)) != Legal) {
1006 HandleOp(Op.getValue(i));
1007 assert(LegalizedNodes.count(Op) &&
1008 "Handling didn't add legal operands!");
1009 return LegalizedNodes[Op];
1013 // Note that LegalizeOp may be reentered even from single-use nodes, which
1014 // means that we always must cache transformed nodes.
1015 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1016 if (I != LegalizedNodes.end()) return I->second;
1018 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
1019 SDValue Result = Op;
1020 bool isCustom = false;
1022 switch (Node->getOpcode()) {
1023 case ISD::FrameIndex:
1024 case ISD::EntryToken:
1026 case ISD::BasicBlock:
1027 case ISD::TargetFrameIndex:
1028 case ISD::TargetJumpTable:
1029 case ISD::TargetConstant:
1030 case ISD::TargetConstantFP:
1031 case ISD::TargetConstantPool:
1032 case ISD::TargetGlobalAddress:
1033 case ISD::TargetGlobalTLSAddress:
1034 case ISD::TargetExternalSymbol:
1035 case ISD::VALUETYPE:
1037 case ISD::MEMOPERAND:
1039 case ISD::ARG_FLAGS:
1040 // Primitives must all be legal.
1041 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
1042 "This must be legal!");
1045 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1046 // If this is a target node, legalize it by legalizing the operands then
1047 // passing it through.
1048 SmallVector<SDValue, 8> Ops;
1049 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1050 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1052 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
1054 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1055 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
1056 return Result.getValue(Op.getResNo());
1058 // Otherwise this is an unhandled builtin node. splat.
1060 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
1062 assert(0 && "Do not know how to legalize this operator!");
1064 case ISD::GLOBAL_OFFSET_TABLE:
1065 case ISD::GlobalAddress:
1066 case ISD::GlobalTLSAddress:
1067 case ISD::ExternalSymbol:
1068 case ISD::ConstantPool:
1069 case ISD::JumpTable: // Nothing to do.
1070 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1071 default: assert(0 && "This action is not supported yet!");
1072 case TargetLowering::Custom:
1073 Tmp1 = TLI.LowerOperation(Op, DAG);
1074 if (Tmp1.getNode()) Result = Tmp1;
1075 // FALLTHROUGH if the target doesn't want to lower this op after all.
1076 case TargetLowering::Legal:
1080 case ISD::FRAMEADDR:
1081 case ISD::RETURNADDR:
1082 // The only option for these nodes is to custom lower them. If the target
1083 // does not custom lower them, then return zero.
1084 Tmp1 = TLI.LowerOperation(Op, DAG);
1088 Result = DAG.getConstant(0, TLI.getPointerTy());
1090 case ISD::FRAME_TO_ARGS_OFFSET: {
1091 MVT VT = Node->getValueType(0);
1092 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1093 default: assert(0 && "This action is not supported yet!");
1094 case TargetLowering::Custom:
1095 Result = TLI.LowerOperation(Op, DAG);
1096 if (Result.getNode()) break;
1098 case TargetLowering::Legal:
1099 Result = DAG.getConstant(0, VT);
1104 case ISD::EXCEPTIONADDR: {
1105 Tmp1 = LegalizeOp(Node->getOperand(0));
1106 MVT VT = Node->getValueType(0);
1107 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1108 default: assert(0 && "This action is not supported yet!");
1109 case TargetLowering::Expand: {
1110 unsigned Reg = TLI.getExceptionAddressRegister();
1111 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
1114 case TargetLowering::Custom:
1115 Result = TLI.LowerOperation(Op, DAG);
1116 if (Result.getNode()) break;
1118 case TargetLowering::Legal: {
1119 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
1120 Result = DAG.getMergeValues(Ops, 2);
1125 if (Result.getNode()->getNumValues() == 1) break;
1127 assert(Result.getNode()->getNumValues() == 2 &&
1128 "Cannot return more than two values!");
1130 // Since we produced two values, make sure to remember that we
1131 // legalized both of them.
1132 Tmp1 = LegalizeOp(Result);
1133 Tmp2 = LegalizeOp(Result.getValue(1));
1134 AddLegalizedOperand(Op.getValue(0), Tmp1);
1135 AddLegalizedOperand(Op.getValue(1), Tmp2);
1136 return Op.getResNo() ? Tmp2 : Tmp1;
1137 case ISD::EHSELECTION: {
1138 Tmp1 = LegalizeOp(Node->getOperand(0));
1139 Tmp2 = LegalizeOp(Node->getOperand(1));
1140 MVT VT = Node->getValueType(0);
1141 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1142 default: assert(0 && "This action is not supported yet!");
1143 case TargetLowering::Expand: {
1144 unsigned Reg = TLI.getExceptionSelectorRegister();
1145 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
1148 case TargetLowering::Custom:
1149 Result = TLI.LowerOperation(Op, DAG);
1150 if (Result.getNode()) break;
1152 case TargetLowering::Legal: {
1153 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
1154 Result = DAG.getMergeValues(Ops, 2);
1159 if (Result.getNode()->getNumValues() == 1) break;
1161 assert(Result.getNode()->getNumValues() == 2 &&
1162 "Cannot return more than two values!");
1164 // Since we produced two values, make sure to remember that we
1165 // legalized both of them.
1166 Tmp1 = LegalizeOp(Result);
1167 Tmp2 = LegalizeOp(Result.getValue(1));
1168 AddLegalizedOperand(Op.getValue(0), Tmp1);
1169 AddLegalizedOperand(Op.getValue(1), Tmp2);
1170 return Op.getResNo() ? Tmp2 : Tmp1;
1171 case ISD::EH_RETURN: {
1172 MVT VT = Node->getValueType(0);
1173 // The only "good" option for this node is to custom lower it.
1174 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1175 default: assert(0 && "This action is not supported at all!");
1176 case TargetLowering::Custom:
1177 Result = TLI.LowerOperation(Op, DAG);
1178 if (Result.getNode()) break;
1180 case TargetLowering::Legal:
1181 // Target does not know, how to lower this, lower to noop
1182 Result = LegalizeOp(Node->getOperand(0));
1187 case ISD::AssertSext:
1188 case ISD::AssertZext:
1189 Tmp1 = LegalizeOp(Node->getOperand(0));
1190 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1192 case ISD::MERGE_VALUES:
1193 // Legalize eliminates MERGE_VALUES nodes.
1194 Result = Node->getOperand(Op.getResNo());
1196 case ISD::CopyFromReg:
1197 Tmp1 = LegalizeOp(Node->getOperand(0));
1198 Result = Op.getValue(0);
1199 if (Node->getNumValues() == 2) {
1200 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1202 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1203 if (Node->getNumOperands() == 3) {
1204 Tmp2 = LegalizeOp(Node->getOperand(2));
1205 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1207 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1209 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1211 // Since CopyFromReg produces two values, make sure to remember that we
1212 // legalized both of them.
1213 AddLegalizedOperand(Op.getValue(0), Result);
1214 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1215 return Result.getValue(Op.getResNo());
1217 MVT VT = Op.getValueType();
1218 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1219 default: assert(0 && "This action is not supported yet!");
1220 case TargetLowering::Expand:
1222 Result = DAG.getConstant(0, VT);
1223 else if (VT.isFloatingPoint())
1224 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1227 assert(0 && "Unknown value type!");
1229 case TargetLowering::Legal:
1235 case ISD::INTRINSIC_W_CHAIN:
1236 case ISD::INTRINSIC_WO_CHAIN:
1237 case ISD::INTRINSIC_VOID: {
1238 SmallVector<SDValue, 8> Ops;
1239 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1240 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1241 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1243 // Allow the target to custom lower its intrinsics if it wants to.
1244 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1245 TargetLowering::Custom) {
1246 Tmp3 = TLI.LowerOperation(Result, DAG);
1247 if (Tmp3.getNode()) Result = Tmp3;
1250 if (Result.getNode()->getNumValues() == 1) break;
1252 // Must have return value and chain result.
1253 assert(Result.getNode()->getNumValues() == 2 &&
1254 "Cannot return more than two values!");
1256 // Since loads produce two values, make sure to remember that we
1257 // legalized both of them.
1258 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1259 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1260 return Result.getValue(Op.getResNo());
1263 case ISD::DBG_STOPPOINT:
1264 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1265 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1267 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1268 case TargetLowering::Promote:
1269 default: assert(0 && "This action is not supported yet!");
1270 case TargetLowering::Expand: {
1271 DwarfWriter *DW = DAG.getDwarfWriter();
1272 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
1274 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
1276 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1277 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
1278 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) {
1279 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit()));
1280 unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
1283 unsigned Line = DSP->getLine();
1284 unsigned Col = DSP->getColumn();
1287 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1288 DAG.getConstant(Col, MVT::i32),
1289 DAG.getConstant(SrcFile, MVT::i32) };
1290 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
1292 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile);
1293 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1296 Result = Tmp1; // chain
1300 case TargetLowering::Legal: {
1301 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1302 if (Action == Legal && Tmp1 == Node->getOperand(0))
1305 SmallVector<SDValue, 8> Ops;
1306 Ops.push_back(Tmp1);
1307 if (Action == Legal) {
1308 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1309 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1311 // Otherwise promote them.
1312 Ops.push_back(PromoteOp(Node->getOperand(1)));
1313 Ops.push_back(PromoteOp(Node->getOperand(2)));
1315 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1316 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1317 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1324 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1325 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1326 default: assert(0 && "This action is not supported yet!");
1327 case TargetLowering::Legal:
1328 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1329 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1330 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1331 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1333 case TargetLowering::Expand:
1334 Result = LegalizeOp(Node->getOperand(0));
1339 case ISD::DEBUG_LOC:
1340 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1341 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1342 default: assert(0 && "This action is not supported yet!");
1343 case TargetLowering::Legal: {
1344 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1345 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1346 if (Action == Legal && Tmp1 == Node->getOperand(0))
1348 if (Action == Legal) {
1349 Tmp2 = Node->getOperand(1);
1350 Tmp3 = Node->getOperand(2);
1351 Tmp4 = Node->getOperand(3);
1353 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1354 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1355 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1357 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1363 case ISD::DBG_LABEL:
1365 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1366 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1367 default: assert(0 && "This action is not supported yet!");
1368 case TargetLowering::Legal:
1369 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1370 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1372 case TargetLowering::Expand:
1373 Result = LegalizeOp(Node->getOperand(0));
1379 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1380 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1381 default: assert(0 && "This action is not supported yet!");
1382 case TargetLowering::Legal:
1383 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1384 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1385 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1386 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1387 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1389 case TargetLowering::Expand:
1391 Result = LegalizeOp(Node->getOperand(0));
1396 case ISD::MEMBARRIER: {
1397 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1398 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1399 default: assert(0 && "This action is not supported yet!");
1400 case TargetLowering::Legal: {
1402 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1403 for (int x = 1; x < 6; ++x) {
1404 Ops[x] = Node->getOperand(x);
1405 if (!isTypeLegal(Ops[x].getValueType()))
1406 Ops[x] = PromoteOp(Ops[x]);
1408 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1411 case TargetLowering::Expand:
1412 //There is no libgcc call for this op
1413 Result = Node->getOperand(0); // Noop
1419 case ISD::ATOMIC_CMP_SWAP: {
1420 unsigned int num_operands = 4;
1421 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1423 for (unsigned int x = 0; x < num_operands; ++x)
1424 Ops[x] = LegalizeOp(Node->getOperand(x));
1425 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1427 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1428 default: assert(0 && "This action is not supported yet!");
1429 case TargetLowering::Custom:
1430 Result = TLI.LowerOperation(Result, DAG);
1432 case TargetLowering::Legal:
1435 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1436 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1437 return Result.getValue(Op.getResNo());
1439 case ISD::ATOMIC_LOAD_ADD:
1440 case ISD::ATOMIC_LOAD_SUB:
1441 case ISD::ATOMIC_LOAD_AND:
1442 case ISD::ATOMIC_LOAD_OR:
1443 case ISD::ATOMIC_LOAD_XOR:
1444 case ISD::ATOMIC_LOAD_NAND:
1445 case ISD::ATOMIC_LOAD_MIN:
1446 case ISD::ATOMIC_LOAD_MAX:
1447 case ISD::ATOMIC_LOAD_UMIN:
1448 case ISD::ATOMIC_LOAD_UMAX:
1449 case ISD::ATOMIC_SWAP: {
1450 unsigned int num_operands = 3;
1451 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1453 for (unsigned int x = 0; x < num_operands; ++x)
1454 Ops[x] = LegalizeOp(Node->getOperand(x));
1455 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1457 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1458 default: assert(0 && "This action is not supported yet!");
1459 case TargetLowering::Custom:
1460 Result = TLI.LowerOperation(Result, DAG);
1462 case TargetLowering::Legal:
1465 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1466 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1467 return Result.getValue(Op.getResNo());
1469 case ISD::Constant: {
1470 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1472 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1474 // We know we don't need to expand constants here, constants only have one
1475 // value and we check that it is fine above.
1477 if (opAction == TargetLowering::Custom) {
1478 Tmp1 = TLI.LowerOperation(Result, DAG);
1484 case ISD::ConstantFP: {
1485 // Spill FP immediates to the constant pool if the target cannot directly
1486 // codegen them. Targets often have some immediate values that can be
1487 // efficiently generated into an FP register without a load. We explicitly
1488 // leave these constants as ConstantFP nodes for the target to deal with.
1489 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1491 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1492 default: assert(0 && "This action is not supported yet!");
1493 case TargetLowering::Legal:
1495 case TargetLowering::Custom:
1496 Tmp3 = TLI.LowerOperation(Result, DAG);
1497 if (Tmp3.getNode()) {
1502 case TargetLowering::Expand: {
1503 // Check to see if this FP immediate is already legal.
1504 bool isLegal = false;
1505 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1506 E = TLI.legal_fpimm_end(); I != E; ++I) {
1507 if (CFP->isExactlyValue(*I)) {
1512 // If this is a legal constant, turn it into a TargetConstantFP node.
1515 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1520 case ISD::TokenFactor:
1521 if (Node->getNumOperands() == 2) {
1522 Tmp1 = LegalizeOp(Node->getOperand(0));
1523 Tmp2 = LegalizeOp(Node->getOperand(1));
1524 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1525 } else if (Node->getNumOperands() == 3) {
1526 Tmp1 = LegalizeOp(Node->getOperand(0));
1527 Tmp2 = LegalizeOp(Node->getOperand(1));
1528 Tmp3 = LegalizeOp(Node->getOperand(2));
1529 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1531 SmallVector<SDValue, 8> Ops;
1532 // Legalize the operands.
1533 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1534 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1535 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1539 case ISD::FORMAL_ARGUMENTS:
1541 // The only option for this is to custom lower it.
1542 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1543 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1544 // A call within a calling sequence must be legalized to something
1545 // other than the normal CALLSEQ_END. Violating this gets Legalize
1546 // into an infinite loop.
1547 assert ((!IsLegalizingCall ||
1548 Node->getOpcode() != ISD::CALL ||
1549 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1550 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1552 // The number of incoming and outgoing values should match; unless the final
1553 // outgoing value is a flag.
1554 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1555 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1556 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1558 "Lowering call/formal_arguments produced unexpected # results!");
1560 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1561 // remember that we legalized all of them, so it doesn't get relegalized.
1562 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1563 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1565 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1566 if (Op.getResNo() == i)
1568 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1571 case ISD::EXTRACT_SUBREG: {
1572 Tmp1 = LegalizeOp(Node->getOperand(0));
1573 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1574 assert(idx && "Operand must be a constant");
1575 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1576 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1579 case ISD::INSERT_SUBREG: {
1580 Tmp1 = LegalizeOp(Node->getOperand(0));
1581 Tmp2 = LegalizeOp(Node->getOperand(1));
1582 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1583 assert(idx && "Operand must be a constant");
1584 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1585 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1588 case ISD::BUILD_VECTOR:
1589 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1590 default: assert(0 && "This action is not supported yet!");
1591 case TargetLowering::Custom:
1592 Tmp3 = TLI.LowerOperation(Result, DAG);
1593 if (Tmp3.getNode()) {
1598 case TargetLowering::Expand:
1599 Result = ExpandBUILD_VECTOR(Result.getNode());
1603 case ISD::INSERT_VECTOR_ELT:
1604 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1605 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1607 // The type of the value to insert may not be legal, even though the vector
1608 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1610 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1611 default: assert(0 && "Cannot expand insert element operand");
1612 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1613 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1615 // FIXME: An alternative would be to check to see if the target is not
1616 // going to custom lower this operation, we could bitcast to half elt
1617 // width and perform two inserts at that width, if that is legal.
1618 Tmp2 = Node->getOperand(1);
1621 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1623 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1624 Node->getValueType(0))) {
1625 default: assert(0 && "This action is not supported yet!");
1626 case TargetLowering::Legal:
1628 case TargetLowering::Custom:
1629 Tmp4 = TLI.LowerOperation(Result, DAG);
1630 if (Tmp4.getNode()) {
1635 case TargetLowering::Promote:
1636 // Fall thru for vector case
1637 case TargetLowering::Expand: {
1638 // If the insert index is a constant, codegen this as a scalar_to_vector,
1639 // then a shuffle that inserts it into the right position in the vector.
1640 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1641 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1642 // match the element type of the vector being created.
1643 if (Tmp2.getValueType() ==
1644 Op.getValueType().getVectorElementType()) {
1645 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1646 Tmp1.getValueType(), Tmp2);
1648 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1650 MVT::getIntVectorWithNumElements(NumElts);
1651 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1653 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1654 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1655 // elt 0 of the RHS.
1656 SmallVector<SDValue, 8> ShufOps;
1657 for (unsigned i = 0; i != NumElts; ++i) {
1658 if (i != InsertPos->getZExtValue())
1659 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1661 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1663 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1664 &ShufOps[0], ShufOps.size());
1666 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1667 Tmp1, ScVec, ShufMask);
1668 Result = LegalizeOp(Result);
1672 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3, dl);
1677 case ISD::SCALAR_TO_VECTOR:
1678 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1679 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1683 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1684 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1685 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1686 Node->getValueType(0))) {
1687 default: assert(0 && "This action is not supported yet!");
1688 case TargetLowering::Legal:
1690 case TargetLowering::Custom:
1691 Tmp3 = TLI.LowerOperation(Result, DAG);
1692 if (Tmp3.getNode()) {
1697 case TargetLowering::Expand:
1698 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1702 case ISD::VECTOR_SHUFFLE:
1703 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1704 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1705 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1707 // Allow targets to custom lower the SHUFFLEs they support.
1708 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1709 default: assert(0 && "Unknown operation action!");
1710 case TargetLowering::Legal:
1711 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1712 "vector shuffle should not be created if not legal!");
1714 case TargetLowering::Custom:
1715 Tmp3 = TLI.LowerOperation(Result, DAG);
1716 if (Tmp3.getNode()) {
1721 case TargetLowering::Expand: {
1722 MVT VT = Node->getValueType(0);
1723 MVT EltVT = VT.getVectorElementType();
1724 MVT PtrVT = TLI.getPointerTy();
1725 SDValue Mask = Node->getOperand(2);
1726 unsigned NumElems = Mask.getNumOperands();
1727 SmallVector<SDValue,8> Ops;
1728 for (unsigned i = 0; i != NumElems; ++i) {
1729 SDValue Arg = Mask.getOperand(i);
1730 if (Arg.getOpcode() == ISD::UNDEF) {
1731 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1733 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1734 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1736 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1737 DAG.getConstant(Idx, PtrVT)));
1739 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1740 DAG.getConstant(Idx - NumElems, PtrVT)));
1743 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1746 case TargetLowering::Promote: {
1747 // Change base type to a different vector type.
1748 MVT OVT = Node->getValueType(0);
1749 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1751 // Cast the two input vectors.
1752 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1753 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1755 // Convert the shuffle mask to the right # elements.
1756 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1757 assert(Tmp3.getNode() && "Shuffle not legal?");
1758 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1759 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1765 case ISD::EXTRACT_VECTOR_ELT:
1766 Tmp1 = Node->getOperand(0);
1767 Tmp2 = LegalizeOp(Node->getOperand(1));
1768 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1769 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1772 case ISD::EXTRACT_SUBVECTOR:
1773 Tmp1 = Node->getOperand(0);
1774 Tmp2 = LegalizeOp(Node->getOperand(1));
1775 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1776 Result = ExpandEXTRACT_SUBVECTOR(Result);
1779 case ISD::CONCAT_VECTORS: {
1780 // Use extract/insert/build vector for now. We might try to be
1781 // more clever later.
1782 MVT PtrVT = TLI.getPointerTy();
1783 SmallVector<SDValue, 8> Ops;
1784 unsigned NumOperands = Node->getNumOperands();
1785 for (unsigned i=0; i < NumOperands; ++i) {
1786 SDValue SubOp = Node->getOperand(i);
1787 MVT VVT = SubOp.getNode()->getValueType(0);
1788 MVT EltVT = VVT.getVectorElementType();
1789 unsigned NumSubElem = VVT.getVectorNumElements();
1790 for (unsigned j=0; j < NumSubElem; ++j) {
1791 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, SubOp,
1792 DAG.getConstant(j, PtrVT)));
1795 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
1796 &Ops[0], Ops.size()));
1799 case ISD::CALLSEQ_START: {
1800 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1802 // Recursively Legalize all of the inputs of the call end that do not lead
1803 // to this call start. This ensures that any libcalls that need be inserted
1804 // are inserted *before* the CALLSEQ_START.
1805 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1806 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1807 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1811 // Now that we legalized all of the inputs (which may have inserted
1812 // libcalls) create the new CALLSEQ_START node.
1813 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1815 // Merge in the last call, to ensure that this call start after the last
1817 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1818 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1819 Tmp1 = LegalizeOp(Tmp1);
1822 // Do not try to legalize the target-specific arguments (#1+).
1823 if (Tmp1 != Node->getOperand(0)) {
1824 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1826 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1829 // Remember that the CALLSEQ_START is legalized.
1830 AddLegalizedOperand(Op.getValue(0), Result);
1831 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1832 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1834 // Now that the callseq_start and all of the non-call nodes above this call
1835 // sequence have been legalized, legalize the call itself. During this
1836 // process, no libcalls can/will be inserted, guaranteeing that no calls
1838 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1839 // Note that we are selecting this call!
1840 LastCALLSEQ_END = SDValue(CallEnd, 0);
1841 IsLegalizingCall = true;
1843 // Legalize the call, starting from the CALLSEQ_END.
1844 LegalizeOp(LastCALLSEQ_END);
1845 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1848 case ISD::CALLSEQ_END:
1849 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1850 // will cause this node to be legalized as well as handling libcalls right.
1851 if (LastCALLSEQ_END.getNode() != Node) {
1852 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1853 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1854 assert(I != LegalizedNodes.end() &&
1855 "Legalizing the call start should have legalized this node!");
1859 // Otherwise, the call start has been legalized and everything is going
1860 // according to plan. Just legalize ourselves normally here.
1861 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1862 // Do not try to legalize the target-specific arguments (#1+), except for
1863 // an optional flag input.
1864 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1865 if (Tmp1 != Node->getOperand(0)) {
1866 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1868 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1871 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1872 if (Tmp1 != Node->getOperand(0) ||
1873 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1874 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1877 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1880 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1881 // This finishes up call legalization.
1882 IsLegalizingCall = false;
1884 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1885 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1886 if (Node->getNumValues() == 2)
1887 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1888 return Result.getValue(Op.getResNo());
1889 case ISD::DYNAMIC_STACKALLOC: {
1890 MVT VT = Node->getValueType(0);
1891 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1892 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1893 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1894 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1896 Tmp1 = Result.getValue(0);
1897 Tmp2 = Result.getValue(1);
1898 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1899 default: assert(0 && "This action is not supported yet!");
1900 case TargetLowering::Expand: {
1901 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1902 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1903 " not tell us which reg is the stack pointer!");
1904 SDValue Chain = Tmp1.getOperand(0);
1906 // Chain the dynamic stack allocation so that it doesn't modify the stack
1907 // pointer when other instructions are using the stack.
1908 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1910 SDValue Size = Tmp2.getOperand(1);
1911 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1912 Chain = SP.getValue(1);
1913 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1914 unsigned StackAlign =
1915 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1916 if (Align > StackAlign)
1917 SP = DAG.getNode(ISD::AND, VT, SP,
1918 DAG.getConstant(-(uint64_t)Align, VT));
1919 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1920 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1922 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1923 DAG.getIntPtrConstant(0, true), SDValue());
1925 Tmp1 = LegalizeOp(Tmp1);
1926 Tmp2 = LegalizeOp(Tmp2);
1929 case TargetLowering::Custom:
1930 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1931 if (Tmp3.getNode()) {
1932 Tmp1 = LegalizeOp(Tmp3);
1933 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1936 case TargetLowering::Legal:
1939 // Since this op produce two values, make sure to remember that we
1940 // legalized both of them.
1941 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1942 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1943 return Op.getResNo() ? Tmp2 : Tmp1;
1945 case ISD::INLINEASM: {
1946 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1947 bool Changed = false;
1948 // Legalize all of the operands of the inline asm, in case they are nodes
1949 // that need to be expanded or something. Note we skip the asm string and
1950 // all of the TargetConstant flags.
1951 SDValue Op = LegalizeOp(Ops[0]);
1952 Changed = Op != Ops[0];
1955 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1956 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1957 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3;
1958 for (++i; NumVals; ++i, --NumVals) {
1959 SDValue Op = LegalizeOp(Ops[i]);
1968 Op = LegalizeOp(Ops.back());
1969 Changed |= Op != Ops.back();
1974 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1976 // INLINE asm returns a chain and flag, make sure to add both to the map.
1977 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1978 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1979 return Result.getValue(Op.getResNo());
1982 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1983 // Ensure that libcalls are emitted before a branch.
1984 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1985 Tmp1 = LegalizeOp(Tmp1);
1986 LastCALLSEQ_END = DAG.getEntryNode();
1988 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1991 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1992 // Ensure that libcalls are emitted before a branch.
1993 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1994 Tmp1 = LegalizeOp(Tmp1);
1995 LastCALLSEQ_END = DAG.getEntryNode();
1997 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1998 default: assert(0 && "Indirect target must be legal type (pointer)!");
2000 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2003 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2006 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2007 // Ensure that libcalls are emitted before a branch.
2008 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2009 Tmp1 = LegalizeOp(Tmp1);
2010 LastCALLSEQ_END = DAG.getEntryNode();
2012 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
2013 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2015 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
2016 default: assert(0 && "This action is not supported yet!");
2017 case TargetLowering::Legal: break;
2018 case TargetLowering::Custom:
2019 Tmp1 = TLI.LowerOperation(Result, DAG);
2020 if (Tmp1.getNode()) Result = Tmp1;
2022 case TargetLowering::Expand: {
2023 SDValue Chain = Result.getOperand(0);
2024 SDValue Table = Result.getOperand(1);
2025 SDValue Index = Result.getOperand(2);
2027 MVT PTy = TLI.getPointerTy();
2028 MachineFunction &MF = DAG.getMachineFunction();
2029 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
2030 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
2031 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
2033 MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
2034 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, Chain, Addr,
2035 PseudoSourceValue::getJumpTable(), 0, MemVT);
2037 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2038 // For PIC, the sequence is:
2039 // BRIND(load(Jumptable + index) + RelocBase)
2040 // RelocBase can be JumpTable, GOT or some sort of global base.
2041 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
2042 TLI.getPICJumpTableRelocBase(Table, DAG));
2044 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
2049 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2050 // Ensure that libcalls are emitted before a return.
2051 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2052 Tmp1 = LegalizeOp(Tmp1);
2053 LastCALLSEQ_END = DAG.getEntryNode();
2055 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2056 case Expand: assert(0 && "It's impossible to expand bools");
2058 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2061 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
2063 // The top bits of the promoted condition are not necessarily zero, ensure
2064 // that the value is properly zero extended.
2065 unsigned BitWidth = Tmp2.getValueSizeInBits();
2066 if (!DAG.MaskedValueIsZero(Tmp2,
2067 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2068 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
2073 // Basic block destination (Op#2) is always legal.
2074 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2076 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
2077 default: assert(0 && "This action is not supported yet!");
2078 case TargetLowering::Legal: break;
2079 case TargetLowering::Custom:
2080 Tmp1 = TLI.LowerOperation(Result, DAG);
2081 if (Tmp1.getNode()) Result = Tmp1;
2083 case TargetLowering::Expand:
2084 // Expand brcond's setcc into its constituent parts and create a BR_CC
2086 if (Tmp2.getOpcode() == ISD::SETCC) {
2087 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
2088 Tmp2.getOperand(0), Tmp2.getOperand(1),
2089 Node->getOperand(2));
2091 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
2092 DAG.getCondCode(ISD::SETNE), Tmp2,
2093 DAG.getConstant(0, Tmp2.getValueType()),
2094 Node->getOperand(2));
2100 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2101 // Ensure that libcalls are emitted before a branch.
2102 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2103 Tmp1 = LegalizeOp(Tmp1);
2104 Tmp2 = Node->getOperand(2); // LHS
2105 Tmp3 = Node->getOperand(3); // RHS
2106 Tmp4 = Node->getOperand(1); // CC
2108 LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()),
2109 Tmp2, Tmp3, Tmp4, dl);
2110 LastCALLSEQ_END = DAG.getEntryNode();
2112 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2113 // the LHS is a legal SETCC itself. In this case, we need to compare
2114 // the result against zero to select between true and false values.
2115 if (Tmp3.getNode() == 0) {
2116 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2117 Tmp4 = DAG.getCondCode(ISD::SETNE);
2120 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
2121 Node->getOperand(4));
2123 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
2124 default: assert(0 && "Unexpected action for BR_CC!");
2125 case TargetLowering::Legal: break;
2126 case TargetLowering::Custom:
2127 Tmp4 = TLI.LowerOperation(Result, DAG);
2128 if (Tmp4.getNode()) Result = Tmp4;
2133 LoadSDNode *LD = cast<LoadSDNode>(Node);
2134 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
2135 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
2137 ISD::LoadExtType ExtType = LD->getExtensionType();
2138 if (ExtType == ISD::NON_EXTLOAD) {
2139 MVT VT = Node->getValueType(0);
2140 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2141 Tmp3 = Result.getValue(0);
2142 Tmp4 = Result.getValue(1);
2144 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
2145 default: assert(0 && "This action is not supported yet!");
2146 case TargetLowering::Legal:
2147 // If this is an unaligned load and the target doesn't support it,
2149 if (!TLI.allowsUnalignedMemoryAccesses()) {
2150 unsigned ABIAlignment = TLI.getTargetData()->
2151 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2152 if (LD->getAlignment() < ABIAlignment){
2153 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2155 Tmp3 = Result.getOperand(0);
2156 Tmp4 = Result.getOperand(1);
2157 Tmp3 = LegalizeOp(Tmp3);
2158 Tmp4 = LegalizeOp(Tmp4);
2162 case TargetLowering::Custom:
2163 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
2164 if (Tmp1.getNode()) {
2165 Tmp3 = LegalizeOp(Tmp1);
2166 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2169 case TargetLowering::Promote: {
2170 // Only promote a load of vector type to another.
2171 assert(VT.isVector() && "Cannot promote this load!");
2172 // Change base type to a different vector type.
2173 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
2175 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
2176 LD->getSrcValueOffset(),
2177 LD->isVolatile(), LD->getAlignment());
2178 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
2179 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2183 // Since loads produce two values, make sure to remember that we
2184 // legalized both of them.
2185 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
2186 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
2187 return Op.getResNo() ? Tmp4 : Tmp3;
2189 MVT SrcVT = LD->getMemoryVT();
2190 unsigned SrcWidth = SrcVT.getSizeInBits();
2191 int SVOffset = LD->getSrcValueOffset();
2192 unsigned Alignment = LD->getAlignment();
2193 bool isVolatile = LD->isVolatile();
2195 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
2196 // Some targets pretend to have an i1 loading operation, and actually
2197 // load an i8. This trick is correct for ZEXTLOAD because the top 7
2198 // bits are guaranteed to be zero; it helps the optimizers understand
2199 // that these bits are zero. It is also useful for EXTLOAD, since it
2200 // tells the optimizers that those bits are undefined. It would be
2201 // nice to have an effective generic way of getting these benefits...
2202 // Until such a way is found, don't insist on promoting i1 here.
2203 (SrcVT != MVT::i1 ||
2204 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2205 // Promote to a byte-sized load if not loading an integral number of
2206 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2207 unsigned NewWidth = SrcVT.getStoreSizeInBits();
2208 MVT NVT = MVT::getIntegerVT(NewWidth);
2211 // The extra bits are guaranteed to be zero, since we stored them that
2212 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2214 ISD::LoadExtType NewExtType =
2215 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2217 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2218 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2219 NVT, isVolatile, Alignment);
2221 Ch = Result.getValue(1); // The chain.
2223 if (ExtType == ISD::SEXTLOAD)
2224 // Having the top bits zero doesn't help when sign extending.
2225 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2226 Result, DAG.getValueType(SrcVT));
2227 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2228 // All the top bits are guaranteed to be zero - inform the optimizers.
2229 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2230 DAG.getValueType(SrcVT));
2232 Tmp1 = LegalizeOp(Result);
2233 Tmp2 = LegalizeOp(Ch);
2234 } else if (SrcWidth & (SrcWidth - 1)) {
2235 // If not loading a power-of-2 number of bits, expand as two loads.
2236 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2237 "Unsupported extload!");
2238 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2239 assert(RoundWidth < SrcWidth);
2240 unsigned ExtraWidth = SrcWidth - RoundWidth;
2241 assert(ExtraWidth < RoundWidth);
2242 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2243 "Load size not an integral number of bytes!");
2244 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2245 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2247 unsigned IncrementSize;
2249 if (TLI.isLittleEndian()) {
2250 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2251 // Load the bottom RoundWidth bits.
2252 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2253 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2256 // Load the remaining ExtraWidth bits.
2257 IncrementSize = RoundWidth / 8;
2258 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2259 DAG.getIntPtrConstant(IncrementSize));
2260 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2261 LD->getSrcValue(), SVOffset + IncrementSize,
2262 ExtraVT, isVolatile,
2263 MinAlign(Alignment, IncrementSize));
2265 // Build a factor node to remember that this load is independent of the
2267 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2270 // Move the top bits to the right place.
2271 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2272 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2274 // Join the hi and lo parts.
2275 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2277 // Big endian - avoid unaligned loads.
2278 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2279 // Load the top RoundWidth bits.
2280 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2281 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2284 // Load the remaining ExtraWidth bits.
2285 IncrementSize = RoundWidth / 8;
2286 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2287 DAG.getIntPtrConstant(IncrementSize));
2288 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2289 LD->getSrcValue(), SVOffset + IncrementSize,
2290 ExtraVT, isVolatile,
2291 MinAlign(Alignment, IncrementSize));
2293 // Build a factor node to remember that this load is independent of the
2295 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2298 // Move the top bits to the right place.
2299 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2300 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2302 // Join the hi and lo parts.
2303 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2306 Tmp1 = LegalizeOp(Result);
2307 Tmp2 = LegalizeOp(Ch);
2309 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
2310 default: assert(0 && "This action is not supported yet!");
2311 case TargetLowering::Custom:
2314 case TargetLowering::Legal:
2315 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2316 Tmp1 = Result.getValue(0);
2317 Tmp2 = Result.getValue(1);
2320 Tmp3 = TLI.LowerOperation(Result, DAG);
2321 if (Tmp3.getNode()) {
2322 Tmp1 = LegalizeOp(Tmp3);
2323 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2326 // If this is an unaligned load and the target doesn't support it,
2328 if (!TLI.allowsUnalignedMemoryAccesses()) {
2329 unsigned ABIAlignment = TLI.getTargetData()->
2330 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2331 if (LD->getAlignment() < ABIAlignment){
2332 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2334 Tmp1 = Result.getOperand(0);
2335 Tmp2 = Result.getOperand(1);
2336 Tmp1 = LegalizeOp(Tmp1);
2337 Tmp2 = LegalizeOp(Tmp2);
2342 case TargetLowering::Expand:
2343 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2344 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2345 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2346 LD->getSrcValueOffset(),
2347 LD->isVolatile(), LD->getAlignment());
2348 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2349 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2350 Tmp2 = LegalizeOp(Load.getValue(1));
2353 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2354 // Turn the unsupported load into an EXTLOAD followed by an explicit
2355 // zero/sign extend inreg.
2356 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2357 Tmp1, Tmp2, LD->getSrcValue(),
2358 LD->getSrcValueOffset(), SrcVT,
2359 LD->isVolatile(), LD->getAlignment());
2361 if (ExtType == ISD::SEXTLOAD)
2362 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2363 Result, DAG.getValueType(SrcVT));
2365 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2366 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2367 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2372 // Since loads produce two values, make sure to remember that we legalized
2374 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2375 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2376 return Op.getResNo() ? Tmp2 : Tmp1;
2379 case ISD::EXTRACT_ELEMENT: {
2380 MVT OpTy = Node->getOperand(0).getValueType();
2381 switch (getTypeAction(OpTy)) {
2382 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2384 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2386 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2387 DAG.getConstant(OpTy.getSizeInBits()/2,
2388 TLI.getShiftAmountTy()));
2389 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2392 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2393 Node->getOperand(0));
2397 // Get both the low and high parts.
2398 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2399 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2400 Result = Tmp2; // 1 -> Hi
2402 Result = Tmp1; // 0 -> Lo
2408 case ISD::CopyToReg:
2409 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2411 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2412 "Register type must be legal!");
2413 // Legalize the incoming value (must be a legal type).
2414 Tmp2 = LegalizeOp(Node->getOperand(2));
2415 if (Node->getNumValues() == 1) {
2416 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2418 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2419 if (Node->getNumOperands() == 4) {
2420 Tmp3 = LegalizeOp(Node->getOperand(3));
2421 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2424 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2427 // Since this produces two values, make sure to remember that we legalized
2429 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2430 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2436 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2438 // Ensure that libcalls are emitted before a return.
2439 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2440 Tmp1 = LegalizeOp(Tmp1);
2441 LastCALLSEQ_END = DAG.getEntryNode();
2443 switch (Node->getNumOperands()) {
2445 Tmp2 = Node->getOperand(1);
2446 Tmp3 = Node->getOperand(2); // Signness
2447 switch (getTypeAction(Tmp2.getValueType())) {
2449 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2452 if (!Tmp2.getValueType().isVector()) {
2454 ExpandOp(Tmp2, Lo, Hi);
2456 // Big endian systems want the hi reg first.
2457 if (TLI.isBigEndian())
2461 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2463 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2464 Result = LegalizeOp(Result);
2466 SDNode *InVal = Tmp2.getNode();
2467 int InIx = Tmp2.getResNo();
2468 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2469 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2471 // Figure out if there is a simple type corresponding to this Vector
2472 // type. If so, convert to the vector type.
2473 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2474 if (TLI.isTypeLegal(TVT)) {
2475 // Turn this into a return of the vector type.
2476 Tmp2 = LegalizeOp(Tmp2);
2477 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2478 } else if (NumElems == 1) {
2479 // Turn this into a return of the scalar type.
2480 Tmp2 = ScalarizeVectorOp(Tmp2);
2481 Tmp2 = LegalizeOp(Tmp2);
2482 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2484 // FIXME: Returns of gcc generic vectors smaller than a legal type
2485 // should be returned in integer registers!
2487 // The scalarized value type may not be legal, e.g. it might require
2488 // promotion or expansion. Relegalize the return.
2489 Result = LegalizeOp(Result);
2491 // FIXME: Returns of gcc generic vectors larger than a legal vector
2492 // type should be returned by reference!
2494 SplitVectorOp(Tmp2, Lo, Hi);
2495 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2496 Result = LegalizeOp(Result);
2501 Tmp2 = PromoteOp(Node->getOperand(1));
2502 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2503 Result = LegalizeOp(Result);
2508 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2510 default: { // ret <values>
2511 SmallVector<SDValue, 8> NewValues;
2512 NewValues.push_back(Tmp1);
2513 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2514 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2516 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2517 NewValues.push_back(Node->getOperand(i+1));
2521 assert(!Node->getOperand(i).getValueType().isExtended() &&
2522 "FIXME: TODO: implement returning non-legal vector types!");
2523 ExpandOp(Node->getOperand(i), Lo, Hi);
2524 NewValues.push_back(Lo);
2525 NewValues.push_back(Node->getOperand(i+1));
2527 NewValues.push_back(Hi);
2528 NewValues.push_back(Node->getOperand(i+1));
2533 assert(0 && "Can't promote multiple return value yet!");
2536 if (NewValues.size() == Node->getNumOperands())
2537 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2539 Result = DAG.getNode(ISD::RET, MVT::Other,
2540 &NewValues[0], NewValues.size());
2545 if (Result.getOpcode() == ISD::RET) {
2546 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2547 default: assert(0 && "This action is not supported yet!");
2548 case TargetLowering::Legal: break;
2549 case TargetLowering::Custom:
2550 Tmp1 = TLI.LowerOperation(Result, DAG);
2551 if (Tmp1.getNode()) Result = Tmp1;
2557 StoreSDNode *ST = cast<StoreSDNode>(Node);
2558 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2559 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2560 int SVOffset = ST->getSrcValueOffset();
2561 unsigned Alignment = ST->getAlignment();
2562 bool isVolatile = ST->isVolatile();
2564 if (!ST->isTruncatingStore()) {
2565 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2566 // FIXME: We shouldn't do this for TargetConstantFP's.
2567 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2568 // to phase ordering between legalized code and the dag combiner. This
2569 // probably means that we need to integrate dag combiner and legalizer
2571 // We generally can't do this one for long doubles.
2572 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2573 if (CFP->getValueType(0) == MVT::f32 &&
2574 getTypeAction(MVT::i32) == Legal) {
2575 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2576 bitcastToAPInt().zextOrTrunc(32),
2578 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2579 SVOffset, isVolatile, Alignment);
2581 } else if (CFP->getValueType(0) == MVT::f64) {
2582 // If this target supports 64-bit registers, do a single 64-bit store.
2583 if (getTypeAction(MVT::i64) == Legal) {
2584 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
2585 zextOrTrunc(64), MVT::i64);
2586 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2587 SVOffset, isVolatile, Alignment);
2589 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2590 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2591 // stores. If the target supports neither 32- nor 64-bits, this
2592 // xform is certainly not worth it.
2593 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
2594 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2595 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2596 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2598 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2599 SVOffset, isVolatile, Alignment);
2600 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2601 DAG.getIntPtrConstant(4));
2602 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2603 isVolatile, MinAlign(Alignment, 4U));
2605 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2611 switch (getTypeAction(ST->getMemoryVT())) {
2613 Tmp3 = LegalizeOp(ST->getValue());
2614 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2617 MVT VT = Tmp3.getValueType();
2618 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2619 default: assert(0 && "This action is not supported yet!");
2620 case TargetLowering::Legal:
2621 // If this is an unaligned store and the target doesn't support it,
2623 if (!TLI.allowsUnalignedMemoryAccesses()) {
2624 unsigned ABIAlignment = TLI.getTargetData()->
2625 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2626 if (ST->getAlignment() < ABIAlignment)
2627 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2631 case TargetLowering::Custom:
2632 Tmp1 = TLI.LowerOperation(Result, DAG);
2633 if (Tmp1.getNode()) Result = Tmp1;
2635 case TargetLowering::Promote:
2636 assert(VT.isVector() && "Unknown legal promote case!");
2637 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2638 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2639 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2640 ST->getSrcValue(), SVOffset, isVolatile,
2647 if (!ST->getMemoryVT().isVector()) {
2648 // Truncate the value and store the result.
2649 Tmp3 = PromoteOp(ST->getValue());
2650 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2651 SVOffset, ST->getMemoryVT(),
2652 isVolatile, Alignment);
2655 // Fall thru to expand for vector
2657 unsigned IncrementSize = 0;
2660 // If this is a vector type, then we have to calculate the increment as
2661 // the product of the element size in bytes, and the number of elements
2662 // in the high half of the vector.
2663 if (ST->getValue().getValueType().isVector()) {
2664 SDNode *InVal = ST->getValue().getNode();
2665 int InIx = ST->getValue().getResNo();
2666 MVT InVT = InVal->getValueType(InIx);
2667 unsigned NumElems = InVT.getVectorNumElements();
2668 MVT EVT = InVT.getVectorElementType();
2670 // Figure out if there is a simple type corresponding to this Vector
2671 // type. If so, convert to the vector type.
2672 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2673 if (TLI.isTypeLegal(TVT)) {
2674 // Turn this into a normal store of the vector type.
2675 Tmp3 = LegalizeOp(ST->getValue());
2676 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2677 SVOffset, isVolatile, Alignment);
2678 Result = LegalizeOp(Result);
2680 } else if (NumElems == 1) {
2681 // Turn this into a normal store of the scalar type.
2682 Tmp3 = ScalarizeVectorOp(ST->getValue());
2683 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2684 SVOffset, isVolatile, Alignment);
2685 // The scalarized value type may not be legal, e.g. it might require
2686 // promotion or expansion. Relegalize the scalar store.
2687 Result = LegalizeOp(Result);
2690 // Check if we have widen this node with another value
2691 std::map<SDValue, SDValue>::iterator I =
2692 WidenNodes.find(ST->getValue());
2693 if (I != WidenNodes.end()) {
2694 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2);
2698 SplitVectorOp(ST->getValue(), Lo, Hi);
2699 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2700 EVT.getSizeInBits()/8;
2704 ExpandOp(ST->getValue(), Lo, Hi);
2705 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2707 if (Hi.getNode() && TLI.isBigEndian())
2711 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2712 SVOffset, isVolatile, Alignment);
2714 if (Hi.getNode() == NULL) {
2715 // Must be int <-> float one-to-one expansion.
2720 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2721 DAG.getIntPtrConstant(IncrementSize));
2722 assert(isTypeLegal(Tmp2.getValueType()) &&
2723 "Pointers must be legal!");
2724 SVOffset += IncrementSize;
2725 Alignment = MinAlign(Alignment, IncrementSize);
2726 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2727 SVOffset, isVolatile, Alignment);
2728 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2733 switch (getTypeAction(ST->getValue().getValueType())) {
2735 Tmp3 = LegalizeOp(ST->getValue());
2738 if (!ST->getValue().getValueType().isVector()) {
2739 // We can promote the value, the truncstore will still take care of it.
2740 Tmp3 = PromoteOp(ST->getValue());
2743 // Vector case falls through to expand
2745 // Just store the low part. This may become a non-trunc store, so make
2746 // sure to use getTruncStore, not UpdateNodeOperands below.
2747 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2748 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2749 SVOffset, MVT::i8, isVolatile, Alignment);
2752 MVT StVT = ST->getMemoryVT();
2753 unsigned StWidth = StVT.getSizeInBits();
2755 if (StWidth != StVT.getStoreSizeInBits()) {
2756 // Promote to a byte-sized store with upper bits zero if not
2757 // storing an integral number of bytes. For example, promote
2758 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2759 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2760 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2761 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2762 SVOffset, NVT, isVolatile, Alignment);
2763 } else if (StWidth & (StWidth - 1)) {
2764 // If not storing a power-of-2 number of bits, expand as two stores.
2765 assert(StVT.isExtended() && !StVT.isVector() &&
2766 "Unsupported truncstore!");
2767 unsigned RoundWidth = 1 << Log2_32(StWidth);
2768 assert(RoundWidth < StWidth);
2769 unsigned ExtraWidth = StWidth - RoundWidth;
2770 assert(ExtraWidth < RoundWidth);
2771 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2772 "Store size not an integral number of bytes!");
2773 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2774 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2776 unsigned IncrementSize;
2778 if (TLI.isLittleEndian()) {
2779 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2780 // Store the bottom RoundWidth bits.
2781 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2783 isVolatile, Alignment);
2785 // Store the remaining ExtraWidth bits.
2786 IncrementSize = RoundWidth / 8;
2787 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2788 DAG.getIntPtrConstant(IncrementSize));
2789 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2790 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2791 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2792 SVOffset + IncrementSize, ExtraVT, isVolatile,
2793 MinAlign(Alignment, IncrementSize));
2795 // Big endian - avoid unaligned stores.
2796 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2797 // Store the top RoundWidth bits.
2798 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2799 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2800 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2801 RoundVT, isVolatile, Alignment);
2803 // Store the remaining ExtraWidth bits.
2804 IncrementSize = RoundWidth / 8;
2805 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2806 DAG.getIntPtrConstant(IncrementSize));
2807 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2808 SVOffset + IncrementSize, ExtraVT, isVolatile,
2809 MinAlign(Alignment, IncrementSize));
2812 // The order of the stores doesn't matter.
2813 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2815 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2816 Tmp2 != ST->getBasePtr())
2817 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2820 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2821 default: assert(0 && "This action is not supported yet!");
2822 case TargetLowering::Legal:
2823 // If this is an unaligned store and the target doesn't support it,
2825 if (!TLI.allowsUnalignedMemoryAccesses()) {
2826 unsigned ABIAlignment = TLI.getTargetData()->
2827 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2828 if (ST->getAlignment() < ABIAlignment)
2829 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2833 case TargetLowering::Custom:
2834 Result = TLI.LowerOperation(Result, DAG);
2837 // TRUNCSTORE:i16 i32 -> STORE i16
2838 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2839 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2840 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2841 isVolatile, Alignment);
2849 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2850 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2852 case ISD::STACKSAVE:
2853 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2854 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2855 Tmp1 = Result.getValue(0);
2856 Tmp2 = Result.getValue(1);
2858 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2859 default: assert(0 && "This action is not supported yet!");
2860 case TargetLowering::Legal: break;
2861 case TargetLowering::Custom:
2862 Tmp3 = TLI.LowerOperation(Result, DAG);
2863 if (Tmp3.getNode()) {
2864 Tmp1 = LegalizeOp(Tmp3);
2865 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2868 case TargetLowering::Expand:
2869 // Expand to CopyFromReg if the target set
2870 // StackPointerRegisterToSaveRestore.
2871 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2872 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2873 Node->getValueType(0));
2874 Tmp2 = Tmp1.getValue(1);
2876 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2877 Tmp2 = Node->getOperand(0);
2882 // Since stacksave produce two values, make sure to remember that we
2883 // legalized both of them.
2884 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2885 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2886 return Op.getResNo() ? Tmp2 : Tmp1;
2888 case ISD::STACKRESTORE:
2889 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2890 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2891 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2893 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2894 default: assert(0 && "This action is not supported yet!");
2895 case TargetLowering::Legal: break;
2896 case TargetLowering::Custom:
2897 Tmp1 = TLI.LowerOperation(Result, DAG);
2898 if (Tmp1.getNode()) Result = Tmp1;
2900 case TargetLowering::Expand:
2901 // Expand to CopyToReg if the target set
2902 // StackPointerRegisterToSaveRestore.
2903 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2904 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2912 case ISD::READCYCLECOUNTER:
2913 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2914 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2915 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2916 Node->getValueType(0))) {
2917 default: assert(0 && "This action is not supported yet!");
2918 case TargetLowering::Legal:
2919 Tmp1 = Result.getValue(0);
2920 Tmp2 = Result.getValue(1);
2922 case TargetLowering::Custom:
2923 Result = TLI.LowerOperation(Result, DAG);
2924 Tmp1 = LegalizeOp(Result.getValue(0));
2925 Tmp2 = LegalizeOp(Result.getValue(1));
2929 // Since rdcc produce two values, make sure to remember that we legalized
2931 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2932 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2936 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2937 case Expand: assert(0 && "It's impossible to expand bools");
2939 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2942 assert(!Node->getOperand(0).getValueType().isVector() && "not possible");
2943 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2944 // Make sure the condition is either zero or one.
2945 unsigned BitWidth = Tmp1.getValueSizeInBits();
2946 if (!DAG.MaskedValueIsZero(Tmp1,
2947 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2948 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2952 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2953 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2955 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2957 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2958 default: assert(0 && "This action is not supported yet!");
2959 case TargetLowering::Legal: break;
2960 case TargetLowering::Custom: {
2961 Tmp1 = TLI.LowerOperation(Result, DAG);
2962 if (Tmp1.getNode()) Result = Tmp1;
2965 case TargetLowering::Expand:
2966 if (Tmp1.getOpcode() == ISD::SETCC) {
2967 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2969 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2971 Result = DAG.getSelectCC(Tmp1,
2972 DAG.getConstant(0, Tmp1.getValueType()),
2973 Tmp2, Tmp3, ISD::SETNE);
2976 case TargetLowering::Promote: {
2978 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2979 unsigned ExtOp, TruncOp;
2980 if (Tmp2.getValueType().isVector()) {
2981 ExtOp = ISD::BIT_CONVERT;
2982 TruncOp = ISD::BIT_CONVERT;
2983 } else if (Tmp2.getValueType().isInteger()) {
2984 ExtOp = ISD::ANY_EXTEND;
2985 TruncOp = ISD::TRUNCATE;
2987 ExtOp = ISD::FP_EXTEND;
2988 TruncOp = ISD::FP_ROUND;
2990 // Promote each of the values to the new type.
2991 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2992 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2993 // Perform the larger operation, then round down.
2994 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2995 if (TruncOp != ISD::FP_ROUND)
2996 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2998 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2999 DAG.getIntPtrConstant(0));
3004 case ISD::SELECT_CC: {
3005 Tmp1 = Node->getOperand(0); // LHS
3006 Tmp2 = Node->getOperand(1); // RHS
3007 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
3008 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
3009 SDValue CC = Node->getOperand(4);
3011 LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()),
3012 Tmp1, Tmp2, CC, dl);
3014 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
3015 // the LHS is a legal SETCC itself. In this case, we need to compare
3016 // the result against zero to select between true and false values.
3017 if (Tmp2.getNode() == 0) {
3018 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3019 CC = DAG.getCondCode(ISD::SETNE);
3021 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
3023 // Everything is legal, see if we should expand this op or something.
3024 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
3025 default: assert(0 && "This action is not supported yet!");
3026 case TargetLowering::Legal: break;
3027 case TargetLowering::Custom:
3028 Tmp1 = TLI.LowerOperation(Result, DAG);
3029 if (Tmp1.getNode()) Result = Tmp1;
3035 Tmp1 = Node->getOperand(0);
3036 Tmp2 = Node->getOperand(1);
3037 Tmp3 = Node->getOperand(2);
3038 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3040 // If we had to Expand the SetCC operands into a SELECT node, then it may
3041 // not always be possible to return a true LHS & RHS. In this case, just
3042 // return the value we legalized, returned in the LHS
3043 if (Tmp2.getNode() == 0) {
3048 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
3049 default: assert(0 && "Cannot handle this action for SETCC yet!");
3050 case TargetLowering::Custom:
3053 case TargetLowering::Legal:
3054 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3056 Tmp4 = TLI.LowerOperation(Result, DAG);
3057 if (Tmp4.getNode()) Result = Tmp4;
3060 case TargetLowering::Promote: {
3061 // First step, figure out the appropriate operation to use.
3062 // Allow SETCC to not be supported for all legal data types
3063 // Mostly this targets FP
3064 MVT NewInTy = Node->getOperand(0).getValueType();
3065 MVT OldVT = NewInTy; OldVT = OldVT;
3067 // Scan for the appropriate larger type to use.
3069 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
3071 assert(NewInTy.isInteger() == OldVT.isInteger() &&
3072 "Fell off of the edge of the integer world");
3073 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
3074 "Fell off of the edge of the floating point world");
3076 // If the target supports SETCC of this type, use it.
3077 if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy))
3080 if (NewInTy.isInteger())
3081 assert(0 && "Cannot promote Legal Integer SETCC yet");
3083 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
3084 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
3086 Tmp1 = LegalizeOp(Tmp1);
3087 Tmp2 = LegalizeOp(Tmp2);
3088 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3089 Result = LegalizeOp(Result);
3092 case TargetLowering::Expand:
3093 // Expand a setcc node into a select_cc of the same condition, lhs, and
3094 // rhs that selects between const 1 (true) and const 0 (false).
3095 MVT VT = Node->getValueType(0);
3096 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
3097 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3103 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3104 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3105 SDValue CC = Node->getOperand(2);
3107 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
3109 // Everything is legal, see if we should expand this op or something.
3110 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
3111 default: assert(0 && "This action is not supported yet!");
3112 case TargetLowering::Legal: break;
3113 case TargetLowering::Custom:
3114 Tmp1 = TLI.LowerOperation(Result, DAG);
3115 if (Tmp1.getNode()) Result = Tmp1;
3117 case TargetLowering::Expand: {
3118 // Unroll into a nasty set of scalar code for now.
3119 MVT VT = Node->getValueType(0);
3120 unsigned NumElems = VT.getVectorNumElements();
3121 MVT EltVT = VT.getVectorElementType();
3122 MVT TmpEltVT = Tmp1.getValueType().getVectorElementType();
3123 SmallVector<SDValue, 8> Ops(NumElems);
3124 for (unsigned i = 0; i < NumElems; ++i) {
3125 SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
3126 Tmp1, DAG.getIntPtrConstant(i));
3127 Ops[i] = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(TmpEltVT), In1,
3128 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
3129 Tmp2, DAG.getIntPtrConstant(i)),
3131 Ops[i] = DAG.getNode(ISD::SELECT, EltVT, Ops[i], DAG.getConstant(
3132 APInt::getAllOnesValue(EltVT.getSizeInBits()),
3133 EltVT), DAG.getConstant(0, EltVT));
3135 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], NumElems);
3142 case ISD::SHL_PARTS:
3143 case ISD::SRA_PARTS:
3144 case ISD::SRL_PARTS: {
3145 SmallVector<SDValue, 8> Ops;
3146 bool Changed = false;
3147 unsigned N = Node->getNumOperands();
3148 for (unsigned i = 0; i + 1 < N; ++i) {
3149 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3150 Changed |= Ops.back() != Node->getOperand(i);
3152 Ops.push_back(LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(N-1))));
3153 Changed |= Ops.back() != Node->getOperand(N-1);
3155 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
3157 switch (TLI.getOperationAction(Node->getOpcode(),
3158 Node->getValueType(0))) {
3159 default: assert(0 && "This action is not supported yet!");
3160 case TargetLowering::Legal: break;
3161 case TargetLowering::Custom:
3162 Tmp1 = TLI.LowerOperation(Result, DAG);
3163 if (Tmp1.getNode()) {
3164 SDValue Tmp2, RetVal(0, 0);
3165 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
3166 Tmp2 = LegalizeOp(Tmp1.getValue(i));
3167 AddLegalizedOperand(SDValue(Node, i), Tmp2);
3168 if (i == Op.getResNo())
3171 assert(RetVal.getNode() && "Illegal result number");
3177 // Since these produce multiple values, make sure to remember that we
3178 // legalized all of them.
3179 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3180 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
3181 return Result.getValue(Op.getResNo());
3203 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3204 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3206 if ((Node->getOpcode() == ISD::SHL ||
3207 Node->getOpcode() == ISD::SRL ||
3208 Node->getOpcode() == ISD::SRA) &&
3209 !Node->getValueType(0).isVector())
3210 Tmp2 = DAG.getShiftAmountOperand(Tmp2);
3212 switch (getTypeAction(Tmp2.getValueType())) {
3213 case Expand: assert(0 && "Not possible");
3215 Tmp2 = LegalizeOp(Tmp2); // Legalize the RHS.
3218 Tmp2 = PromoteOp(Tmp2); // Promote the RHS.
3222 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3224 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3225 default: assert(0 && "BinOp legalize operation not supported");
3226 case TargetLowering::Legal: break;
3227 case TargetLowering::Custom:
3228 Tmp1 = TLI.LowerOperation(Result, DAG);
3229 if (Tmp1.getNode()) {
3233 // Fall through if the custom lower can't deal with the operation
3234 case TargetLowering::Expand: {
3235 MVT VT = Op.getValueType();
3237 // See if multiply or divide can be lowered using two-result operations.
3238 SDVTList VTs = DAG.getVTList(VT, VT);
3239 if (Node->getOpcode() == ISD::MUL) {
3240 // We just need the low half of the multiply; try both the signed
3241 // and unsigned forms. If the target supports both SMUL_LOHI and
3242 // UMUL_LOHI, form a preference by checking which forms of plain
3243 // MULH it supports.
3244 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3245 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3246 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3247 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3248 unsigned OpToUse = 0;
3249 if (HasSMUL_LOHI && !HasMULHS) {
3250 OpToUse = ISD::SMUL_LOHI;
3251 } else if (HasUMUL_LOHI && !HasMULHU) {
3252 OpToUse = ISD::UMUL_LOHI;
3253 } else if (HasSMUL_LOHI) {
3254 OpToUse = ISD::SMUL_LOHI;
3255 } else if (HasUMUL_LOHI) {
3256 OpToUse = ISD::UMUL_LOHI;
3259 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0);
3263 if (Node->getOpcode() == ISD::MULHS &&
3264 TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
3265 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3269 if (Node->getOpcode() == ISD::MULHU &&
3270 TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) {
3271 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3275 if (Node->getOpcode() == ISD::SDIV &&
3276 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
3277 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(),
3281 if (Node->getOpcode() == ISD::UDIV &&
3282 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
3283 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(),
3288 // Check to see if we have a libcall for this operator.
3289 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3290 bool isSigned = false;
3291 switch (Node->getOpcode()) {
3294 if (VT == MVT::i32) {
3295 LC = Node->getOpcode() == ISD::UDIV
3296 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3297 isSigned = Node->getOpcode() == ISD::SDIV;
3302 LC = RTLIB::MUL_I32;
3303 else if (VT == MVT::i64)
3304 LC = RTLIB::MUL_I64;
3307 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3308 RTLIB::POW_PPCF128);
3311 LC = GetFPLibCall(VT, RTLIB::DIV_F32, RTLIB::DIV_F64, RTLIB::DIV_F80,
3312 RTLIB::DIV_PPCF128);
3316 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3318 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3322 assert(Node->getValueType(0).isVector() &&
3323 "Cannot expand this binary operator!");
3324 // Expand the operation into a bunch of nasty scalar code.
3325 Result = LegalizeOp(UnrollVectorOp(Op));
3328 case TargetLowering::Promote: {
3329 switch (Node->getOpcode()) {
3330 default: assert(0 && "Do not know how to promote this BinOp!");
3334 MVT OVT = Node->getValueType(0);
3335 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3336 assert(OVT.isVector() && "Cannot promote this BinOp!");
3337 // Bit convert each of the values to the new type.
3338 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3339 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3340 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3341 // Bit convert the result back the original type.
3342 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3350 case ISD::SMUL_LOHI:
3351 case ISD::UMUL_LOHI:
3354 // These nodes will only be produced by target-specific lowering, so
3355 // they shouldn't be here if they aren't legal.
3356 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3357 "This must be legal!");
3359 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3360 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3361 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3364 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3365 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3366 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3367 case Expand: assert(0 && "Not possible");
3369 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3372 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3376 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3378 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3379 default: assert(0 && "Operation not supported");
3380 case TargetLowering::Custom:
3381 Tmp1 = TLI.LowerOperation(Result, DAG);
3382 if (Tmp1.getNode()) Result = Tmp1;
3384 case TargetLowering::Legal: break;
3385 case TargetLowering::Expand: {
3386 // If this target supports fabs/fneg natively and select is cheap,
3387 // do this efficiently.
3388 if (!TLI.isSelectExpensive() &&
3389 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3390 TargetLowering::Legal &&
3391 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3392 TargetLowering::Legal) {
3393 // Get the sign bit of the RHS.
3395 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3396 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3397 SignBit = DAG.getSetCC(TLI.getSetCCResultType(IVT),
3398 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3399 // Get the absolute value of the result.
3400 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3401 // Select between the nabs and abs value based on the sign bit of
3403 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3404 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3407 Result = LegalizeOp(Result);
3411 // Otherwise, do bitwise ops!
3413 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3414 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3415 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3416 Result = LegalizeOp(Result);
3424 Tmp1 = LegalizeOp(Node->getOperand(0));
3425 Tmp2 = LegalizeOp(Node->getOperand(1));
3426 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3427 Tmp3 = Result.getValue(0);
3428 Tmp4 = Result.getValue(1);
3430 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3431 default: assert(0 && "This action is not supported yet!");
3432 case TargetLowering::Legal:
3434 case TargetLowering::Custom:
3435 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3436 if (Tmp1.getNode() != NULL) {
3437 Tmp3 = LegalizeOp(Tmp1);
3438 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3442 // Since this produces two values, make sure to remember that we legalized
3444 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3445 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3446 return Op.getResNo() ? Tmp4 : Tmp3;
3450 Tmp1 = LegalizeOp(Node->getOperand(0));
3451 Tmp2 = LegalizeOp(Node->getOperand(1));
3452 Tmp3 = LegalizeOp(Node->getOperand(2));
3453 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3454 Tmp3 = Result.getValue(0);
3455 Tmp4 = Result.getValue(1);
3457 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3458 default: assert(0 && "This action is not supported yet!");
3459 case TargetLowering::Legal:
3461 case TargetLowering::Custom:
3462 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3463 if (Tmp1.getNode() != NULL) {
3464 Tmp3 = LegalizeOp(Tmp1);
3465 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3469 // Since this produces two values, make sure to remember that we legalized
3471 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3472 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3473 return Op.getResNo() ? Tmp4 : Tmp3;
3475 case ISD::BUILD_PAIR: {
3476 MVT PairTy = Node->getValueType(0);
3477 // TODO: handle the case where the Lo and Hi operands are not of legal type
3478 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3479 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3480 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3481 case TargetLowering::Promote:
3482 case TargetLowering::Custom:
3483 assert(0 && "Cannot promote/custom this yet!");
3484 case TargetLowering::Legal:
3485 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3486 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3488 case TargetLowering::Expand:
3489 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3490 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3491 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3492 DAG.getConstant(PairTy.getSizeInBits()/2,
3493 TLI.getShiftAmountTy()));
3494 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3503 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3504 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3506 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3507 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3508 case TargetLowering::Custom:
3511 case TargetLowering::Legal:
3512 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3514 Tmp1 = TLI.LowerOperation(Result, DAG);
3515 if (Tmp1.getNode()) Result = Tmp1;
3518 case TargetLowering::Expand: {
3519 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3520 bool isSigned = DivOpc == ISD::SDIV;
3521 MVT VT = Node->getValueType(0);
3523 // See if remainder can be lowered using two-result operations.
3524 SDVTList VTs = DAG.getVTList(VT, VT);
3525 if (Node->getOpcode() == ISD::SREM &&
3526 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
3527 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3530 if (Node->getOpcode() == ISD::UREM &&
3531 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
3532 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3536 if (VT.isInteger()) {
3537 if (TLI.getOperationAction(DivOpc, VT) ==
3538 TargetLowering::Legal) {
3540 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3541 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3542 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3543 } else if (VT.isVector()) {
3544 Result = LegalizeOp(UnrollVectorOp(Op));
3546 assert(VT == MVT::i32 &&
3547 "Cannot expand this binary operator!");
3548 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3549 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3551 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3554 assert(VT.isFloatingPoint() &&
3555 "remainder op must have integer or floating-point type");
3556 if (VT.isVector()) {
3557 Result = LegalizeOp(UnrollVectorOp(Op));
3559 // Floating point mod -> fmod libcall.
3560 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3561 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3563 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3571 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3572 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3574 MVT VT = Node->getValueType(0);
3575 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3576 default: assert(0 && "This action is not supported yet!");
3577 case TargetLowering::Custom:
3580 case TargetLowering::Legal:
3581 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3582 Result = Result.getValue(0);
3583 Tmp1 = Result.getValue(1);
3586 Tmp2 = TLI.LowerOperation(Result, DAG);
3587 if (Tmp2.getNode()) {
3588 Result = LegalizeOp(Tmp2);
3589 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3593 case TargetLowering::Expand: {
3594 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3595 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3596 // Increment the pointer, VAList, to the next vaarg
3597 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3598 DAG.getConstant(TLI.getTargetData()->
3599 getTypePaddedSize(VT.getTypeForMVT()),
3600 TLI.getPointerTy()));
3601 // Store the incremented VAList to the legalized pointer
3602 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3603 // Load the actual argument out of the pointer VAList
3604 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3605 Tmp1 = LegalizeOp(Result.getValue(1));
3606 Result = LegalizeOp(Result);
3610 // Since VAARG produces two values, make sure to remember that we
3611 // legalized both of them.
3612 AddLegalizedOperand(SDValue(Node, 0), Result);
3613 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3614 return Op.getResNo() ? Tmp1 : Result;
3618 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3619 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3620 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3622 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3623 default: assert(0 && "This action is not supported yet!");
3624 case TargetLowering::Custom:
3627 case TargetLowering::Legal:
3628 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3629 Node->getOperand(3), Node->getOperand(4));
3631 Tmp1 = TLI.LowerOperation(Result, DAG);
3632 if (Tmp1.getNode()) Result = Tmp1;
3635 case TargetLowering::Expand:
3636 // This defaults to loading a pointer from the input and storing it to the
3637 // output, returning the chain.
3638 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3639 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3640 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3641 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3647 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3648 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3650 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3651 default: assert(0 && "This action is not supported yet!");
3652 case TargetLowering::Custom:
3655 case TargetLowering::Legal:
3656 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3658 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3659 if (Tmp1.getNode()) Result = Tmp1;
3662 case TargetLowering::Expand:
3663 Result = Tmp1; // Default to a no-op, return the chain
3669 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3670 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3672 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3674 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3675 default: assert(0 && "This action is not supported yet!");
3676 case TargetLowering::Legal: break;
3677 case TargetLowering::Custom:
3678 Tmp1 = TLI.LowerOperation(Result, DAG);
3679 if (Tmp1.getNode()) Result = Tmp1;
3686 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3687 Tmp2 = LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(1))); // RHS
3688 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3689 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3691 assert(0 && "ROTL/ROTR legalize operation not supported");
3693 case TargetLowering::Legal:
3695 case TargetLowering::Custom:
3696 Tmp1 = TLI.LowerOperation(Result, DAG);
3697 if (Tmp1.getNode()) Result = Tmp1;
3699 case TargetLowering::Promote:
3700 assert(0 && "Do not know how to promote ROTL/ROTR");
3702 case TargetLowering::Expand:
3703 assert(0 && "Do not know how to expand ROTL/ROTR");
3709 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3710 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3711 case TargetLowering::Custom:
3712 assert(0 && "Cannot custom legalize this yet!");
3713 case TargetLowering::Legal:
3714 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3716 case TargetLowering::Promote: {
3717 MVT OVT = Tmp1.getValueType();
3718 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3719 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3721 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3722 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3723 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3724 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3727 case TargetLowering::Expand:
3728 Result = ExpandBSWAP(Tmp1, dl);
3736 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3737 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3738 case TargetLowering::Custom:
3739 case TargetLowering::Legal:
3740 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3741 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3742 TargetLowering::Custom) {
3743 Tmp1 = TLI.LowerOperation(Result, DAG);
3744 if (Tmp1.getNode()) {
3749 case TargetLowering::Promote: {
3750 MVT OVT = Tmp1.getValueType();
3751 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3753 // Zero extend the argument.
3754 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3755 // Perform the larger operation, then subtract if needed.
3756 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3757 switch (Node->getOpcode()) {
3762 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3763 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
3764 DAG.getConstant(NVT.getSizeInBits(), NVT),
3766 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3767 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3770 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3771 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3772 DAG.getConstant(NVT.getSizeInBits() -
3773 OVT.getSizeInBits(), NVT));
3778 case TargetLowering::Expand:
3779 Result = ExpandBitCount(Node->getOpcode(), Tmp1, dl);
3799 case ISD::FNEARBYINT:
3800 Tmp1 = LegalizeOp(Node->getOperand(0));
3801 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3802 case TargetLowering::Promote:
3803 case TargetLowering::Custom:
3806 case TargetLowering::Legal:
3807 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3809 Tmp1 = TLI.LowerOperation(Result, DAG);
3810 if (Tmp1.getNode()) Result = Tmp1;
3813 case TargetLowering::Expand:
3814 switch (Node->getOpcode()) {
3815 default: assert(0 && "Unreachable!");
3817 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3818 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3819 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3822 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3823 MVT VT = Node->getValueType(0);
3824 Tmp2 = DAG.getConstantFP(0.0, VT);
3825 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()),
3826 Tmp1, Tmp2, ISD::SETUGT);
3827 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3828 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3843 case ISD::FNEARBYINT: {
3844 MVT VT = Node->getValueType(0);
3846 // Expand unsupported unary vector operators by unrolling them.
3847 if (VT.isVector()) {
3848 Result = LegalizeOp(UnrollVectorOp(Op));
3852 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3853 switch(Node->getOpcode()) {
3855 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3856 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3859 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3860 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3863 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3864 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3867 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3868 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3871 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3872 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3875 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3876 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3879 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3880 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3883 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3884 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3887 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3888 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3891 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3892 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3895 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3896 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3899 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3900 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3902 case ISD::FNEARBYINT:
3903 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3904 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3907 default: assert(0 && "Unreachable!");
3910 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3918 MVT VT = Node->getValueType(0);
3920 // Expand unsupported unary vector operators by unrolling them.
3921 if (VT.isVector()) {
3922 Result = LegalizeOp(UnrollVectorOp(Op));
3926 // We always lower FPOWI into a libcall. No target support for it yet.
3927 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3928 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3930 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3933 case ISD::BIT_CONVERT:
3934 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3935 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3936 Node->getValueType(0), dl);
3937 } else if (Op.getOperand(0).getValueType().isVector()) {
3938 // The input has to be a vector type, we have to either scalarize it, pack
3939 // it, or convert it based on whether the input vector type is legal.
3940 SDNode *InVal = Node->getOperand(0).getNode();
3941 int InIx = Node->getOperand(0).getResNo();
3942 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3943 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3945 // Figure out if there is a simple type corresponding to this Vector
3946 // type. If so, convert to the vector type.
3947 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3948 if (TLI.isTypeLegal(TVT)) {
3949 // Turn this into a bit convert of the vector input.
3950 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3951 LegalizeOp(Node->getOperand(0)));
3953 } else if (NumElems == 1) {
3954 // Turn this into a bit convert of the scalar input.
3955 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3956 ScalarizeVectorOp(Node->getOperand(0)));
3959 // FIXME: UNIMP! Store then reload
3960 assert(0 && "Cast from unsupported vector type not implemented yet!");
3963 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3964 Node->getOperand(0).getValueType())) {
3965 default: assert(0 && "Unknown operation action!");
3966 case TargetLowering::Expand:
3967 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3968 Node->getValueType(0), dl);
3970 case TargetLowering::Legal:
3971 Tmp1 = LegalizeOp(Node->getOperand(0));
3972 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3977 case ISD::CONVERT_RNDSAT: {
3978 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
3980 default: assert(0 && "Unknown cvt code!");
3991 SDValue DTyOp = Node->getOperand(1);
3992 SDValue STyOp = Node->getOperand(2);
3993 SDValue RndOp = Node->getOperand(3);
3994 SDValue SatOp = Node->getOperand(4);
3995 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3996 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3998 Tmp1 = LegalizeOp(Node->getOperand(0));
3999 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp,
4001 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4002 TargetLowering::Custom) {
4003 Tmp1 = TLI.LowerOperation(Result, DAG);
4004 if (Tmp1.getNode()) Result = Tmp1;
4008 Result = PromoteOp(Node->getOperand(0));
4009 // For FP, make Op1 a i32
4011 Result = DAG.getConvertRndSat(Op.getValueType(), Result,
4012 DTyOp, STyOp, RndOp, SatOp, CvtCode);
4017 } // end switch CvtCode
4020 // Conversion operators. The source and destination have different types.
4021 case ISD::SINT_TO_FP:
4022 case ISD::UINT_TO_FP: {
4023 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
4024 Result = LegalizeINT_TO_FP(Result, isSigned,
4025 Node->getValueType(0), Node->getOperand(0), dl);
4029 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4031 Tmp1 = LegalizeOp(Node->getOperand(0));
4032 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
4033 default: assert(0 && "Unknown TRUNCATE legalization operation action!");
4034 case TargetLowering::Custom:
4037 case TargetLowering::Legal:
4038 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4040 Tmp1 = TLI.LowerOperation(Result, DAG);
4041 if (Tmp1.getNode()) Result = Tmp1;
4044 case TargetLowering::Expand:
4045 assert(Result.getValueType().isVector() && "must be vector type");
4046 // Unroll the truncate. We should do better.
4047 Result = LegalizeOp(UnrollVectorOp(Result));
4051 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4053 // Since the result is legal, we should just be able to truncate the low
4054 // part of the source.
4055 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
4058 Result = PromoteOp(Node->getOperand(0));
4059 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
4064 case ISD::FP_TO_SINT:
4065 case ISD::FP_TO_UINT:
4066 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4068 Tmp1 = LegalizeOp(Node->getOperand(0));
4070 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
4071 default: assert(0 && "Unknown operation action!");
4072 case TargetLowering::Custom:
4075 case TargetLowering::Legal:
4076 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4078 Tmp1 = TLI.LowerOperation(Result, DAG);
4079 if (Tmp1.getNode()) Result = Tmp1;
4082 case TargetLowering::Promote:
4083 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
4084 Node->getOpcode() == ISD::FP_TO_SINT,
4087 case TargetLowering::Expand:
4088 if (Node->getOpcode() == ISD::FP_TO_UINT) {
4089 SDValue True, False;
4090 MVT VT = Node->getOperand(0).getValueType();
4091 MVT NVT = Node->getValueType(0);
4092 const uint64_t zero[] = {0, 0};
4093 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
4094 APInt x = APInt::getSignBit(NVT.getSizeInBits());
4095 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
4096 Tmp2 = DAG.getConstantFP(apf, VT);
4097 Tmp3 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
4098 Node->getOperand(0),
4100 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
4101 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
4102 DAG.getNode(ISD::FSUB, dl, VT,
4103 Node->getOperand(0), Tmp2));
4104 False = DAG.getNode(ISD::XOR, dl, NVT, False,
4105 DAG.getConstant(x, NVT));
4106 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp3, True, False);
4109 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
4115 MVT VT = Op.getValueType();
4116 MVT OVT = Node->getOperand(0).getValueType();
4117 // Convert ppcf128 to i32
4118 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
4119 if (Node->getOpcode() == ISD::FP_TO_SINT) {
4120 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
4121 Node->getOperand(0), DAG.getValueType(MVT::f64));
4122 Result = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Result,
4123 DAG.getIntPtrConstant(1));
4124 Result = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Result);
4126 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
4127 APFloat apf = APFloat(APInt(128, 2, TwoE31));
4128 Tmp2 = DAG.getConstantFP(apf, OVT);
4129 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
4130 // FIXME: generated code sucks.
4131 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Node->getOperand(0),
4133 DAG.getNode(ISD::ADD, dl, MVT::i32,
4134 DAG.getNode(ISD::FP_TO_SINT, dl, VT,
4135 DAG.getNode(ISD::FSUB, dl, OVT,
4136 Node->getOperand(0), Tmp2)),
4137 DAG.getConstant(0x80000000, MVT::i32)),
4138 DAG.getNode(ISD::FP_TO_SINT, dl, VT,
4139 Node->getOperand(0)),
4140 DAG.getCondCode(ISD::SETGE));
4144 // Convert f32 / f64 to i32 / i64 / i128.
4145 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
4146 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
4147 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
4149 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
4153 Tmp1 = PromoteOp(Node->getOperand(0));
4154 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
4155 Result = LegalizeOp(Result);
4160 case ISD::FP_EXTEND: {
4161 MVT DstVT = Op.getValueType();
4162 MVT SrcVT = Op.getOperand(0).getValueType();
4163 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4164 // The only other way we can lower this is to turn it into a STORE,
4165 // LOAD pair, targetting a temporary location (a stack slot).
4166 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT, dl);
4169 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4170 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4172 Tmp1 = LegalizeOp(Node->getOperand(0));
4173 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4176 Tmp1 = PromoteOp(Node->getOperand(0));
4177 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
4182 case ISD::FP_ROUND: {
4183 MVT DstVT = Op.getValueType();
4184 MVT SrcVT = Op.getOperand(0).getValueType();
4185 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4186 if (SrcVT == MVT::ppcf128) {
4188 ExpandOp(Node->getOperand(0), Lo, Result);
4189 // Round it the rest of the way (e.g. to f32) if needed.
4190 if (DstVT!=MVT::f64)
4191 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
4194 // The only other way we can lower this is to turn it into a STORE,
4195 // LOAD pair, targetting a temporary location (a stack slot).
4196 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT, dl);
4199 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4200 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4202 Tmp1 = LegalizeOp(Node->getOperand(0));
4203 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4206 Tmp1 = PromoteOp(Node->getOperand(0));
4207 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
4208 Node->getOperand(1));
4213 case ISD::ANY_EXTEND:
4214 case ISD::ZERO_EXTEND:
4215 case ISD::SIGN_EXTEND:
4216 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4217 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4219 Tmp1 = LegalizeOp(Node->getOperand(0));
4220 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4221 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4222 TargetLowering::Custom) {
4223 Tmp1 = TLI.LowerOperation(Result, DAG);
4224 if (Tmp1.getNode()) Result = Tmp1;
4228 switch (Node->getOpcode()) {
4229 case ISD::ANY_EXTEND:
4230 Tmp1 = PromoteOp(Node->getOperand(0));
4231 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
4233 case ISD::ZERO_EXTEND:
4234 Result = PromoteOp(Node->getOperand(0));
4235 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
4236 Result = DAG.getZeroExtendInReg(Result,
4237 Node->getOperand(0).getValueType());
4239 case ISD::SIGN_EXTEND:
4240 Result = PromoteOp(Node->getOperand(0));
4241 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
4242 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4244 DAG.getValueType(Node->getOperand(0).getValueType()));
4249 case ISD::FP_ROUND_INREG:
4250 case ISD::SIGN_EXTEND_INREG: {
4251 Tmp1 = LegalizeOp(Node->getOperand(0));
4252 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
4254 // If this operation is not supported, convert it to a shl/shr or load/store
4256 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
4257 default: assert(0 && "This action not supported for this op yet!");
4258 case TargetLowering::Legal:
4259 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4261 case TargetLowering::Expand:
4262 // If this is an integer extend and shifts are supported, do that.
4263 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
4264 // NOTE: we could fall back on load/store here too for targets without
4265 // SAR. However, it is doubtful that any exist.
4266 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
4267 ExtraVT.getSizeInBits();
4268 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
4269 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
4270 Node->getOperand(0), ShiftCst);
4271 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
4273 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
4274 // The only way we can lower this is to turn it into a TRUNCSTORE,
4275 // EXTLOAD pair, targetting a temporary location (a stack slot).
4277 // NOTE: there is a choice here between constantly creating new stack
4278 // slots and always reusing the same one. We currently always create
4279 // new ones, as reuse may inhibit scheduling.
4280 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
4281 Node->getValueType(0), dl);
4283 assert(0 && "Unknown op");
4289 case ISD::TRAMPOLINE: {
4291 for (unsigned i = 0; i != 6; ++i)
4292 Ops[i] = LegalizeOp(Node->getOperand(i));
4293 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
4294 // The only option for this node is to custom lower it.
4295 Result = TLI.LowerOperation(Result, DAG);
4296 assert(Result.getNode() && "Should always custom lower!");
4298 // Since trampoline produces two values, make sure to remember that we
4299 // legalized both of them.
4300 Tmp1 = LegalizeOp(Result.getValue(1));
4301 Result = LegalizeOp(Result);
4302 AddLegalizedOperand(SDValue(Node, 0), Result);
4303 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
4304 return Op.getResNo() ? Tmp1 : Result;
4306 case ISD::FLT_ROUNDS_: {
4307 MVT VT = Node->getValueType(0);
4308 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4309 default: assert(0 && "This action not supported for this op yet!");
4310 case TargetLowering::Custom:
4311 Result = TLI.LowerOperation(Op, DAG);
4312 if (Result.getNode()) break;
4314 case TargetLowering::Legal:
4315 // If this operation is not supported, lower it to constant 1
4316 Result = DAG.getConstant(1, VT);
4322 MVT VT = Node->getValueType(0);
4323 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4324 default: assert(0 && "This action not supported for this op yet!");
4325 case TargetLowering::Legal:
4326 Tmp1 = LegalizeOp(Node->getOperand(0));
4327 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4329 case TargetLowering::Custom:
4330 Result = TLI.LowerOperation(Op, DAG);
4331 if (Result.getNode()) break;
4333 case TargetLowering::Expand:
4334 // If this operation is not supported, lower it to 'abort()' call
4335 Tmp1 = LegalizeOp(Node->getOperand(0));
4336 TargetLowering::ArgListTy Args;
4337 std::pair<SDValue,SDValue> CallResult =
4338 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4339 false, false, false, false, CallingConv::C, false,
4340 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4342 Result = CallResult.second;
4350 MVT VT = Node->getValueType(0);
4351 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4352 default: assert(0 && "This action not supported for this op yet!");
4353 case TargetLowering::Custom:
4354 Result = TLI.LowerOperation(Op, DAG);
4355 if (Result.getNode()) break;
4357 case TargetLowering::Legal: {
4358 SDValue LHS = LegalizeOp(Node->getOperand(0));
4359 SDValue RHS = LegalizeOp(Node->getOperand(1));
4361 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
4362 ISD::ADD : ISD::SUB, LHS.getValueType(),
4364 MVT OType = Node->getValueType(1);
4366 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
4368 // LHSSign -> LHS >= 0
4369 // RHSSign -> RHS >= 0
4370 // SumSign -> Sum >= 0
4373 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4375 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
4377 SDValue LHSSign = DAG.getSetCC(OType, LHS, Zero, ISD::SETGE);
4378 SDValue RHSSign = DAG.getSetCC(OType, RHS, Zero, ISD::SETGE);
4379 SDValue SignsMatch = DAG.getSetCC(OType, LHSSign, RHSSign,
4380 Node->getOpcode() == ISD::SADDO ?
4381 ISD::SETEQ : ISD::SETNE);
4383 SDValue SumSign = DAG.getSetCC(OType, Sum, Zero, ISD::SETGE);
4384 SDValue SumSignNE = DAG.getSetCC(OType, LHSSign, SumSign, ISD::SETNE);
4386 SDValue Cmp = DAG.getNode(ISD::AND, OType, SignsMatch, SumSignNE);
4388 MVT ValueVTs[] = { LHS.getValueType(), OType };
4389 SDValue Ops[] = { Sum, Cmp };
4391 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2),
4393 SDNode *RNode = Result.getNode();
4394 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4395 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4404 MVT VT = Node->getValueType(0);
4405 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4406 default: assert(0 && "This action not supported for this op yet!");
4407 case TargetLowering::Custom:
4408 Result = TLI.LowerOperation(Op, DAG);
4409 if (Result.getNode()) break;
4411 case TargetLowering::Legal: {
4412 SDValue LHS = LegalizeOp(Node->getOperand(0));
4413 SDValue RHS = LegalizeOp(Node->getOperand(1));
4415 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
4416 ISD::ADD : ISD::SUB, LHS.getValueType(),
4418 MVT OType = Node->getValueType(1);
4419 SDValue Cmp = DAG.getSetCC(OType, Sum, LHS,
4420 Node->getOpcode () == ISD::UADDO ?
4421 ISD::SETULT : ISD::SETUGT);
4423 MVT ValueVTs[] = { LHS.getValueType(), OType };
4424 SDValue Ops[] = { Sum, Cmp };
4426 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2),
4428 SDNode *RNode = Result.getNode();
4429 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4430 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4439 MVT VT = Node->getValueType(0);
4440 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4441 default: assert(0 && "This action is not supported at all!");
4442 case TargetLowering::Custom:
4443 Result = TLI.LowerOperation(Op, DAG);
4444 if (Result.getNode()) break;
4446 case TargetLowering::Legal:
4447 // FIXME: According to Hacker's Delight, this can be implemented in
4448 // target independent lowering, but it would be inefficient, since it
4449 // requires a division + a branch.
4450 assert(0 && "Target independent lowering is not supported for SMULO/UMULO!");
4458 assert(Result.getValueType() == Op.getValueType() &&
4459 "Bad legalization!");
4461 // Make sure that the generated code is itself legal.
4463 Result = LegalizeOp(Result);
4465 // Note that LegalizeOp may be reentered even from single-use nodes, which
4466 // means that we always must cache transformed nodes.
4467 AddLegalizedOperand(Op, Result);
4471 /// PromoteOp - Given an operation that produces a value in an invalid type,
4472 /// promote it to compute the value into a larger type. The produced value will
4473 /// have the correct bits for the low portion of the register, but no guarantee
4474 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4475 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4476 MVT VT = Op.getValueType();
4477 MVT NVT = TLI.getTypeToTransformTo(VT);
4478 assert(getTypeAction(VT) == Promote &&
4479 "Caller should expand or legalize operands that are not promotable!");
4480 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4481 "Cannot promote to smaller type!");
4483 SDValue Tmp1, Tmp2, Tmp3;
4485 SDNode *Node = Op.getNode();
4486 DebugLoc dl = Node->getDebugLoc();
4488 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4489 if (I != PromotedNodes.end()) return I->second;
4491 switch (Node->getOpcode()) {
4492 case ISD::CopyFromReg:
4493 assert(0 && "CopyFromReg must be legal!");
4496 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4498 assert(0 && "Do not know how to promote this operator!");
4501 Result = DAG.getNode(ISD::UNDEF, dl, NVT);
4505 Result = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Op);
4507 Result = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Op);
4508 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4510 case ISD::ConstantFP:
4511 Result = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op);
4512 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4516 MVT VT0 = Node->getOperand(0).getValueType();
4517 assert(isTypeLegal(TLI.getSetCCResultType(VT0))
4518 && "SetCC type is not legal??");
4519 Result = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(VT0),
4520 Node->getOperand(0), Node->getOperand(1),
4521 Node->getOperand(2));
4525 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4527 Result = LegalizeOp(Node->getOperand(0));
4528 assert(Result.getValueType().bitsGE(NVT) &&
4529 "This truncation doesn't make sense!");
4530 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4531 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Result);
4534 // The truncation is not required, because we don't guarantee anything
4535 // about high bits anyway.
4536 Result = PromoteOp(Node->getOperand(0));
4539 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4540 // Truncate the low part of the expanded value to the result type
4541 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Tmp1);
4544 case ISD::SIGN_EXTEND:
4545 case ISD::ZERO_EXTEND:
4546 case ISD::ANY_EXTEND:
4547 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4548 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4550 // Input is legal? Just do extend all the way to the larger type.
4551 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0));
4554 // Promote the reg if it's smaller.
4555 Result = PromoteOp(Node->getOperand(0));
4556 // The high bits are not guaranteed to be anything. Insert an extend.
4557 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4558 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
4559 DAG.getValueType(Node->getOperand(0).getValueType()));
4560 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4561 Result = DAG.getZeroExtendInReg(Result, dl,
4562 Node->getOperand(0).getValueType());
4566 case ISD::CONVERT_RNDSAT: {
4567 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4568 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
4569 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
4570 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
4571 "can only promote integers");
4572 Result = DAG.getConvertRndSat(NVT, Node->getOperand(0),
4573 Node->getOperand(1), Node->getOperand(2),
4574 Node->getOperand(3), Node->getOperand(4),
4579 case ISD::BIT_CONVERT:
4580 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4581 Node->getValueType(0), dl);
4582 Result = PromoteOp(Result);
4585 case ISD::FP_EXTEND:
4586 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4588 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4589 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4590 case Promote: assert(0 && "Unreachable with 2 FP types!");
4592 if (Node->getConstantOperandVal(1) == 0) {
4593 // Input is legal? Do an FP_ROUND_INREG.
4594 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Node->getOperand(0),
4595 DAG.getValueType(VT));
4597 // Just remove the truncate, it isn't affecting the value.
4598 Result = DAG.getNode(ISD::FP_ROUND, dl, NVT, Node->getOperand(0),
4599 Node->getOperand(1));
4604 case ISD::SINT_TO_FP:
4605 case ISD::UINT_TO_FP:
4606 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4608 // No extra round required here.
4609 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0));
4613 Result = PromoteOp(Node->getOperand(0));
4614 if (Node->getOpcode() == ISD::SINT_TO_FP)
4615 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(),
4617 DAG.getValueType(Node->getOperand(0).getValueType()));
4619 Result = DAG.getZeroExtendInReg(Result, dl,
4620 Node->getOperand(0).getValueType());
4621 // No extra round required here.
4622 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Result);
4625 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4626 Node->getOperand(0), dl);
4627 // Round if we cannot tolerate excess precision.
4628 if (NoExcessFPPrecision)
4629 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4630 DAG.getValueType(VT));
4635 case ISD::SIGN_EXTEND_INREG:
4636 Result = PromoteOp(Node->getOperand(0));
4637 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
4638 Node->getOperand(1));
4640 case ISD::FP_TO_SINT:
4641 case ISD::FP_TO_UINT:
4642 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4645 Tmp1 = Node->getOperand(0);
4648 // The input result is prerounded, so we don't have to do anything
4650 Tmp1 = PromoteOp(Node->getOperand(0));
4653 // If we're promoting a UINT to a larger size, check to see if the new node
4654 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4655 // we can use that instead. This allows us to generate better code for
4656 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4657 // legal, such as PowerPC.
4658 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4659 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
4660 (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT) ||
4661 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4662 Result = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Tmp1);
4664 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4670 Tmp1 = PromoteOp(Node->getOperand(0));
4671 assert(Tmp1.getValueType() == NVT);
4672 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4673 // NOTE: we do not have to do any extra rounding here for
4674 // NoExcessFPPrecision, because we know the input will have the appropriate
4675 // precision, and these operations don't modify precision at all.
4690 case ISD::FNEARBYINT:
4691 Tmp1 = PromoteOp(Node->getOperand(0));
4692 assert(Tmp1.getValueType() == NVT);
4693 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4694 if (NoExcessFPPrecision)
4695 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4696 DAG.getValueType(VT));
4701 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4702 // directly as well, which may be better.
4703 Tmp1 = PromoteOp(Node->getOperand(0));
4704 Tmp2 = Node->getOperand(1);
4705 if (Node->getOpcode() == ISD::FPOW)
4706 Tmp2 = PromoteOp(Tmp2);
4707 assert(Tmp1.getValueType() == NVT);
4708 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4709 if (NoExcessFPPrecision)
4710 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4711 DAG.getValueType(VT));
4715 case ISD::ATOMIC_CMP_SWAP: {
4716 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4717 Tmp2 = PromoteOp(Node->getOperand(2));
4718 Tmp3 = PromoteOp(Node->getOperand(3));
4719 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
4720 AtomNode->getChain(),
4721 AtomNode->getBasePtr(), Tmp2, Tmp3,
4722 AtomNode->getSrcValue(),
4723 AtomNode->getAlignment());
4724 // Remember that we legalized the chain.
4725 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4728 case ISD::ATOMIC_LOAD_ADD:
4729 case ISD::ATOMIC_LOAD_SUB:
4730 case ISD::ATOMIC_LOAD_AND:
4731 case ISD::ATOMIC_LOAD_OR:
4732 case ISD::ATOMIC_LOAD_XOR:
4733 case ISD::ATOMIC_LOAD_NAND:
4734 case ISD::ATOMIC_LOAD_MIN:
4735 case ISD::ATOMIC_LOAD_MAX:
4736 case ISD::ATOMIC_LOAD_UMIN:
4737 case ISD::ATOMIC_LOAD_UMAX:
4738 case ISD::ATOMIC_SWAP: {
4739 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4740 Tmp2 = PromoteOp(Node->getOperand(2));
4741 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
4742 AtomNode->getChain(),
4743 AtomNode->getBasePtr(), Tmp2,
4744 AtomNode->getSrcValue(),
4745 AtomNode->getAlignment());
4746 // Remember that we legalized the chain.
4747 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4757 // The input may have strange things in the top bits of the registers, but
4758 // these operations don't care. They may have weird bits going out, but
4759 // that too is okay if they are integer operations.
4760 Tmp1 = PromoteOp(Node->getOperand(0));
4761 Tmp2 = PromoteOp(Node->getOperand(1));
4762 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4763 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4768 Tmp1 = PromoteOp(Node->getOperand(0));
4769 Tmp2 = PromoteOp(Node->getOperand(1));
4770 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4771 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4773 // Floating point operations will give excess precision that we may not be
4774 // able to tolerate. If we DO allow excess precision, just leave it,
4775 // otherwise excise it.
4776 // FIXME: Why would we need to round FP ops more than integer ones?
4777 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4778 if (NoExcessFPPrecision)
4779 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4780 DAG.getValueType(VT));
4785 // These operators require that their input be sign extended.
4786 Tmp1 = PromoteOp(Node->getOperand(0));
4787 Tmp2 = PromoteOp(Node->getOperand(1));
4788 if (NVT.isInteger()) {
4789 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
4790 DAG.getValueType(VT));
4791 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2,
4792 DAG.getValueType(VT));
4794 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4796 // Perform FP_ROUND: this is probably overly pessimistic.
4797 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4798 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4799 DAG.getValueType(VT));
4803 case ISD::FCOPYSIGN:
4804 // These operators require that their input be fp extended.
4805 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4806 case Expand: assert(0 && "not implemented");
4807 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4808 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4810 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4811 case Expand: assert(0 && "not implemented");
4812 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4813 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4815 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4817 // Perform FP_ROUND: this is probably overly pessimistic.
4818 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4819 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4820 DAG.getValueType(VT));
4825 // These operators require that their input be zero extended.
4826 Tmp1 = PromoteOp(Node->getOperand(0));
4827 Tmp2 = PromoteOp(Node->getOperand(1));
4828 assert(NVT.isInteger() && "Operators don't apply to FP!");
4829 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
4830 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT);
4831 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4835 Tmp1 = PromoteOp(Node->getOperand(0));
4836 Result = DAG.getNode(ISD::SHL, dl, NVT, Tmp1, Node->getOperand(1));
4839 // The input value must be properly sign extended.
4840 Tmp1 = PromoteOp(Node->getOperand(0));
4841 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
4842 DAG.getValueType(VT));
4843 Result = DAG.getNode(ISD::SRA, dl, NVT, Tmp1, Node->getOperand(1));
4846 // The input value must be properly zero extended.
4847 Tmp1 = PromoteOp(Node->getOperand(0));
4848 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
4849 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, Node->getOperand(1));
4853 Tmp1 = Node->getOperand(0); // Get the chain.
4854 Tmp2 = Node->getOperand(1); // Get the pointer.
4855 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4856 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4857 Result = TLI.LowerOperation(Tmp3, DAG);
4859 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4860 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4861 // Increment the pointer, VAList, to the next vaarg
4862 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
4863 DAG.getConstant(VT.getSizeInBits()/8,
4864 TLI.getPointerTy()));
4865 // Store the incremented VAList to the legalized pointer
4866 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
4867 // Load the actual argument out of the pointer VAList
4868 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Tmp3, VAList, NULL, 0, VT);
4870 // Remember that we legalized the chain.
4871 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4875 LoadSDNode *LD = cast<LoadSDNode>(Node);
4876 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4877 ? ISD::EXTLOAD : LD->getExtensionType();
4878 Result = DAG.getExtLoad(ExtType, dl, NVT,
4879 LD->getChain(), LD->getBasePtr(),
4880 LD->getSrcValue(), LD->getSrcValueOffset(),
4883 LD->getAlignment());
4884 // Remember that we legalized the chain.
4885 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4889 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4890 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4892 MVT VT2 = Tmp2.getValueType();
4893 assert(VT2 == Tmp3.getValueType()
4894 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4895 // Ensure that the resulting node is at least the same size as the operands'
4896 // value types, because we cannot assume that TLI.getSetCCValueType() is
4898 Result = DAG.getNode(ISD::SELECT, dl, VT2, Node->getOperand(0), Tmp2, Tmp3);
4901 case ISD::SELECT_CC:
4902 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4903 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4904 Result = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
4905 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4908 Tmp1 = Node->getOperand(0);
4909 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
4910 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4911 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
4912 DAG.getConstant(NVT.getSizeInBits() -
4914 TLI.getShiftAmountTy()));
4919 // Zero extend the argument
4920 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4921 // Perform the larger operation, then subtract if needed.
4922 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4923 switch(Node->getOpcode()) {
4928 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4929 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
4930 DAG.getConstant(NVT.getSizeInBits(), NVT),
4932 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
4933 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4936 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4937 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4938 DAG.getConstant(NVT.getSizeInBits() -
4939 VT.getSizeInBits(), NVT));
4943 case ISD::EXTRACT_SUBVECTOR:
4944 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4946 case ISD::EXTRACT_VECTOR_ELT:
4947 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4951 assert(Result.getNode() && "Didn't set a result!");
4953 // Make sure the result is itself legal.
4954 Result = LegalizeOp(Result);
4956 // Remember that we promoted this!
4957 AddPromotedOperand(Op, Result);
4961 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4962 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4963 /// based on the vector type. The return type of this matches the element type
4964 /// of the vector, which may not be legal for the target.
4965 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
4966 // We know that operand #0 is the Vec vector. If the index is a constant
4967 // or if the invec is a supported hardware type, we can use it. Otherwise,
4968 // lower to a store then an indexed load.
4969 SDValue Vec = Op.getOperand(0);
4970 SDValue Idx = Op.getOperand(1);
4971 DebugLoc dl = Op.getNode()->getDebugLoc();
4973 MVT TVT = Vec.getValueType();
4974 unsigned NumElems = TVT.getVectorNumElements();
4976 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4977 default: assert(0 && "This action is not supported yet!");
4978 case TargetLowering::Custom: {
4979 Vec = LegalizeOp(Vec);
4980 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4981 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
4986 case TargetLowering::Legal:
4987 if (isTypeLegal(TVT)) {
4988 Vec = LegalizeOp(Vec);
4989 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4993 case TargetLowering::Promote:
4994 assert(TVT.isVector() && "not vector type");
4995 // fall thru to expand since vectors are by default are promote
4996 case TargetLowering::Expand:
5000 if (NumElems == 1) {
5001 // This must be an access of the only element. Return it.
5002 Op = ScalarizeVectorOp(Vec);
5003 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
5004 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
5005 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5007 SplitVectorOp(Vec, Lo, Hi);
5008 if (CIdx->getZExtValue() < NumLoElts) {
5012 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
5013 Idx.getValueType());
5016 // It's now an extract from the appropriate high or low part. Recurse.
5017 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5018 Op = ExpandEXTRACT_VECTOR_ELT(Op);
5020 // Store the value to a temporary stack slot, then LOAD the scalar
5021 // element back out.
5022 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
5023 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
5025 // Add the offset to the index.
5026 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
5027 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
5028 DAG.getConstant(EltSize, Idx.getValueType()));
5030 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
5031 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
5033 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
5035 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
5037 Op = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0);
5042 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
5043 /// we assume the operation can be split if it is not already legal.
5044 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
5045 // We know that operand #0 is the Vec vector. For now we assume the index
5046 // is a constant and that the extracted result is a supported hardware type.
5047 SDValue Vec = Op.getOperand(0);
5048 SDValue Idx = LegalizeOp(Op.getOperand(1));
5050 unsigned NumElems = Vec.getValueType().getVectorNumElements();
5052 if (NumElems == Op.getValueType().getVectorNumElements()) {
5053 // This must be an access of the desired vector length. Return it.
5057 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5059 SplitVectorOp(Vec, Lo, Hi);
5060 if (CIdx->getZExtValue() < NumElems/2) {
5064 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
5065 Idx.getValueType());
5068 // It's now an extract from the appropriate high or low part. Recurse.
5069 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5070 return ExpandEXTRACT_SUBVECTOR(Op);
5073 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
5074 /// with condition CC on the current target. This usually involves legalizing
5075 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
5076 /// there may be no choice but to create a new SetCC node to represent the
5077 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
5078 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
5079 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
5083 SDValue Tmp1, Tmp2, Tmp3, Result;
5085 switch (getTypeAction(LHS.getValueType())) {
5087 Tmp1 = LegalizeOp(LHS); // LHS
5088 Tmp2 = LegalizeOp(RHS); // RHS
5091 Tmp1 = PromoteOp(LHS); // LHS
5092 Tmp2 = PromoteOp(RHS); // RHS
5094 // If this is an FP compare, the operands have already been extended.
5095 if (LHS.getValueType().isInteger()) {
5096 MVT VT = LHS.getValueType();
5097 MVT NVT = TLI.getTypeToTransformTo(VT);
5099 // Otherwise, we have to insert explicit sign or zero extends. Note
5100 // that we could insert sign extends for ALL conditions, but zero extend
5101 // is cheaper on many machines (an AND instead of two shifts), so prefer
5103 switch (cast<CondCodeSDNode>(CC)->get()) {
5104 default: assert(0 && "Unknown integer comparison!");
5111 // ALL of these operations will work if we either sign or zero extend
5112 // the operands (including the unsigned comparisons!). Zero extend is
5113 // usually a simpler/cheaper operation, so prefer it.
5114 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
5115 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT);
5121 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
5122 DAG.getValueType(VT));
5123 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2,
5124 DAG.getValueType(VT));
5125 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
5126 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
5132 MVT VT = LHS.getValueType();
5133 if (VT == MVT::f32 || VT == MVT::f64) {
5134 // Expand into one or more soft-fp libcall(s).
5135 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
5136 switch (cast<CondCodeSDNode>(CC)->get()) {
5139 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5143 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
5147 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5151 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5155 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5159 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5162 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5165 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
5168 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5169 switch (cast<CondCodeSDNode>(CC)->get()) {
5171 // SETONE = SETOLT | SETOGT
5172 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5175 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5178 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5181 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5184 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5187 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5189 default: assert(0 && "Unsupported FP setcc!");
5194 SDValue Ops[2] = { LHS, RHS };
5195 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2, dl).getNode(),
5196 false /*sign irrelevant*/, Dummy);
5197 Tmp2 = DAG.getConstant(0, MVT::i32);
5198 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
5199 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
5200 Tmp1 = DAG.getNode(ISD::SETCC, dl,
5201 TLI.getSetCCResultType(Tmp1.getValueType()),
5203 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2, dl).getNode(),
5204 false /*sign irrelevant*/, Dummy);
5205 Tmp2 = DAG.getNode(ISD::SETCC, dl,
5206 TLI.getSetCCResultType(LHS.getValueType()), LHS,
5207 Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
5208 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5211 LHS = LegalizeOp(Tmp1);
5216 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5217 ExpandOp(LHS, LHSLo, LHSHi);
5218 ExpandOp(RHS, RHSLo, RHSHi);
5219 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5221 if (VT==MVT::ppcf128) {
5222 // FIXME: This generated code sucks. We want to generate
5223 // FCMPU crN, hi1, hi2
5225 // FCMPU crN, lo1, lo2
5226 // The following can be improved, but not that much.
5227 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5228 LHSHi, RHSHi, ISD::SETOEQ);
5229 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
5230 LHSLo, RHSLo, CCCode);
5231 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5232 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5233 LHSHi, RHSHi, ISD::SETUNE);
5234 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5235 LHSHi, RHSHi, CCCode);
5236 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5237 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3);
5246 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
5247 if (RHSCST->isAllOnesValue()) {
5248 // Comparison to -1.
5249 Tmp1 = DAG.getNode(ISD::AND, dl,LHSLo.getValueType(), LHSLo, LHSHi);
5254 Tmp1 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
5255 Tmp2 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
5256 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5257 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
5260 // If this is a comparison of the sign bit, just look at the top part.
5262 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
5263 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
5264 CST->isNullValue()) || // X < 0
5265 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
5266 CST->isAllOnesValue())) { // X > -1
5272 // FIXME: This generated code sucks.
5273 ISD::CondCode LowCC;
5275 default: assert(0 && "Unknown integer setcc!");
5277 case ISD::SETULT: LowCC = ISD::SETULT; break;
5279 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5281 case ISD::SETULE: LowCC = ISD::SETULE; break;
5283 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5286 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
5287 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
5288 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
5290 // NOTE: on targets without efficient SELECT of bools, we can always use
5291 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5292 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
5293 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
5294 LHSLo, RHSLo, LowCC, false, DagCombineInfo);
5295 if (!Tmp1.getNode())
5296 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
5297 LHSLo, RHSLo, LowCC);
5298 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5299 LHSHi, RHSHi, CCCode, false, DagCombineInfo);
5300 if (!Tmp2.getNode())
5301 Tmp2 = DAG.getNode(ISD::SETCC, dl,
5302 TLI.getSetCCResultType(LHSHi.getValueType()),
5305 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
5306 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
5307 if ((Tmp1C && Tmp1C->isNullValue()) ||
5308 (Tmp2C && Tmp2C->isNullValue() &&
5309 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
5310 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
5311 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
5312 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
5313 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
5314 // low part is known false, returns high part.
5315 // For LE / GE, if high part is known false, ignore the low part.
5316 // For LT / GT, if high part is known true, ignore the low part.
5320 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5321 LHSHi, RHSHi, ISD::SETEQ, false,
5323 if (!Result.getNode())
5324 Result=DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5325 LHSHi, RHSHi, ISD::SETEQ);
5326 Result = LegalizeOp(DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
5327 Result, Tmp1, Tmp2));
5338 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
5339 /// condition code CC on the current target. This routine assumes LHS and rHS
5340 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
5341 /// illegal condition code into AND / OR of multiple SETCC values.
5342 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
5343 SDValue &LHS, SDValue &RHS,
5346 MVT OpVT = LHS.getValueType();
5347 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5348 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
5349 default: assert(0 && "Unknown condition code action!");
5350 case TargetLowering::Legal:
5353 case TargetLowering::Expand: {
5354 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
5357 default: assert(0 && "Don't know how to expand this condition!"); abort();
5358 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
5359 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5360 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5361 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5362 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5363 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5364 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5365 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5366 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5367 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5368 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5369 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5370 // FIXME: Implement more expansions.
5373 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
5374 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
5375 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
5383 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
5384 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
5385 /// a load from the stack slot to DestVT, extending it if needed.
5386 /// The resultant code need not be legal.
5387 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
5391 // Create the stack frame object.
5392 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
5393 SrcOp.getValueType().getTypeForMVT());
5394 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
5396 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
5397 int SPFI = StackPtrFI->getIndex();
5398 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
5400 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
5401 unsigned SlotSize = SlotVT.getSizeInBits();
5402 unsigned DestSize = DestVT.getSizeInBits();
5403 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
5404 DestVT.getTypeForMVT());
5406 // Emit a store to the stack slot. Use a truncstore if the input value is
5407 // later than DestVT.
5410 if (SrcSize > SlotSize)
5411 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
5412 SV, 0, SlotVT, false, SrcAlign);
5414 assert(SrcSize == SlotSize && "Invalid store");
5415 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
5416 SV, 0, false, SrcAlign);
5419 // Result is a load from the stack slot.
5420 if (SlotSize == DestSize)
5421 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign);
5423 assert(SlotSize < DestSize && "Unknown extension!");
5424 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
5428 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
5429 DebugLoc dl = Node->getDebugLoc();
5430 // Create a vector sized/aligned stack slot, store the value to element #0,
5431 // then load the whole vector back out.
5432 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
5434 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
5435 int SPFI = StackPtrFI->getIndex();
5437 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(0),
5439 PseudoSourceValue::getFixedStack(SPFI), 0);
5440 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
5441 PseudoSourceValue::getFixedStack(SPFI), 0);
5445 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
5446 /// support the operation, but do support the resultant vector type.
5447 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
5449 // If the only non-undef value is the low element, turn this into a
5450 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
5451 unsigned NumElems = Node->getNumOperands();
5452 bool isOnlyLowElement = true;
5453 SDValue SplatValue = Node->getOperand(0);
5454 DebugLoc dl = Node->getDebugLoc();
5456 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
5457 // and use a bitmask instead of a list of elements.
5458 std::map<SDValue, std::vector<unsigned> > Values;
5459 Values[SplatValue].push_back(0);
5460 bool isConstant = true;
5461 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
5462 SplatValue.getOpcode() != ISD::UNDEF)
5465 for (unsigned i = 1; i < NumElems; ++i) {
5466 SDValue V = Node->getOperand(i);
5467 Values[V].push_back(i);
5468 if (V.getOpcode() != ISD::UNDEF)
5469 isOnlyLowElement = false;
5470 if (SplatValue != V)
5471 SplatValue = SDValue(0,0);
5473 // If this isn't a constant element or an undef, we can't use a constant
5475 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
5476 V.getOpcode() != ISD::UNDEF)
5480 if (isOnlyLowElement) {
5481 // If the low element is an undef too, then this whole things is an undef.
5482 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
5483 return DAG.getNode(ISD::UNDEF, dl, Node->getValueType(0));
5484 // Otherwise, turn this into a scalar_to_vector node.
5485 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, Node->getValueType(0),
5486 Node->getOperand(0));
5489 // If all elements are constants, create a load from the constant pool.
5491 MVT VT = Node->getValueType(0);
5492 std::vector<Constant*> CV;
5493 for (unsigned i = 0, e = NumElems; i != e; ++i) {
5494 if (ConstantFPSDNode *V =
5495 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
5496 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
5497 } else if (ConstantSDNode *V =
5498 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
5499 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
5501 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
5503 Node->getOperand(0).getValueType().getTypeForMVT();
5504 CV.push_back(UndefValue::get(OpNTy));
5507 Constant *CP = ConstantVector::get(CV);
5508 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5509 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5510 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5511 PseudoSourceValue::getConstantPool(), 0,
5515 if (SplatValue.getNode()) { // Splat of one value?
5516 // Build the shuffle constant vector: <0, 0, 0, 0>
5517 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5518 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5519 std::vector<SDValue> ZeroVec(NumElems, Zero);
5520 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
5521 &ZeroVec[0], ZeroVec.size());
5523 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5524 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5525 // Get the splatted value into the low element of a vector register.
5527 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5528 Node->getValueType(0), SplatValue);
5530 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5531 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,
5532 Node->getValueType(0), LowValVec,
5533 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
5538 // If there are only two unique elements, we may be able to turn this into a
5540 if (Values.size() == 2) {
5541 // Get the two values in deterministic order.
5542 SDValue Val1 = Node->getOperand(1);
5544 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5545 if (MI->first != Val1)
5548 Val2 = (++MI)->first;
5550 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5551 // vector shuffle has the undef vector on the RHS.
5552 if (Val1.getOpcode() == ISD::UNDEF)
5553 std::swap(Val1, Val2);
5555 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5556 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5557 MVT MaskEltVT = MaskVT.getVectorElementType();
5558 std::vector<SDValue> MaskVec(NumElems);
5560 // Set elements of the shuffle mask for Val1.
5561 std::vector<unsigned> &Val1Elts = Values[Val1];
5562 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5563 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5565 // Set elements of the shuffle mask for Val2.
5566 std::vector<unsigned> &Val2Elts = Values[Val2];
5567 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5568 if (Val2.getOpcode() != ISD::UNDEF)
5569 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5571 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, dl, MaskEltVT);
5573 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
5574 &MaskVec[0], MaskVec.size());
5576 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5577 if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR,
5578 Node->getValueType(0)) &&
5579 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5580 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,Node->getValueType(0), Val1);
5581 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,Node->getValueType(0), Val2);
5582 SDValue Ops[] = { Val1, Val2, ShuffleMask };
5584 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5585 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,Node->getValueType(0), Ops, 3);
5589 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5590 // aligned object on the stack, store each element into it, then load
5591 // the result as a vector.
5592 MVT VT = Node->getValueType(0);
5593 // Create the stack frame object.
5594 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5595 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
5596 const Value *SV = PseudoSourceValue::getFixedStack(FI);
5598 // Emit a store of each element to the stack slot.
5599 SmallVector<SDValue, 8> Stores;
5600 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5601 // Store (in the right endianness) the elements to memory.
5602 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5603 // Ignore undef elements.
5604 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5606 unsigned Offset = TypeByteSize*i;
5608 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5609 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
5611 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
5616 if (!Stores.empty()) // Not all undef elements?
5617 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5618 &Stores[0], Stores.size());
5620 StoreChain = DAG.getEntryNode();
5622 // Result is a load from the stack slot.
5623 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0);
5626 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5627 SDValue Op, SDValue Amt,
5628 SDValue &Lo, SDValue &Hi,
5630 // Expand the subcomponents.
5632 ExpandOp(Op, LHSL, LHSH);
5634 SDValue Ops[] = { LHSL, LHSH, Amt };
5635 MVT VT = LHSL.getValueType();
5636 Lo = DAG.getNode(NodeOp, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5637 Hi = Lo.getValue(1);
5641 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5642 /// smaller elements. If we can't find a way that is more efficient than a
5643 /// libcall on this target, return false. Otherwise, return true with the
5644 /// low-parts expanded into Lo and Hi.
5645 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5646 SDValue &Lo, SDValue &Hi,
5648 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5649 "This is not a shift!");
5651 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5652 SDValue ShAmt = LegalizeOp(Amt);
5653 MVT ShTy = ShAmt.getValueType();
5654 unsigned ShBits = ShTy.getSizeInBits();
5655 unsigned VTBits = Op.getValueType().getSizeInBits();
5656 unsigned NVTBits = NVT.getSizeInBits();
5658 // Handle the case when Amt is an immediate.
5659 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5660 unsigned Cst = CN->getZExtValue();
5661 // Expand the incoming operand to be shifted, so that we have its parts
5663 ExpandOp(Op, InL, InH);
5667 Lo = DAG.getConstant(0, NVT);
5668 Hi = DAG.getConstant(0, NVT);
5669 } else if (Cst > NVTBits) {
5670 Lo = DAG.getConstant(0, NVT);
5671 Hi = DAG.getNode(ISD::SHL, dl,
5672 NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5673 } else if (Cst == NVTBits) {
5674 Lo = DAG.getConstant(0, NVT);
5677 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Cst, ShTy));
5678 Hi = DAG.getNode(ISD::OR, dl, NVT,
5679 DAG.getNode(ISD::SHL, dl, NVT, InH, DAG.getConstant(Cst, ShTy)),
5680 DAG.getNode(ISD::SRL, dl, NVT, InL,
5681 DAG.getConstant(NVTBits-Cst, ShTy)));
5686 Lo = DAG.getConstant(0, NVT);
5687 Hi = DAG.getConstant(0, NVT);
5688 } else if (Cst > NVTBits) {
5689 Lo = DAG.getNode(ISD::SRL, dl, NVT,
5690 InH, DAG.getConstant(Cst-NVTBits,ShTy));
5691 Hi = DAG.getConstant(0, NVT);
5692 } else if (Cst == NVTBits) {
5694 Hi = DAG.getConstant(0, NVT);
5696 Lo = DAG.getNode(ISD::OR, dl, NVT,
5697 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
5698 DAG.getNode(ISD::SHL, dl, NVT, InH,
5699 DAG.getConstant(NVTBits-Cst, ShTy)));
5700 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
5705 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
5706 DAG.getConstant(NVTBits-1, ShTy));
5707 } else if (Cst > NVTBits) {
5708 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
5709 DAG.getConstant(Cst-NVTBits, ShTy));
5710 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
5711 DAG.getConstant(NVTBits-1, ShTy));
5712 } else if (Cst == NVTBits) {
5714 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
5715 DAG.getConstant(NVTBits-1, ShTy));
5717 Lo = DAG.getNode(ISD::OR, dl, NVT,
5718 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
5719 DAG.getNode(ISD::SHL, dl,
5720 NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5721 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
5727 // Okay, the shift amount isn't constant. However, if we can tell that it is
5728 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5729 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5730 APInt KnownZero, KnownOne;
5731 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5733 // If we know that if any of the high bits of the shift amount are one, then
5734 // we can do this as a couple of simple shifts.
5735 if (KnownOne.intersects(Mask)) {
5736 // Mask out the high bit, which we know is set.
5737 Amt = DAG.getNode(ISD::AND, dl, Amt.getValueType(), Amt,
5738 DAG.getConstant(~Mask, Amt.getValueType()));
5740 // Expand the incoming operand to be shifted, so that we have its parts
5742 ExpandOp(Op, InL, InH);
5745 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5746 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
5749 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5750 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
5753 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
5754 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5755 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
5760 // If we know that the high bits of the shift amount are all zero, then we can
5761 // do this as a couple of simple shifts.
5762 if ((KnownZero & Mask) == Mask) {
5764 SDValue Amt2 = DAG.getNode(ISD::SUB, dl, Amt.getValueType(),
5765 DAG.getConstant(NVTBits, Amt.getValueType()),
5768 // Expand the incoming operand to be shifted, so that we have its parts
5770 ExpandOp(Op, InL, InH);
5773 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
5774 Hi = DAG.getNode(ISD::OR, dl, NVT,
5775 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
5776 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2));
5779 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
5780 Lo = DAG.getNode(ISD::OR, dl, NVT,
5781 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
5782 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
5785 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
5786 Lo = DAG.getNode(ISD::OR, dl, NVT,
5787 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
5788 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
5797 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5798 // does not fit into a register, return the lo part and set the hi part to the
5799 // by-reg argument. If it does fit into a single register, return the result
5800 // and leave the Hi part unset.
5801 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5802 bool isSigned, SDValue &Hi) {
5803 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5804 // The input chain to this libcall is the entry node of the function.
5805 // Legalizing the call will automatically add the previous call to the
5807 SDValue InChain = DAG.getEntryNode();
5809 TargetLowering::ArgListTy Args;
5810 TargetLowering::ArgListEntry Entry;
5811 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5812 MVT ArgVT = Node->getOperand(i).getValueType();
5813 const Type *ArgTy = ArgVT.getTypeForMVT();
5814 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5815 Entry.isSExt = isSigned;
5816 Entry.isZExt = !isSigned;
5817 Args.push_back(Entry);
5819 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5820 TLI.getPointerTy());
5822 // Splice the libcall in wherever FindInputOutputChains tells us to.
5823 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5824 std::pair<SDValue,SDValue> CallInfo =
5825 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5826 CallingConv::C, false, Callee, Args, DAG,
5827 Node->getDebugLoc());
5829 // Legalize the call sequence, starting with the chain. This will advance
5830 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5831 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5832 LegalizeOp(CallInfo.second);
5834 switch (getTypeAction(CallInfo.first.getValueType())) {
5835 default: assert(0 && "Unknown thing");
5837 Result = CallInfo.first;
5840 ExpandOp(CallInfo.first, Result, Hi);
5846 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5848 SDValue SelectionDAGLegalize::
5849 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op,
5851 bool isCustom = false;
5853 switch (getTypeAction(Op.getValueType())) {
5855 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5856 Op.getValueType())) {
5857 default: assert(0 && "Unknown operation action!");
5858 case TargetLowering::Custom:
5861 case TargetLowering::Legal:
5862 Tmp1 = LegalizeOp(Op);
5863 if (Result.getNode())
5864 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5866 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl,
5869 Tmp1 = TLI.LowerOperation(Result, DAG);
5870 if (Tmp1.getNode()) Result = Tmp1;
5873 case TargetLowering::Expand:
5874 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy, dl);
5876 case TargetLowering::Promote:
5877 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned, dl);
5882 Result = ExpandIntToFP(isSigned, DestTy, Op, dl) ;
5885 Tmp1 = PromoteOp(Op);
5887 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp1.getValueType(),
5888 Tmp1, DAG.getValueType(Op.getValueType()));
5890 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl,
5893 if (Result.getNode())
5894 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5896 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl,
5898 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5904 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5906 SDValue SelectionDAGLegalize::
5907 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl) {
5908 MVT SourceVT = Source.getValueType();
5909 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5911 // Expand unsupported int-to-fp vector casts by unrolling them.
5912 if (DestTy.isVector()) {
5914 return LegalizeOp(UnrollVectorOp(Source));
5915 MVT DestEltTy = DestTy.getVectorElementType();
5916 if (DestTy.getVectorNumElements() == 1) {
5917 SDValue Scalar = ScalarizeVectorOp(Source);
5918 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5919 DestEltTy, Scalar, dl);
5920 return DAG.getNode(ISD::BUILD_VECTOR, dl, DestTy, Result);
5923 SplitVectorOp(Source, Lo, Hi);
5924 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5925 DestTy.getVectorNumElements() / 2);
5926 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
5928 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
5930 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, DestTy, LoResult,
5934 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5935 if (!isSigned && SourceVT != MVT::i32) {
5936 // The integer value loaded will be incorrectly if the 'sign bit' of the
5937 // incoming integer is set. To handle this, we dynamically test to see if
5938 // it is set, and, if so, add a fudge factor.
5942 ExpandOp(Source, Lo, Hi);
5943 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, Lo, Hi);
5945 // The comparison for the sign bit will use the entire operand.
5949 // Check to see if the target has a custom way to lower this. If so, use
5950 // it. (Note we've already expanded the operand in this case.)
5951 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) {
5952 default: assert(0 && "This action not implemented for this operation!");
5953 case TargetLowering::Legal:
5954 case TargetLowering::Expand:
5955 break; // This case is handled below.
5956 case TargetLowering::Custom: {
5957 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, DestTy,
5960 return LegalizeOp(NV);
5961 break; // The target decided this was legal after all
5965 // If this is unsigned, and not supported, first perform the conversion to
5966 // signed, then adjust the result if the sign bit is set.
5967 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source, dl);
5969 SDValue SignSet = DAG.getSetCC(dl,
5970 TLI.getSetCCResultType(Hi.getValueType()),
5971 Hi, DAG.getConstant(0, Hi.getValueType()),
5973 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5974 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
5975 SignSet, Four, Zero);
5976 uint64_t FF = 0x5f800000ULL;
5977 if (TLI.isLittleEndian()) FF <<= 32;
5978 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5980 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5981 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5982 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
5983 Alignment = std::min(Alignment, 4u);
5985 if (DestTy == MVT::f32)
5986 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
5987 PseudoSourceValue::getConstantPool(), 0,
5989 else if (DestTy.bitsGT(MVT::f32))
5990 // FIXME: Avoid the extend by construction the right constantpool?
5991 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, dl, DestTy, DAG.getEntryNode(),
5993 PseudoSourceValue::getConstantPool(), 0,
5994 MVT::f32, false, Alignment);
5996 assert(0 && "Unexpected conversion");
5998 MVT SCVT = SignedConv.getValueType();
5999 if (SCVT != DestTy) {
6000 // Destination type needs to be expanded as well. The FADD now we are
6001 // constructing will be expanded into a libcall.
6002 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
6003 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
6004 SignedConv = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy,
6005 SignedConv, SignedConv.getValue(1));
6007 SignedConv = DAG.getNode(ISD::BIT_CONVERT, dl, DestTy, SignedConv);
6009 return DAG.getNode(ISD::FADD, dl, DestTy, SignedConv, FudgeInReg);
6012 // Check to see if the target has a custom way to lower this. If so, use it.
6013 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
6014 default: assert(0 && "This action not implemented for this operation!");
6015 case TargetLowering::Legal:
6016 case TargetLowering::Expand:
6017 break; // This case is handled below.
6018 case TargetLowering::Custom: {
6019 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, dl, DestTy,
6022 return LegalizeOp(NV);
6023 break; // The target decided this was legal after all
6027 // Expand the source, then glue it back together for the call. We must expand
6028 // the source in case it is shared (this pass of legalize must traverse it).
6030 SDValue SrcLo, SrcHi;
6031 ExpandOp(Source, SrcLo, SrcHi);
6032 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, SrcLo, SrcHi);
6035 RTLIB::Libcall LC = isSigned ?
6036 RTLIB::getSINTTOFP(SourceVT, DestTy) :
6037 RTLIB::getUINTTOFP(SourceVT, DestTy);
6038 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
6040 Source = DAG.getNode(ISD::SINT_TO_FP, dl, DestTy, Source);
6042 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
6043 if (Result.getValueType() != DestTy && HiPart.getNode())
6044 Result = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy, Result, HiPart);
6048 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
6049 /// INT_TO_FP operation of the specified operand when the target requests that
6050 /// we expand it. At this point, we know that the result and operand types are
6051 /// legal for the target.
6052 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
6056 if (Op0.getValueType() == MVT::i32) {
6057 // simple 32-bit [signed|unsigned] integer to float/double expansion
6059 // Get the stack frame index of a 8 byte buffer.
6060 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
6062 // word offset constant for Hi/Lo address computation
6063 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
6064 // set up Hi and Lo (into buffer) address based on endian
6065 SDValue Hi = StackSlot;
6066 SDValue Lo = DAG.getNode(ISD::ADD, dl,
6067 TLI.getPointerTy(), StackSlot,WordOff);
6068 if (TLI.isLittleEndian())
6071 // if signed map to unsigned space
6074 // constant used to invert sign bit (signed to unsigned mapping)
6075 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
6076 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
6080 // store the lo of the constructed double - based on integer input
6081 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
6082 Op0Mapped, Lo, NULL, 0);
6083 // initial hi portion of constructed double
6084 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
6085 // store the hi of the constructed double - biased exponent
6086 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
6087 // load the constructed double
6088 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
6089 // FP constant to bias correct the final result
6090 SDValue Bias = DAG.getConstantFP(isSigned ?
6091 BitsToDouble(0x4330000080000000ULL)
6092 : BitsToDouble(0x4330000000000000ULL),
6094 // subtract the bias
6095 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
6098 // handle final rounding
6099 if (DestVT == MVT::f64) {
6102 } else if (DestVT.bitsLT(MVT::f64)) {
6103 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
6104 DAG.getIntPtrConstant(0));
6105 } else if (DestVT.bitsGT(MVT::f64)) {
6106 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
6110 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
6111 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
6113 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
6114 Op0, DAG.getConstant(0, Op0.getValueType()),
6116 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
6117 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
6118 SignSet, Four, Zero);
6120 // If the sign bit of the integer is set, the large number will be treated
6121 // as a negative number. To counteract this, the dynamic code adds an
6122 // offset depending on the data type.
6124 switch (Op0.getValueType().getSimpleVT()) {
6125 default: assert(0 && "Unsupported integer type!");
6126 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
6127 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
6128 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
6129 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
6131 if (TLI.isLittleEndian()) FF <<= 32;
6132 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
6134 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
6135 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6136 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
6137 Alignment = std::min(Alignment, 4u);
6139 if (DestVT == MVT::f32)
6140 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
6141 PseudoSourceValue::getConstantPool(), 0,
6145 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
6146 DAG.getEntryNode(), CPIdx,
6147 PseudoSourceValue::getConstantPool(), 0,
6148 MVT::f32, false, Alignment));
6151 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
6154 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
6155 /// *INT_TO_FP operation of the specified operand when the target requests that
6156 /// we promote it. At this point, we know that the result and operand types are
6157 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
6158 /// operation that takes a larger input.
6159 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
6163 // First step, figure out the appropriate *INT_TO_FP operation to use.
6164 MVT NewInTy = LegalOp.getValueType();
6166 unsigned OpToUse = 0;
6168 // Scan for the appropriate larger type to use.
6170 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
6171 assert(NewInTy.isInteger() && "Ran out of possibilities!");
6173 // If the target supports SINT_TO_FP of this type, use it.
6174 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
6176 case TargetLowering::Legal:
6177 if (!TLI.isTypeLegal(NewInTy))
6178 break; // Can't use this datatype.
6180 case TargetLowering::Custom:
6181 OpToUse = ISD::SINT_TO_FP;
6185 if (isSigned) continue;
6187 // If the target supports UINT_TO_FP of this type, use it.
6188 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
6190 case TargetLowering::Legal:
6191 if (!TLI.isTypeLegal(NewInTy))
6192 break; // Can't use this datatype.
6194 case TargetLowering::Custom:
6195 OpToUse = ISD::UINT_TO_FP;
6200 // Otherwise, try a larger type.
6203 // Okay, we found the operation and type to use. Zero extend our input to the
6204 // desired type then run the operation on it.
6205 return DAG.getNode(OpToUse, dl, DestVT,
6206 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
6207 dl, NewInTy, LegalOp));
6210 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
6211 /// FP_TO_*INT operation of the specified operand when the target requests that
6212 /// we promote it. At this point, we know that the result and operand types are
6213 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
6214 /// operation that returns a larger result.
6215 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
6219 // First step, figure out the appropriate FP_TO*INT operation to use.
6220 MVT NewOutTy = DestVT;
6222 unsigned OpToUse = 0;
6224 // Scan for the appropriate larger type to use.
6226 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
6227 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
6229 // If the target supports FP_TO_SINT returning this type, use it.
6230 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
6232 case TargetLowering::Legal:
6233 if (!TLI.isTypeLegal(NewOutTy))
6234 break; // Can't use this datatype.
6236 case TargetLowering::Custom:
6237 OpToUse = ISD::FP_TO_SINT;
6242 // If the target supports FP_TO_UINT of this type, use it.
6243 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
6245 case TargetLowering::Legal:
6246 if (!TLI.isTypeLegal(NewOutTy))
6247 break; // Can't use this datatype.
6249 case TargetLowering::Custom:
6250 OpToUse = ISD::FP_TO_UINT;
6255 // Otherwise, try a larger type.
6259 // Okay, we found the operation and type to use.
6260 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
6262 // If the operation produces an invalid type, it must be custom lowered. Use
6263 // the target lowering hooks to expand it. Just keep the low part of the
6264 // expanded operation, we know that we're truncating anyway.
6265 if (getTypeAction(NewOutTy) == Expand) {
6266 SmallVector<SDValue, 2> Results;
6267 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG);
6268 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!");
6269 Operation = Results[0];
6272 // Truncate the result of the extended FP_TO_*INT operation to the desired
6274 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
6277 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
6279 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
6280 MVT VT = Op.getValueType();
6281 MVT SHVT = TLI.getShiftAmountTy();
6282 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
6283 switch (VT.getSimpleVT()) {
6284 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
6286 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6287 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6288 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
6290 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
6291 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6292 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6293 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
6294 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
6295 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
6296 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
6297 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
6298 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
6300 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
6301 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
6302 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
6303 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6304 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6305 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
6306 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
6307 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
6308 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
6309 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
6310 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
6311 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
6312 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
6313 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
6314 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
6315 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
6316 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
6317 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
6318 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
6319 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
6320 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
6324 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
6326 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
6329 default: assert(0 && "Cannot expand this yet!");
6331 static const uint64_t mask[6] = {
6332 0x5555555555555555ULL, 0x3333333333333333ULL,
6333 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
6334 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
6336 MVT VT = Op.getValueType();
6337 MVT ShVT = TLI.getShiftAmountTy();
6338 unsigned len = VT.getSizeInBits();
6339 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6340 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
6341 unsigned EltSize = VT.isVector() ?
6342 VT.getVectorElementType().getSizeInBits() : len;
6343 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
6344 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6345 Op = DAG.getNode(ISD::ADD, dl, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
6346 DAG.getNode(ISD::AND, dl, VT,
6347 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
6353 // for now, we do this:
6354 // x = x | (x >> 1);
6355 // x = x | (x >> 2);
6357 // x = x | (x >>16);
6358 // x = x | (x >>32); // for 64-bit input
6359 // return popcount(~x);
6361 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
6362 MVT VT = Op.getValueType();
6363 MVT ShVT = TLI.getShiftAmountTy();
6364 unsigned len = VT.getSizeInBits();
6365 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6366 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6367 Op = DAG.getNode(ISD::OR, dl, VT, Op,
6368 DAG.getNode(ISD::SRL, VT, Op, Tmp3));
6370 Op = DAG.getNOT(dl, Op, VT);
6371 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
6374 // for now, we use: { return popcount(~x & (x - 1)); }
6375 // unless the target has ctlz but not ctpop, in which case we use:
6376 // { return 32 - nlz(~x & (x-1)); }
6377 // see also http://www.hackersdelight.org/HDcode/ntz.cc
6378 MVT VT = Op.getValueType();
6379 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
6380 DAG.getNOT(dl, Op, VT),
6381 DAG.getNode(ISD::SUB, dl, VT, Op,
6382 DAG.getConstant(1, VT)));
6383 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6384 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
6385 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
6386 return DAG.getNode(ISD::SUB, dl, VT,
6387 DAG.getConstant(VT.getSizeInBits(), VT),
6388 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
6389 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
6394 /// ExpandOp - Expand the specified SDValue into its two component pieces
6395 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
6396 /// LegalizedNodes map is filled in for any results that are not expanded, the
6397 /// ExpandedNodes map is filled in for any results that are expanded, and the
6398 /// Lo/Hi values are returned.
6399 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
6400 MVT VT = Op.getValueType();
6401 MVT NVT = TLI.getTypeToTransformTo(VT);
6402 SDNode *Node = Op.getNode();
6403 DebugLoc dl = Node->getDebugLoc();
6404 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
6405 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
6406 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
6408 // See if we already expanded it.
6409 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
6410 = ExpandedNodes.find(Op);
6411 if (I != ExpandedNodes.end()) {
6412 Lo = I->second.first;
6413 Hi = I->second.second;
6417 switch (Node->getOpcode()) {
6418 case ISD::CopyFromReg:
6419 assert(0 && "CopyFromReg must be legal!");
6420 case ISD::FP_ROUND_INREG:
6421 if (VT == MVT::ppcf128 &&
6422 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
6423 TargetLowering::Custom) {
6424 SDValue SrcLo, SrcHi, Src;
6425 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
6426 Src = DAG.getNode(ISD::BUILD_PAIR, dl, VT, SrcLo, SrcHi);
6427 SDValue Result = TLI.LowerOperation(
6428 DAG.getNode(ISD::FP_ROUND_INREG, dl, VT, Src, Op.getOperand(1)), DAG);
6429 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
6430 Lo = Result.getNode()->getOperand(0);
6431 Hi = Result.getNode()->getOperand(1);
6437 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
6439 assert(0 && "Do not know how to expand this operator!");
6441 case ISD::EXTRACT_ELEMENT:
6442 ExpandOp(Node->getOperand(0), Lo, Hi);
6443 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
6444 return ExpandOp(Hi, Lo, Hi);
6445 return ExpandOp(Lo, Lo, Hi);
6446 case ISD::EXTRACT_VECTOR_ELT:
6447 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
6448 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
6449 return ExpandOp(Lo, Lo, Hi);
6451 Lo = DAG.getNode(ISD::UNDEF, dl, NVT);
6452 Hi = DAG.getNode(ISD::UNDEF, dl, NVT);
6454 case ISD::Constant: {
6455 unsigned NVTBits = NVT.getSizeInBits();
6456 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
6457 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
6458 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
6461 case ISD::ConstantFP: {
6462 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
6463 if (CFP->getValueType(0) == MVT::ppcf128) {
6464 APInt api = CFP->getValueAPF().bitcastToAPInt();
6465 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
6467 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
6471 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
6472 if (getTypeAction(Lo.getValueType()) == Expand)
6473 ExpandOp(Lo, Lo, Hi);
6476 case ISD::BUILD_PAIR:
6477 // Return the operands.
6478 Lo = Node->getOperand(0);
6479 Hi = Node->getOperand(1);
6482 case ISD::MERGE_VALUES:
6483 if (Node->getNumValues() == 1) {
6484 ExpandOp(Op.getOperand(0), Lo, Hi);
6487 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
6488 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
6489 Op.getValue(1).getValueType() == MVT::Other &&
6490 "unhandled MERGE_VALUES");
6491 ExpandOp(Op.getOperand(0), Lo, Hi);
6492 // Remember that we legalized the chain.
6493 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
6496 case ISD::SIGN_EXTEND_INREG:
6497 ExpandOp(Node->getOperand(0), Lo, Hi);
6498 // sext_inreg the low part if needed.
6499 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Lo, Node->getOperand(1));
6501 // The high part gets the sign extension from the lo-part. This handles
6502 // things like sextinreg V:i64 from i8.
6503 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6504 DAG.getConstant(NVT.getSizeInBits()-1,
6505 TLI.getShiftAmountTy()));
6509 ExpandOp(Node->getOperand(0), Lo, Hi);
6510 SDValue TempLo = DAG.getNode(ISD::BSWAP, dl, NVT, Hi);
6511 Hi = DAG.getNode(ISD::BSWAP, dl, NVT, Lo);
6517 ExpandOp(Node->getOperand(0), Lo, Hi);
6518 Lo = DAG.getNode(ISD::ADD, dl, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
6519 DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
6520 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
6521 Hi = DAG.getConstant(0, NVT);
6525 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
6526 ExpandOp(Node->getOperand(0), Lo, Hi);
6527 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6528 SDValue HLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
6529 SDValue TopNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), HLZ,
6531 SDValue LowPart = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
6532 LowPart = DAG.getNode(ISD::ADD, dl, NVT, LowPart, BitsC);
6534 Lo = DAG.getNode(ISD::SELECT, dl, NVT, TopNotZero, HLZ, LowPart);
6535 Hi = DAG.getConstant(0, NVT);
6540 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
6541 ExpandOp(Node->getOperand(0), Lo, Hi);
6542 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6543 SDValue LTZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
6544 SDValue BotNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), LTZ,
6546 SDValue HiPart = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
6547 HiPart = DAG.getNode(ISD::ADD, dl, NVT, HiPart, BitsC);
6549 Lo = DAG.getNode(ISD::SELECT, dl, NVT, BotNotZero, LTZ, HiPart);
6550 Hi = DAG.getConstant(0, NVT);
6555 SDValue Ch = Node->getOperand(0); // Legalize the chain.
6556 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6557 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
6558 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
6560 // Remember that we legalized the chain.
6561 Hi = LegalizeOp(Hi);
6562 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6563 if (TLI.isBigEndian())
6569 LoadSDNode *LD = cast<LoadSDNode>(Node);
6570 SDValue Ch = LD->getChain(); // Legalize the chain.
6571 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6572 ISD::LoadExtType ExtType = LD->getExtensionType();
6573 const Value *SV = LD->getSrcValue();
6574 int SVOffset = LD->getSrcValueOffset();
6575 unsigned Alignment = LD->getAlignment();
6576 bool isVolatile = LD->isVolatile();
6578 if (ExtType == ISD::NON_EXTLOAD) {
6579 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset,
6580 isVolatile, Alignment);
6581 if (VT == MVT::f32 || VT == MVT::f64) {
6582 // f32->i32 or f64->i64 one to one expansion.
6583 // Remember that we legalized the chain.
6584 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6585 // Recursively expand the new load.
6586 if (getTypeAction(NVT) == Expand)
6587 ExpandOp(Lo, Lo, Hi);
6591 // Increment the pointer to the other half.
6592 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6593 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
6594 DAG.getIntPtrConstant(IncrementSize));
6595 SVOffset += IncrementSize;
6596 Alignment = MinAlign(Alignment, IncrementSize);
6597 Hi = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset,
6598 isVolatile, Alignment);
6600 // Build a factor node to remember that this load is independent of the
6602 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
6605 // Remember that we legalized the chain.
6606 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6607 if (TLI.isBigEndian())
6610 MVT EVT = LD->getMemoryVT();
6612 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6613 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6614 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6615 SDValue Load = DAG.getLoad(EVT, dl, Ch, Ptr, SV,
6616 SVOffset, isVolatile, Alignment);
6617 // Remember that we legalized the chain.
6618 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6619 ExpandOp(DAG.getNode(ISD::FP_EXTEND, dl, VT, Load), Lo, Hi);
6624 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV,
6625 SVOffset, isVolatile, Alignment);
6627 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, SV,
6628 SVOffset, EVT, isVolatile,
6631 // Remember that we legalized the chain.
6632 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6634 if (ExtType == ISD::SEXTLOAD) {
6635 // The high part is obtained by SRA'ing all but one of the bits of the
6637 unsigned LoSize = Lo.getValueType().getSizeInBits();
6638 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6639 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6640 } else if (ExtType == ISD::ZEXTLOAD) {
6641 // The high part is just a zero.
6642 Hi = DAG.getConstant(0, NVT);
6643 } else /* if (ExtType == ISD::EXTLOAD) */ {
6644 // The high part is undefined.
6645 Hi = DAG.getNode(ISD::UNDEF, dl, NVT);
6652 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6653 SDValue LL, LH, RL, RH;
6654 ExpandOp(Node->getOperand(0), LL, LH);
6655 ExpandOp(Node->getOperand(1), RL, RH);
6656 Lo = DAG.getNode(Node->getOpcode(), dl, NVT, LL, RL);
6657 Hi = DAG.getNode(Node->getOpcode(), dl, NVT, LH, RH);
6661 SDValue LL, LH, RL, RH;
6662 ExpandOp(Node->getOperand(1), LL, LH);
6663 ExpandOp(Node->getOperand(2), RL, RH);
6664 if (getTypeAction(NVT) == Expand)
6665 NVT = TLI.getTypeToExpandTo(NVT);
6666 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LL, RL);
6668 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LH, RH);
6671 case ISD::SELECT_CC: {
6672 SDValue TL, TH, FL, FH;
6673 ExpandOp(Node->getOperand(2), TL, TH);
6674 ExpandOp(Node->getOperand(3), FL, FH);
6675 if (getTypeAction(NVT) == Expand)
6676 NVT = TLI.getTypeToExpandTo(NVT);
6677 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
6678 Node->getOperand(1), TL, FL, Node->getOperand(4));
6680 Hi = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
6681 Node->getOperand(1), TH, FH, Node->getOperand(4));
6684 case ISD::ANY_EXTEND:
6685 // The low part is any extension of the input (which degenerates to a copy).
6686 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0));
6687 // The high part is undefined.
6688 Hi = DAG.getNode(ISD::UNDEF, dl, NVT);
6690 case ISD::SIGN_EXTEND: {
6691 // The low part is just a sign extension of the input (which degenerates to
6693 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Node->getOperand(0));
6695 // The high part is obtained by SRA'ing all but one of the bits of the lo
6697 unsigned LoSize = Lo.getValueType().getSizeInBits();
6698 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6699 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6702 case ISD::ZERO_EXTEND:
6703 // The low part is just a zero extension of the input (which degenerates to
6705 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
6707 // The high part is just a zero.
6708 Hi = DAG.getConstant(0, NVT);
6711 case ISD::TRUNCATE: {
6712 // The input value must be larger than this value. Expand *it*.
6714 ExpandOp(Node->getOperand(0), NewLo, Hi);
6716 // The low part is now either the right size, or it is closer. If not the
6717 // right size, make an illegal truncate so we recursively expand it.
6718 if (NewLo.getValueType() != Node->getValueType(0))
6719 NewLo = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), NewLo);
6720 ExpandOp(NewLo, Lo, Hi);
6724 case ISD::BIT_CONVERT: {
6726 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6727 // If the target wants to, allow it to lower this itself.
6728 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6729 case Expand: assert(0 && "cannot expand FP!");
6730 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6731 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6733 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp), DAG);
6736 // f32 / f64 must be expanded to i32 / i64.
6737 if (VT == MVT::f32 || VT == MVT::f64) {
6738 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
6739 if (getTypeAction(NVT) == Expand)
6740 ExpandOp(Lo, Lo, Hi);
6744 // If source operand will be expanded to the same type as VT, i.e.
6745 // i64 <- f64, i32 <- f32, expand the source operand instead.
6746 MVT VT0 = Node->getOperand(0).getValueType();
6747 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6748 ExpandOp(Node->getOperand(0), Lo, Hi);
6752 // Turn this into a load/store pair by default.
6753 if (Tmp.getNode() == 0)
6754 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT, dl);
6756 ExpandOp(Tmp, Lo, Hi);
6760 case ISD::READCYCLECOUNTER: {
6761 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6762 TargetLowering::Custom &&
6763 "Must custom expand ReadCycleCounter");
6764 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6765 assert(Tmp.getNode() && "Node must be custom expanded!");
6766 ExpandOp(Tmp.getValue(0), Lo, Hi);
6767 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6768 LegalizeOp(Tmp.getValue(1)));
6772 case ISD::ATOMIC_CMP_SWAP: {
6773 // This operation does not need a loop.
6774 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6775 assert(Tmp.getNode() && "Node must be custom expanded!");
6776 ExpandOp(Tmp.getValue(0), Lo, Hi);
6777 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6778 LegalizeOp(Tmp.getValue(1)));
6782 case ISD::ATOMIC_LOAD_ADD:
6783 case ISD::ATOMIC_LOAD_SUB:
6784 case ISD::ATOMIC_LOAD_AND:
6785 case ISD::ATOMIC_LOAD_OR:
6786 case ISD::ATOMIC_LOAD_XOR:
6787 case ISD::ATOMIC_LOAD_NAND:
6788 case ISD::ATOMIC_SWAP: {
6789 // These operations require a loop to be generated. We can't do that yet,
6790 // so substitute a target-dependent pseudo and expand that later.
6791 SDValue In2Lo, In2Hi, In2;
6792 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6793 In2 = DAG.getNode(ISD::BUILD_PAIR, dl, VT, In2Lo, In2Hi);
6794 AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
6796 DAG.getAtomic(Op.getOpcode(), dl, Anode->getMemoryVT(),
6797 Op.getOperand(0), Op.getOperand(1), In2,
6798 Anode->getSrcValue(), Anode->getAlignment());
6799 SDValue Result = TLI.LowerOperation(Replace, DAG);
6800 ExpandOp(Result.getValue(0), Lo, Hi);
6801 // Remember that we legalized the chain.
6802 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
6806 // These operators cannot be expanded directly, emit them as calls to
6807 // library functions.
6808 case ISD::FP_TO_SINT: {
6809 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6811 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6812 case Expand: assert(0 && "cannot expand FP!");
6813 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6814 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6817 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op), DAG);
6819 // Now that the custom expander is done, expand the result, which is still
6822 ExpandOp(Op, Lo, Hi);
6827 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6829 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6830 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6834 case ISD::FP_TO_UINT: {
6835 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6837 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6838 case Expand: assert(0 && "cannot expand FP!");
6839 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6840 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6843 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, dl, VT, Op), DAG);
6845 // Now that the custom expander is done, expand the result.
6847 ExpandOp(Op, Lo, Hi);
6852 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6854 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6855 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6860 // If the target wants custom lowering, do so.
6861 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6862 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6863 SDValue Op = DAG.getNode(ISD::SHL, dl, VT, Node->getOperand(0), ShiftAmt);
6864 Op = TLI.LowerOperation(Op, DAG);
6866 // Now that the custom expander is done, expand the result, which is
6868 ExpandOp(Op, Lo, Hi);
6873 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6874 // this X << 1 as X+X.
6875 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6876 if (ShAmt->getAPIntValue() == 1 &&
6877 TLI.isOperationLegalOrCustom(ISD::ADDC, NVT) &&
6878 TLI.isOperationLegalOrCustom(ISD::ADDE, NVT)) {
6879 SDValue LoOps[2], HiOps[3];
6880 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6881 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6882 LoOps[1] = LoOps[0];
6883 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
6885 HiOps[1] = HiOps[0];
6886 HiOps[2] = Lo.getValue(1);
6887 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
6892 // If we can emit an efficient shift operation, do so now.
6893 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6896 // If this target supports SHL_PARTS, use it.
6897 TargetLowering::LegalizeAction Action =
6898 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6899 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6900 Action == TargetLowering::Custom) {
6901 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0),
6902 ShiftAmt, Lo, Hi, dl);
6906 // Otherwise, emit a libcall.
6907 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6912 // If the target wants custom lowering, do so.
6913 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6914 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6915 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6916 Op = TLI.LowerOperation(Op, DAG);
6918 // Now that the custom expander is done, expand the result, which is
6920 ExpandOp(Op, Lo, Hi);
6925 // If we can emit an efficient shift operation, do so now.
6926 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6929 // If this target supports SRA_PARTS, use it.
6930 TargetLowering::LegalizeAction Action =
6931 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6932 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6933 Action == TargetLowering::Custom) {
6934 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0),
6935 ShiftAmt, Lo, Hi, dl);
6939 // Otherwise, emit a libcall.
6940 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6945 // If the target wants custom lowering, do so.
6946 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6947 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6948 SDValue Op = DAG.getNode(ISD::SRL, dl, VT, Node->getOperand(0), ShiftAmt);
6949 Op = TLI.LowerOperation(Op, DAG);
6951 // Now that the custom expander is done, expand the result, which is
6953 ExpandOp(Op, Lo, Hi);
6958 // If we can emit an efficient shift operation, do so now.
6959 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6962 // If this target supports SRL_PARTS, use it.
6963 TargetLowering::LegalizeAction Action =
6964 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6965 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6966 Action == TargetLowering::Custom) {
6967 ExpandShiftParts(ISD::SRL_PARTS,
6968 Node->getOperand(0), ShiftAmt, Lo, Hi, dl);
6972 // Otherwise, emit a libcall.
6973 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6979 // If the target wants to custom expand this, let them.
6980 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6981 TargetLowering::Custom) {
6982 SDValue Result = TLI.LowerOperation(Op, DAG);
6983 if (Result.getNode()) {
6984 ExpandOp(Result, Lo, Hi);
6988 // Expand the subcomponents.
6989 SDValue LHSL, LHSH, RHSL, RHSH;
6990 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6991 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6992 SDValue LoOps[2], HiOps[3];
6998 //cascaded check to see if any smaller size has a a carry flag.
6999 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
7000 bool hasCarry = false;
7001 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
7002 MVT AVT = MVT::getIntegerVT(BitSize);
7003 if (TLI.isOperationLegalOrCustom(OpV, AVT)) {
7010 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7011 if (Node->getOpcode() == ISD::ADD) {
7012 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
7013 HiOps[2] = Lo.getValue(1);
7014 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
7016 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
7017 HiOps[2] = Lo.getValue(1);
7018 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
7022 if (Node->getOpcode() == ISD::ADD) {
7023 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
7024 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
7025 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
7026 Lo, LoOps[0], ISD::SETULT);
7027 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
7028 DAG.getConstant(1, NVT),
7029 DAG.getConstant(0, NVT));
7030 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
7031 Lo, LoOps[1], ISD::SETULT);
7032 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
7033 DAG.getConstant(1, NVT),
7035 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
7037 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
7038 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
7039 SDValue Cmp = DAG.getSetCC(dl, NVT, LoOps[0], LoOps[1], ISD::SETULT);
7040 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
7041 DAG.getConstant(1, NVT),
7042 DAG.getConstant(0, NVT));
7043 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
7051 // Expand the subcomponents.
7052 SDValue LHSL, LHSH, RHSL, RHSH;
7053 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7054 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7055 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7056 SDValue LoOps[2] = { LHSL, RHSL };
7057 SDValue HiOps[3] = { LHSH, RHSH };
7059 if (Node->getOpcode() == ISD::ADDC) {
7060 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
7061 HiOps[2] = Lo.getValue(1);
7062 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
7064 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
7065 HiOps[2] = Lo.getValue(1);
7066 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
7068 // Remember that we legalized the flag.
7069 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7074 // Expand the subcomponents.
7075 SDValue LHSL, LHSH, RHSL, RHSH;
7076 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7077 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7078 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7079 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
7080 SDValue HiOps[3] = { LHSH, RHSH };
7082 Lo = DAG.getNode(Node->getOpcode(), dl, VTList, LoOps, 3);
7083 HiOps[2] = Lo.getValue(1);
7084 Hi = DAG.getNode(Node->getOpcode(), dl, VTList, HiOps, 3);
7086 // Remember that we legalized the flag.
7087 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7091 // If the target wants to custom expand this, let them.
7092 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
7093 SDValue New = TLI.LowerOperation(Op, DAG);
7094 if (New.getNode()) {
7095 ExpandOp(New, Lo, Hi);
7100 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
7101 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
7102 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
7103 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
7104 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
7105 SDValue LL, LH, RL, RH;
7106 ExpandOp(Node->getOperand(0), LL, LH);
7107 ExpandOp(Node->getOperand(1), RL, RH);
7108 unsigned OuterBitSize = Op.getValueSizeInBits();
7109 unsigned InnerBitSize = RH.getValueSizeInBits();
7110 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
7111 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
7112 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
7113 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
7114 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
7115 // The inputs are both zero-extended.
7117 // We can emit a umul_lohi.
7118 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
7119 Hi = SDValue(Lo.getNode(), 1);
7123 // We can emit a mulhu+mul.
7124 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7125 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
7129 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
7130 // The input values are both sign-extended.
7132 // We can emit a smul_lohi.
7133 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
7134 Hi = SDValue(Lo.getNode(), 1);
7138 // We can emit a mulhs+mul.
7139 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7140 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
7145 // Lo,Hi = umul LHS, RHS.
7146 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
7147 DAG.getVTList(NVT, NVT), LL, RL);
7149 Hi = UMulLOHI.getValue(1);
7150 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
7151 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
7152 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
7153 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
7157 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7158 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
7159 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
7160 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
7161 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
7162 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
7167 // If nothing else, we can make a libcall.
7168 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
7172 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
7175 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
7178 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
7181 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
7185 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
7188 RTLIB::ADD_PPCF128),
7192 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
7195 RTLIB::SUB_PPCF128),
7199 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
7202 RTLIB::MUL_PPCF128),
7206 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
7209 RTLIB::DIV_PPCF128),
7212 case ISD::FP_EXTEND: {
7213 if (VT == MVT::ppcf128) {
7214 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
7215 Node->getOperand(0).getValueType()==MVT::f64);
7216 const uint64_t zero = 0;
7217 if (Node->getOperand(0).getValueType()==MVT::f32)
7218 Hi = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Node->getOperand(0));
7220 Hi = Node->getOperand(0);
7221 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7224 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
7225 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
7226 Lo = ExpandLibCall(LC, Node, true, Hi);
7229 case ISD::FP_ROUND: {
7230 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
7232 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
7233 Lo = ExpandLibCall(LC, Node, true, Hi);
7248 case ISD::FNEARBYINT:
7251 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
7252 switch(Node->getOpcode()) {
7254 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
7255 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
7258 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
7259 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
7262 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
7263 RTLIB::COS_F80, RTLIB::COS_PPCF128);
7266 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
7267 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
7270 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
7271 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
7274 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
7275 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
7278 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
7279 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
7282 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
7283 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
7286 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
7287 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
7290 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
7291 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
7294 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
7295 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
7298 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
7299 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
7301 case ISD::FNEARBYINT:
7302 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
7303 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
7306 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
7307 RTLIB::POW_PPCF128);
7310 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
7311 RTLIB::POWI_PPCF128);
7313 default: assert(0 && "Unreachable!");
7315 Lo = ExpandLibCall(LC, Node, false, Hi);
7319 if (VT == MVT::ppcf128) {
7321 ExpandOp(Node->getOperand(0), Lo, Tmp);
7322 Hi = DAG.getNode(ISD::FABS, dl, NVT, Tmp);
7323 // lo = hi==fabs(hi) ? lo : -lo;
7324 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Hi, Tmp,
7325 Lo, DAG.getNode(ISD::FNEG, dl, NVT, Lo),
7326 DAG.getCondCode(ISD::SETEQ));
7329 SDValue Mask = (VT == MVT::f64)
7330 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
7331 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
7332 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask);
7333 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
7334 Lo = DAG.getNode(ISD::AND, dl, NVT, Lo, Mask);
7335 if (getTypeAction(NVT) == Expand)
7336 ExpandOp(Lo, Lo, Hi);
7340 if (VT == MVT::ppcf128) {
7341 ExpandOp(Node->getOperand(0), Lo, Hi);
7342 Lo = DAG.getNode(ISD::FNEG, dl, MVT::f64, Lo);
7343 Hi = DAG.getNode(ISD::FNEG, dl, MVT::f64, Hi);
7346 SDValue Mask = (VT == MVT::f64)
7347 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
7348 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
7349 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask);
7350 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
7351 Lo = DAG.getNode(ISD::XOR, dl, NVT, Lo, Mask);
7352 if (getTypeAction(NVT) == Expand)
7353 ExpandOp(Lo, Lo, Hi);
7356 case ISD::FCOPYSIGN: {
7357 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
7358 if (getTypeAction(NVT) == Expand)
7359 ExpandOp(Lo, Lo, Hi);
7362 case ISD::SINT_TO_FP:
7363 case ISD::UINT_TO_FP: {
7364 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
7365 MVT SrcVT = Node->getOperand(0).getValueType();
7367 // Promote the operand if needed. Do this before checking for
7368 // ppcf128 so conversions of i16 and i8 work.
7369 if (getTypeAction(SrcVT) == Promote) {
7370 SDValue Tmp = PromoteOp(Node->getOperand(0));
7372 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp.getValueType(), Tmp,
7373 DAG.getValueType(SrcVT))
7374 : DAG.getZeroExtendInReg(Tmp, dl, SrcVT);
7375 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
7376 SrcVT = Node->getOperand(0).getValueType();
7379 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
7380 static const uint64_t zero = 0;
7382 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
7383 Node->getOperand(0)));
7384 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7386 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
7387 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
7388 Node->getOperand(0)));
7389 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7390 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
7391 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
7392 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl,
7393 MVT::ppcf128, Node->getOperand(0),
7394 DAG.getConstant(0, MVT::i32),
7395 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
7397 APFloat(APInt(128, 2, TwoE32)),
7400 DAG.getCondCode(ISD::SETLT)),
7405 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
7406 // si64->ppcf128 done by libcall, below
7407 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
7408 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::ppcf128,
7409 Node->getOperand(0)), Lo, Hi);
7410 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
7411 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
7412 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl, MVT::ppcf128,
7413 Node->getOperand(0),
7414 DAG.getConstant(0, MVT::i64),
7415 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
7417 APFloat(APInt(128, 2, TwoE64)),
7420 DAG.getCondCode(ISD::SETLT)),
7425 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
7426 Node->getOperand(0), dl);
7427 if (getTypeAction(Lo.getValueType()) == Expand)
7428 // float to i32 etc. can be 'expanded' to a single node.
7429 ExpandOp(Lo, Lo, Hi);
7434 // Make sure the resultant values have been legalized themselves, unless this
7435 // is a type that requires multi-step expansion.
7436 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
7437 Lo = LegalizeOp(Lo);
7439 // Don't legalize the high part if it is expanded to a single node.
7440 Hi = LegalizeOp(Hi);
7443 // Remember in a map if the values will be reused later.
7445 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7446 assert(isNew && "Value already expanded?!?");
7450 /// SplitVectorOp - Given an operand of vector type, break it down into
7451 /// two smaller values, still of vector type.
7452 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
7454 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
7455 SDNode *Node = Op.getNode();
7456 DebugLoc dl = Node->getDebugLoc();
7457 unsigned NumElements = Op.getValueType().getVectorNumElements();
7458 assert(NumElements > 1 && "Cannot split a single element vector!");
7460 MVT NewEltVT = Op.getValueType().getVectorElementType();
7462 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
7463 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
7465 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
7466 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
7468 // See if we already split it.
7469 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
7470 = SplitNodes.find(Op);
7471 if (I != SplitNodes.end()) {
7472 Lo = I->second.first;
7473 Hi = I->second.second;
7477 switch (Node->getOpcode()) {
7482 assert(0 && "Unhandled operation in SplitVectorOp!");
7484 Lo = DAG.getNode(ISD::UNDEF, dl, NewVT_Lo);
7485 Hi = DAG.getNode(ISD::UNDEF, dl, NewVT_Hi);
7487 case ISD::BUILD_PAIR:
7488 Lo = Node->getOperand(0);
7489 Hi = Node->getOperand(1);
7491 case ISD::INSERT_VECTOR_ELT: {
7492 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
7493 SplitVectorOp(Node->getOperand(0), Lo, Hi);
7494 unsigned Index = Idx->getZExtValue();
7495 SDValue ScalarOp = Node->getOperand(1);
7496 if (Index < NewNumElts_Lo)
7497 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Lo, Lo, ScalarOp,
7498 DAG.getIntPtrConstant(Index));
7500 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Hi, Hi, ScalarOp,
7501 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
7504 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
7505 Node->getOperand(1),
7506 Node->getOperand(2), dl);
7507 SplitVectorOp(Tmp, Lo, Hi);
7510 case ISD::VECTOR_SHUFFLE: {
7511 // Build the low part.
7512 SDValue Mask = Node->getOperand(2);
7513 SmallVector<SDValue, 8> Ops;
7514 MVT PtrVT = TLI.getPointerTy();
7516 // Insert all of the elements from the input that are needed. We use
7517 // buildvector of extractelement here because the input vectors will have
7518 // to be legalized, so this makes the code simpler.
7519 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
7520 SDValue IdxNode = Mask.getOperand(i);
7521 if (IdxNode.getOpcode() == ISD::UNDEF) {
7522 Ops.push_back(DAG.getNode(ISD::UNDEF, dl, NewEltVT));
7525 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7526 SDValue InVec = Node->getOperand(0);
7527 if (Idx >= NumElements) {
7528 InVec = Node->getOperand(1);
7531 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
7532 DAG.getConstant(Idx, PtrVT)));
7534 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &Ops[0], Ops.size());
7537 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
7538 SDValue IdxNode = Mask.getOperand(i);
7539 if (IdxNode.getOpcode() == ISD::UNDEF) {
7540 Ops.push_back(DAG.getNode(ISD::UNDEF, dl, NewEltVT));
7543 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7544 SDValue InVec = Node->getOperand(0);
7545 if (Idx >= NumElements) {
7546 InVec = Node->getOperand(1);
7549 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
7550 DAG.getConstant(Idx, PtrVT)));
7552 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &Ops[0], Ops.size());
7555 case ISD::BUILD_VECTOR: {
7556 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7557 Node->op_begin()+NewNumElts_Lo);
7558 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &LoOps[0], LoOps.size());
7560 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
7562 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &HiOps[0], HiOps.size());
7565 case ISD::CONCAT_VECTORS: {
7566 // FIXME: Handle non-power-of-two vectors?
7567 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
7568 if (NewNumSubvectors == 1) {
7569 Lo = Node->getOperand(0);
7570 Hi = Node->getOperand(1);
7572 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7573 Node->op_begin()+NewNumSubvectors);
7574 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Lo,
7575 &LoOps[0], LoOps.size());
7577 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
7579 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Hi,
7580 &HiOps[0], HiOps.size());
7584 case ISD::EXTRACT_SUBVECTOR: {
7585 SDValue Vec = Op.getOperand(0);
7586 SDValue Idx = Op.getOperand(1);
7587 MVT IdxVT = Idx.getValueType();
7589 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Lo, Vec, Idx);
7590 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
7592 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec,
7593 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo,
7596 Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx,
7597 DAG.getConstant(NewNumElts_Lo, IdxVT));
7598 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec, Idx);
7603 SDValue Cond = Node->getOperand(0);
7605 SDValue LL, LH, RL, RH;
7606 SplitVectorOp(Node->getOperand(1), LL, LH);
7607 SplitVectorOp(Node->getOperand(2), RL, RH);
7609 if (Cond.getValueType().isVector()) {
7610 // Handle a vector merge.
7612 SplitVectorOp(Cond, CL, CH);
7613 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, CL, LL, RL);
7614 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, CH, LH, RH);
7616 // Handle a simple select with vector operands.
7617 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, Cond, LL, RL);
7618 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, Cond, LH, RH);
7622 case ISD::SELECT_CC: {
7623 SDValue CondLHS = Node->getOperand(0);
7624 SDValue CondRHS = Node->getOperand(1);
7625 SDValue CondCode = Node->getOperand(4);
7627 SDValue LL, LH, RL, RH;
7628 SplitVectorOp(Node->getOperand(2), LL, LH);
7629 SplitVectorOp(Node->getOperand(3), RL, RH);
7631 // Handle a simple select with vector operands.
7632 Lo = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Lo, CondLHS, CondRHS,
7634 Hi = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Hi, CondLHS, CondRHS,
7639 SDValue LL, LH, RL, RH;
7640 SplitVectorOp(Node->getOperand(0), LL, LH);
7641 SplitVectorOp(Node->getOperand(1), RL, RH);
7642 Lo = DAG.getNode(ISD::VSETCC, dl, NewVT_Lo, LL, RL, Node->getOperand(2));
7643 Hi = DAG.getNode(ISD::VSETCC, dl, NewVT_Hi, LH, RH, Node->getOperand(2));
7665 SDValue LL, LH, RL, RH;
7666 SplitVectorOp(Node->getOperand(0), LL, LH);
7667 SplitVectorOp(Node->getOperand(1), RL, RH);
7669 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, LL, RL);
7670 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, LH, RH);
7676 SplitVectorOp(Node->getOperand(0), L, H);
7678 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L, Node->getOperand(1));
7679 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H, Node->getOperand(1));
7695 case ISD::FP_TO_SINT:
7696 case ISD::FP_TO_UINT:
7697 case ISD::SINT_TO_FP:
7698 case ISD::UINT_TO_FP:
7700 case ISD::ANY_EXTEND:
7701 case ISD::SIGN_EXTEND:
7702 case ISD::ZERO_EXTEND:
7703 case ISD::FP_EXTEND: {
7705 SplitVectorOp(Node->getOperand(0), L, H);
7707 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L);
7708 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H);
7711 case ISD::CONVERT_RNDSAT: {
7712 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
7714 SplitVectorOp(Node->getOperand(0), L, H);
7715 SDValue DTyOpL = DAG.getValueType(NewVT_Lo);
7716 SDValue DTyOpH = DAG.getValueType(NewVT_Hi);
7717 SDValue STyOpL = DAG.getValueType(L.getValueType());
7718 SDValue STyOpH = DAG.getValueType(H.getValueType());
7720 SDValue RndOp = Node->getOperand(3);
7721 SDValue SatOp = Node->getOperand(4);
7723 Lo = DAG.getConvertRndSat(NewVT_Lo, L, DTyOpL, STyOpL,
7724 RndOp, SatOp, CvtCode);
7725 Hi = DAG.getConvertRndSat(NewVT_Hi, H, DTyOpH, STyOpH,
7726 RndOp, SatOp, CvtCode);
7730 LoadSDNode *LD = cast<LoadSDNode>(Node);
7731 SDValue Ch = LD->getChain();
7732 SDValue Ptr = LD->getBasePtr();
7733 ISD::LoadExtType ExtType = LD->getExtensionType();
7734 const Value *SV = LD->getSrcValue();
7735 int SVOffset = LD->getSrcValueOffset();
7736 MVT MemoryVT = LD->getMemoryVT();
7737 unsigned Alignment = LD->getAlignment();
7738 bool isVolatile = LD->isVolatile();
7740 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7741 SDValue Offset = DAG.getNode(ISD::UNDEF, dl, Ptr.getValueType());
7743 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7744 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7745 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7747 Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7748 NewVT_Lo, Ch, Ptr, Offset,
7749 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7750 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7751 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
7752 DAG.getIntPtrConstant(IncrementSize));
7753 SVOffset += IncrementSize;
7754 Alignment = MinAlign(Alignment, IncrementSize);
7755 Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7756 NewVT_Hi, Ch, Ptr, Offset,
7757 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7759 // Build a factor node to remember that this load is independent of the
7761 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
7764 // Remember that we legalized the chain.
7765 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7768 case ISD::BIT_CONVERT: {
7769 // We know the result is a vector. The input may be either a vector or a
7771 SDValue InOp = Node->getOperand(0);
7772 if (!InOp.getValueType().isVector() ||
7773 InOp.getValueType().getVectorNumElements() == 1) {
7774 // The input is a scalar or single-element vector.
7775 // Lower to a store/load so that it can be split.
7776 // FIXME: this could be improved probably.
7777 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
7778 Op.getValueType().getTypeForMVT());
7779 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7780 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7782 SDValue St = DAG.getStore(DAG.getEntryNode(), dl,
7784 PseudoSourceValue::getFixedStack(FI), 0);
7785 InOp = DAG.getLoad(Op.getValueType(), dl, St, Ptr,
7786 PseudoSourceValue::getFixedStack(FI), 0);
7788 // Split the vector and convert each of the pieces now.
7789 SplitVectorOp(InOp, Lo, Hi);
7790 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Lo, Lo);
7791 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Hi, Hi);
7796 // Remember in a map if the values will be reused later.
7798 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7799 assert(isNew && "Value already split?!?");
7804 /// ScalarizeVectorOp - Given an operand of single-element vector type
7805 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7806 /// scalar (e.g. f32) value.
7807 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7808 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7809 SDNode *Node = Op.getNode();
7810 DebugLoc dl = Node->getDebugLoc();
7811 MVT NewVT = Op.getValueType().getVectorElementType();
7812 assert(Op.getValueType().getVectorNumElements() == 1);
7814 // See if we already scalarized it.
7815 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7816 if (I != ScalarizedNodes.end()) return I->second;
7819 switch (Node->getOpcode()) {
7822 Node->dump(&DAG); cerr << "\n";
7824 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7841 Result = DAG.getNode(Node->getOpcode(), dl,
7843 ScalarizeVectorOp(Node->getOperand(0)),
7844 ScalarizeVectorOp(Node->getOperand(1)));
7856 case ISD::FP_TO_SINT:
7857 case ISD::FP_TO_UINT:
7858 case ISD::SINT_TO_FP:
7859 case ISD::UINT_TO_FP:
7860 case ISD::SIGN_EXTEND:
7861 case ISD::ZERO_EXTEND:
7862 case ISD::ANY_EXTEND:
7864 case ISD::FP_EXTEND:
7865 Result = DAG.getNode(Node->getOpcode(), dl,
7867 ScalarizeVectorOp(Node->getOperand(0)));
7869 case ISD::CONVERT_RNDSAT: {
7870 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
7871 Result = DAG.getConvertRndSat(NewVT, Op0,
7872 DAG.getValueType(NewVT),
7873 DAG.getValueType(Op0.getValueType()),
7874 Node->getOperand(3),
7875 Node->getOperand(4),
7876 cast<CvtRndSatSDNode>(Node)->getCvtCode());
7881 Result = DAG.getNode(Node->getOpcode(), dl,
7883 ScalarizeVectorOp(Node->getOperand(0)),
7884 Node->getOperand(1));
7887 LoadSDNode *LD = cast<LoadSDNode>(Node);
7888 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7889 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7890 ISD::LoadExtType ExtType = LD->getExtensionType();
7891 const Value *SV = LD->getSrcValue();
7892 int SVOffset = LD->getSrcValueOffset();
7893 MVT MemoryVT = LD->getMemoryVT();
7894 unsigned Alignment = LD->getAlignment();
7895 bool isVolatile = LD->isVolatile();
7897 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7898 SDValue Offset = DAG.getNode(ISD::UNDEF, dl, Ptr.getValueType());
7900 Result = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7901 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7902 MemoryVT.getVectorElementType(),
7903 isVolatile, Alignment);
7905 // Remember that we legalized the chain.
7906 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7909 case ISD::BUILD_VECTOR:
7910 Result = Node->getOperand(0);
7912 case ISD::INSERT_VECTOR_ELT:
7913 // Returning the inserted scalar element.
7914 Result = Node->getOperand(1);
7916 case ISD::CONCAT_VECTORS:
7917 assert(Node->getOperand(0).getValueType() == NewVT &&
7918 "Concat of non-legal vectors not yet supported!");
7919 Result = Node->getOperand(0);
7921 case ISD::VECTOR_SHUFFLE: {
7922 // Figure out if the scalar is the LHS or RHS and return it.
7923 SDValue EltNum = Node->getOperand(2).getOperand(0);
7924 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7925 Result = ScalarizeVectorOp(Node->getOperand(1));
7927 Result = ScalarizeVectorOp(Node->getOperand(0));
7930 case ISD::EXTRACT_SUBVECTOR:
7931 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT,
7932 Node->getOperand(0), Node->getOperand(1));
7934 case ISD::BIT_CONVERT: {
7935 SDValue Op0 = Op.getOperand(0);
7936 if (Op0.getValueType().getVectorNumElements() == 1)
7937 Op0 = ScalarizeVectorOp(Op0);
7938 Result = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, Op0);
7942 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Op.getOperand(0),
7943 ScalarizeVectorOp(Op.getOperand(1)),
7944 ScalarizeVectorOp(Op.getOperand(2)));
7946 case ISD::SELECT_CC:
7947 Result = DAG.getNode(ISD::SELECT_CC, dl, NewVT, Node->getOperand(0),
7948 Node->getOperand(1),
7949 ScalarizeVectorOp(Op.getOperand(2)),
7950 ScalarizeVectorOp(Op.getOperand(3)),
7951 Node->getOperand(4));
7954 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7955 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7956 Result = DAG.getNode(ISD::SETCC, dl,
7957 TLI.getSetCCResultType(Op0.getValueType()),
7958 Op0, Op1, Op.getOperand(2));
7959 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Result,
7960 DAG.getConstant(-1ULL, NewVT),
7961 DAG.getConstant(0ULL, NewVT));
7966 if (TLI.isTypeLegal(NewVT))
7967 Result = LegalizeOp(Result);
7968 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7969 assert(isNew && "Value already scalarized?");
7975 SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
7976 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op);
7977 if (I != WidenNodes.end()) return I->second;
7979 MVT VT = Op.getValueType();
7980 assert(VT.isVector() && "Cannot widen non-vector type!");
7983 SDNode *Node = Op.getNode();
7984 DebugLoc dl = Node->getDebugLoc();
7985 MVT EVT = VT.getVectorElementType();
7987 unsigned NumElts = VT.getVectorNumElements();
7988 unsigned NewNumElts = WidenVT.getVectorNumElements();
7989 assert(NewNumElts > NumElts && "Cannot widen to smaller type!");
7990 assert(NewNumElts < 17);
7992 // When widen is called, it is assumed that it is more efficient to use a
7993 // wide type. The default action is to widen to operation to a wider legal
7994 // vector type and then do the operation if it is legal by calling LegalizeOp
7995 // again. If there is no vector equivalent, we will unroll the operation, do
7996 // it, and rebuild the vector. If most of the operations are vectorizible to
7997 // the legal type, the resulting code will be more efficient. If this is not
7998 // the case, the resulting code will preform badly as we end up generating
7999 // code to pack/unpack the results. It is the function that calls widen
8000 // that is responsible for seeing this doesn't happen.
8001 switch (Node->getOpcode()) {
8006 assert(0 && "Unexpected operation in WidenVectorOp!");
8008 case ISD::CopyFromReg:
8009 assert(0 && "CopyFromReg doesn't need widening!");
8011 case ISD::ConstantFP:
8012 // To build a vector of these elements, clients should call BuildVector
8013 // and with each element instead of creating a node with a vector type
8014 assert(0 && "Unexpected operation in WidenVectorOp!");
8016 // Variable Arguments with vector types doesn't make any sense to me
8017 assert(0 && "Unexpected operation in WidenVectorOp!");
8020 Result = DAG.getNode(ISD::UNDEF, dl, WidenVT);
8022 case ISD::BUILD_VECTOR: {
8023 // Build a vector with undefined for the new nodes
8024 SDValueVector NewOps(Node->op_begin(), Node->op_end());
8025 for (unsigned i = NumElts; i < NewNumElts; ++i) {
8026 NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, EVT));
8028 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT,
8029 &NewOps[0], NewOps.size());
8032 case ISD::INSERT_VECTOR_ELT: {
8033 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8034 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WidenVT, Tmp1,
8035 Node->getOperand(1), Node->getOperand(2));
8038 case ISD::VECTOR_SHUFFLE: {
8039 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8040 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8041 // VECTOR_SHUFFLE 3rd operand must be a constant build vector that is
8042 // used as permutation array. We build the vector here instead of widening
8043 // because we don't want to legalize and have it turned to something else.
8044 SDValue PermOp = Node->getOperand(2);
8045 SDValueVector NewOps;
8046 MVT PVT = PermOp.getValueType().getVectorElementType();
8047 for (unsigned i = 0; i < NumElts; ++i) {
8048 if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) {
8049 NewOps.push_back(PermOp.getOperand(i));
8052 cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue();
8053 if (Idx < NumElts) {
8054 NewOps.push_back(PermOp.getOperand(i));
8057 NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts,
8058 PermOp.getOperand(i).getValueType()));
8062 for (unsigned i = NumElts; i < NewNumElts; ++i) {
8063 NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, PVT));
8066 SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR, dl,
8067 MVT::getVectorVT(PVT, NewOps.size()),
8068 &NewOps[0], NewOps.size());
8070 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, WidenVT, Tmp1, Tmp2, Tmp3);
8074 // If the load widen returns true, we can use a single load for the
8075 // vector. Otherwise, it is returning a token factor for multiple
8078 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT))
8079 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1)));
8081 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0)));
8085 case ISD::BIT_CONVERT: {
8086 SDValue Tmp1 = Node->getOperand(0);
8087 // Converts between two different types so we need to determine
8088 // the correct widen type for the input operand.
8089 MVT InVT = Tmp1.getValueType();
8090 unsigned WidenSize = WidenVT.getSizeInBits();
8091 if (InVT.isVector()) {
8092 MVT InEltVT = InVT.getVectorElementType();
8093 unsigned InEltSize = InEltVT.getSizeInBits();
8094 assert(WidenSize % InEltSize == 0 &&
8095 "can not widen bit convert that are not multiple of element type");
8096 MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize);
8097 Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT);
8098 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
8099 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Tmp1);
8101 // If the result size is a multiple of the input size, widen the input
8102 // and then convert.
8103 unsigned InSize = InVT.getSizeInBits();
8104 assert(WidenSize % InSize == 0 &&
8105 "can not widen bit convert that are not multiple of element type");
8106 unsigned NewNumElts = WidenSize / InSize;
8107 SmallVector<SDValue, 16> Ops(NewNumElts);
8108 SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
8110 for (unsigned i = 1; i < NewNumElts; ++i)
8113 MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts);
8114 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, &Ops[0], NewNumElts);
8115 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Result);
8120 case ISD::SINT_TO_FP:
8121 case ISD::UINT_TO_FP:
8122 case ISD::FP_TO_SINT:
8123 case ISD::FP_TO_UINT:
8124 case ISD::FP_ROUND: {
8125 SDValue Tmp1 = Node->getOperand(0);
8126 // Converts between two different types so we need to determine
8127 // the correct widen type for the input operand.
8128 MVT TVT = Tmp1.getValueType();
8129 assert(TVT.isVector() && "can not widen non vector type");
8130 MVT TEVT = TVT.getVectorElementType();
8131 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts);
8132 Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
8133 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts);
8134 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
8138 case ISD::FP_EXTEND:
8139 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
8141 case ISD::SIGN_EXTEND:
8142 case ISD::ZERO_EXTEND:
8143 case ISD::ANY_EXTEND:
8144 case ISD::SIGN_EXTEND_INREG:
8153 // Unary op widening
8155 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8156 assert(Tmp1.getValueType() == WidenVT);
8157 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
8160 case ISD::CONVERT_RNDSAT: {
8161 SDValue RndOp = Node->getOperand(3);
8162 SDValue SatOp = Node->getOperand(4);
8163 SDValue SrcOp = Node->getOperand(0);
8165 // Converts between two different types so we need to determine
8166 // the correct widen type for the input operand.
8167 MVT SVT = SrcOp.getValueType();
8168 assert(SVT.isVector() && "can not widen non vector type");
8169 MVT SEVT = SVT.getVectorElementType();
8170 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts);
8172 SrcOp = WidenVectorOp(SrcOp, SWidenVT);
8173 assert(SrcOp.getValueType() == WidenVT);
8174 SDValue DTyOp = DAG.getValueType(WidenVT);
8175 SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
8176 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
8178 Result = DAG.getConvertRndSat(WidenVT, SrcOp, DTyOp, STyOp,
8179 RndOp, SatOp, CvtCode);
8199 case ISD::FCOPYSIGN:
8203 // Binary op widening
8204 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8205 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8206 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8207 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2);
8214 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8215 assert(Tmp1.getValueType() == WidenVT);
8216 SDValue ShOp = Node->getOperand(1);
8217 MVT ShVT = ShOp.getValueType();
8218 MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(),
8219 WidenVT.getVectorNumElements());
8220 ShOp = WidenVectorOp(ShOp, NewShVT);
8221 assert(ShOp.getValueType() == NewShVT);
8222 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, ShOp);
8226 case ISD::EXTRACT_VECTOR_ELT: {
8227 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8228 assert(Tmp1.getValueType() == WidenVT);
8229 Result = DAG.getNode(Node->getOpcode(), dl, EVT, Tmp1, Node->getOperand(1));
8232 case ISD::CONCAT_VECTORS: {
8233 // We concurrently support only widen on a multiple of the incoming vector.
8234 // We could widen on a multiple of the incoming operand if necessary.
8235 unsigned NumConcat = NewNumElts / NumElts;
8236 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
8237 SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, VT);
8238 SmallVector<SDValue, 8> MOps;
8240 for (unsigned i = 1; i != NumConcat; ++i) {
8241 MOps.push_back(UndefVal);
8243 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
8244 &MOps[0], MOps.size()));
8247 case ISD::EXTRACT_SUBVECTOR: {
8248 SDValue Tmp1 = Node->getOperand(0);
8249 SDValue Idx = Node->getOperand(1);
8250 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
8251 if (CIdx && CIdx->getZExtValue() == 0) {
8252 // Since we are access the start of the vector, the incoming
8253 // vector type might be the proper.
8254 MVT Tmp1VT = Tmp1.getValueType();
8255 if (Tmp1VT == WidenVT)
8258 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements();
8259 if (Tmp1VTNumElts < NewNumElts)
8260 Result = WidenVectorOp(Tmp1, WidenVT);
8262 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, Tmp1, Idx);
8264 } else if (NewNumElts % NumElts == 0) {
8265 // Widen the extracted subvector.
8266 unsigned NumConcat = NewNumElts / NumElts;
8267 SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, VT);
8268 SmallVector<SDValue, 8> MOps;
8270 for (unsigned i = 1; i != NumConcat; ++i) {
8271 MOps.push_back(UndefVal);
8273 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
8274 &MOps[0], MOps.size()));
8276 assert(0 && "can not widen extract subvector");
8277 // This could be implemented using insert and build vector but I would
8278 // like to see when this happens.
8284 // Determine new condition widen type and widen
8285 SDValue Cond1 = Node->getOperand(0);
8286 MVT CondVT = Cond1.getValueType();
8287 assert(CondVT.isVector() && "can not widen non vector type");
8288 MVT CondEVT = CondVT.getVectorElementType();
8289 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8290 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8291 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen");
8293 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT);
8294 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT);
8295 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8296 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Tmp1, Tmp2);
8300 case ISD::SELECT_CC: {
8301 // Determine new condition widen type and widen
8302 SDValue Cond1 = Node->getOperand(0);
8303 SDValue Cond2 = Node->getOperand(1);
8304 MVT CondVT = Cond1.getValueType();
8305 assert(CondVT.isVector() && "can not widen non vector type");
8306 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs");
8307 MVT CondEVT = CondVT.getVectorElementType();
8308 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8309 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8310 Cond2 = WidenVectorOp(Cond2, CondWidenVT);
8311 assert(Cond1.getValueType() == CondWidenVT &&
8312 Cond2.getValueType() == CondWidenVT && "condition not widen");
8314 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT);
8315 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT);
8316 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT &&
8317 "operands not widen");
8318 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Cond2, Tmp1,
8319 Tmp2, Node->getOperand(4));
8323 // Determine widen for the operand
8324 SDValue Tmp1 = Node->getOperand(0);
8325 MVT TmpVT = Tmp1.getValueType();
8326 assert(TmpVT.isVector() && "can not widen non vector type");
8327 MVT TmpEVT = TmpVT.getVectorElementType();
8328 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts);
8329 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT);
8330 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT);
8331 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2,
8332 Node->getOperand(2));
8335 case ISD::ATOMIC_CMP_SWAP:
8336 case ISD::ATOMIC_LOAD_ADD:
8337 case ISD::ATOMIC_LOAD_SUB:
8338 case ISD::ATOMIC_LOAD_AND:
8339 case ISD::ATOMIC_LOAD_OR:
8340 case ISD::ATOMIC_LOAD_XOR:
8341 case ISD::ATOMIC_LOAD_NAND:
8342 case ISD::ATOMIC_LOAD_MIN:
8343 case ISD::ATOMIC_LOAD_MAX:
8344 case ISD::ATOMIC_LOAD_UMIN:
8345 case ISD::ATOMIC_LOAD_UMAX:
8346 case ISD::ATOMIC_SWAP: {
8347 // For now, we assume that using vectors for these operations don't make
8348 // much sense so we just split it. We return an empty result
8350 SplitVectorOp(Op, X, Y);
8355 } // end switch (Node->getOpcode())
8357 assert(Result.getNode() && "Didn't set a result!");
8359 Result = LegalizeOp(Result);
8361 AddWidenedOperand(Op, Result);
8365 // Utility function to find a legal vector type and its associated element
8366 // type from a preferred width and whose vector type must be the same size
8368 // TLI: Target lowering used to determine legal types
8369 // Width: Preferred width of element type
8370 // VVT: Vector value type whose size we must match.
8371 // Returns VecEVT and EVT - the vector type and its associated element type
8372 static void FindWidenVecType(const TargetLowering &TLI, unsigned Width, MVT VVT,
8373 MVT& EVT, MVT& VecEVT) {
8374 // We start with the preferred width, make it a power of 2 and see if
8375 // we can find a vector type of that width. If not, we reduce it by
8376 // another power of 2. If we have widen the type, a vector of bytes should
8378 assert(TLI.isTypeLegal(VVT));
8379 unsigned EWidth = Width + 1;
8382 EWidth = (1 << Log2_32(EWidth-1));
8383 EVT = MVT::getIntegerVT(EWidth);
8384 unsigned NumEVT = VVT.getSizeInBits()/EWidth;
8385 VecEVT = MVT::getVectorVT(EVT, NumEVT);
8386 } while (!TLI.isTypeLegal(VecEVT) ||
8387 VVT.getSizeInBits() != VecEVT.getSizeInBits());
8390 SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
8400 // We assume that we have good rules to handle loading power of two loads so
8401 // we break down the operations to power of 2 loads. The strategy is to
8402 // load the largest power of 2 that we can easily transform to a legal vector
8403 // and then insert into that vector, and the cast the result into the legal
8404 // vector that we want. This avoids unnecessary stack converts.
8405 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
8406 // the load is nonvolatile, we an use a wider load for the value.
8407 // Find a vector length we can load a large chunk
8410 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8411 EVTWidth = EVT.getSizeInBits();
8413 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV, SVOffset,
8414 isVolatile, Alignment);
8415 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecEVT, LdOp);
8416 LdChain.push_back(LdOp.getValue(1));
8418 // Check if we can load the element with one instruction
8419 if (LdWidth == EVTWidth) {
8420 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
8423 // The vector element order is endianness dependent.
8425 LdWidth -= EVTWidth;
8426 unsigned Offset = 0;
8428 while (LdWidth > 0) {
8429 unsigned Increment = EVTWidth / 8;
8430 Offset += Increment;
8431 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8432 DAG.getIntPtrConstant(Increment));
8434 if (LdWidth < EVTWidth) {
8435 // Our current type we are using is too large, use a smaller size by
8436 // using a smaller power of 2
8437 unsigned oEVTWidth = EVTWidth;
8438 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8439 EVTWidth = EVT.getSizeInBits();
8440 // Readjust position and vector position based on new load type
8441 Idx = Idx * (oEVTWidth/EVTWidth);
8442 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
8445 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV,
8446 SVOffset+Offset, isVolatile,
8447 MinAlign(Alignment, Offset));
8448 LdChain.push_back(LdOp.getValue(1));
8449 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecEVT, VecOp, LdOp,
8450 DAG.getIntPtrConstant(Idx++));
8452 LdWidth -= EVTWidth;
8455 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
8458 bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
8462 // TODO: Add support for ConcatVec and the ability to load many vector
8463 // types (e.g., v4i8). This will not work when a vector register
8464 // to memory mapping is strange (e.g., vector elements are not
8465 // stored in some sequential order).
8467 // It must be true that the widen vector type is bigger than where
8468 // we need to load from.
8469 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
8470 MVT LdVT = LD->getMemoryVT();
8471 DebugLoc dl = LD->getDebugLoc();
8472 assert(LdVT.isVector() && NVT.isVector());
8473 assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
8476 SDValue Chain = LD->getChain();
8477 SDValue BasePtr = LD->getBasePtr();
8478 int SVOffset = LD->getSrcValueOffset();
8479 unsigned Alignment = LD->getAlignment();
8480 bool isVolatile = LD->isVolatile();
8481 const Value *SV = LD->getSrcValue();
8482 unsigned int LdWidth = LdVT.getSizeInBits();
8484 // Load value as a large register
8485 SDValueVector LdChain;
8486 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
8487 Alignment, isVolatile, LdWidth, NVT, dl);
8489 if (LdChain.size() == 1) {
8494 TFOp=DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8495 &LdChain[0], LdChain.size());
8501 void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
8511 // Breaks the stores into a series of power of 2 width stores. For any
8512 // width, we convert the vector to the vector of element size that we
8513 // want to store. This avoids requiring a stack convert.
8515 // Find a width of the element type we can store with
8516 MVT VVT = ValOp.getValueType();
8519 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8520 EVTWidth = EVT.getSizeInBits();
8522 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, ValOp);
8523 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
8524 DAG.getIntPtrConstant(0));
8525 SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset,
8526 isVolatile, Alignment);
8527 StChain.push_back(StOp);
8529 // Check if we are done
8530 if (StWidth == EVTWidth) {
8535 StWidth -= EVTWidth;
8536 unsigned Offset = 0;
8538 while (StWidth > 0) {
8539 unsigned Increment = EVTWidth / 8;
8540 Offset += Increment;
8541 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8542 DAG.getIntPtrConstant(Increment));
8544 if (StWidth < EVTWidth) {
8545 // Our current type we are using is too large, use a smaller size by
8546 // using a smaller power of 2
8547 unsigned oEVTWidth = EVTWidth;
8548 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8549 EVTWidth = EVT.getSizeInBits();
8550 // Readjust position and vector position based on new load type
8551 Idx = Idx * (oEVTWidth/EVTWidth);
8552 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
8555 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
8556 DAG.getIntPtrConstant(Idx++));
8557 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
8558 SVOffset + Offset, isVolatile,
8559 MinAlign(Alignment, Offset)));
8560 StWidth -= EVTWidth;
8565 SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
8568 // TODO: It might be cleaner if we can use SplitVector and have more legal
8569 // vector types that can be stored into memory (e.g., v4xi8 can
8570 // be stored as a word). This will not work when a vector register
8571 // to memory mapping is strange (e.g., vector elements are not
8572 // stored in some sequential order).
8574 MVT StVT = ST->getMemoryVT();
8575 SDValue ValOp = ST->getValue();
8576 DebugLoc dl = ST->getDebugLoc();
8578 // Check if we have widen this node with another value
8579 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
8580 if (I != WidenNodes.end())
8583 MVT VVT = ValOp.getValueType();
8585 // It must be true that we the widen vector type is bigger than where
8586 // we need to store.
8587 assert(StVT.isVector() && VVT.isVector());
8588 assert(StVT.bitsLT(VVT));
8589 assert(StVT.getVectorElementType() == VVT.getVectorElementType());
8592 SDValueVector StChain;
8593 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(),
8594 ST->getSrcValueOffset(), ST->getAlignment(),
8595 ST->isVolatile(), ValOp, StVT.getSizeInBits(), dl);
8596 if (StChain.size() == 1)
8599 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8600 &StChain[0], StChain.size());
8604 // SelectionDAG::Legalize - This is the entry point for the file.
8606 void SelectionDAG::Legalize(bool TypesNeedLegalizing) {
8607 /// run - This is the main entry point to this class.
8609 SelectionDAGLegalize(*this, TypesNeedLegalizing).LegalizeDAG();