1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
40 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
41 cl::desc("Pop up a window to show dags before legalize"));
43 static const bool ViewLegalizeDAGs = 0;
46 //===----------------------------------------------------------------------===//
47 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
48 /// hacks on it until the target machine can handle it. This involves
49 /// eliminating value sizes the machine cannot handle (promoting small sizes to
50 /// large sizes or splitting up large values into small values) as well as
51 /// eliminating operations the machine cannot handle.
53 /// This code also does a small amount of optimization and recognition of idioms
54 /// as part of its processing. For example, if a target does not support a
55 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
56 /// will attempt merge setcc and brc instructions into brcc's.
59 class VISIBILITY_HIDDEN SelectionDAGLegalize {
63 // Libcall insertion helpers.
65 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
66 /// legalized. We use this to ensure that calls are properly serialized
67 /// against each other, including inserted libcalls.
68 SDOperand LastCALLSEQ_END;
70 /// IsLegalizingCall - This member is used *only* for purposes of providing
71 /// helpful assertions that a libcall isn't created while another call is
72 /// being legalized (which could lead to non-serialized call sequences).
73 bool IsLegalizingCall;
76 Legal, // The target natively supports this operation.
77 Promote, // This operation should be executed in a larger type.
78 Expand // Try to expand this to other ops, otherwise use a libcall.
81 /// ValueTypeActions - This is a bitvector that contains two bits for each
82 /// value type, where the two bits correspond to the LegalizeAction enum.
83 /// This can be queried with "getTypeAction(VT)".
84 TargetLowering::ValueTypeActionImpl ValueTypeActions;
86 /// LegalizedNodes - For nodes that are of legal width, and that have more
87 /// than one use, this map indicates what regularized operand to use. This
88 /// allows us to avoid legalizing the same thing more than once.
89 DenseMap<SDOperand, SDOperand> LegalizedNodes;
91 /// PromotedNodes - For nodes that are below legal width, and that have more
92 /// than one use, this map indicates what promoted value to use. This allows
93 /// us to avoid promoting the same thing more than once.
94 DenseMap<SDOperand, SDOperand> PromotedNodes;
96 /// ExpandedNodes - For nodes that need to be expanded this map indicates
97 /// which which operands are the expanded version of the input. This allows
98 /// us to avoid expanding the same node more than once.
99 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
101 /// SplitNodes - For vector nodes that need to be split, this map indicates
102 /// which which operands are the split version of the input. This allows us
103 /// to avoid splitting the same node more than once.
104 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
106 /// ScalarizedNodes - For nodes that need to be converted from vector types to
107 /// scalar types, this contains the mapping of ones we have already
108 /// processed to the result.
109 std::map<SDOperand, SDOperand> ScalarizedNodes;
111 void AddLegalizedOperand(SDOperand From, SDOperand To) {
112 LegalizedNodes.insert(std::make_pair(From, To));
113 // If someone requests legalization of the new node, return itself.
115 LegalizedNodes.insert(std::make_pair(To, To));
117 void AddPromotedOperand(SDOperand From, SDOperand To) {
118 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
119 assert(isNew && "Got into the map somehow?");
120 // If someone requests legalization of the new node, return itself.
121 LegalizedNodes.insert(std::make_pair(To, To));
125 explicit SelectionDAGLegalize(SelectionDAG &DAG);
127 /// getTypeAction - Return how we should legalize values of this type, either
128 /// it is already legal or we need to expand it into multiple registers of
129 /// smaller integer type, or we need to promote it to a larger type.
130 LegalizeAction getTypeAction(MVT VT) const {
131 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
134 /// isTypeLegal - Return true if this type is legal on this target.
136 bool isTypeLegal(MVT VT) const {
137 return getTypeAction(VT) == Legal;
143 /// HandleOp - Legalize, Promote, or Expand the specified operand as
144 /// appropriate for its type.
145 void HandleOp(SDOperand Op);
147 /// LegalizeOp - We know that the specified value has a legal type.
148 /// Recursively ensure that the operands have legal types, then return the
150 SDOperand LegalizeOp(SDOperand O);
152 /// UnrollVectorOp - We know that the given vector has a legal type, however
153 /// the operation it performs is not legal and is an operation that we have
154 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
155 /// operating on each element individually.
156 SDOperand UnrollVectorOp(SDOperand O);
158 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
159 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
160 /// is necessary to spill the vector being inserted into to memory, perform
161 /// the insert there, and then read the result back.
162 SDOperand PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val,
165 /// PromoteOp - Given an operation that produces a value in an invalid type,
166 /// promote it to compute the value into a larger type. The produced value
167 /// will have the correct bits for the low portion of the register, but no
168 /// guarantee is made about the top bits: it may be zero, sign-extended, or
170 SDOperand PromoteOp(SDOperand O);
172 /// ExpandOp - Expand the specified SDOperand into its two component pieces
173 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
174 /// the LegalizeNodes map is filled in for any results that are not expanded,
175 /// the ExpandedNodes map is filled in for any results that are expanded, and
176 /// the Lo/Hi values are returned. This applies to integer types and Vector
178 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
180 /// SplitVectorOp - Given an operand of vector type, break it down into
181 /// two smaller values.
182 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
184 /// ScalarizeVectorOp - Given an operand of single-element vector type
185 /// (e.g. v1f32), convert it into the equivalent operation that returns a
186 /// scalar (e.g. f32) value.
187 SDOperand ScalarizeVectorOp(SDOperand O);
189 /// isShuffleLegal - Return true if a vector shuffle is legal with the
190 /// specified mask and type. Targets can specify exactly which masks they
191 /// support and the code generator is tasked with not creating illegal masks.
193 /// Note that this will also return true for shuffles that are promoted to a
196 /// If this is a legal shuffle, this method returns the (possibly promoted)
197 /// build_vector Mask. If it's not a legal shuffle, it returns null.
198 SDNode *isShuffleLegal(MVT VT, SDOperand Mask) const;
200 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
201 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
203 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
205 SDOperand ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
207 SDOperand ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source);
209 SDOperand EmitStackConvert(SDOperand SrcOp, MVT SlotVT, MVT DestVT);
210 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
211 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
212 SDOperand ExpandLegalINT_TO_FP(bool isSigned, SDOperand LegalOp, MVT DestVT);
213 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT DestVT, bool isSigned);
214 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT DestVT, bool isSigned);
216 SDOperand ExpandBSWAP(SDOperand Op);
217 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
218 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
219 SDOperand &Lo, SDOperand &Hi);
220 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
221 SDOperand &Lo, SDOperand &Hi);
223 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
224 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
228 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
229 /// specified mask and type. Targets can specify exactly which masks they
230 /// support and the code generator is tasked with not creating illegal masks.
232 /// Note that this will also return true for shuffles that are promoted to a
234 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDOperand Mask) const {
235 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
237 case TargetLowering::Legal:
238 case TargetLowering::Custom:
240 case TargetLowering::Promote: {
241 // If this is promoted to a different type, convert the shuffle mask and
242 // ask if it is legal in the promoted type!
243 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
245 // If we changed # elements, change the shuffle mask.
246 unsigned NumEltsGrowth =
247 NVT.getVectorNumElements() / VT.getVectorNumElements();
248 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
249 if (NumEltsGrowth > 1) {
250 // Renumber the elements.
251 SmallVector<SDOperand, 8> Ops;
252 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
253 SDOperand InOp = Mask.getOperand(i);
254 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
255 if (InOp.getOpcode() == ISD::UNDEF)
256 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
258 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
259 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
263 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
269 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
272 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
273 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
274 ValueTypeActions(TLI.getValueTypeActions()) {
275 assert(MVT::LAST_VALUETYPE <= 32 &&
276 "Too many value types for ValueTypeActions to hold!");
279 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
280 /// contains all of a nodes operands before it contains the node.
281 static void ComputeTopDownOrdering(SelectionDAG &DAG,
282 SmallVector<SDNode*, 64> &Order) {
284 DenseMap<SDNode*, unsigned> Visited;
285 std::vector<SDNode*> Worklist;
286 Worklist.reserve(128);
288 // Compute ordering from all of the leaves in the graphs, those (like the
289 // entry node) that have no operands.
290 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
291 E = DAG.allnodes_end(); I != E; ++I) {
292 if (I->getNumOperands() == 0) {
294 Worklist.push_back(I);
298 while (!Worklist.empty()) {
299 SDNode *N = Worklist.back();
302 if (++Visited[N] != N->getNumOperands())
303 continue; // Haven't visited all operands yet
307 // Now that we have N in, add anything that uses it if all of their operands
309 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
311 Worklist.push_back(UI->getUser());
314 assert(Order.size() == Visited.size() &&
315 Order.size() == DAG.allnodes_size() &&
316 "Error: DAG is cyclic!");
320 void SelectionDAGLegalize::LegalizeDAG() {
321 LastCALLSEQ_END = DAG.getEntryNode();
322 IsLegalizingCall = false;
324 // The legalize process is inherently a bottom-up recursive process (users
325 // legalize their uses before themselves). Given infinite stack space, we
326 // could just start legalizing on the root and traverse the whole graph. In
327 // practice however, this causes us to run out of stack space on large basic
328 // blocks. To avoid this problem, compute an ordering of the nodes where each
329 // node is only legalized after all of its operands are legalized.
330 SmallVector<SDNode*, 64> Order;
331 ComputeTopDownOrdering(DAG, Order);
333 for (unsigned i = 0, e = Order.size(); i != e; ++i)
334 HandleOp(SDOperand(Order[i], 0));
336 // Finally, it's possible the root changed. Get the new root.
337 SDOperand OldRoot = DAG.getRoot();
338 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
339 DAG.setRoot(LegalizedNodes[OldRoot]);
341 ExpandedNodes.clear();
342 LegalizedNodes.clear();
343 PromotedNodes.clear();
345 ScalarizedNodes.clear();
347 // Remove dead nodes now.
348 DAG.RemoveDeadNodes();
352 /// FindCallEndFromCallStart - Given a chained node that is part of a call
353 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
354 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
355 if (Node->getOpcode() == ISD::CALLSEQ_END)
357 if (Node->use_empty())
358 return 0; // No CallSeqEnd
360 // The chain is usually at the end.
361 SDOperand TheChain(Node, Node->getNumValues()-1);
362 if (TheChain.getValueType() != MVT::Other) {
363 // Sometimes it's at the beginning.
364 TheChain = SDOperand(Node, 0);
365 if (TheChain.getValueType() != MVT::Other) {
366 // Otherwise, hunt for it.
367 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
368 if (Node->getValueType(i) == MVT::Other) {
369 TheChain = SDOperand(Node, i);
373 // Otherwise, we walked into a node without a chain.
374 if (TheChain.getValueType() != MVT::Other)
379 for (SDNode::use_iterator UI = Node->use_begin(),
380 E = Node->use_end(); UI != E; ++UI) {
382 // Make sure to only follow users of our token chain.
383 SDNode *User = UI->getUser();
384 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
385 if (User->getOperand(i) == TheChain)
386 if (SDNode *Result = FindCallEndFromCallStart(User))
392 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
393 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
394 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
395 assert(Node && "Didn't find callseq_start for a call??");
396 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
398 assert(Node->getOperand(0).getValueType() == MVT::Other &&
399 "Node doesn't have a token chain argument!");
400 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
403 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
404 /// see if any uses can reach Dest. If no dest operands can get to dest,
405 /// legalize them, legalize ourself, and return false, otherwise, return true.
407 /// Keep track of the nodes we fine that actually do lead to Dest in
408 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
410 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
411 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
412 if (N == Dest) return true; // N certainly leads to Dest :)
414 // If we've already processed this node and it does lead to Dest, there is no
415 // need to reprocess it.
416 if (NodesLeadingTo.count(N)) return true;
418 // If the first result of this node has been already legalized, then it cannot
420 switch (getTypeAction(N->getValueType(0))) {
422 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
425 if (PromotedNodes.count(SDOperand(N, 0))) return false;
428 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
432 // Okay, this node has not already been legalized. Check and legalize all
433 // operands. If none lead to Dest, then we can legalize this node.
434 bool OperandsLeadToDest = false;
435 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
436 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
437 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
439 if (OperandsLeadToDest) {
440 NodesLeadingTo.insert(N);
444 // Okay, this node looks safe, legalize it and return false.
445 HandleOp(SDOperand(N, 0));
449 /// HandleOp - Legalize, Promote, or Expand the specified operand as
450 /// appropriate for its type.
451 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
452 MVT VT = Op.getValueType();
453 switch (getTypeAction(VT)) {
454 default: assert(0 && "Bad type action!");
455 case Legal: (void)LegalizeOp(Op); break;
456 case Promote: (void)PromoteOp(Op); break;
458 if (!VT.isVector()) {
459 // If this is an illegal scalar, expand it into its two component
462 if (Op.getOpcode() == ISD::TargetConstant)
463 break; // Allow illegal target nodes.
465 } else if (VT.getVectorNumElements() == 1) {
466 // If this is an illegal single element vector, convert it to a
468 (void)ScalarizeVectorOp(Op);
470 // Otherwise, this is an illegal multiple element vector.
471 // Split it in half and legalize both parts.
473 SplitVectorOp(Op, X, Y);
479 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
480 /// a load from the constant pool.
481 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
482 SelectionDAG &DAG, TargetLowering &TLI) {
485 // If a FP immediate is precise when represented as a float and if the
486 // target can do an extending load from float to double, we put it into
487 // the constant pool as a float, even if it's is statically typed as a
488 // double. This shrinks FP constants and canonicalizes them for targets where
489 // an FP extending load is the same cost as a normal load (such as on the x87
490 // fp stack or PPC FP unit).
491 MVT VT = CFP->getValueType(0);
492 ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF());
494 if (VT!=MVT::f64 && VT!=MVT::f32)
495 assert(0 && "Invalid type expansion");
496 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(),
497 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
502 while (SVT != MVT::f32) {
503 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
504 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
505 // Only do this if the target has a native EXTLOAD instruction from
507 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) &&
508 TLI.ShouldShrinkFPConstant(OrigVT)) {
509 const Type *SType = SVT.getTypeForMVT();
510 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
516 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
518 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
519 CPIdx, PseudoSourceValue::getConstantPool(),
521 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
522 PseudoSourceValue::getConstantPool(), 0);
526 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
529 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
530 SelectionDAG &DAG, TargetLowering &TLI) {
531 MVT VT = Node->getValueType(0);
532 MVT SrcVT = Node->getOperand(1).getValueType();
533 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
534 "fcopysign expansion only supported for f32 and f64");
535 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
537 // First get the sign bit of second operand.
538 SDOperand Mask1 = (SrcVT == MVT::f64)
539 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
540 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
541 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
542 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
543 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
544 // Shift right or sign-extend it if the two operands have different types.
545 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
547 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
548 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
549 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
550 } else if (SizeDiff < 0)
551 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
553 // Clear the sign bit of first operand.
554 SDOperand Mask2 = (VT == MVT::f64)
555 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
556 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
557 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
558 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
559 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
561 // Or the value with the sign bit.
562 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
566 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
568 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
569 TargetLowering &TLI) {
570 SDOperand Chain = ST->getChain();
571 SDOperand Ptr = ST->getBasePtr();
572 SDOperand Val = ST->getValue();
573 MVT VT = Val.getValueType();
574 int Alignment = ST->getAlignment();
575 int SVOffset = ST->getSrcValueOffset();
576 if (ST->getMemoryVT().isFloatingPoint() ||
577 ST->getMemoryVT().isVector()) {
578 // Expand to a bitconvert of the value to the integer type of the
579 // same size, then a (misaligned) int store.
581 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128)
583 else if (VT.is64BitVector() || VT==MVT::f64)
585 else if (VT==MVT::f32)
588 assert(0 && "Unaligned store of unsupported type");
590 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
591 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
592 SVOffset, ST->isVolatile(), Alignment);
594 assert(ST->getMemoryVT().isInteger() &&
595 !ST->getMemoryVT().isVector() &&
596 "Unaligned store of unknown type.");
597 // Get the half-size VT
599 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
600 int NumBits = NewStoredVT.getSizeInBits();
601 int IncrementSize = NumBits / 8;
603 // Divide the stored value in two parts.
604 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
606 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
608 // Store the two parts
609 SDOperand Store1, Store2;
610 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
611 ST->getSrcValue(), SVOffset, NewStoredVT,
612 ST->isVolatile(), Alignment);
613 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
614 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
615 Alignment = MinAlign(Alignment, IncrementSize);
616 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
617 ST->getSrcValue(), SVOffset + IncrementSize,
618 NewStoredVT, ST->isVolatile(), Alignment);
620 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
623 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
625 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
626 TargetLowering &TLI) {
627 int SVOffset = LD->getSrcValueOffset();
628 SDOperand Chain = LD->getChain();
629 SDOperand Ptr = LD->getBasePtr();
630 MVT VT = LD->getValueType(0);
631 MVT LoadedVT = LD->getMemoryVT();
632 if (VT.isFloatingPoint() || VT.isVector()) {
633 // Expand to a (misaligned) integer load of the same size,
634 // then bitconvert to floating point or vector.
636 if (LoadedVT.is128BitVector() ||
637 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
639 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64)
641 else if (LoadedVT == MVT::f32)
644 assert(0 && "Unaligned load of unsupported type");
646 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
647 SVOffset, LD->isVolatile(),
649 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
650 if (VT.isFloatingPoint() && LoadedVT != VT)
651 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
653 SDOperand Ops[] = { Result, Chain };
654 return DAG.getMergeValues(Ops, 2);
656 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
657 "Unaligned load of unsupported type.");
659 // Compute the new VT that is half the size of the old one. This is an
661 unsigned NumBits = LoadedVT.getSizeInBits();
663 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
666 unsigned Alignment = LD->getAlignment();
667 unsigned IncrementSize = NumBits / 8;
668 ISD::LoadExtType HiExtType = LD->getExtensionType();
670 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
671 if (HiExtType == ISD::NON_EXTLOAD)
672 HiExtType = ISD::ZEXTLOAD;
674 // Load the value in two parts
676 if (TLI.isLittleEndian()) {
677 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
678 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
679 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
680 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
681 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
682 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
683 MinAlign(Alignment, IncrementSize));
685 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
686 NewLoadedVT,LD->isVolatile(), Alignment);
687 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
688 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
689 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
690 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
691 MinAlign(Alignment, IncrementSize));
694 // aggregate the two parts
695 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
696 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
697 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
699 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
702 SDOperand Ops[] = { Result, TF };
703 return DAG.getMergeValues(Ops, 2);
706 /// UnrollVectorOp - We know that the given vector has a legal type, however
707 /// the operation it performs is not legal and is an operation that we have
708 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
709 /// operating on each element individually.
710 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
711 MVT VT = Op.getValueType();
712 assert(isTypeLegal(VT) &&
713 "Caller should expand or promote operands that are not legal!");
714 assert(Op.Val->getNumValues() == 1 &&
715 "Can't unroll a vector with multiple results!");
716 unsigned NE = VT.getVectorNumElements();
717 MVT EltVT = VT.getVectorElementType();
719 SmallVector<SDOperand, 8> Scalars;
720 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
721 for (unsigned i = 0; i != NE; ++i) {
722 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
723 SDOperand Operand = Op.getOperand(j);
724 MVT OperandVT = Operand.getValueType();
725 if (OperandVT.isVector()) {
726 // A vector operand; extract a single element.
727 MVT OperandEltVT = OperandVT.getVectorElementType();
728 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
731 DAG.getConstant(i, MVT::i32));
733 // A scalar operand; just use it as is.
734 Operands[j] = Operand;
737 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
738 &Operands[0], Operands.size()));
741 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
744 /// GetFPLibCall - Return the right libcall for the given floating point type.
745 static RTLIB::Libcall GetFPLibCall(MVT VT,
746 RTLIB::Libcall Call_F32,
747 RTLIB::Libcall Call_F64,
748 RTLIB::Libcall Call_F80,
749 RTLIB::Libcall Call_PPCF128) {
751 VT == MVT::f32 ? Call_F32 :
752 VT == MVT::f64 ? Call_F64 :
753 VT == MVT::f80 ? Call_F80 :
754 VT == MVT::ppcf128 ? Call_PPCF128 :
755 RTLIB::UNKNOWN_LIBCALL;
758 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
759 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
760 /// is necessary to spill the vector being inserted into to memory, perform
761 /// the insert there, and then read the result back.
762 SDOperand SelectionDAGLegalize::
763 PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) {
764 SDOperand Tmp1 = Vec;
765 SDOperand Tmp2 = Val;
766 SDOperand Tmp3 = Idx;
768 // If the target doesn't support this, we have to spill the input vector
769 // to a temporary stack slot, update the element, then reload it. This is
770 // badness. We could also load the value into a vector register (either
771 // with a "move to register" or "extload into register" instruction, then
772 // permute it into place, if the idx is a constant and if the idx is
773 // supported by the target.
774 MVT VT = Tmp1.getValueType();
775 MVT EltVT = VT.getVectorElementType();
776 MVT IdxVT = Tmp3.getValueType();
777 MVT PtrVT = TLI.getPointerTy();
778 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
780 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val);
781 int SPFI = StackPtrFI->getIndex();
784 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
785 PseudoSourceValue::getFixedStack(),
788 // Truncate or zero extend offset to target pointer type.
789 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
790 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
791 // Add the offset to the index.
792 unsigned EltSize = EltVT.getSizeInBits()/8;
793 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
794 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
795 // Store the scalar value.
796 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
797 PseudoSourceValue::getFixedStack(), SPFI, EltVT);
798 // Load the updated vector.
799 return DAG.getLoad(VT, Ch, StackPtr, PseudoSourceValue::getFixedStack(),SPFI);
802 /// LegalizeOp - We know that the specified value has a legal type, and
803 /// that its operands are legal. Now ensure that the operation itself
804 /// is legal, recursively ensuring that the operands' operations remain
806 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
807 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
810 assert(isTypeLegal(Op.getValueType()) &&
811 "Caller should expand or promote operands that are not legal!");
812 SDNode *Node = Op.Val;
814 // If this operation defines any values that cannot be represented in a
815 // register on this target, make sure to expand or promote them.
816 if (Node->getNumValues() > 1) {
817 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
818 if (getTypeAction(Node->getValueType(i)) != Legal) {
819 HandleOp(Op.getValue(i));
820 assert(LegalizedNodes.count(Op) &&
821 "Handling didn't add legal operands!");
822 return LegalizedNodes[Op];
826 // Note that LegalizeOp may be reentered even from single-use nodes, which
827 // means that we always must cache transformed nodes.
828 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
829 if (I != LegalizedNodes.end()) return I->second;
831 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
832 SDOperand Result = Op;
833 bool isCustom = false;
835 switch (Node->getOpcode()) {
836 case ISD::FrameIndex:
837 case ISD::EntryToken:
839 case ISD::BasicBlock:
840 case ISD::TargetFrameIndex:
841 case ISD::TargetJumpTable:
842 case ISD::TargetConstant:
843 case ISD::TargetConstantFP:
844 case ISD::TargetConstantPool:
845 case ISD::TargetGlobalAddress:
846 case ISD::TargetGlobalTLSAddress:
847 case ISD::TargetExternalSymbol:
850 case ISD::MEMOPERAND:
853 // Primitives must all be legal.
854 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
855 "This must be legal!");
858 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
859 // If this is a target node, legalize it by legalizing the operands then
860 // passing it through.
861 SmallVector<SDOperand, 8> Ops;
862 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
863 Ops.push_back(LegalizeOp(Node->getOperand(i)));
865 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
867 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
868 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
869 return Result.getValue(Op.ResNo);
871 // Otherwise this is an unhandled builtin node. splat.
873 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
875 assert(0 && "Do not know how to legalize this operator!");
877 case ISD::GLOBAL_OFFSET_TABLE:
878 case ISD::GlobalAddress:
879 case ISD::GlobalTLSAddress:
880 case ISD::ExternalSymbol:
881 case ISD::ConstantPool:
882 case ISD::JumpTable: // Nothing to do.
883 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
884 default: assert(0 && "This action is not supported yet!");
885 case TargetLowering::Custom:
886 Tmp1 = TLI.LowerOperation(Op, DAG);
887 if (Tmp1.Val) Result = Tmp1;
888 // FALLTHROUGH if the target doesn't want to lower this op after all.
889 case TargetLowering::Legal:
894 case ISD::RETURNADDR:
895 // The only option for these nodes is to custom lower them. If the target
896 // does not custom lower them, then return zero.
897 Tmp1 = TLI.LowerOperation(Op, DAG);
901 Result = DAG.getConstant(0, TLI.getPointerTy());
903 case ISD::FRAME_TO_ARGS_OFFSET: {
904 MVT VT = Node->getValueType(0);
905 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
906 default: assert(0 && "This action is not supported yet!");
907 case TargetLowering::Custom:
908 Result = TLI.LowerOperation(Op, DAG);
909 if (Result.Val) break;
911 case TargetLowering::Legal:
912 Result = DAG.getConstant(0, VT);
917 case ISD::EXCEPTIONADDR: {
918 Tmp1 = LegalizeOp(Node->getOperand(0));
919 MVT VT = Node->getValueType(0);
920 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
921 default: assert(0 && "This action is not supported yet!");
922 case TargetLowering::Expand: {
923 unsigned Reg = TLI.getExceptionAddressRegister();
924 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
927 case TargetLowering::Custom:
928 Result = TLI.LowerOperation(Op, DAG);
929 if (Result.Val) break;
931 case TargetLowering::Legal: {
932 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
933 Result = DAG.getMergeValues(Ops, 2);
938 if (Result.Val->getNumValues() == 1) break;
940 assert(Result.Val->getNumValues() == 2 &&
941 "Cannot return more than two values!");
943 // Since we produced two values, make sure to remember that we
944 // legalized both of them.
945 Tmp1 = LegalizeOp(Result);
946 Tmp2 = LegalizeOp(Result.getValue(1));
947 AddLegalizedOperand(Op.getValue(0), Tmp1);
948 AddLegalizedOperand(Op.getValue(1), Tmp2);
949 return Op.ResNo ? Tmp2 : Tmp1;
950 case ISD::EHSELECTION: {
951 Tmp1 = LegalizeOp(Node->getOperand(0));
952 Tmp2 = LegalizeOp(Node->getOperand(1));
953 MVT VT = Node->getValueType(0);
954 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
955 default: assert(0 && "This action is not supported yet!");
956 case TargetLowering::Expand: {
957 unsigned Reg = TLI.getExceptionSelectorRegister();
958 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
961 case TargetLowering::Custom:
962 Result = TLI.LowerOperation(Op, DAG);
963 if (Result.Val) break;
965 case TargetLowering::Legal: {
966 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
967 Result = DAG.getMergeValues(Ops, 2);
972 if (Result.Val->getNumValues() == 1) break;
974 assert(Result.Val->getNumValues() == 2 &&
975 "Cannot return more than two values!");
977 // Since we produced two values, make sure to remember that we
978 // legalized both of them.
979 Tmp1 = LegalizeOp(Result);
980 Tmp2 = LegalizeOp(Result.getValue(1));
981 AddLegalizedOperand(Op.getValue(0), Tmp1);
982 AddLegalizedOperand(Op.getValue(1), Tmp2);
983 return Op.ResNo ? Tmp2 : Tmp1;
984 case ISD::EH_RETURN: {
985 MVT VT = Node->getValueType(0);
986 // The only "good" option for this node is to custom lower it.
987 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
988 default: assert(0 && "This action is not supported at all!");
989 case TargetLowering::Custom:
990 Result = TLI.LowerOperation(Op, DAG);
991 if (Result.Val) break;
993 case TargetLowering::Legal:
994 // Target does not know, how to lower this, lower to noop
995 Result = LegalizeOp(Node->getOperand(0));
1000 case ISD::AssertSext:
1001 case ISD::AssertZext:
1002 Tmp1 = LegalizeOp(Node->getOperand(0));
1003 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1005 case ISD::MERGE_VALUES:
1006 // Legalize eliminates MERGE_VALUES nodes.
1007 Result = Node->getOperand(Op.ResNo);
1009 case ISD::CopyFromReg:
1010 Tmp1 = LegalizeOp(Node->getOperand(0));
1011 Result = Op.getValue(0);
1012 if (Node->getNumValues() == 2) {
1013 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1015 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1016 if (Node->getNumOperands() == 3) {
1017 Tmp2 = LegalizeOp(Node->getOperand(2));
1018 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1020 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1022 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1024 // Since CopyFromReg produces two values, make sure to remember that we
1025 // legalized both of them.
1026 AddLegalizedOperand(Op.getValue(0), Result);
1027 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1028 return Result.getValue(Op.ResNo);
1030 MVT VT = Op.getValueType();
1031 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1032 default: assert(0 && "This action is not supported yet!");
1033 case TargetLowering::Expand:
1035 Result = DAG.getConstant(0, VT);
1036 else if (VT.isFloatingPoint())
1037 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1040 assert(0 && "Unknown value type!");
1042 case TargetLowering::Legal:
1048 case ISD::INTRINSIC_W_CHAIN:
1049 case ISD::INTRINSIC_WO_CHAIN:
1050 case ISD::INTRINSIC_VOID: {
1051 SmallVector<SDOperand, 8> Ops;
1052 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1053 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1054 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1056 // Allow the target to custom lower its intrinsics if it wants to.
1057 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1058 TargetLowering::Custom) {
1059 Tmp3 = TLI.LowerOperation(Result, DAG);
1060 if (Tmp3.Val) Result = Tmp3;
1063 if (Result.Val->getNumValues() == 1) break;
1065 // Must have return value and chain result.
1066 assert(Result.Val->getNumValues() == 2 &&
1067 "Cannot return more than two values!");
1069 // Since loads produce two values, make sure to remember that we
1070 // legalized both of them.
1071 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1072 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1073 return Result.getValue(Op.ResNo);
1076 case ISD::DBG_STOPPOINT:
1077 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1078 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1080 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1081 case TargetLowering::Promote:
1082 default: assert(0 && "This action is not supported yet!");
1083 case TargetLowering::Expand: {
1084 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1085 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1086 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
1088 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1089 if (MMI && (useDEBUG_LOC || useLABEL)) {
1090 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
1091 unsigned SrcFile = MMI->RecordSource(CompileUnit);
1093 unsigned Line = DSP->getLine();
1094 unsigned Col = DSP->getColumn();
1097 SDOperand Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1098 DAG.getConstant(Col, MVT::i32),
1099 DAG.getConstant(SrcFile, MVT::i32) };
1100 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
1102 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1103 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1106 Result = Tmp1; // chain
1110 case TargetLowering::Legal: {
1111 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1112 if (Action == Legal && Tmp1 == Node->getOperand(0))
1115 SmallVector<SDOperand, 8> Ops;
1116 Ops.push_back(Tmp1);
1117 if (Action == Legal) {
1118 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1119 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1121 // Otherwise promote them.
1122 Ops.push_back(PromoteOp(Node->getOperand(1)));
1123 Ops.push_back(PromoteOp(Node->getOperand(2)));
1125 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1126 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1127 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1134 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1135 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1136 default: assert(0 && "This action is not supported yet!");
1137 case TargetLowering::Legal:
1138 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1139 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1140 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1141 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1143 case TargetLowering::Expand:
1144 Result = LegalizeOp(Node->getOperand(0));
1149 case ISD::DEBUG_LOC:
1150 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1151 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1152 default: assert(0 && "This action is not supported yet!");
1153 case TargetLowering::Legal: {
1154 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1155 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1156 if (Action == Legal && Tmp1 == Node->getOperand(0))
1158 if (Action == Legal) {
1159 Tmp2 = Node->getOperand(1);
1160 Tmp3 = Node->getOperand(2);
1161 Tmp4 = Node->getOperand(3);
1163 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1164 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1165 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1167 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1173 case ISD::DBG_LABEL:
1175 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1176 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1177 default: assert(0 && "This action is not supported yet!");
1178 case TargetLowering::Legal:
1179 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1180 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1182 case TargetLowering::Expand:
1183 Result = LegalizeOp(Node->getOperand(0));
1189 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1190 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1191 default: assert(0 && "This action is not supported yet!");
1192 case TargetLowering::Legal:
1193 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1194 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1195 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1196 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1197 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1199 case TargetLowering::Expand:
1201 Result = LegalizeOp(Node->getOperand(0));
1206 case ISD::MEMBARRIER: {
1207 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1208 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1209 default: assert(0 && "This action is not supported yet!");
1210 case TargetLowering::Legal: {
1212 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1213 for (int x = 1; x < 6; ++x) {
1214 Ops[x] = Node->getOperand(x);
1215 if (!isTypeLegal(Ops[x].getValueType()))
1216 Ops[x] = PromoteOp(Ops[x]);
1218 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1221 case TargetLowering::Expand:
1222 //There is no libgcc call for this op
1223 Result = Node->getOperand(0); // Noop
1229 case ISD::ATOMIC_CMP_SWAP: {
1230 unsigned int num_operands = 4;
1231 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1233 for (unsigned int x = 0; x < num_operands; ++x)
1234 Ops[x] = LegalizeOp(Node->getOperand(x));
1235 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1237 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1238 default: assert(0 && "This action is not supported yet!");
1239 case TargetLowering::Custom:
1240 Result = TLI.LowerOperation(Result, DAG);
1242 case TargetLowering::Legal:
1245 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1246 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1247 return Result.getValue(Op.ResNo);
1249 case ISD::ATOMIC_LOAD_ADD:
1250 case ISD::ATOMIC_LOAD_SUB:
1251 case ISD::ATOMIC_LOAD_AND:
1252 case ISD::ATOMIC_LOAD_OR:
1253 case ISD::ATOMIC_LOAD_XOR:
1254 case ISD::ATOMIC_LOAD_NAND:
1255 case ISD::ATOMIC_LOAD_MIN:
1256 case ISD::ATOMIC_LOAD_MAX:
1257 case ISD::ATOMIC_LOAD_UMIN:
1258 case ISD::ATOMIC_LOAD_UMAX:
1259 case ISD::ATOMIC_SWAP: {
1260 unsigned int num_operands = 3;
1261 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1263 for (unsigned int x = 0; x < num_operands; ++x)
1264 Ops[x] = LegalizeOp(Node->getOperand(x));
1265 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1267 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1268 default: assert(0 && "This action is not supported yet!");
1269 case TargetLowering::Custom:
1270 Result = TLI.LowerOperation(Result, DAG);
1272 case TargetLowering::Expand:
1273 Result = SDOperand(TLI.ReplaceNodeResults(Op.Val, DAG),0);
1275 case TargetLowering::Legal:
1278 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1279 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1280 return Result.getValue(Op.ResNo);
1282 case ISD::Constant: {
1283 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1285 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1287 // We know we don't need to expand constants here, constants only have one
1288 // value and we check that it is fine above.
1290 if (opAction == TargetLowering::Custom) {
1291 Tmp1 = TLI.LowerOperation(Result, DAG);
1297 case ISD::ConstantFP: {
1298 // Spill FP immediates to the constant pool if the target cannot directly
1299 // codegen them. Targets often have some immediate values that can be
1300 // efficiently generated into an FP register without a load. We explicitly
1301 // leave these constants as ConstantFP nodes for the target to deal with.
1302 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1304 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1305 default: assert(0 && "This action is not supported yet!");
1306 case TargetLowering::Legal:
1308 case TargetLowering::Custom:
1309 Tmp3 = TLI.LowerOperation(Result, DAG);
1315 case TargetLowering::Expand: {
1316 // Check to see if this FP immediate is already legal.
1317 bool isLegal = false;
1318 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1319 E = TLI.legal_fpimm_end(); I != E; ++I) {
1320 if (CFP->isExactlyValue(*I)) {
1325 // If this is a legal constant, turn it into a TargetConstantFP node.
1328 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1333 case ISD::TokenFactor:
1334 if (Node->getNumOperands() == 2) {
1335 Tmp1 = LegalizeOp(Node->getOperand(0));
1336 Tmp2 = LegalizeOp(Node->getOperand(1));
1337 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1338 } else if (Node->getNumOperands() == 3) {
1339 Tmp1 = LegalizeOp(Node->getOperand(0));
1340 Tmp2 = LegalizeOp(Node->getOperand(1));
1341 Tmp3 = LegalizeOp(Node->getOperand(2));
1342 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1344 SmallVector<SDOperand, 8> Ops;
1345 // Legalize the operands.
1346 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1347 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1348 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1352 case ISD::FORMAL_ARGUMENTS:
1354 // The only option for this is to custom lower it.
1355 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1356 assert(Tmp3.Val && "Target didn't custom lower this node!");
1357 // A call within a calling sequence must be legalized to something
1358 // other than the normal CALLSEQ_END. Violating this gets Legalize
1359 // into an infinite loop.
1360 assert ((!IsLegalizingCall ||
1361 Node->getOpcode() != ISD::CALL ||
1362 Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) &&
1363 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1365 // The number of incoming and outgoing values should match; unless the final
1366 // outgoing value is a flag.
1367 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1368 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1369 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1371 "Lowering call/formal_arguments produced unexpected # results!");
1373 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1374 // remember that we legalized all of them, so it doesn't get relegalized.
1375 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1376 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1378 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1381 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1384 case ISD::EXTRACT_SUBREG: {
1385 Tmp1 = LegalizeOp(Node->getOperand(0));
1386 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1387 assert(idx && "Operand must be a constant");
1388 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1389 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1392 case ISD::INSERT_SUBREG: {
1393 Tmp1 = LegalizeOp(Node->getOperand(0));
1394 Tmp2 = LegalizeOp(Node->getOperand(1));
1395 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1396 assert(idx && "Operand must be a constant");
1397 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1398 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1401 case ISD::BUILD_VECTOR:
1402 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1403 default: assert(0 && "This action is not supported yet!");
1404 case TargetLowering::Custom:
1405 Tmp3 = TLI.LowerOperation(Result, DAG);
1411 case TargetLowering::Expand:
1412 Result = ExpandBUILD_VECTOR(Result.Val);
1416 case ISD::INSERT_VECTOR_ELT:
1417 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1418 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1420 // The type of the value to insert may not be legal, even though the vector
1421 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1423 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1424 default: assert(0 && "Cannot expand insert element operand");
1425 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1426 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1428 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1430 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1431 Node->getValueType(0))) {
1432 default: assert(0 && "This action is not supported yet!");
1433 case TargetLowering::Legal:
1435 case TargetLowering::Custom:
1436 Tmp4 = TLI.LowerOperation(Result, DAG);
1442 case TargetLowering::Expand: {
1443 // If the insert index is a constant, codegen this as a scalar_to_vector,
1444 // then a shuffle that inserts it into the right position in the vector.
1445 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1446 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1447 // match the element type of the vector being created.
1448 if (Tmp2.getValueType() ==
1449 Op.getValueType().getVectorElementType()) {
1450 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1451 Tmp1.getValueType(), Tmp2);
1453 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1455 MVT::getIntVectorWithNumElements(NumElts);
1456 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1458 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1459 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1460 // elt 0 of the RHS.
1461 SmallVector<SDOperand, 8> ShufOps;
1462 for (unsigned i = 0; i != NumElts; ++i) {
1463 if (i != InsertPos->getValue())
1464 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1466 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1468 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1469 &ShufOps[0], ShufOps.size());
1471 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1472 Tmp1, ScVec, ShufMask);
1473 Result = LegalizeOp(Result);
1477 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1482 case ISD::SCALAR_TO_VECTOR:
1483 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1484 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1488 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1489 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1490 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1491 Node->getValueType(0))) {
1492 default: assert(0 && "This action is not supported yet!");
1493 case TargetLowering::Legal:
1495 case TargetLowering::Custom:
1496 Tmp3 = TLI.LowerOperation(Result, DAG);
1502 case TargetLowering::Expand:
1503 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1507 case ISD::VECTOR_SHUFFLE:
1508 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1509 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1510 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1512 // Allow targets to custom lower the SHUFFLEs they support.
1513 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1514 default: assert(0 && "Unknown operation action!");
1515 case TargetLowering::Legal:
1516 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1517 "vector shuffle should not be created if not legal!");
1519 case TargetLowering::Custom:
1520 Tmp3 = TLI.LowerOperation(Result, DAG);
1526 case TargetLowering::Expand: {
1527 MVT VT = Node->getValueType(0);
1528 MVT EltVT = VT.getVectorElementType();
1529 MVT PtrVT = TLI.getPointerTy();
1530 SDOperand Mask = Node->getOperand(2);
1531 unsigned NumElems = Mask.getNumOperands();
1532 SmallVector<SDOperand,8> Ops;
1533 for (unsigned i = 0; i != NumElems; ++i) {
1534 SDOperand Arg = Mask.getOperand(i);
1535 if (Arg.getOpcode() == ISD::UNDEF) {
1536 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1538 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1539 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1541 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1542 DAG.getConstant(Idx, PtrVT)));
1544 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1545 DAG.getConstant(Idx - NumElems, PtrVT)));
1548 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1551 case TargetLowering::Promote: {
1552 // Change base type to a different vector type.
1553 MVT OVT = Node->getValueType(0);
1554 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1556 // Cast the two input vectors.
1557 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1558 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1560 // Convert the shuffle mask to the right # elements.
1561 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1562 assert(Tmp3.Val && "Shuffle not legal?");
1563 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1564 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1570 case ISD::EXTRACT_VECTOR_ELT:
1571 Tmp1 = Node->getOperand(0);
1572 Tmp2 = LegalizeOp(Node->getOperand(1));
1573 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1574 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1577 case ISD::EXTRACT_SUBVECTOR:
1578 Tmp1 = Node->getOperand(0);
1579 Tmp2 = LegalizeOp(Node->getOperand(1));
1580 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1581 Result = ExpandEXTRACT_SUBVECTOR(Result);
1584 case ISD::CALLSEQ_START: {
1585 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1587 // Recursively Legalize all of the inputs of the call end that do not lead
1588 // to this call start. This ensures that any libcalls that need be inserted
1589 // are inserted *before* the CALLSEQ_START.
1590 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1591 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1592 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1596 // Now that we legalized all of the inputs (which may have inserted
1597 // libcalls) create the new CALLSEQ_START node.
1598 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1600 // Merge in the last call, to ensure that this call start after the last
1602 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1603 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1604 Tmp1 = LegalizeOp(Tmp1);
1607 // Do not try to legalize the target-specific arguments (#1+).
1608 if (Tmp1 != Node->getOperand(0)) {
1609 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1611 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1614 // Remember that the CALLSEQ_START is legalized.
1615 AddLegalizedOperand(Op.getValue(0), Result);
1616 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1617 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1619 // Now that the callseq_start and all of the non-call nodes above this call
1620 // sequence have been legalized, legalize the call itself. During this
1621 // process, no libcalls can/will be inserted, guaranteeing that no calls
1623 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1624 // Note that we are selecting this call!
1625 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1626 IsLegalizingCall = true;
1628 // Legalize the call, starting from the CALLSEQ_END.
1629 LegalizeOp(LastCALLSEQ_END);
1630 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1633 case ISD::CALLSEQ_END:
1634 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1635 // will cause this node to be legalized as well as handling libcalls right.
1636 if (LastCALLSEQ_END.Val != Node) {
1637 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1638 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1639 assert(I != LegalizedNodes.end() &&
1640 "Legalizing the call start should have legalized this node!");
1644 // Otherwise, the call start has been legalized and everything is going
1645 // according to plan. Just legalize ourselves normally here.
1646 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1647 // Do not try to legalize the target-specific arguments (#1+), except for
1648 // an optional flag input.
1649 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1650 if (Tmp1 != Node->getOperand(0)) {
1651 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1653 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1656 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1657 if (Tmp1 != Node->getOperand(0) ||
1658 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1659 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1662 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1665 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1666 // This finishes up call legalization.
1667 IsLegalizingCall = false;
1669 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1670 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1671 if (Node->getNumValues() == 2)
1672 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1673 return Result.getValue(Op.ResNo);
1674 case ISD::DYNAMIC_STACKALLOC: {
1675 MVT VT = Node->getValueType(0);
1676 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1677 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1678 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1679 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1681 Tmp1 = Result.getValue(0);
1682 Tmp2 = Result.getValue(1);
1683 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1684 default: assert(0 && "This action is not supported yet!");
1685 case TargetLowering::Expand: {
1686 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1687 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1688 " not tell us which reg is the stack pointer!");
1689 SDOperand Chain = Tmp1.getOperand(0);
1691 // Chain the dynamic stack allocation so that it doesn't modify the stack
1692 // pointer when other instructions are using the stack.
1693 Chain = DAG.getCALLSEQ_START(Chain,
1694 DAG.getConstant(0, TLI.getPointerTy()));
1696 SDOperand Size = Tmp2.getOperand(1);
1697 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1698 Chain = SP.getValue(1);
1699 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1700 unsigned StackAlign =
1701 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1702 if (Align > StackAlign)
1703 SP = DAG.getNode(ISD::AND, VT, SP,
1704 DAG.getConstant(-(uint64_t)Align, VT));
1705 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1706 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1709 DAG.getCALLSEQ_END(Chain,
1710 DAG.getConstant(0, TLI.getPointerTy()),
1711 DAG.getConstant(0, TLI.getPointerTy()),
1714 Tmp1 = LegalizeOp(Tmp1);
1715 Tmp2 = LegalizeOp(Tmp2);
1718 case TargetLowering::Custom:
1719 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1721 Tmp1 = LegalizeOp(Tmp3);
1722 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1725 case TargetLowering::Legal:
1728 // Since this op produce two values, make sure to remember that we
1729 // legalized both of them.
1730 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1731 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1732 return Op.ResNo ? Tmp2 : Tmp1;
1734 case ISD::INLINEASM: {
1735 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1736 bool Changed = false;
1737 // Legalize all of the operands of the inline asm, in case they are nodes
1738 // that need to be expanded or something. Note we skip the asm string and
1739 // all of the TargetConstant flags.
1740 SDOperand Op = LegalizeOp(Ops[0]);
1741 Changed = Op != Ops[0];
1744 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1745 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1746 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1747 for (++i; NumVals; ++i, --NumVals) {
1748 SDOperand Op = LegalizeOp(Ops[i]);
1757 Op = LegalizeOp(Ops.back());
1758 Changed |= Op != Ops.back();
1763 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1765 // INLINE asm returns a chain and flag, make sure to add both to the map.
1766 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1767 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1768 return Result.getValue(Op.ResNo);
1771 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1772 // Ensure that libcalls are emitted before a branch.
1773 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1774 Tmp1 = LegalizeOp(Tmp1);
1775 LastCALLSEQ_END = DAG.getEntryNode();
1777 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1780 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1781 // Ensure that libcalls are emitted before a branch.
1782 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1783 Tmp1 = LegalizeOp(Tmp1);
1784 LastCALLSEQ_END = DAG.getEntryNode();
1786 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1787 default: assert(0 && "Indirect target must be legal type (pointer)!");
1789 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1792 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1795 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1796 // Ensure that libcalls are emitted before a branch.
1797 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1798 Tmp1 = LegalizeOp(Tmp1);
1799 LastCALLSEQ_END = DAG.getEntryNode();
1801 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1802 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1804 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1805 default: assert(0 && "This action is not supported yet!");
1806 case TargetLowering::Legal: break;
1807 case TargetLowering::Custom:
1808 Tmp1 = TLI.LowerOperation(Result, DAG);
1809 if (Tmp1.Val) Result = Tmp1;
1811 case TargetLowering::Expand: {
1812 SDOperand Chain = Result.getOperand(0);
1813 SDOperand Table = Result.getOperand(1);
1814 SDOperand Index = Result.getOperand(2);
1816 MVT PTy = TLI.getPointerTy();
1817 MachineFunction &MF = DAG.getMachineFunction();
1818 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1819 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1820 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1823 switch (EntrySize) {
1824 default: assert(0 && "Size of jump table not supported yet."); break;
1825 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1826 PseudoSourceValue::getJumpTable(), 0); break;
1827 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1828 PseudoSourceValue::getJumpTable(), 0); break;
1832 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1833 // For PIC, the sequence is:
1834 // BRIND(load(Jumptable + index) + RelocBase)
1835 // RelocBase can be JumpTable, GOT or some sort of global base.
1836 if (PTy != MVT::i32)
1837 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1838 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1839 TLI.getPICJumpTableRelocBase(Table, DAG));
1841 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1846 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1847 // Ensure that libcalls are emitted before a return.
1848 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1849 Tmp1 = LegalizeOp(Tmp1);
1850 LastCALLSEQ_END = DAG.getEntryNode();
1852 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1853 case Expand: assert(0 && "It's impossible to expand bools");
1855 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1858 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1860 // The top bits of the promoted condition are not necessarily zero, ensure
1861 // that the value is properly zero extended.
1862 unsigned BitWidth = Tmp2.getValueSizeInBits();
1863 if (!DAG.MaskedValueIsZero(Tmp2,
1864 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1865 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1870 // Basic block destination (Op#2) is always legal.
1871 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1873 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1874 default: assert(0 && "This action is not supported yet!");
1875 case TargetLowering::Legal: break;
1876 case TargetLowering::Custom:
1877 Tmp1 = TLI.LowerOperation(Result, DAG);
1878 if (Tmp1.Val) Result = Tmp1;
1880 case TargetLowering::Expand:
1881 // Expand brcond's setcc into its constituent parts and create a BR_CC
1883 if (Tmp2.getOpcode() == ISD::SETCC) {
1884 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1885 Tmp2.getOperand(0), Tmp2.getOperand(1),
1886 Node->getOperand(2));
1888 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1889 DAG.getCondCode(ISD::SETNE), Tmp2,
1890 DAG.getConstant(0, Tmp2.getValueType()),
1891 Node->getOperand(2));
1897 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1898 // Ensure that libcalls are emitted before a branch.
1899 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1900 Tmp1 = LegalizeOp(Tmp1);
1901 Tmp2 = Node->getOperand(2); // LHS
1902 Tmp3 = Node->getOperand(3); // RHS
1903 Tmp4 = Node->getOperand(1); // CC
1905 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1906 LastCALLSEQ_END = DAG.getEntryNode();
1908 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1909 // the LHS is a legal SETCC itself. In this case, we need to compare
1910 // the result against zero to select between true and false values.
1911 if (Tmp3.Val == 0) {
1912 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1913 Tmp4 = DAG.getCondCode(ISD::SETNE);
1916 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1917 Node->getOperand(4));
1919 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1920 default: assert(0 && "Unexpected action for BR_CC!");
1921 case TargetLowering::Legal: break;
1922 case TargetLowering::Custom:
1923 Tmp4 = TLI.LowerOperation(Result, DAG);
1924 if (Tmp4.Val) Result = Tmp4;
1929 LoadSDNode *LD = cast<LoadSDNode>(Node);
1930 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1931 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1933 ISD::LoadExtType ExtType = LD->getExtensionType();
1934 if (ExtType == ISD::NON_EXTLOAD) {
1935 MVT VT = Node->getValueType(0);
1936 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1937 Tmp3 = Result.getValue(0);
1938 Tmp4 = Result.getValue(1);
1940 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1941 default: assert(0 && "This action is not supported yet!");
1942 case TargetLowering::Legal:
1943 // If this is an unaligned load and the target doesn't support it,
1945 if (!TLI.allowsUnalignedMemoryAccesses()) {
1946 unsigned ABIAlignment = TLI.getTargetData()->
1947 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
1948 if (LD->getAlignment() < ABIAlignment){
1949 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1951 Tmp3 = Result.getOperand(0);
1952 Tmp4 = Result.getOperand(1);
1953 Tmp3 = LegalizeOp(Tmp3);
1954 Tmp4 = LegalizeOp(Tmp4);
1958 case TargetLowering::Custom:
1959 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1961 Tmp3 = LegalizeOp(Tmp1);
1962 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1965 case TargetLowering::Promote: {
1966 // Only promote a load of vector type to another.
1967 assert(VT.isVector() && "Cannot promote this load!");
1968 // Change base type to a different vector type.
1969 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1971 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1972 LD->getSrcValueOffset(),
1973 LD->isVolatile(), LD->getAlignment());
1974 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1975 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1979 // Since loads produce two values, make sure to remember that we
1980 // legalized both of them.
1981 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1982 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1983 return Op.ResNo ? Tmp4 : Tmp3;
1985 MVT SrcVT = LD->getMemoryVT();
1986 unsigned SrcWidth = SrcVT.getSizeInBits();
1987 int SVOffset = LD->getSrcValueOffset();
1988 unsigned Alignment = LD->getAlignment();
1989 bool isVolatile = LD->isVolatile();
1991 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1992 // Some targets pretend to have an i1 loading operation, and actually
1993 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1994 // bits are guaranteed to be zero; it helps the optimizers understand
1995 // that these bits are zero. It is also useful for EXTLOAD, since it
1996 // tells the optimizers that those bits are undefined. It would be
1997 // nice to have an effective generic way of getting these benefits...
1998 // Until such a way is found, don't insist on promoting i1 here.
1999 (SrcVT != MVT::i1 ||
2000 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2001 // Promote to a byte-sized load if not loading an integral number of
2002 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2003 unsigned NewWidth = SrcVT.getStoreSizeInBits();
2004 MVT NVT = MVT::getIntegerVT(NewWidth);
2007 // The extra bits are guaranteed to be zero, since we stored them that
2008 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2010 ISD::LoadExtType NewExtType =
2011 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2013 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2014 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2015 NVT, isVolatile, Alignment);
2017 Ch = Result.getValue(1); // The chain.
2019 if (ExtType == ISD::SEXTLOAD)
2020 // Having the top bits zero doesn't help when sign extending.
2021 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2022 Result, DAG.getValueType(SrcVT));
2023 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2024 // All the top bits are guaranteed to be zero - inform the optimizers.
2025 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2026 DAG.getValueType(SrcVT));
2028 Tmp1 = LegalizeOp(Result);
2029 Tmp2 = LegalizeOp(Ch);
2030 } else if (SrcWidth & (SrcWidth - 1)) {
2031 // If not loading a power-of-2 number of bits, expand as two loads.
2032 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2033 "Unsupported extload!");
2034 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2035 assert(RoundWidth < SrcWidth);
2036 unsigned ExtraWidth = SrcWidth - RoundWidth;
2037 assert(ExtraWidth < RoundWidth);
2038 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2039 "Load size not an integral number of bytes!");
2040 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2041 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2042 SDOperand Lo, Hi, Ch;
2043 unsigned IncrementSize;
2045 if (TLI.isLittleEndian()) {
2046 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2047 // Load the bottom RoundWidth bits.
2048 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2049 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2052 // Load the remaining ExtraWidth bits.
2053 IncrementSize = RoundWidth / 8;
2054 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2055 DAG.getIntPtrConstant(IncrementSize));
2056 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2057 LD->getSrcValue(), SVOffset + IncrementSize,
2058 ExtraVT, isVolatile,
2059 MinAlign(Alignment, IncrementSize));
2061 // Build a factor node to remember that this load is independent of the
2063 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2066 // Move the top bits to the right place.
2067 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2068 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2070 // Join the hi and lo parts.
2071 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2073 // Big endian - avoid unaligned loads.
2074 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2075 // Load the top RoundWidth bits.
2076 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2077 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2080 // Load the remaining ExtraWidth bits.
2081 IncrementSize = RoundWidth / 8;
2082 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2083 DAG.getIntPtrConstant(IncrementSize));
2084 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2085 LD->getSrcValue(), SVOffset + IncrementSize,
2086 ExtraVT, isVolatile,
2087 MinAlign(Alignment, IncrementSize));
2089 // Build a factor node to remember that this load is independent of the
2091 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2094 // Move the top bits to the right place.
2095 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2096 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2098 // Join the hi and lo parts.
2099 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2102 Tmp1 = LegalizeOp(Result);
2103 Tmp2 = LegalizeOp(Ch);
2105 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2106 default: assert(0 && "This action is not supported yet!");
2107 case TargetLowering::Custom:
2110 case TargetLowering::Legal:
2111 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2112 Tmp1 = Result.getValue(0);
2113 Tmp2 = Result.getValue(1);
2116 Tmp3 = TLI.LowerOperation(Result, DAG);
2118 Tmp1 = LegalizeOp(Tmp3);
2119 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2122 // If this is an unaligned load and the target doesn't support it,
2124 if (!TLI.allowsUnalignedMemoryAccesses()) {
2125 unsigned ABIAlignment = TLI.getTargetData()->
2126 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2127 if (LD->getAlignment() < ABIAlignment){
2128 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
2130 Tmp1 = Result.getOperand(0);
2131 Tmp2 = Result.getOperand(1);
2132 Tmp1 = LegalizeOp(Tmp1);
2133 Tmp2 = LegalizeOp(Tmp2);
2138 case TargetLowering::Expand:
2139 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2140 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2141 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2142 LD->getSrcValueOffset(),
2143 LD->isVolatile(), LD->getAlignment());
2144 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2145 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2146 Tmp2 = LegalizeOp(Load.getValue(1));
2149 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2150 // Turn the unsupported load into an EXTLOAD followed by an explicit
2151 // zero/sign extend inreg.
2152 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2153 Tmp1, Tmp2, LD->getSrcValue(),
2154 LD->getSrcValueOffset(), SrcVT,
2155 LD->isVolatile(), LD->getAlignment());
2157 if (ExtType == ISD::SEXTLOAD)
2158 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2159 Result, DAG.getValueType(SrcVT));
2161 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2162 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2163 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2168 // Since loads produce two values, make sure to remember that we legalized
2170 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2171 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2172 return Op.ResNo ? Tmp2 : Tmp1;
2175 case ISD::EXTRACT_ELEMENT: {
2176 MVT OpTy = Node->getOperand(0).getValueType();
2177 switch (getTypeAction(OpTy)) {
2178 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2180 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2182 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2183 DAG.getConstant(OpTy.getSizeInBits()/2,
2184 TLI.getShiftAmountTy()));
2185 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2188 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2189 Node->getOperand(0));
2193 // Get both the low and high parts.
2194 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2195 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2196 Result = Tmp2; // 1 -> Hi
2198 Result = Tmp1; // 0 -> Lo
2204 case ISD::CopyToReg:
2205 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2207 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2208 "Register type must be legal!");
2209 // Legalize the incoming value (must be a legal type).
2210 Tmp2 = LegalizeOp(Node->getOperand(2));
2211 if (Node->getNumValues() == 1) {
2212 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2214 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2215 if (Node->getNumOperands() == 4) {
2216 Tmp3 = LegalizeOp(Node->getOperand(3));
2217 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2220 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2223 // Since this produces two values, make sure to remember that we legalized
2225 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2226 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2232 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2234 // Ensure that libcalls are emitted before a return.
2235 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2236 Tmp1 = LegalizeOp(Tmp1);
2237 LastCALLSEQ_END = DAG.getEntryNode();
2239 switch (Node->getNumOperands()) {
2241 Tmp2 = Node->getOperand(1);
2242 Tmp3 = Node->getOperand(2); // Signness
2243 switch (getTypeAction(Tmp2.getValueType())) {
2245 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2248 if (!Tmp2.getValueType().isVector()) {
2250 ExpandOp(Tmp2, Lo, Hi);
2252 // Big endian systems want the hi reg first.
2253 if (TLI.isBigEndian())
2257 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2259 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2260 Result = LegalizeOp(Result);
2262 SDNode *InVal = Tmp2.Val;
2263 int InIx = Tmp2.ResNo;
2264 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2265 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2267 // Figure out if there is a simple type corresponding to this Vector
2268 // type. If so, convert to the vector type.
2269 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2270 if (TLI.isTypeLegal(TVT)) {
2271 // Turn this into a return of the vector type.
2272 Tmp2 = LegalizeOp(Tmp2);
2273 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2274 } else if (NumElems == 1) {
2275 // Turn this into a return of the scalar type.
2276 Tmp2 = ScalarizeVectorOp(Tmp2);
2277 Tmp2 = LegalizeOp(Tmp2);
2278 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2280 // FIXME: Returns of gcc generic vectors smaller than a legal type
2281 // should be returned in integer registers!
2283 // The scalarized value type may not be legal, e.g. it might require
2284 // promotion or expansion. Relegalize the return.
2285 Result = LegalizeOp(Result);
2287 // FIXME: Returns of gcc generic vectors larger than a legal vector
2288 // type should be returned by reference!
2290 SplitVectorOp(Tmp2, Lo, Hi);
2291 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2292 Result = LegalizeOp(Result);
2297 Tmp2 = PromoteOp(Node->getOperand(1));
2298 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2299 Result = LegalizeOp(Result);
2304 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2306 default: { // ret <values>
2307 SmallVector<SDOperand, 8> NewValues;
2308 NewValues.push_back(Tmp1);
2309 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2310 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2312 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2313 NewValues.push_back(Node->getOperand(i+1));
2317 assert(!Node->getOperand(i).getValueType().isExtended() &&
2318 "FIXME: TODO: implement returning non-legal vector types!");
2319 ExpandOp(Node->getOperand(i), Lo, Hi);
2320 NewValues.push_back(Lo);
2321 NewValues.push_back(Node->getOperand(i+1));
2323 NewValues.push_back(Hi);
2324 NewValues.push_back(Node->getOperand(i+1));
2329 assert(0 && "Can't promote multiple return value yet!");
2332 if (NewValues.size() == Node->getNumOperands())
2333 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2335 Result = DAG.getNode(ISD::RET, MVT::Other,
2336 &NewValues[0], NewValues.size());
2341 if (Result.getOpcode() == ISD::RET) {
2342 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2343 default: assert(0 && "This action is not supported yet!");
2344 case TargetLowering::Legal: break;
2345 case TargetLowering::Custom:
2346 Tmp1 = TLI.LowerOperation(Result, DAG);
2347 if (Tmp1.Val) Result = Tmp1;
2353 StoreSDNode *ST = cast<StoreSDNode>(Node);
2354 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2355 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2356 int SVOffset = ST->getSrcValueOffset();
2357 unsigned Alignment = ST->getAlignment();
2358 bool isVolatile = ST->isVolatile();
2360 if (!ST->isTruncatingStore()) {
2361 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2362 // FIXME: We shouldn't do this for TargetConstantFP's.
2363 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2364 // to phase ordering between legalized code and the dag combiner. This
2365 // probably means that we need to integrate dag combiner and legalizer
2367 // We generally can't do this one for long doubles.
2368 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2369 if (CFP->getValueType(0) == MVT::f32 &&
2370 getTypeAction(MVT::i32) == Legal) {
2371 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2372 convertToAPInt().zextOrTrunc(32),
2374 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2375 SVOffset, isVolatile, Alignment);
2377 } else if (CFP->getValueType(0) == MVT::f64) {
2378 // If this target supports 64-bit registers, do a single 64-bit store.
2379 if (getTypeAction(MVT::i64) == Legal) {
2380 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2381 zextOrTrunc(64), MVT::i64);
2382 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2383 SVOffset, isVolatile, Alignment);
2385 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2386 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2387 // stores. If the target supports neither 32- nor 64-bits, this
2388 // xform is certainly not worth it.
2389 const APInt &IntVal =CFP->getValueAPF().convertToAPInt();
2390 SDOperand Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2391 SDOperand Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2392 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2394 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2395 SVOffset, isVolatile, Alignment);
2396 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2397 DAG.getIntPtrConstant(4));
2398 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2399 isVolatile, MinAlign(Alignment, 4U));
2401 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2407 switch (getTypeAction(ST->getMemoryVT())) {
2409 Tmp3 = LegalizeOp(ST->getValue());
2410 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2413 MVT VT = Tmp3.getValueType();
2414 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2415 default: assert(0 && "This action is not supported yet!");
2416 case TargetLowering::Legal:
2417 // If this is an unaligned store and the target doesn't support it,
2419 if (!TLI.allowsUnalignedMemoryAccesses()) {
2420 unsigned ABIAlignment = TLI.getTargetData()->
2421 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2422 if (ST->getAlignment() < ABIAlignment)
2423 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2427 case TargetLowering::Custom:
2428 Tmp1 = TLI.LowerOperation(Result, DAG);
2429 if (Tmp1.Val) Result = Tmp1;
2431 case TargetLowering::Promote:
2432 assert(VT.isVector() && "Unknown legal promote case!");
2433 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2434 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2435 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2436 ST->getSrcValue(), SVOffset, isVolatile,
2443 // Truncate the value and store the result.
2444 Tmp3 = PromoteOp(ST->getValue());
2445 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2446 SVOffset, ST->getMemoryVT(),
2447 isVolatile, Alignment);
2451 unsigned IncrementSize = 0;
2454 // If this is a vector type, then we have to calculate the increment as
2455 // the product of the element size in bytes, and the number of elements
2456 // in the high half of the vector.
2457 if (ST->getValue().getValueType().isVector()) {
2458 SDNode *InVal = ST->getValue().Val;
2459 int InIx = ST->getValue().ResNo;
2460 MVT InVT = InVal->getValueType(InIx);
2461 unsigned NumElems = InVT.getVectorNumElements();
2462 MVT EVT = InVT.getVectorElementType();
2464 // Figure out if there is a simple type corresponding to this Vector
2465 // type. If so, convert to the vector type.
2466 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2467 if (TLI.isTypeLegal(TVT)) {
2468 // Turn this into a normal store of the vector type.
2469 Tmp3 = LegalizeOp(ST->getValue());
2470 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2471 SVOffset, isVolatile, Alignment);
2472 Result = LegalizeOp(Result);
2474 } else if (NumElems == 1) {
2475 // Turn this into a normal store of the scalar type.
2476 Tmp3 = ScalarizeVectorOp(ST->getValue());
2477 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2478 SVOffset, isVolatile, Alignment);
2479 // The scalarized value type may not be legal, e.g. it might require
2480 // promotion or expansion. Relegalize the scalar store.
2481 Result = LegalizeOp(Result);
2484 SplitVectorOp(ST->getValue(), Lo, Hi);
2485 IncrementSize = Lo.Val->getValueType(0).getVectorNumElements() *
2486 EVT.getSizeInBits()/8;
2489 ExpandOp(ST->getValue(), Lo, Hi);
2490 IncrementSize = Hi.Val ? Hi.getValueType().getSizeInBits()/8 : 0;
2492 if (TLI.isBigEndian())
2496 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2497 SVOffset, isVolatile, Alignment);
2499 if (Hi.Val == NULL) {
2500 // Must be int <-> float one-to-one expansion.
2505 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2506 DAG.getIntPtrConstant(IncrementSize));
2507 assert(isTypeLegal(Tmp2.getValueType()) &&
2508 "Pointers must be legal!");
2509 SVOffset += IncrementSize;
2510 Alignment = MinAlign(Alignment, IncrementSize);
2511 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2512 SVOffset, isVolatile, Alignment);
2513 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2517 switch (getTypeAction(ST->getValue().getValueType())) {
2519 Tmp3 = LegalizeOp(ST->getValue());
2522 // We can promote the value, the truncstore will still take care of it.
2523 Tmp3 = PromoteOp(ST->getValue());
2526 // Just store the low part. This may become a non-trunc store, so make
2527 // sure to use getTruncStore, not UpdateNodeOperands below.
2528 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2529 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2530 SVOffset, MVT::i8, isVolatile, Alignment);
2533 MVT StVT = ST->getMemoryVT();
2534 unsigned StWidth = StVT.getSizeInBits();
2536 if (StWidth != StVT.getStoreSizeInBits()) {
2537 // Promote to a byte-sized store with upper bits zero if not
2538 // storing an integral number of bytes. For example, promote
2539 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2540 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2541 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2542 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2543 SVOffset, NVT, isVolatile, Alignment);
2544 } else if (StWidth & (StWidth - 1)) {
2545 // If not storing a power-of-2 number of bits, expand as two stores.
2546 assert(StVT.isExtended() && !StVT.isVector() &&
2547 "Unsupported truncstore!");
2548 unsigned RoundWidth = 1 << Log2_32(StWidth);
2549 assert(RoundWidth < StWidth);
2550 unsigned ExtraWidth = StWidth - RoundWidth;
2551 assert(ExtraWidth < RoundWidth);
2552 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2553 "Store size not an integral number of bytes!");
2554 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2555 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2557 unsigned IncrementSize;
2559 if (TLI.isLittleEndian()) {
2560 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2561 // Store the bottom RoundWidth bits.
2562 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2564 isVolatile, Alignment);
2566 // Store the remaining ExtraWidth bits.
2567 IncrementSize = RoundWidth / 8;
2568 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2569 DAG.getIntPtrConstant(IncrementSize));
2570 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2571 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2572 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2573 SVOffset + IncrementSize, ExtraVT, isVolatile,
2574 MinAlign(Alignment, IncrementSize));
2576 // Big endian - avoid unaligned stores.
2577 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2578 // Store the top RoundWidth bits.
2579 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2580 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2581 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2582 RoundVT, isVolatile, Alignment);
2584 // Store the remaining ExtraWidth bits.
2585 IncrementSize = RoundWidth / 8;
2586 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2587 DAG.getIntPtrConstant(IncrementSize));
2588 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2589 SVOffset + IncrementSize, ExtraVT, isVolatile,
2590 MinAlign(Alignment, IncrementSize));
2593 // The order of the stores doesn't matter.
2594 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2596 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2597 Tmp2 != ST->getBasePtr())
2598 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2601 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2602 default: assert(0 && "This action is not supported yet!");
2603 case TargetLowering::Legal:
2604 // If this is an unaligned store and the target doesn't support it,
2606 if (!TLI.allowsUnalignedMemoryAccesses()) {
2607 unsigned ABIAlignment = TLI.getTargetData()->
2608 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2609 if (ST->getAlignment() < ABIAlignment)
2610 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2614 case TargetLowering::Custom:
2615 Result = TLI.LowerOperation(Result, DAG);
2618 // TRUNCSTORE:i16 i32 -> STORE i16
2619 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2620 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2621 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2622 isVolatile, Alignment);
2630 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2631 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2633 case ISD::STACKSAVE:
2634 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2635 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2636 Tmp1 = Result.getValue(0);
2637 Tmp2 = Result.getValue(1);
2639 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2640 default: assert(0 && "This action is not supported yet!");
2641 case TargetLowering::Legal: break;
2642 case TargetLowering::Custom:
2643 Tmp3 = TLI.LowerOperation(Result, DAG);
2645 Tmp1 = LegalizeOp(Tmp3);
2646 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2649 case TargetLowering::Expand:
2650 // Expand to CopyFromReg if the target set
2651 // StackPointerRegisterToSaveRestore.
2652 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2653 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2654 Node->getValueType(0));
2655 Tmp2 = Tmp1.getValue(1);
2657 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2658 Tmp2 = Node->getOperand(0);
2663 // Since stacksave produce two values, make sure to remember that we
2664 // legalized both of them.
2665 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2666 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2667 return Op.ResNo ? Tmp2 : Tmp1;
2669 case ISD::STACKRESTORE:
2670 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2671 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2672 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2674 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2675 default: assert(0 && "This action is not supported yet!");
2676 case TargetLowering::Legal: break;
2677 case TargetLowering::Custom:
2678 Tmp1 = TLI.LowerOperation(Result, DAG);
2679 if (Tmp1.Val) Result = Tmp1;
2681 case TargetLowering::Expand:
2682 // Expand to CopyToReg if the target set
2683 // StackPointerRegisterToSaveRestore.
2684 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2685 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2693 case ISD::READCYCLECOUNTER:
2694 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2695 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2696 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2697 Node->getValueType(0))) {
2698 default: assert(0 && "This action is not supported yet!");
2699 case TargetLowering::Legal:
2700 Tmp1 = Result.getValue(0);
2701 Tmp2 = Result.getValue(1);
2703 case TargetLowering::Custom:
2704 Result = TLI.LowerOperation(Result, DAG);
2705 Tmp1 = LegalizeOp(Result.getValue(0));
2706 Tmp2 = LegalizeOp(Result.getValue(1));
2710 // Since rdcc produce two values, make sure to remember that we legalized
2712 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2713 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2717 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2718 case Expand: assert(0 && "It's impossible to expand bools");
2720 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2723 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2724 // Make sure the condition is either zero or one.
2725 unsigned BitWidth = Tmp1.getValueSizeInBits();
2726 if (!DAG.MaskedValueIsZero(Tmp1,
2727 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2728 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2732 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2733 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2735 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2737 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2738 default: assert(0 && "This action is not supported yet!");
2739 case TargetLowering::Legal: break;
2740 case TargetLowering::Custom: {
2741 Tmp1 = TLI.LowerOperation(Result, DAG);
2742 if (Tmp1.Val) Result = Tmp1;
2745 case TargetLowering::Expand:
2746 if (Tmp1.getOpcode() == ISD::SETCC) {
2747 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2749 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2751 Result = DAG.getSelectCC(Tmp1,
2752 DAG.getConstant(0, Tmp1.getValueType()),
2753 Tmp2, Tmp3, ISD::SETNE);
2756 case TargetLowering::Promote: {
2758 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2759 unsigned ExtOp, TruncOp;
2760 if (Tmp2.getValueType().isVector()) {
2761 ExtOp = ISD::BIT_CONVERT;
2762 TruncOp = ISD::BIT_CONVERT;
2763 } else if (Tmp2.getValueType().isInteger()) {
2764 ExtOp = ISD::ANY_EXTEND;
2765 TruncOp = ISD::TRUNCATE;
2767 ExtOp = ISD::FP_EXTEND;
2768 TruncOp = ISD::FP_ROUND;
2770 // Promote each of the values to the new type.
2771 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2772 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2773 // Perform the larger operation, then round down.
2774 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2775 if (TruncOp != ISD::FP_ROUND)
2776 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2778 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2779 DAG.getIntPtrConstant(0));
2784 case ISD::SELECT_CC: {
2785 Tmp1 = Node->getOperand(0); // LHS
2786 Tmp2 = Node->getOperand(1); // RHS
2787 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2788 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2789 SDOperand CC = Node->getOperand(4);
2791 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2793 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2794 // the LHS is a legal SETCC itself. In this case, we need to compare
2795 // the result against zero to select between true and false values.
2796 if (Tmp2.Val == 0) {
2797 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2798 CC = DAG.getCondCode(ISD::SETNE);
2800 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2802 // Everything is legal, see if we should expand this op or something.
2803 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2804 default: assert(0 && "This action is not supported yet!");
2805 case TargetLowering::Legal: break;
2806 case TargetLowering::Custom:
2807 Tmp1 = TLI.LowerOperation(Result, DAG);
2808 if (Tmp1.Val) Result = Tmp1;
2814 Tmp1 = Node->getOperand(0);
2815 Tmp2 = Node->getOperand(1);
2816 Tmp3 = Node->getOperand(2);
2817 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2819 // If we had to Expand the SetCC operands into a SELECT node, then it may
2820 // not always be possible to return a true LHS & RHS. In this case, just
2821 // return the value we legalized, returned in the LHS
2822 if (Tmp2.Val == 0) {
2827 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2828 default: assert(0 && "Cannot handle this action for SETCC yet!");
2829 case TargetLowering::Custom:
2832 case TargetLowering::Legal:
2833 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2835 Tmp4 = TLI.LowerOperation(Result, DAG);
2836 if (Tmp4.Val) Result = Tmp4;
2839 case TargetLowering::Promote: {
2840 // First step, figure out the appropriate operation to use.
2841 // Allow SETCC to not be supported for all legal data types
2842 // Mostly this targets FP
2843 MVT NewInTy = Node->getOperand(0).getValueType();
2844 MVT OldVT = NewInTy; OldVT = OldVT;
2846 // Scan for the appropriate larger type to use.
2848 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
2850 assert(NewInTy.isInteger() == OldVT.isInteger() &&
2851 "Fell off of the edge of the integer world");
2852 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
2853 "Fell off of the edge of the floating point world");
2855 // If the target supports SETCC of this type, use it.
2856 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2859 if (NewInTy.isInteger())
2860 assert(0 && "Cannot promote Legal Integer SETCC yet");
2862 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2863 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2865 Tmp1 = LegalizeOp(Tmp1);
2866 Tmp2 = LegalizeOp(Tmp2);
2867 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2868 Result = LegalizeOp(Result);
2871 case TargetLowering::Expand:
2872 // Expand a setcc node into a select_cc of the same condition, lhs, and
2873 // rhs that selects between const 1 (true) and const 0 (false).
2874 MVT VT = Node->getValueType(0);
2875 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2876 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2882 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2883 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2884 SDOperand CC = Node->getOperand(2);
2886 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
2888 // Everything is legal, see if we should expand this op or something.
2889 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
2890 default: assert(0 && "This action is not supported yet!");
2891 case TargetLowering::Legal: break;
2892 case TargetLowering::Custom:
2893 Tmp1 = TLI.LowerOperation(Result, DAG);
2894 if (Tmp1.Val) Result = Tmp1;
2900 case ISD::SHL_PARTS:
2901 case ISD::SRA_PARTS:
2902 case ISD::SRL_PARTS: {
2903 SmallVector<SDOperand, 8> Ops;
2904 bool Changed = false;
2905 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2906 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2907 Changed |= Ops.back() != Node->getOperand(i);
2910 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2912 switch (TLI.getOperationAction(Node->getOpcode(),
2913 Node->getValueType(0))) {
2914 default: assert(0 && "This action is not supported yet!");
2915 case TargetLowering::Legal: break;
2916 case TargetLowering::Custom:
2917 Tmp1 = TLI.LowerOperation(Result, DAG);
2919 SDOperand Tmp2, RetVal(0, 0);
2920 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2921 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2922 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2926 assert(RetVal.Val && "Illegal result number");
2932 // Since these produce multiple values, make sure to remember that we
2933 // legalized all of them.
2934 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2935 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2936 return Result.getValue(Op.ResNo);
2958 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2959 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2960 case Expand: assert(0 && "Not possible");
2962 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2965 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2969 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2971 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2972 default: assert(0 && "BinOp legalize operation not supported");
2973 case TargetLowering::Legal: break;
2974 case TargetLowering::Custom:
2975 Tmp1 = TLI.LowerOperation(Result, DAG);
2976 if (Tmp1.Val) Result = Tmp1;
2978 case TargetLowering::Expand: {
2979 MVT VT = Op.getValueType();
2981 // See if multiply or divide can be lowered using two-result operations.
2982 SDVTList VTs = DAG.getVTList(VT, VT);
2983 if (Node->getOpcode() == ISD::MUL) {
2984 // We just need the low half of the multiply; try both the signed
2985 // and unsigned forms. If the target supports both SMUL_LOHI and
2986 // UMUL_LOHI, form a preference by checking which forms of plain
2987 // MULH it supports.
2988 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2989 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2990 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2991 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2992 unsigned OpToUse = 0;
2993 if (HasSMUL_LOHI && !HasMULHS) {
2994 OpToUse = ISD::SMUL_LOHI;
2995 } else if (HasUMUL_LOHI && !HasMULHU) {
2996 OpToUse = ISD::UMUL_LOHI;
2997 } else if (HasSMUL_LOHI) {
2998 OpToUse = ISD::SMUL_LOHI;
2999 } else if (HasUMUL_LOHI) {
3000 OpToUse = ISD::UMUL_LOHI;
3003 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
3007 if (Node->getOpcode() == ISD::MULHS &&
3008 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3009 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3012 if (Node->getOpcode() == ISD::MULHU &&
3013 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3014 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3017 if (Node->getOpcode() == ISD::SDIV &&
3018 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3019 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3022 if (Node->getOpcode() == ISD::UDIV &&
3023 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3024 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3028 // Check to see if we have a libcall for this operator.
3029 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3030 bool isSigned = false;
3031 switch (Node->getOpcode()) {
3034 if (VT == MVT::i32) {
3035 LC = Node->getOpcode() == ISD::UDIV
3036 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3037 isSigned = Node->getOpcode() == ISD::SDIV;
3041 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3042 RTLIB::POW_PPCF128);
3046 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3048 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3052 assert(Node->getValueType(0).isVector() &&
3053 "Cannot expand this binary operator!");
3054 // Expand the operation into a bunch of nasty scalar code.
3055 Result = LegalizeOp(UnrollVectorOp(Op));
3058 case TargetLowering::Promote: {
3059 switch (Node->getOpcode()) {
3060 default: assert(0 && "Do not know how to promote this BinOp!");
3064 MVT OVT = Node->getValueType(0);
3065 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3066 assert(OVT.isVector() && "Cannot promote this BinOp!");
3067 // Bit convert each of the values to the new type.
3068 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3069 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3070 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3071 // Bit convert the result back the original type.
3072 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3080 case ISD::SMUL_LOHI:
3081 case ISD::UMUL_LOHI:
3084 // These nodes will only be produced by target-specific lowering, so
3085 // they shouldn't be here if they aren't legal.
3086 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3087 "This must be legal!");
3089 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3090 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3091 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3094 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3095 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3096 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3097 case Expand: assert(0 && "Not possible");
3099 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3102 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3106 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3108 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3109 default: assert(0 && "Operation not supported");
3110 case TargetLowering::Custom:
3111 Tmp1 = TLI.LowerOperation(Result, DAG);
3112 if (Tmp1.Val) Result = Tmp1;
3114 case TargetLowering::Legal: break;
3115 case TargetLowering::Expand: {
3116 // If this target supports fabs/fneg natively and select is cheap,
3117 // do this efficiently.
3118 if (!TLI.isSelectExpensive() &&
3119 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3120 TargetLowering::Legal &&
3121 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3122 TargetLowering::Legal) {
3123 // Get the sign bit of the RHS.
3125 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3126 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3127 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3128 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3129 // Get the absolute value of the result.
3130 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3131 // Select between the nabs and abs value based on the sign bit of
3133 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3134 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3137 Result = LegalizeOp(Result);
3141 // Otherwise, do bitwise ops!
3143 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3144 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3145 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3146 Result = LegalizeOp(Result);
3154 Tmp1 = LegalizeOp(Node->getOperand(0));
3155 Tmp2 = LegalizeOp(Node->getOperand(1));
3156 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3157 // Since this produces two values, make sure to remember that we legalized
3159 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3160 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3165 Tmp1 = LegalizeOp(Node->getOperand(0));
3166 Tmp2 = LegalizeOp(Node->getOperand(1));
3167 Tmp3 = LegalizeOp(Node->getOperand(2));
3168 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3169 // Since this produces two values, make sure to remember that we legalized
3171 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3172 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3175 case ISD::BUILD_PAIR: {
3176 MVT PairTy = Node->getValueType(0);
3177 // TODO: handle the case where the Lo and Hi operands are not of legal type
3178 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3179 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3180 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3181 case TargetLowering::Promote:
3182 case TargetLowering::Custom:
3183 assert(0 && "Cannot promote/custom this yet!");
3184 case TargetLowering::Legal:
3185 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3186 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3188 case TargetLowering::Expand:
3189 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3190 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3191 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3192 DAG.getConstant(PairTy.getSizeInBits()/2,
3193 TLI.getShiftAmountTy()));
3194 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3203 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3204 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3206 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3207 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3208 case TargetLowering::Custom:
3211 case TargetLowering::Legal:
3212 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3214 Tmp1 = TLI.LowerOperation(Result, DAG);
3215 if (Tmp1.Val) Result = Tmp1;
3218 case TargetLowering::Expand: {
3219 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3220 bool isSigned = DivOpc == ISD::SDIV;
3221 MVT VT = Node->getValueType(0);
3223 // See if remainder can be lowered using two-result operations.
3224 SDVTList VTs = DAG.getVTList(VT, VT);
3225 if (Node->getOpcode() == ISD::SREM &&
3226 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3227 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3230 if (Node->getOpcode() == ISD::UREM &&
3231 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3232 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3236 if (VT.isInteger()) {
3237 if (TLI.getOperationAction(DivOpc, VT) ==
3238 TargetLowering::Legal) {
3240 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3241 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3242 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3243 } else if (VT.isVector()) {
3244 Result = LegalizeOp(UnrollVectorOp(Op));
3246 assert(VT == MVT::i32 &&
3247 "Cannot expand this binary operator!");
3248 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3249 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3251 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3254 assert(VT.isFloatingPoint() &&
3255 "remainder op must have integer or floating-point type");
3256 if (VT.isVector()) {
3257 Result = LegalizeOp(UnrollVectorOp(Op));
3259 // Floating point mod -> fmod libcall.
3260 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3261 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3263 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3271 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3272 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3274 MVT VT = Node->getValueType(0);
3275 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3276 default: assert(0 && "This action is not supported yet!");
3277 case TargetLowering::Custom:
3280 case TargetLowering::Legal:
3281 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3282 Result = Result.getValue(0);
3283 Tmp1 = Result.getValue(1);
3286 Tmp2 = TLI.LowerOperation(Result, DAG);
3288 Result = LegalizeOp(Tmp2);
3289 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3293 case TargetLowering::Expand: {
3294 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3295 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3296 // Increment the pointer, VAList, to the next vaarg
3297 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3298 DAG.getConstant(VT.getSizeInBits()/8,
3299 TLI.getPointerTy()));
3300 // Store the incremented VAList to the legalized pointer
3301 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3302 // Load the actual argument out of the pointer VAList
3303 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3304 Tmp1 = LegalizeOp(Result.getValue(1));
3305 Result = LegalizeOp(Result);
3309 // Since VAARG produces two values, make sure to remember that we
3310 // legalized both of them.
3311 AddLegalizedOperand(SDOperand(Node, 0), Result);
3312 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3313 return Op.ResNo ? Tmp1 : Result;
3317 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3318 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3319 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3321 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3322 default: assert(0 && "This action is not supported yet!");
3323 case TargetLowering::Custom:
3326 case TargetLowering::Legal:
3327 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3328 Node->getOperand(3), Node->getOperand(4));
3330 Tmp1 = TLI.LowerOperation(Result, DAG);
3331 if (Tmp1.Val) Result = Tmp1;
3334 case TargetLowering::Expand:
3335 // This defaults to loading a pointer from the input and storing it to the
3336 // output, returning the chain.
3337 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3338 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3339 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3340 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3346 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3347 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3349 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3350 default: assert(0 && "This action is not supported yet!");
3351 case TargetLowering::Custom:
3354 case TargetLowering::Legal:
3355 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3357 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3358 if (Tmp1.Val) Result = Tmp1;
3361 case TargetLowering::Expand:
3362 Result = Tmp1; // Default to a no-op, return the chain
3368 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3369 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3371 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3373 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3374 default: assert(0 && "This action is not supported yet!");
3375 case TargetLowering::Legal: break;
3376 case TargetLowering::Custom:
3377 Tmp1 = TLI.LowerOperation(Result, DAG);
3378 if (Tmp1.Val) Result = Tmp1;
3385 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3386 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3387 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3388 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3390 assert(0 && "ROTL/ROTR legalize operation not supported");
3392 case TargetLowering::Legal:
3394 case TargetLowering::Custom:
3395 Tmp1 = TLI.LowerOperation(Result, DAG);
3396 if (Tmp1.Val) Result = Tmp1;
3398 case TargetLowering::Promote:
3399 assert(0 && "Do not know how to promote ROTL/ROTR");
3401 case TargetLowering::Expand:
3402 assert(0 && "Do not know how to expand ROTL/ROTR");
3408 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3409 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3410 case TargetLowering::Custom:
3411 assert(0 && "Cannot custom legalize this yet!");
3412 case TargetLowering::Legal:
3413 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3415 case TargetLowering::Promote: {
3416 MVT OVT = Tmp1.getValueType();
3417 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3418 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3420 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3421 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3422 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3423 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3426 case TargetLowering::Expand:
3427 Result = ExpandBSWAP(Tmp1);
3435 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3436 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3437 case TargetLowering::Custom:
3438 case TargetLowering::Legal:
3439 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3440 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3441 TargetLowering::Custom) {
3442 Tmp1 = TLI.LowerOperation(Result, DAG);
3448 case TargetLowering::Promote: {
3449 MVT OVT = Tmp1.getValueType();
3450 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3452 // Zero extend the argument.
3453 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3454 // Perform the larger operation, then subtract if needed.
3455 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3456 switch (Node->getOpcode()) {
3461 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3462 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3463 DAG.getConstant(NVT.getSizeInBits(), NVT),
3465 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3466 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3469 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3470 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3471 DAG.getConstant(NVT.getSizeInBits() -
3472 OVT.getSizeInBits(), NVT));
3477 case TargetLowering::Expand:
3478 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3489 Tmp1 = LegalizeOp(Node->getOperand(0));
3490 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3491 case TargetLowering::Promote:
3492 case TargetLowering::Custom:
3495 case TargetLowering::Legal:
3496 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3498 Tmp1 = TLI.LowerOperation(Result, DAG);
3499 if (Tmp1.Val) Result = Tmp1;
3502 case TargetLowering::Expand:
3503 switch (Node->getOpcode()) {
3504 default: assert(0 && "Unreachable!");
3506 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3507 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3508 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3511 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3512 MVT VT = Node->getValueType(0);
3513 Tmp2 = DAG.getConstantFP(0.0, VT);
3514 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3516 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3517 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3523 MVT VT = Node->getValueType(0);
3525 // Expand unsupported unary vector operators by unrolling them.
3526 if (VT.isVector()) {
3527 Result = LegalizeOp(UnrollVectorOp(Op));
3531 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3532 switch(Node->getOpcode()) {
3534 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3535 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3538 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3539 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3542 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3543 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3545 default: assert(0 && "Unreachable!");
3548 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3556 MVT VT = Node->getValueType(0);
3558 // Expand unsupported unary vector operators by unrolling them.
3559 if (VT.isVector()) {
3560 Result = LegalizeOp(UnrollVectorOp(Op));
3564 // We always lower FPOWI into a libcall. No target support for it yet.
3565 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3566 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3568 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3571 case ISD::BIT_CONVERT:
3572 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3573 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3574 Node->getValueType(0));
3575 } else if (Op.getOperand(0).getValueType().isVector()) {
3576 // The input has to be a vector type, we have to either scalarize it, pack
3577 // it, or convert it based on whether the input vector type is legal.
3578 SDNode *InVal = Node->getOperand(0).Val;
3579 int InIx = Node->getOperand(0).ResNo;
3580 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3581 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3583 // Figure out if there is a simple type corresponding to this Vector
3584 // type. If so, convert to the vector type.
3585 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3586 if (TLI.isTypeLegal(TVT)) {
3587 // Turn this into a bit convert of the vector input.
3588 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3589 LegalizeOp(Node->getOperand(0)));
3591 } else if (NumElems == 1) {
3592 // Turn this into a bit convert of the scalar input.
3593 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3594 ScalarizeVectorOp(Node->getOperand(0)));
3597 // FIXME: UNIMP! Store then reload
3598 assert(0 && "Cast from unsupported vector type not implemented yet!");
3601 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3602 Node->getOperand(0).getValueType())) {
3603 default: assert(0 && "Unknown operation action!");
3604 case TargetLowering::Expand:
3605 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3606 Node->getValueType(0));
3608 case TargetLowering::Legal:
3609 Tmp1 = LegalizeOp(Node->getOperand(0));
3610 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3616 // Conversion operators. The source and destination have different types.
3617 case ISD::SINT_TO_FP:
3618 case ISD::UINT_TO_FP: {
3619 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3620 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3622 switch (TLI.getOperationAction(Node->getOpcode(),
3623 Node->getOperand(0).getValueType())) {
3624 default: assert(0 && "Unknown operation action!");
3625 case TargetLowering::Custom:
3628 case TargetLowering::Legal:
3629 Tmp1 = LegalizeOp(Node->getOperand(0));
3630 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3632 Tmp1 = TLI.LowerOperation(Result, DAG);
3633 if (Tmp1.Val) Result = Tmp1;
3636 case TargetLowering::Expand:
3637 Result = ExpandLegalINT_TO_FP(isSigned,
3638 LegalizeOp(Node->getOperand(0)),
3639 Node->getValueType(0));
3641 case TargetLowering::Promote:
3642 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3643 Node->getValueType(0),
3649 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3650 Node->getValueType(0), Node->getOperand(0));
3653 Tmp1 = PromoteOp(Node->getOperand(0));
3655 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3656 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3658 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3659 Node->getOperand(0).getValueType());
3661 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3662 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3668 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3670 Tmp1 = LegalizeOp(Node->getOperand(0));
3671 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3674 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3676 // Since the result is legal, we should just be able to truncate the low
3677 // part of the source.
3678 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3681 Result = PromoteOp(Node->getOperand(0));
3682 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3687 case ISD::FP_TO_SINT:
3688 case ISD::FP_TO_UINT:
3689 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3691 Tmp1 = LegalizeOp(Node->getOperand(0));
3693 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3694 default: assert(0 && "Unknown operation action!");
3695 case TargetLowering::Custom:
3698 case TargetLowering::Legal:
3699 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3701 Tmp1 = TLI.LowerOperation(Result, DAG);
3702 if (Tmp1.Val) Result = Tmp1;
3705 case TargetLowering::Promote:
3706 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3707 Node->getOpcode() == ISD::FP_TO_SINT);
3709 case TargetLowering::Expand:
3710 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3711 SDOperand True, False;
3712 MVT VT = Node->getOperand(0).getValueType();
3713 MVT NVT = Node->getValueType(0);
3714 const uint64_t zero[] = {0, 0};
3715 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
3716 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3717 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3718 Tmp2 = DAG.getConstantFP(apf, VT);
3719 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
3720 Node->getOperand(0), Tmp2, ISD::SETLT);
3721 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3722 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3723 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3725 False = DAG.getNode(ISD::XOR, NVT, False,
3726 DAG.getConstant(x, NVT));
3727 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3730 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3736 MVT VT = Op.getValueType();
3737 MVT OVT = Node->getOperand(0).getValueType();
3738 // Convert ppcf128 to i32
3739 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3740 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3741 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3742 Node->getOperand(0), DAG.getValueType(MVT::f64));
3743 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3744 DAG.getIntPtrConstant(1));
3745 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3747 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3748 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3749 Tmp2 = DAG.getConstantFP(apf, OVT);
3750 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3751 // FIXME: generated code sucks.
3752 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3753 DAG.getNode(ISD::ADD, MVT::i32,
3754 DAG.getNode(ISD::FP_TO_SINT, VT,
3755 DAG.getNode(ISD::FSUB, OVT,
3756 Node->getOperand(0), Tmp2)),
3757 DAG.getConstant(0x80000000, MVT::i32)),
3758 DAG.getNode(ISD::FP_TO_SINT, VT,
3759 Node->getOperand(0)),
3760 DAG.getCondCode(ISD::SETGE));
3764 // Convert f32 / f64 to i32 / i64 / i128.
3765 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3766 switch (Node->getOpcode()) {
3767 case ISD::FP_TO_SINT: {
3768 if (VT == MVT::i32) {
3769 if (OVT == MVT::f32)
3770 LC = RTLIB::FPTOSINT_F32_I32;
3771 else if (OVT == MVT::f64)
3772 LC = RTLIB::FPTOSINT_F64_I32;
3774 assert(0 && "Unexpected i32-to-fp conversion!");
3775 } else if (VT == MVT::i64) {
3776 if (OVT == MVT::f32)
3777 LC = RTLIB::FPTOSINT_F32_I64;
3778 else if (OVT == MVT::f64)
3779 LC = RTLIB::FPTOSINT_F64_I64;
3780 else if (OVT == MVT::f80)
3781 LC = RTLIB::FPTOSINT_F80_I64;
3782 else if (OVT == MVT::ppcf128)
3783 LC = RTLIB::FPTOSINT_PPCF128_I64;
3785 assert(0 && "Unexpected i64-to-fp conversion!");
3786 } else if (VT == MVT::i128) {
3787 if (OVT == MVT::f32)
3788 LC = RTLIB::FPTOSINT_F32_I128;
3789 else if (OVT == MVT::f64)
3790 LC = RTLIB::FPTOSINT_F64_I128;
3791 else if (OVT == MVT::f80)
3792 LC = RTLIB::FPTOSINT_F80_I128;
3793 else if (OVT == MVT::ppcf128)
3794 LC = RTLIB::FPTOSINT_PPCF128_I128;
3796 assert(0 && "Unexpected i128-to-fp conversion!");
3798 assert(0 && "Unexpectd int-to-fp conversion!");
3802 case ISD::FP_TO_UINT: {
3803 if (VT == MVT::i32) {
3804 if (OVT == MVT::f32)
3805 LC = RTLIB::FPTOUINT_F32_I32;
3806 else if (OVT == MVT::f64)
3807 LC = RTLIB::FPTOUINT_F64_I32;
3808 else if (OVT == MVT::f80)
3809 LC = RTLIB::FPTOUINT_F80_I32;
3811 assert(0 && "Unexpected i32-to-fp conversion!");
3812 } else if (VT == MVT::i64) {
3813 if (OVT == MVT::f32)
3814 LC = RTLIB::FPTOUINT_F32_I64;
3815 else if (OVT == MVT::f64)
3816 LC = RTLIB::FPTOUINT_F64_I64;
3817 else if (OVT == MVT::f80)
3818 LC = RTLIB::FPTOUINT_F80_I64;
3819 else if (OVT == MVT::ppcf128)
3820 LC = RTLIB::FPTOUINT_PPCF128_I64;
3822 assert(0 && "Unexpected i64-to-fp conversion!");
3823 } else if (VT == MVT::i128) {
3824 if (OVT == MVT::f32)
3825 LC = RTLIB::FPTOUINT_F32_I128;
3826 else if (OVT == MVT::f64)
3827 LC = RTLIB::FPTOUINT_F64_I128;
3828 else if (OVT == MVT::f80)
3829 LC = RTLIB::FPTOUINT_F80_I128;
3830 else if (OVT == MVT::ppcf128)
3831 LC = RTLIB::FPTOUINT_PPCF128_I128;
3833 assert(0 && "Unexpected i128-to-fp conversion!");
3835 assert(0 && "Unexpectd int-to-fp conversion!");
3839 default: assert(0 && "Unreachable!");
3842 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3846 Tmp1 = PromoteOp(Node->getOperand(0));
3847 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3848 Result = LegalizeOp(Result);
3853 case ISD::FP_EXTEND: {
3854 MVT DstVT = Op.getValueType();
3855 MVT SrcVT = Op.getOperand(0).getValueType();
3856 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3857 // The only other way we can lower this is to turn it into a STORE,
3858 // LOAD pair, targetting a temporary location (a stack slot).
3859 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3862 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3863 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3865 Tmp1 = LegalizeOp(Node->getOperand(0));
3866 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3869 Tmp1 = PromoteOp(Node->getOperand(0));
3870 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3875 case ISD::FP_ROUND: {
3876 MVT DstVT = Op.getValueType();
3877 MVT SrcVT = Op.getOperand(0).getValueType();
3878 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3879 if (SrcVT == MVT::ppcf128) {
3881 ExpandOp(Node->getOperand(0), Lo, Result);
3882 // Round it the rest of the way (e.g. to f32) if needed.
3883 if (DstVT!=MVT::f64)
3884 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3887 // The only other way we can lower this is to turn it into a STORE,
3888 // LOAD pair, targetting a temporary location (a stack slot).
3889 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3892 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3893 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3895 Tmp1 = LegalizeOp(Node->getOperand(0));
3896 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3899 Tmp1 = PromoteOp(Node->getOperand(0));
3900 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3901 Node->getOperand(1));
3906 case ISD::ANY_EXTEND:
3907 case ISD::ZERO_EXTEND:
3908 case ISD::SIGN_EXTEND:
3909 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3910 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3912 Tmp1 = LegalizeOp(Node->getOperand(0));
3913 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3914 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3915 TargetLowering::Custom) {
3916 Tmp1 = TLI.LowerOperation(Result, DAG);
3917 if (Tmp1.Val) Result = Tmp1;
3921 switch (Node->getOpcode()) {
3922 case ISD::ANY_EXTEND:
3923 Tmp1 = PromoteOp(Node->getOperand(0));
3924 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3926 case ISD::ZERO_EXTEND:
3927 Result = PromoteOp(Node->getOperand(0));
3928 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3929 Result = DAG.getZeroExtendInReg(Result,
3930 Node->getOperand(0).getValueType());
3932 case ISD::SIGN_EXTEND:
3933 Result = PromoteOp(Node->getOperand(0));
3934 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3935 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3937 DAG.getValueType(Node->getOperand(0).getValueType()));
3942 case ISD::FP_ROUND_INREG:
3943 case ISD::SIGN_EXTEND_INREG: {
3944 Tmp1 = LegalizeOp(Node->getOperand(0));
3945 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3947 // If this operation is not supported, convert it to a shl/shr or load/store
3949 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3950 default: assert(0 && "This action not supported for this op yet!");
3951 case TargetLowering::Legal:
3952 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3954 case TargetLowering::Expand:
3955 // If this is an integer extend and shifts are supported, do that.
3956 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3957 // NOTE: we could fall back on load/store here too for targets without
3958 // SAR. However, it is doubtful that any exist.
3959 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
3960 ExtraVT.getSizeInBits();
3961 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3962 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3963 Node->getOperand(0), ShiftCst);
3964 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3966 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3967 // The only way we can lower this is to turn it into a TRUNCSTORE,
3968 // EXTLOAD pair, targetting a temporary location (a stack slot).
3970 // NOTE: there is a choice here between constantly creating new stack
3971 // slots and always reusing the same one. We currently always create
3972 // new ones, as reuse may inhibit scheduling.
3973 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3974 Node->getValueType(0));
3976 assert(0 && "Unknown op");
3982 case ISD::TRAMPOLINE: {
3984 for (unsigned i = 0; i != 6; ++i)
3985 Ops[i] = LegalizeOp(Node->getOperand(i));
3986 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3987 // The only option for this node is to custom lower it.
3988 Result = TLI.LowerOperation(Result, DAG);
3989 assert(Result.Val && "Should always custom lower!");
3991 // Since trampoline produces two values, make sure to remember that we
3992 // legalized both of them.
3993 Tmp1 = LegalizeOp(Result.getValue(1));
3994 Result = LegalizeOp(Result);
3995 AddLegalizedOperand(SDOperand(Node, 0), Result);
3996 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3997 return Op.ResNo ? Tmp1 : Result;
3999 case ISD::FLT_ROUNDS_: {
4000 MVT VT = Node->getValueType(0);
4001 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4002 default: assert(0 && "This action not supported for this op yet!");
4003 case TargetLowering::Custom:
4004 Result = TLI.LowerOperation(Op, DAG);
4005 if (Result.Val) break;
4007 case TargetLowering::Legal:
4008 // If this operation is not supported, lower it to constant 1
4009 Result = DAG.getConstant(1, VT);
4015 MVT VT = Node->getValueType(0);
4016 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4017 default: assert(0 && "This action not supported for this op yet!");
4018 case TargetLowering::Legal:
4019 Tmp1 = LegalizeOp(Node->getOperand(0));
4020 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4022 case TargetLowering::Custom:
4023 Result = TLI.LowerOperation(Op, DAG);
4024 if (Result.Val) break;
4026 case TargetLowering::Expand:
4027 // If this operation is not supported, lower it to 'abort()' call
4028 Tmp1 = LegalizeOp(Node->getOperand(0));
4029 TargetLowering::ArgListTy Args;
4030 std::pair<SDOperand,SDOperand> CallResult =
4031 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4032 false, false, false, CallingConv::C, false,
4033 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4035 Result = CallResult.second;
4042 assert(Result.getValueType() == Op.getValueType() &&
4043 "Bad legalization!");
4045 // Make sure that the generated code is itself legal.
4047 Result = LegalizeOp(Result);
4049 // Note that LegalizeOp may be reentered even from single-use nodes, which
4050 // means that we always must cache transformed nodes.
4051 AddLegalizedOperand(Op, Result);
4055 /// PromoteOp - Given an operation that produces a value in an invalid type,
4056 /// promote it to compute the value into a larger type. The produced value will
4057 /// have the correct bits for the low portion of the register, but no guarantee
4058 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4059 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
4060 MVT VT = Op.getValueType();
4061 MVT NVT = TLI.getTypeToTransformTo(VT);
4062 assert(getTypeAction(VT) == Promote &&
4063 "Caller should expand or legalize operands that are not promotable!");
4064 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4065 "Cannot promote to smaller type!");
4067 SDOperand Tmp1, Tmp2, Tmp3;
4069 SDNode *Node = Op.Val;
4071 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
4072 if (I != PromotedNodes.end()) return I->second;
4074 switch (Node->getOpcode()) {
4075 case ISD::CopyFromReg:
4076 assert(0 && "CopyFromReg must be legal!");
4079 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4081 assert(0 && "Do not know how to promote this operator!");
4084 Result = DAG.getNode(ISD::UNDEF, NVT);
4088 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4090 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4091 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4093 case ISD::ConstantFP:
4094 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4095 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4099 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
4100 && "SetCC type is not legal??");
4101 Result = DAG.getNode(ISD::SETCC,
4102 TLI.getSetCCResultType(Node->getOperand(0)),
4103 Node->getOperand(0), Node->getOperand(1),
4104 Node->getOperand(2));
4108 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4110 Result = LegalizeOp(Node->getOperand(0));
4111 assert(Result.getValueType().bitsGE(NVT) &&
4112 "This truncation doesn't make sense!");
4113 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4114 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4117 // The truncation is not required, because we don't guarantee anything
4118 // about high bits anyway.
4119 Result = PromoteOp(Node->getOperand(0));
4122 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4123 // Truncate the low part of the expanded value to the result type
4124 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4127 case ISD::SIGN_EXTEND:
4128 case ISD::ZERO_EXTEND:
4129 case ISD::ANY_EXTEND:
4130 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4131 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4133 // Input is legal? Just do extend all the way to the larger type.
4134 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4137 // Promote the reg if it's smaller.
4138 Result = PromoteOp(Node->getOperand(0));
4139 // The high bits are not guaranteed to be anything. Insert an extend.
4140 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4141 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4142 DAG.getValueType(Node->getOperand(0).getValueType()));
4143 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4144 Result = DAG.getZeroExtendInReg(Result,
4145 Node->getOperand(0).getValueType());
4149 case ISD::BIT_CONVERT:
4150 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4151 Node->getValueType(0));
4152 Result = PromoteOp(Result);
4155 case ISD::FP_EXTEND:
4156 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4158 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4159 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4160 case Promote: assert(0 && "Unreachable with 2 FP types!");
4162 if (Node->getConstantOperandVal(1) == 0) {
4163 // Input is legal? Do an FP_ROUND_INREG.
4164 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4165 DAG.getValueType(VT));
4167 // Just remove the truncate, it isn't affecting the value.
4168 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4169 Node->getOperand(1));
4174 case ISD::SINT_TO_FP:
4175 case ISD::UINT_TO_FP:
4176 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4178 // No extra round required here.
4179 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4183 Result = PromoteOp(Node->getOperand(0));
4184 if (Node->getOpcode() == ISD::SINT_TO_FP)
4185 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4187 DAG.getValueType(Node->getOperand(0).getValueType()));
4189 Result = DAG.getZeroExtendInReg(Result,
4190 Node->getOperand(0).getValueType());
4191 // No extra round required here.
4192 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4195 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4196 Node->getOperand(0));
4197 // Round if we cannot tolerate excess precision.
4198 if (NoExcessFPPrecision)
4199 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4200 DAG.getValueType(VT));
4205 case ISD::SIGN_EXTEND_INREG:
4206 Result = PromoteOp(Node->getOperand(0));
4207 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4208 Node->getOperand(1));
4210 case ISD::FP_TO_SINT:
4211 case ISD::FP_TO_UINT:
4212 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4215 Tmp1 = Node->getOperand(0);
4218 // The input result is prerounded, so we don't have to do anything
4220 Tmp1 = PromoteOp(Node->getOperand(0));
4223 // If we're promoting a UINT to a larger size, check to see if the new node
4224 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4225 // we can use that instead. This allows us to generate better code for
4226 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4227 // legal, such as PowerPC.
4228 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4229 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4230 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4231 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4232 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4234 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4240 Tmp1 = PromoteOp(Node->getOperand(0));
4241 assert(Tmp1.getValueType() == NVT);
4242 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4243 // NOTE: we do not have to do any extra rounding here for
4244 // NoExcessFPPrecision, because we know the input will have the appropriate
4245 // precision, and these operations don't modify precision at all.
4251 Tmp1 = PromoteOp(Node->getOperand(0));
4252 assert(Tmp1.getValueType() == NVT);
4253 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4254 if (NoExcessFPPrecision)
4255 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4256 DAG.getValueType(VT));
4260 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4261 // directly as well, which may be better.
4262 Tmp1 = PromoteOp(Node->getOperand(0));
4263 assert(Tmp1.getValueType() == NVT);
4264 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4265 if (NoExcessFPPrecision)
4266 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4267 DAG.getValueType(VT));
4271 case ISD::ATOMIC_CMP_SWAP: {
4272 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4273 Tmp2 = PromoteOp(Node->getOperand(2));
4274 Tmp3 = PromoteOp(Node->getOperand(3));
4275 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4276 AtomNode->getBasePtr(), Tmp2, Tmp3,
4277 AtomNode->getSrcValue(),
4278 AtomNode->getAlignment());
4279 // Remember that we legalized the chain.
4280 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4283 case ISD::ATOMIC_LOAD_ADD:
4284 case ISD::ATOMIC_LOAD_SUB:
4285 case ISD::ATOMIC_LOAD_AND:
4286 case ISD::ATOMIC_LOAD_OR:
4287 case ISD::ATOMIC_LOAD_XOR:
4288 case ISD::ATOMIC_LOAD_NAND:
4289 case ISD::ATOMIC_LOAD_MIN:
4290 case ISD::ATOMIC_LOAD_MAX:
4291 case ISD::ATOMIC_LOAD_UMIN:
4292 case ISD::ATOMIC_LOAD_UMAX:
4293 case ISD::ATOMIC_SWAP: {
4294 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4295 Tmp2 = PromoteOp(Node->getOperand(2));
4296 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4297 AtomNode->getBasePtr(), Tmp2,
4298 AtomNode->getSrcValue(),
4299 AtomNode->getAlignment());
4300 // Remember that we legalized the chain.
4301 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4311 // The input may have strange things in the top bits of the registers, but
4312 // these operations don't care. They may have weird bits going out, but
4313 // that too is okay if they are integer operations.
4314 Tmp1 = PromoteOp(Node->getOperand(0));
4315 Tmp2 = PromoteOp(Node->getOperand(1));
4316 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4317 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4322 Tmp1 = PromoteOp(Node->getOperand(0));
4323 Tmp2 = PromoteOp(Node->getOperand(1));
4324 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4325 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4327 // Floating point operations will give excess precision that we may not be
4328 // able to tolerate. If we DO allow excess precision, just leave it,
4329 // otherwise excise it.
4330 // FIXME: Why would we need to round FP ops more than integer ones?
4331 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4332 if (NoExcessFPPrecision)
4333 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4334 DAG.getValueType(VT));
4339 // These operators require that their input be sign extended.
4340 Tmp1 = PromoteOp(Node->getOperand(0));
4341 Tmp2 = PromoteOp(Node->getOperand(1));
4342 if (NVT.isInteger()) {
4343 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4344 DAG.getValueType(VT));
4345 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4346 DAG.getValueType(VT));
4348 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4350 // Perform FP_ROUND: this is probably overly pessimistic.
4351 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4352 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4353 DAG.getValueType(VT));
4357 case ISD::FCOPYSIGN:
4358 // These operators require that their input be fp extended.
4359 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4360 case Expand: assert(0 && "not implemented");
4361 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4362 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4364 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4365 case Expand: assert(0 && "not implemented");
4366 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4367 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4369 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4371 // Perform FP_ROUND: this is probably overly pessimistic.
4372 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4373 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4374 DAG.getValueType(VT));
4379 // These operators require that their input be zero extended.
4380 Tmp1 = PromoteOp(Node->getOperand(0));
4381 Tmp2 = PromoteOp(Node->getOperand(1));
4382 assert(NVT.isInteger() && "Operators don't apply to FP!");
4383 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4384 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4385 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4389 Tmp1 = PromoteOp(Node->getOperand(0));
4390 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4393 // The input value must be properly sign extended.
4394 Tmp1 = PromoteOp(Node->getOperand(0));
4395 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4396 DAG.getValueType(VT));
4397 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4400 // The input value must be properly zero extended.
4401 Tmp1 = PromoteOp(Node->getOperand(0));
4402 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4403 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4407 Tmp1 = Node->getOperand(0); // Get the chain.
4408 Tmp2 = Node->getOperand(1); // Get the pointer.
4409 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4410 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4411 Result = TLI.LowerOperation(Tmp3, DAG);
4413 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4414 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4415 // Increment the pointer, VAList, to the next vaarg
4416 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4417 DAG.getConstant(VT.getSizeInBits()/8,
4418 TLI.getPointerTy()));
4419 // Store the incremented VAList to the legalized pointer
4420 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4421 // Load the actual argument out of the pointer VAList
4422 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4424 // Remember that we legalized the chain.
4425 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4429 LoadSDNode *LD = cast<LoadSDNode>(Node);
4430 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4431 ? ISD::EXTLOAD : LD->getExtensionType();
4432 Result = DAG.getExtLoad(ExtType, NVT,
4433 LD->getChain(), LD->getBasePtr(),
4434 LD->getSrcValue(), LD->getSrcValueOffset(),
4437 LD->getAlignment());
4438 // Remember that we legalized the chain.
4439 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4443 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4444 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4446 MVT VT2 = Tmp2.getValueType();
4447 assert(VT2 == Tmp3.getValueType()
4448 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4449 // Ensure that the resulting node is at least the same size as the operands'
4450 // value types, because we cannot assume that TLI.getSetCCValueType() is
4452 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4455 case ISD::SELECT_CC:
4456 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4457 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4458 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4459 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4462 Tmp1 = Node->getOperand(0);
4463 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4464 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4465 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4466 DAG.getConstant(NVT.getSizeInBits() -
4468 TLI.getShiftAmountTy()));
4473 // Zero extend the argument
4474 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4475 // Perform the larger operation, then subtract if needed.
4476 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4477 switch(Node->getOpcode()) {
4482 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4483 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4484 DAG.getConstant(NVT.getSizeInBits(), NVT),
4486 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4487 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4490 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4491 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4492 DAG.getConstant(NVT.getSizeInBits() -
4493 VT.getSizeInBits(), NVT));
4497 case ISD::EXTRACT_SUBVECTOR:
4498 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4500 case ISD::EXTRACT_VECTOR_ELT:
4501 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4505 assert(Result.Val && "Didn't set a result!");
4507 // Make sure the result is itself legal.
4508 Result = LegalizeOp(Result);
4510 // Remember that we promoted this!
4511 AddPromotedOperand(Op, Result);
4515 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4516 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4517 /// based on the vector type. The return type of this matches the element type
4518 /// of the vector, which may not be legal for the target.
4519 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4520 // We know that operand #0 is the Vec vector. If the index is a constant
4521 // or if the invec is a supported hardware type, we can use it. Otherwise,
4522 // lower to a store then an indexed load.
4523 SDOperand Vec = Op.getOperand(0);
4524 SDOperand Idx = Op.getOperand(1);
4526 MVT TVT = Vec.getValueType();
4527 unsigned NumElems = TVT.getVectorNumElements();
4529 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4530 default: assert(0 && "This action is not supported yet!");
4531 case TargetLowering::Custom: {
4532 Vec = LegalizeOp(Vec);
4533 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4534 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4539 case TargetLowering::Legal:
4540 if (isTypeLegal(TVT)) {
4541 Vec = LegalizeOp(Vec);
4542 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4546 case TargetLowering::Expand:
4550 if (NumElems == 1) {
4551 // This must be an access of the only element. Return it.
4552 Op = ScalarizeVectorOp(Vec);
4553 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4554 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4555 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4557 SplitVectorOp(Vec, Lo, Hi);
4558 if (CIdx->getValue() < NumLoElts) {
4562 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4563 Idx.getValueType());
4566 // It's now an extract from the appropriate high or low part. Recurse.
4567 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4568 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4570 // Store the value to a temporary stack slot, then LOAD the scalar
4571 // element back out.
4572 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4573 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4575 // Add the offset to the index.
4576 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
4577 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4578 DAG.getConstant(EltSize, Idx.getValueType()));
4580 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
4581 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4583 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4585 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4587 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4592 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4593 /// we assume the operation can be split if it is not already legal.
4594 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4595 // We know that operand #0 is the Vec vector. For now we assume the index
4596 // is a constant and that the extracted result is a supported hardware type.
4597 SDOperand Vec = Op.getOperand(0);
4598 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4600 unsigned NumElems = Vec.getValueType().getVectorNumElements();
4602 if (NumElems == Op.getValueType().getVectorNumElements()) {
4603 // This must be an access of the desired vector length. Return it.
4607 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4609 SplitVectorOp(Vec, Lo, Hi);
4610 if (CIdx->getValue() < NumElems/2) {
4614 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4617 // It's now an extract from the appropriate high or low part. Recurse.
4618 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4619 return ExpandEXTRACT_SUBVECTOR(Op);
4622 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4623 /// with condition CC on the current target. This usually involves legalizing
4624 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4625 /// there may be no choice but to create a new SetCC node to represent the
4626 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4627 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4628 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4631 SDOperand Tmp1, Tmp2, Tmp3, Result;
4633 switch (getTypeAction(LHS.getValueType())) {
4635 Tmp1 = LegalizeOp(LHS); // LHS
4636 Tmp2 = LegalizeOp(RHS); // RHS
4639 Tmp1 = PromoteOp(LHS); // LHS
4640 Tmp2 = PromoteOp(RHS); // RHS
4642 // If this is an FP compare, the operands have already been extended.
4643 if (LHS.getValueType().isInteger()) {
4644 MVT VT = LHS.getValueType();
4645 MVT NVT = TLI.getTypeToTransformTo(VT);
4647 // Otherwise, we have to insert explicit sign or zero extends. Note
4648 // that we could insert sign extends for ALL conditions, but zero extend
4649 // is cheaper on many machines (an AND instead of two shifts), so prefer
4651 switch (cast<CondCodeSDNode>(CC)->get()) {
4652 default: assert(0 && "Unknown integer comparison!");
4659 // ALL of these operations will work if we either sign or zero extend
4660 // the operands (including the unsigned comparisons!). Zero extend is
4661 // usually a simpler/cheaper operation, so prefer it.
4662 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4663 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4669 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4670 DAG.getValueType(VT));
4671 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4672 DAG.getValueType(VT));
4678 MVT VT = LHS.getValueType();
4679 if (VT == MVT::f32 || VT == MVT::f64) {
4680 // Expand into one or more soft-fp libcall(s).
4681 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
4682 switch (cast<CondCodeSDNode>(CC)->get()) {
4685 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4689 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4693 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4697 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4701 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4705 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4708 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4711 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4714 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4715 switch (cast<CondCodeSDNode>(CC)->get()) {
4717 // SETONE = SETOLT | SETOGT
4718 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4721 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4724 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4727 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4730 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4733 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4735 default: assert(0 && "Unsupported FP setcc!");
4740 SDOperand Ops[2] = { LHS, RHS };
4741 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).Val,
4742 false /*sign irrelevant*/, Dummy);
4743 Tmp2 = DAG.getConstant(0, MVT::i32);
4744 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4745 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4746 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
4748 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).Val,
4749 false /*sign irrelevant*/, Dummy);
4750 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
4751 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4752 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4755 LHS = LegalizeOp(Tmp1);
4760 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4761 ExpandOp(LHS, LHSLo, LHSHi);
4762 ExpandOp(RHS, RHSLo, RHSHi);
4763 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4765 if (VT==MVT::ppcf128) {
4766 // FIXME: This generated code sucks. We want to generate
4767 // FCMP crN, hi1, hi2
4769 // FCMP crN, lo1, lo2
4770 // The following can be improved, but not that much.
4771 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
4772 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
4773 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4774 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE);
4775 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
4776 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4777 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4786 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4787 if (RHSCST->isAllOnesValue()) {
4788 // Comparison to -1.
4789 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4794 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4795 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4796 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4797 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4800 // If this is a comparison of the sign bit, just look at the top part.
4802 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4803 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4804 CST->isNullValue()) || // X < 0
4805 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4806 CST->isAllOnesValue())) { // X > -1
4812 // FIXME: This generated code sucks.
4813 ISD::CondCode LowCC;
4815 default: assert(0 && "Unknown integer setcc!");
4817 case ISD::SETULT: LowCC = ISD::SETULT; break;
4819 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4821 case ISD::SETULE: LowCC = ISD::SETULE; break;
4823 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4826 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4827 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4828 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4830 // NOTE: on targets without efficient SELECT of bools, we can always use
4831 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4832 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4833 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
4834 LowCC, false, DagCombineInfo);
4836 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
4837 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4838 CCCode, false, DagCombineInfo);
4840 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
4843 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4844 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4845 if ((Tmp1C && Tmp1C->isNullValue()) ||
4846 (Tmp2C && Tmp2C->isNullValue() &&
4847 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4848 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4849 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
4850 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4851 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4852 // low part is known false, returns high part.
4853 // For LE / GE, if high part is known false, ignore the low part.
4854 // For LT / GT, if high part is known true, ignore the low part.
4858 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4859 ISD::SETEQ, false, DagCombineInfo);
4861 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4863 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4864 Result, Tmp1, Tmp2));
4875 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4876 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4877 /// a load from the stack slot to DestVT, extending it if needed.
4878 /// The resultant code need not be legal.
4879 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4882 // Create the stack frame object.
4883 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
4884 SrcOp.getValueType().getTypeForMVT());
4885 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
4887 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4888 int SPFI = StackPtrFI->getIndex();
4890 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
4891 unsigned SlotSize = SlotVT.getSizeInBits();
4892 unsigned DestSize = DestVT.getSizeInBits();
4893 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
4894 DestVT.getTypeForMVT());
4896 // Emit a store to the stack slot. Use a truncstore if the input value is
4897 // later than DestVT.
4900 if (SrcSize > SlotSize)
4901 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4902 PseudoSourceValue::getFixedStack(), SPFI, SlotVT,
4905 assert(SrcSize == SlotSize && "Invalid store");
4906 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4907 PseudoSourceValue::getFixedStack(), SPFI,
4911 // Result is a load from the stack slot.
4912 if (SlotSize == DestSize)
4913 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
4915 assert(SlotSize < DestSize && "Unknown extension!");
4916 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
4920 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4921 // Create a vector sized/aligned stack slot, store the value to element #0,
4922 // then load the whole vector back out.
4923 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4925 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4926 int SPFI = StackPtrFI->getIndex();
4928 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4929 PseudoSourceValue::getFixedStack(), SPFI);
4930 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4931 PseudoSourceValue::getFixedStack(), SPFI);
4935 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4936 /// support the operation, but do support the resultant vector type.
4937 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4939 // If the only non-undef value is the low element, turn this into a
4940 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4941 unsigned NumElems = Node->getNumOperands();
4942 bool isOnlyLowElement = true;
4943 SDOperand SplatValue = Node->getOperand(0);
4945 // FIXME: it would be far nicer to change this into map<SDOperand,uint64_t>
4946 // and use a bitmask instead of a list of elements.
4947 std::map<SDOperand, std::vector<unsigned> > Values;
4948 Values[SplatValue].push_back(0);
4949 bool isConstant = true;
4950 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4951 SplatValue.getOpcode() != ISD::UNDEF)
4954 for (unsigned i = 1; i < NumElems; ++i) {
4955 SDOperand V = Node->getOperand(i);
4956 Values[V].push_back(i);
4957 if (V.getOpcode() != ISD::UNDEF)
4958 isOnlyLowElement = false;
4959 if (SplatValue != V)
4960 SplatValue = SDOperand(0,0);
4962 // If this isn't a constant element or an undef, we can't use a constant
4964 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4965 V.getOpcode() != ISD::UNDEF)
4969 if (isOnlyLowElement) {
4970 // If the low element is an undef too, then this whole things is an undef.
4971 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4972 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4973 // Otherwise, turn this into a scalar_to_vector node.
4974 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4975 Node->getOperand(0));
4978 // If all elements are constants, create a load from the constant pool.
4980 MVT VT = Node->getValueType(0);
4981 std::vector<Constant*> CV;
4982 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4983 if (ConstantFPSDNode *V =
4984 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4985 CV.push_back(ConstantFP::get(V->getValueAPF()));
4986 } else if (ConstantSDNode *V =
4987 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4988 CV.push_back(ConstantInt::get(V->getAPIntValue()));
4990 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4992 Node->getOperand(0).getValueType().getTypeForMVT();
4993 CV.push_back(UndefValue::get(OpNTy));
4996 Constant *CP = ConstantVector::get(CV);
4997 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4998 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4999 PseudoSourceValue::getConstantPool(), 0);
5002 if (SplatValue.Val) { // Splat of one value?
5003 // Build the shuffle constant vector: <0, 0, 0, 0>
5004 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5005 SDOperand Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5006 std::vector<SDOperand> ZeroVec(NumElems, Zero);
5007 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5008 &ZeroVec[0], ZeroVec.size());
5010 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5011 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5012 // Get the splatted value into the low element of a vector register.
5013 SDOperand LowValVec =
5014 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
5016 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5017 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
5018 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
5023 // If there are only two unique elements, we may be able to turn this into a
5025 if (Values.size() == 2) {
5026 // Get the two values in deterministic order.
5027 SDOperand Val1 = Node->getOperand(1);
5029 std::map<SDOperand, std::vector<unsigned> >::iterator MI = Values.begin();
5030 if (MI->first != Val1)
5033 Val2 = (++MI)->first;
5035 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5036 // vector shuffle has the undef vector on the RHS.
5037 if (Val1.getOpcode() == ISD::UNDEF)
5038 std::swap(Val1, Val2);
5040 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5041 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5042 MVT MaskEltVT = MaskVT.getVectorElementType();
5043 std::vector<SDOperand> MaskVec(NumElems);
5045 // Set elements of the shuffle mask for Val1.
5046 std::vector<unsigned> &Val1Elts = Values[Val1];
5047 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5048 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5050 // Set elements of the shuffle mask for Val2.
5051 std::vector<unsigned> &Val2Elts = Values[Val2];
5052 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5053 if (Val2.getOpcode() != ISD::UNDEF)
5054 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5056 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
5058 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5059 &MaskVec[0], MaskVec.size());
5061 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5062 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5063 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5064 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
5065 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
5066 SDOperand Ops[] = { Val1, Val2, ShuffleMask };
5068 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5069 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5073 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5074 // aligned object on the stack, store each element into it, then load
5075 // the result as a vector.
5076 MVT VT = Node->getValueType(0);
5077 // Create the stack frame object.
5078 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
5080 // Emit a store of each element to the stack slot.
5081 SmallVector<SDOperand, 8> Stores;
5082 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5083 // Store (in the right endianness) the elements to memory.
5084 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5085 // Ignore undef elements.
5086 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5088 unsigned Offset = TypeByteSize*i;
5090 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5091 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5093 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5097 SDOperand StoreChain;
5098 if (!Stores.empty()) // Not all undef elements?
5099 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5100 &Stores[0], Stores.size());
5102 StoreChain = DAG.getEntryNode();
5104 // Result is a load from the stack slot.
5105 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5108 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5109 SDOperand Op, SDOperand Amt,
5110 SDOperand &Lo, SDOperand &Hi) {
5111 // Expand the subcomponents.
5112 SDOperand LHSL, LHSH;
5113 ExpandOp(Op, LHSL, LHSH);
5115 SDOperand Ops[] = { LHSL, LHSH, Amt };
5116 MVT VT = LHSL.getValueType();
5117 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5118 Hi = Lo.getValue(1);
5122 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5123 /// smaller elements. If we can't find a way that is more efficient than a
5124 /// libcall on this target, return false. Otherwise, return true with the
5125 /// low-parts expanded into Lo and Hi.
5126 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
5127 SDOperand &Lo, SDOperand &Hi) {
5128 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5129 "This is not a shift!");
5131 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5132 SDOperand ShAmt = LegalizeOp(Amt);
5133 MVT ShTy = ShAmt.getValueType();
5134 unsigned ShBits = ShTy.getSizeInBits();
5135 unsigned VTBits = Op.getValueType().getSizeInBits();
5136 unsigned NVTBits = NVT.getSizeInBits();
5138 // Handle the case when Amt is an immediate.
5139 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
5140 unsigned Cst = CN->getValue();
5141 // Expand the incoming operand to be shifted, so that we have its parts
5143 ExpandOp(Op, InL, InH);
5147 Lo = DAG.getConstant(0, NVT);
5148 Hi = DAG.getConstant(0, NVT);
5149 } else if (Cst > NVTBits) {
5150 Lo = DAG.getConstant(0, NVT);
5151 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5152 } else if (Cst == NVTBits) {
5153 Lo = DAG.getConstant(0, NVT);
5156 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5157 Hi = DAG.getNode(ISD::OR, NVT,
5158 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5159 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5164 Lo = DAG.getConstant(0, NVT);
5165 Hi = DAG.getConstant(0, NVT);
5166 } else if (Cst > NVTBits) {
5167 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5168 Hi = DAG.getConstant(0, NVT);
5169 } else if (Cst == NVTBits) {
5171 Hi = DAG.getConstant(0, NVT);
5173 Lo = DAG.getNode(ISD::OR, NVT,
5174 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5175 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5176 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5181 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5182 DAG.getConstant(NVTBits-1, ShTy));
5183 } else if (Cst > NVTBits) {
5184 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5185 DAG.getConstant(Cst-NVTBits, ShTy));
5186 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5187 DAG.getConstant(NVTBits-1, ShTy));
5188 } else if (Cst == NVTBits) {
5190 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5191 DAG.getConstant(NVTBits-1, ShTy));
5193 Lo = DAG.getNode(ISD::OR, NVT,
5194 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5195 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5196 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5202 // Okay, the shift amount isn't constant. However, if we can tell that it is
5203 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5204 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5205 APInt KnownZero, KnownOne;
5206 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5208 // If we know that if any of the high bits of the shift amount are one, then
5209 // we can do this as a couple of simple shifts.
5210 if (KnownOne.intersects(Mask)) {
5211 // Mask out the high bit, which we know is set.
5212 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5213 DAG.getConstant(~Mask, Amt.getValueType()));
5215 // Expand the incoming operand to be shifted, so that we have its parts
5217 ExpandOp(Op, InL, InH);
5220 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5221 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5224 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5225 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5228 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5229 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5230 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5235 // If we know that the high bits of the shift amount are all zero, then we can
5236 // do this as a couple of simple shifts.
5237 if ((KnownZero & Mask) == Mask) {
5239 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5240 DAG.getConstant(NVTBits, Amt.getValueType()),
5243 // Expand the incoming operand to be shifted, so that we have its parts
5245 ExpandOp(Op, InL, InH);
5248 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5249 Hi = DAG.getNode(ISD::OR, NVT,
5250 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5251 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5254 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5255 Lo = DAG.getNode(ISD::OR, NVT,
5256 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5257 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5260 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5261 Lo = DAG.getNode(ISD::OR, NVT,
5262 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5263 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5272 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5273 // does not fit into a register, return the lo part and set the hi part to the
5274 // by-reg argument. If it does fit into a single register, return the result
5275 // and leave the Hi part unset.
5276 SDOperand SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5277 bool isSigned, SDOperand &Hi) {
5278 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5279 // The input chain to this libcall is the entry node of the function.
5280 // Legalizing the call will automatically add the previous call to the
5282 SDOperand InChain = DAG.getEntryNode();
5284 TargetLowering::ArgListTy Args;
5285 TargetLowering::ArgListEntry Entry;
5286 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5287 MVT ArgVT = Node->getOperand(i).getValueType();
5288 const Type *ArgTy = ArgVT.getTypeForMVT();
5289 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5290 Entry.isSExt = isSigned;
5291 Entry.isZExt = !isSigned;
5292 Args.push_back(Entry);
5294 SDOperand Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5295 TLI.getPointerTy());
5297 // Splice the libcall in wherever FindInputOutputChains tells us to.
5298 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5299 std::pair<SDOperand,SDOperand> CallInfo =
5300 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
5301 false, Callee, Args, DAG);
5303 // Legalize the call sequence, starting with the chain. This will advance
5304 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5305 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5306 LegalizeOp(CallInfo.second);
5308 switch (getTypeAction(CallInfo.first.getValueType())) {
5309 default: assert(0 && "Unknown thing");
5311 Result = CallInfo.first;
5314 ExpandOp(CallInfo.first, Result, Hi);
5321 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5323 SDOperand SelectionDAGLegalize::
5324 ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source) {
5325 MVT SourceVT = Source.getValueType();
5326 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5328 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5329 if (!isSigned && SourceVT != MVT::i32) {
5330 // The integer value loaded will be incorrectly if the 'sign bit' of the
5331 // incoming integer is set. To handle this, we dynamically test to see if
5332 // it is set, and, if so, add a fudge factor.
5336 ExpandOp(Source, Lo, Hi);
5337 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5339 // The comparison for the sign bit will use the entire operand.
5343 // If this is unsigned, and not supported, first perform the conversion to
5344 // signed, then adjust the result if the sign bit is set.
5345 SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source);
5347 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5348 DAG.getConstant(0, Hi.getValueType()),
5350 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5351 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5352 SignSet, Four, Zero);
5353 uint64_t FF = 0x5f800000ULL;
5354 if (TLI.isLittleEndian()) FF <<= 32;
5355 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5357 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5358 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5359 SDOperand FudgeInReg;
5360 if (DestTy == MVT::f32)
5361 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5362 PseudoSourceValue::getConstantPool(), 0);
5363 else if (DestTy.bitsGT(MVT::f32))
5364 // FIXME: Avoid the extend by construction the right constantpool?
5365 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5367 PseudoSourceValue::getConstantPool(), 0,
5370 assert(0 && "Unexpected conversion");
5372 MVT SCVT = SignedConv.getValueType();
5373 if (SCVT != DestTy) {
5374 // Destination type needs to be expanded as well. The FADD now we are
5375 // constructing will be expanded into a libcall.
5376 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5377 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5378 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5379 SignedConv, SignedConv.getValue(1));
5381 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5383 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5386 // Check to see if the target has a custom way to lower this. If so, use it.
5387 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5388 default: assert(0 && "This action not implemented for this operation!");
5389 case TargetLowering::Legal:
5390 case TargetLowering::Expand:
5391 break; // This case is handled below.
5392 case TargetLowering::Custom: {
5393 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5396 return LegalizeOp(NV);
5397 break; // The target decided this was legal after all
5401 // Expand the source, then glue it back together for the call. We must expand
5402 // the source in case it is shared (this pass of legalize must traverse it).
5404 SDOperand SrcLo, SrcHi;
5405 ExpandOp(Source, SrcLo, SrcHi);
5406 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5410 if (SourceVT == MVT::i32) {
5411 if (DestTy == MVT::f32)
5412 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
5414 assert(DestTy == MVT::f64 && "Unknown fp value type!");
5415 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
5417 } else if (SourceVT == MVT::i64) {
5418 if (DestTy == MVT::f32)
5419 LC = RTLIB::SINTTOFP_I64_F32;
5420 else if (DestTy == MVT::f64)
5421 LC = RTLIB::SINTTOFP_I64_F64;
5422 else if (DestTy == MVT::f80)
5423 LC = RTLIB::SINTTOFP_I64_F80;
5425 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
5426 LC = RTLIB::SINTTOFP_I64_PPCF128;
5428 } else if (SourceVT == MVT::i128) {
5429 if (DestTy == MVT::f32)
5430 LC = RTLIB::SINTTOFP_I128_F32;
5431 else if (DestTy == MVT::f64)
5432 LC = RTLIB::SINTTOFP_I128_F64;
5433 else if (DestTy == MVT::f80)
5434 LC = RTLIB::SINTTOFP_I128_F80;
5436 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
5437 LC = RTLIB::SINTTOFP_I128_PPCF128;
5440 assert(0 && "Unknown int value type");
5443 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
5444 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5446 SDOperand Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart);
5447 if (Result.getValueType() != DestTy && HiPart.Val)
5448 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5452 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5453 /// INT_TO_FP operation of the specified operand when the target requests that
5454 /// we expand it. At this point, we know that the result and operand types are
5455 /// legal for the target.
5456 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5459 if (Op0.getValueType() == MVT::i32) {
5460 // simple 32-bit [signed|unsigned] integer to float/double expansion
5462 // Get the stack frame index of a 8 byte buffer.
5463 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5465 // word offset constant for Hi/Lo address computation
5466 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5467 // set up Hi and Lo (into buffer) address based on endian
5468 SDOperand Hi = StackSlot;
5469 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5470 if (TLI.isLittleEndian())
5473 // if signed map to unsigned space
5474 SDOperand Op0Mapped;
5476 // constant used to invert sign bit (signed to unsigned mapping)
5477 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5478 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5482 // store the lo of the constructed double - based on integer input
5483 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5484 Op0Mapped, Lo, NULL, 0);
5485 // initial hi portion of constructed double
5486 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5487 // store the hi of the constructed double - biased exponent
5488 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5489 // load the constructed double
5490 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5491 // FP constant to bias correct the final result
5492 SDOperand Bias = DAG.getConstantFP(isSigned ?
5493 BitsToDouble(0x4330000080000000ULL)
5494 : BitsToDouble(0x4330000000000000ULL),
5496 // subtract the bias
5497 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5500 // handle final rounding
5501 if (DestVT == MVT::f64) {
5504 } else if (DestVT.bitsLT(MVT::f64)) {
5505 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5506 DAG.getIntPtrConstant(0));
5507 } else if (DestVT.bitsGT(MVT::f64)) {
5508 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5512 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5513 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5515 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
5516 DAG.getConstant(0, Op0.getValueType()),
5518 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5519 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5520 SignSet, Four, Zero);
5522 // If the sign bit of the integer is set, the large number will be treated
5523 // as a negative number. To counteract this, the dynamic code adds an
5524 // offset depending on the data type.
5526 switch (Op0.getValueType().getSimpleVT()) {
5527 default: assert(0 && "Unsupported integer type!");
5528 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5529 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5530 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5531 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5533 if (TLI.isLittleEndian()) FF <<= 32;
5534 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5536 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5537 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5538 SDOperand FudgeInReg;
5539 if (DestVT == MVT::f32)
5540 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5541 PseudoSourceValue::getConstantPool(), 0);
5544 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5545 DAG.getEntryNode(), CPIdx,
5546 PseudoSourceValue::getConstantPool(), 0,
5550 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5553 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5554 /// *INT_TO_FP operation of the specified operand when the target requests that
5555 /// we promote it. At this point, we know that the result and operand types are
5556 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5557 /// operation that takes a larger input.
5558 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5561 // First step, figure out the appropriate *INT_TO_FP operation to use.
5562 MVT NewInTy = LegalOp.getValueType();
5564 unsigned OpToUse = 0;
5566 // Scan for the appropriate larger type to use.
5568 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
5569 assert(NewInTy.isInteger() && "Ran out of possibilities!");
5571 // If the target supports SINT_TO_FP of this type, use it.
5572 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5574 case TargetLowering::Legal:
5575 if (!TLI.isTypeLegal(NewInTy))
5576 break; // Can't use this datatype.
5578 case TargetLowering::Custom:
5579 OpToUse = ISD::SINT_TO_FP;
5583 if (isSigned) continue;
5585 // If the target supports UINT_TO_FP of this type, use it.
5586 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5588 case TargetLowering::Legal:
5589 if (!TLI.isTypeLegal(NewInTy))
5590 break; // Can't use this datatype.
5592 case TargetLowering::Custom:
5593 OpToUse = ISD::UINT_TO_FP;
5598 // Otherwise, try a larger type.
5601 // Okay, we found the operation and type to use. Zero extend our input to the
5602 // desired type then run the operation on it.
5603 return DAG.getNode(OpToUse, DestVT,
5604 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5608 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5609 /// FP_TO_*INT operation of the specified operand when the target requests that
5610 /// we promote it. At this point, we know that the result and operand types are
5611 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5612 /// operation that returns a larger result.
5613 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5616 // First step, figure out the appropriate FP_TO*INT operation to use.
5617 MVT NewOutTy = DestVT;
5619 unsigned OpToUse = 0;
5621 // Scan for the appropriate larger type to use.
5623 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
5624 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
5626 // If the target supports FP_TO_SINT returning this type, use it.
5627 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5629 case TargetLowering::Legal:
5630 if (!TLI.isTypeLegal(NewOutTy))
5631 break; // Can't use this datatype.
5633 case TargetLowering::Custom:
5634 OpToUse = ISD::FP_TO_SINT;
5639 // If the target supports FP_TO_UINT of this type, use it.
5640 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5642 case TargetLowering::Legal:
5643 if (!TLI.isTypeLegal(NewOutTy))
5644 break; // Can't use this datatype.
5646 case TargetLowering::Custom:
5647 OpToUse = ISD::FP_TO_UINT;
5652 // Otherwise, try a larger type.
5656 // Okay, we found the operation and type to use.
5657 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5659 // If the operation produces an invalid type, it must be custom lowered. Use
5660 // the target lowering hooks to expand it. Just keep the low part of the
5661 // expanded operation, we know that we're truncating anyway.
5662 if (getTypeAction(NewOutTy) == Expand) {
5663 Operation = SDOperand(TLI.ReplaceNodeResults(Operation.Val, DAG), 0);
5664 assert(Operation.Val && "Didn't return anything");
5667 // Truncate the result of the extended FP_TO_*INT operation to the desired
5669 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5672 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5674 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5675 MVT VT = Op.getValueType();
5676 MVT SHVT = TLI.getShiftAmountTy();
5677 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5678 switch (VT.getSimpleVT()) {
5679 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5681 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5682 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5683 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5685 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5686 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5687 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5688 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5689 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5690 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5691 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5692 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5693 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5695 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5696 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5697 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5698 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5699 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5700 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5701 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5702 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5703 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5704 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5705 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5706 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5707 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5708 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5709 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5710 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5711 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5712 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5713 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5714 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5715 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5719 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5721 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5723 default: assert(0 && "Cannot expand this yet!");
5725 static const uint64_t mask[6] = {
5726 0x5555555555555555ULL, 0x3333333333333333ULL,
5727 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5728 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5730 MVT VT = Op.getValueType();
5731 MVT ShVT = TLI.getShiftAmountTy();
5732 unsigned len = VT.getSizeInBits();
5733 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5734 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5735 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5736 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5737 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5738 DAG.getNode(ISD::AND, VT,
5739 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5744 // for now, we do this:
5745 // x = x | (x >> 1);
5746 // x = x | (x >> 2);
5748 // x = x | (x >>16);
5749 // x = x | (x >>32); // for 64-bit input
5750 // return popcount(~x);
5752 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5753 MVT VT = Op.getValueType();
5754 MVT ShVT = TLI.getShiftAmountTy();
5755 unsigned len = VT.getSizeInBits();
5756 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5757 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5758 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5760 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5761 return DAG.getNode(ISD::CTPOP, VT, Op);
5764 // for now, we use: { return popcount(~x & (x - 1)); }
5765 // unless the target has ctlz but not ctpop, in which case we use:
5766 // { return 32 - nlz(~x & (x-1)); }
5767 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5768 MVT VT = Op.getValueType();
5769 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5770 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5771 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5772 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5773 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5774 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5775 TLI.isOperationLegal(ISD::CTLZ, VT))
5776 return DAG.getNode(ISD::SUB, VT,
5777 DAG.getConstant(VT.getSizeInBits(), VT),
5778 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5779 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5784 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5785 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5786 /// LegalizeNodes map is filled in for any results that are not expanded, the
5787 /// ExpandedNodes map is filled in for any results that are expanded, and the
5788 /// Lo/Hi values are returned.
5789 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5790 MVT VT = Op.getValueType();
5791 MVT NVT = TLI.getTypeToTransformTo(VT);
5792 SDNode *Node = Op.Val;
5793 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5794 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
5795 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
5797 // See if we already expanded it.
5798 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5799 = ExpandedNodes.find(Op);
5800 if (I != ExpandedNodes.end()) {
5801 Lo = I->second.first;
5802 Hi = I->second.second;
5806 switch (Node->getOpcode()) {
5807 case ISD::CopyFromReg:
5808 assert(0 && "CopyFromReg must be legal!");
5809 case ISD::FP_ROUND_INREG:
5810 if (VT == MVT::ppcf128 &&
5811 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5812 TargetLowering::Custom) {
5813 SDOperand SrcLo, SrcHi, Src;
5814 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5815 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5816 SDOperand Result = TLI.LowerOperation(
5817 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5818 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5819 Lo = Result.Val->getOperand(0);
5820 Hi = Result.Val->getOperand(1);
5826 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5828 assert(0 && "Do not know how to expand this operator!");
5830 case ISD::EXTRACT_ELEMENT:
5831 ExpandOp(Node->getOperand(0), Lo, Hi);
5832 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
5833 return ExpandOp(Hi, Lo, Hi);
5834 return ExpandOp(Lo, Lo, Hi);
5835 case ISD::EXTRACT_VECTOR_ELT:
5836 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5837 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5838 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5839 return ExpandOp(Lo, Lo, Hi);
5841 Lo = DAG.getNode(ISD::UNDEF, NVT);
5842 Hi = DAG.getNode(ISD::UNDEF, NVT);
5844 case ISD::Constant: {
5845 unsigned NVTBits = NVT.getSizeInBits();
5846 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
5847 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
5848 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
5851 case ISD::ConstantFP: {
5852 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5853 if (CFP->getValueType(0) == MVT::ppcf128) {
5854 APInt api = CFP->getValueAPF().convertToAPInt();
5855 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5857 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5861 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5862 if (getTypeAction(Lo.getValueType()) == Expand)
5863 ExpandOp(Lo, Lo, Hi);
5866 case ISD::BUILD_PAIR:
5867 // Return the operands.
5868 Lo = Node->getOperand(0);
5869 Hi = Node->getOperand(1);
5872 case ISD::MERGE_VALUES:
5873 if (Node->getNumValues() == 1) {
5874 ExpandOp(Op.getOperand(0), Lo, Hi);
5877 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5878 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5879 Op.getValue(1).getValueType() == MVT::Other &&
5880 "unhandled MERGE_VALUES");
5881 ExpandOp(Op.getOperand(0), Lo, Hi);
5882 // Remember that we legalized the chain.
5883 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5886 case ISD::SIGN_EXTEND_INREG:
5887 ExpandOp(Node->getOperand(0), Lo, Hi);
5888 // sext_inreg the low part if needed.
5889 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5891 // The high part gets the sign extension from the lo-part. This handles
5892 // things like sextinreg V:i64 from i8.
5893 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5894 DAG.getConstant(NVT.getSizeInBits()-1,
5895 TLI.getShiftAmountTy()));
5899 ExpandOp(Node->getOperand(0), Lo, Hi);
5900 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5901 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5907 ExpandOp(Node->getOperand(0), Lo, Hi);
5908 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5909 DAG.getNode(ISD::CTPOP, NVT, Lo),
5910 DAG.getNode(ISD::CTPOP, NVT, Hi));
5911 Hi = DAG.getConstant(0, NVT);
5915 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5916 ExpandOp(Node->getOperand(0), Lo, Hi);
5917 SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5918 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5919 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
5921 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5922 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5924 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5925 Hi = DAG.getConstant(0, NVT);
5930 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5931 ExpandOp(Node->getOperand(0), Lo, Hi);
5932 SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5933 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5934 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
5936 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5937 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5939 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5940 Hi = DAG.getConstant(0, NVT);
5945 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5946 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5947 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5948 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5950 // Remember that we legalized the chain.
5951 Hi = LegalizeOp(Hi);
5952 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5953 if (TLI.isBigEndian())
5959 LoadSDNode *LD = cast<LoadSDNode>(Node);
5960 SDOperand Ch = LD->getChain(); // Legalize the chain.
5961 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5962 ISD::LoadExtType ExtType = LD->getExtensionType();
5963 int SVOffset = LD->getSrcValueOffset();
5964 unsigned Alignment = LD->getAlignment();
5965 bool isVolatile = LD->isVolatile();
5967 if (ExtType == ISD::NON_EXTLOAD) {
5968 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5969 isVolatile, Alignment);
5970 if (VT == MVT::f32 || VT == MVT::f64) {
5971 // f32->i32 or f64->i64 one to one expansion.
5972 // Remember that we legalized the chain.
5973 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5974 // Recursively expand the new load.
5975 if (getTypeAction(NVT) == Expand)
5976 ExpandOp(Lo, Lo, Hi);
5980 // Increment the pointer to the other half.
5981 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
5982 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5983 DAG.getIntPtrConstant(IncrementSize));
5984 SVOffset += IncrementSize;
5985 Alignment = MinAlign(Alignment, IncrementSize);
5986 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5987 isVolatile, Alignment);
5989 // Build a factor node to remember that this load is independent of the
5991 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5994 // Remember that we legalized the chain.
5995 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5996 if (TLI.isBigEndian())
5999 MVT EVT = LD->getMemoryVT();
6001 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6002 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6003 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6004 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
6005 SVOffset, isVolatile, Alignment);
6006 // Remember that we legalized the chain.
6007 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
6008 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
6013 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
6014 SVOffset, isVolatile, Alignment);
6016 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
6017 SVOffset, EVT, isVolatile,
6020 // Remember that we legalized the chain.
6021 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
6023 if (ExtType == ISD::SEXTLOAD) {
6024 // The high part is obtained by SRA'ing all but one of the bits of the
6026 unsigned LoSize = Lo.getValueType().getSizeInBits();
6027 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6028 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6029 } else if (ExtType == ISD::ZEXTLOAD) {
6030 // The high part is just a zero.
6031 Hi = DAG.getConstant(0, NVT);
6032 } else /* if (ExtType == ISD::EXTLOAD) */ {
6033 // The high part is undefined.
6034 Hi = DAG.getNode(ISD::UNDEF, NVT);
6041 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6042 SDOperand LL, LH, RL, RH;
6043 ExpandOp(Node->getOperand(0), LL, LH);
6044 ExpandOp(Node->getOperand(1), RL, RH);
6045 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
6046 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
6050 SDOperand LL, LH, RL, RH;
6051 ExpandOp(Node->getOperand(1), LL, LH);
6052 ExpandOp(Node->getOperand(2), RL, RH);
6053 if (getTypeAction(NVT) == Expand)
6054 NVT = TLI.getTypeToExpandTo(NVT);
6055 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
6057 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
6060 case ISD::SELECT_CC: {
6061 SDOperand TL, TH, FL, FH;
6062 ExpandOp(Node->getOperand(2), TL, TH);
6063 ExpandOp(Node->getOperand(3), FL, FH);
6064 if (getTypeAction(NVT) == Expand)
6065 NVT = TLI.getTypeToExpandTo(NVT);
6066 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6067 Node->getOperand(1), TL, FL, Node->getOperand(4));
6069 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6070 Node->getOperand(1), TH, FH, Node->getOperand(4));
6073 case ISD::ANY_EXTEND:
6074 // The low part is any extension of the input (which degenerates to a copy).
6075 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6076 // The high part is undefined.
6077 Hi = DAG.getNode(ISD::UNDEF, NVT);
6079 case ISD::SIGN_EXTEND: {
6080 // The low part is just a sign extension of the input (which degenerates to
6082 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6084 // The high part is obtained by SRA'ing all but one of the bits of the lo
6086 unsigned LoSize = Lo.getValueType().getSizeInBits();
6087 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6088 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6091 case ISD::ZERO_EXTEND:
6092 // The low part is just a zero extension of the input (which degenerates to
6094 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6096 // The high part is just a zero.
6097 Hi = DAG.getConstant(0, NVT);
6100 case ISD::TRUNCATE: {
6101 // The input value must be larger than this value. Expand *it*.
6103 ExpandOp(Node->getOperand(0), NewLo, Hi);
6105 // The low part is now either the right size, or it is closer. If not the
6106 // right size, make an illegal truncate so we recursively expand it.
6107 if (NewLo.getValueType() != Node->getValueType(0))
6108 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6109 ExpandOp(NewLo, Lo, Hi);
6113 case ISD::BIT_CONVERT: {
6115 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6116 // If the target wants to, allow it to lower this itself.
6117 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6118 case Expand: assert(0 && "cannot expand FP!");
6119 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6120 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6122 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6125 // f32 / f64 must be expanded to i32 / i64.
6126 if (VT == MVT::f32 || VT == MVT::f64) {
6127 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6128 if (getTypeAction(NVT) == Expand)
6129 ExpandOp(Lo, Lo, Hi);
6133 // If source operand will be expanded to the same type as VT, i.e.
6134 // i64 <- f64, i32 <- f32, expand the source operand instead.
6135 MVT VT0 = Node->getOperand(0).getValueType();
6136 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6137 ExpandOp(Node->getOperand(0), Lo, Hi);
6141 // Turn this into a load/store pair by default.
6143 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6145 ExpandOp(Tmp, Lo, Hi);
6149 case ISD::READCYCLECOUNTER: {
6150 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6151 TargetLowering::Custom &&
6152 "Must custom expand ReadCycleCounter");
6153 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6154 assert(Tmp.Val && "Node must be custom expanded!");
6155 ExpandOp(Tmp.getValue(0), Lo, Hi);
6156 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6157 LegalizeOp(Tmp.getValue(1)));
6161 case ISD::ATOMIC_CMP_SWAP: {
6162 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6163 assert(Tmp.Val && "Node must be custom expanded!");
6164 ExpandOp(Tmp.getValue(0), Lo, Hi);
6165 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6166 LegalizeOp(Tmp.getValue(1)));
6172 // These operators cannot be expanded directly, emit them as calls to
6173 // library functions.
6174 case ISD::FP_TO_SINT: {
6175 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6177 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6178 case Expand: assert(0 && "cannot expand FP!");
6179 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6180 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6183 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6185 // Now that the custom expander is done, expand the result, which is still
6188 ExpandOp(Op, Lo, Hi);
6193 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6194 if (VT == MVT::i64) {
6195 if (Node->getOperand(0).getValueType() == MVT::f32)
6196 LC = RTLIB::FPTOSINT_F32_I64;
6197 else if (Node->getOperand(0).getValueType() == MVT::f64)
6198 LC = RTLIB::FPTOSINT_F64_I64;
6199 else if (Node->getOperand(0).getValueType() == MVT::f80)
6200 LC = RTLIB::FPTOSINT_F80_I64;
6201 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6202 LC = RTLIB::FPTOSINT_PPCF128_I64;
6203 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6204 } else if (VT == MVT::i128) {
6205 if (Node->getOperand(0).getValueType() == MVT::f32)
6206 LC = RTLIB::FPTOSINT_F32_I128;
6207 else if (Node->getOperand(0).getValueType() == MVT::f64)
6208 LC = RTLIB::FPTOSINT_F64_I128;
6209 else if (Node->getOperand(0).getValueType() == MVT::f80)
6210 LC = RTLIB::FPTOSINT_F80_I128;
6211 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6212 LC = RTLIB::FPTOSINT_PPCF128_I128;
6213 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6215 assert(0 && "Unexpected uint-to-fp conversion!");
6220 case ISD::FP_TO_UINT: {
6221 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6223 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6224 case Expand: assert(0 && "cannot expand FP!");
6225 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6226 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6229 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6231 // Now that the custom expander is done, expand the result.
6233 ExpandOp(Op, Lo, Hi);
6238 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6239 if (VT == MVT::i64) {
6240 if (Node->getOperand(0).getValueType() == MVT::f32)
6241 LC = RTLIB::FPTOUINT_F32_I64;
6242 else if (Node->getOperand(0).getValueType() == MVT::f64)
6243 LC = RTLIB::FPTOUINT_F64_I64;
6244 else if (Node->getOperand(0).getValueType() == MVT::f80)
6245 LC = RTLIB::FPTOUINT_F80_I64;
6246 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6247 LC = RTLIB::FPTOUINT_PPCF128_I64;
6248 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6249 } else if (VT == MVT::i128) {
6250 if (Node->getOperand(0).getValueType() == MVT::f32)
6251 LC = RTLIB::FPTOUINT_F32_I128;
6252 else if (Node->getOperand(0).getValueType() == MVT::f64)
6253 LC = RTLIB::FPTOUINT_F64_I128;
6254 else if (Node->getOperand(0).getValueType() == MVT::f80)
6255 LC = RTLIB::FPTOUINT_F80_I128;
6256 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6257 LC = RTLIB::FPTOUINT_PPCF128_I128;
6258 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6260 assert(0 && "Unexpected uint-to-fp conversion!");
6266 // If the target wants custom lowering, do so.
6267 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6268 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6269 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6270 Op = TLI.LowerOperation(Op, DAG);
6272 // Now that the custom expander is done, expand the result, which is
6274 ExpandOp(Op, Lo, Hi);
6279 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6280 // this X << 1 as X+X.
6281 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6282 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6283 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6284 SDOperand LoOps[2], HiOps[3];
6285 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6286 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6287 LoOps[1] = LoOps[0];
6288 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6290 HiOps[1] = HiOps[0];
6291 HiOps[2] = Lo.getValue(1);
6292 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6297 // If we can emit an efficient shift operation, do so now.
6298 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6301 // If this target supports SHL_PARTS, use it.
6302 TargetLowering::LegalizeAction Action =
6303 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6304 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6305 Action == TargetLowering::Custom) {
6306 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6310 // Otherwise, emit a libcall.
6311 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6316 // If the target wants custom lowering, do so.
6317 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6318 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6319 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6320 Op = TLI.LowerOperation(Op, DAG);
6322 // Now that the custom expander is done, expand the result, which is
6324 ExpandOp(Op, Lo, Hi);
6329 // If we can emit an efficient shift operation, do so now.
6330 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6333 // If this target supports SRA_PARTS, use it.
6334 TargetLowering::LegalizeAction Action =
6335 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6336 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6337 Action == TargetLowering::Custom) {
6338 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6342 // Otherwise, emit a libcall.
6343 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6348 // If the target wants custom lowering, do so.
6349 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6350 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6351 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6352 Op = TLI.LowerOperation(Op, DAG);
6354 // Now that the custom expander is done, expand the result, which is
6356 ExpandOp(Op, Lo, Hi);
6361 // If we can emit an efficient shift operation, do so now.
6362 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6365 // If this target supports SRL_PARTS, use it.
6366 TargetLowering::LegalizeAction Action =
6367 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6368 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6369 Action == TargetLowering::Custom) {
6370 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6374 // Otherwise, emit a libcall.
6375 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6381 // If the target wants to custom expand this, let them.
6382 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6383 TargetLowering::Custom) {
6384 SDOperand Result = TLI.LowerOperation(Op, DAG);
6386 ExpandOp(Result, Lo, Hi);
6391 // Expand the subcomponents.
6392 SDOperand LHSL, LHSH, RHSL, RHSH;
6393 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6394 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6395 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6396 SDOperand LoOps[2], HiOps[3];
6401 if (Node->getOpcode() == ISD::ADD) {
6402 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6403 HiOps[2] = Lo.getValue(1);
6404 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6406 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6407 HiOps[2] = Lo.getValue(1);
6408 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6415 // Expand the subcomponents.
6416 SDOperand LHSL, LHSH, RHSL, RHSH;
6417 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6418 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6419 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6420 SDOperand LoOps[2] = { LHSL, RHSL };
6421 SDOperand HiOps[3] = { LHSH, RHSH };
6423 if (Node->getOpcode() == ISD::ADDC) {
6424 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6425 HiOps[2] = Lo.getValue(1);
6426 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6428 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6429 HiOps[2] = Lo.getValue(1);
6430 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6432 // Remember that we legalized the flag.
6433 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6438 // Expand the subcomponents.
6439 SDOperand LHSL, LHSH, RHSL, RHSH;
6440 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6441 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6442 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6443 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6444 SDOperand HiOps[3] = { LHSH, RHSH };
6446 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6447 HiOps[2] = Lo.getValue(1);
6448 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6450 // Remember that we legalized the flag.
6451 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6455 // If the target wants to custom expand this, let them.
6456 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6457 SDOperand New = TLI.LowerOperation(Op, DAG);
6459 ExpandOp(New, Lo, Hi);
6464 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6465 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6466 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6467 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6468 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6469 SDOperand LL, LH, RL, RH;
6470 ExpandOp(Node->getOperand(0), LL, LH);
6471 ExpandOp(Node->getOperand(1), RL, RH);
6472 unsigned OuterBitSize = Op.getValueSizeInBits();
6473 unsigned InnerBitSize = RH.getValueSizeInBits();
6474 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6475 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6476 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
6477 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
6478 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
6479 // The inputs are both zero-extended.
6481 // We can emit a umul_lohi.
6482 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6483 Hi = SDOperand(Lo.Val, 1);
6487 // We can emit a mulhu+mul.
6488 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6489 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6493 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6494 // The input values are both sign-extended.
6496 // We can emit a smul_lohi.
6497 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6498 Hi = SDOperand(Lo.Val, 1);
6502 // We can emit a mulhs+mul.
6503 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6504 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6509 // Lo,Hi = umul LHS, RHS.
6510 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6511 DAG.getVTList(NVT, NVT), LL, RL);
6513 Hi = UMulLOHI.getValue(1);
6514 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6515 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6516 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6517 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6521 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6522 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6523 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6524 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6525 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6526 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6531 // If nothing else, we can make a libcall.
6532 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
6536 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
6539 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
6542 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
6545 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
6549 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
6552 RTLIB::ADD_PPCF128),
6556 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
6559 RTLIB::SUB_PPCF128),
6563 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
6566 RTLIB::MUL_PPCF128),
6570 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
6573 RTLIB::DIV_PPCF128),
6576 case ISD::FP_EXTEND:
6577 if (VT == MVT::ppcf128) {
6578 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6579 Node->getOperand(0).getValueType()==MVT::f64);
6580 const uint64_t zero = 0;
6581 if (Node->getOperand(0).getValueType()==MVT::f32)
6582 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6584 Hi = Node->getOperand(0);
6585 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6588 Lo = ExpandLibCall(RTLIB::FPEXT_F32_F64, Node, true, Hi);
6591 Lo = ExpandLibCall(RTLIB::FPROUND_F64_F32, Node, true, Hi);
6594 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::POWI_F32,
6597 RTLIB::POWI_PPCF128),
6603 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6604 switch(Node->getOpcode()) {
6606 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6607 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6610 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6611 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6614 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6615 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6617 default: assert(0 && "Unreachable!");
6619 Lo = ExpandLibCall(LC, Node, false, Hi);
6623 if (VT == MVT::ppcf128) {
6625 ExpandOp(Node->getOperand(0), Lo, Tmp);
6626 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6627 // lo = hi==fabs(hi) ? lo : -lo;
6628 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6629 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6630 DAG.getCondCode(ISD::SETEQ));
6633 SDOperand Mask = (VT == MVT::f64)
6634 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6635 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6636 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6637 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6638 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6639 if (getTypeAction(NVT) == Expand)
6640 ExpandOp(Lo, Lo, Hi);
6644 if (VT == MVT::ppcf128) {
6645 ExpandOp(Node->getOperand(0), Lo, Hi);
6646 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6647 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6650 SDOperand Mask = (VT == MVT::f64)
6651 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6652 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6653 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6654 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6655 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6656 if (getTypeAction(NVT) == Expand)
6657 ExpandOp(Lo, Lo, Hi);
6660 case ISD::FCOPYSIGN: {
6661 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6662 if (getTypeAction(NVT) == Expand)
6663 ExpandOp(Lo, Lo, Hi);
6666 case ISD::SINT_TO_FP:
6667 case ISD::UINT_TO_FP: {
6668 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6669 MVT SrcVT = Node->getOperand(0).getValueType();
6671 // Promote the operand if needed. Do this before checking for
6672 // ppcf128 so conversions of i16 and i8 work.
6673 if (getTypeAction(SrcVT) == Promote) {
6674 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6676 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6677 DAG.getValueType(SrcVT))
6678 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6679 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6680 SrcVT = Node->getOperand(0).getValueType();
6683 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
6684 static const uint64_t zero = 0;
6686 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6687 Node->getOperand(0)));
6688 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6690 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6691 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6692 Node->getOperand(0)));
6693 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6694 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6695 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6696 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6697 DAG.getConstant(0, MVT::i32),
6698 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6700 APFloat(APInt(128, 2, TwoE32)),
6703 DAG.getCondCode(ISD::SETLT)),
6708 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6709 // si64->ppcf128 done by libcall, below
6710 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6711 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6713 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6714 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6715 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6716 DAG.getConstant(0, MVT::i64),
6717 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6719 APFloat(APInt(128, 2, TwoE64)),
6722 DAG.getCondCode(ISD::SETLT)),
6727 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6728 Node->getOperand(0));
6729 if (getTypeAction(Lo.getValueType()) == Expand)
6730 // float to i32 etc. can be 'expanded' to a single node.
6731 ExpandOp(Lo, Lo, Hi);
6736 // Make sure the resultant values have been legalized themselves, unless this
6737 // is a type that requires multi-step expansion.
6738 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6739 Lo = LegalizeOp(Lo);
6741 // Don't legalize the high part if it is expanded to a single node.
6742 Hi = LegalizeOp(Hi);
6745 // Remember in a map if the values will be reused later.
6747 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6748 assert(isNew && "Value already expanded?!?");
6751 /// SplitVectorOp - Given an operand of vector type, break it down into
6752 /// two smaller values, still of vector type.
6753 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6755 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
6756 SDNode *Node = Op.Val;
6757 unsigned NumElements = Op.getValueType().getVectorNumElements();
6758 assert(NumElements > 1 && "Cannot split a single element vector!");
6760 MVT NewEltVT = Op.getValueType().getVectorElementType();
6762 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6763 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6765 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
6766 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
6768 // See if we already split it.
6769 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6770 = SplitNodes.find(Op);
6771 if (I != SplitNodes.end()) {
6772 Lo = I->second.first;
6773 Hi = I->second.second;
6777 switch (Node->getOpcode()) {
6782 assert(0 && "Unhandled operation in SplitVectorOp!");
6784 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6785 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6787 case ISD::BUILD_PAIR:
6788 Lo = Node->getOperand(0);
6789 Hi = Node->getOperand(1);
6791 case ISD::INSERT_VECTOR_ELT: {
6792 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
6793 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6794 unsigned Index = Idx->getValue();
6795 SDOperand ScalarOp = Node->getOperand(1);
6796 if (Index < NewNumElts_Lo)
6797 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6798 DAG.getIntPtrConstant(Index));
6800 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6801 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
6804 SDOperand Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
6805 Node->getOperand(1),
6806 Node->getOperand(2));
6807 SplitVectorOp(Tmp, Lo, Hi);
6810 case ISD::VECTOR_SHUFFLE: {
6811 // Build the low part.
6812 SDOperand Mask = Node->getOperand(2);
6813 SmallVector<SDOperand, 8> Ops;
6814 MVT PtrVT = TLI.getPointerTy();
6816 // Insert all of the elements from the input that are needed. We use
6817 // buildvector of extractelement here because the input vectors will have
6818 // to be legalized, so this makes the code simpler.
6819 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6820 SDOperand IdxNode = Mask.getOperand(i);
6821 if (IdxNode.getOpcode() == ISD::UNDEF) {
6822 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6825 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6826 SDOperand InVec = Node->getOperand(0);
6827 if (Idx >= NumElements) {
6828 InVec = Node->getOperand(1);
6831 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6832 DAG.getConstant(Idx, PtrVT)));
6834 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6837 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6838 SDOperand IdxNode = Mask.getOperand(i);
6839 if (IdxNode.getOpcode() == ISD::UNDEF) {
6840 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6843 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6844 SDOperand InVec = Node->getOperand(0);
6845 if (Idx >= NumElements) {
6846 InVec = Node->getOperand(1);
6849 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6850 DAG.getConstant(Idx, PtrVT)));
6852 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6855 case ISD::BUILD_VECTOR: {
6856 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6857 Node->op_begin()+NewNumElts_Lo);
6858 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6860 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6862 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6865 case ISD::CONCAT_VECTORS: {
6866 // FIXME: Handle non-power-of-two vectors?
6867 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6868 if (NewNumSubvectors == 1) {
6869 Lo = Node->getOperand(0);
6870 Hi = Node->getOperand(1);
6872 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6873 Node->op_begin()+NewNumSubvectors);
6874 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6876 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6878 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6883 SDOperand Cond = Node->getOperand(0);
6885 SDOperand LL, LH, RL, RH;
6886 SplitVectorOp(Node->getOperand(1), LL, LH);
6887 SplitVectorOp(Node->getOperand(2), RL, RH);
6889 if (Cond.getValueType().isVector()) {
6890 // Handle a vector merge.
6892 SplitVectorOp(Cond, CL, CH);
6893 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6894 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6896 // Handle a simple select with vector operands.
6897 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6898 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6902 case ISD::SELECT_CC: {
6903 SDOperand CondLHS = Node->getOperand(0);
6904 SDOperand CondRHS = Node->getOperand(1);
6905 SDOperand CondCode = Node->getOperand(4);
6907 SDOperand LL, LH, RL, RH;
6908 SplitVectorOp(Node->getOperand(2), LL, LH);
6909 SplitVectorOp(Node->getOperand(3), RL, RH);
6911 // Handle a simple select with vector operands.
6912 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
6914 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
6919 SDOperand LL, LH, RL, RH;
6920 SplitVectorOp(Node->getOperand(0), LL, LH);
6921 SplitVectorOp(Node->getOperand(1), RL, RH);
6922 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
6923 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
6942 SDOperand LL, LH, RL, RH;
6943 SplitVectorOp(Node->getOperand(0), LL, LH);
6944 SplitVectorOp(Node->getOperand(1), RL, RH);
6946 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6947 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6952 SplitVectorOp(Node->getOperand(0), L, H);
6954 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6955 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6966 case ISD::FP_TO_SINT:
6967 case ISD::FP_TO_UINT:
6968 case ISD::SINT_TO_FP:
6969 case ISD::UINT_TO_FP: {
6971 SplitVectorOp(Node->getOperand(0), L, H);
6973 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6974 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6978 LoadSDNode *LD = cast<LoadSDNode>(Node);
6979 SDOperand Ch = LD->getChain();
6980 SDOperand Ptr = LD->getBasePtr();
6981 const Value *SV = LD->getSrcValue();
6982 int SVOffset = LD->getSrcValueOffset();
6983 unsigned Alignment = LD->getAlignment();
6984 bool isVolatile = LD->isVolatile();
6986 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6987 unsigned IncrementSize = NewNumElts_Lo * NewEltVT.getSizeInBits()/8;
6988 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6989 DAG.getIntPtrConstant(IncrementSize));
6990 SVOffset += IncrementSize;
6991 Alignment = MinAlign(Alignment, IncrementSize);
6992 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6994 // Build a factor node to remember that this load is independent of the
6996 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6999 // Remember that we legalized the chain.
7000 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7003 case ISD::BIT_CONVERT: {
7004 // We know the result is a vector. The input may be either a vector or a
7006 SDOperand InOp = Node->getOperand(0);
7007 if (!InOp.getValueType().isVector() ||
7008 InOp.getValueType().getVectorNumElements() == 1) {
7009 // The input is a scalar or single-element vector.
7010 // Lower to a store/load so that it can be split.
7011 // FIXME: this could be improved probably.
7012 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
7013 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val);
7015 SDOperand St = DAG.getStore(DAG.getEntryNode(),
7017 PseudoSourceValue::getFixedStack(),
7019 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
7020 PseudoSourceValue::getFixedStack(),
7023 // Split the vector and convert each of the pieces now.
7024 SplitVectorOp(InOp, Lo, Hi);
7025 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
7026 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
7031 // Remember in a map if the values will be reused later.
7033 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7034 assert(isNew && "Value already split?!?");
7038 /// ScalarizeVectorOp - Given an operand of single-element vector type
7039 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7040 /// scalar (e.g. f32) value.
7041 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
7042 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7043 SDNode *Node = Op.Val;
7044 MVT NewVT = Op.getValueType().getVectorElementType();
7045 assert(Op.getValueType().getVectorNumElements() == 1);
7047 // See if we already scalarized it.
7048 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
7049 if (I != ScalarizedNodes.end()) return I->second;
7052 switch (Node->getOpcode()) {
7055 Node->dump(&DAG); cerr << "\n";
7057 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7074 Result = DAG.getNode(Node->getOpcode(),
7076 ScalarizeVectorOp(Node->getOperand(0)),
7077 ScalarizeVectorOp(Node->getOperand(1)));
7084 Result = DAG.getNode(Node->getOpcode(),
7086 ScalarizeVectorOp(Node->getOperand(0)));
7089 Result = DAG.getNode(Node->getOpcode(),
7091 ScalarizeVectorOp(Node->getOperand(0)),
7092 Node->getOperand(1));
7095 LoadSDNode *LD = cast<LoadSDNode>(Node);
7096 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7097 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7099 const Value *SV = LD->getSrcValue();
7100 int SVOffset = LD->getSrcValueOffset();
7101 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
7102 LD->isVolatile(), LD->getAlignment());
7104 // Remember that we legalized the chain.
7105 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7108 case ISD::BUILD_VECTOR:
7109 Result = Node->getOperand(0);
7111 case ISD::INSERT_VECTOR_ELT:
7112 // Returning the inserted scalar element.
7113 Result = Node->getOperand(1);
7115 case ISD::CONCAT_VECTORS:
7116 assert(Node->getOperand(0).getValueType() == NewVT &&
7117 "Concat of non-legal vectors not yet supported!");
7118 Result = Node->getOperand(0);
7120 case ISD::VECTOR_SHUFFLE: {
7121 // Figure out if the scalar is the LHS or RHS and return it.
7122 SDOperand EltNum = Node->getOperand(2).getOperand(0);
7123 if (cast<ConstantSDNode>(EltNum)->getValue())
7124 Result = ScalarizeVectorOp(Node->getOperand(1));
7126 Result = ScalarizeVectorOp(Node->getOperand(0));
7129 case ISD::EXTRACT_SUBVECTOR:
7130 Result = Node->getOperand(0);
7131 assert(Result.getValueType() == NewVT);
7133 case ISD::BIT_CONVERT: {
7134 SDOperand Op0 = Op.getOperand(0);
7135 if (Op0.getValueType().getVectorNumElements() == 1)
7136 Op0 = ScalarizeVectorOp(Op0);
7137 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7141 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7142 ScalarizeVectorOp(Op.getOperand(1)),
7143 ScalarizeVectorOp(Op.getOperand(2)));
7145 case ISD::SELECT_CC:
7146 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
7147 Node->getOperand(1),
7148 ScalarizeVectorOp(Op.getOperand(2)),
7149 ScalarizeVectorOp(Op.getOperand(3)),
7150 Node->getOperand(4));
7153 SDOperand Op0 = ScalarizeVectorOp(Op.getOperand(0));
7154 SDOperand Op1 = ScalarizeVectorOp(Op.getOperand(1));
7155 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
7157 Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7158 DAG.getConstant(-1ULL, NewVT),
7159 DAG.getConstant(0ULL, NewVT));
7164 if (TLI.isTypeLegal(NewVT))
7165 Result = LegalizeOp(Result);
7166 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7167 assert(isNew && "Value already scalarized?");
7172 // SelectionDAG::Legalize - This is the entry point for the file.
7174 void SelectionDAG::Legalize() {
7175 if (ViewLegalizeDAGs) viewGraph();
7177 /// run - This is the main entry point to this class.
7179 SelectionDAGLegalize(*this).LegalizeDAG();