1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/Target/TargetFrameInfo.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetData.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/CallingConv.h"
25 #include "llvm/Constants.h"
26 #include "llvm/DerivedTypes.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/ADT/SmallPtrSet.h"
38 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
39 cl::desc("Pop up a window to show dags before legalize"));
41 static const bool ViewLegalizeDAGs = 0;
44 //===----------------------------------------------------------------------===//
45 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
46 /// hacks on it until the target machine can handle it. This involves
47 /// eliminating value sizes the machine cannot handle (promoting small sizes to
48 /// large sizes or splitting up large values into small values) as well as
49 /// eliminating operations the machine cannot handle.
51 /// This code also does a small amount of optimization and recognition of idioms
52 /// as part of its processing. For example, if a target does not support a
53 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
54 /// will attempt merge setcc and brc instructions into brcc's.
57 class VISIBILITY_HIDDEN SelectionDAGLegalize {
61 // Libcall insertion helpers.
63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
64 /// legalized. We use this to ensure that calls are properly serialized
65 /// against each other, including inserted libcalls.
66 SDOperand LastCALLSEQ_END;
68 /// IsLegalizingCall - This member is used *only* for purposes of providing
69 /// helpful assertions that a libcall isn't created while another call is
70 /// being legalized (which could lead to non-serialized call sequences).
71 bool IsLegalizingCall;
74 Legal, // The target natively supports this operation.
75 Promote, // This operation should be executed in a larger type.
76 Expand // Try to expand this to other ops, otherwise use a libcall.
79 /// ValueTypeActions - This is a bitvector that contains two bits for each
80 /// value type, where the two bits correspond to the LegalizeAction enum.
81 /// This can be queried with "getTypeAction(VT)".
82 TargetLowering::ValueTypeActionImpl ValueTypeActions;
84 /// LegalizedNodes - For nodes that are of legal width, and that have more
85 /// than one use, this map indicates what regularized operand to use. This
86 /// allows us to avoid legalizing the same thing more than once.
87 DenseMap<SDOperand, SDOperand> LegalizedNodes;
89 /// PromotedNodes - For nodes that are below legal width, and that have more
90 /// than one use, this map indicates what promoted value to use. This allows
91 /// us to avoid promoting the same thing more than once.
92 DenseMap<SDOperand, SDOperand> PromotedNodes;
94 /// ExpandedNodes - For nodes that need to be expanded this map indicates
95 /// which which operands are the expanded version of the input. This allows
96 /// us to avoid expanding the same node more than once.
97 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
99 /// SplitNodes - For vector nodes that need to be split, this map indicates
100 /// which which operands are the split version of the input. This allows us
101 /// to avoid splitting the same node more than once.
102 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
104 /// ScalarizedNodes - For nodes that need to be converted from vector types to
105 /// scalar types, this contains the mapping of ones we have already
106 /// processed to the result.
107 std::map<SDOperand, SDOperand> ScalarizedNodes;
109 void AddLegalizedOperand(SDOperand From, SDOperand To) {
110 LegalizedNodes.insert(std::make_pair(From, To));
111 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
115 void AddPromotedOperand(SDOperand From, SDOperand To) {
116 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
117 assert(isNew && "Got into the map somehow?");
118 // If someone requests legalization of the new node, return itself.
119 LegalizedNodes.insert(std::make_pair(To, To));
124 SelectionDAGLegalize(SelectionDAG &DAG);
126 /// getTypeAction - Return how we should legalize values of this type, either
127 /// it is already legal or we need to expand it into multiple registers of
128 /// smaller integer type, or we need to promote it to a larger type.
129 LegalizeAction getTypeAction(MVT::ValueType VT) const {
130 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
133 /// isTypeLegal - Return true if this type is legal on this target.
135 bool isTypeLegal(MVT::ValueType VT) const {
136 return getTypeAction(VT) == Legal;
142 /// HandleOp - Legalize, Promote, or Expand the specified operand as
143 /// appropriate for its type.
144 void HandleOp(SDOperand Op);
146 /// LegalizeOp - We know that the specified value has a legal type.
147 /// Recursively ensure that the operands have legal types, then return the
149 SDOperand LegalizeOp(SDOperand O);
151 /// UnrollVectorOp - We know that the given vector has a legal type, however
152 /// the operation it performs is not legal and is an operation that we have
153 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
154 /// operating on each element individually.
155 SDOperand UnrollVectorOp(SDOperand O);
157 /// PromoteOp - Given an operation that produces a value in an invalid type,
158 /// promote it to compute the value into a larger type. The produced value
159 /// will have the correct bits for the low portion of the register, but no
160 /// guarantee is made about the top bits: it may be zero, sign-extended, or
162 SDOperand PromoteOp(SDOperand O);
164 /// ExpandOp - Expand the specified SDOperand into its two component pieces
165 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
166 /// the LegalizeNodes map is filled in for any results that are not expanded,
167 /// the ExpandedNodes map is filled in for any results that are expanded, and
168 /// the Lo/Hi values are returned. This applies to integer types and Vector
170 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
172 /// SplitVectorOp - Given an operand of vector type, break it down into
173 /// two smaller values.
174 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
176 /// ScalarizeVectorOp - Given an operand of single-element vector type
177 /// (e.g. v1f32), convert it into the equivalent operation that returns a
178 /// scalar (e.g. f32) value.
179 SDOperand ScalarizeVectorOp(SDOperand O);
181 /// isShuffleLegal - Return true if a vector shuffle is legal with the
182 /// specified mask and type. Targets can specify exactly which masks they
183 /// support and the code generator is tasked with not creating illegal masks.
185 /// Note that this will also return true for shuffles that are promoted to a
188 /// If this is a legal shuffle, this method returns the (possibly promoted)
189 /// build_vector Mask. If it's not a legal shuffle, it returns null.
190 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
192 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
193 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
195 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
197 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
199 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
202 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT,
203 MVT::ValueType DestVT);
204 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
205 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
206 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
208 MVT::ValueType DestVT);
209 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
211 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
214 SDOperand ExpandBSWAP(SDOperand Op);
215 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
216 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
217 SDOperand &Lo, SDOperand &Hi);
218 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
219 SDOperand &Lo, SDOperand &Hi);
221 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
222 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
226 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
227 /// specified mask and type. Targets can specify exactly which masks they
228 /// support and the code generator is tasked with not creating illegal masks.
230 /// Note that this will also return true for shuffles that are promoted to a
232 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
233 SDOperand Mask) const {
234 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
236 case TargetLowering::Legal:
237 case TargetLowering::Custom:
239 case TargetLowering::Promote: {
240 // If this is promoted to a different type, convert the shuffle mask and
241 // ask if it is legal in the promoted type!
242 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
244 // If we changed # elements, change the shuffle mask.
245 unsigned NumEltsGrowth =
246 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
247 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
248 if (NumEltsGrowth > 1) {
249 // Renumber the elements.
250 SmallVector<SDOperand, 8> Ops;
251 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
252 SDOperand InOp = Mask.getOperand(i);
253 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
254 if (InOp.getOpcode() == ISD::UNDEF)
255 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
257 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
258 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
262 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
268 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
271 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
272 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
273 ValueTypeActions(TLI.getValueTypeActions()) {
274 assert(MVT::LAST_VALUETYPE <= 32 &&
275 "Too many value types for ValueTypeActions to hold!");
278 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
279 /// contains all of a nodes operands before it contains the node.
280 static void ComputeTopDownOrdering(SelectionDAG &DAG,
281 SmallVector<SDNode*, 64> &Order) {
283 DenseMap<SDNode*, unsigned> Visited;
284 std::vector<SDNode*> Worklist;
285 Worklist.reserve(128);
287 // Compute ordering from all of the leaves in the graphs, those (like the
288 // entry node) that have no operands.
289 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
290 E = DAG.allnodes_end(); I != E; ++I) {
291 if (I->getNumOperands() == 0) {
293 Worklist.push_back(I);
297 while (!Worklist.empty()) {
298 SDNode *N = Worklist.back();
301 if (++Visited[N] != N->getNumOperands())
302 continue; // Haven't visited all operands yet
306 // Now that we have N in, add anything that uses it if all of their operands
308 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
310 Worklist.push_back(*UI);
313 assert(Order.size() == Visited.size() &&
315 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
316 "Error: DAG is cyclic!");
320 void SelectionDAGLegalize::LegalizeDAG() {
321 LastCALLSEQ_END = DAG.getEntryNode();
322 IsLegalizingCall = false;
324 // The legalize process is inherently a bottom-up recursive process (users
325 // legalize their uses before themselves). Given infinite stack space, we
326 // could just start legalizing on the root and traverse the whole graph. In
327 // practice however, this causes us to run out of stack space on large basic
328 // blocks. To avoid this problem, compute an ordering of the nodes where each
329 // node is only legalized after all of its operands are legalized.
330 SmallVector<SDNode*, 64> Order;
331 ComputeTopDownOrdering(DAG, Order);
333 for (unsigned i = 0, e = Order.size(); i != e; ++i)
334 HandleOp(SDOperand(Order[i], 0));
336 // Finally, it's possible the root changed. Get the new root.
337 SDOperand OldRoot = DAG.getRoot();
338 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
339 DAG.setRoot(LegalizedNodes[OldRoot]);
341 ExpandedNodes.clear();
342 LegalizedNodes.clear();
343 PromotedNodes.clear();
345 ScalarizedNodes.clear();
347 // Remove dead nodes now.
348 DAG.RemoveDeadNodes();
352 /// FindCallEndFromCallStart - Given a chained node that is part of a call
353 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
354 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
355 if (Node->getOpcode() == ISD::CALLSEQ_END)
357 if (Node->use_empty())
358 return 0; // No CallSeqEnd
360 // The chain is usually at the end.
361 SDOperand TheChain(Node, Node->getNumValues()-1);
362 if (TheChain.getValueType() != MVT::Other) {
363 // Sometimes it's at the beginning.
364 TheChain = SDOperand(Node, 0);
365 if (TheChain.getValueType() != MVT::Other) {
366 // Otherwise, hunt for it.
367 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
368 if (Node->getValueType(i) == MVT::Other) {
369 TheChain = SDOperand(Node, i);
373 // Otherwise, we walked into a node without a chain.
374 if (TheChain.getValueType() != MVT::Other)
379 for (SDNode::use_iterator UI = Node->use_begin(),
380 E = Node->use_end(); UI != E; ++UI) {
382 // Make sure to only follow users of our token chain.
384 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
385 if (User->getOperand(i) == TheChain)
386 if (SDNode *Result = FindCallEndFromCallStart(User))
392 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
393 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
394 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
395 assert(Node && "Didn't find callseq_start for a call??");
396 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
398 assert(Node->getOperand(0).getValueType() == MVT::Other &&
399 "Node doesn't have a token chain argument!");
400 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
403 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
404 /// see if any uses can reach Dest. If no dest operands can get to dest,
405 /// legalize them, legalize ourself, and return false, otherwise, return true.
407 /// Keep track of the nodes we fine that actually do lead to Dest in
408 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
410 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
411 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
412 if (N == Dest) return true; // N certainly leads to Dest :)
414 // If we've already processed this node and it does lead to Dest, there is no
415 // need to reprocess it.
416 if (NodesLeadingTo.count(N)) return true;
418 // If the first result of this node has been already legalized, then it cannot
420 switch (getTypeAction(N->getValueType(0))) {
422 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
425 if (PromotedNodes.count(SDOperand(N, 0))) return false;
428 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
432 // Okay, this node has not already been legalized. Check and legalize all
433 // operands. If none lead to Dest, then we can legalize this node.
434 bool OperandsLeadToDest = false;
435 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
436 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
437 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
439 if (OperandsLeadToDest) {
440 NodesLeadingTo.insert(N);
444 // Okay, this node looks safe, legalize it and return false.
445 HandleOp(SDOperand(N, 0));
449 /// HandleOp - Legalize, Promote, or Expand the specified operand as
450 /// appropriate for its type.
451 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
452 MVT::ValueType VT = Op.getValueType();
453 switch (getTypeAction(VT)) {
454 default: assert(0 && "Bad type action!");
455 case Legal: (void)LegalizeOp(Op); break;
456 case Promote: (void)PromoteOp(Op); break;
458 if (!MVT::isVector(VT)) {
459 // If this is an illegal scalar, expand it into its two component
462 if (Op.getOpcode() == ISD::TargetConstant)
463 break; // Allow illegal target nodes.
465 } else if (MVT::getVectorNumElements(VT) == 1) {
466 // If this is an illegal single element vector, convert it to a
468 (void)ScalarizeVectorOp(Op);
470 // Otherwise, this is an illegal multiple element vector.
471 // Split it in half and legalize both parts.
473 SplitVectorOp(Op, X, Y);
479 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
480 /// a load from the constant pool.
481 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
482 SelectionDAG &DAG, TargetLowering &TLI) {
485 // If a FP immediate is precise when represented as a float and if the
486 // target can do an extending load from float to double, we put it into
487 // the constant pool as a float, even if it's is statically typed as a
489 MVT::ValueType VT = CFP->getValueType(0);
490 bool isDouble = VT == MVT::f64;
491 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
494 if (VT!=MVT::f64 && VT!=MVT::f32)
495 assert(0 && "Invalid type expansion");
496 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(),
497 isDouble ? MVT::i64 : MVT::i32);
500 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) &&
501 // Only do this if the target has a native EXTLOAD instruction from f32.
502 // Do not try to be clever about long doubles (so far)
503 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
504 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
509 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
511 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
512 CPIdx, NULL, 0, MVT::f32);
514 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
519 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
522 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
523 SelectionDAG &DAG, TargetLowering &TLI) {
524 MVT::ValueType VT = Node->getValueType(0);
525 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
526 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
527 "fcopysign expansion only supported for f32 and f64");
528 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
530 // First get the sign bit of second operand.
531 SDOperand Mask1 = (SrcVT == MVT::f64)
532 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
533 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
534 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
535 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
536 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
537 // Shift right or sign-extend it if the two operands have different types.
538 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
540 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
541 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
542 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
543 } else if (SizeDiff < 0)
544 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
546 // Clear the sign bit of first operand.
547 SDOperand Mask2 = (VT == MVT::f64)
548 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
549 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
550 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
551 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
552 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
554 // Or the value with the sign bit.
555 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
559 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
561 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
562 TargetLowering &TLI) {
563 SDOperand Chain = ST->getChain();
564 SDOperand Ptr = ST->getBasePtr();
565 SDOperand Val = ST->getValue();
566 MVT::ValueType VT = Val.getValueType();
567 int Alignment = ST->getAlignment();
568 int SVOffset = ST->getSrcValueOffset();
569 if (MVT::isFloatingPoint(ST->getMemoryVT())) {
570 // Expand to a bitconvert of the value to the integer type of the
571 // same size, then a (misaligned) int store.
572 MVT::ValueType intVT;
575 else if (VT==MVT::f32)
578 assert(0 && "Unaligned load of unsupported floating point type");
580 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
581 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
582 SVOffset, ST->isVolatile(), Alignment);
584 assert(MVT::isInteger(ST->getMemoryVT()) &&
585 "Unaligned store of unknown type.");
586 // Get the half-size VT
587 MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1;
588 int NumBits = MVT::getSizeInBits(NewStoredVT);
589 int IncrementSize = NumBits / 8;
591 // Divide the stored value in two parts.
592 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
594 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
596 // Store the two parts
597 SDOperand Store1, Store2;
598 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
599 ST->getSrcValue(), SVOffset, NewStoredVT,
600 ST->isVolatile(), Alignment);
601 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
602 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
603 Alignment = MinAlign(Alignment, IncrementSize);
604 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
605 ST->getSrcValue(), SVOffset + IncrementSize,
606 NewStoredVT, ST->isVolatile(), Alignment);
608 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
611 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
613 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
614 TargetLowering &TLI) {
615 int SVOffset = LD->getSrcValueOffset();
616 SDOperand Chain = LD->getChain();
617 SDOperand Ptr = LD->getBasePtr();
618 MVT::ValueType VT = LD->getValueType(0);
619 MVT::ValueType LoadedVT = LD->getMemoryVT();
620 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT)) {
621 // Expand to a (misaligned) integer load of the same size,
622 // then bitconvert to floating point.
623 MVT::ValueType intVT;
624 if (LoadedVT == MVT::f64)
626 else if (LoadedVT == MVT::f32)
629 assert(0 && "Unaligned load of unsupported floating point type");
631 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
632 SVOffset, LD->isVolatile(),
634 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
636 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
638 SDOperand Ops[] = { Result, Chain };
639 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
642 assert((MVT::isInteger(LoadedVT) || MVT::isVector(LoadedVT)) &&
643 "Unaligned load of unsupported type.");
645 // Compute the new VT that is half the size of the old one. We either have an
646 // integer MVT or we have a vector MVT.
647 unsigned NumBits = MVT::getSizeInBits(LoadedVT);
648 MVT::ValueType NewLoadedVT;
649 if (!MVT::isVector(LoadedVT)) {
650 NewLoadedVT = MVT::getIntegerType(NumBits/2);
652 // FIXME: This is not right for <1 x anything> it is also not right for
653 // non-power-of-two vectors.
654 NewLoadedVT = MVT::getVectorType(MVT::getVectorElementType(LoadedVT),
655 MVT::getVectorNumElements(LoadedVT)/2);
659 unsigned Alignment = LD->getAlignment();
660 unsigned IncrementSize = NumBits / 8;
661 ISD::LoadExtType HiExtType = LD->getExtensionType();
663 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
664 if (HiExtType == ISD::NON_EXTLOAD)
665 HiExtType = ISD::ZEXTLOAD;
667 // Load the value in two parts
669 if (TLI.isLittleEndian()) {
670 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
671 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
672 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
673 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
674 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
675 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
676 MinAlign(Alignment, IncrementSize));
678 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
679 NewLoadedVT,LD->isVolatile(), Alignment);
680 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
681 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
682 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
683 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
684 MinAlign(Alignment, IncrementSize));
687 // aggregate the two parts
688 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
689 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
690 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
692 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
695 SDOperand Ops[] = { Result, TF };
696 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
699 /// UnrollVectorOp - We know that the given vector has a legal type, however
700 /// the operation it performs is not legal and is an operation that we have
701 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
702 /// operating on each element individually.
703 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
704 MVT::ValueType VT = Op.getValueType();
705 assert(isTypeLegal(VT) &&
706 "Caller should expand or promote operands that are not legal!");
707 assert(Op.Val->getNumValues() == 1 &&
708 "Can't unroll a vector with multiple results!");
709 unsigned NE = MVT::getVectorNumElements(VT);
710 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
712 SmallVector<SDOperand, 8> Scalars;
713 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
714 for (unsigned i = 0; i != NE; ++i) {
715 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
716 SDOperand Operand = Op.getOperand(j);
717 MVT::ValueType OperandVT = Operand.getValueType();
718 if (MVT::isVector(OperandVT)) {
719 // A vector operand; extract a single element.
720 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
721 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
724 DAG.getConstant(i, MVT::i32));
726 // A scalar operand; just use it as is.
727 Operands[j] = Operand;
730 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
731 &Operands[0], Operands.size()));
734 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
737 /// GetFPLibCall - Return the right libcall for the given floating point type.
738 static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
739 RTLIB::Libcall Call_F32,
740 RTLIB::Libcall Call_F64,
741 RTLIB::Libcall Call_F80,
742 RTLIB::Libcall Call_PPCF128) {
744 VT == MVT::f32 ? Call_F32 :
745 VT == MVT::f64 ? Call_F64 :
746 VT == MVT::f80 ? Call_F80 :
747 VT == MVT::ppcf128 ? Call_PPCF128 :
748 RTLIB::UNKNOWN_LIBCALL;
751 /// LegalizeOp - We know that the specified value has a legal type, and
752 /// that its operands are legal. Now ensure that the operation itself
753 /// is legal, recursively ensuring that the operands' operations remain
755 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
756 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
759 assert(isTypeLegal(Op.getValueType()) &&
760 "Caller should expand or promote operands that are not legal!");
761 SDNode *Node = Op.Val;
763 // If this operation defines any values that cannot be represented in a
764 // register on this target, make sure to expand or promote them.
765 if (Node->getNumValues() > 1) {
766 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
767 if (getTypeAction(Node->getValueType(i)) != Legal) {
768 HandleOp(Op.getValue(i));
769 assert(LegalizedNodes.count(Op) &&
770 "Handling didn't add legal operands!");
771 return LegalizedNodes[Op];
775 // Note that LegalizeOp may be reentered even from single-use nodes, which
776 // means that we always must cache transformed nodes.
777 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
778 if (I != LegalizedNodes.end()) return I->second;
780 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
781 SDOperand Result = Op;
782 bool isCustom = false;
784 switch (Node->getOpcode()) {
785 case ISD::FrameIndex:
786 case ISD::EntryToken:
788 case ISD::BasicBlock:
789 case ISD::TargetFrameIndex:
790 case ISD::TargetJumpTable:
791 case ISD::TargetConstant:
792 case ISD::TargetConstantFP:
793 case ISD::TargetConstantPool:
794 case ISD::TargetGlobalAddress:
795 case ISD::TargetGlobalTLSAddress:
796 case ISD::TargetExternalSymbol:
801 // Primitives must all be legal.
802 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
803 "This must be legal!");
806 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
807 // If this is a target node, legalize it by legalizing the operands then
808 // passing it through.
809 SmallVector<SDOperand, 8> Ops;
810 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
811 Ops.push_back(LegalizeOp(Node->getOperand(i)));
813 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
815 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
816 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
817 return Result.getValue(Op.ResNo);
819 // Otherwise this is an unhandled builtin node. splat.
821 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
823 assert(0 && "Do not know how to legalize this operator!");
825 case ISD::GLOBAL_OFFSET_TABLE:
826 case ISD::GlobalAddress:
827 case ISD::GlobalTLSAddress:
828 case ISD::ExternalSymbol:
829 case ISD::ConstantPool:
830 case ISD::JumpTable: // Nothing to do.
831 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
832 default: assert(0 && "This action is not supported yet!");
833 case TargetLowering::Custom:
834 Tmp1 = TLI.LowerOperation(Op, DAG);
835 if (Tmp1.Val) Result = Tmp1;
836 // FALLTHROUGH if the target doesn't want to lower this op after all.
837 case TargetLowering::Legal:
842 case ISD::RETURNADDR:
843 // The only option for these nodes is to custom lower them. If the target
844 // does not custom lower them, then return zero.
845 Tmp1 = TLI.LowerOperation(Op, DAG);
849 Result = DAG.getConstant(0, TLI.getPointerTy());
851 case ISD::FRAME_TO_ARGS_OFFSET: {
852 MVT::ValueType VT = Node->getValueType(0);
853 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
854 default: assert(0 && "This action is not supported yet!");
855 case TargetLowering::Custom:
856 Result = TLI.LowerOperation(Op, DAG);
857 if (Result.Val) break;
859 case TargetLowering::Legal:
860 Result = DAG.getConstant(0, VT);
865 case ISD::EXCEPTIONADDR: {
866 Tmp1 = LegalizeOp(Node->getOperand(0));
867 MVT::ValueType VT = Node->getValueType(0);
868 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
869 default: assert(0 && "This action is not supported yet!");
870 case TargetLowering::Expand: {
871 unsigned Reg = TLI.getExceptionAddressRegister();
872 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
875 case TargetLowering::Custom:
876 Result = TLI.LowerOperation(Op, DAG);
877 if (Result.Val) break;
879 case TargetLowering::Legal: {
880 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
881 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
887 if (Result.Val->getNumValues() == 1) break;
889 assert(Result.Val->getNumValues() == 2 &&
890 "Cannot return more than two values!");
892 // Since we produced two values, make sure to remember that we
893 // legalized both of them.
894 Tmp1 = LegalizeOp(Result);
895 Tmp2 = LegalizeOp(Result.getValue(1));
896 AddLegalizedOperand(Op.getValue(0), Tmp1);
897 AddLegalizedOperand(Op.getValue(1), Tmp2);
898 return Op.ResNo ? Tmp2 : Tmp1;
899 case ISD::EHSELECTION: {
900 Tmp1 = LegalizeOp(Node->getOperand(0));
901 Tmp2 = LegalizeOp(Node->getOperand(1));
902 MVT::ValueType VT = Node->getValueType(0);
903 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
904 default: assert(0 && "This action is not supported yet!");
905 case TargetLowering::Expand: {
906 unsigned Reg = TLI.getExceptionSelectorRegister();
907 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
910 case TargetLowering::Custom:
911 Result = TLI.LowerOperation(Op, DAG);
912 if (Result.Val) break;
914 case TargetLowering::Legal: {
915 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
916 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
922 if (Result.Val->getNumValues() == 1) break;
924 assert(Result.Val->getNumValues() == 2 &&
925 "Cannot return more than two values!");
927 // Since we produced two values, make sure to remember that we
928 // legalized both of them.
929 Tmp1 = LegalizeOp(Result);
930 Tmp2 = LegalizeOp(Result.getValue(1));
931 AddLegalizedOperand(Op.getValue(0), Tmp1);
932 AddLegalizedOperand(Op.getValue(1), Tmp2);
933 return Op.ResNo ? Tmp2 : Tmp1;
934 case ISD::EH_RETURN: {
935 MVT::ValueType VT = Node->getValueType(0);
936 // The only "good" option for this node is to custom lower it.
937 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
938 default: assert(0 && "This action is not supported at all!");
939 case TargetLowering::Custom:
940 Result = TLI.LowerOperation(Op, DAG);
941 if (Result.Val) break;
943 case TargetLowering::Legal:
944 // Target does not know, how to lower this, lower to noop
945 Result = LegalizeOp(Node->getOperand(0));
950 case ISD::AssertSext:
951 case ISD::AssertZext:
952 Tmp1 = LegalizeOp(Node->getOperand(0));
953 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
955 case ISD::MERGE_VALUES:
956 // Legalize eliminates MERGE_VALUES nodes.
957 Result = Node->getOperand(Op.ResNo);
959 case ISD::CopyFromReg:
960 Tmp1 = LegalizeOp(Node->getOperand(0));
961 Result = Op.getValue(0);
962 if (Node->getNumValues() == 2) {
963 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
965 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
966 if (Node->getNumOperands() == 3) {
967 Tmp2 = LegalizeOp(Node->getOperand(2));
968 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
970 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
972 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
974 // Since CopyFromReg produces two values, make sure to remember that we
975 // legalized both of them.
976 AddLegalizedOperand(Op.getValue(0), Result);
977 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
978 return Result.getValue(Op.ResNo);
980 MVT::ValueType VT = Op.getValueType();
981 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
982 default: assert(0 && "This action is not supported yet!");
983 case TargetLowering::Expand:
984 if (MVT::isInteger(VT))
985 Result = DAG.getConstant(0, VT);
986 else if (MVT::isFloatingPoint(VT))
987 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
990 assert(0 && "Unknown value type!");
992 case TargetLowering::Legal:
998 case ISD::INTRINSIC_W_CHAIN:
999 case ISD::INTRINSIC_WO_CHAIN:
1000 case ISD::INTRINSIC_VOID: {
1001 SmallVector<SDOperand, 8> Ops;
1002 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1003 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1004 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1006 // Allow the target to custom lower its intrinsics if it wants to.
1007 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1008 TargetLowering::Custom) {
1009 Tmp3 = TLI.LowerOperation(Result, DAG);
1010 if (Tmp3.Val) Result = Tmp3;
1013 if (Result.Val->getNumValues() == 1) break;
1015 // Must have return value and chain result.
1016 assert(Result.Val->getNumValues() == 2 &&
1017 "Cannot return more than two values!");
1019 // Since loads produce two values, make sure to remember that we
1020 // legalized both of them.
1021 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1022 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1023 return Result.getValue(Op.ResNo);
1027 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
1028 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1030 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
1031 case TargetLowering::Promote:
1032 default: assert(0 && "This action is not supported yet!");
1033 case TargetLowering::Expand: {
1034 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1035 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1036 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
1038 if (MMI && (useDEBUG_LOC || useLABEL)) {
1039 const std::string &FName =
1040 cast<StringSDNode>(Node->getOperand(3))->getValue();
1041 const std::string &DirName =
1042 cast<StringSDNode>(Node->getOperand(4))->getValue();
1043 unsigned SrcFile = MMI->RecordSource(DirName, FName);
1045 SmallVector<SDOperand, 8> Ops;
1046 Ops.push_back(Tmp1); // chain
1047 SDOperand LineOp = Node->getOperand(1);
1048 SDOperand ColOp = Node->getOperand(2);
1051 Ops.push_back(LineOp); // line #
1052 Ops.push_back(ColOp); // col #
1053 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1054 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1056 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
1057 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
1058 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
1059 Ops.push_back(DAG.getConstant(ID, MVT::i32));
1060 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
1063 Result = Tmp1; // chain
1067 case TargetLowering::Legal:
1068 if (Tmp1 != Node->getOperand(0) ||
1069 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1070 SmallVector<SDOperand, 8> Ops;
1071 Ops.push_back(Tmp1);
1072 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1073 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1074 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1076 // Otherwise promote them.
1077 Ops.push_back(PromoteOp(Node->getOperand(1)));
1078 Ops.push_back(PromoteOp(Node->getOperand(2)));
1080 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1081 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1082 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1088 case ISD::DEBUG_LOC:
1089 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1090 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1091 default: assert(0 && "This action is not supported yet!");
1092 case TargetLowering::Legal:
1093 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1094 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1095 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1096 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1097 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1103 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
1104 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1105 default: assert(0 && "This action is not supported yet!");
1106 case TargetLowering::Legal:
1107 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1108 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1109 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1111 case TargetLowering::Expand:
1112 Result = LegalizeOp(Node->getOperand(0));
1117 case ISD::Constant: {
1118 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1120 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1122 // We know we don't need to expand constants here, constants only have one
1123 // value and we check that it is fine above.
1125 if (opAction == TargetLowering::Custom) {
1126 Tmp1 = TLI.LowerOperation(Result, DAG);
1132 case ISD::ConstantFP: {
1133 // Spill FP immediates to the constant pool if the target cannot directly
1134 // codegen them. Targets often have some immediate values that can be
1135 // efficiently generated into an FP register without a load. We explicitly
1136 // leave these constants as ConstantFP nodes for the target to deal with.
1137 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1139 // Check to see if this FP immediate is already legal.
1140 bool isLegal = false;
1141 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1142 E = TLI.legal_fpimm_end(); I != E; ++I)
1143 if (CFP->isExactlyValue(*I)) {
1148 // If this is a legal constant, turn it into a TargetConstantFP node.
1150 Result = DAG.getTargetConstantFP(CFP->getValueAPF(),
1151 CFP->getValueType(0));
1155 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1156 default: assert(0 && "This action is not supported yet!");
1157 case TargetLowering::Custom:
1158 Tmp3 = TLI.LowerOperation(Result, DAG);
1164 case TargetLowering::Expand:
1165 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1169 case ISD::TokenFactor:
1170 if (Node->getNumOperands() == 2) {
1171 Tmp1 = LegalizeOp(Node->getOperand(0));
1172 Tmp2 = LegalizeOp(Node->getOperand(1));
1173 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1174 } else if (Node->getNumOperands() == 3) {
1175 Tmp1 = LegalizeOp(Node->getOperand(0));
1176 Tmp2 = LegalizeOp(Node->getOperand(1));
1177 Tmp3 = LegalizeOp(Node->getOperand(2));
1178 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1180 SmallVector<SDOperand, 8> Ops;
1181 // Legalize the operands.
1182 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1183 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1184 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1188 case ISD::FORMAL_ARGUMENTS:
1190 // The only option for this is to custom lower it.
1191 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1192 assert(Tmp3.Val && "Target didn't custom lower this node!");
1194 // The number of incoming and outgoing values should match; unless the final
1195 // outgoing value is a flag.
1196 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1197 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1198 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1200 "Lowering call/formal_arguments produced unexpected # results!");
1202 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1203 // remember that we legalized all of them, so it doesn't get relegalized.
1204 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1205 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1207 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1210 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1213 case ISD::EXTRACT_SUBREG: {
1214 Tmp1 = LegalizeOp(Node->getOperand(0));
1215 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1216 assert(idx && "Operand must be a constant");
1217 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1218 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1221 case ISD::INSERT_SUBREG: {
1222 Tmp1 = LegalizeOp(Node->getOperand(0));
1223 Tmp2 = LegalizeOp(Node->getOperand(1));
1224 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1225 assert(idx && "Operand must be a constant");
1226 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1227 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1230 case ISD::BUILD_VECTOR:
1231 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1232 default: assert(0 && "This action is not supported yet!");
1233 case TargetLowering::Custom:
1234 Tmp3 = TLI.LowerOperation(Result, DAG);
1240 case TargetLowering::Expand:
1241 Result = ExpandBUILD_VECTOR(Result.Val);
1245 case ISD::INSERT_VECTOR_ELT:
1246 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1247 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
1248 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1249 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1251 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1252 Node->getValueType(0))) {
1253 default: assert(0 && "This action is not supported yet!");
1254 case TargetLowering::Legal:
1256 case TargetLowering::Custom:
1257 Tmp4 = TLI.LowerOperation(Result, DAG);
1263 case TargetLowering::Expand: {
1264 // If the insert index is a constant, codegen this as a scalar_to_vector,
1265 // then a shuffle that inserts it into the right position in the vector.
1266 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1267 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1268 Tmp1.getValueType(), Tmp2);
1270 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1271 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1272 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1274 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
1275 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
1277 SmallVector<SDOperand, 8> ShufOps;
1278 for (unsigned i = 0; i != NumElts; ++i) {
1279 if (i != InsertPos->getValue())
1280 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1282 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1284 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1285 &ShufOps[0], ShufOps.size());
1287 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1288 Tmp1, ScVec, ShufMask);
1289 Result = LegalizeOp(Result);
1293 // If the target doesn't support this, we have to spill the input vector
1294 // to a temporary stack slot, update the element, then reload it. This is
1295 // badness. We could also load the value into a vector register (either
1296 // with a "move to register" or "extload into register" instruction, then
1297 // permute it into place, if the idx is a constant and if the idx is
1298 // supported by the target.
1299 MVT::ValueType VT = Tmp1.getValueType();
1300 MVT::ValueType EltVT = Tmp2.getValueType();
1301 MVT::ValueType IdxVT = Tmp3.getValueType();
1302 MVT::ValueType PtrVT = TLI.getPointerTy();
1303 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
1304 // Store the vector.
1305 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
1307 // Truncate or zero extend offset to target pointer type.
1308 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1309 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1310 // Add the offset to the index.
1311 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1312 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1313 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1314 // Store the scalar value.
1315 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
1316 // Load the updated vector.
1317 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1322 case ISD::SCALAR_TO_VECTOR:
1323 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1324 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1328 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1329 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1330 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1331 Node->getValueType(0))) {
1332 default: assert(0 && "This action is not supported yet!");
1333 case TargetLowering::Legal:
1335 case TargetLowering::Custom:
1336 Tmp3 = TLI.LowerOperation(Result, DAG);
1342 case TargetLowering::Expand:
1343 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1347 case ISD::VECTOR_SHUFFLE:
1348 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1349 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1350 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1352 // Allow targets to custom lower the SHUFFLEs they support.
1353 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1354 default: assert(0 && "Unknown operation action!");
1355 case TargetLowering::Legal:
1356 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1357 "vector shuffle should not be created if not legal!");
1359 case TargetLowering::Custom:
1360 Tmp3 = TLI.LowerOperation(Result, DAG);
1366 case TargetLowering::Expand: {
1367 MVT::ValueType VT = Node->getValueType(0);
1368 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1369 MVT::ValueType PtrVT = TLI.getPointerTy();
1370 SDOperand Mask = Node->getOperand(2);
1371 unsigned NumElems = Mask.getNumOperands();
1372 SmallVector<SDOperand,8> Ops;
1373 for (unsigned i = 0; i != NumElems; ++i) {
1374 SDOperand Arg = Mask.getOperand(i);
1375 if (Arg.getOpcode() == ISD::UNDEF) {
1376 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1378 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1379 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1381 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1382 DAG.getConstant(Idx, PtrVT)));
1384 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1385 DAG.getConstant(Idx - NumElems, PtrVT)));
1388 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1391 case TargetLowering::Promote: {
1392 // Change base type to a different vector type.
1393 MVT::ValueType OVT = Node->getValueType(0);
1394 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1396 // Cast the two input vectors.
1397 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1398 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1400 // Convert the shuffle mask to the right # elements.
1401 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1402 assert(Tmp3.Val && "Shuffle not legal?");
1403 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1404 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1410 case ISD::EXTRACT_VECTOR_ELT:
1411 Tmp1 = Node->getOperand(0);
1412 Tmp2 = LegalizeOp(Node->getOperand(1));
1413 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1414 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1417 case ISD::EXTRACT_SUBVECTOR:
1418 Tmp1 = Node->getOperand(0);
1419 Tmp2 = LegalizeOp(Node->getOperand(1));
1420 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1421 Result = ExpandEXTRACT_SUBVECTOR(Result);
1424 case ISD::CALLSEQ_START: {
1425 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1427 // Recursively Legalize all of the inputs of the call end that do not lead
1428 // to this call start. This ensures that any libcalls that need be inserted
1429 // are inserted *before* the CALLSEQ_START.
1430 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1431 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1432 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1436 // Now that we legalized all of the inputs (which may have inserted
1437 // libcalls) create the new CALLSEQ_START node.
1438 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1440 // Merge in the last call, to ensure that this call start after the last
1442 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1443 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1444 Tmp1 = LegalizeOp(Tmp1);
1447 // Do not try to legalize the target-specific arguments (#1+).
1448 if (Tmp1 != Node->getOperand(0)) {
1449 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1451 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1454 // Remember that the CALLSEQ_START is legalized.
1455 AddLegalizedOperand(Op.getValue(0), Result);
1456 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1457 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1459 // Now that the callseq_start and all of the non-call nodes above this call
1460 // sequence have been legalized, legalize the call itself. During this
1461 // process, no libcalls can/will be inserted, guaranteeing that no calls
1463 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1464 SDOperand InCallSEQ = LastCALLSEQ_END;
1465 // Note that we are selecting this call!
1466 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1467 IsLegalizingCall = true;
1469 // Legalize the call, starting from the CALLSEQ_END.
1470 LegalizeOp(LastCALLSEQ_END);
1471 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1474 case ISD::CALLSEQ_END:
1475 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1476 // will cause this node to be legalized as well as handling libcalls right.
1477 if (LastCALLSEQ_END.Val != Node) {
1478 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1479 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1480 assert(I != LegalizedNodes.end() &&
1481 "Legalizing the call start should have legalized this node!");
1485 // Otherwise, the call start has been legalized and everything is going
1486 // according to plan. Just legalize ourselves normally here.
1487 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1488 // Do not try to legalize the target-specific arguments (#1+), except for
1489 // an optional flag input.
1490 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1491 if (Tmp1 != Node->getOperand(0)) {
1492 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1494 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1497 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1498 if (Tmp1 != Node->getOperand(0) ||
1499 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1500 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1503 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1506 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1507 // This finishes up call legalization.
1508 IsLegalizingCall = false;
1510 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1511 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1512 if (Node->getNumValues() == 2)
1513 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1514 return Result.getValue(Op.ResNo);
1515 case ISD::DYNAMIC_STACKALLOC: {
1516 MVT::ValueType VT = Node->getValueType(0);
1517 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1518 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1519 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1520 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1522 Tmp1 = Result.getValue(0);
1523 Tmp2 = Result.getValue(1);
1524 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1525 default: assert(0 && "This action is not supported yet!");
1526 case TargetLowering::Expand: {
1527 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1528 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1529 " not tell us which reg is the stack pointer!");
1530 SDOperand Chain = Tmp1.getOperand(0);
1532 // Chain the dynamic stack allocation so that it doesn't modify the stack
1533 // pointer when other instructions are using the stack.
1534 Chain = DAG.getCALLSEQ_START(Chain,
1535 DAG.getConstant(0, TLI.getPointerTy()));
1537 SDOperand Size = Tmp2.getOperand(1);
1538 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1539 Chain = SP.getValue(1);
1540 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1541 unsigned StackAlign =
1542 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1543 if (Align > StackAlign)
1544 SP = DAG.getNode(ISD::AND, VT, SP,
1545 DAG.getConstant(-(uint64_t)Align, VT));
1546 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1547 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1550 DAG.getCALLSEQ_END(Chain,
1551 DAG.getConstant(0, TLI.getPointerTy()),
1552 DAG.getConstant(0, TLI.getPointerTy()),
1555 Tmp1 = LegalizeOp(Tmp1);
1556 Tmp2 = LegalizeOp(Tmp2);
1559 case TargetLowering::Custom:
1560 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1562 Tmp1 = LegalizeOp(Tmp3);
1563 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1566 case TargetLowering::Legal:
1569 // Since this op produce two values, make sure to remember that we
1570 // legalized both of them.
1571 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1572 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1573 return Op.ResNo ? Tmp2 : Tmp1;
1575 case ISD::INLINEASM: {
1576 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1577 bool Changed = false;
1578 // Legalize all of the operands of the inline asm, in case they are nodes
1579 // that need to be expanded or something. Note we skip the asm string and
1580 // all of the TargetConstant flags.
1581 SDOperand Op = LegalizeOp(Ops[0]);
1582 Changed = Op != Ops[0];
1585 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1586 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1587 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1588 for (++i; NumVals; ++i, --NumVals) {
1589 SDOperand Op = LegalizeOp(Ops[i]);
1598 Op = LegalizeOp(Ops.back());
1599 Changed |= Op != Ops.back();
1604 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1606 // INLINE asm returns a chain and flag, make sure to add both to the map.
1607 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1608 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1609 return Result.getValue(Op.ResNo);
1612 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1613 // Ensure that libcalls are emitted before a branch.
1614 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1615 Tmp1 = LegalizeOp(Tmp1);
1616 LastCALLSEQ_END = DAG.getEntryNode();
1618 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1621 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1622 // Ensure that libcalls are emitted before a branch.
1623 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1624 Tmp1 = LegalizeOp(Tmp1);
1625 LastCALLSEQ_END = DAG.getEntryNode();
1627 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1628 default: assert(0 && "Indirect target must be legal type (pointer)!");
1630 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1633 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1636 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1637 // Ensure that libcalls are emitted before a branch.
1638 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1639 Tmp1 = LegalizeOp(Tmp1);
1640 LastCALLSEQ_END = DAG.getEntryNode();
1642 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1643 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1645 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1646 default: assert(0 && "This action is not supported yet!");
1647 case TargetLowering::Legal: break;
1648 case TargetLowering::Custom:
1649 Tmp1 = TLI.LowerOperation(Result, DAG);
1650 if (Tmp1.Val) Result = Tmp1;
1652 case TargetLowering::Expand: {
1653 SDOperand Chain = Result.getOperand(0);
1654 SDOperand Table = Result.getOperand(1);
1655 SDOperand Index = Result.getOperand(2);
1657 MVT::ValueType PTy = TLI.getPointerTy();
1658 MachineFunction &MF = DAG.getMachineFunction();
1659 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1660 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1661 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1664 switch (EntrySize) {
1665 default: assert(0 && "Size of jump table not supported yet."); break;
1666 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1667 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1671 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1672 // For PIC, the sequence is:
1673 // BRIND(load(Jumptable + index) + RelocBase)
1674 // RelocBase can be JumpTable, GOT or some sort of global base.
1675 if (PTy != MVT::i32)
1676 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1677 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1678 TLI.getPICJumpTableRelocBase(Table, DAG));
1680 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1685 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1686 // Ensure that libcalls are emitted before a return.
1687 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1688 Tmp1 = LegalizeOp(Tmp1);
1689 LastCALLSEQ_END = DAG.getEntryNode();
1691 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1692 case Expand: assert(0 && "It's impossible to expand bools");
1694 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1697 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1699 // The top bits of the promoted condition are not necessarily zero, ensure
1700 // that the value is properly zero extended.
1701 if (!DAG.MaskedValueIsZero(Tmp2,
1702 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1703 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1707 // Basic block destination (Op#2) is always legal.
1708 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1710 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1711 default: assert(0 && "This action is not supported yet!");
1712 case TargetLowering::Legal: break;
1713 case TargetLowering::Custom:
1714 Tmp1 = TLI.LowerOperation(Result, DAG);
1715 if (Tmp1.Val) Result = Tmp1;
1717 case TargetLowering::Expand:
1718 // Expand brcond's setcc into its constituent parts and create a BR_CC
1720 if (Tmp2.getOpcode() == ISD::SETCC) {
1721 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1722 Tmp2.getOperand(0), Tmp2.getOperand(1),
1723 Node->getOperand(2));
1725 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1726 DAG.getCondCode(ISD::SETNE), Tmp2,
1727 DAG.getConstant(0, Tmp2.getValueType()),
1728 Node->getOperand(2));
1734 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1735 // Ensure that libcalls are emitted before a branch.
1736 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1737 Tmp1 = LegalizeOp(Tmp1);
1738 Tmp2 = Node->getOperand(2); // LHS
1739 Tmp3 = Node->getOperand(3); // RHS
1740 Tmp4 = Node->getOperand(1); // CC
1742 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1743 LastCALLSEQ_END = DAG.getEntryNode();
1745 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1746 // the LHS is a legal SETCC itself. In this case, we need to compare
1747 // the result against zero to select between true and false values.
1748 if (Tmp3.Val == 0) {
1749 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1750 Tmp4 = DAG.getCondCode(ISD::SETNE);
1753 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1754 Node->getOperand(4));
1756 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1757 default: assert(0 && "Unexpected action for BR_CC!");
1758 case TargetLowering::Legal: break;
1759 case TargetLowering::Custom:
1760 Tmp4 = TLI.LowerOperation(Result, DAG);
1761 if (Tmp4.Val) Result = Tmp4;
1766 LoadSDNode *LD = cast<LoadSDNode>(Node);
1767 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1768 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1770 ISD::LoadExtType ExtType = LD->getExtensionType();
1771 if (ExtType == ISD::NON_EXTLOAD) {
1772 MVT::ValueType VT = Node->getValueType(0);
1773 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1774 Tmp3 = Result.getValue(0);
1775 Tmp4 = Result.getValue(1);
1777 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1778 default: assert(0 && "This action is not supported yet!");
1779 case TargetLowering::Legal:
1780 // If this is an unaligned load and the target doesn't support it,
1782 if (!TLI.allowsUnalignedMemoryAccesses()) {
1783 unsigned ABIAlignment = TLI.getTargetData()->
1784 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
1785 if (LD->getAlignment() < ABIAlignment){
1786 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1788 Tmp3 = Result.getOperand(0);
1789 Tmp4 = Result.getOperand(1);
1790 Tmp3 = LegalizeOp(Tmp3);
1791 Tmp4 = LegalizeOp(Tmp4);
1795 case TargetLowering::Custom:
1796 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1798 Tmp3 = LegalizeOp(Tmp1);
1799 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1802 case TargetLowering::Promote: {
1803 // Only promote a load of vector type to another.
1804 assert(MVT::isVector(VT) && "Cannot promote this load!");
1805 // Change base type to a different vector type.
1806 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1808 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1809 LD->getSrcValueOffset(),
1810 LD->isVolatile(), LD->getAlignment());
1811 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1812 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1816 // Since loads produce two values, make sure to remember that we
1817 // legalized both of them.
1818 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1819 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1820 return Op.ResNo ? Tmp4 : Tmp3;
1822 MVT::ValueType SrcVT = LD->getMemoryVT();
1823 unsigned SrcWidth = MVT::getSizeInBits(SrcVT);
1824 int SVOffset = LD->getSrcValueOffset();
1825 unsigned Alignment = LD->getAlignment();
1826 bool isVolatile = LD->isVolatile();
1828 if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) &&
1829 // Some targets pretend to have an i1 loading operation, and actually
1830 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1831 // bits are guaranteed to be zero; it helps the optimizers understand
1832 // that these bits are zero. It is also useful for EXTLOAD, since it
1833 // tells the optimizers that those bits are undefined. It would be
1834 // nice to have an effective generic way of getting these benefits...
1835 // Until such a way is found, don't insist on promoting i1 here.
1836 (SrcVT != MVT::i1 ||
1837 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1838 // Promote to a byte-sized load if not loading an integral number of
1839 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1840 unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT);
1841 MVT::ValueType NVT = MVT::getIntegerType(NewWidth);
1844 // The extra bits are guaranteed to be zero, since we stored them that
1845 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1847 ISD::LoadExtType NewExtType =
1848 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1850 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
1851 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1852 NVT, isVolatile, Alignment);
1854 Ch = Result.getValue(1); // The chain.
1856 if (ExtType == ISD::SEXTLOAD)
1857 // Having the top bits zero doesn't help when sign extending.
1858 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1859 Result, DAG.getValueType(SrcVT));
1860 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1861 // All the top bits are guaranteed to be zero - inform the optimizers.
1862 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
1863 DAG.getValueType(SrcVT));
1865 Tmp1 = LegalizeOp(Result);
1866 Tmp2 = LegalizeOp(Ch);
1867 } else if (SrcWidth & (SrcWidth - 1)) {
1868 // If not loading a power-of-2 number of bits, expand as two loads.
1869 assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) &&
1870 "Unsupported extload!");
1871 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1872 assert(RoundWidth < SrcWidth);
1873 unsigned ExtraWidth = SrcWidth - RoundWidth;
1874 assert(ExtraWidth < RoundWidth);
1875 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1876 "Load size not an integral number of bytes!");
1877 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
1878 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
1879 SDOperand Lo, Hi, Ch;
1880 unsigned IncrementSize;
1882 if (TLI.isLittleEndian()) {
1883 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1884 // Load the bottom RoundWidth bits.
1885 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
1886 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1889 // Load the remaining ExtraWidth bits.
1890 IncrementSize = RoundWidth / 8;
1891 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1892 DAG.getIntPtrConstant(IncrementSize));
1893 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1894 LD->getSrcValue(), SVOffset + IncrementSize,
1895 ExtraVT, isVolatile,
1896 MinAlign(Alignment, IncrementSize));
1898 // Build a factor node to remember that this load is independent of the
1900 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1903 // Move the top bits to the right place.
1904 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
1905 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1907 // Join the hi and lo parts.
1908 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
1910 // Big endian - avoid unaligned loads.
1911 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1912 // Load the top RoundWidth bits.
1913 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1914 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1917 // Load the remaining ExtraWidth bits.
1918 IncrementSize = RoundWidth / 8;
1919 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1920 DAG.getIntPtrConstant(IncrementSize));
1921 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
1922 LD->getSrcValue(), SVOffset + IncrementSize,
1923 ExtraVT, isVolatile,
1924 MinAlign(Alignment, IncrementSize));
1926 // Build a factor node to remember that this load is independent of the
1928 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1931 // Move the top bits to the right place.
1932 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
1933 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1935 // Join the hi and lo parts.
1936 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
1939 Tmp1 = LegalizeOp(Result);
1940 Tmp2 = LegalizeOp(Ch);
1942 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1943 default: assert(0 && "This action is not supported yet!");
1944 case TargetLowering::Custom:
1947 case TargetLowering::Legal:
1948 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1949 Tmp1 = Result.getValue(0);
1950 Tmp2 = Result.getValue(1);
1953 Tmp3 = TLI.LowerOperation(Result, DAG);
1955 Tmp1 = LegalizeOp(Tmp3);
1956 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1959 // If this is an unaligned load and the target doesn't support it,
1961 if (!TLI.allowsUnalignedMemoryAccesses()) {
1962 unsigned ABIAlignment = TLI.getTargetData()->
1963 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
1964 if (LD->getAlignment() < ABIAlignment){
1965 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1967 Tmp1 = Result.getOperand(0);
1968 Tmp2 = Result.getOperand(1);
1969 Tmp1 = LegalizeOp(Tmp1);
1970 Tmp2 = LegalizeOp(Tmp2);
1975 case TargetLowering::Expand:
1976 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1977 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1978 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1979 LD->getSrcValueOffset(),
1980 LD->isVolatile(), LD->getAlignment());
1981 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1982 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1983 Tmp2 = LegalizeOp(Load.getValue(1));
1986 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1987 // Turn the unsupported load into an EXTLOAD followed by an explicit
1988 // zero/sign extend inreg.
1989 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1990 Tmp1, Tmp2, LD->getSrcValue(),
1991 LD->getSrcValueOffset(), SrcVT,
1992 LD->isVolatile(), LD->getAlignment());
1994 if (ExtType == ISD::SEXTLOAD)
1995 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1996 Result, DAG.getValueType(SrcVT));
1998 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1999 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2000 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2005 // Since loads produce two values, make sure to remember that we legalized
2007 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2008 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2009 return Op.ResNo ? Tmp2 : Tmp1;
2012 case ISD::EXTRACT_ELEMENT: {
2013 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
2014 switch (getTypeAction(OpTy)) {
2015 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2017 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2019 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2020 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
2021 TLI.getShiftAmountTy()));
2022 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2025 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2026 Node->getOperand(0));
2030 // Get both the low and high parts.
2031 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2032 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2033 Result = Tmp2; // 1 -> Hi
2035 Result = Tmp1; // 0 -> Lo
2041 case ISD::CopyToReg:
2042 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2044 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2045 "Register type must be legal!");
2046 // Legalize the incoming value (must be a legal type).
2047 Tmp2 = LegalizeOp(Node->getOperand(2));
2048 if (Node->getNumValues() == 1) {
2049 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2051 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2052 if (Node->getNumOperands() == 4) {
2053 Tmp3 = LegalizeOp(Node->getOperand(3));
2054 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2057 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2060 // Since this produces two values, make sure to remember that we legalized
2062 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2063 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2069 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2071 // Ensure that libcalls are emitted before a return.
2072 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2073 Tmp1 = LegalizeOp(Tmp1);
2074 LastCALLSEQ_END = DAG.getEntryNode();
2076 switch (Node->getNumOperands()) {
2078 Tmp2 = Node->getOperand(1);
2079 Tmp3 = Node->getOperand(2); // Signness
2080 switch (getTypeAction(Tmp2.getValueType())) {
2082 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2085 if (!MVT::isVector(Tmp2.getValueType())) {
2087 ExpandOp(Tmp2, Lo, Hi);
2089 // Big endian systems want the hi reg first.
2090 if (!TLI.isLittleEndian())
2094 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2096 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2097 Result = LegalizeOp(Result);
2099 SDNode *InVal = Tmp2.Val;
2100 int InIx = Tmp2.ResNo;
2101 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
2102 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
2104 // Figure out if there is a simple type corresponding to this Vector
2105 // type. If so, convert to the vector type.
2106 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2107 if (TLI.isTypeLegal(TVT)) {
2108 // Turn this into a return of the vector type.
2109 Tmp2 = LegalizeOp(Tmp2);
2110 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2111 } else if (NumElems == 1) {
2112 // Turn this into a return of the scalar type.
2113 Tmp2 = ScalarizeVectorOp(Tmp2);
2114 Tmp2 = LegalizeOp(Tmp2);
2115 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2117 // FIXME: Returns of gcc generic vectors smaller than a legal type
2118 // should be returned in integer registers!
2120 // The scalarized value type may not be legal, e.g. it might require
2121 // promotion or expansion. Relegalize the return.
2122 Result = LegalizeOp(Result);
2124 // FIXME: Returns of gcc generic vectors larger than a legal vector
2125 // type should be returned by reference!
2127 SplitVectorOp(Tmp2, Lo, Hi);
2128 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2129 Result = LegalizeOp(Result);
2134 Tmp2 = PromoteOp(Node->getOperand(1));
2135 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2136 Result = LegalizeOp(Result);
2141 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2143 default: { // ret <values>
2144 SmallVector<SDOperand, 8> NewValues;
2145 NewValues.push_back(Tmp1);
2146 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2147 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2149 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2150 NewValues.push_back(Node->getOperand(i+1));
2154 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
2155 "FIXME: TODO: implement returning non-legal vector types!");
2156 ExpandOp(Node->getOperand(i), Lo, Hi);
2157 NewValues.push_back(Lo);
2158 NewValues.push_back(Node->getOperand(i+1));
2160 NewValues.push_back(Hi);
2161 NewValues.push_back(Node->getOperand(i+1));
2166 assert(0 && "Can't promote multiple return value yet!");
2169 if (NewValues.size() == Node->getNumOperands())
2170 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2172 Result = DAG.getNode(ISD::RET, MVT::Other,
2173 &NewValues[0], NewValues.size());
2178 if (Result.getOpcode() == ISD::RET) {
2179 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2180 default: assert(0 && "This action is not supported yet!");
2181 case TargetLowering::Legal: break;
2182 case TargetLowering::Custom:
2183 Tmp1 = TLI.LowerOperation(Result, DAG);
2184 if (Tmp1.Val) Result = Tmp1;
2190 StoreSDNode *ST = cast<StoreSDNode>(Node);
2191 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2192 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2193 int SVOffset = ST->getSrcValueOffset();
2194 unsigned Alignment = ST->getAlignment();
2195 bool isVolatile = ST->isVolatile();
2197 if (!ST->isTruncatingStore()) {
2198 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2199 // FIXME: We shouldn't do this for TargetConstantFP's.
2200 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2201 // to phase ordering between legalized code and the dag combiner. This
2202 // probably means that we need to integrate dag combiner and legalizer
2204 // We generally can't do this one for long doubles.
2205 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2206 if (CFP->getValueType(0) == MVT::f32 &&
2207 getTypeAction(MVT::i32) == Legal) {
2208 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF().
2209 convertToAPInt().getZExtValue(),
2211 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2212 SVOffset, isVolatile, Alignment);
2214 } else if (CFP->getValueType(0) == MVT::f64) {
2215 // If this target supports 64-bit registers, do a single 64-bit store.
2216 if (getTypeAction(MVT::i64) == Legal) {
2217 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2218 getZExtValue(), MVT::i64);
2219 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2220 SVOffset, isVolatile, Alignment);
2222 } else if (getTypeAction(MVT::i32) == Legal) {
2223 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2224 // stores. If the target supports neither 32- nor 64-bits, this
2225 // xform is certainly not worth it.
2226 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue();
2227 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32);
2228 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32);
2229 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
2231 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2232 SVOffset, isVolatile, Alignment);
2233 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2234 DAG.getIntPtrConstant(4));
2235 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2236 isVolatile, MinAlign(Alignment, 4U));
2238 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2244 switch (getTypeAction(ST->getMemoryVT())) {
2246 Tmp3 = LegalizeOp(ST->getValue());
2247 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2250 MVT::ValueType VT = Tmp3.getValueType();
2251 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2252 default: assert(0 && "This action is not supported yet!");
2253 case TargetLowering::Legal:
2254 // If this is an unaligned store and the target doesn't support it,
2256 if (!TLI.allowsUnalignedMemoryAccesses()) {
2257 unsigned ABIAlignment = TLI.getTargetData()->
2258 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2259 if (ST->getAlignment() < ABIAlignment)
2260 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2264 case TargetLowering::Custom:
2265 Tmp1 = TLI.LowerOperation(Result, DAG);
2266 if (Tmp1.Val) Result = Tmp1;
2268 case TargetLowering::Promote:
2269 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2270 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2271 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2272 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2273 ST->getSrcValue(), SVOffset, isVolatile,
2280 // Truncate the value and store the result.
2281 Tmp3 = PromoteOp(ST->getValue());
2282 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2283 SVOffset, ST->getMemoryVT(),
2284 isVolatile, Alignment);
2288 unsigned IncrementSize = 0;
2291 // If this is a vector type, then we have to calculate the increment as
2292 // the product of the element size in bytes, and the number of elements
2293 // in the high half of the vector.
2294 if (MVT::isVector(ST->getValue().getValueType())) {
2295 SDNode *InVal = ST->getValue().Val;
2296 int InIx = ST->getValue().ResNo;
2297 MVT::ValueType InVT = InVal->getValueType(InIx);
2298 unsigned NumElems = MVT::getVectorNumElements(InVT);
2299 MVT::ValueType EVT = MVT::getVectorElementType(InVT);
2301 // Figure out if there is a simple type corresponding to this Vector
2302 // type. If so, convert to the vector type.
2303 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2304 if (TLI.isTypeLegal(TVT)) {
2305 // Turn this into a normal store of the vector type.
2306 Tmp3 = LegalizeOp(Node->getOperand(1));
2307 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2308 SVOffset, isVolatile, Alignment);
2309 Result = LegalizeOp(Result);
2311 } else if (NumElems == 1) {
2312 // Turn this into a normal store of the scalar type.
2313 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
2314 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2315 SVOffset, isVolatile, Alignment);
2316 // The scalarized value type may not be legal, e.g. it might require
2317 // promotion or expansion. Relegalize the scalar store.
2318 Result = LegalizeOp(Result);
2321 SplitVectorOp(Node->getOperand(1), Lo, Hi);
2322 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
2323 MVT::getSizeInBits(EVT)/8;
2326 ExpandOp(Node->getOperand(1), Lo, Hi);
2327 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2329 if (!TLI.isLittleEndian())
2333 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2334 SVOffset, isVolatile, Alignment);
2336 if (Hi.Val == NULL) {
2337 // Must be int <-> float one-to-one expansion.
2342 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2343 DAG.getIntPtrConstant(IncrementSize));
2344 assert(isTypeLegal(Tmp2.getValueType()) &&
2345 "Pointers must be legal!");
2346 SVOffset += IncrementSize;
2347 Alignment = MinAlign(Alignment, IncrementSize);
2348 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2349 SVOffset, isVolatile, Alignment);
2350 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2354 switch (getTypeAction(ST->getValue().getValueType())) {
2356 Tmp3 = LegalizeOp(ST->getValue());
2359 // We can promote the value, the truncstore will still take care of it.
2360 Tmp3 = PromoteOp(ST->getValue());
2363 // Just store the low part. This may become a non-trunc store, so make
2364 // sure to use getTruncStore, not UpdateNodeOperands below.
2365 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2366 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2367 SVOffset, MVT::i8, isVolatile, Alignment);
2370 MVT::ValueType StVT = ST->getMemoryVT();
2371 unsigned StWidth = MVT::getSizeInBits(StVT);
2373 if (StWidth != MVT::getStoreSizeInBits(StVT)) {
2374 // Promote to a byte-sized store with upper bits zero if not
2375 // storing an integral number of bytes. For example, promote
2376 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2377 MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT));
2378 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2379 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2380 SVOffset, NVT, isVolatile, Alignment);
2381 } else if (StWidth & (StWidth - 1)) {
2382 // If not storing a power-of-2 number of bits, expand as two stores.
2383 assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) &&
2384 "Unsupported truncstore!");
2385 unsigned RoundWidth = 1 << Log2_32(StWidth);
2386 assert(RoundWidth < StWidth);
2387 unsigned ExtraWidth = StWidth - RoundWidth;
2388 assert(ExtraWidth < RoundWidth);
2389 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2390 "Store size not an integral number of bytes!");
2391 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
2392 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
2394 unsigned IncrementSize;
2396 if (TLI.isLittleEndian()) {
2397 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2398 // Store the bottom RoundWidth bits.
2399 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2401 isVolatile, Alignment);
2403 // Store the remaining ExtraWidth bits.
2404 IncrementSize = RoundWidth / 8;
2405 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2406 DAG.getIntPtrConstant(IncrementSize));
2407 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2408 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2409 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2410 SVOffset + IncrementSize, ExtraVT, isVolatile,
2411 MinAlign(Alignment, IncrementSize));
2413 // Big endian - avoid unaligned stores.
2414 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2415 // Store the top RoundWidth bits.
2416 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2417 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2418 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2419 RoundVT, isVolatile, Alignment);
2421 // Store the remaining ExtraWidth bits.
2422 IncrementSize = RoundWidth / 8;
2423 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2424 DAG.getIntPtrConstant(IncrementSize));
2425 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2426 SVOffset + IncrementSize, ExtraVT, isVolatile,
2427 MinAlign(Alignment, IncrementSize));
2430 // The order of the stores doesn't matter.
2431 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2433 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2434 Tmp2 != ST->getBasePtr())
2435 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2438 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2439 default: assert(0 && "This action is not supported yet!");
2440 case TargetLowering::Legal:
2441 // If this is an unaligned store and the target doesn't support it,
2443 if (!TLI.allowsUnalignedMemoryAccesses()) {
2444 unsigned ABIAlignment = TLI.getTargetData()->
2445 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2446 if (ST->getAlignment() < ABIAlignment)
2447 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2451 case TargetLowering::Custom:
2452 Result = TLI.LowerOperation(Result, DAG);
2455 // TRUNCSTORE:i16 i32 -> STORE i16
2456 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2457 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2458 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2459 isVolatile, Alignment);
2467 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2468 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2470 case ISD::STACKSAVE:
2471 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2472 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2473 Tmp1 = Result.getValue(0);
2474 Tmp2 = Result.getValue(1);
2476 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2477 default: assert(0 && "This action is not supported yet!");
2478 case TargetLowering::Legal: break;
2479 case TargetLowering::Custom:
2480 Tmp3 = TLI.LowerOperation(Result, DAG);
2482 Tmp1 = LegalizeOp(Tmp3);
2483 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2486 case TargetLowering::Expand:
2487 // Expand to CopyFromReg if the target set
2488 // StackPointerRegisterToSaveRestore.
2489 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2490 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2491 Node->getValueType(0));
2492 Tmp2 = Tmp1.getValue(1);
2494 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2495 Tmp2 = Node->getOperand(0);
2500 // Since stacksave produce two values, make sure to remember that we
2501 // legalized both of them.
2502 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2503 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2504 return Op.ResNo ? Tmp2 : Tmp1;
2506 case ISD::STACKRESTORE:
2507 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2508 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2509 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2511 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2512 default: assert(0 && "This action is not supported yet!");
2513 case TargetLowering::Legal: break;
2514 case TargetLowering::Custom:
2515 Tmp1 = TLI.LowerOperation(Result, DAG);
2516 if (Tmp1.Val) Result = Tmp1;
2518 case TargetLowering::Expand:
2519 // Expand to CopyToReg if the target set
2520 // StackPointerRegisterToSaveRestore.
2521 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2522 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2530 case ISD::READCYCLECOUNTER:
2531 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2532 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2533 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2534 Node->getValueType(0))) {
2535 default: assert(0 && "This action is not supported yet!");
2536 case TargetLowering::Legal:
2537 Tmp1 = Result.getValue(0);
2538 Tmp2 = Result.getValue(1);
2540 case TargetLowering::Custom:
2541 Result = TLI.LowerOperation(Result, DAG);
2542 Tmp1 = LegalizeOp(Result.getValue(0));
2543 Tmp2 = LegalizeOp(Result.getValue(1));
2547 // Since rdcc produce two values, make sure to remember that we legalized
2549 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2550 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2554 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2555 case Expand: assert(0 && "It's impossible to expand bools");
2557 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2560 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2561 // Make sure the condition is either zero or one.
2562 if (!DAG.MaskedValueIsZero(Tmp1,
2563 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2564 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2567 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2568 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2570 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2572 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2573 default: assert(0 && "This action is not supported yet!");
2574 case TargetLowering::Legal: break;
2575 case TargetLowering::Custom: {
2576 Tmp1 = TLI.LowerOperation(Result, DAG);
2577 if (Tmp1.Val) Result = Tmp1;
2580 case TargetLowering::Expand:
2581 if (Tmp1.getOpcode() == ISD::SETCC) {
2582 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2584 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2586 Result = DAG.getSelectCC(Tmp1,
2587 DAG.getConstant(0, Tmp1.getValueType()),
2588 Tmp2, Tmp3, ISD::SETNE);
2591 case TargetLowering::Promote: {
2592 MVT::ValueType NVT =
2593 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2594 unsigned ExtOp, TruncOp;
2595 if (MVT::isVector(Tmp2.getValueType())) {
2596 ExtOp = ISD::BIT_CONVERT;
2597 TruncOp = ISD::BIT_CONVERT;
2598 } else if (MVT::isInteger(Tmp2.getValueType())) {
2599 ExtOp = ISD::ANY_EXTEND;
2600 TruncOp = ISD::TRUNCATE;
2602 ExtOp = ISD::FP_EXTEND;
2603 TruncOp = ISD::FP_ROUND;
2605 // Promote each of the values to the new type.
2606 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2607 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2608 // Perform the larger operation, then round down.
2609 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2610 if (TruncOp != ISD::FP_ROUND)
2611 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2613 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2614 DAG.getIntPtrConstant(0));
2619 case ISD::SELECT_CC: {
2620 Tmp1 = Node->getOperand(0); // LHS
2621 Tmp2 = Node->getOperand(1); // RHS
2622 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2623 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2624 SDOperand CC = Node->getOperand(4);
2626 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2628 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2629 // the LHS is a legal SETCC itself. In this case, we need to compare
2630 // the result against zero to select between true and false values.
2631 if (Tmp2.Val == 0) {
2632 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2633 CC = DAG.getCondCode(ISD::SETNE);
2635 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2637 // Everything is legal, see if we should expand this op or something.
2638 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2639 default: assert(0 && "This action is not supported yet!");
2640 case TargetLowering::Legal: break;
2641 case TargetLowering::Custom:
2642 Tmp1 = TLI.LowerOperation(Result, DAG);
2643 if (Tmp1.Val) Result = Tmp1;
2649 Tmp1 = Node->getOperand(0);
2650 Tmp2 = Node->getOperand(1);
2651 Tmp3 = Node->getOperand(2);
2652 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2654 // If we had to Expand the SetCC operands into a SELECT node, then it may
2655 // not always be possible to return a true LHS & RHS. In this case, just
2656 // return the value we legalized, returned in the LHS
2657 if (Tmp2.Val == 0) {
2662 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2663 default: assert(0 && "Cannot handle this action for SETCC yet!");
2664 case TargetLowering::Custom:
2667 case TargetLowering::Legal:
2668 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2670 Tmp4 = TLI.LowerOperation(Result, DAG);
2671 if (Tmp4.Val) Result = Tmp4;
2674 case TargetLowering::Promote: {
2675 // First step, figure out the appropriate operation to use.
2676 // Allow SETCC to not be supported for all legal data types
2677 // Mostly this targets FP
2678 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2679 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2681 // Scan for the appropriate larger type to use.
2683 NewInTy = (MVT::ValueType)(NewInTy+1);
2685 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2686 "Fell off of the edge of the integer world");
2687 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2688 "Fell off of the edge of the floating point world");
2690 // If the target supports SETCC of this type, use it.
2691 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2694 if (MVT::isInteger(NewInTy))
2695 assert(0 && "Cannot promote Legal Integer SETCC yet");
2697 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2698 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2700 Tmp1 = LegalizeOp(Tmp1);
2701 Tmp2 = LegalizeOp(Tmp2);
2702 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2703 Result = LegalizeOp(Result);
2706 case TargetLowering::Expand:
2707 // Expand a setcc node into a select_cc of the same condition, lhs, and
2708 // rhs that selects between const 1 (true) and const 0 (false).
2709 MVT::ValueType VT = Node->getValueType(0);
2710 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2711 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2718 case ISD::MEMMOVE: {
2719 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2720 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2722 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2723 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2724 case Expand: assert(0 && "Cannot expand a byte!");
2726 Tmp3 = LegalizeOp(Node->getOperand(2));
2729 Tmp3 = PromoteOp(Node->getOperand(2));
2733 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2737 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2739 // Length is too big, just take the lo-part of the length.
2741 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2745 Tmp4 = LegalizeOp(Node->getOperand(3));
2748 Tmp4 = PromoteOp(Node->getOperand(3));
2753 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2754 case Expand: assert(0 && "Cannot expand this yet!");
2756 Tmp5 = LegalizeOp(Node->getOperand(4));
2759 Tmp5 = PromoteOp(Node->getOperand(4));
2764 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool
2765 case Expand: assert(0 && "Cannot expand this yet!");
2767 Tmp6 = LegalizeOp(Node->getOperand(5));
2770 Tmp6 = PromoteOp(Node->getOperand(5));
2774 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2775 default: assert(0 && "This action not implemented for this operation!");
2776 case TargetLowering::Custom:
2779 case TargetLowering::Legal: {
2780 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 };
2781 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
2783 Tmp1 = TLI.LowerOperation(Result, DAG);
2784 if (Tmp1.Val) Result = Tmp1;
2788 case TargetLowering::Expand: {
2789 // Otherwise, the target does not support this operation. Lower the
2790 // operation to an explicit libcall as appropriate.
2791 MVT::ValueType IntPtr = TLI.getPointerTy();
2792 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2793 TargetLowering::ArgListTy Args;
2794 TargetLowering::ArgListEntry Entry;
2796 const char *FnName = 0;
2797 if (Node->getOpcode() == ISD::MEMSET) {
2798 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2799 Args.push_back(Entry);
2800 // Extend the (previously legalized) ubyte argument to be an int value
2802 if (Tmp3.getValueType() > MVT::i32)
2803 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2805 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2806 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2807 Args.push_back(Entry);
2808 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2809 Args.push_back(Entry);
2812 } else if (Node->getOpcode() == ISD::MEMCPY ||
2813 Node->getOpcode() == ISD::MEMMOVE) {
2814 Entry.Ty = IntPtrTy;
2815 Entry.Node = Tmp2; Args.push_back(Entry);
2816 Entry.Node = Tmp3; Args.push_back(Entry);
2817 Entry.Node = Tmp4; Args.push_back(Entry);
2818 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2820 assert(0 && "Unknown op!");
2823 std::pair<SDOperand,SDOperand> CallResult =
2824 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2825 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2826 Result = CallResult.second;
2833 case ISD::SHL_PARTS:
2834 case ISD::SRA_PARTS:
2835 case ISD::SRL_PARTS: {
2836 SmallVector<SDOperand, 8> Ops;
2837 bool Changed = false;
2838 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2839 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2840 Changed |= Ops.back() != Node->getOperand(i);
2843 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2845 switch (TLI.getOperationAction(Node->getOpcode(),
2846 Node->getValueType(0))) {
2847 default: assert(0 && "This action is not supported yet!");
2848 case TargetLowering::Legal: break;
2849 case TargetLowering::Custom:
2850 Tmp1 = TLI.LowerOperation(Result, DAG);
2852 SDOperand Tmp2, RetVal(0, 0);
2853 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2854 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2855 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2859 assert(RetVal.Val && "Illegal result number");
2865 // Since these produce multiple values, make sure to remember that we
2866 // legalized all of them.
2867 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2868 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2869 return Result.getValue(Op.ResNo);
2891 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2892 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2893 case Expand: assert(0 && "Not possible");
2895 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2898 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2902 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2904 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2905 default: assert(0 && "BinOp legalize operation not supported");
2906 case TargetLowering::Legal: break;
2907 case TargetLowering::Custom:
2908 Tmp1 = TLI.LowerOperation(Result, DAG);
2909 if (Tmp1.Val) Result = Tmp1;
2911 case TargetLowering::Expand: {
2912 MVT::ValueType VT = Op.getValueType();
2914 // See if multiply or divide can be lowered using two-result operations.
2915 SDVTList VTs = DAG.getVTList(VT, VT);
2916 if (Node->getOpcode() == ISD::MUL) {
2917 // We just need the low half of the multiply; try both the signed
2918 // and unsigned forms. If the target supports both SMUL_LOHI and
2919 // UMUL_LOHI, form a preference by checking which forms of plain
2920 // MULH it supports.
2921 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2922 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2923 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2924 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2925 unsigned OpToUse = 0;
2926 if (HasSMUL_LOHI && !HasMULHS) {
2927 OpToUse = ISD::SMUL_LOHI;
2928 } else if (HasUMUL_LOHI && !HasMULHU) {
2929 OpToUse = ISD::UMUL_LOHI;
2930 } else if (HasSMUL_LOHI) {
2931 OpToUse = ISD::SMUL_LOHI;
2932 } else if (HasUMUL_LOHI) {
2933 OpToUse = ISD::UMUL_LOHI;
2936 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
2940 if (Node->getOpcode() == ISD::MULHS &&
2941 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
2942 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2945 if (Node->getOpcode() == ISD::MULHU &&
2946 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
2947 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2950 if (Node->getOpcode() == ISD::SDIV &&
2951 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
2952 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2955 if (Node->getOpcode() == ISD::UDIV &&
2956 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
2957 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2961 // Check to see if we have a libcall for this operator.
2962 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2963 bool isSigned = false;
2964 switch (Node->getOpcode()) {
2967 if (VT == MVT::i32) {
2968 LC = Node->getOpcode() == ISD::UDIV
2969 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2970 isSigned = Node->getOpcode() == ISD::SDIV;
2974 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
2975 RTLIB::POW_PPCF128);
2979 if (LC != RTLIB::UNKNOWN_LIBCALL) {
2981 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2985 assert(MVT::isVector(Node->getValueType(0)) &&
2986 "Cannot expand this binary operator!");
2987 // Expand the operation into a bunch of nasty scalar code.
2988 Result = LegalizeOp(UnrollVectorOp(Op));
2991 case TargetLowering::Promote: {
2992 switch (Node->getOpcode()) {
2993 default: assert(0 && "Do not know how to promote this BinOp!");
2997 MVT::ValueType OVT = Node->getValueType(0);
2998 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2999 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
3000 // Bit convert each of the values to the new type.
3001 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3002 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3003 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3004 // Bit convert the result back the original type.
3005 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3013 case ISD::SMUL_LOHI:
3014 case ISD::UMUL_LOHI:
3017 // These nodes will only be produced by target-specific lowering, so
3018 // they shouldn't be here if they aren't legal.
3019 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3020 "This must be legal!");
3022 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3023 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3024 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3027 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3028 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3029 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3030 case Expand: assert(0 && "Not possible");
3032 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3035 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3039 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3041 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3042 default: assert(0 && "Operation not supported");
3043 case TargetLowering::Custom:
3044 Tmp1 = TLI.LowerOperation(Result, DAG);
3045 if (Tmp1.Val) Result = Tmp1;
3047 case TargetLowering::Legal: break;
3048 case TargetLowering::Expand: {
3049 // If this target supports fabs/fneg natively and select is cheap,
3050 // do this efficiently.
3051 if (!TLI.isSelectExpensive() &&
3052 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3053 TargetLowering::Legal &&
3054 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3055 TargetLowering::Legal) {
3056 // Get the sign bit of the RHS.
3057 MVT::ValueType IVT =
3058 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3059 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3060 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
3061 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3062 // Get the absolute value of the result.
3063 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3064 // Select between the nabs and abs value based on the sign bit of
3066 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3067 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3070 Result = LegalizeOp(Result);
3074 // Otherwise, do bitwise ops!
3075 MVT::ValueType NVT =
3076 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3077 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3078 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3079 Result = LegalizeOp(Result);
3087 Tmp1 = LegalizeOp(Node->getOperand(0));
3088 Tmp2 = LegalizeOp(Node->getOperand(1));
3089 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3090 // Since this produces two values, make sure to remember that we legalized
3092 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3093 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3098 Tmp1 = LegalizeOp(Node->getOperand(0));
3099 Tmp2 = LegalizeOp(Node->getOperand(1));
3100 Tmp3 = LegalizeOp(Node->getOperand(2));
3101 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3102 // Since this produces two values, make sure to remember that we legalized
3104 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3105 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3108 case ISD::BUILD_PAIR: {
3109 MVT::ValueType PairTy = Node->getValueType(0);
3110 // TODO: handle the case where the Lo and Hi operands are not of legal type
3111 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3112 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3113 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3114 case TargetLowering::Promote:
3115 case TargetLowering::Custom:
3116 assert(0 && "Cannot promote/custom this yet!");
3117 case TargetLowering::Legal:
3118 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3119 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3121 case TargetLowering::Expand:
3122 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3123 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3124 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3125 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
3126 TLI.getShiftAmountTy()));
3127 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3136 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3137 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3139 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3140 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3141 case TargetLowering::Custom:
3144 case TargetLowering::Legal:
3145 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3147 Tmp1 = TLI.LowerOperation(Result, DAG);
3148 if (Tmp1.Val) Result = Tmp1;
3151 case TargetLowering::Expand: {
3152 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3153 bool isSigned = DivOpc == ISD::SDIV;
3154 MVT::ValueType VT = Node->getValueType(0);
3156 // See if remainder can be lowered using two-result operations.
3157 SDVTList VTs = DAG.getVTList(VT, VT);
3158 if (Node->getOpcode() == ISD::SREM &&
3159 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3160 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3163 if (Node->getOpcode() == ISD::UREM &&
3164 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3165 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3169 if (MVT::isInteger(VT)) {
3170 if (TLI.getOperationAction(DivOpc, VT) ==
3171 TargetLowering::Legal) {
3173 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3174 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3175 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3176 } else if (MVT::isVector(VT)) {
3177 Result = LegalizeOp(UnrollVectorOp(Op));
3179 assert(VT == MVT::i32 &&
3180 "Cannot expand this binary operator!");
3181 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3182 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3184 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3187 assert(MVT::isFloatingPoint(VT) &&
3188 "remainder op must have integer or floating-point type");
3189 if (MVT::isVector(VT)) {
3190 Result = LegalizeOp(UnrollVectorOp(Op));
3192 // Floating point mod -> fmod libcall.
3193 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3194 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3196 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3197 false/*sign irrelevant*/, Dummy);
3205 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3206 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3208 MVT::ValueType VT = Node->getValueType(0);
3209 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3210 default: assert(0 && "This action is not supported yet!");
3211 case TargetLowering::Custom:
3214 case TargetLowering::Legal:
3215 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3216 Result = Result.getValue(0);
3217 Tmp1 = Result.getValue(1);
3220 Tmp2 = TLI.LowerOperation(Result, DAG);
3222 Result = LegalizeOp(Tmp2);
3223 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3227 case TargetLowering::Expand: {
3228 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3229 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3230 SV->getValue(), SV->getOffset());
3231 // Increment the pointer, VAList, to the next vaarg
3232 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3233 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3234 TLI.getPointerTy()));
3235 // Store the incremented VAList to the legalized pointer
3236 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3238 // Load the actual argument out of the pointer VAList
3239 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3240 Tmp1 = LegalizeOp(Result.getValue(1));
3241 Result = LegalizeOp(Result);
3245 // Since VAARG produces two values, make sure to remember that we
3246 // legalized both of them.
3247 AddLegalizedOperand(SDOperand(Node, 0), Result);
3248 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3249 return Op.ResNo ? Tmp1 : Result;
3253 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3254 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3255 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3257 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3258 default: assert(0 && "This action is not supported yet!");
3259 case TargetLowering::Custom:
3262 case TargetLowering::Legal:
3263 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3264 Node->getOperand(3), Node->getOperand(4));
3266 Tmp1 = TLI.LowerOperation(Result, DAG);
3267 if (Tmp1.Val) Result = Tmp1;
3270 case TargetLowering::Expand:
3271 // This defaults to loading a pointer from the input and storing it to the
3272 // output, returning the chain.
3273 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
3274 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
3275 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
3277 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
3284 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3285 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3287 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3288 default: assert(0 && "This action is not supported yet!");
3289 case TargetLowering::Custom:
3292 case TargetLowering::Legal:
3293 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3295 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3296 if (Tmp1.Val) Result = Tmp1;
3299 case TargetLowering::Expand:
3300 Result = Tmp1; // Default to a no-op, return the chain
3306 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3307 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3309 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3311 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3312 default: assert(0 && "This action is not supported yet!");
3313 case TargetLowering::Legal: break;
3314 case TargetLowering::Custom:
3315 Tmp1 = TLI.LowerOperation(Result, DAG);
3316 if (Tmp1.Val) Result = Tmp1;
3323 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3324 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3325 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3326 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3328 assert(0 && "ROTL/ROTR legalize operation not supported");
3330 case TargetLowering::Legal:
3332 case TargetLowering::Custom:
3333 Tmp1 = TLI.LowerOperation(Result, DAG);
3334 if (Tmp1.Val) Result = Tmp1;
3336 case TargetLowering::Promote:
3337 assert(0 && "Do not know how to promote ROTL/ROTR");
3339 case TargetLowering::Expand:
3340 assert(0 && "Do not know how to expand ROTL/ROTR");
3346 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3347 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3348 case TargetLowering::Custom:
3349 assert(0 && "Cannot custom legalize this yet!");
3350 case TargetLowering::Legal:
3351 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3353 case TargetLowering::Promote: {
3354 MVT::ValueType OVT = Tmp1.getValueType();
3355 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3356 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
3358 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3359 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3360 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3361 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3364 case TargetLowering::Expand:
3365 Result = ExpandBSWAP(Tmp1);
3373 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3374 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3375 case TargetLowering::Custom:
3376 case TargetLowering::Legal:
3377 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3378 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3379 TargetLowering::Custom) {
3380 Tmp1 = TLI.LowerOperation(Result, DAG);
3386 case TargetLowering::Promote: {
3387 MVT::ValueType OVT = Tmp1.getValueType();
3388 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3390 // Zero extend the argument.
3391 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3392 // Perform the larger operation, then subtract if needed.
3393 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3394 switch (Node->getOpcode()) {
3399 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3400 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3401 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3403 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3404 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
3407 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3408 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3409 DAG.getConstant(MVT::getSizeInBits(NVT) -
3410 MVT::getSizeInBits(OVT), NVT));
3415 case TargetLowering::Expand:
3416 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3427 Tmp1 = LegalizeOp(Node->getOperand(0));
3428 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3429 case TargetLowering::Promote:
3430 case TargetLowering::Custom:
3433 case TargetLowering::Legal:
3434 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3436 Tmp1 = TLI.LowerOperation(Result, DAG);
3437 if (Tmp1.Val) Result = Tmp1;
3440 case TargetLowering::Expand:
3441 switch (Node->getOpcode()) {
3442 default: assert(0 && "Unreachable!");
3444 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3445 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3446 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3449 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3450 MVT::ValueType VT = Node->getValueType(0);
3451 Tmp2 = DAG.getConstantFP(0.0, VT);
3452 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
3453 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3454 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3460 MVT::ValueType VT = Node->getValueType(0);
3462 // Expand unsupported unary vector operators by unrolling them.
3463 if (MVT::isVector(VT)) {
3464 Result = LegalizeOp(UnrollVectorOp(Op));
3468 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3469 switch(Node->getOpcode()) {
3471 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3472 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3475 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3476 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3479 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3480 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3482 default: assert(0 && "Unreachable!");
3485 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3486 false/*sign irrelevant*/, Dummy);
3494 MVT::ValueType VT = Node->getValueType(0);
3496 // Expand unsupported unary vector operators by unrolling them.
3497 if (MVT::isVector(VT)) {
3498 Result = LegalizeOp(UnrollVectorOp(Op));
3502 // We always lower FPOWI into a libcall. No target support for it yet.
3503 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3504 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3506 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3507 false/*sign irrelevant*/, Dummy);
3510 case ISD::BIT_CONVERT:
3511 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3512 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3513 Node->getValueType(0));
3514 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3515 // The input has to be a vector type, we have to either scalarize it, pack
3516 // it, or convert it based on whether the input vector type is legal.
3517 SDNode *InVal = Node->getOperand(0).Val;
3518 int InIx = Node->getOperand(0).ResNo;
3519 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
3520 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
3522 // Figure out if there is a simple type corresponding to this Vector
3523 // type. If so, convert to the vector type.
3524 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3525 if (TLI.isTypeLegal(TVT)) {
3526 // Turn this into a bit convert of the vector input.
3527 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3528 LegalizeOp(Node->getOperand(0)));
3530 } else if (NumElems == 1) {
3531 // Turn this into a bit convert of the scalar input.
3532 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3533 ScalarizeVectorOp(Node->getOperand(0)));
3536 // FIXME: UNIMP! Store then reload
3537 assert(0 && "Cast from unsupported vector type not implemented yet!");
3540 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3541 Node->getOperand(0).getValueType())) {
3542 default: assert(0 && "Unknown operation action!");
3543 case TargetLowering::Expand:
3544 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3545 Node->getValueType(0));
3547 case TargetLowering::Legal:
3548 Tmp1 = LegalizeOp(Node->getOperand(0));
3549 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3555 // Conversion operators. The source and destination have different types.
3556 case ISD::SINT_TO_FP:
3557 case ISD::UINT_TO_FP: {
3558 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3559 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3561 switch (TLI.getOperationAction(Node->getOpcode(),
3562 Node->getOperand(0).getValueType())) {
3563 default: assert(0 && "Unknown operation action!");
3564 case TargetLowering::Custom:
3567 case TargetLowering::Legal:
3568 Tmp1 = LegalizeOp(Node->getOperand(0));
3569 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3571 Tmp1 = TLI.LowerOperation(Result, DAG);
3572 if (Tmp1.Val) Result = Tmp1;
3575 case TargetLowering::Expand:
3576 Result = ExpandLegalINT_TO_FP(isSigned,
3577 LegalizeOp(Node->getOperand(0)),
3578 Node->getValueType(0));
3580 case TargetLowering::Promote:
3581 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3582 Node->getValueType(0),
3588 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3589 Node->getValueType(0), Node->getOperand(0));
3592 Tmp1 = PromoteOp(Node->getOperand(0));
3594 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3595 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3597 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3598 Node->getOperand(0).getValueType());
3600 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3601 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3607 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3609 Tmp1 = LegalizeOp(Node->getOperand(0));
3610 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3613 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3615 // Since the result is legal, we should just be able to truncate the low
3616 // part of the source.
3617 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3620 Result = PromoteOp(Node->getOperand(0));
3621 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3626 case ISD::FP_TO_SINT:
3627 case ISD::FP_TO_UINT:
3628 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3630 Tmp1 = LegalizeOp(Node->getOperand(0));
3632 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3633 default: assert(0 && "Unknown operation action!");
3634 case TargetLowering::Custom:
3637 case TargetLowering::Legal:
3638 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3640 Tmp1 = TLI.LowerOperation(Result, DAG);
3641 if (Tmp1.Val) Result = Tmp1;
3644 case TargetLowering::Promote:
3645 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3646 Node->getOpcode() == ISD::FP_TO_SINT);
3648 case TargetLowering::Expand:
3649 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3650 SDOperand True, False;
3651 MVT::ValueType VT = Node->getOperand(0).getValueType();
3652 MVT::ValueType NVT = Node->getValueType(0);
3653 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1;
3654 const uint64_t zero[] = {0, 0};
3655 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3656 uint64_t x = 1ULL << ShiftAmt;
3657 (void)apf.convertFromZeroExtendedInteger
3658 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven);
3659 Tmp2 = DAG.getConstantFP(apf, VT);
3660 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3661 Node->getOperand(0), Tmp2, ISD::SETLT);
3662 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3663 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3664 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3666 False = DAG.getNode(ISD::XOR, NVT, False,
3667 DAG.getConstant(1ULL << ShiftAmt, NVT));
3668 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3671 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3677 MVT::ValueType VT = Op.getValueType();
3678 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3679 // Convert ppcf128 to i32
3680 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3681 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3682 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3683 Node->getOperand(0), DAG.getValueType(MVT::f64));
3684 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3685 DAG.getIntPtrConstant(1));
3686 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3688 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3689 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3690 Tmp2 = DAG.getConstantFP(apf, OVT);
3691 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3692 // FIXME: generated code sucks.
3693 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3694 DAG.getNode(ISD::ADD, MVT::i32,
3695 DAG.getNode(ISD::FP_TO_SINT, VT,
3696 DAG.getNode(ISD::FSUB, OVT,
3697 Node->getOperand(0), Tmp2)),
3698 DAG.getConstant(0x80000000, MVT::i32)),
3699 DAG.getNode(ISD::FP_TO_SINT, VT,
3700 Node->getOperand(0)),
3701 DAG.getCondCode(ISD::SETGE));
3705 // Convert f32 / f64 to i32 / i64.
3706 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3707 switch (Node->getOpcode()) {
3708 case ISD::FP_TO_SINT: {
3709 if (OVT == MVT::f32)
3710 LC = (VT == MVT::i32)
3711 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3712 else if (OVT == MVT::f64)
3713 LC = (VT == MVT::i32)
3714 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3715 else if (OVT == MVT::f80) {
3716 assert(VT == MVT::i64);
3717 LC = RTLIB::FPTOSINT_F80_I64;
3719 else if (OVT == MVT::ppcf128) {
3720 assert(VT == MVT::i64);
3721 LC = RTLIB::FPTOSINT_PPCF128_I64;
3725 case ISD::FP_TO_UINT: {
3726 if (OVT == MVT::f32)
3727 LC = (VT == MVT::i32)
3728 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3729 else if (OVT == MVT::f64)
3730 LC = (VT == MVT::i32)
3731 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3732 else if (OVT == MVT::f80) {
3733 LC = (VT == MVT::i32)
3734 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64;
3736 else if (OVT == MVT::ppcf128) {
3737 assert(VT == MVT::i64);
3738 LC = RTLIB::FPTOUINT_PPCF128_I64;
3742 default: assert(0 && "Unreachable!");
3745 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3746 false/*sign irrelevant*/, Dummy);
3750 Tmp1 = PromoteOp(Node->getOperand(0));
3751 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3752 Result = LegalizeOp(Result);
3757 case ISD::FP_EXTEND: {
3758 MVT::ValueType DstVT = Op.getValueType();
3759 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3760 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3761 // The only other way we can lower this is to turn it into a STORE,
3762 // LOAD pair, targetting a temporary location (a stack slot).
3763 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3766 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3767 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3769 Tmp1 = LegalizeOp(Node->getOperand(0));
3770 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3773 Tmp1 = PromoteOp(Node->getOperand(0));
3774 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3779 case ISD::FP_ROUND: {
3780 MVT::ValueType DstVT = Op.getValueType();
3781 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3782 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3783 if (SrcVT == MVT::ppcf128) {
3785 ExpandOp(Node->getOperand(0), Lo, Result);
3786 // Round it the rest of the way (e.g. to f32) if needed.
3787 if (DstVT!=MVT::f64)
3788 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3791 // The only other way we can lower this is to turn it into a STORE,
3792 // LOAD pair, targetting a temporary location (a stack slot).
3793 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3796 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3797 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3799 Tmp1 = LegalizeOp(Node->getOperand(0));
3800 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3803 Tmp1 = PromoteOp(Node->getOperand(0));
3804 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3805 Node->getOperand(1));
3810 case ISD::ANY_EXTEND:
3811 case ISD::ZERO_EXTEND:
3812 case ISD::SIGN_EXTEND:
3813 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3814 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3816 Tmp1 = LegalizeOp(Node->getOperand(0));
3817 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3820 switch (Node->getOpcode()) {
3821 case ISD::ANY_EXTEND:
3822 Tmp1 = PromoteOp(Node->getOperand(0));
3823 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3825 case ISD::ZERO_EXTEND:
3826 Result = PromoteOp(Node->getOperand(0));
3827 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3828 Result = DAG.getZeroExtendInReg(Result,
3829 Node->getOperand(0).getValueType());
3831 case ISD::SIGN_EXTEND:
3832 Result = PromoteOp(Node->getOperand(0));
3833 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3834 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3836 DAG.getValueType(Node->getOperand(0).getValueType()));
3841 case ISD::FP_ROUND_INREG:
3842 case ISD::SIGN_EXTEND_INREG: {
3843 Tmp1 = LegalizeOp(Node->getOperand(0));
3844 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3846 // If this operation is not supported, convert it to a shl/shr or load/store
3848 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3849 default: assert(0 && "This action not supported for this op yet!");
3850 case TargetLowering::Legal:
3851 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3853 case TargetLowering::Expand:
3854 // If this is an integer extend and shifts are supported, do that.
3855 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3856 // NOTE: we could fall back on load/store here too for targets without
3857 // SAR. However, it is doubtful that any exist.
3858 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3859 MVT::getSizeInBits(ExtraVT);
3860 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3861 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3862 Node->getOperand(0), ShiftCst);
3863 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3865 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3866 // The only way we can lower this is to turn it into a TRUNCSTORE,
3867 // EXTLOAD pair, targetting a temporary location (a stack slot).
3869 // NOTE: there is a choice here between constantly creating new stack
3870 // slots and always reusing the same one. We currently always create
3871 // new ones, as reuse may inhibit scheduling.
3872 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3873 Node->getValueType(0));
3875 assert(0 && "Unknown op");
3881 case ISD::TRAMPOLINE: {
3883 for (unsigned i = 0; i != 6; ++i)
3884 Ops[i] = LegalizeOp(Node->getOperand(i));
3885 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3886 // The only option for this node is to custom lower it.
3887 Result = TLI.LowerOperation(Result, DAG);
3888 assert(Result.Val && "Should always custom lower!");
3890 // Since trampoline produces two values, make sure to remember that we
3891 // legalized both of them.
3892 Tmp1 = LegalizeOp(Result.getValue(1));
3893 Result = LegalizeOp(Result);
3894 AddLegalizedOperand(SDOperand(Node, 0), Result);
3895 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3896 return Op.ResNo ? Tmp1 : Result;
3898 case ISD::FLT_ROUNDS: {
3899 MVT::ValueType VT = Node->getValueType(0);
3900 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3901 default: assert(0 && "This action not supported for this op yet!");
3902 case TargetLowering::Custom:
3903 Result = TLI.LowerOperation(Op, DAG);
3904 if (Result.Val) break;
3906 case TargetLowering::Legal:
3907 // If this operation is not supported, lower it to constant 1
3908 Result = DAG.getConstant(1, VT);
3913 MVT::ValueType VT = Node->getValueType(0);
3914 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3915 default: assert(0 && "This action not supported for this op yet!");
3916 case TargetLowering::Legal:
3917 Tmp1 = LegalizeOp(Node->getOperand(0));
3918 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3920 case TargetLowering::Custom:
3921 Result = TLI.LowerOperation(Op, DAG);
3922 if (Result.Val) break;
3924 case TargetLowering::Expand:
3925 // If this operation is not supported, lower it to 'abort()' call
3926 Tmp1 = LegalizeOp(Node->getOperand(0));
3927 TargetLowering::ArgListTy Args;
3928 std::pair<SDOperand,SDOperand> CallResult =
3929 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
3930 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3932 Result = CallResult.second;
3939 assert(Result.getValueType() == Op.getValueType() &&
3940 "Bad legalization!");
3942 // Make sure that the generated code is itself legal.
3944 Result = LegalizeOp(Result);
3946 // Note that LegalizeOp may be reentered even from single-use nodes, which
3947 // means that we always must cache transformed nodes.
3948 AddLegalizedOperand(Op, Result);
3952 /// PromoteOp - Given an operation that produces a value in an invalid type,
3953 /// promote it to compute the value into a larger type. The produced value will
3954 /// have the correct bits for the low portion of the register, but no guarantee
3955 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3956 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3957 MVT::ValueType VT = Op.getValueType();
3958 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3959 assert(getTypeAction(VT) == Promote &&
3960 "Caller should expand or legalize operands that are not promotable!");
3961 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3962 "Cannot promote to smaller type!");
3964 SDOperand Tmp1, Tmp2, Tmp3;
3966 SDNode *Node = Op.Val;
3968 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3969 if (I != PromotedNodes.end()) return I->second;
3971 switch (Node->getOpcode()) {
3972 case ISD::CopyFromReg:
3973 assert(0 && "CopyFromReg must be legal!");
3976 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
3978 assert(0 && "Do not know how to promote this operator!");
3981 Result = DAG.getNode(ISD::UNDEF, NVT);
3985 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3987 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3988 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3990 case ISD::ConstantFP:
3991 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3992 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3996 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3997 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3998 Node->getOperand(1), Node->getOperand(2));
4002 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4004 Result = LegalizeOp(Node->getOperand(0));
4005 assert(Result.getValueType() >= NVT &&
4006 "This truncation doesn't make sense!");
4007 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
4008 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4011 // The truncation is not required, because we don't guarantee anything
4012 // about high bits anyway.
4013 Result = PromoteOp(Node->getOperand(0));
4016 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4017 // Truncate the low part of the expanded value to the result type
4018 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4021 case ISD::SIGN_EXTEND:
4022 case ISD::ZERO_EXTEND:
4023 case ISD::ANY_EXTEND:
4024 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4025 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4027 // Input is legal? Just do extend all the way to the larger type.
4028 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4031 // Promote the reg if it's smaller.
4032 Result = PromoteOp(Node->getOperand(0));
4033 // The high bits are not guaranteed to be anything. Insert an extend.
4034 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4035 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4036 DAG.getValueType(Node->getOperand(0).getValueType()));
4037 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4038 Result = DAG.getZeroExtendInReg(Result,
4039 Node->getOperand(0).getValueType());
4043 case ISD::BIT_CONVERT:
4044 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4045 Node->getValueType(0));
4046 Result = PromoteOp(Result);
4049 case ISD::FP_EXTEND:
4050 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4052 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4053 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4054 case Promote: assert(0 && "Unreachable with 2 FP types!");
4056 if (Node->getConstantOperandVal(1) == 0) {
4057 // Input is legal? Do an FP_ROUND_INREG.
4058 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4059 DAG.getValueType(VT));
4061 // Just remove the truncate, it isn't affecting the value.
4062 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4063 Node->getOperand(1));
4068 case ISD::SINT_TO_FP:
4069 case ISD::UINT_TO_FP:
4070 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4072 // No extra round required here.
4073 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4077 Result = PromoteOp(Node->getOperand(0));
4078 if (Node->getOpcode() == ISD::SINT_TO_FP)
4079 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4081 DAG.getValueType(Node->getOperand(0).getValueType()));
4083 Result = DAG.getZeroExtendInReg(Result,
4084 Node->getOperand(0).getValueType());
4085 // No extra round required here.
4086 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4089 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4090 Node->getOperand(0));
4091 // Round if we cannot tolerate excess precision.
4092 if (NoExcessFPPrecision)
4093 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4094 DAG.getValueType(VT));
4099 case ISD::SIGN_EXTEND_INREG:
4100 Result = PromoteOp(Node->getOperand(0));
4101 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4102 Node->getOperand(1));
4104 case ISD::FP_TO_SINT:
4105 case ISD::FP_TO_UINT:
4106 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4109 Tmp1 = Node->getOperand(0);
4112 // The input result is prerounded, so we don't have to do anything
4114 Tmp1 = PromoteOp(Node->getOperand(0));
4117 // If we're promoting a UINT to a larger size, check to see if the new node
4118 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4119 // we can use that instead. This allows us to generate better code for
4120 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4121 // legal, such as PowerPC.
4122 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4123 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4124 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4125 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4126 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4128 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4134 Tmp1 = PromoteOp(Node->getOperand(0));
4135 assert(Tmp1.getValueType() == NVT);
4136 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4137 // NOTE: we do not have to do any extra rounding here for
4138 // NoExcessFPPrecision, because we know the input will have the appropriate
4139 // precision, and these operations don't modify precision at all.
4145 Tmp1 = PromoteOp(Node->getOperand(0));
4146 assert(Tmp1.getValueType() == NVT);
4147 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4148 if (NoExcessFPPrecision)
4149 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4150 DAG.getValueType(VT));
4154 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4155 // directly as well, which may be better.
4156 Tmp1 = PromoteOp(Node->getOperand(0));
4157 assert(Tmp1.getValueType() == NVT);
4158 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4159 if (NoExcessFPPrecision)
4160 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4161 DAG.getValueType(VT));
4171 // The input may have strange things in the top bits of the registers, but
4172 // these operations don't care. They may have weird bits going out, but
4173 // that too is okay if they are integer operations.
4174 Tmp1 = PromoteOp(Node->getOperand(0));
4175 Tmp2 = PromoteOp(Node->getOperand(1));
4176 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4177 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4182 Tmp1 = PromoteOp(Node->getOperand(0));
4183 Tmp2 = PromoteOp(Node->getOperand(1));
4184 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4185 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4187 // Floating point operations will give excess precision that we may not be
4188 // able to tolerate. If we DO allow excess precision, just leave it,
4189 // otherwise excise it.
4190 // FIXME: Why would we need to round FP ops more than integer ones?
4191 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4192 if (NoExcessFPPrecision)
4193 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4194 DAG.getValueType(VT));
4199 // These operators require that their input be sign extended.
4200 Tmp1 = PromoteOp(Node->getOperand(0));
4201 Tmp2 = PromoteOp(Node->getOperand(1));
4202 if (MVT::isInteger(NVT)) {
4203 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4204 DAG.getValueType(VT));
4205 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4206 DAG.getValueType(VT));
4208 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4210 // Perform FP_ROUND: this is probably overly pessimistic.
4211 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
4212 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4213 DAG.getValueType(VT));
4217 case ISD::FCOPYSIGN:
4218 // These operators require that their input be fp extended.
4219 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4220 case Expand: assert(0 && "not implemented");
4221 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4222 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4224 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4225 case Expand: assert(0 && "not implemented");
4226 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4227 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4229 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4231 // Perform FP_ROUND: this is probably overly pessimistic.
4232 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4233 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4234 DAG.getValueType(VT));
4239 // These operators require that their input be zero extended.
4240 Tmp1 = PromoteOp(Node->getOperand(0));
4241 Tmp2 = PromoteOp(Node->getOperand(1));
4242 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
4243 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4244 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4245 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4249 Tmp1 = PromoteOp(Node->getOperand(0));
4250 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4253 // The input value must be properly sign extended.
4254 Tmp1 = PromoteOp(Node->getOperand(0));
4255 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4256 DAG.getValueType(VT));
4257 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4260 // The input value must be properly zero extended.
4261 Tmp1 = PromoteOp(Node->getOperand(0));
4262 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4263 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4267 Tmp1 = Node->getOperand(0); // Get the chain.
4268 Tmp2 = Node->getOperand(1); // Get the pointer.
4269 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4270 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4271 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
4273 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
4274 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
4275 SV->getValue(), SV->getOffset());
4276 // Increment the pointer, VAList, to the next vaarg
4277 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4278 DAG.getConstant(MVT::getSizeInBits(VT)/8,
4279 TLI.getPointerTy()));
4280 // Store the incremented VAList to the legalized pointer
4281 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
4283 // Load the actual argument out of the pointer VAList
4284 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4286 // Remember that we legalized the chain.
4287 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4291 LoadSDNode *LD = cast<LoadSDNode>(Node);
4292 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4293 ? ISD::EXTLOAD : LD->getExtensionType();
4294 Result = DAG.getExtLoad(ExtType, NVT,
4295 LD->getChain(), LD->getBasePtr(),
4296 LD->getSrcValue(), LD->getSrcValueOffset(),
4299 LD->getAlignment());
4300 // Remember that we legalized the chain.
4301 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4305 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4306 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4307 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
4309 case ISD::SELECT_CC:
4310 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4311 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4312 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4313 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4316 Tmp1 = Node->getOperand(0);
4317 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4318 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4319 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4320 DAG.getConstant(MVT::getSizeInBits(NVT) -
4321 MVT::getSizeInBits(VT),
4322 TLI.getShiftAmountTy()));
4327 // Zero extend the argument
4328 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4329 // Perform the larger operation, then subtract if needed.
4330 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4331 switch(Node->getOpcode()) {
4336 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4337 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
4338 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
4340 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4341 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
4344 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4345 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4346 DAG.getConstant(MVT::getSizeInBits(NVT) -
4347 MVT::getSizeInBits(VT), NVT));
4351 case ISD::EXTRACT_SUBVECTOR:
4352 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4354 case ISD::EXTRACT_VECTOR_ELT:
4355 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4359 assert(Result.Val && "Didn't set a result!");
4361 // Make sure the result is itself legal.
4362 Result = LegalizeOp(Result);
4364 // Remember that we promoted this!
4365 AddPromotedOperand(Op, Result);
4369 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4370 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4371 /// based on the vector type. The return type of this matches the element type
4372 /// of the vector, which may not be legal for the target.
4373 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4374 // We know that operand #0 is the Vec vector. If the index is a constant
4375 // or if the invec is a supported hardware type, we can use it. Otherwise,
4376 // lower to a store then an indexed load.
4377 SDOperand Vec = Op.getOperand(0);
4378 SDOperand Idx = Op.getOperand(1);
4380 MVT::ValueType TVT = Vec.getValueType();
4381 unsigned NumElems = MVT::getVectorNumElements(TVT);
4383 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4384 default: assert(0 && "This action is not supported yet!");
4385 case TargetLowering::Custom: {
4386 Vec = LegalizeOp(Vec);
4387 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4388 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4393 case TargetLowering::Legal:
4394 if (isTypeLegal(TVT)) {
4395 Vec = LegalizeOp(Vec);
4396 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4400 case TargetLowering::Expand:
4404 if (NumElems == 1) {
4405 // This must be an access of the only element. Return it.
4406 Op = ScalarizeVectorOp(Vec);
4407 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4408 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4409 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4411 SplitVectorOp(Vec, Lo, Hi);
4412 if (CIdx->getValue() < NumLoElts) {
4416 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4417 Idx.getValueType());
4420 // It's now an extract from the appropriate high or low part. Recurse.
4421 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4422 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4424 // Store the value to a temporary stack slot, then LOAD the scalar
4425 // element back out.
4426 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4427 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4429 // Add the offset to the index.
4430 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
4431 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4432 DAG.getConstant(EltSize, Idx.getValueType()));
4434 if (MVT::getSizeInBits(Idx.getValueType()) >
4435 MVT::getSizeInBits(TLI.getPointerTy()))
4436 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4438 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4440 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4442 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4447 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4448 /// we assume the operation can be split if it is not already legal.
4449 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4450 // We know that operand #0 is the Vec vector. For now we assume the index
4451 // is a constant and that the extracted result is a supported hardware type.
4452 SDOperand Vec = Op.getOperand(0);
4453 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4455 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
4457 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
4458 // This must be an access of the desired vector length. Return it.
4462 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4464 SplitVectorOp(Vec, Lo, Hi);
4465 if (CIdx->getValue() < NumElems/2) {
4469 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4472 // It's now an extract from the appropriate high or low part. Recurse.
4473 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4474 return ExpandEXTRACT_SUBVECTOR(Op);
4477 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4478 /// with condition CC on the current target. This usually involves legalizing
4479 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4480 /// there may be no choice but to create a new SetCC node to represent the
4481 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4482 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4483 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4486 SDOperand Tmp1, Tmp2, Tmp3, Result;
4488 switch (getTypeAction(LHS.getValueType())) {
4490 Tmp1 = LegalizeOp(LHS); // LHS
4491 Tmp2 = LegalizeOp(RHS); // RHS
4494 Tmp1 = PromoteOp(LHS); // LHS
4495 Tmp2 = PromoteOp(RHS); // RHS
4497 // If this is an FP compare, the operands have already been extended.
4498 if (MVT::isInteger(LHS.getValueType())) {
4499 MVT::ValueType VT = LHS.getValueType();
4500 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4502 // Otherwise, we have to insert explicit sign or zero extends. Note
4503 // that we could insert sign extends for ALL conditions, but zero extend
4504 // is cheaper on many machines (an AND instead of two shifts), so prefer
4506 switch (cast<CondCodeSDNode>(CC)->get()) {
4507 default: assert(0 && "Unknown integer comparison!");
4514 // ALL of these operations will work if we either sign or zero extend
4515 // the operands (including the unsigned comparisons!). Zero extend is
4516 // usually a simpler/cheaper operation, so prefer it.
4517 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4518 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4524 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4525 DAG.getValueType(VT));
4526 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4527 DAG.getValueType(VT));
4533 MVT::ValueType VT = LHS.getValueType();
4534 if (VT == MVT::f32 || VT == MVT::f64) {
4535 // Expand into one or more soft-fp libcall(s).
4536 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4537 switch (cast<CondCodeSDNode>(CC)->get()) {
4540 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4544 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4548 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4552 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4556 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4560 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4563 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4566 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4569 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4570 switch (cast<CondCodeSDNode>(CC)->get()) {
4572 // SETONE = SETOLT | SETOGT
4573 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4576 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4579 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4582 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4585 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4588 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4590 default: assert(0 && "Unsupported FP setcc!");
4595 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4596 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4597 false /*sign irrelevant*/, Dummy);
4598 Tmp2 = DAG.getConstant(0, MVT::i32);
4599 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4600 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4601 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4602 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4603 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4604 false /*sign irrelevant*/, Dummy);
4605 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4606 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4607 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4615 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4616 ExpandOp(LHS, LHSLo, LHSHi);
4617 ExpandOp(RHS, RHSLo, RHSHi);
4618 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4620 if (VT==MVT::ppcf128) {
4621 // FIXME: This generated code sucks. We want to generate
4622 // FCMP crN, hi1, hi2
4624 // FCMP crN, lo1, lo2
4625 // The following can be improved, but not that much.
4626 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4627 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
4628 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4629 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
4630 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
4631 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4632 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4641 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4642 if (RHSCST->isAllOnesValue()) {
4643 // Comparison to -1.
4644 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4649 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4650 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4651 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4652 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4655 // If this is a comparison of the sign bit, just look at the top part.
4657 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4658 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4659 CST->getValue() == 0) || // X < 0
4660 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4661 CST->isAllOnesValue())) { // X > -1
4667 // FIXME: This generated code sucks.
4668 ISD::CondCode LowCC;
4670 default: assert(0 && "Unknown integer setcc!");
4672 case ISD::SETULT: LowCC = ISD::SETULT; break;
4674 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4676 case ISD::SETULE: LowCC = ISD::SETULE; break;
4678 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4681 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4682 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4683 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4685 // NOTE: on targets without efficient SELECT of bools, we can always use
4686 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4687 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4688 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4689 false, DagCombineInfo);
4691 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4692 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4693 CCCode, false, DagCombineInfo);
4695 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC);
4697 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4698 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4699 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4700 (Tmp2C && Tmp2C->getValue() == 0 &&
4701 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4702 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4703 (Tmp2C && Tmp2C->getValue() == 1 &&
4704 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4705 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4706 // low part is known false, returns high part.
4707 // For LE / GE, if high part is known false, ignore the low part.
4708 // For LT / GT, if high part is known true, ignore the low part.
4712 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4713 ISD::SETEQ, false, DagCombineInfo);
4715 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4716 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4717 Result, Tmp1, Tmp2));
4728 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4729 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4730 /// a load from the stack slot to DestVT, extending it if needed.
4731 /// The resultant code need not be legal.
4732 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4733 MVT::ValueType SlotVT,
4734 MVT::ValueType DestVT) {
4735 // Create the stack frame object.
4736 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
4738 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType());
4739 unsigned SlotSize = MVT::getSizeInBits(SlotVT);
4740 unsigned DestSize = MVT::getSizeInBits(DestVT);
4742 // Emit a store to the stack slot. Use a truncstore if the input value is
4743 // later than DestVT.
4745 if (SrcSize > SlotSize)
4746 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0,SlotVT);
4748 assert(SrcSize == SlotSize && "Invalid store");
4749 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
4752 // Result is a load from the stack slot.
4753 if (SlotSize == DestSize)
4754 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4756 assert(SlotSize < DestSize && "Unknown extension!");
4757 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT);
4760 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4761 // Create a vector sized/aligned stack slot, store the value to element #0,
4762 // then load the whole vector back out.
4763 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4764 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4766 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
4770 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4771 /// support the operation, but do support the resultant vector type.
4772 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4774 // If the only non-undef value is the low element, turn this into a
4775 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4776 unsigned NumElems = Node->getNumOperands();
4777 bool isOnlyLowElement = true;
4778 SDOperand SplatValue = Node->getOperand(0);
4779 std::map<SDOperand, std::vector<unsigned> > Values;
4780 Values[SplatValue].push_back(0);
4781 bool isConstant = true;
4782 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4783 SplatValue.getOpcode() != ISD::UNDEF)
4786 for (unsigned i = 1; i < NumElems; ++i) {
4787 SDOperand V = Node->getOperand(i);
4788 Values[V].push_back(i);
4789 if (V.getOpcode() != ISD::UNDEF)
4790 isOnlyLowElement = false;
4791 if (SplatValue != V)
4792 SplatValue = SDOperand(0,0);
4794 // If this isn't a constant element or an undef, we can't use a constant
4796 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4797 V.getOpcode() != ISD::UNDEF)
4801 if (isOnlyLowElement) {
4802 // If the low element is an undef too, then this whole things is an undef.
4803 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4804 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4805 // Otherwise, turn this into a scalar_to_vector node.
4806 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4807 Node->getOperand(0));
4810 // If all elements are constants, create a load from the constant pool.
4812 MVT::ValueType VT = Node->getValueType(0);
4814 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4815 std::vector<Constant*> CV;
4816 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4817 if (ConstantFPSDNode *V =
4818 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4819 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4820 } else if (ConstantSDNode *V =
4821 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4822 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4824 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4825 CV.push_back(UndefValue::get(OpNTy));
4828 Constant *CP = ConstantVector::get(CV);
4829 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4830 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
4833 if (SplatValue.Val) { // Splat of one value?
4834 // Build the shuffle constant vector: <0, 0, 0, 0>
4835 MVT::ValueType MaskVT =
4836 MVT::getIntVectorWithNumElements(NumElems);
4837 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4838 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4839 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4840 &ZeroVec[0], ZeroVec.size());
4842 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4843 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4844 // Get the splatted value into the low element of a vector register.
4845 SDOperand LowValVec =
4846 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4848 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4849 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4850 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4855 // If there are only two unique elements, we may be able to turn this into a
4857 if (Values.size() == 2) {
4858 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4859 MVT::ValueType MaskVT =
4860 MVT::getIntVectorWithNumElements(NumElems);
4861 std::vector<SDOperand> MaskVec(NumElems);
4863 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4864 E = Values.end(); I != E; ++I) {
4865 for (std::vector<unsigned>::iterator II = I->second.begin(),
4866 EE = I->second.end(); II != EE; ++II)
4867 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4870 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4871 &MaskVec[0], MaskVec.size());
4873 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4874 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4875 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4876 SmallVector<SDOperand, 8> Ops;
4877 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4878 E = Values.end(); I != E; ++I) {
4879 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4883 Ops.push_back(ShuffleMask);
4885 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4886 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4887 &Ops[0], Ops.size());
4891 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4892 // aligned object on the stack, store each element into it, then load
4893 // the result as a vector.
4894 MVT::ValueType VT = Node->getValueType(0);
4895 // Create the stack frame object.
4896 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
4898 // Emit a store of each element to the stack slot.
4899 SmallVector<SDOperand, 8> Stores;
4900 unsigned TypeByteSize =
4901 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4902 // Store (in the right endianness) the elements to memory.
4903 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4904 // Ignore undef elements.
4905 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4907 unsigned Offset = TypeByteSize*i;
4909 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4910 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4912 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4916 SDOperand StoreChain;
4917 if (!Stores.empty()) // Not all undef elements?
4918 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4919 &Stores[0], Stores.size());
4921 StoreChain = DAG.getEntryNode();
4923 // Result is a load from the stack slot.
4924 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4927 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4928 SDOperand Op, SDOperand Amt,
4929 SDOperand &Lo, SDOperand &Hi) {
4930 // Expand the subcomponents.
4931 SDOperand LHSL, LHSH;
4932 ExpandOp(Op, LHSL, LHSH);
4934 SDOperand Ops[] = { LHSL, LHSH, Amt };
4935 MVT::ValueType VT = LHSL.getValueType();
4936 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4937 Hi = Lo.getValue(1);
4941 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4942 /// smaller elements. If we can't find a way that is more efficient than a
4943 /// libcall on this target, return false. Otherwise, return true with the
4944 /// low-parts expanded into Lo and Hi.
4945 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4946 SDOperand &Lo, SDOperand &Hi) {
4947 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4948 "This is not a shift!");
4950 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4951 SDOperand ShAmt = LegalizeOp(Amt);
4952 MVT::ValueType ShTy = ShAmt.getValueType();
4953 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4954 unsigned NVTBits = MVT::getSizeInBits(NVT);
4956 // Handle the case when Amt is an immediate.
4957 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4958 unsigned Cst = CN->getValue();
4959 // Expand the incoming operand to be shifted, so that we have its parts
4961 ExpandOp(Op, InL, InH);
4965 Lo = DAG.getConstant(0, NVT);
4966 Hi = DAG.getConstant(0, NVT);
4967 } else if (Cst > NVTBits) {
4968 Lo = DAG.getConstant(0, NVT);
4969 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4970 } else if (Cst == NVTBits) {
4971 Lo = DAG.getConstant(0, NVT);
4974 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4975 Hi = DAG.getNode(ISD::OR, NVT,
4976 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4977 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4982 Lo = DAG.getConstant(0, NVT);
4983 Hi = DAG.getConstant(0, NVT);
4984 } else if (Cst > NVTBits) {
4985 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
4986 Hi = DAG.getConstant(0, NVT);
4987 } else if (Cst == NVTBits) {
4989 Hi = DAG.getConstant(0, NVT);
4991 Lo = DAG.getNode(ISD::OR, NVT,
4992 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4993 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4994 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
4999 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5000 DAG.getConstant(NVTBits-1, ShTy));
5001 } else if (Cst > NVTBits) {
5002 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5003 DAG.getConstant(Cst-NVTBits, ShTy));
5004 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5005 DAG.getConstant(NVTBits-1, ShTy));
5006 } else if (Cst == NVTBits) {
5008 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5009 DAG.getConstant(NVTBits-1, ShTy));
5011 Lo = DAG.getNode(ISD::OR, NVT,
5012 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5013 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5014 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5020 // Okay, the shift amount isn't constant. However, if we can tell that it is
5021 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5022 uint64_t Mask = NVTBits, KnownZero, KnownOne;
5023 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5025 // If we know that the high bit of the shift amount is one, then we can do
5026 // this as a couple of simple shifts.
5027 if (KnownOne & Mask) {
5028 // Mask out the high bit, which we know is set.
5029 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5030 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5032 // Expand the incoming operand to be shifted, so that we have its parts
5034 ExpandOp(Op, InL, InH);
5037 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5038 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5041 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5042 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5045 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5046 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5047 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5052 // If we know that the high bit of the shift amount is zero, then we can do
5053 // this as a couple of simple shifts.
5054 if (KnownZero & Mask) {
5056 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5057 DAG.getConstant(NVTBits, Amt.getValueType()),
5060 // Expand the incoming operand to be shifted, so that we have its parts
5062 ExpandOp(Op, InL, InH);
5065 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5066 Hi = DAG.getNode(ISD::OR, NVT,
5067 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5068 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5071 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5072 Lo = DAG.getNode(ISD::OR, NVT,
5073 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5074 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5077 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5078 Lo = DAG.getNode(ISD::OR, NVT,
5079 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5080 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5089 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5090 // does not fit into a register, return the lo part and set the hi part to the
5091 // by-reg argument. If it does fit into a single register, return the result
5092 // and leave the Hi part unset.
5093 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
5094 bool isSigned, SDOperand &Hi) {
5095 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5096 // The input chain to this libcall is the entry node of the function.
5097 // Legalizing the call will automatically add the previous call to the
5099 SDOperand InChain = DAG.getEntryNode();
5101 TargetLowering::ArgListTy Args;
5102 TargetLowering::ArgListEntry Entry;
5103 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5104 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
5105 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
5106 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5107 Entry.isSExt = isSigned;
5108 Args.push_back(Entry);
5110 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
5112 // Splice the libcall in wherever FindInputOutputChains tells us to.
5113 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
5114 std::pair<SDOperand,SDOperand> CallInfo =
5115 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
5118 // Legalize the call sequence, starting with the chain. This will advance
5119 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5120 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5121 LegalizeOp(CallInfo.second);
5123 switch (getTypeAction(CallInfo.first.getValueType())) {
5124 default: assert(0 && "Unknown thing");
5126 Result = CallInfo.first;
5129 ExpandOp(CallInfo.first, Result, Hi);
5136 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5138 SDOperand SelectionDAGLegalize::
5139 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
5140 assert(getTypeAction(Source.getValueType()) == Expand &&
5141 "This is not an expansion!");
5142 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
5145 assert(Source.getValueType() == MVT::i64 &&
5146 "This only works for 64-bit -> FP");
5147 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
5148 // incoming integer is set. To handle this, we dynamically test to see if
5149 // it is set, and, if so, add a fudge factor.
5151 ExpandOp(Source, Lo, Hi);
5153 // If this is unsigned, and not supported, first perform the conversion to
5154 // signed, then adjust the result if the sign bit is set.
5155 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
5156 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
5158 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
5159 DAG.getConstant(0, Hi.getValueType()),
5161 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5162 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5163 SignSet, Four, Zero);
5164 uint64_t FF = 0x5f800000ULL;
5165 if (TLI.isLittleEndian()) FF <<= 32;
5166 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5168 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5169 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5170 SDOperand FudgeInReg;
5171 if (DestTy == MVT::f32)
5172 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
5173 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
5174 // FIXME: Avoid the extend by construction the right constantpool?
5175 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5176 CPIdx, NULL, 0, MVT::f32);
5178 assert(0 && "Unexpected conversion");
5180 MVT::ValueType SCVT = SignedConv.getValueType();
5181 if (SCVT != DestTy) {
5182 // Destination type needs to be expanded as well. The FADD now we are
5183 // constructing will be expanded into a libcall.
5184 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
5185 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
5186 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
5187 SignedConv, SignedConv.getValue(1));
5189 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5191 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5194 // Check to see if the target has a custom way to lower this. If so, use it.
5195 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
5196 default: assert(0 && "This action not implemented for this operation!");
5197 case TargetLowering::Legal:
5198 case TargetLowering::Expand:
5199 break; // This case is handled below.
5200 case TargetLowering::Custom: {
5201 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5204 return LegalizeOp(NV);
5205 break; // The target decided this was legal after all
5209 // Expand the source, then glue it back together for the call. We must expand
5210 // the source in case it is shared (this pass of legalize must traverse it).
5211 SDOperand SrcLo, SrcHi;
5212 ExpandOp(Source, SrcLo, SrcHi);
5213 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
5216 if (DestTy == MVT::f32)
5217 LC = RTLIB::SINTTOFP_I64_F32;
5219 assert(DestTy == MVT::f64 && "Unknown fp value type!");
5220 LC = RTLIB::SINTTOFP_I64_F64;
5223 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
5224 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5225 SDOperand UnusedHiPart;
5226 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
5230 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5231 /// INT_TO_FP operation of the specified operand when the target requests that
5232 /// we expand it. At this point, we know that the result and operand types are
5233 /// legal for the target.
5234 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5236 MVT::ValueType DestVT) {
5237 if (Op0.getValueType() == MVT::i32) {
5238 // simple 32-bit [signed|unsigned] integer to float/double expansion
5240 // Get the stack frame index of a 8 byte buffer.
5241 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5243 // word offset constant for Hi/Lo address computation
5244 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5245 // set up Hi and Lo (into buffer) address based on endian
5246 SDOperand Hi = StackSlot;
5247 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5248 if (TLI.isLittleEndian())
5251 // if signed map to unsigned space
5252 SDOperand Op0Mapped;
5254 // constant used to invert sign bit (signed to unsigned mapping)
5255 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5256 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5260 // store the lo of the constructed double - based on integer input
5261 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5262 Op0Mapped, Lo, NULL, 0);
5263 // initial hi portion of constructed double
5264 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5265 // store the hi of the constructed double - biased exponent
5266 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5267 // load the constructed double
5268 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5269 // FP constant to bias correct the final result
5270 SDOperand Bias = DAG.getConstantFP(isSigned ?
5271 BitsToDouble(0x4330000080000000ULL)
5272 : BitsToDouble(0x4330000000000000ULL),
5274 // subtract the bias
5275 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5278 // handle final rounding
5279 if (DestVT == MVT::f64) {
5282 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
5283 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5284 DAG.getIntPtrConstant(0));
5285 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
5286 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5290 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5291 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5293 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
5294 DAG.getConstant(0, Op0.getValueType()),
5296 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5297 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5298 SignSet, Four, Zero);
5300 // If the sign bit of the integer is set, the large number will be treated
5301 // as a negative number. To counteract this, the dynamic code adds an
5302 // offset depending on the data type.
5304 switch (Op0.getValueType()) {
5305 default: assert(0 && "Unsupported integer type!");
5306 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5307 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5308 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5309 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5311 if (TLI.isLittleEndian()) FF <<= 32;
5312 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5314 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5315 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5316 SDOperand FudgeInReg;
5317 if (DestVT == MVT::f32)
5318 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
5320 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5321 DAG.getEntryNode(), CPIdx,
5322 NULL, 0, MVT::f32));
5325 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5328 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5329 /// *INT_TO_FP operation of the specified operand when the target requests that
5330 /// we promote it. At this point, we know that the result and operand types are
5331 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5332 /// operation that takes a larger input.
5333 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5334 MVT::ValueType DestVT,
5336 // First step, figure out the appropriate *INT_TO_FP operation to use.
5337 MVT::ValueType NewInTy = LegalOp.getValueType();
5339 unsigned OpToUse = 0;
5341 // Scan for the appropriate larger type to use.
5343 NewInTy = (MVT::ValueType)(NewInTy+1);
5344 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
5346 // If the target supports SINT_TO_FP of this type, use it.
5347 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5349 case TargetLowering::Legal:
5350 if (!TLI.isTypeLegal(NewInTy))
5351 break; // Can't use this datatype.
5353 case TargetLowering::Custom:
5354 OpToUse = ISD::SINT_TO_FP;
5358 if (isSigned) continue;
5360 // If the target supports UINT_TO_FP of this type, use it.
5361 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5363 case TargetLowering::Legal:
5364 if (!TLI.isTypeLegal(NewInTy))
5365 break; // Can't use this datatype.
5367 case TargetLowering::Custom:
5368 OpToUse = ISD::UINT_TO_FP;
5373 // Otherwise, try a larger type.
5376 // Okay, we found the operation and type to use. Zero extend our input to the
5377 // desired type then run the operation on it.
5378 return DAG.getNode(OpToUse, DestVT,
5379 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5383 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5384 /// FP_TO_*INT operation of the specified operand when the target requests that
5385 /// we promote it. At this point, we know that the result and operand types are
5386 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5387 /// operation that returns a larger result.
5388 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5389 MVT::ValueType DestVT,
5391 // First step, figure out the appropriate FP_TO*INT operation to use.
5392 MVT::ValueType NewOutTy = DestVT;
5394 unsigned OpToUse = 0;
5396 // Scan for the appropriate larger type to use.
5398 NewOutTy = (MVT::ValueType)(NewOutTy+1);
5399 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
5401 // If the target supports FP_TO_SINT returning this type, use it.
5402 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5404 case TargetLowering::Legal:
5405 if (!TLI.isTypeLegal(NewOutTy))
5406 break; // Can't use this datatype.
5408 case TargetLowering::Custom:
5409 OpToUse = ISD::FP_TO_SINT;
5414 // If the target supports FP_TO_UINT of this type, use it.
5415 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5417 case TargetLowering::Legal:
5418 if (!TLI.isTypeLegal(NewOutTy))
5419 break; // Can't use this datatype.
5421 case TargetLowering::Custom:
5422 OpToUse = ISD::FP_TO_UINT;
5427 // Otherwise, try a larger type.
5431 // Okay, we found the operation and type to use.
5432 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5434 // If the operation produces an invalid type, it must be custom lowered. Use
5435 // the target lowering hooks to expand it. Just keep the low part of the
5436 // expanded operation, we know that we're truncating anyway.
5437 if (getTypeAction(NewOutTy) == Expand) {
5438 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
5439 assert(Operation.Val && "Didn't return anything");
5442 // Truncate the result of the extended FP_TO_*INT operation to the desired
5444 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5447 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5449 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5450 MVT::ValueType VT = Op.getValueType();
5451 MVT::ValueType SHVT = TLI.getShiftAmountTy();
5452 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5454 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5456 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5457 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5458 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5460 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5461 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5462 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5463 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5464 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5465 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5466 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5467 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5468 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5470 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5471 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5472 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5473 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5474 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5475 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5476 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5477 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5478 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5479 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5480 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5481 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5482 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5483 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5484 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5485 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5486 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5487 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5488 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5489 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5490 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5494 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5496 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5498 default: assert(0 && "Cannot expand this yet!");
5500 static const uint64_t mask[6] = {
5501 0x5555555555555555ULL, 0x3333333333333333ULL,
5502 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5503 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5505 MVT::ValueType VT = Op.getValueType();
5506 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5507 unsigned len = MVT::getSizeInBits(VT);
5508 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5509 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5510 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5511 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5512 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5513 DAG.getNode(ISD::AND, VT,
5514 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5519 // for now, we do this:
5520 // x = x | (x >> 1);
5521 // x = x | (x >> 2);
5523 // x = x | (x >>16);
5524 // x = x | (x >>32); // for 64-bit input
5525 // return popcount(~x);
5527 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5528 MVT::ValueType VT = Op.getValueType();
5529 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5530 unsigned len = MVT::getSizeInBits(VT);
5531 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5532 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5533 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5535 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5536 return DAG.getNode(ISD::CTPOP, VT, Op);
5539 // for now, we use: { return popcount(~x & (x - 1)); }
5540 // unless the target has ctlz but not ctpop, in which case we use:
5541 // { return 32 - nlz(~x & (x-1)); }
5542 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5543 MVT::ValueType VT = Op.getValueType();
5544 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5545 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5546 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5547 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5548 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5549 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5550 TLI.isOperationLegal(ISD::CTLZ, VT))
5551 return DAG.getNode(ISD::SUB, VT,
5552 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5553 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5554 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5559 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5560 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5561 /// LegalizeNodes map is filled in for any results that are not expanded, the
5562 /// ExpandedNodes map is filled in for any results that are expanded, and the
5563 /// Lo/Hi values are returned.
5564 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5565 MVT::ValueType VT = Op.getValueType();
5566 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5567 SDNode *Node = Op.Val;
5568 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5569 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5570 MVT::isVector(VT)) &&
5571 "Cannot expand to FP value or to larger int value!");
5573 // See if we already expanded it.
5574 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5575 = ExpandedNodes.find(Op);
5576 if (I != ExpandedNodes.end()) {
5577 Lo = I->second.first;
5578 Hi = I->second.second;
5582 switch (Node->getOpcode()) {
5583 case ISD::CopyFromReg:
5584 assert(0 && "CopyFromReg must be legal!");
5585 case ISD::FP_ROUND_INREG:
5586 if (VT == MVT::ppcf128 &&
5587 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5588 TargetLowering::Custom) {
5589 SDOperand SrcLo, SrcHi, Src;
5590 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5591 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5592 SDOperand Result = TLI.LowerOperation(
5593 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5594 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5595 Lo = Result.Val->getOperand(0);
5596 Hi = Result.Val->getOperand(1);
5602 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5604 assert(0 && "Do not know how to expand this operator!");
5606 case ISD::EXTRACT_VECTOR_ELT:
5607 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5608 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5609 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5610 return ExpandOp(Lo, Lo, Hi);
5612 NVT = TLI.getTypeToExpandTo(VT);
5613 Lo = DAG.getNode(ISD::UNDEF, NVT);
5614 Hi = DAG.getNode(ISD::UNDEF, NVT);
5616 case ISD::Constant: {
5617 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
5618 Lo = DAG.getConstant(Cst, NVT);
5619 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
5622 case ISD::ConstantFP: {
5623 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5624 if (CFP->getValueType(0) == MVT::ppcf128) {
5625 APInt api = CFP->getValueAPF().convertToAPInt();
5626 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5628 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5632 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5633 if (getTypeAction(Lo.getValueType()) == Expand)
5634 ExpandOp(Lo, Lo, Hi);
5637 case ISD::BUILD_PAIR:
5638 // Return the operands.
5639 Lo = Node->getOperand(0);
5640 Hi = Node->getOperand(1);
5643 case ISD::MERGE_VALUES:
5644 if (Node->getNumValues() == 1) {
5645 ExpandOp(Op.getOperand(0), Lo, Hi);
5648 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5649 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5650 Op.getValue(1).getValueType() == MVT::Other &&
5651 "unhandled MERGE_VALUES");
5652 ExpandOp(Op.getOperand(0), Lo, Hi);
5653 // Remember that we legalized the chain.
5654 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5657 case ISD::SIGN_EXTEND_INREG:
5658 ExpandOp(Node->getOperand(0), Lo, Hi);
5659 // sext_inreg the low part if needed.
5660 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5662 // The high part gets the sign extension from the lo-part. This handles
5663 // things like sextinreg V:i64 from i8.
5664 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5665 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5666 TLI.getShiftAmountTy()));
5670 ExpandOp(Node->getOperand(0), Lo, Hi);
5671 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5672 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5678 ExpandOp(Node->getOperand(0), Lo, Hi);
5679 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5680 DAG.getNode(ISD::CTPOP, NVT, Lo),
5681 DAG.getNode(ISD::CTPOP, NVT, Hi));
5682 Hi = DAG.getConstant(0, NVT);
5686 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5687 ExpandOp(Node->getOperand(0), Lo, Hi);
5688 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5689 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5690 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5692 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5693 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5695 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5696 Hi = DAG.getConstant(0, NVT);
5701 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5702 ExpandOp(Node->getOperand(0), Lo, Hi);
5703 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5704 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5705 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5707 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5708 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5710 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5711 Hi = DAG.getConstant(0, NVT);
5716 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5717 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5718 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5719 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5721 // Remember that we legalized the chain.
5722 Hi = LegalizeOp(Hi);
5723 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5724 if (!TLI.isLittleEndian())
5730 LoadSDNode *LD = cast<LoadSDNode>(Node);
5731 SDOperand Ch = LD->getChain(); // Legalize the chain.
5732 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5733 ISD::LoadExtType ExtType = LD->getExtensionType();
5734 int SVOffset = LD->getSrcValueOffset();
5735 unsigned Alignment = LD->getAlignment();
5736 bool isVolatile = LD->isVolatile();
5738 if (ExtType == ISD::NON_EXTLOAD) {
5739 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5740 isVolatile, Alignment);
5741 if (VT == MVT::f32 || VT == MVT::f64) {
5742 // f32->i32 or f64->i64 one to one expansion.
5743 // Remember that we legalized the chain.
5744 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5745 // Recursively expand the new load.
5746 if (getTypeAction(NVT) == Expand)
5747 ExpandOp(Lo, Lo, Hi);
5751 // Increment the pointer to the other half.
5752 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5753 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5754 DAG.getIntPtrConstant(IncrementSize));
5755 SVOffset += IncrementSize;
5756 Alignment = MinAlign(Alignment, IncrementSize);
5757 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5758 isVolatile, Alignment);
5760 // Build a factor node to remember that this load is independent of the
5762 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5765 // Remember that we legalized the chain.
5766 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5767 if (!TLI.isLittleEndian())
5770 MVT::ValueType EVT = LD->getMemoryVT();
5772 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5773 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5774 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5775 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5776 SVOffset, isVolatile, Alignment);
5777 // Remember that we legalized the chain.
5778 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5779 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5784 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5785 SVOffset, isVolatile, Alignment);
5787 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5788 SVOffset, EVT, isVolatile,
5791 // Remember that we legalized the chain.
5792 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5794 if (ExtType == ISD::SEXTLOAD) {
5795 // The high part is obtained by SRA'ing all but one of the bits of the
5797 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5798 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5799 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5800 } else if (ExtType == ISD::ZEXTLOAD) {
5801 // The high part is just a zero.
5802 Hi = DAG.getConstant(0, NVT);
5803 } else /* if (ExtType == ISD::EXTLOAD) */ {
5804 // The high part is undefined.
5805 Hi = DAG.getNode(ISD::UNDEF, NVT);
5812 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5813 SDOperand LL, LH, RL, RH;
5814 ExpandOp(Node->getOperand(0), LL, LH);
5815 ExpandOp(Node->getOperand(1), RL, RH);
5816 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5817 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5821 SDOperand LL, LH, RL, RH;
5822 ExpandOp(Node->getOperand(1), LL, LH);
5823 ExpandOp(Node->getOperand(2), RL, RH);
5824 if (getTypeAction(NVT) == Expand)
5825 NVT = TLI.getTypeToExpandTo(NVT);
5826 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5828 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5831 case ISD::SELECT_CC: {
5832 SDOperand TL, TH, FL, FH;
5833 ExpandOp(Node->getOperand(2), TL, TH);
5834 ExpandOp(Node->getOperand(3), FL, FH);
5835 if (getTypeAction(NVT) == Expand)
5836 NVT = TLI.getTypeToExpandTo(NVT);
5837 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5838 Node->getOperand(1), TL, FL, Node->getOperand(4));
5840 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5841 Node->getOperand(1), TH, FH, Node->getOperand(4));
5844 case ISD::ANY_EXTEND:
5845 // The low part is any extension of the input (which degenerates to a copy).
5846 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5847 // The high part is undefined.
5848 Hi = DAG.getNode(ISD::UNDEF, NVT);
5850 case ISD::SIGN_EXTEND: {
5851 // The low part is just a sign extension of the input (which degenerates to
5853 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5855 // The high part is obtained by SRA'ing all but one of the bits of the lo
5857 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5858 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5859 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5862 case ISD::ZERO_EXTEND:
5863 // The low part is just a zero extension of the input (which degenerates to
5865 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5867 // The high part is just a zero.
5868 Hi = DAG.getConstant(0, NVT);
5871 case ISD::TRUNCATE: {
5872 // The input value must be larger than this value. Expand *it*.
5874 ExpandOp(Node->getOperand(0), NewLo, Hi);
5876 // The low part is now either the right size, or it is closer. If not the
5877 // right size, make an illegal truncate so we recursively expand it.
5878 if (NewLo.getValueType() != Node->getValueType(0))
5879 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
5880 ExpandOp(NewLo, Lo, Hi);
5884 case ISD::BIT_CONVERT: {
5886 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
5887 // If the target wants to, allow it to lower this itself.
5888 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5889 case Expand: assert(0 && "cannot expand FP!");
5890 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
5891 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
5893 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
5896 // f32 / f64 must be expanded to i32 / i64.
5897 if (VT == MVT::f32 || VT == MVT::f64) {
5898 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5899 if (getTypeAction(NVT) == Expand)
5900 ExpandOp(Lo, Lo, Hi);
5904 // If source operand will be expanded to the same type as VT, i.e.
5905 // i64 <- f64, i32 <- f32, expand the source operand instead.
5906 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
5907 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
5908 ExpandOp(Node->getOperand(0), Lo, Hi);
5912 // Turn this into a load/store pair by default.
5914 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
5916 ExpandOp(Tmp, Lo, Hi);
5920 case ISD::READCYCLECOUNTER: {
5921 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5922 TargetLowering::Custom &&
5923 "Must custom expand ReadCycleCounter");
5924 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
5925 assert(Tmp.Val && "Node must be custom expanded!");
5926 ExpandOp(Tmp.getValue(0), Lo, Hi);
5927 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5928 LegalizeOp(Tmp.getValue(1)));
5932 // These operators cannot be expanded directly, emit them as calls to
5933 // library functions.
5934 case ISD::FP_TO_SINT: {
5935 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5937 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5938 case Expand: assert(0 && "cannot expand FP!");
5939 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5940 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5943 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5945 // Now that the custom expander is done, expand the result, which is still
5948 ExpandOp(Op, Lo, Hi);
5953 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5954 if (Node->getOperand(0).getValueType() == MVT::f32)
5955 LC = RTLIB::FPTOSINT_F32_I64;
5956 else if (Node->getOperand(0).getValueType() == MVT::f64)
5957 LC = RTLIB::FPTOSINT_F64_I64;
5958 else if (Node->getOperand(0).getValueType() == MVT::f80)
5959 LC = RTLIB::FPTOSINT_F80_I64;
5960 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
5961 LC = RTLIB::FPTOSINT_PPCF128_I64;
5962 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5963 false/*sign irrelevant*/, Hi);
5967 case ISD::FP_TO_UINT: {
5968 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
5970 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5971 case Expand: assert(0 && "cannot expand FP!");
5972 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5973 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5976 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
5978 // Now that the custom expander is done, expand the result.
5980 ExpandOp(Op, Lo, Hi);
5985 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5986 if (Node->getOperand(0).getValueType() == MVT::f32)
5987 LC = RTLIB::FPTOUINT_F32_I64;
5988 else if (Node->getOperand(0).getValueType() == MVT::f64)
5989 LC = RTLIB::FPTOUINT_F64_I64;
5990 else if (Node->getOperand(0).getValueType() == MVT::f80)
5991 LC = RTLIB::FPTOUINT_F80_I64;
5992 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
5993 LC = RTLIB::FPTOUINT_PPCF128_I64;
5994 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5995 false/*sign irrelevant*/, Hi);
6000 // If the target wants custom lowering, do so.
6001 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6002 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6003 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6004 Op = TLI.LowerOperation(Op, DAG);
6006 // Now that the custom expander is done, expand the result, which is
6008 ExpandOp(Op, Lo, Hi);
6013 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6014 // this X << 1 as X+X.
6015 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6016 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6017 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6018 SDOperand LoOps[2], HiOps[3];
6019 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6020 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6021 LoOps[1] = LoOps[0];
6022 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6024 HiOps[1] = HiOps[0];
6025 HiOps[2] = Lo.getValue(1);
6026 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6031 // If we can emit an efficient shift operation, do so now.
6032 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6035 // If this target supports SHL_PARTS, use it.
6036 TargetLowering::LegalizeAction Action =
6037 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6038 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6039 Action == TargetLowering::Custom) {
6040 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6044 // Otherwise, emit a libcall.
6045 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
6046 false/*left shift=unsigned*/, Hi);
6051 // If the target wants custom lowering, do so.
6052 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6053 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6054 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6055 Op = TLI.LowerOperation(Op, DAG);
6057 // Now that the custom expander is done, expand the result, which is
6059 ExpandOp(Op, Lo, Hi);
6064 // If we can emit an efficient shift operation, do so now.
6065 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6068 // If this target supports SRA_PARTS, use it.
6069 TargetLowering::LegalizeAction Action =
6070 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6071 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6072 Action == TargetLowering::Custom) {
6073 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6077 // Otherwise, emit a libcall.
6078 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
6079 true/*ashr is signed*/, Hi);
6084 // If the target wants custom lowering, do so.
6085 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6086 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6087 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6088 Op = TLI.LowerOperation(Op, DAG);
6090 // Now that the custom expander is done, expand the result, which is
6092 ExpandOp(Op, Lo, Hi);
6097 // If we can emit an efficient shift operation, do so now.
6098 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6101 // If this target supports SRL_PARTS, use it.
6102 TargetLowering::LegalizeAction Action =
6103 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6104 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6105 Action == TargetLowering::Custom) {
6106 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6110 // Otherwise, emit a libcall.
6111 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
6112 false/*lshr is unsigned*/, Hi);
6118 // If the target wants to custom expand this, let them.
6119 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6120 TargetLowering::Custom) {
6121 Op = TLI.LowerOperation(Op, DAG);
6123 ExpandOp(Op, Lo, Hi);
6128 // Expand the subcomponents.
6129 SDOperand LHSL, LHSH, RHSL, RHSH;
6130 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6131 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6132 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6133 SDOperand LoOps[2], HiOps[3];
6138 if (Node->getOpcode() == ISD::ADD) {
6139 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6140 HiOps[2] = Lo.getValue(1);
6141 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6143 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6144 HiOps[2] = Lo.getValue(1);
6145 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6152 // Expand the subcomponents.
6153 SDOperand LHSL, LHSH, RHSL, RHSH;
6154 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6155 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6156 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6157 SDOperand LoOps[2] = { LHSL, RHSL };
6158 SDOperand HiOps[3] = { LHSH, RHSH };
6160 if (Node->getOpcode() == ISD::ADDC) {
6161 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6162 HiOps[2] = Lo.getValue(1);
6163 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6165 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6166 HiOps[2] = Lo.getValue(1);
6167 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6169 // Remember that we legalized the flag.
6170 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6175 // Expand the subcomponents.
6176 SDOperand LHSL, LHSH, RHSL, RHSH;
6177 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6178 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6179 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6180 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6181 SDOperand HiOps[3] = { LHSH, RHSH };
6183 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6184 HiOps[2] = Lo.getValue(1);
6185 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6187 // Remember that we legalized the flag.
6188 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6192 // If the target wants to custom expand this, let them.
6193 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6194 SDOperand New = TLI.LowerOperation(Op, DAG);
6196 ExpandOp(New, Lo, Hi);
6201 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6202 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6203 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6204 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6205 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6206 SDOperand LL, LH, RL, RH;
6207 ExpandOp(Node->getOperand(0), LL, LH);
6208 ExpandOp(Node->getOperand(1), RL, RH);
6209 unsigned BitSize = MVT::getSizeInBits(RH.getValueType());
6210 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6211 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6212 // FIXME: generalize this to handle other bit sizes
6213 if (LHSSB == 32 && RHSSB == 32 &&
6214 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) &&
6215 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) {
6216 // The inputs are both zero-extended.
6218 // We can emit a umul_lohi.
6219 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6220 Hi = SDOperand(Lo.Val, 1);
6224 // We can emit a mulhu+mul.
6225 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6226 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6230 if (LHSSB > BitSize && RHSSB > BitSize) {
6231 // The input values are both sign-extended.
6233 // We can emit a smul_lohi.
6234 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6235 Hi = SDOperand(Lo.Val, 1);
6239 // We can emit a mulhs+mul.
6240 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6241 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6246 // Lo,Hi = umul LHS, RHS.
6247 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6248 DAG.getVTList(NVT, NVT), LL, RL);
6250 Hi = UMulLOHI.getValue(1);
6251 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6252 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6253 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6254 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6258 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6259 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6260 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6261 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6262 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6263 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6268 // If nothing else, we can make a libcall.
6269 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
6270 false/*sign irrelevant*/, Hi);
6274 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
6277 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
6280 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
6283 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
6287 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32,
6290 RTLIB::ADD_PPCF128)),
6294 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32,
6297 RTLIB::SUB_PPCF128)),
6301 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32,
6304 RTLIB::MUL_PPCF128)),
6308 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32,
6311 RTLIB::DIV_PPCF128)),
6314 case ISD::FP_EXTEND:
6315 if (VT == MVT::ppcf128) {
6316 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6317 Node->getOperand(0).getValueType()==MVT::f64);
6318 const uint64_t zero = 0;
6319 if (Node->getOperand(0).getValueType()==MVT::f32)
6320 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6322 Hi = Node->getOperand(0);
6323 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6326 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
6329 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
6332 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32,
6335 RTLIB::POWI_PPCF128)),
6341 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6342 switch(Node->getOpcode()) {
6344 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6345 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6348 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6349 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6352 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6353 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6355 default: assert(0 && "Unreachable!");
6357 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
6361 if (VT == MVT::ppcf128) {
6363 ExpandOp(Node->getOperand(0), Lo, Tmp);
6364 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6365 // lo = hi==fabs(hi) ? lo : -lo;
6366 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6367 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6368 DAG.getCondCode(ISD::SETEQ));
6371 SDOperand Mask = (VT == MVT::f64)
6372 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6373 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6374 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6375 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6376 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6377 if (getTypeAction(NVT) == Expand)
6378 ExpandOp(Lo, Lo, Hi);
6382 if (VT == MVT::ppcf128) {
6383 ExpandOp(Node->getOperand(0), Lo, Hi);
6384 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6385 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6388 SDOperand Mask = (VT == MVT::f64)
6389 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6390 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6391 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6392 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6393 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6394 if (getTypeAction(NVT) == Expand)
6395 ExpandOp(Lo, Lo, Hi);
6398 case ISD::FCOPYSIGN: {
6399 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6400 if (getTypeAction(NVT) == Expand)
6401 ExpandOp(Lo, Lo, Hi);
6404 case ISD::SINT_TO_FP:
6405 case ISD::UINT_TO_FP: {
6406 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6407 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
6408 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) {
6409 static uint64_t zero = 0;
6411 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6412 Node->getOperand(0)));
6413 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6415 static uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6416 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6417 Node->getOperand(0)));
6418 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6419 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6420 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6421 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6422 DAG.getConstant(0, MVT::i32),
6423 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6425 APFloat(APInt(128, 2, TwoE32)),
6428 DAG.getCondCode(ISD::SETLT)),
6433 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6434 // si64->ppcf128 done by libcall, below
6435 static uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6436 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6438 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6439 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6440 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6441 DAG.getConstant(0, MVT::i64),
6442 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6444 APFloat(APInt(128, 2, TwoE64)),
6447 DAG.getCondCode(ISD::SETLT)),
6451 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6452 if (Node->getOperand(0).getValueType() == MVT::i64) {
6454 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
6455 else if (VT == MVT::f64)
6456 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
6457 else if (VT == MVT::f80) {
6459 LC = RTLIB::SINTTOFP_I64_F80;
6461 else if (VT == MVT::ppcf128) {
6463 LC = RTLIB::SINTTOFP_I64_PPCF128;
6467 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
6469 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
6472 // Promote the operand if needed.
6473 if (getTypeAction(SrcVT) == Promote) {
6474 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6476 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6477 DAG.getValueType(SrcVT))
6478 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6479 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6482 const char *LibCall = TLI.getLibcallName(LC);
6484 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
6486 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6487 Node->getOperand(0));
6488 if (getTypeAction(Lo.getValueType()) == Expand)
6489 ExpandOp(Lo, Lo, Hi);
6495 // Make sure the resultant values have been legalized themselves, unless this
6496 // is a type that requires multi-step expansion.
6497 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6498 Lo = LegalizeOp(Lo);
6500 // Don't legalize the high part if it is expanded to a single node.
6501 Hi = LegalizeOp(Hi);
6504 // Remember in a map if the values will be reused later.
6505 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6506 assert(isNew && "Value already expanded?!?");
6509 /// SplitVectorOp - Given an operand of vector type, break it down into
6510 /// two smaller values, still of vector type.
6511 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6513 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
6514 SDNode *Node = Op.Val;
6515 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
6516 assert(NumElements > 1 && "Cannot split a single element vector!");
6518 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
6520 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6521 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6523 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
6524 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
6526 // See if we already split it.
6527 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6528 = SplitNodes.find(Op);
6529 if (I != SplitNodes.end()) {
6530 Lo = I->second.first;
6531 Hi = I->second.second;
6535 switch (Node->getOpcode()) {
6540 assert(0 && "Unhandled operation in SplitVectorOp!");
6542 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6543 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6545 case ISD::BUILD_PAIR:
6546 Lo = Node->getOperand(0);
6547 Hi = Node->getOperand(1);
6549 case ISD::INSERT_VECTOR_ELT: {
6550 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6551 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
6552 SDOperand ScalarOp = Node->getOperand(1);
6553 if (Index < NewNumElts_Lo)
6554 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6555 DAG.getConstant(Index, TLI.getPointerTy()));
6557 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6558 DAG.getConstant(Index - NewNumElts_Lo,
6559 TLI.getPointerTy()));
6562 case ISD::VECTOR_SHUFFLE: {
6563 // Build the low part.
6564 SDOperand Mask = Node->getOperand(2);
6565 SmallVector<SDOperand, 8> Ops;
6566 MVT::ValueType PtrVT = TLI.getPointerTy();
6568 // Insert all of the elements from the input that are needed. We use
6569 // buildvector of extractelement here because the input vectors will have
6570 // to be legalized, so this makes the code simpler.
6571 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6572 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6573 SDOperand InVec = Node->getOperand(0);
6574 if (Idx >= NumElements) {
6575 InVec = Node->getOperand(1);
6578 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6579 DAG.getConstant(Idx, PtrVT)));
6581 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6584 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6585 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6586 SDOperand InVec = Node->getOperand(0);
6587 if (Idx >= NumElements) {
6588 InVec = Node->getOperand(1);
6591 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6592 DAG.getConstant(Idx, PtrVT)));
6594 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6597 case ISD::BUILD_VECTOR: {
6598 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6599 Node->op_begin()+NewNumElts_Lo);
6600 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6602 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6604 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6607 case ISD::CONCAT_VECTORS: {
6608 // FIXME: Handle non-power-of-two vectors?
6609 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6610 if (NewNumSubvectors == 1) {
6611 Lo = Node->getOperand(0);
6612 Hi = Node->getOperand(1);
6614 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6615 Node->op_begin()+NewNumSubvectors);
6616 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6618 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6620 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6625 SDOperand Cond = Node->getOperand(0);
6627 SDOperand LL, LH, RL, RH;
6628 SplitVectorOp(Node->getOperand(1), LL, LH);
6629 SplitVectorOp(Node->getOperand(2), RL, RH);
6631 if (MVT::isVector(Cond.getValueType())) {
6632 // Handle a vector merge.
6634 SplitVectorOp(Cond, CL, CH);
6635 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6636 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6638 // Handle a simple select with vector operands.
6639 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6640 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6660 SDOperand LL, LH, RL, RH;
6661 SplitVectorOp(Node->getOperand(0), LL, LH);
6662 SplitVectorOp(Node->getOperand(1), RL, RH);
6664 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6665 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6670 SplitVectorOp(Node->getOperand(0), L, H);
6672 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6673 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6684 case ISD::FP_TO_SINT:
6685 case ISD::FP_TO_UINT:
6686 case ISD::SINT_TO_FP:
6687 case ISD::UINT_TO_FP: {
6689 SplitVectorOp(Node->getOperand(0), L, H);
6691 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6692 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6696 LoadSDNode *LD = cast<LoadSDNode>(Node);
6697 SDOperand Ch = LD->getChain();
6698 SDOperand Ptr = LD->getBasePtr();
6699 const Value *SV = LD->getSrcValue();
6700 int SVOffset = LD->getSrcValueOffset();
6701 unsigned Alignment = LD->getAlignment();
6702 bool isVolatile = LD->isVolatile();
6704 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6705 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
6706 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6707 DAG.getIntPtrConstant(IncrementSize));
6708 SVOffset += IncrementSize;
6709 Alignment = MinAlign(Alignment, IncrementSize);
6710 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6712 // Build a factor node to remember that this load is independent of the
6714 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6717 // Remember that we legalized the chain.
6718 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6721 case ISD::BIT_CONVERT: {
6722 // We know the result is a vector. The input may be either a vector or a
6724 SDOperand InOp = Node->getOperand(0);
6725 if (!MVT::isVector(InOp.getValueType()) ||
6726 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
6727 // The input is a scalar or single-element vector.
6728 // Lower to a store/load so that it can be split.
6729 // FIXME: this could be improved probably.
6730 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6732 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6733 InOp, Ptr, NULL, 0);
6734 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0);
6736 // Split the vector and convert each of the pieces now.
6737 SplitVectorOp(InOp, Lo, Hi);
6738 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6739 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6744 // Remember in a map if the values will be reused later.
6746 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6747 assert(isNew && "Value already split?!?");
6751 /// ScalarizeVectorOp - Given an operand of single-element vector type
6752 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6753 /// scalar (e.g. f32) value.
6754 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6755 assert(MVT::isVector(Op.getValueType()) &&
6756 "Bad ScalarizeVectorOp invocation!");
6757 SDNode *Node = Op.Val;
6758 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
6759 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
6761 // See if we already scalarized it.
6762 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
6763 if (I != ScalarizedNodes.end()) return I->second;
6766 switch (Node->getOpcode()) {
6769 Node->dump(&DAG); cerr << "\n";
6771 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
6788 Result = DAG.getNode(Node->getOpcode(),
6790 ScalarizeVectorOp(Node->getOperand(0)),
6791 ScalarizeVectorOp(Node->getOperand(1)));
6798 Result = DAG.getNode(Node->getOpcode(),
6800 ScalarizeVectorOp(Node->getOperand(0)));
6803 Result = DAG.getNode(Node->getOpcode(),
6805 ScalarizeVectorOp(Node->getOperand(0)),
6806 Node->getOperand(1));
6809 LoadSDNode *LD = cast<LoadSDNode>(Node);
6810 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
6811 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
6813 const Value *SV = LD->getSrcValue();
6814 int SVOffset = LD->getSrcValueOffset();
6815 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
6816 LD->isVolatile(), LD->getAlignment());
6818 // Remember that we legalized the chain.
6819 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
6822 case ISD::BUILD_VECTOR:
6823 Result = Node->getOperand(0);
6825 case ISD::INSERT_VECTOR_ELT:
6826 // Returning the inserted scalar element.
6827 Result = Node->getOperand(1);
6829 case ISD::CONCAT_VECTORS:
6830 assert(Node->getOperand(0).getValueType() == NewVT &&
6831 "Concat of non-legal vectors not yet supported!");
6832 Result = Node->getOperand(0);
6834 case ISD::VECTOR_SHUFFLE: {
6835 // Figure out if the scalar is the LHS or RHS and return it.
6836 SDOperand EltNum = Node->getOperand(2).getOperand(0);
6837 if (cast<ConstantSDNode>(EltNum)->getValue())
6838 Result = ScalarizeVectorOp(Node->getOperand(1));
6840 Result = ScalarizeVectorOp(Node->getOperand(0));
6843 case ISD::EXTRACT_SUBVECTOR:
6844 Result = Node->getOperand(0);
6845 assert(Result.getValueType() == NewVT);
6847 case ISD::BIT_CONVERT:
6848 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
6851 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
6852 ScalarizeVectorOp(Op.getOperand(1)),
6853 ScalarizeVectorOp(Op.getOperand(2)));
6857 if (TLI.isTypeLegal(NewVT))
6858 Result = LegalizeOp(Result);
6859 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
6860 assert(isNew && "Value already scalarized?");
6865 // SelectionDAG::Legalize - This is the entry point for the file.
6867 void SelectionDAG::Legalize() {
6868 if (ViewLegalizeDAGs) viewGraph();
6870 /// run - This is the main entry point to this class.
6872 SelectionDAGLegalize(*this).LegalizeDAG();