1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/Constants.h"
27 #include "llvm/DerivedTypes.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/SmallPtrSet.h"
39 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
40 cl::desc("Pop up a window to show dags before legalize"));
42 static const bool ViewLegalizeDAGs = 0;
45 //===----------------------------------------------------------------------===//
46 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
47 /// hacks on it until the target machine can handle it. This involves
48 /// eliminating value sizes the machine cannot handle (promoting small sizes to
49 /// large sizes or splitting up large values into small values) as well as
50 /// eliminating operations the machine cannot handle.
52 /// This code also does a small amount of optimization and recognition of idioms
53 /// as part of its processing. For example, if a target does not support a
54 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
55 /// will attempt merge setcc and brc instructions into brcc's.
58 class VISIBILITY_HIDDEN SelectionDAGLegalize {
62 // Libcall insertion helpers.
64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
65 /// legalized. We use this to ensure that calls are properly serialized
66 /// against each other, including inserted libcalls.
67 SDOperand LastCALLSEQ_END;
69 /// IsLegalizingCall - This member is used *only* for purposes of providing
70 /// helpful assertions that a libcall isn't created while another call is
71 /// being legalized (which could lead to non-serialized call sequences).
72 bool IsLegalizingCall;
75 Legal, // The target natively supports this operation.
76 Promote, // This operation should be executed in a larger type.
77 Expand // Try to expand this to other ops, otherwise use a libcall.
80 /// ValueTypeActions - This is a bitvector that contains two bits for each
81 /// value type, where the two bits correspond to the LegalizeAction enum.
82 /// This can be queried with "getTypeAction(VT)".
83 TargetLowering::ValueTypeActionImpl ValueTypeActions;
85 /// LegalizedNodes - For nodes that are of legal width, and that have more
86 /// than one use, this map indicates what regularized operand to use. This
87 /// allows us to avoid legalizing the same thing more than once.
88 DenseMap<SDOperand, SDOperand> LegalizedNodes;
90 /// PromotedNodes - For nodes that are below legal width, and that have more
91 /// than one use, this map indicates what promoted value to use. This allows
92 /// us to avoid promoting the same thing more than once.
93 DenseMap<SDOperand, SDOperand> PromotedNodes;
95 /// ExpandedNodes - For nodes that need to be expanded this map indicates
96 /// which which operands are the expanded version of the input. This allows
97 /// us to avoid expanding the same node more than once.
98 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
100 /// SplitNodes - For vector nodes that need to be split, this map indicates
101 /// which which operands are the split version of the input. This allows us
102 /// to avoid splitting the same node more than once.
103 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
105 /// ScalarizedNodes - For nodes that need to be converted from vector types to
106 /// scalar types, this contains the mapping of ones we have already
107 /// processed to the result.
108 std::map<SDOperand, SDOperand> ScalarizedNodes;
110 void AddLegalizedOperand(SDOperand From, SDOperand To) {
111 LegalizedNodes.insert(std::make_pair(From, To));
112 // If someone requests legalization of the new node, return itself.
114 LegalizedNodes.insert(std::make_pair(To, To));
116 void AddPromotedOperand(SDOperand From, SDOperand To) {
117 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
118 assert(isNew && "Got into the map somehow?");
119 // If someone requests legalization of the new node, return itself.
120 LegalizedNodes.insert(std::make_pair(To, To));
125 SelectionDAGLegalize(SelectionDAG &DAG);
127 /// getTypeAction - Return how we should legalize values of this type, either
128 /// it is already legal or we need to expand it into multiple registers of
129 /// smaller integer type, or we need to promote it to a larger type.
130 LegalizeAction getTypeAction(MVT::ValueType VT) const {
131 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
134 /// isTypeLegal - Return true if this type is legal on this target.
136 bool isTypeLegal(MVT::ValueType VT) const {
137 return getTypeAction(VT) == Legal;
143 /// HandleOp - Legalize, Promote, or Expand the specified operand as
144 /// appropriate for its type.
145 void HandleOp(SDOperand Op);
147 /// LegalizeOp - We know that the specified value has a legal type.
148 /// Recursively ensure that the operands have legal types, then return the
150 SDOperand LegalizeOp(SDOperand O);
152 /// UnrollVectorOp - We know that the given vector has a legal type, however
153 /// the operation it performs is not legal and is an operation that we have
154 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
155 /// operating on each element individually.
156 SDOperand UnrollVectorOp(SDOperand O);
158 /// PromoteOp - Given an operation that produces a value in an invalid type,
159 /// promote it to compute the value into a larger type. The produced value
160 /// will have the correct bits for the low portion of the register, but no
161 /// guarantee is made about the top bits: it may be zero, sign-extended, or
163 SDOperand PromoteOp(SDOperand O);
165 /// ExpandOp - Expand the specified SDOperand into its two component pieces
166 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
167 /// the LegalizeNodes map is filled in for any results that are not expanded,
168 /// the ExpandedNodes map is filled in for any results that are expanded, and
169 /// the Lo/Hi values are returned. This applies to integer types and Vector
171 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
173 /// SplitVectorOp - Given an operand of vector type, break it down into
174 /// two smaller values.
175 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
177 /// ScalarizeVectorOp - Given an operand of single-element vector type
178 /// (e.g. v1f32), convert it into the equivalent operation that returns a
179 /// scalar (e.g. f32) value.
180 SDOperand ScalarizeVectorOp(SDOperand O);
182 /// isShuffleLegal - Return true if a vector shuffle is legal with the
183 /// specified mask and type. Targets can specify exactly which masks they
184 /// support and the code generator is tasked with not creating illegal masks.
186 /// Note that this will also return true for shuffles that are promoted to a
189 /// If this is a legal shuffle, this method returns the (possibly promoted)
190 /// build_vector Mask. If it's not a legal shuffle, it returns null.
191 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
193 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
194 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
196 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
198 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
200 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
203 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT,
204 MVT::ValueType DestVT);
205 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
206 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
207 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
209 MVT::ValueType DestVT);
210 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
212 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
215 SDOperand ExpandBSWAP(SDOperand Op);
216 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
217 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
218 SDOperand &Lo, SDOperand &Hi);
219 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
220 SDOperand &Lo, SDOperand &Hi);
222 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
223 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
227 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
228 /// specified mask and type. Targets can specify exactly which masks they
229 /// support and the code generator is tasked with not creating illegal masks.
231 /// Note that this will also return true for shuffles that are promoted to a
233 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
234 SDOperand Mask) const {
235 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
237 case TargetLowering::Legal:
238 case TargetLowering::Custom:
240 case TargetLowering::Promote: {
241 // If this is promoted to a different type, convert the shuffle mask and
242 // ask if it is legal in the promoted type!
243 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
245 // If we changed # elements, change the shuffle mask.
246 unsigned NumEltsGrowth =
247 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
248 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
249 if (NumEltsGrowth > 1) {
250 // Renumber the elements.
251 SmallVector<SDOperand, 8> Ops;
252 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
253 SDOperand InOp = Mask.getOperand(i);
254 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
255 if (InOp.getOpcode() == ISD::UNDEF)
256 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
258 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
259 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
263 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
269 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
272 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
273 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
274 ValueTypeActions(TLI.getValueTypeActions()) {
275 assert(MVT::LAST_VALUETYPE <= 32 &&
276 "Too many value types for ValueTypeActions to hold!");
279 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
280 /// contains all of a nodes operands before it contains the node.
281 static void ComputeTopDownOrdering(SelectionDAG &DAG,
282 SmallVector<SDNode*, 64> &Order) {
284 DenseMap<SDNode*, unsigned> Visited;
285 std::vector<SDNode*> Worklist;
286 Worklist.reserve(128);
288 // Compute ordering from all of the leaves in the graphs, those (like the
289 // entry node) that have no operands.
290 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
291 E = DAG.allnodes_end(); I != E; ++I) {
292 if (I->getNumOperands() == 0) {
294 Worklist.push_back(I);
298 while (!Worklist.empty()) {
299 SDNode *N = Worklist.back();
302 if (++Visited[N] != N->getNumOperands())
303 continue; // Haven't visited all operands yet
307 // Now that we have N in, add anything that uses it if all of their operands
309 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
311 Worklist.push_back(*UI);
314 assert(Order.size() == Visited.size() &&
316 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
317 "Error: DAG is cyclic!");
321 void SelectionDAGLegalize::LegalizeDAG() {
322 LastCALLSEQ_END = DAG.getEntryNode();
323 IsLegalizingCall = false;
325 // The legalize process is inherently a bottom-up recursive process (users
326 // legalize their uses before themselves). Given infinite stack space, we
327 // could just start legalizing on the root and traverse the whole graph. In
328 // practice however, this causes us to run out of stack space on large basic
329 // blocks. To avoid this problem, compute an ordering of the nodes where each
330 // node is only legalized after all of its operands are legalized.
331 SmallVector<SDNode*, 64> Order;
332 ComputeTopDownOrdering(DAG, Order);
334 for (unsigned i = 0, e = Order.size(); i != e; ++i)
335 HandleOp(SDOperand(Order[i], 0));
337 // Finally, it's possible the root changed. Get the new root.
338 SDOperand OldRoot = DAG.getRoot();
339 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
340 DAG.setRoot(LegalizedNodes[OldRoot]);
342 ExpandedNodes.clear();
343 LegalizedNodes.clear();
344 PromotedNodes.clear();
346 ScalarizedNodes.clear();
348 // Remove dead nodes now.
349 DAG.RemoveDeadNodes();
353 /// FindCallEndFromCallStart - Given a chained node that is part of a call
354 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
355 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
356 if (Node->getOpcode() == ISD::CALLSEQ_END)
358 if (Node->use_empty())
359 return 0; // No CallSeqEnd
361 // The chain is usually at the end.
362 SDOperand TheChain(Node, Node->getNumValues()-1);
363 if (TheChain.getValueType() != MVT::Other) {
364 // Sometimes it's at the beginning.
365 TheChain = SDOperand(Node, 0);
366 if (TheChain.getValueType() != MVT::Other) {
367 // Otherwise, hunt for it.
368 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
369 if (Node->getValueType(i) == MVT::Other) {
370 TheChain = SDOperand(Node, i);
374 // Otherwise, we walked into a node without a chain.
375 if (TheChain.getValueType() != MVT::Other)
380 for (SDNode::use_iterator UI = Node->use_begin(),
381 E = Node->use_end(); UI != E; ++UI) {
383 // Make sure to only follow users of our token chain.
385 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
386 if (User->getOperand(i) == TheChain)
387 if (SDNode *Result = FindCallEndFromCallStart(User))
393 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
394 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
395 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
396 assert(Node && "Didn't find callseq_start for a call??");
397 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
399 assert(Node->getOperand(0).getValueType() == MVT::Other &&
400 "Node doesn't have a token chain argument!");
401 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
404 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
405 /// see if any uses can reach Dest. If no dest operands can get to dest,
406 /// legalize them, legalize ourself, and return false, otherwise, return true.
408 /// Keep track of the nodes we fine that actually do lead to Dest in
409 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
411 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
412 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
413 if (N == Dest) return true; // N certainly leads to Dest :)
415 // If we've already processed this node and it does lead to Dest, there is no
416 // need to reprocess it.
417 if (NodesLeadingTo.count(N)) return true;
419 // If the first result of this node has been already legalized, then it cannot
421 switch (getTypeAction(N->getValueType(0))) {
423 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
426 if (PromotedNodes.count(SDOperand(N, 0))) return false;
429 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
433 // Okay, this node has not already been legalized. Check and legalize all
434 // operands. If none lead to Dest, then we can legalize this node.
435 bool OperandsLeadToDest = false;
436 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
437 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
438 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
440 if (OperandsLeadToDest) {
441 NodesLeadingTo.insert(N);
445 // Okay, this node looks safe, legalize it and return false.
446 HandleOp(SDOperand(N, 0));
450 /// HandleOp - Legalize, Promote, or Expand the specified operand as
451 /// appropriate for its type.
452 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
453 MVT::ValueType VT = Op.getValueType();
454 switch (getTypeAction(VT)) {
455 default: assert(0 && "Bad type action!");
456 case Legal: (void)LegalizeOp(Op); break;
457 case Promote: (void)PromoteOp(Op); break;
459 if (!MVT::isVector(VT)) {
460 // If this is an illegal scalar, expand it into its two component
463 if (Op.getOpcode() == ISD::TargetConstant)
464 break; // Allow illegal target nodes.
466 } else if (MVT::getVectorNumElements(VT) == 1) {
467 // If this is an illegal single element vector, convert it to a
469 (void)ScalarizeVectorOp(Op);
471 // Otherwise, this is an illegal multiple element vector.
472 // Split it in half and legalize both parts.
474 SplitVectorOp(Op, X, Y);
480 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
481 /// a load from the constant pool.
482 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
483 SelectionDAG &DAG, TargetLowering &TLI) {
486 // If a FP immediate is precise when represented as a float and if the
487 // target can do an extending load from float to double, we put it into
488 // the constant pool as a float, even if it's is statically typed as a
490 MVT::ValueType VT = CFP->getValueType(0);
491 bool isDouble = VT == MVT::f64;
492 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
495 if (VT!=MVT::f64 && VT!=MVT::f32)
496 assert(0 && "Invalid type expansion");
497 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(),
498 isDouble ? MVT::i64 : MVT::i32);
501 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) &&
502 // Only do this if the target has a native EXTLOAD instruction from f32.
503 // Do not try to be clever about long doubles (so far)
504 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
505 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
510 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
512 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
513 CPIdx, PseudoSourceValue::getConstantPool(),
516 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
517 PseudoSourceValue::getConstantPool(), 0);
522 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
525 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
526 SelectionDAG &DAG, TargetLowering &TLI) {
527 MVT::ValueType VT = Node->getValueType(0);
528 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
529 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
530 "fcopysign expansion only supported for f32 and f64");
531 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
533 // First get the sign bit of second operand.
534 SDOperand Mask1 = (SrcVT == MVT::f64)
535 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
536 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
537 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
538 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
539 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
540 // Shift right or sign-extend it if the two operands have different types.
541 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
543 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
544 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
545 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
546 } else if (SizeDiff < 0)
547 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
549 // Clear the sign bit of first operand.
550 SDOperand Mask2 = (VT == MVT::f64)
551 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
552 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
553 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
554 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
555 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
557 // Or the value with the sign bit.
558 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
562 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
564 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
565 TargetLowering &TLI) {
566 SDOperand Chain = ST->getChain();
567 SDOperand Ptr = ST->getBasePtr();
568 SDOperand Val = ST->getValue();
569 MVT::ValueType VT = Val.getValueType();
570 int Alignment = ST->getAlignment();
571 int SVOffset = ST->getSrcValueOffset();
572 if (MVT::isFloatingPoint(ST->getMemoryVT())) {
573 // Expand to a bitconvert of the value to the integer type of the
574 // same size, then a (misaligned) int store.
575 MVT::ValueType intVT;
578 else if (VT==MVT::f32)
581 assert(0 && "Unaligned load of unsupported floating point type");
583 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
584 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
585 SVOffset, ST->isVolatile(), Alignment);
587 assert(MVT::isInteger(ST->getMemoryVT()) &&
588 "Unaligned store of unknown type.");
589 // Get the half-size VT
590 MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1;
591 int NumBits = MVT::getSizeInBits(NewStoredVT);
592 int IncrementSize = NumBits / 8;
594 // Divide the stored value in two parts.
595 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
597 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
599 // Store the two parts
600 SDOperand Store1, Store2;
601 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
602 ST->getSrcValue(), SVOffset, NewStoredVT,
603 ST->isVolatile(), Alignment);
604 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
605 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
606 Alignment = MinAlign(Alignment, IncrementSize);
607 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
608 ST->getSrcValue(), SVOffset + IncrementSize,
609 NewStoredVT, ST->isVolatile(), Alignment);
611 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
614 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
616 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
617 TargetLowering &TLI) {
618 int SVOffset = LD->getSrcValueOffset();
619 SDOperand Chain = LD->getChain();
620 SDOperand Ptr = LD->getBasePtr();
621 MVT::ValueType VT = LD->getValueType(0);
622 MVT::ValueType LoadedVT = LD->getMemoryVT();
623 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT)) {
624 // Expand to a (misaligned) integer load of the same size,
625 // then bitconvert to floating point.
626 MVT::ValueType intVT;
627 if (LoadedVT == MVT::f64)
629 else if (LoadedVT == MVT::f32)
632 assert(0 && "Unaligned load of unsupported floating point type");
634 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
635 SVOffset, LD->isVolatile(),
637 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
639 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
641 SDOperand Ops[] = { Result, Chain };
642 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
645 assert((MVT::isInteger(LoadedVT) || MVT::isVector(LoadedVT)) &&
646 "Unaligned load of unsupported type.");
648 // Compute the new VT that is half the size of the old one. We either have an
649 // integer MVT or we have a vector MVT.
650 unsigned NumBits = MVT::getSizeInBits(LoadedVT);
651 MVT::ValueType NewLoadedVT;
652 if (!MVT::isVector(LoadedVT)) {
653 NewLoadedVT = MVT::getIntegerType(NumBits/2);
655 // FIXME: This is not right for <1 x anything> it is also not right for
656 // non-power-of-two vectors.
657 NewLoadedVT = MVT::getVectorType(MVT::getVectorElementType(LoadedVT),
658 MVT::getVectorNumElements(LoadedVT)/2);
662 unsigned Alignment = LD->getAlignment();
663 unsigned IncrementSize = NumBits / 8;
664 ISD::LoadExtType HiExtType = LD->getExtensionType();
666 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
667 if (HiExtType == ISD::NON_EXTLOAD)
668 HiExtType = ISD::ZEXTLOAD;
670 // Load the value in two parts
672 if (TLI.isLittleEndian()) {
673 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
674 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
675 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
676 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
677 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
678 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
679 MinAlign(Alignment, IncrementSize));
681 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
682 NewLoadedVT,LD->isVolatile(), Alignment);
683 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
684 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
685 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
686 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
687 MinAlign(Alignment, IncrementSize));
690 // aggregate the two parts
691 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
692 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
693 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
695 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
698 SDOperand Ops[] = { Result, TF };
699 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
702 /// UnrollVectorOp - We know that the given vector has a legal type, however
703 /// the operation it performs is not legal and is an operation that we have
704 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
705 /// operating on each element individually.
706 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
707 MVT::ValueType VT = Op.getValueType();
708 assert(isTypeLegal(VT) &&
709 "Caller should expand or promote operands that are not legal!");
710 assert(Op.Val->getNumValues() == 1 &&
711 "Can't unroll a vector with multiple results!");
712 unsigned NE = MVT::getVectorNumElements(VT);
713 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
715 SmallVector<SDOperand, 8> Scalars;
716 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
717 for (unsigned i = 0; i != NE; ++i) {
718 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
719 SDOperand Operand = Op.getOperand(j);
720 MVT::ValueType OperandVT = Operand.getValueType();
721 if (MVT::isVector(OperandVT)) {
722 // A vector operand; extract a single element.
723 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
724 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
727 DAG.getConstant(i, MVT::i32));
729 // A scalar operand; just use it as is.
730 Operands[j] = Operand;
733 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
734 &Operands[0], Operands.size()));
737 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
740 /// GetFPLibCall - Return the right libcall for the given floating point type.
741 static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
742 RTLIB::Libcall Call_F32,
743 RTLIB::Libcall Call_F64,
744 RTLIB::Libcall Call_F80,
745 RTLIB::Libcall Call_PPCF128) {
747 VT == MVT::f32 ? Call_F32 :
748 VT == MVT::f64 ? Call_F64 :
749 VT == MVT::f80 ? Call_F80 :
750 VT == MVT::ppcf128 ? Call_PPCF128 :
751 RTLIB::UNKNOWN_LIBCALL;
754 /// LegalizeOp - We know that the specified value has a legal type, and
755 /// that its operands are legal. Now ensure that the operation itself
756 /// is legal, recursively ensuring that the operands' operations remain
758 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
759 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
762 assert(isTypeLegal(Op.getValueType()) &&
763 "Caller should expand or promote operands that are not legal!");
764 SDNode *Node = Op.Val;
766 // If this operation defines any values that cannot be represented in a
767 // register on this target, make sure to expand or promote them.
768 if (Node->getNumValues() > 1) {
769 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
770 if (getTypeAction(Node->getValueType(i)) != Legal) {
771 HandleOp(Op.getValue(i));
772 assert(LegalizedNodes.count(Op) &&
773 "Handling didn't add legal operands!");
774 return LegalizedNodes[Op];
778 // Note that LegalizeOp may be reentered even from single-use nodes, which
779 // means that we always must cache transformed nodes.
780 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
781 if (I != LegalizedNodes.end()) return I->second;
783 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
784 SDOperand Result = Op;
785 bool isCustom = false;
787 switch (Node->getOpcode()) {
788 case ISD::FrameIndex:
789 case ISD::EntryToken:
791 case ISD::BasicBlock:
792 case ISD::TargetFrameIndex:
793 case ISD::TargetJumpTable:
794 case ISD::TargetConstant:
795 case ISD::TargetConstantFP:
796 case ISD::TargetConstantPool:
797 case ISD::TargetGlobalAddress:
798 case ISD::TargetGlobalTLSAddress:
799 case ISD::TargetExternalSymbol:
802 case ISD::MEMOPERAND:
805 // Primitives must all be legal.
806 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
807 "This must be legal!");
810 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
811 // If this is a target node, legalize it by legalizing the operands then
812 // passing it through.
813 SmallVector<SDOperand, 8> Ops;
814 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
815 Ops.push_back(LegalizeOp(Node->getOperand(i)));
817 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
819 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
820 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
821 return Result.getValue(Op.ResNo);
823 // Otherwise this is an unhandled builtin node. splat.
825 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
827 assert(0 && "Do not know how to legalize this operator!");
829 case ISD::GLOBAL_OFFSET_TABLE:
830 case ISD::GlobalAddress:
831 case ISD::GlobalTLSAddress:
832 case ISD::ExternalSymbol:
833 case ISD::ConstantPool:
834 case ISD::JumpTable: // Nothing to do.
835 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
836 default: assert(0 && "This action is not supported yet!");
837 case TargetLowering::Custom:
838 Tmp1 = TLI.LowerOperation(Op, DAG);
839 if (Tmp1.Val) Result = Tmp1;
840 // FALLTHROUGH if the target doesn't want to lower this op after all.
841 case TargetLowering::Legal:
846 case ISD::RETURNADDR:
847 // The only option for these nodes is to custom lower them. If the target
848 // does not custom lower them, then return zero.
849 Tmp1 = TLI.LowerOperation(Op, DAG);
853 Result = DAG.getConstant(0, TLI.getPointerTy());
855 case ISD::FRAME_TO_ARGS_OFFSET: {
856 MVT::ValueType VT = Node->getValueType(0);
857 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
858 default: assert(0 && "This action is not supported yet!");
859 case TargetLowering::Custom:
860 Result = TLI.LowerOperation(Op, DAG);
861 if (Result.Val) break;
863 case TargetLowering::Legal:
864 Result = DAG.getConstant(0, VT);
869 case ISD::EXCEPTIONADDR: {
870 Tmp1 = LegalizeOp(Node->getOperand(0));
871 MVT::ValueType VT = Node->getValueType(0);
872 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
873 default: assert(0 && "This action is not supported yet!");
874 case TargetLowering::Expand: {
875 unsigned Reg = TLI.getExceptionAddressRegister();
876 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
879 case TargetLowering::Custom:
880 Result = TLI.LowerOperation(Op, DAG);
881 if (Result.Val) break;
883 case TargetLowering::Legal: {
884 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
885 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
891 if (Result.Val->getNumValues() == 1) break;
893 assert(Result.Val->getNumValues() == 2 &&
894 "Cannot return more than two values!");
896 // Since we produced two values, make sure to remember that we
897 // legalized both of them.
898 Tmp1 = LegalizeOp(Result);
899 Tmp2 = LegalizeOp(Result.getValue(1));
900 AddLegalizedOperand(Op.getValue(0), Tmp1);
901 AddLegalizedOperand(Op.getValue(1), Tmp2);
902 return Op.ResNo ? Tmp2 : Tmp1;
903 case ISD::EHSELECTION: {
904 Tmp1 = LegalizeOp(Node->getOperand(0));
905 Tmp2 = LegalizeOp(Node->getOperand(1));
906 MVT::ValueType VT = Node->getValueType(0);
907 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
908 default: assert(0 && "This action is not supported yet!");
909 case TargetLowering::Expand: {
910 unsigned Reg = TLI.getExceptionSelectorRegister();
911 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
914 case TargetLowering::Custom:
915 Result = TLI.LowerOperation(Op, DAG);
916 if (Result.Val) break;
918 case TargetLowering::Legal: {
919 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
920 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
926 if (Result.Val->getNumValues() == 1) break;
928 assert(Result.Val->getNumValues() == 2 &&
929 "Cannot return more than two values!");
931 // Since we produced two values, make sure to remember that we
932 // legalized both of them.
933 Tmp1 = LegalizeOp(Result);
934 Tmp2 = LegalizeOp(Result.getValue(1));
935 AddLegalizedOperand(Op.getValue(0), Tmp1);
936 AddLegalizedOperand(Op.getValue(1), Tmp2);
937 return Op.ResNo ? Tmp2 : Tmp1;
938 case ISD::EH_RETURN: {
939 MVT::ValueType VT = Node->getValueType(0);
940 // The only "good" option for this node is to custom lower it.
941 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
942 default: assert(0 && "This action is not supported at all!");
943 case TargetLowering::Custom:
944 Result = TLI.LowerOperation(Op, DAG);
945 if (Result.Val) break;
947 case TargetLowering::Legal:
948 // Target does not know, how to lower this, lower to noop
949 Result = LegalizeOp(Node->getOperand(0));
954 case ISD::AssertSext:
955 case ISD::AssertZext:
956 Tmp1 = LegalizeOp(Node->getOperand(0));
957 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
959 case ISD::MERGE_VALUES:
960 // Legalize eliminates MERGE_VALUES nodes.
961 Result = Node->getOperand(Op.ResNo);
963 case ISD::CopyFromReg:
964 Tmp1 = LegalizeOp(Node->getOperand(0));
965 Result = Op.getValue(0);
966 if (Node->getNumValues() == 2) {
967 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
969 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
970 if (Node->getNumOperands() == 3) {
971 Tmp2 = LegalizeOp(Node->getOperand(2));
972 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
974 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
976 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
978 // Since CopyFromReg produces two values, make sure to remember that we
979 // legalized both of them.
980 AddLegalizedOperand(Op.getValue(0), Result);
981 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
982 return Result.getValue(Op.ResNo);
984 MVT::ValueType VT = Op.getValueType();
985 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
986 default: assert(0 && "This action is not supported yet!");
987 case TargetLowering::Expand:
988 if (MVT::isInteger(VT))
989 Result = DAG.getConstant(0, VT);
990 else if (MVT::isFloatingPoint(VT))
991 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
994 assert(0 && "Unknown value type!");
996 case TargetLowering::Legal:
1002 case ISD::INTRINSIC_W_CHAIN:
1003 case ISD::INTRINSIC_WO_CHAIN:
1004 case ISD::INTRINSIC_VOID: {
1005 SmallVector<SDOperand, 8> Ops;
1006 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1007 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1008 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1010 // Allow the target to custom lower its intrinsics if it wants to.
1011 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1012 TargetLowering::Custom) {
1013 Tmp3 = TLI.LowerOperation(Result, DAG);
1014 if (Tmp3.Val) Result = Tmp3;
1017 if (Result.Val->getNumValues() == 1) break;
1019 // Must have return value and chain result.
1020 assert(Result.Val->getNumValues() == 2 &&
1021 "Cannot return more than two values!");
1023 // Since loads produce two values, make sure to remember that we
1024 // legalized both of them.
1025 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1026 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1027 return Result.getValue(Op.ResNo);
1031 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
1032 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1034 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
1035 case TargetLowering::Promote:
1036 default: assert(0 && "This action is not supported yet!");
1037 case TargetLowering::Expand: {
1038 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1039 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1040 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
1042 if (MMI && (useDEBUG_LOC || useLABEL)) {
1043 const std::string &FName =
1044 cast<StringSDNode>(Node->getOperand(3))->getValue();
1045 const std::string &DirName =
1046 cast<StringSDNode>(Node->getOperand(4))->getValue();
1047 unsigned SrcFile = MMI->RecordSource(DirName, FName);
1049 SmallVector<SDOperand, 8> Ops;
1050 Ops.push_back(Tmp1); // chain
1051 SDOperand LineOp = Node->getOperand(1);
1052 SDOperand ColOp = Node->getOperand(2);
1055 Ops.push_back(LineOp); // line #
1056 Ops.push_back(ColOp); // col #
1057 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1058 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1060 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
1061 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
1062 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1063 Ops.push_back(DAG.getConstant(ID, MVT::i32));
1064 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label
1065 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size());
1068 Result = Tmp1; // chain
1072 case TargetLowering::Legal:
1073 if (Tmp1 != Node->getOperand(0) ||
1074 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1075 SmallVector<SDOperand, 8> Ops;
1076 Ops.push_back(Tmp1);
1077 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1078 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1079 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1081 // Otherwise promote them.
1082 Ops.push_back(PromoteOp(Node->getOperand(1)));
1083 Ops.push_back(PromoteOp(Node->getOperand(2)));
1085 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1086 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1087 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1094 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1095 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1096 default: assert(0 && "This action is not supported yet!");
1097 case TargetLowering::Legal:
1098 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1099 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1100 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1101 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1106 case ISD::DEBUG_LOC:
1107 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1108 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1109 default: assert(0 && "This action is not supported yet!");
1110 case TargetLowering::Legal:
1111 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1112 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1113 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1114 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1115 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1121 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!");
1122 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1123 default: assert(0 && "This action is not supported yet!");
1124 case TargetLowering::Legal:
1125 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1126 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1127 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand.
1128 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1130 case TargetLowering::Expand:
1131 Result = LegalizeOp(Node->getOperand(0));
1136 case ISD::Constant: {
1137 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1139 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1141 // We know we don't need to expand constants here, constants only have one
1142 // value and we check that it is fine above.
1144 if (opAction == TargetLowering::Custom) {
1145 Tmp1 = TLI.LowerOperation(Result, DAG);
1151 case ISD::ConstantFP: {
1152 // Spill FP immediates to the constant pool if the target cannot directly
1153 // codegen them. Targets often have some immediate values that can be
1154 // efficiently generated into an FP register without a load. We explicitly
1155 // leave these constants as ConstantFP nodes for the target to deal with.
1156 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1158 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1159 default: assert(0 && "This action is not supported yet!");
1160 case TargetLowering::Legal:
1162 case TargetLowering::Custom:
1163 Tmp3 = TLI.LowerOperation(Result, DAG);
1169 case TargetLowering::Expand: {
1170 // Check to see if this FP immediate is already legal.
1171 bool isLegal = false;
1172 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1173 E = TLI.legal_fpimm_end(); I != E; ++I) {
1174 if (CFP->isExactlyValue(*I)) {
1179 // If this is a legal constant, turn it into a TargetConstantFP node.
1182 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1187 case ISD::TokenFactor:
1188 if (Node->getNumOperands() == 2) {
1189 Tmp1 = LegalizeOp(Node->getOperand(0));
1190 Tmp2 = LegalizeOp(Node->getOperand(1));
1191 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1192 } else if (Node->getNumOperands() == 3) {
1193 Tmp1 = LegalizeOp(Node->getOperand(0));
1194 Tmp2 = LegalizeOp(Node->getOperand(1));
1195 Tmp3 = LegalizeOp(Node->getOperand(2));
1196 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1198 SmallVector<SDOperand, 8> Ops;
1199 // Legalize the operands.
1200 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1201 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1202 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1206 case ISD::FORMAL_ARGUMENTS:
1208 // The only option for this is to custom lower it.
1209 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1210 assert(Tmp3.Val && "Target didn't custom lower this node!");
1212 // The number of incoming and outgoing values should match; unless the final
1213 // outgoing value is a flag.
1214 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1215 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1216 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1218 "Lowering call/formal_arguments produced unexpected # results!");
1220 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1221 // remember that we legalized all of them, so it doesn't get relegalized.
1222 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1223 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1225 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1228 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1231 case ISD::EXTRACT_SUBREG: {
1232 Tmp1 = LegalizeOp(Node->getOperand(0));
1233 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1234 assert(idx && "Operand must be a constant");
1235 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1236 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1239 case ISD::INSERT_SUBREG: {
1240 Tmp1 = LegalizeOp(Node->getOperand(0));
1241 Tmp2 = LegalizeOp(Node->getOperand(1));
1242 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1243 assert(idx && "Operand must be a constant");
1244 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1245 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1248 case ISD::BUILD_VECTOR:
1249 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1250 default: assert(0 && "This action is not supported yet!");
1251 case TargetLowering::Custom:
1252 Tmp3 = TLI.LowerOperation(Result, DAG);
1258 case TargetLowering::Expand:
1259 Result = ExpandBUILD_VECTOR(Result.Val);
1263 case ISD::INSERT_VECTOR_ELT:
1264 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1265 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1267 // The type of the value to insert may not be legal, even though the vector
1268 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1270 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1271 default: assert(0 && "Cannot expand insert element operand");
1272 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1273 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1275 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1277 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1278 Node->getValueType(0))) {
1279 default: assert(0 && "This action is not supported yet!");
1280 case TargetLowering::Legal:
1282 case TargetLowering::Custom:
1283 Tmp4 = TLI.LowerOperation(Result, DAG);
1289 case TargetLowering::Expand: {
1290 // If the insert index is a constant, codegen this as a scalar_to_vector,
1291 // then a shuffle that inserts it into the right position in the vector.
1292 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1293 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1294 // match the element type of the vector being created.
1295 if (Tmp2.getValueType() ==
1296 MVT::getVectorElementType(Op.getValueType())) {
1297 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1298 Tmp1.getValueType(), Tmp2);
1300 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1301 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1302 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1304 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1305 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1306 // elt 0 of the RHS.
1307 SmallVector<SDOperand, 8> ShufOps;
1308 for (unsigned i = 0; i != NumElts; ++i) {
1309 if (i != InsertPos->getValue())
1310 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1312 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1314 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1315 &ShufOps[0], ShufOps.size());
1317 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1318 Tmp1, ScVec, ShufMask);
1319 Result = LegalizeOp(Result);
1324 // If the target doesn't support this, we have to spill the input vector
1325 // to a temporary stack slot, update the element, then reload it. This is
1326 // badness. We could also load the value into a vector register (either
1327 // with a "move to register" or "extload into register" instruction, then
1328 // permute it into place, if the idx is a constant and if the idx is
1329 // supported by the target.
1330 MVT::ValueType VT = Tmp1.getValueType();
1331 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1332 MVT::ValueType IdxVT = Tmp3.getValueType();
1333 MVT::ValueType PtrVT = TLI.getPointerTy();
1334 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
1336 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val);
1337 int SPFI = StackPtrFI->getIndex();
1339 // Store the vector.
1340 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
1341 PseudoSourceValue::getFixedStack(),
1344 // Truncate or zero extend offset to target pointer type.
1345 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1346 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1347 // Add the offset to the index.
1348 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1349 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1350 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1351 // Store the scalar value.
1352 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
1353 PseudoSourceValue::getFixedStack(), SPFI, EltVT);
1354 // Load the updated vector.
1355 Result = DAG.getLoad(VT, Ch, StackPtr,
1356 PseudoSourceValue::getFixedStack(), SPFI);
1361 case ISD::SCALAR_TO_VECTOR:
1362 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1363 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1367 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1368 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1369 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1370 Node->getValueType(0))) {
1371 default: assert(0 && "This action is not supported yet!");
1372 case TargetLowering::Legal:
1374 case TargetLowering::Custom:
1375 Tmp3 = TLI.LowerOperation(Result, DAG);
1381 case TargetLowering::Expand:
1382 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1386 case ISD::VECTOR_SHUFFLE:
1387 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1388 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1389 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1391 // Allow targets to custom lower the SHUFFLEs they support.
1392 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1393 default: assert(0 && "Unknown operation action!");
1394 case TargetLowering::Legal:
1395 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1396 "vector shuffle should not be created if not legal!");
1398 case TargetLowering::Custom:
1399 Tmp3 = TLI.LowerOperation(Result, DAG);
1405 case TargetLowering::Expand: {
1406 MVT::ValueType VT = Node->getValueType(0);
1407 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1408 MVT::ValueType PtrVT = TLI.getPointerTy();
1409 SDOperand Mask = Node->getOperand(2);
1410 unsigned NumElems = Mask.getNumOperands();
1411 SmallVector<SDOperand,8> Ops;
1412 for (unsigned i = 0; i != NumElems; ++i) {
1413 SDOperand Arg = Mask.getOperand(i);
1414 if (Arg.getOpcode() == ISD::UNDEF) {
1415 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1417 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1418 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1420 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1421 DAG.getConstant(Idx, PtrVT)));
1423 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1424 DAG.getConstant(Idx - NumElems, PtrVT)));
1427 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1430 case TargetLowering::Promote: {
1431 // Change base type to a different vector type.
1432 MVT::ValueType OVT = Node->getValueType(0);
1433 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1435 // Cast the two input vectors.
1436 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1437 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1439 // Convert the shuffle mask to the right # elements.
1440 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1441 assert(Tmp3.Val && "Shuffle not legal?");
1442 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1443 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1449 case ISD::EXTRACT_VECTOR_ELT:
1450 Tmp1 = Node->getOperand(0);
1451 Tmp2 = LegalizeOp(Node->getOperand(1));
1452 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1453 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1456 case ISD::EXTRACT_SUBVECTOR:
1457 Tmp1 = Node->getOperand(0);
1458 Tmp2 = LegalizeOp(Node->getOperand(1));
1459 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1460 Result = ExpandEXTRACT_SUBVECTOR(Result);
1463 case ISD::CALLSEQ_START: {
1464 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1466 // Recursively Legalize all of the inputs of the call end that do not lead
1467 // to this call start. This ensures that any libcalls that need be inserted
1468 // are inserted *before* the CALLSEQ_START.
1469 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1470 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1471 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1475 // Now that we legalized all of the inputs (which may have inserted
1476 // libcalls) create the new CALLSEQ_START node.
1477 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1479 // Merge in the last call, to ensure that this call start after the last
1481 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1482 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1483 Tmp1 = LegalizeOp(Tmp1);
1486 // Do not try to legalize the target-specific arguments (#1+).
1487 if (Tmp1 != Node->getOperand(0)) {
1488 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1490 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1493 // Remember that the CALLSEQ_START is legalized.
1494 AddLegalizedOperand(Op.getValue(0), Result);
1495 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1496 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1498 // Now that the callseq_start and all of the non-call nodes above this call
1499 // sequence have been legalized, legalize the call itself. During this
1500 // process, no libcalls can/will be inserted, guaranteeing that no calls
1502 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1503 SDOperand InCallSEQ = LastCALLSEQ_END;
1504 // Note that we are selecting this call!
1505 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1506 IsLegalizingCall = true;
1508 // Legalize the call, starting from the CALLSEQ_END.
1509 LegalizeOp(LastCALLSEQ_END);
1510 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1513 case ISD::CALLSEQ_END:
1514 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1515 // will cause this node to be legalized as well as handling libcalls right.
1516 if (LastCALLSEQ_END.Val != Node) {
1517 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1518 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1519 assert(I != LegalizedNodes.end() &&
1520 "Legalizing the call start should have legalized this node!");
1524 // Otherwise, the call start has been legalized and everything is going
1525 // according to plan. Just legalize ourselves normally here.
1526 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1527 // Do not try to legalize the target-specific arguments (#1+), except for
1528 // an optional flag input.
1529 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1530 if (Tmp1 != Node->getOperand(0)) {
1531 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1533 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1536 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1537 if (Tmp1 != Node->getOperand(0) ||
1538 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1539 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1542 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1545 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1546 // This finishes up call legalization.
1547 IsLegalizingCall = false;
1549 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1550 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1551 if (Node->getNumValues() == 2)
1552 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1553 return Result.getValue(Op.ResNo);
1554 case ISD::DYNAMIC_STACKALLOC: {
1555 MVT::ValueType VT = Node->getValueType(0);
1556 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1557 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1558 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1559 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1561 Tmp1 = Result.getValue(0);
1562 Tmp2 = Result.getValue(1);
1563 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1564 default: assert(0 && "This action is not supported yet!");
1565 case TargetLowering::Expand: {
1566 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1567 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1568 " not tell us which reg is the stack pointer!");
1569 SDOperand Chain = Tmp1.getOperand(0);
1571 // Chain the dynamic stack allocation so that it doesn't modify the stack
1572 // pointer when other instructions are using the stack.
1573 Chain = DAG.getCALLSEQ_START(Chain,
1574 DAG.getConstant(0, TLI.getPointerTy()));
1576 SDOperand Size = Tmp2.getOperand(1);
1577 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1578 Chain = SP.getValue(1);
1579 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1580 unsigned StackAlign =
1581 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1582 if (Align > StackAlign)
1583 SP = DAG.getNode(ISD::AND, VT, SP,
1584 DAG.getConstant(-(uint64_t)Align, VT));
1585 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1586 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1589 DAG.getCALLSEQ_END(Chain,
1590 DAG.getConstant(0, TLI.getPointerTy()),
1591 DAG.getConstant(0, TLI.getPointerTy()),
1594 Tmp1 = LegalizeOp(Tmp1);
1595 Tmp2 = LegalizeOp(Tmp2);
1598 case TargetLowering::Custom:
1599 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1601 Tmp1 = LegalizeOp(Tmp3);
1602 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1605 case TargetLowering::Legal:
1608 // Since this op produce two values, make sure to remember that we
1609 // legalized both of them.
1610 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1611 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1612 return Op.ResNo ? Tmp2 : Tmp1;
1614 case ISD::INLINEASM: {
1615 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1616 bool Changed = false;
1617 // Legalize all of the operands of the inline asm, in case they are nodes
1618 // that need to be expanded or something. Note we skip the asm string and
1619 // all of the TargetConstant flags.
1620 SDOperand Op = LegalizeOp(Ops[0]);
1621 Changed = Op != Ops[0];
1624 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1625 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1626 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1627 for (++i; NumVals; ++i, --NumVals) {
1628 SDOperand Op = LegalizeOp(Ops[i]);
1637 Op = LegalizeOp(Ops.back());
1638 Changed |= Op != Ops.back();
1643 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1645 // INLINE asm returns a chain and flag, make sure to add both to the map.
1646 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1647 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1648 return Result.getValue(Op.ResNo);
1651 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1652 // Ensure that libcalls are emitted before a branch.
1653 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1654 Tmp1 = LegalizeOp(Tmp1);
1655 LastCALLSEQ_END = DAG.getEntryNode();
1657 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1660 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1661 // Ensure that libcalls are emitted before a branch.
1662 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1663 Tmp1 = LegalizeOp(Tmp1);
1664 LastCALLSEQ_END = DAG.getEntryNode();
1666 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1667 default: assert(0 && "Indirect target must be legal type (pointer)!");
1669 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1672 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1675 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1676 // Ensure that libcalls are emitted before a branch.
1677 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1678 Tmp1 = LegalizeOp(Tmp1);
1679 LastCALLSEQ_END = DAG.getEntryNode();
1681 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1682 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1684 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1685 default: assert(0 && "This action is not supported yet!");
1686 case TargetLowering::Legal: break;
1687 case TargetLowering::Custom:
1688 Tmp1 = TLI.LowerOperation(Result, DAG);
1689 if (Tmp1.Val) Result = Tmp1;
1691 case TargetLowering::Expand: {
1692 SDOperand Chain = Result.getOperand(0);
1693 SDOperand Table = Result.getOperand(1);
1694 SDOperand Index = Result.getOperand(2);
1696 MVT::ValueType PTy = TLI.getPointerTy();
1697 MachineFunction &MF = DAG.getMachineFunction();
1698 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1699 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1700 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1703 switch (EntrySize) {
1704 default: assert(0 && "Size of jump table not supported yet."); break;
1705 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1706 PseudoSourceValue::getJumpTable(), 0); break;
1707 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1708 PseudoSourceValue::getJumpTable(), 0); break;
1712 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1713 // For PIC, the sequence is:
1714 // BRIND(load(Jumptable + index) + RelocBase)
1715 // RelocBase can be JumpTable, GOT or some sort of global base.
1716 if (PTy != MVT::i32)
1717 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1718 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1719 TLI.getPICJumpTableRelocBase(Table, DAG));
1721 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1726 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1727 // Ensure that libcalls are emitted before a return.
1728 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1729 Tmp1 = LegalizeOp(Tmp1);
1730 LastCALLSEQ_END = DAG.getEntryNode();
1732 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1733 case Expand: assert(0 && "It's impossible to expand bools");
1735 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1738 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1740 // The top bits of the promoted condition are not necessarily zero, ensure
1741 // that the value is properly zero extended.
1742 if (!DAG.MaskedValueIsZero(Tmp2,
1743 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1744 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1748 // Basic block destination (Op#2) is always legal.
1749 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1751 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1752 default: assert(0 && "This action is not supported yet!");
1753 case TargetLowering::Legal: break;
1754 case TargetLowering::Custom:
1755 Tmp1 = TLI.LowerOperation(Result, DAG);
1756 if (Tmp1.Val) Result = Tmp1;
1758 case TargetLowering::Expand:
1759 // Expand brcond's setcc into its constituent parts and create a BR_CC
1761 if (Tmp2.getOpcode() == ISD::SETCC) {
1762 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1763 Tmp2.getOperand(0), Tmp2.getOperand(1),
1764 Node->getOperand(2));
1766 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1767 DAG.getCondCode(ISD::SETNE), Tmp2,
1768 DAG.getConstant(0, Tmp2.getValueType()),
1769 Node->getOperand(2));
1775 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1776 // Ensure that libcalls are emitted before a branch.
1777 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1778 Tmp1 = LegalizeOp(Tmp1);
1779 Tmp2 = Node->getOperand(2); // LHS
1780 Tmp3 = Node->getOperand(3); // RHS
1781 Tmp4 = Node->getOperand(1); // CC
1783 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1784 LastCALLSEQ_END = DAG.getEntryNode();
1786 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1787 // the LHS is a legal SETCC itself. In this case, we need to compare
1788 // the result against zero to select between true and false values.
1789 if (Tmp3.Val == 0) {
1790 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1791 Tmp4 = DAG.getCondCode(ISD::SETNE);
1794 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1795 Node->getOperand(4));
1797 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1798 default: assert(0 && "Unexpected action for BR_CC!");
1799 case TargetLowering::Legal: break;
1800 case TargetLowering::Custom:
1801 Tmp4 = TLI.LowerOperation(Result, DAG);
1802 if (Tmp4.Val) Result = Tmp4;
1807 LoadSDNode *LD = cast<LoadSDNode>(Node);
1808 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1809 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1811 ISD::LoadExtType ExtType = LD->getExtensionType();
1812 if (ExtType == ISD::NON_EXTLOAD) {
1813 MVT::ValueType VT = Node->getValueType(0);
1814 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1815 Tmp3 = Result.getValue(0);
1816 Tmp4 = Result.getValue(1);
1818 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1819 default: assert(0 && "This action is not supported yet!");
1820 case TargetLowering::Legal:
1821 // If this is an unaligned load and the target doesn't support it,
1823 if (!TLI.allowsUnalignedMemoryAccesses()) {
1824 unsigned ABIAlignment = TLI.getTargetData()->
1825 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
1826 if (LD->getAlignment() < ABIAlignment){
1827 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1829 Tmp3 = Result.getOperand(0);
1830 Tmp4 = Result.getOperand(1);
1831 Tmp3 = LegalizeOp(Tmp3);
1832 Tmp4 = LegalizeOp(Tmp4);
1836 case TargetLowering::Custom:
1837 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1839 Tmp3 = LegalizeOp(Tmp1);
1840 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1843 case TargetLowering::Promote: {
1844 // Only promote a load of vector type to another.
1845 assert(MVT::isVector(VT) && "Cannot promote this load!");
1846 // Change base type to a different vector type.
1847 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1849 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1850 LD->getSrcValueOffset(),
1851 LD->isVolatile(), LD->getAlignment());
1852 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1853 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1857 // Since loads produce two values, make sure to remember that we
1858 // legalized both of them.
1859 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1860 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1861 return Op.ResNo ? Tmp4 : Tmp3;
1863 MVT::ValueType SrcVT = LD->getMemoryVT();
1864 unsigned SrcWidth = MVT::getSizeInBits(SrcVT);
1865 int SVOffset = LD->getSrcValueOffset();
1866 unsigned Alignment = LD->getAlignment();
1867 bool isVolatile = LD->isVolatile();
1869 if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) &&
1870 // Some targets pretend to have an i1 loading operation, and actually
1871 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1872 // bits are guaranteed to be zero; it helps the optimizers understand
1873 // that these bits are zero. It is also useful for EXTLOAD, since it
1874 // tells the optimizers that those bits are undefined. It would be
1875 // nice to have an effective generic way of getting these benefits...
1876 // Until such a way is found, don't insist on promoting i1 here.
1877 (SrcVT != MVT::i1 ||
1878 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1879 // Promote to a byte-sized load if not loading an integral number of
1880 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1881 unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT);
1882 MVT::ValueType NVT = MVT::getIntegerType(NewWidth);
1885 // The extra bits are guaranteed to be zero, since we stored them that
1886 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1888 ISD::LoadExtType NewExtType =
1889 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1891 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
1892 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1893 NVT, isVolatile, Alignment);
1895 Ch = Result.getValue(1); // The chain.
1897 if (ExtType == ISD::SEXTLOAD)
1898 // Having the top bits zero doesn't help when sign extending.
1899 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1900 Result, DAG.getValueType(SrcVT));
1901 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1902 // All the top bits are guaranteed to be zero - inform the optimizers.
1903 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
1904 DAG.getValueType(SrcVT));
1906 Tmp1 = LegalizeOp(Result);
1907 Tmp2 = LegalizeOp(Ch);
1908 } else if (SrcWidth & (SrcWidth - 1)) {
1909 // If not loading a power-of-2 number of bits, expand as two loads.
1910 assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) &&
1911 "Unsupported extload!");
1912 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1913 assert(RoundWidth < SrcWidth);
1914 unsigned ExtraWidth = SrcWidth - RoundWidth;
1915 assert(ExtraWidth < RoundWidth);
1916 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1917 "Load size not an integral number of bytes!");
1918 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
1919 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
1920 SDOperand Lo, Hi, Ch;
1921 unsigned IncrementSize;
1923 if (TLI.isLittleEndian()) {
1924 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1925 // Load the bottom RoundWidth bits.
1926 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
1927 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1930 // Load the remaining ExtraWidth bits.
1931 IncrementSize = RoundWidth / 8;
1932 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1933 DAG.getIntPtrConstant(IncrementSize));
1934 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1935 LD->getSrcValue(), SVOffset + IncrementSize,
1936 ExtraVT, isVolatile,
1937 MinAlign(Alignment, IncrementSize));
1939 // Build a factor node to remember that this load is independent of the
1941 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1944 // Move the top bits to the right place.
1945 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
1946 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1948 // Join the hi and lo parts.
1949 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
1951 // Big endian - avoid unaligned loads.
1952 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1953 // Load the top RoundWidth bits.
1954 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1955 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1958 // Load the remaining ExtraWidth bits.
1959 IncrementSize = RoundWidth / 8;
1960 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1961 DAG.getIntPtrConstant(IncrementSize));
1962 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
1963 LD->getSrcValue(), SVOffset + IncrementSize,
1964 ExtraVT, isVolatile,
1965 MinAlign(Alignment, IncrementSize));
1967 // Build a factor node to remember that this load is independent of the
1969 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1972 // Move the top bits to the right place.
1973 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
1974 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1976 // Join the hi and lo parts.
1977 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
1980 Tmp1 = LegalizeOp(Result);
1981 Tmp2 = LegalizeOp(Ch);
1983 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1984 default: assert(0 && "This action is not supported yet!");
1985 case TargetLowering::Custom:
1988 case TargetLowering::Legal:
1989 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1990 Tmp1 = Result.getValue(0);
1991 Tmp2 = Result.getValue(1);
1994 Tmp3 = TLI.LowerOperation(Result, DAG);
1996 Tmp1 = LegalizeOp(Tmp3);
1997 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2000 // If this is an unaligned load and the target doesn't support it,
2002 if (!TLI.allowsUnalignedMemoryAccesses()) {
2003 unsigned ABIAlignment = TLI.getTargetData()->
2004 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
2005 if (LD->getAlignment() < ABIAlignment){
2006 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
2008 Tmp1 = Result.getOperand(0);
2009 Tmp2 = Result.getOperand(1);
2010 Tmp1 = LegalizeOp(Tmp1);
2011 Tmp2 = LegalizeOp(Tmp2);
2016 case TargetLowering::Expand:
2017 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2018 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2019 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2020 LD->getSrcValueOffset(),
2021 LD->isVolatile(), LD->getAlignment());
2022 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2023 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2024 Tmp2 = LegalizeOp(Load.getValue(1));
2027 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2028 // Turn the unsupported load into an EXTLOAD followed by an explicit
2029 // zero/sign extend inreg.
2030 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2031 Tmp1, Tmp2, LD->getSrcValue(),
2032 LD->getSrcValueOffset(), SrcVT,
2033 LD->isVolatile(), LD->getAlignment());
2035 if (ExtType == ISD::SEXTLOAD)
2036 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2037 Result, DAG.getValueType(SrcVT));
2039 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2040 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2041 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2046 // Since loads produce two values, make sure to remember that we legalized
2048 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2049 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2050 return Op.ResNo ? Tmp2 : Tmp1;
2053 case ISD::EXTRACT_ELEMENT: {
2054 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
2055 switch (getTypeAction(OpTy)) {
2056 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2058 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2060 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2061 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
2062 TLI.getShiftAmountTy()));
2063 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2066 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2067 Node->getOperand(0));
2071 // Get both the low and high parts.
2072 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2073 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2074 Result = Tmp2; // 1 -> Hi
2076 Result = Tmp1; // 0 -> Lo
2082 case ISD::CopyToReg:
2083 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2085 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2086 "Register type must be legal!");
2087 // Legalize the incoming value (must be a legal type).
2088 Tmp2 = LegalizeOp(Node->getOperand(2));
2089 if (Node->getNumValues() == 1) {
2090 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2092 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2093 if (Node->getNumOperands() == 4) {
2094 Tmp3 = LegalizeOp(Node->getOperand(3));
2095 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2098 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2101 // Since this produces two values, make sure to remember that we legalized
2103 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2104 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2110 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2112 // Ensure that libcalls are emitted before a return.
2113 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2114 Tmp1 = LegalizeOp(Tmp1);
2115 LastCALLSEQ_END = DAG.getEntryNode();
2117 switch (Node->getNumOperands()) {
2119 Tmp2 = Node->getOperand(1);
2120 Tmp3 = Node->getOperand(2); // Signness
2121 switch (getTypeAction(Tmp2.getValueType())) {
2123 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2126 if (!MVT::isVector(Tmp2.getValueType())) {
2128 ExpandOp(Tmp2, Lo, Hi);
2130 // Big endian systems want the hi reg first.
2131 if (TLI.isBigEndian())
2135 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2137 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2138 Result = LegalizeOp(Result);
2140 SDNode *InVal = Tmp2.Val;
2141 int InIx = Tmp2.ResNo;
2142 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
2143 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
2145 // Figure out if there is a simple type corresponding to this Vector
2146 // type. If so, convert to the vector type.
2147 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2148 if (TLI.isTypeLegal(TVT)) {
2149 // Turn this into a return of the vector type.
2150 Tmp2 = LegalizeOp(Tmp2);
2151 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2152 } else if (NumElems == 1) {
2153 // Turn this into a return of the scalar type.
2154 Tmp2 = ScalarizeVectorOp(Tmp2);
2155 Tmp2 = LegalizeOp(Tmp2);
2156 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2158 // FIXME: Returns of gcc generic vectors smaller than a legal type
2159 // should be returned in integer registers!
2161 // The scalarized value type may not be legal, e.g. it might require
2162 // promotion or expansion. Relegalize the return.
2163 Result = LegalizeOp(Result);
2165 // FIXME: Returns of gcc generic vectors larger than a legal vector
2166 // type should be returned by reference!
2168 SplitVectorOp(Tmp2, Lo, Hi);
2169 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2170 Result = LegalizeOp(Result);
2175 Tmp2 = PromoteOp(Node->getOperand(1));
2176 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2177 Result = LegalizeOp(Result);
2182 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2184 default: { // ret <values>
2185 SmallVector<SDOperand, 8> NewValues;
2186 NewValues.push_back(Tmp1);
2187 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2188 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2190 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2191 NewValues.push_back(Node->getOperand(i+1));
2195 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
2196 "FIXME: TODO: implement returning non-legal vector types!");
2197 ExpandOp(Node->getOperand(i), Lo, Hi);
2198 NewValues.push_back(Lo);
2199 NewValues.push_back(Node->getOperand(i+1));
2201 NewValues.push_back(Hi);
2202 NewValues.push_back(Node->getOperand(i+1));
2207 assert(0 && "Can't promote multiple return value yet!");
2210 if (NewValues.size() == Node->getNumOperands())
2211 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2213 Result = DAG.getNode(ISD::RET, MVT::Other,
2214 &NewValues[0], NewValues.size());
2219 if (Result.getOpcode() == ISD::RET) {
2220 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2221 default: assert(0 && "This action is not supported yet!");
2222 case TargetLowering::Legal: break;
2223 case TargetLowering::Custom:
2224 Tmp1 = TLI.LowerOperation(Result, DAG);
2225 if (Tmp1.Val) Result = Tmp1;
2231 StoreSDNode *ST = cast<StoreSDNode>(Node);
2232 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2233 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2234 int SVOffset = ST->getSrcValueOffset();
2235 unsigned Alignment = ST->getAlignment();
2236 bool isVolatile = ST->isVolatile();
2238 if (!ST->isTruncatingStore()) {
2239 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2240 // FIXME: We shouldn't do this for TargetConstantFP's.
2241 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2242 // to phase ordering between legalized code and the dag combiner. This
2243 // probably means that we need to integrate dag combiner and legalizer
2245 // We generally can't do this one for long doubles.
2246 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2247 if (CFP->getValueType(0) == MVT::f32 &&
2248 getTypeAction(MVT::i32) == Legal) {
2249 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF().
2250 convertToAPInt().getZExtValue(),
2252 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2253 SVOffset, isVolatile, Alignment);
2255 } else if (CFP->getValueType(0) == MVT::f64) {
2256 // If this target supports 64-bit registers, do a single 64-bit store.
2257 if (getTypeAction(MVT::i64) == Legal) {
2258 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2259 getZExtValue(), MVT::i64);
2260 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2261 SVOffset, isVolatile, Alignment);
2263 } else if (getTypeAction(MVT::i32) == Legal) {
2264 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2265 // stores. If the target supports neither 32- nor 64-bits, this
2266 // xform is certainly not worth it.
2267 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue();
2268 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32);
2269 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32);
2270 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2272 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2273 SVOffset, isVolatile, Alignment);
2274 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2275 DAG.getIntPtrConstant(4));
2276 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2277 isVolatile, MinAlign(Alignment, 4U));
2279 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2285 switch (getTypeAction(ST->getMemoryVT())) {
2287 Tmp3 = LegalizeOp(ST->getValue());
2288 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2291 MVT::ValueType VT = Tmp3.getValueType();
2292 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2293 default: assert(0 && "This action is not supported yet!");
2294 case TargetLowering::Legal:
2295 // If this is an unaligned store and the target doesn't support it,
2297 if (!TLI.allowsUnalignedMemoryAccesses()) {
2298 unsigned ABIAlignment = TLI.getTargetData()->
2299 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2300 if (ST->getAlignment() < ABIAlignment)
2301 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2305 case TargetLowering::Custom:
2306 Tmp1 = TLI.LowerOperation(Result, DAG);
2307 if (Tmp1.Val) Result = Tmp1;
2309 case TargetLowering::Promote:
2310 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2311 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2312 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2313 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2314 ST->getSrcValue(), SVOffset, isVolatile,
2321 // Truncate the value and store the result.
2322 Tmp3 = PromoteOp(ST->getValue());
2323 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2324 SVOffset, ST->getMemoryVT(),
2325 isVolatile, Alignment);
2329 unsigned IncrementSize = 0;
2332 // If this is a vector type, then we have to calculate the increment as
2333 // the product of the element size in bytes, and the number of elements
2334 // in the high half of the vector.
2335 if (MVT::isVector(ST->getValue().getValueType())) {
2336 SDNode *InVal = ST->getValue().Val;
2337 int InIx = ST->getValue().ResNo;
2338 MVT::ValueType InVT = InVal->getValueType(InIx);
2339 unsigned NumElems = MVT::getVectorNumElements(InVT);
2340 MVT::ValueType EVT = MVT::getVectorElementType(InVT);
2342 // Figure out if there is a simple type corresponding to this Vector
2343 // type. If so, convert to the vector type.
2344 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2345 if (TLI.isTypeLegal(TVT)) {
2346 // Turn this into a normal store of the vector type.
2347 Tmp3 = LegalizeOp(Node->getOperand(1));
2348 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2349 SVOffset, isVolatile, Alignment);
2350 Result = LegalizeOp(Result);
2352 } else if (NumElems == 1) {
2353 // Turn this into a normal store of the scalar type.
2354 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
2355 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2356 SVOffset, isVolatile, Alignment);
2357 // The scalarized value type may not be legal, e.g. it might require
2358 // promotion or expansion. Relegalize the scalar store.
2359 Result = LegalizeOp(Result);
2362 SplitVectorOp(Node->getOperand(1), Lo, Hi);
2363 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
2364 MVT::getSizeInBits(EVT)/8;
2367 ExpandOp(Node->getOperand(1), Lo, Hi);
2368 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2370 if (TLI.isBigEndian())
2374 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2375 SVOffset, isVolatile, Alignment);
2377 if (Hi.Val == NULL) {
2378 // Must be int <-> float one-to-one expansion.
2383 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2384 DAG.getIntPtrConstant(IncrementSize));
2385 assert(isTypeLegal(Tmp2.getValueType()) &&
2386 "Pointers must be legal!");
2387 SVOffset += IncrementSize;
2388 Alignment = MinAlign(Alignment, IncrementSize);
2389 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2390 SVOffset, isVolatile, Alignment);
2391 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2395 switch (getTypeAction(ST->getValue().getValueType())) {
2397 Tmp3 = LegalizeOp(ST->getValue());
2400 // We can promote the value, the truncstore will still take care of it.
2401 Tmp3 = PromoteOp(ST->getValue());
2404 // Just store the low part. This may become a non-trunc store, so make
2405 // sure to use getTruncStore, not UpdateNodeOperands below.
2406 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2407 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2408 SVOffset, MVT::i8, isVolatile, Alignment);
2411 MVT::ValueType StVT = ST->getMemoryVT();
2412 unsigned StWidth = MVT::getSizeInBits(StVT);
2414 if (StWidth != MVT::getStoreSizeInBits(StVT)) {
2415 // Promote to a byte-sized store with upper bits zero if not
2416 // storing an integral number of bytes. For example, promote
2417 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2418 MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT));
2419 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2420 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2421 SVOffset, NVT, isVolatile, Alignment);
2422 } else if (StWidth & (StWidth - 1)) {
2423 // If not storing a power-of-2 number of bits, expand as two stores.
2424 assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) &&
2425 "Unsupported truncstore!");
2426 unsigned RoundWidth = 1 << Log2_32(StWidth);
2427 assert(RoundWidth < StWidth);
2428 unsigned ExtraWidth = StWidth - RoundWidth;
2429 assert(ExtraWidth < RoundWidth);
2430 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2431 "Store size not an integral number of bytes!");
2432 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
2433 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
2435 unsigned IncrementSize;
2437 if (TLI.isLittleEndian()) {
2438 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2439 // Store the bottom RoundWidth bits.
2440 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2442 isVolatile, Alignment);
2444 // Store the remaining ExtraWidth bits.
2445 IncrementSize = RoundWidth / 8;
2446 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2447 DAG.getIntPtrConstant(IncrementSize));
2448 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2449 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2450 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2451 SVOffset + IncrementSize, ExtraVT, isVolatile,
2452 MinAlign(Alignment, IncrementSize));
2454 // Big endian - avoid unaligned stores.
2455 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2456 // Store the top RoundWidth bits.
2457 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2458 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2459 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2460 RoundVT, isVolatile, Alignment);
2462 // Store the remaining ExtraWidth bits.
2463 IncrementSize = RoundWidth / 8;
2464 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2465 DAG.getIntPtrConstant(IncrementSize));
2466 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2467 SVOffset + IncrementSize, ExtraVT, isVolatile,
2468 MinAlign(Alignment, IncrementSize));
2471 // The order of the stores doesn't matter.
2472 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2474 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2475 Tmp2 != ST->getBasePtr())
2476 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2479 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2480 default: assert(0 && "This action is not supported yet!");
2481 case TargetLowering::Legal:
2482 // If this is an unaligned store and the target doesn't support it,
2484 if (!TLI.allowsUnalignedMemoryAccesses()) {
2485 unsigned ABIAlignment = TLI.getTargetData()->
2486 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2487 if (ST->getAlignment() < ABIAlignment)
2488 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2492 case TargetLowering::Custom:
2493 Result = TLI.LowerOperation(Result, DAG);
2496 // TRUNCSTORE:i16 i32 -> STORE i16
2497 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2498 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2499 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2500 isVolatile, Alignment);
2508 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2509 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2511 case ISD::STACKSAVE:
2512 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2513 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2514 Tmp1 = Result.getValue(0);
2515 Tmp2 = Result.getValue(1);
2517 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2518 default: assert(0 && "This action is not supported yet!");
2519 case TargetLowering::Legal: break;
2520 case TargetLowering::Custom:
2521 Tmp3 = TLI.LowerOperation(Result, DAG);
2523 Tmp1 = LegalizeOp(Tmp3);
2524 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2527 case TargetLowering::Expand:
2528 // Expand to CopyFromReg if the target set
2529 // StackPointerRegisterToSaveRestore.
2530 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2531 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2532 Node->getValueType(0));
2533 Tmp2 = Tmp1.getValue(1);
2535 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2536 Tmp2 = Node->getOperand(0);
2541 // Since stacksave produce two values, make sure to remember that we
2542 // legalized both of them.
2543 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2544 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2545 return Op.ResNo ? Tmp2 : Tmp1;
2547 case ISD::STACKRESTORE:
2548 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2549 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2550 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2552 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2553 default: assert(0 && "This action is not supported yet!");
2554 case TargetLowering::Legal: break;
2555 case TargetLowering::Custom:
2556 Tmp1 = TLI.LowerOperation(Result, DAG);
2557 if (Tmp1.Val) Result = Tmp1;
2559 case TargetLowering::Expand:
2560 // Expand to CopyToReg if the target set
2561 // StackPointerRegisterToSaveRestore.
2562 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2563 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2571 case ISD::READCYCLECOUNTER:
2572 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2573 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2574 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2575 Node->getValueType(0))) {
2576 default: assert(0 && "This action is not supported yet!");
2577 case TargetLowering::Legal:
2578 Tmp1 = Result.getValue(0);
2579 Tmp2 = Result.getValue(1);
2581 case TargetLowering::Custom:
2582 Result = TLI.LowerOperation(Result, DAG);
2583 Tmp1 = LegalizeOp(Result.getValue(0));
2584 Tmp2 = LegalizeOp(Result.getValue(1));
2588 // Since rdcc produce two values, make sure to remember that we legalized
2590 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2591 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2595 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2596 case Expand: assert(0 && "It's impossible to expand bools");
2598 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2601 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2602 // Make sure the condition is either zero or one.
2603 if (!DAG.MaskedValueIsZero(Tmp1,
2604 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2605 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2608 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2609 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2611 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2613 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2614 default: assert(0 && "This action is not supported yet!");
2615 case TargetLowering::Legal: break;
2616 case TargetLowering::Custom: {
2617 Tmp1 = TLI.LowerOperation(Result, DAG);
2618 if (Tmp1.Val) Result = Tmp1;
2621 case TargetLowering::Expand:
2622 if (Tmp1.getOpcode() == ISD::SETCC) {
2623 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2625 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2627 Result = DAG.getSelectCC(Tmp1,
2628 DAG.getConstant(0, Tmp1.getValueType()),
2629 Tmp2, Tmp3, ISD::SETNE);
2632 case TargetLowering::Promote: {
2633 MVT::ValueType NVT =
2634 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2635 unsigned ExtOp, TruncOp;
2636 if (MVT::isVector(Tmp2.getValueType())) {
2637 ExtOp = ISD::BIT_CONVERT;
2638 TruncOp = ISD::BIT_CONVERT;
2639 } else if (MVT::isInteger(Tmp2.getValueType())) {
2640 ExtOp = ISD::ANY_EXTEND;
2641 TruncOp = ISD::TRUNCATE;
2643 ExtOp = ISD::FP_EXTEND;
2644 TruncOp = ISD::FP_ROUND;
2646 // Promote each of the values to the new type.
2647 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2648 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2649 // Perform the larger operation, then round down.
2650 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2651 if (TruncOp != ISD::FP_ROUND)
2652 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2654 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2655 DAG.getIntPtrConstant(0));
2660 case ISD::SELECT_CC: {
2661 Tmp1 = Node->getOperand(0); // LHS
2662 Tmp2 = Node->getOperand(1); // RHS
2663 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2664 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2665 SDOperand CC = Node->getOperand(4);
2667 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2669 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2670 // the LHS is a legal SETCC itself. In this case, we need to compare
2671 // the result against zero to select between true and false values.
2672 if (Tmp2.Val == 0) {
2673 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2674 CC = DAG.getCondCode(ISD::SETNE);
2676 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2678 // Everything is legal, see if we should expand this op or something.
2679 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2680 default: assert(0 && "This action is not supported yet!");
2681 case TargetLowering::Legal: break;
2682 case TargetLowering::Custom:
2683 Tmp1 = TLI.LowerOperation(Result, DAG);
2684 if (Tmp1.Val) Result = Tmp1;
2690 Tmp1 = Node->getOperand(0);
2691 Tmp2 = Node->getOperand(1);
2692 Tmp3 = Node->getOperand(2);
2693 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2695 // If we had to Expand the SetCC operands into a SELECT node, then it may
2696 // not always be possible to return a true LHS & RHS. In this case, just
2697 // return the value we legalized, returned in the LHS
2698 if (Tmp2.Val == 0) {
2703 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2704 default: assert(0 && "Cannot handle this action for SETCC yet!");
2705 case TargetLowering::Custom:
2708 case TargetLowering::Legal:
2709 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2711 Tmp4 = TLI.LowerOperation(Result, DAG);
2712 if (Tmp4.Val) Result = Tmp4;
2715 case TargetLowering::Promote: {
2716 // First step, figure out the appropriate operation to use.
2717 // Allow SETCC to not be supported for all legal data types
2718 // Mostly this targets FP
2719 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2720 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2722 // Scan for the appropriate larger type to use.
2724 NewInTy = (MVT::ValueType)(NewInTy+1);
2726 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2727 "Fell off of the edge of the integer world");
2728 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2729 "Fell off of the edge of the floating point world");
2731 // If the target supports SETCC of this type, use it.
2732 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2735 if (MVT::isInteger(NewInTy))
2736 assert(0 && "Cannot promote Legal Integer SETCC yet");
2738 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2739 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2741 Tmp1 = LegalizeOp(Tmp1);
2742 Tmp2 = LegalizeOp(Tmp2);
2743 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2744 Result = LegalizeOp(Result);
2747 case TargetLowering::Expand:
2748 // Expand a setcc node into a select_cc of the same condition, lhs, and
2749 // rhs that selects between const 1 (true) and const 0 (false).
2750 MVT::ValueType VT = Node->getValueType(0);
2751 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2752 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2759 case ISD::MEMMOVE: {
2760 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2761 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2763 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2764 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2765 case Expand: assert(0 && "Cannot expand a byte!");
2767 Tmp3 = LegalizeOp(Node->getOperand(2));
2770 Tmp3 = PromoteOp(Node->getOperand(2));
2774 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2778 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2780 // Length is too big, just take the lo-part of the length.
2782 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2786 Tmp4 = LegalizeOp(Node->getOperand(3));
2789 Tmp4 = PromoteOp(Node->getOperand(3));
2794 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2795 case Expand: assert(0 && "Cannot expand this yet!");
2797 Tmp5 = LegalizeOp(Node->getOperand(4));
2800 Tmp5 = PromoteOp(Node->getOperand(4));
2805 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool
2806 case Expand: assert(0 && "Cannot expand this yet!");
2808 Tmp6 = LegalizeOp(Node->getOperand(5));
2811 Tmp6 = PromoteOp(Node->getOperand(5));
2815 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2816 default: assert(0 && "This action not implemented for this operation!");
2817 case TargetLowering::Custom:
2820 case TargetLowering::Legal: {
2821 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 };
2822 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
2824 Tmp1 = TLI.LowerOperation(Result, DAG);
2825 if (Tmp1.Val) Result = Tmp1;
2829 case TargetLowering::Expand: {
2830 // Otherwise, the target does not support this operation. Lower the
2831 // operation to an explicit libcall as appropriate.
2832 MVT::ValueType IntPtr = TLI.getPointerTy();
2833 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2834 TargetLowering::ArgListTy Args;
2835 TargetLowering::ArgListEntry Entry;
2837 const char *FnName = 0;
2838 if (Node->getOpcode() == ISD::MEMSET) {
2839 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2840 Args.push_back(Entry);
2841 // Extend the (previously legalized) ubyte argument to be an int value
2843 if (Tmp3.getValueType() > MVT::i32)
2844 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2846 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2847 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2848 Args.push_back(Entry);
2849 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2850 Args.push_back(Entry);
2853 } else if (Node->getOpcode() == ISD::MEMCPY ||
2854 Node->getOpcode() == ISD::MEMMOVE) {
2855 Entry.Ty = IntPtrTy;
2856 Entry.Node = Tmp2; Args.push_back(Entry);
2857 Entry.Node = Tmp3; Args.push_back(Entry);
2858 Entry.Node = Tmp4; Args.push_back(Entry);
2859 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2861 assert(0 && "Unknown op!");
2864 std::pair<SDOperand,SDOperand> CallResult =
2865 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2866 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2867 Result = CallResult.second;
2874 case ISD::SHL_PARTS:
2875 case ISD::SRA_PARTS:
2876 case ISD::SRL_PARTS: {
2877 SmallVector<SDOperand, 8> Ops;
2878 bool Changed = false;
2879 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2880 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2881 Changed |= Ops.back() != Node->getOperand(i);
2884 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2886 switch (TLI.getOperationAction(Node->getOpcode(),
2887 Node->getValueType(0))) {
2888 default: assert(0 && "This action is not supported yet!");
2889 case TargetLowering::Legal: break;
2890 case TargetLowering::Custom:
2891 Tmp1 = TLI.LowerOperation(Result, DAG);
2893 SDOperand Tmp2, RetVal(0, 0);
2894 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2895 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2896 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2900 assert(RetVal.Val && "Illegal result number");
2906 // Since these produce multiple values, make sure to remember that we
2907 // legalized all of them.
2908 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2909 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2910 return Result.getValue(Op.ResNo);
2932 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2933 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2934 case Expand: assert(0 && "Not possible");
2936 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2939 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2943 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2945 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2946 default: assert(0 && "BinOp legalize operation not supported");
2947 case TargetLowering::Legal: break;
2948 case TargetLowering::Custom:
2949 Tmp1 = TLI.LowerOperation(Result, DAG);
2950 if (Tmp1.Val) Result = Tmp1;
2952 case TargetLowering::Expand: {
2953 MVT::ValueType VT = Op.getValueType();
2955 // See if multiply or divide can be lowered using two-result operations.
2956 SDVTList VTs = DAG.getVTList(VT, VT);
2957 if (Node->getOpcode() == ISD::MUL) {
2958 // We just need the low half of the multiply; try both the signed
2959 // and unsigned forms. If the target supports both SMUL_LOHI and
2960 // UMUL_LOHI, form a preference by checking which forms of plain
2961 // MULH it supports.
2962 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2963 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2964 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2965 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2966 unsigned OpToUse = 0;
2967 if (HasSMUL_LOHI && !HasMULHS) {
2968 OpToUse = ISD::SMUL_LOHI;
2969 } else if (HasUMUL_LOHI && !HasMULHU) {
2970 OpToUse = ISD::UMUL_LOHI;
2971 } else if (HasSMUL_LOHI) {
2972 OpToUse = ISD::SMUL_LOHI;
2973 } else if (HasUMUL_LOHI) {
2974 OpToUse = ISD::UMUL_LOHI;
2977 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
2981 if (Node->getOpcode() == ISD::MULHS &&
2982 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
2983 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2986 if (Node->getOpcode() == ISD::MULHU &&
2987 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
2988 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2991 if (Node->getOpcode() == ISD::SDIV &&
2992 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
2993 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2996 if (Node->getOpcode() == ISD::UDIV &&
2997 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
2998 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3002 // Check to see if we have a libcall for this operator.
3003 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3004 bool isSigned = false;
3005 switch (Node->getOpcode()) {
3008 if (VT == MVT::i32) {
3009 LC = Node->getOpcode() == ISD::UDIV
3010 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3011 isSigned = Node->getOpcode() == ISD::SDIV;
3015 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3016 RTLIB::POW_PPCF128);
3020 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3022 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3026 assert(MVT::isVector(Node->getValueType(0)) &&
3027 "Cannot expand this binary operator!");
3028 // Expand the operation into a bunch of nasty scalar code.
3029 Result = LegalizeOp(UnrollVectorOp(Op));
3032 case TargetLowering::Promote: {
3033 switch (Node->getOpcode()) {
3034 default: assert(0 && "Do not know how to promote this BinOp!");
3038 MVT::ValueType OVT = Node->getValueType(0);
3039 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3040 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
3041 // Bit convert each of the values to the new type.
3042 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3043 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3044 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3045 // Bit convert the result back the original type.
3046 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3054 case ISD::SMUL_LOHI:
3055 case ISD::UMUL_LOHI:
3058 // These nodes will only be produced by target-specific lowering, so
3059 // they shouldn't be here if they aren't legal.
3060 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3061 "This must be legal!");
3063 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3064 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3065 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3068 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3069 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3070 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3071 case Expand: assert(0 && "Not possible");
3073 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3076 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3080 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3082 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3083 default: assert(0 && "Operation not supported");
3084 case TargetLowering::Custom:
3085 Tmp1 = TLI.LowerOperation(Result, DAG);
3086 if (Tmp1.Val) Result = Tmp1;
3088 case TargetLowering::Legal: break;
3089 case TargetLowering::Expand: {
3090 // If this target supports fabs/fneg natively and select is cheap,
3091 // do this efficiently.
3092 if (!TLI.isSelectExpensive() &&
3093 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3094 TargetLowering::Legal &&
3095 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3096 TargetLowering::Legal) {
3097 // Get the sign bit of the RHS.
3098 MVT::ValueType IVT =
3099 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3100 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3101 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
3102 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3103 // Get the absolute value of the result.
3104 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3105 // Select between the nabs and abs value based on the sign bit of
3107 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3108 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3111 Result = LegalizeOp(Result);
3115 // Otherwise, do bitwise ops!
3116 MVT::ValueType NVT =
3117 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3118 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3119 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3120 Result = LegalizeOp(Result);
3128 Tmp1 = LegalizeOp(Node->getOperand(0));
3129 Tmp2 = LegalizeOp(Node->getOperand(1));
3130 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3131 // Since this produces two values, make sure to remember that we legalized
3133 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3134 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3139 Tmp1 = LegalizeOp(Node->getOperand(0));
3140 Tmp2 = LegalizeOp(Node->getOperand(1));
3141 Tmp3 = LegalizeOp(Node->getOperand(2));
3142 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3143 // Since this produces two values, make sure to remember that we legalized
3145 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3146 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3149 case ISD::BUILD_PAIR: {
3150 MVT::ValueType PairTy = Node->getValueType(0);
3151 // TODO: handle the case where the Lo and Hi operands are not of legal type
3152 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3153 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3154 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3155 case TargetLowering::Promote:
3156 case TargetLowering::Custom:
3157 assert(0 && "Cannot promote/custom this yet!");
3158 case TargetLowering::Legal:
3159 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3160 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3162 case TargetLowering::Expand:
3163 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3164 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3165 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3166 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
3167 TLI.getShiftAmountTy()));
3168 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3177 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3178 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3180 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3181 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3182 case TargetLowering::Custom:
3185 case TargetLowering::Legal:
3186 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3188 Tmp1 = TLI.LowerOperation(Result, DAG);
3189 if (Tmp1.Val) Result = Tmp1;
3192 case TargetLowering::Expand: {
3193 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3194 bool isSigned = DivOpc == ISD::SDIV;
3195 MVT::ValueType VT = Node->getValueType(0);
3197 // See if remainder can be lowered using two-result operations.
3198 SDVTList VTs = DAG.getVTList(VT, VT);
3199 if (Node->getOpcode() == ISD::SREM &&
3200 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3201 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3204 if (Node->getOpcode() == ISD::UREM &&
3205 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3206 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3210 if (MVT::isInteger(VT)) {
3211 if (TLI.getOperationAction(DivOpc, VT) ==
3212 TargetLowering::Legal) {
3214 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3215 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3216 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3217 } else if (MVT::isVector(VT)) {
3218 Result = LegalizeOp(UnrollVectorOp(Op));
3220 assert(VT == MVT::i32 &&
3221 "Cannot expand this binary operator!");
3222 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3223 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3225 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3228 assert(MVT::isFloatingPoint(VT) &&
3229 "remainder op must have integer or floating-point type");
3230 if (MVT::isVector(VT)) {
3231 Result = LegalizeOp(UnrollVectorOp(Op));
3233 // Floating point mod -> fmod libcall.
3234 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3235 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3237 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3238 false/*sign irrelevant*/, Dummy);
3246 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3247 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3249 MVT::ValueType VT = Node->getValueType(0);
3250 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3251 default: assert(0 && "This action is not supported yet!");
3252 case TargetLowering::Custom:
3255 case TargetLowering::Legal:
3256 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3257 Result = Result.getValue(0);
3258 Tmp1 = Result.getValue(1);
3261 Tmp2 = TLI.LowerOperation(Result, DAG);
3263 Result = LegalizeOp(Tmp2);
3264 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3268 case TargetLowering::Expand: {
3269 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3270 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3271 // Increment the pointer, VAList, to the next vaarg
3272 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3273 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3274 TLI.getPointerTy()));
3275 // Store the incremented VAList to the legalized pointer
3276 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3277 // Load the actual argument out of the pointer VAList
3278 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3279 Tmp1 = LegalizeOp(Result.getValue(1));
3280 Result = LegalizeOp(Result);
3284 // Since VAARG produces two values, make sure to remember that we
3285 // legalized both of them.
3286 AddLegalizedOperand(SDOperand(Node, 0), Result);
3287 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3288 return Op.ResNo ? Tmp1 : Result;
3292 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3293 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3294 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3296 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3297 default: assert(0 && "This action is not supported yet!");
3298 case TargetLowering::Custom:
3301 case TargetLowering::Legal:
3302 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3303 Node->getOperand(3), Node->getOperand(4));
3305 Tmp1 = TLI.LowerOperation(Result, DAG);
3306 if (Tmp1.Val) Result = Tmp1;
3309 case TargetLowering::Expand:
3310 // This defaults to loading a pointer from the input and storing it to the
3311 // output, returning the chain.
3312 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3313 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3314 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VD, 0);
3315 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VS, 0);
3321 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3322 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3324 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3325 default: assert(0 && "This action is not supported yet!");
3326 case TargetLowering::Custom:
3329 case TargetLowering::Legal:
3330 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3332 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3333 if (Tmp1.Val) Result = Tmp1;
3336 case TargetLowering::Expand:
3337 Result = Tmp1; // Default to a no-op, return the chain
3343 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3344 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3346 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3348 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3349 default: assert(0 && "This action is not supported yet!");
3350 case TargetLowering::Legal: break;
3351 case TargetLowering::Custom:
3352 Tmp1 = TLI.LowerOperation(Result, DAG);
3353 if (Tmp1.Val) Result = Tmp1;
3360 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3361 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3362 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3363 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3365 assert(0 && "ROTL/ROTR legalize operation not supported");
3367 case TargetLowering::Legal:
3369 case TargetLowering::Custom:
3370 Tmp1 = TLI.LowerOperation(Result, DAG);
3371 if (Tmp1.Val) Result = Tmp1;
3373 case TargetLowering::Promote:
3374 assert(0 && "Do not know how to promote ROTL/ROTR");
3376 case TargetLowering::Expand:
3377 assert(0 && "Do not know how to expand ROTL/ROTR");
3383 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3384 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3385 case TargetLowering::Custom:
3386 assert(0 && "Cannot custom legalize this yet!");
3387 case TargetLowering::Legal:
3388 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3390 case TargetLowering::Promote: {
3391 MVT::ValueType OVT = Tmp1.getValueType();
3392 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3393 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
3395 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3396 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3397 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3398 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3401 case TargetLowering::Expand:
3402 Result = ExpandBSWAP(Tmp1);
3410 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3411 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3412 case TargetLowering::Custom:
3413 case TargetLowering::Legal:
3414 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3415 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3416 TargetLowering::Custom) {
3417 Tmp1 = TLI.LowerOperation(Result, DAG);
3423 case TargetLowering::Promote: {
3424 MVT::ValueType OVT = Tmp1.getValueType();
3425 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3427 // Zero extend the argument.
3428 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3429 // Perform the larger operation, then subtract if needed.
3430 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3431 switch (Node->getOpcode()) {
3436 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3437 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3438 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3440 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3441 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
3444 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3445 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3446 DAG.getConstant(MVT::getSizeInBits(NVT) -
3447 MVT::getSizeInBits(OVT), NVT));
3452 case TargetLowering::Expand:
3453 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3464 Tmp1 = LegalizeOp(Node->getOperand(0));
3465 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3466 case TargetLowering::Promote:
3467 case TargetLowering::Custom:
3470 case TargetLowering::Legal:
3471 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3473 Tmp1 = TLI.LowerOperation(Result, DAG);
3474 if (Tmp1.Val) Result = Tmp1;
3477 case TargetLowering::Expand:
3478 switch (Node->getOpcode()) {
3479 default: assert(0 && "Unreachable!");
3481 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3482 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3483 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3486 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3487 MVT::ValueType VT = Node->getValueType(0);
3488 Tmp2 = DAG.getConstantFP(0.0, VT);
3489 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
3490 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3491 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3497 MVT::ValueType VT = Node->getValueType(0);
3499 // Expand unsupported unary vector operators by unrolling them.
3500 if (MVT::isVector(VT)) {
3501 Result = LegalizeOp(UnrollVectorOp(Op));
3505 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3506 switch(Node->getOpcode()) {
3508 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3509 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3512 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3513 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3516 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3517 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3519 default: assert(0 && "Unreachable!");
3522 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3523 false/*sign irrelevant*/, Dummy);
3531 MVT::ValueType VT = Node->getValueType(0);
3533 // Expand unsupported unary vector operators by unrolling them.
3534 if (MVT::isVector(VT)) {
3535 Result = LegalizeOp(UnrollVectorOp(Op));
3539 // We always lower FPOWI into a libcall. No target support for it yet.
3540 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3541 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3543 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3544 false/*sign irrelevant*/, Dummy);
3547 case ISD::BIT_CONVERT:
3548 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3549 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3550 Node->getValueType(0));
3551 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3552 // The input has to be a vector type, we have to either scalarize it, pack
3553 // it, or convert it based on whether the input vector type is legal.
3554 SDNode *InVal = Node->getOperand(0).Val;
3555 int InIx = Node->getOperand(0).ResNo;
3556 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
3557 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
3559 // Figure out if there is a simple type corresponding to this Vector
3560 // type. If so, convert to the vector type.
3561 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3562 if (TLI.isTypeLegal(TVT)) {
3563 // Turn this into a bit convert of the vector input.
3564 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3565 LegalizeOp(Node->getOperand(0)));
3567 } else if (NumElems == 1) {
3568 // Turn this into a bit convert of the scalar input.
3569 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3570 ScalarizeVectorOp(Node->getOperand(0)));
3573 // FIXME: UNIMP! Store then reload
3574 assert(0 && "Cast from unsupported vector type not implemented yet!");
3577 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3578 Node->getOperand(0).getValueType())) {
3579 default: assert(0 && "Unknown operation action!");
3580 case TargetLowering::Expand:
3581 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3582 Node->getValueType(0));
3584 case TargetLowering::Legal:
3585 Tmp1 = LegalizeOp(Node->getOperand(0));
3586 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3592 // Conversion operators. The source and destination have different types.
3593 case ISD::SINT_TO_FP:
3594 case ISD::UINT_TO_FP: {
3595 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3596 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3598 switch (TLI.getOperationAction(Node->getOpcode(),
3599 Node->getOperand(0).getValueType())) {
3600 default: assert(0 && "Unknown operation action!");
3601 case TargetLowering::Custom:
3604 case TargetLowering::Legal:
3605 Tmp1 = LegalizeOp(Node->getOperand(0));
3606 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3608 Tmp1 = TLI.LowerOperation(Result, DAG);
3609 if (Tmp1.Val) Result = Tmp1;
3612 case TargetLowering::Expand:
3613 Result = ExpandLegalINT_TO_FP(isSigned,
3614 LegalizeOp(Node->getOperand(0)),
3615 Node->getValueType(0));
3617 case TargetLowering::Promote:
3618 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3619 Node->getValueType(0),
3625 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3626 Node->getValueType(0), Node->getOperand(0));
3629 Tmp1 = PromoteOp(Node->getOperand(0));
3631 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3632 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3634 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3635 Node->getOperand(0).getValueType());
3637 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3638 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3644 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3646 Tmp1 = LegalizeOp(Node->getOperand(0));
3647 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3650 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3652 // Since the result is legal, we should just be able to truncate the low
3653 // part of the source.
3654 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3657 Result = PromoteOp(Node->getOperand(0));
3658 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3663 case ISD::FP_TO_SINT:
3664 case ISD::FP_TO_UINT:
3665 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3667 Tmp1 = LegalizeOp(Node->getOperand(0));
3669 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3670 default: assert(0 && "Unknown operation action!");
3671 case TargetLowering::Custom:
3674 case TargetLowering::Legal:
3675 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3677 Tmp1 = TLI.LowerOperation(Result, DAG);
3678 if (Tmp1.Val) Result = Tmp1;
3681 case TargetLowering::Promote:
3682 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3683 Node->getOpcode() == ISD::FP_TO_SINT);
3685 case TargetLowering::Expand:
3686 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3687 SDOperand True, False;
3688 MVT::ValueType VT = Node->getOperand(0).getValueType();
3689 MVT::ValueType NVT = Node->getValueType(0);
3690 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1;
3691 const uint64_t zero[] = {0, 0};
3692 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3693 uint64_t x = 1ULL << ShiftAmt;
3694 (void)apf.convertFromZeroExtendedInteger
3695 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven);
3696 Tmp2 = DAG.getConstantFP(apf, VT);
3697 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3698 Node->getOperand(0), Tmp2, ISD::SETLT);
3699 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3700 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3701 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3703 False = DAG.getNode(ISD::XOR, NVT, False,
3704 DAG.getConstant(1ULL << ShiftAmt, NVT));
3705 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3708 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3714 MVT::ValueType VT = Op.getValueType();
3715 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3716 // Convert ppcf128 to i32
3717 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3718 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3719 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3720 Node->getOperand(0), DAG.getValueType(MVT::f64));
3721 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3722 DAG.getIntPtrConstant(1));
3723 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3725 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3726 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3727 Tmp2 = DAG.getConstantFP(apf, OVT);
3728 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3729 // FIXME: generated code sucks.
3730 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3731 DAG.getNode(ISD::ADD, MVT::i32,
3732 DAG.getNode(ISD::FP_TO_SINT, VT,
3733 DAG.getNode(ISD::FSUB, OVT,
3734 Node->getOperand(0), Tmp2)),
3735 DAG.getConstant(0x80000000, MVT::i32)),
3736 DAG.getNode(ISD::FP_TO_SINT, VT,
3737 Node->getOperand(0)),
3738 DAG.getCondCode(ISD::SETGE));
3742 // Convert f32 / f64 to i32 / i64.
3743 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3744 switch (Node->getOpcode()) {
3745 case ISD::FP_TO_SINT: {
3746 if (OVT == MVT::f32)
3747 LC = (VT == MVT::i32)
3748 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3749 else if (OVT == MVT::f64)
3750 LC = (VT == MVT::i32)
3751 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3752 else if (OVT == MVT::f80) {
3753 assert(VT == MVT::i64);
3754 LC = RTLIB::FPTOSINT_F80_I64;
3756 else if (OVT == MVT::ppcf128) {
3757 assert(VT == MVT::i64);
3758 LC = RTLIB::FPTOSINT_PPCF128_I64;
3762 case ISD::FP_TO_UINT: {
3763 if (OVT == MVT::f32)
3764 LC = (VT == MVT::i32)
3765 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3766 else if (OVT == MVT::f64)
3767 LC = (VT == MVT::i32)
3768 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3769 else if (OVT == MVT::f80) {
3770 LC = (VT == MVT::i32)
3771 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64;
3773 else if (OVT == MVT::ppcf128) {
3774 assert(VT == MVT::i64);
3775 LC = RTLIB::FPTOUINT_PPCF128_I64;
3779 default: assert(0 && "Unreachable!");
3782 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3783 false/*sign irrelevant*/, Dummy);
3787 Tmp1 = PromoteOp(Node->getOperand(0));
3788 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3789 Result = LegalizeOp(Result);
3794 case ISD::FP_EXTEND: {
3795 MVT::ValueType DstVT = Op.getValueType();
3796 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3797 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3798 // The only other way we can lower this is to turn it into a STORE,
3799 // LOAD pair, targetting a temporary location (a stack slot).
3800 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3803 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3804 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3806 Tmp1 = LegalizeOp(Node->getOperand(0));
3807 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3810 Tmp1 = PromoteOp(Node->getOperand(0));
3811 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3816 case ISD::FP_ROUND: {
3817 MVT::ValueType DstVT = Op.getValueType();
3818 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3819 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3820 if (SrcVT == MVT::ppcf128) {
3822 ExpandOp(Node->getOperand(0), Lo, Result);
3823 // Round it the rest of the way (e.g. to f32) if needed.
3824 if (DstVT!=MVT::f64)
3825 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3828 // The only other way we can lower this is to turn it into a STORE,
3829 // LOAD pair, targetting a temporary location (a stack slot).
3830 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3833 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3834 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3836 Tmp1 = LegalizeOp(Node->getOperand(0));
3837 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3840 Tmp1 = PromoteOp(Node->getOperand(0));
3841 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3842 Node->getOperand(1));
3847 case ISD::ANY_EXTEND:
3848 case ISD::ZERO_EXTEND:
3849 case ISD::SIGN_EXTEND:
3850 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3851 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3853 Tmp1 = LegalizeOp(Node->getOperand(0));
3854 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3857 switch (Node->getOpcode()) {
3858 case ISD::ANY_EXTEND:
3859 Tmp1 = PromoteOp(Node->getOperand(0));
3860 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3862 case ISD::ZERO_EXTEND:
3863 Result = PromoteOp(Node->getOperand(0));
3864 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3865 Result = DAG.getZeroExtendInReg(Result,
3866 Node->getOperand(0).getValueType());
3868 case ISD::SIGN_EXTEND:
3869 Result = PromoteOp(Node->getOperand(0));
3870 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3871 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3873 DAG.getValueType(Node->getOperand(0).getValueType()));
3878 case ISD::FP_ROUND_INREG:
3879 case ISD::SIGN_EXTEND_INREG: {
3880 Tmp1 = LegalizeOp(Node->getOperand(0));
3881 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3883 // If this operation is not supported, convert it to a shl/shr or load/store
3885 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3886 default: assert(0 && "This action not supported for this op yet!");
3887 case TargetLowering::Legal:
3888 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3890 case TargetLowering::Expand:
3891 // If this is an integer extend and shifts are supported, do that.
3892 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3893 // NOTE: we could fall back on load/store here too for targets without
3894 // SAR. However, it is doubtful that any exist.
3895 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3896 MVT::getSizeInBits(ExtraVT);
3897 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3898 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3899 Node->getOperand(0), ShiftCst);
3900 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3902 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3903 // The only way we can lower this is to turn it into a TRUNCSTORE,
3904 // EXTLOAD pair, targetting a temporary location (a stack slot).
3906 // NOTE: there is a choice here between constantly creating new stack
3907 // slots and always reusing the same one. We currently always create
3908 // new ones, as reuse may inhibit scheduling.
3909 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3910 Node->getValueType(0));
3912 assert(0 && "Unknown op");
3918 case ISD::TRAMPOLINE: {
3920 for (unsigned i = 0; i != 6; ++i)
3921 Ops[i] = LegalizeOp(Node->getOperand(i));
3922 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3923 // The only option for this node is to custom lower it.
3924 Result = TLI.LowerOperation(Result, DAG);
3925 assert(Result.Val && "Should always custom lower!");
3927 // Since trampoline produces two values, make sure to remember that we
3928 // legalized both of them.
3929 Tmp1 = LegalizeOp(Result.getValue(1));
3930 Result = LegalizeOp(Result);
3931 AddLegalizedOperand(SDOperand(Node, 0), Result);
3932 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3933 return Op.ResNo ? Tmp1 : Result;
3935 case ISD::FLT_ROUNDS_: {
3936 MVT::ValueType VT = Node->getValueType(0);
3937 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3938 default: assert(0 && "This action not supported for this op yet!");
3939 case TargetLowering::Custom:
3940 Result = TLI.LowerOperation(Op, DAG);
3941 if (Result.Val) break;
3943 case TargetLowering::Legal:
3944 // If this operation is not supported, lower it to constant 1
3945 Result = DAG.getConstant(1, VT);
3950 MVT::ValueType VT = Node->getValueType(0);
3951 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3952 default: assert(0 && "This action not supported for this op yet!");
3953 case TargetLowering::Legal:
3954 Tmp1 = LegalizeOp(Node->getOperand(0));
3955 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3957 case TargetLowering::Custom:
3958 Result = TLI.LowerOperation(Op, DAG);
3959 if (Result.Val) break;
3961 case TargetLowering::Expand:
3962 // If this operation is not supported, lower it to 'abort()' call
3963 Tmp1 = LegalizeOp(Node->getOperand(0));
3964 TargetLowering::ArgListTy Args;
3965 std::pair<SDOperand,SDOperand> CallResult =
3966 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
3967 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3969 Result = CallResult.second;
3976 assert(Result.getValueType() == Op.getValueType() &&
3977 "Bad legalization!");
3979 // Make sure that the generated code is itself legal.
3981 Result = LegalizeOp(Result);
3983 // Note that LegalizeOp may be reentered even from single-use nodes, which
3984 // means that we always must cache transformed nodes.
3985 AddLegalizedOperand(Op, Result);
3989 /// PromoteOp - Given an operation that produces a value in an invalid type,
3990 /// promote it to compute the value into a larger type. The produced value will
3991 /// have the correct bits for the low portion of the register, but no guarantee
3992 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3993 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3994 MVT::ValueType VT = Op.getValueType();
3995 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3996 assert(getTypeAction(VT) == Promote &&
3997 "Caller should expand or legalize operands that are not promotable!");
3998 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3999 "Cannot promote to smaller type!");
4001 SDOperand Tmp1, Tmp2, Tmp3;
4003 SDNode *Node = Op.Val;
4005 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
4006 if (I != PromotedNodes.end()) return I->second;
4008 switch (Node->getOpcode()) {
4009 case ISD::CopyFromReg:
4010 assert(0 && "CopyFromReg must be legal!");
4013 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4015 assert(0 && "Do not know how to promote this operator!");
4018 Result = DAG.getNode(ISD::UNDEF, NVT);
4022 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4024 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4025 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4027 case ISD::ConstantFP:
4028 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4029 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4033 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
4034 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
4035 Node->getOperand(1), Node->getOperand(2));
4039 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4041 Result = LegalizeOp(Node->getOperand(0));
4042 assert(Result.getValueType() >= NVT &&
4043 "This truncation doesn't make sense!");
4044 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
4045 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4048 // The truncation is not required, because we don't guarantee anything
4049 // about high bits anyway.
4050 Result = PromoteOp(Node->getOperand(0));
4053 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4054 // Truncate the low part of the expanded value to the result type
4055 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4058 case ISD::SIGN_EXTEND:
4059 case ISD::ZERO_EXTEND:
4060 case ISD::ANY_EXTEND:
4061 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4062 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4064 // Input is legal? Just do extend all the way to the larger type.
4065 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4068 // Promote the reg if it's smaller.
4069 Result = PromoteOp(Node->getOperand(0));
4070 // The high bits are not guaranteed to be anything. Insert an extend.
4071 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4072 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4073 DAG.getValueType(Node->getOperand(0).getValueType()));
4074 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4075 Result = DAG.getZeroExtendInReg(Result,
4076 Node->getOperand(0).getValueType());
4080 case ISD::BIT_CONVERT:
4081 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4082 Node->getValueType(0));
4083 Result = PromoteOp(Result);
4086 case ISD::FP_EXTEND:
4087 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4089 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4090 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4091 case Promote: assert(0 && "Unreachable with 2 FP types!");
4093 if (Node->getConstantOperandVal(1) == 0) {
4094 // Input is legal? Do an FP_ROUND_INREG.
4095 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4096 DAG.getValueType(VT));
4098 // Just remove the truncate, it isn't affecting the value.
4099 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4100 Node->getOperand(1));
4105 case ISD::SINT_TO_FP:
4106 case ISD::UINT_TO_FP:
4107 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4109 // No extra round required here.
4110 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4114 Result = PromoteOp(Node->getOperand(0));
4115 if (Node->getOpcode() == ISD::SINT_TO_FP)
4116 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4118 DAG.getValueType(Node->getOperand(0).getValueType()));
4120 Result = DAG.getZeroExtendInReg(Result,
4121 Node->getOperand(0).getValueType());
4122 // No extra round required here.
4123 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4126 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4127 Node->getOperand(0));
4128 // Round if we cannot tolerate excess precision.
4129 if (NoExcessFPPrecision)
4130 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4131 DAG.getValueType(VT));
4136 case ISD::SIGN_EXTEND_INREG:
4137 Result = PromoteOp(Node->getOperand(0));
4138 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4139 Node->getOperand(1));
4141 case ISD::FP_TO_SINT:
4142 case ISD::FP_TO_UINT:
4143 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4146 Tmp1 = Node->getOperand(0);
4149 // The input result is prerounded, so we don't have to do anything
4151 Tmp1 = PromoteOp(Node->getOperand(0));
4154 // If we're promoting a UINT to a larger size, check to see if the new node
4155 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4156 // we can use that instead. This allows us to generate better code for
4157 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4158 // legal, such as PowerPC.
4159 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4160 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4161 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4162 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4163 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4165 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4171 Tmp1 = PromoteOp(Node->getOperand(0));
4172 assert(Tmp1.getValueType() == NVT);
4173 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4174 // NOTE: we do not have to do any extra rounding here for
4175 // NoExcessFPPrecision, because we know the input will have the appropriate
4176 // precision, and these operations don't modify precision at all.
4182 Tmp1 = PromoteOp(Node->getOperand(0));
4183 assert(Tmp1.getValueType() == NVT);
4184 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4185 if (NoExcessFPPrecision)
4186 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4187 DAG.getValueType(VT));
4191 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4192 // directly as well, which may be better.
4193 Tmp1 = PromoteOp(Node->getOperand(0));
4194 assert(Tmp1.getValueType() == NVT);
4195 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4196 if (NoExcessFPPrecision)
4197 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4198 DAG.getValueType(VT));
4208 // The input may have strange things in the top bits of the registers, but
4209 // these operations don't care. They may have weird bits going out, but
4210 // that too is okay if they are integer operations.
4211 Tmp1 = PromoteOp(Node->getOperand(0));
4212 Tmp2 = PromoteOp(Node->getOperand(1));
4213 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4214 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4219 Tmp1 = PromoteOp(Node->getOperand(0));
4220 Tmp2 = PromoteOp(Node->getOperand(1));
4221 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4222 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4224 // Floating point operations will give excess precision that we may not be
4225 // able to tolerate. If we DO allow excess precision, just leave it,
4226 // otherwise excise it.
4227 // FIXME: Why would we need to round FP ops more than integer ones?
4228 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4229 if (NoExcessFPPrecision)
4230 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4231 DAG.getValueType(VT));
4236 // These operators require that their input be sign extended.
4237 Tmp1 = PromoteOp(Node->getOperand(0));
4238 Tmp2 = PromoteOp(Node->getOperand(1));
4239 if (MVT::isInteger(NVT)) {
4240 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4241 DAG.getValueType(VT));
4242 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4243 DAG.getValueType(VT));
4245 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4247 // Perform FP_ROUND: this is probably overly pessimistic.
4248 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
4249 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4250 DAG.getValueType(VT));
4254 case ISD::FCOPYSIGN:
4255 // These operators require that their input be fp extended.
4256 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4257 case Expand: assert(0 && "not implemented");
4258 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4259 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4261 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4262 case Expand: assert(0 && "not implemented");
4263 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4264 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4266 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4268 // Perform FP_ROUND: this is probably overly pessimistic.
4269 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4270 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4271 DAG.getValueType(VT));
4276 // These operators require that their input be zero extended.
4277 Tmp1 = PromoteOp(Node->getOperand(0));
4278 Tmp2 = PromoteOp(Node->getOperand(1));
4279 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
4280 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4281 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4282 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4286 Tmp1 = PromoteOp(Node->getOperand(0));
4287 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4290 // The input value must be properly sign extended.
4291 Tmp1 = PromoteOp(Node->getOperand(0));
4292 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4293 DAG.getValueType(VT));
4294 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4297 // The input value must be properly zero extended.
4298 Tmp1 = PromoteOp(Node->getOperand(0));
4299 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4300 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4304 Tmp1 = Node->getOperand(0); // Get the chain.
4305 Tmp2 = Node->getOperand(1); // Get the pointer.
4306 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4307 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4308 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
4310 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4311 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4312 // Increment the pointer, VAList, to the next vaarg
4313 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4314 DAG.getConstant(MVT::getSizeInBits(VT)/8,
4315 TLI.getPointerTy()));
4316 // Store the incremented VAList to the legalized pointer
4317 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4318 // Load the actual argument out of the pointer VAList
4319 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4321 // Remember that we legalized the chain.
4322 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4326 LoadSDNode *LD = cast<LoadSDNode>(Node);
4327 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4328 ? ISD::EXTLOAD : LD->getExtensionType();
4329 Result = DAG.getExtLoad(ExtType, NVT,
4330 LD->getChain(), LD->getBasePtr(),
4331 LD->getSrcValue(), LD->getSrcValueOffset(),
4334 LD->getAlignment());
4335 // Remember that we legalized the chain.
4336 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4340 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4341 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4342 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
4344 case ISD::SELECT_CC:
4345 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4346 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4347 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4348 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4351 Tmp1 = Node->getOperand(0);
4352 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4353 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4354 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4355 DAG.getConstant(MVT::getSizeInBits(NVT) -
4356 MVT::getSizeInBits(VT),
4357 TLI.getShiftAmountTy()));
4362 // Zero extend the argument
4363 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4364 // Perform the larger operation, then subtract if needed.
4365 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4366 switch(Node->getOpcode()) {
4371 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4372 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
4373 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
4375 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4376 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
4379 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4380 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4381 DAG.getConstant(MVT::getSizeInBits(NVT) -
4382 MVT::getSizeInBits(VT), NVT));
4386 case ISD::EXTRACT_SUBVECTOR:
4387 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4389 case ISD::EXTRACT_VECTOR_ELT:
4390 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4394 assert(Result.Val && "Didn't set a result!");
4396 // Make sure the result is itself legal.
4397 Result = LegalizeOp(Result);
4399 // Remember that we promoted this!
4400 AddPromotedOperand(Op, Result);
4404 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4405 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4406 /// based on the vector type. The return type of this matches the element type
4407 /// of the vector, which may not be legal for the target.
4408 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4409 // We know that operand #0 is the Vec vector. If the index is a constant
4410 // or if the invec is a supported hardware type, we can use it. Otherwise,
4411 // lower to a store then an indexed load.
4412 SDOperand Vec = Op.getOperand(0);
4413 SDOperand Idx = Op.getOperand(1);
4415 MVT::ValueType TVT = Vec.getValueType();
4416 unsigned NumElems = MVT::getVectorNumElements(TVT);
4418 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4419 default: assert(0 && "This action is not supported yet!");
4420 case TargetLowering::Custom: {
4421 Vec = LegalizeOp(Vec);
4422 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4423 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4428 case TargetLowering::Legal:
4429 if (isTypeLegal(TVT)) {
4430 Vec = LegalizeOp(Vec);
4431 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4435 case TargetLowering::Expand:
4439 if (NumElems == 1) {
4440 // This must be an access of the only element. Return it.
4441 Op = ScalarizeVectorOp(Vec);
4442 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4443 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4444 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4446 SplitVectorOp(Vec, Lo, Hi);
4447 if (CIdx->getValue() < NumLoElts) {
4451 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4452 Idx.getValueType());
4455 // It's now an extract from the appropriate high or low part. Recurse.
4456 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4457 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4459 // Store the value to a temporary stack slot, then LOAD the scalar
4460 // element back out.
4461 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4462 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4464 // Add the offset to the index.
4465 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
4466 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4467 DAG.getConstant(EltSize, Idx.getValueType()));
4469 if (MVT::getSizeInBits(Idx.getValueType()) >
4470 MVT::getSizeInBits(TLI.getPointerTy()))
4471 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4473 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4475 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4477 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4482 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4483 /// we assume the operation can be split if it is not already legal.
4484 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4485 // We know that operand #0 is the Vec vector. For now we assume the index
4486 // is a constant and that the extracted result is a supported hardware type.
4487 SDOperand Vec = Op.getOperand(0);
4488 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4490 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
4492 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
4493 // This must be an access of the desired vector length. Return it.
4497 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4499 SplitVectorOp(Vec, Lo, Hi);
4500 if (CIdx->getValue() < NumElems/2) {
4504 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4507 // It's now an extract from the appropriate high or low part. Recurse.
4508 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4509 return ExpandEXTRACT_SUBVECTOR(Op);
4512 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4513 /// with condition CC on the current target. This usually involves legalizing
4514 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4515 /// there may be no choice but to create a new SetCC node to represent the
4516 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4517 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4518 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4521 SDOperand Tmp1, Tmp2, Tmp3, Result;
4523 switch (getTypeAction(LHS.getValueType())) {
4525 Tmp1 = LegalizeOp(LHS); // LHS
4526 Tmp2 = LegalizeOp(RHS); // RHS
4529 Tmp1 = PromoteOp(LHS); // LHS
4530 Tmp2 = PromoteOp(RHS); // RHS
4532 // If this is an FP compare, the operands have already been extended.
4533 if (MVT::isInteger(LHS.getValueType())) {
4534 MVT::ValueType VT = LHS.getValueType();
4535 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4537 // Otherwise, we have to insert explicit sign or zero extends. Note
4538 // that we could insert sign extends for ALL conditions, but zero extend
4539 // is cheaper on many machines (an AND instead of two shifts), so prefer
4541 switch (cast<CondCodeSDNode>(CC)->get()) {
4542 default: assert(0 && "Unknown integer comparison!");
4549 // ALL of these operations will work if we either sign or zero extend
4550 // the operands (including the unsigned comparisons!). Zero extend is
4551 // usually a simpler/cheaper operation, so prefer it.
4552 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4553 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4559 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4560 DAG.getValueType(VT));
4561 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4562 DAG.getValueType(VT));
4568 MVT::ValueType VT = LHS.getValueType();
4569 if (VT == MVT::f32 || VT == MVT::f64) {
4570 // Expand into one or more soft-fp libcall(s).
4571 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4572 switch (cast<CondCodeSDNode>(CC)->get()) {
4575 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4579 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4583 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4587 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4591 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4595 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4598 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4601 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4604 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4605 switch (cast<CondCodeSDNode>(CC)->get()) {
4607 // SETONE = SETOLT | SETOGT
4608 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4611 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4614 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4617 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4620 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4623 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4625 default: assert(0 && "Unsupported FP setcc!");
4630 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4631 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4632 false /*sign irrelevant*/, Dummy);
4633 Tmp2 = DAG.getConstant(0, MVT::i32);
4634 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4635 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4636 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4637 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4638 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4639 false /*sign irrelevant*/, Dummy);
4640 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4641 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4642 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4650 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4651 ExpandOp(LHS, LHSLo, LHSHi);
4652 ExpandOp(RHS, RHSLo, RHSHi);
4653 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4655 if (VT==MVT::ppcf128) {
4656 // FIXME: This generated code sucks. We want to generate
4657 // FCMP crN, hi1, hi2
4659 // FCMP crN, lo1, lo2
4660 // The following can be improved, but not that much.
4661 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4662 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
4663 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4664 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
4665 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
4666 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4667 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4676 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4677 if (RHSCST->isAllOnesValue()) {
4678 // Comparison to -1.
4679 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4684 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4685 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4686 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4687 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4690 // If this is a comparison of the sign bit, just look at the top part.
4692 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4693 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4694 CST->getValue() == 0) || // X < 0
4695 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4696 CST->isAllOnesValue())) { // X > -1
4702 // FIXME: This generated code sucks.
4703 ISD::CondCode LowCC;
4705 default: assert(0 && "Unknown integer setcc!");
4707 case ISD::SETULT: LowCC = ISD::SETULT; break;
4709 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4711 case ISD::SETULE: LowCC = ISD::SETULE; break;
4713 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4716 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4717 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4718 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4720 // NOTE: on targets without efficient SELECT of bools, we can always use
4721 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4722 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4723 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4724 false, DagCombineInfo);
4726 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4727 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4728 CCCode, false, DagCombineInfo);
4730 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC);
4732 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4733 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4734 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4735 (Tmp2C && Tmp2C->getValue() == 0 &&
4736 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4737 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4738 (Tmp2C && Tmp2C->getValue() == 1 &&
4739 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4740 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4741 // low part is known false, returns high part.
4742 // For LE / GE, if high part is known false, ignore the low part.
4743 // For LT / GT, if high part is known true, ignore the low part.
4747 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4748 ISD::SETEQ, false, DagCombineInfo);
4750 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4751 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4752 Result, Tmp1, Tmp2));
4763 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4764 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4765 /// a load from the stack slot to DestVT, extending it if needed.
4766 /// The resultant code need not be legal.
4767 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4768 MVT::ValueType SlotVT,
4769 MVT::ValueType DestVT) {
4770 // Create the stack frame object.
4771 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
4773 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4774 int SPFI = StackPtrFI->getIndex();
4776 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType());
4777 unsigned SlotSize = MVT::getSizeInBits(SlotVT);
4778 unsigned DestSize = MVT::getSizeInBits(DestVT);
4780 // Emit a store to the stack slot. Use a truncstore if the input value is
4781 // later than DestVT.
4783 if (SrcSize > SlotSize)
4784 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4785 PseudoSourceValue::getFixedStack(),
4788 assert(SrcSize == SlotSize && "Invalid store");
4789 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4790 PseudoSourceValue::getFixedStack(),
4794 // Result is a load from the stack slot.
4795 if (SlotSize == DestSize)
4796 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4798 assert(SlotSize < DestSize && "Unknown extension!");
4799 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT);
4802 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4803 // Create a vector sized/aligned stack slot, store the value to element #0,
4804 // then load the whole vector back out.
4805 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4807 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4808 int SPFI = StackPtrFI->getIndex();
4810 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4811 PseudoSourceValue::getFixedStack(), SPFI);
4812 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4813 PseudoSourceValue::getFixedStack(), SPFI);
4817 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4818 /// support the operation, but do support the resultant vector type.
4819 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4821 // If the only non-undef value is the low element, turn this into a
4822 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4823 unsigned NumElems = Node->getNumOperands();
4824 bool isOnlyLowElement = true;
4825 SDOperand SplatValue = Node->getOperand(0);
4826 std::map<SDOperand, std::vector<unsigned> > Values;
4827 Values[SplatValue].push_back(0);
4828 bool isConstant = true;
4829 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4830 SplatValue.getOpcode() != ISD::UNDEF)
4833 for (unsigned i = 1; i < NumElems; ++i) {
4834 SDOperand V = Node->getOperand(i);
4835 Values[V].push_back(i);
4836 if (V.getOpcode() != ISD::UNDEF)
4837 isOnlyLowElement = false;
4838 if (SplatValue != V)
4839 SplatValue = SDOperand(0,0);
4841 // If this isn't a constant element or an undef, we can't use a constant
4843 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4844 V.getOpcode() != ISD::UNDEF)
4848 if (isOnlyLowElement) {
4849 // If the low element is an undef too, then this whole things is an undef.
4850 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4851 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4852 // Otherwise, turn this into a scalar_to_vector node.
4853 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4854 Node->getOperand(0));
4857 // If all elements are constants, create a load from the constant pool.
4859 MVT::ValueType VT = Node->getValueType(0);
4861 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4862 std::vector<Constant*> CV;
4863 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4864 if (ConstantFPSDNode *V =
4865 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4866 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4867 } else if (ConstantSDNode *V =
4868 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4869 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4871 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4872 CV.push_back(UndefValue::get(OpNTy));
4875 Constant *CP = ConstantVector::get(CV);
4876 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4877 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4878 PseudoSourceValue::getConstantPool(), 0);
4881 if (SplatValue.Val) { // Splat of one value?
4882 // Build the shuffle constant vector: <0, 0, 0, 0>
4883 MVT::ValueType MaskVT =
4884 MVT::getIntVectorWithNumElements(NumElems);
4885 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4886 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4887 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4888 &ZeroVec[0], ZeroVec.size());
4890 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4891 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4892 // Get the splatted value into the low element of a vector register.
4893 SDOperand LowValVec =
4894 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4896 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4897 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4898 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4903 // If there are only two unique elements, we may be able to turn this into a
4905 if (Values.size() == 2) {
4906 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4907 MVT::ValueType MaskVT =
4908 MVT::getIntVectorWithNumElements(NumElems);
4909 std::vector<SDOperand> MaskVec(NumElems);
4911 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4912 E = Values.end(); I != E; ++I) {
4913 for (std::vector<unsigned>::iterator II = I->second.begin(),
4914 EE = I->second.end(); II != EE; ++II)
4915 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4918 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4919 &MaskVec[0], MaskVec.size());
4921 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4922 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4923 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4924 SmallVector<SDOperand, 8> Ops;
4925 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4926 E = Values.end(); I != E; ++I) {
4927 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4931 Ops.push_back(ShuffleMask);
4933 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4934 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4935 &Ops[0], Ops.size());
4939 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4940 // aligned object on the stack, store each element into it, then load
4941 // the result as a vector.
4942 MVT::ValueType VT = Node->getValueType(0);
4943 // Create the stack frame object.
4944 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
4946 // Emit a store of each element to the stack slot.
4947 SmallVector<SDOperand, 8> Stores;
4948 unsigned TypeByteSize =
4949 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4950 // Store (in the right endianness) the elements to memory.
4951 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4952 // Ignore undef elements.
4953 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4955 unsigned Offset = TypeByteSize*i;
4957 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4958 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4960 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4964 SDOperand StoreChain;
4965 if (!Stores.empty()) // Not all undef elements?
4966 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4967 &Stores[0], Stores.size());
4969 StoreChain = DAG.getEntryNode();
4971 // Result is a load from the stack slot.
4972 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4975 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4976 SDOperand Op, SDOperand Amt,
4977 SDOperand &Lo, SDOperand &Hi) {
4978 // Expand the subcomponents.
4979 SDOperand LHSL, LHSH;
4980 ExpandOp(Op, LHSL, LHSH);
4982 SDOperand Ops[] = { LHSL, LHSH, Amt };
4983 MVT::ValueType VT = LHSL.getValueType();
4984 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4985 Hi = Lo.getValue(1);
4989 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4990 /// smaller elements. If we can't find a way that is more efficient than a
4991 /// libcall on this target, return false. Otherwise, return true with the
4992 /// low-parts expanded into Lo and Hi.
4993 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4994 SDOperand &Lo, SDOperand &Hi) {
4995 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4996 "This is not a shift!");
4998 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4999 SDOperand ShAmt = LegalizeOp(Amt);
5000 MVT::ValueType ShTy = ShAmt.getValueType();
5001 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
5002 unsigned NVTBits = MVT::getSizeInBits(NVT);
5004 // Handle the case when Amt is an immediate.
5005 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
5006 unsigned Cst = CN->getValue();
5007 // Expand the incoming operand to be shifted, so that we have its parts
5009 ExpandOp(Op, InL, InH);
5013 Lo = DAG.getConstant(0, NVT);
5014 Hi = DAG.getConstant(0, NVT);
5015 } else if (Cst > NVTBits) {
5016 Lo = DAG.getConstant(0, NVT);
5017 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5018 } else if (Cst == NVTBits) {
5019 Lo = DAG.getConstant(0, NVT);
5022 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5023 Hi = DAG.getNode(ISD::OR, NVT,
5024 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5025 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5030 Lo = DAG.getConstant(0, NVT);
5031 Hi = DAG.getConstant(0, NVT);
5032 } else if (Cst > NVTBits) {
5033 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5034 Hi = DAG.getConstant(0, NVT);
5035 } else if (Cst == NVTBits) {
5037 Hi = DAG.getConstant(0, NVT);
5039 Lo = DAG.getNode(ISD::OR, NVT,
5040 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5041 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5042 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5047 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5048 DAG.getConstant(NVTBits-1, ShTy));
5049 } else if (Cst > NVTBits) {
5050 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5051 DAG.getConstant(Cst-NVTBits, ShTy));
5052 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5053 DAG.getConstant(NVTBits-1, ShTy));
5054 } else if (Cst == NVTBits) {
5056 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5057 DAG.getConstant(NVTBits-1, ShTy));
5059 Lo = DAG.getNode(ISD::OR, NVT,
5060 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5061 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5062 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5068 // Okay, the shift amount isn't constant. However, if we can tell that it is
5069 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5070 uint64_t Mask = NVTBits, KnownZero, KnownOne;
5071 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5073 // If we know that the high bit of the shift amount is one, then we can do
5074 // this as a couple of simple shifts.
5075 if (KnownOne & Mask) {
5076 // Mask out the high bit, which we know is set.
5077 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5078 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5080 // Expand the incoming operand to be shifted, so that we have its parts
5082 ExpandOp(Op, InL, InH);
5085 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5086 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5089 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5090 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5093 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5094 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5095 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5100 // If we know that the high bit of the shift amount is zero, then we can do
5101 // this as a couple of simple shifts.
5102 if (KnownZero & Mask) {
5104 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5105 DAG.getConstant(NVTBits, Amt.getValueType()),
5108 // Expand the incoming operand to be shifted, so that we have its parts
5110 ExpandOp(Op, InL, InH);
5113 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5114 Hi = DAG.getNode(ISD::OR, NVT,
5115 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5116 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5119 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5120 Lo = DAG.getNode(ISD::OR, NVT,
5121 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5122 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5125 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5126 Lo = DAG.getNode(ISD::OR, NVT,
5127 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5128 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5137 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5138 // does not fit into a register, return the lo part and set the hi part to the
5139 // by-reg argument. If it does fit into a single register, return the result
5140 // and leave the Hi part unset.
5141 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
5142 bool isSigned, SDOperand &Hi) {
5143 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5144 // The input chain to this libcall is the entry node of the function.
5145 // Legalizing the call will automatically add the previous call to the
5147 SDOperand InChain = DAG.getEntryNode();
5149 TargetLowering::ArgListTy Args;
5150 TargetLowering::ArgListEntry Entry;
5151 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5152 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
5153 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
5154 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5155 Entry.isSExt = isSigned;
5156 Args.push_back(Entry);
5158 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
5160 // Splice the libcall in wherever FindInputOutputChains tells us to.
5161 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
5162 std::pair<SDOperand,SDOperand> CallInfo =
5163 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
5166 // Legalize the call sequence, starting with the chain. This will advance
5167 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5168 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5169 LegalizeOp(CallInfo.second);
5171 switch (getTypeAction(CallInfo.first.getValueType())) {
5172 default: assert(0 && "Unknown thing");
5174 Result = CallInfo.first;
5177 ExpandOp(CallInfo.first, Result, Hi);
5184 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5186 SDOperand SelectionDAGLegalize::
5187 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
5188 assert(getTypeAction(Source.getValueType()) == Expand &&
5189 "This is not an expansion!");
5190 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
5193 assert(Source.getValueType() == MVT::i64 &&
5194 "This only works for 64-bit -> FP");
5195 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
5196 // incoming integer is set. To handle this, we dynamically test to see if
5197 // it is set, and, if so, add a fudge factor.
5199 ExpandOp(Source, Lo, Hi);
5201 // If this is unsigned, and not supported, first perform the conversion to
5202 // signed, then adjust the result if the sign bit is set.
5203 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
5204 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
5206 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
5207 DAG.getConstant(0, Hi.getValueType()),
5209 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5210 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5211 SignSet, Four, Zero);
5212 uint64_t FF = 0x5f800000ULL;
5213 if (TLI.isLittleEndian()) FF <<= 32;
5214 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5216 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5217 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5218 SDOperand FudgeInReg;
5219 if (DestTy == MVT::f32)
5220 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5221 PseudoSourceValue::getConstantPool(), 0);
5222 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
5223 // FIXME: Avoid the extend by construction the right constantpool?
5224 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5226 PseudoSourceValue::getConstantPool(), 0,
5229 assert(0 && "Unexpected conversion");
5231 MVT::ValueType SCVT = SignedConv.getValueType();
5232 if (SCVT != DestTy) {
5233 // Destination type needs to be expanded as well. The FADD now we are
5234 // constructing will be expanded into a libcall.
5235 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
5236 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
5237 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
5238 SignedConv, SignedConv.getValue(1));
5240 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5242 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5245 // Check to see if the target has a custom way to lower this. If so, use it.
5246 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
5247 default: assert(0 && "This action not implemented for this operation!");
5248 case TargetLowering::Legal:
5249 case TargetLowering::Expand:
5250 break; // This case is handled below.
5251 case TargetLowering::Custom: {
5252 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5255 return LegalizeOp(NV);
5256 break; // The target decided this was legal after all
5260 // Expand the source, then glue it back together for the call. We must expand
5261 // the source in case it is shared (this pass of legalize must traverse it).
5262 SDOperand SrcLo, SrcHi;
5263 ExpandOp(Source, SrcLo, SrcHi);
5264 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
5267 if (DestTy == MVT::f32)
5268 LC = RTLIB::SINTTOFP_I64_F32;
5270 assert(DestTy == MVT::f64 && "Unknown fp value type!");
5271 LC = RTLIB::SINTTOFP_I64_F64;
5274 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
5275 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5276 SDOperand UnusedHiPart;
5277 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
5281 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5282 /// INT_TO_FP operation of the specified operand when the target requests that
5283 /// we expand it. At this point, we know that the result and operand types are
5284 /// legal for the target.
5285 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5287 MVT::ValueType DestVT) {
5288 if (Op0.getValueType() == MVT::i32) {
5289 // simple 32-bit [signed|unsigned] integer to float/double expansion
5291 // Get the stack frame index of a 8 byte buffer.
5292 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5294 // word offset constant for Hi/Lo address computation
5295 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5296 // set up Hi and Lo (into buffer) address based on endian
5297 SDOperand Hi = StackSlot;
5298 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5299 if (TLI.isLittleEndian())
5302 // if signed map to unsigned space
5303 SDOperand Op0Mapped;
5305 // constant used to invert sign bit (signed to unsigned mapping)
5306 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5307 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5311 // store the lo of the constructed double - based on integer input
5312 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5313 Op0Mapped, Lo, NULL, 0);
5314 // initial hi portion of constructed double
5315 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5316 // store the hi of the constructed double - biased exponent
5317 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5318 // load the constructed double
5319 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5320 // FP constant to bias correct the final result
5321 SDOperand Bias = DAG.getConstantFP(isSigned ?
5322 BitsToDouble(0x4330000080000000ULL)
5323 : BitsToDouble(0x4330000000000000ULL),
5325 // subtract the bias
5326 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5329 // handle final rounding
5330 if (DestVT == MVT::f64) {
5333 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
5334 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5335 DAG.getIntPtrConstant(0));
5336 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
5337 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5341 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5342 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5344 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
5345 DAG.getConstant(0, Op0.getValueType()),
5347 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5348 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5349 SignSet, Four, Zero);
5351 // If the sign bit of the integer is set, the large number will be treated
5352 // as a negative number. To counteract this, the dynamic code adds an
5353 // offset depending on the data type.
5355 switch (Op0.getValueType()) {
5356 default: assert(0 && "Unsupported integer type!");
5357 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5358 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5359 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5360 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5362 if (TLI.isLittleEndian()) FF <<= 32;
5363 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5365 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5366 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5367 SDOperand FudgeInReg;
5368 if (DestVT == MVT::f32)
5369 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5370 PseudoSourceValue::getConstantPool(), 0);
5373 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5374 DAG.getEntryNode(), CPIdx,
5375 PseudoSourceValue::getConstantPool(), 0,
5379 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5382 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5383 /// *INT_TO_FP operation of the specified operand when the target requests that
5384 /// we promote it. At this point, we know that the result and operand types are
5385 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5386 /// operation that takes a larger input.
5387 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5388 MVT::ValueType DestVT,
5390 // First step, figure out the appropriate *INT_TO_FP operation to use.
5391 MVT::ValueType NewInTy = LegalOp.getValueType();
5393 unsigned OpToUse = 0;
5395 // Scan for the appropriate larger type to use.
5397 NewInTy = (MVT::ValueType)(NewInTy+1);
5398 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
5400 // If the target supports SINT_TO_FP of this type, use it.
5401 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5403 case TargetLowering::Legal:
5404 if (!TLI.isTypeLegal(NewInTy))
5405 break; // Can't use this datatype.
5407 case TargetLowering::Custom:
5408 OpToUse = ISD::SINT_TO_FP;
5412 if (isSigned) continue;
5414 // If the target supports UINT_TO_FP of this type, use it.
5415 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5417 case TargetLowering::Legal:
5418 if (!TLI.isTypeLegal(NewInTy))
5419 break; // Can't use this datatype.
5421 case TargetLowering::Custom:
5422 OpToUse = ISD::UINT_TO_FP;
5427 // Otherwise, try a larger type.
5430 // Okay, we found the operation and type to use. Zero extend our input to the
5431 // desired type then run the operation on it.
5432 return DAG.getNode(OpToUse, DestVT,
5433 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5437 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5438 /// FP_TO_*INT operation of the specified operand when the target requests that
5439 /// we promote it. At this point, we know that the result and operand types are
5440 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5441 /// operation that returns a larger result.
5442 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5443 MVT::ValueType DestVT,
5445 // First step, figure out the appropriate FP_TO*INT operation to use.
5446 MVT::ValueType NewOutTy = DestVT;
5448 unsigned OpToUse = 0;
5450 // Scan for the appropriate larger type to use.
5452 NewOutTy = (MVT::ValueType)(NewOutTy+1);
5453 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
5455 // If the target supports FP_TO_SINT returning this type, use it.
5456 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5458 case TargetLowering::Legal:
5459 if (!TLI.isTypeLegal(NewOutTy))
5460 break; // Can't use this datatype.
5462 case TargetLowering::Custom:
5463 OpToUse = ISD::FP_TO_SINT;
5468 // If the target supports FP_TO_UINT of this type, use it.
5469 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5471 case TargetLowering::Legal:
5472 if (!TLI.isTypeLegal(NewOutTy))
5473 break; // Can't use this datatype.
5475 case TargetLowering::Custom:
5476 OpToUse = ISD::FP_TO_UINT;
5481 // Otherwise, try a larger type.
5485 // Okay, we found the operation and type to use.
5486 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5488 // If the operation produces an invalid type, it must be custom lowered. Use
5489 // the target lowering hooks to expand it. Just keep the low part of the
5490 // expanded operation, we know that we're truncating anyway.
5491 if (getTypeAction(NewOutTy) == Expand) {
5492 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
5493 assert(Operation.Val && "Didn't return anything");
5496 // Truncate the result of the extended FP_TO_*INT operation to the desired
5498 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5501 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5503 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5504 MVT::ValueType VT = Op.getValueType();
5505 MVT::ValueType SHVT = TLI.getShiftAmountTy();
5506 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5508 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5510 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5511 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5512 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5514 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5515 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5516 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5517 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5518 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5519 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5520 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5521 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5522 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5524 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5525 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5526 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5527 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5528 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5529 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5530 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5531 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5532 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5533 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5534 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5535 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5536 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5537 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5538 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5539 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5540 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5541 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5542 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5543 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5544 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5548 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5550 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5552 default: assert(0 && "Cannot expand this yet!");
5554 static const uint64_t mask[6] = {
5555 0x5555555555555555ULL, 0x3333333333333333ULL,
5556 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5557 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5559 MVT::ValueType VT = Op.getValueType();
5560 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5561 unsigned len = MVT::getSizeInBits(VT);
5562 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5563 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5564 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5565 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5566 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5567 DAG.getNode(ISD::AND, VT,
5568 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5573 // for now, we do this:
5574 // x = x | (x >> 1);
5575 // x = x | (x >> 2);
5577 // x = x | (x >>16);
5578 // x = x | (x >>32); // for 64-bit input
5579 // return popcount(~x);
5581 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5582 MVT::ValueType VT = Op.getValueType();
5583 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5584 unsigned len = MVT::getSizeInBits(VT);
5585 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5586 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5587 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5589 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5590 return DAG.getNode(ISD::CTPOP, VT, Op);
5593 // for now, we use: { return popcount(~x & (x - 1)); }
5594 // unless the target has ctlz but not ctpop, in which case we use:
5595 // { return 32 - nlz(~x & (x-1)); }
5596 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5597 MVT::ValueType VT = Op.getValueType();
5598 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5599 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5600 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5601 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5602 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5603 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5604 TLI.isOperationLegal(ISD::CTLZ, VT))
5605 return DAG.getNode(ISD::SUB, VT,
5606 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5607 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5608 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5613 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5614 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5615 /// LegalizeNodes map is filled in for any results that are not expanded, the
5616 /// ExpandedNodes map is filled in for any results that are expanded, and the
5617 /// Lo/Hi values are returned.
5618 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5619 MVT::ValueType VT = Op.getValueType();
5620 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5621 SDNode *Node = Op.Val;
5622 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5623 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5624 MVT::isVector(VT)) &&
5625 "Cannot expand to FP value or to larger int value!");
5627 // See if we already expanded it.
5628 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5629 = ExpandedNodes.find(Op);
5630 if (I != ExpandedNodes.end()) {
5631 Lo = I->second.first;
5632 Hi = I->second.second;
5636 switch (Node->getOpcode()) {
5637 case ISD::CopyFromReg:
5638 assert(0 && "CopyFromReg must be legal!");
5639 case ISD::FP_ROUND_INREG:
5640 if (VT == MVT::ppcf128 &&
5641 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5642 TargetLowering::Custom) {
5643 SDOperand SrcLo, SrcHi, Src;
5644 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5645 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5646 SDOperand Result = TLI.LowerOperation(
5647 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5648 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5649 Lo = Result.Val->getOperand(0);
5650 Hi = Result.Val->getOperand(1);
5656 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5658 assert(0 && "Do not know how to expand this operator!");
5660 case ISD::EXTRACT_VECTOR_ELT:
5661 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5662 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5663 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5664 return ExpandOp(Lo, Lo, Hi);
5666 NVT = TLI.getTypeToExpandTo(VT);
5667 Lo = DAG.getNode(ISD::UNDEF, NVT);
5668 Hi = DAG.getNode(ISD::UNDEF, NVT);
5670 case ISD::Constant: {
5671 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
5672 Lo = DAG.getConstant(Cst, NVT);
5673 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
5676 case ISD::ConstantFP: {
5677 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5678 if (CFP->getValueType(0) == MVT::ppcf128) {
5679 APInt api = CFP->getValueAPF().convertToAPInt();
5680 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5682 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5686 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5687 if (getTypeAction(Lo.getValueType()) == Expand)
5688 ExpandOp(Lo, Lo, Hi);
5691 case ISD::BUILD_PAIR:
5692 // Return the operands.
5693 Lo = Node->getOperand(0);
5694 Hi = Node->getOperand(1);
5697 case ISD::MERGE_VALUES:
5698 if (Node->getNumValues() == 1) {
5699 ExpandOp(Op.getOperand(0), Lo, Hi);
5702 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5703 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5704 Op.getValue(1).getValueType() == MVT::Other &&
5705 "unhandled MERGE_VALUES");
5706 ExpandOp(Op.getOperand(0), Lo, Hi);
5707 // Remember that we legalized the chain.
5708 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5711 case ISD::SIGN_EXTEND_INREG:
5712 ExpandOp(Node->getOperand(0), Lo, Hi);
5713 // sext_inreg the low part if needed.
5714 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5716 // The high part gets the sign extension from the lo-part. This handles
5717 // things like sextinreg V:i64 from i8.
5718 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5719 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5720 TLI.getShiftAmountTy()));
5724 ExpandOp(Node->getOperand(0), Lo, Hi);
5725 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5726 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5732 ExpandOp(Node->getOperand(0), Lo, Hi);
5733 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5734 DAG.getNode(ISD::CTPOP, NVT, Lo),
5735 DAG.getNode(ISD::CTPOP, NVT, Hi));
5736 Hi = DAG.getConstant(0, NVT);
5740 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5741 ExpandOp(Node->getOperand(0), Lo, Hi);
5742 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5743 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5744 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5746 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5747 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5749 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5750 Hi = DAG.getConstant(0, NVT);
5755 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5756 ExpandOp(Node->getOperand(0), Lo, Hi);
5757 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5758 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5759 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5761 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5762 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5764 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5765 Hi = DAG.getConstant(0, NVT);
5770 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5771 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5772 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5773 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5775 // Remember that we legalized the chain.
5776 Hi = LegalizeOp(Hi);
5777 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5778 if (TLI.isBigEndian())
5784 LoadSDNode *LD = cast<LoadSDNode>(Node);
5785 SDOperand Ch = LD->getChain(); // Legalize the chain.
5786 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5787 ISD::LoadExtType ExtType = LD->getExtensionType();
5788 int SVOffset = LD->getSrcValueOffset();
5789 unsigned Alignment = LD->getAlignment();
5790 bool isVolatile = LD->isVolatile();
5792 if (ExtType == ISD::NON_EXTLOAD) {
5793 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5794 isVolatile, Alignment);
5795 if (VT == MVT::f32 || VT == MVT::f64) {
5796 // f32->i32 or f64->i64 one to one expansion.
5797 // Remember that we legalized the chain.
5798 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5799 // Recursively expand the new load.
5800 if (getTypeAction(NVT) == Expand)
5801 ExpandOp(Lo, Lo, Hi);
5805 // Increment the pointer to the other half.
5806 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5807 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5808 DAG.getIntPtrConstant(IncrementSize));
5809 SVOffset += IncrementSize;
5810 Alignment = MinAlign(Alignment, IncrementSize);
5811 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5812 isVolatile, Alignment);
5814 // Build a factor node to remember that this load is independent of the
5816 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5819 // Remember that we legalized the chain.
5820 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5821 if (TLI.isBigEndian())
5824 MVT::ValueType EVT = LD->getMemoryVT();
5826 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5827 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5828 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5829 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5830 SVOffset, isVolatile, Alignment);
5831 // Remember that we legalized the chain.
5832 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5833 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5838 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5839 SVOffset, isVolatile, Alignment);
5841 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5842 SVOffset, EVT, isVolatile,
5845 // Remember that we legalized the chain.
5846 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5848 if (ExtType == ISD::SEXTLOAD) {
5849 // The high part is obtained by SRA'ing all but one of the bits of the
5851 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5852 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5853 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5854 } else if (ExtType == ISD::ZEXTLOAD) {
5855 // The high part is just a zero.
5856 Hi = DAG.getConstant(0, NVT);
5857 } else /* if (ExtType == ISD::EXTLOAD) */ {
5858 // The high part is undefined.
5859 Hi = DAG.getNode(ISD::UNDEF, NVT);
5866 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5867 SDOperand LL, LH, RL, RH;
5868 ExpandOp(Node->getOperand(0), LL, LH);
5869 ExpandOp(Node->getOperand(1), RL, RH);
5870 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5871 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5875 SDOperand LL, LH, RL, RH;
5876 ExpandOp(Node->getOperand(1), LL, LH);
5877 ExpandOp(Node->getOperand(2), RL, RH);
5878 if (getTypeAction(NVT) == Expand)
5879 NVT = TLI.getTypeToExpandTo(NVT);
5880 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5882 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5885 case ISD::SELECT_CC: {
5886 SDOperand TL, TH, FL, FH;
5887 ExpandOp(Node->getOperand(2), TL, TH);
5888 ExpandOp(Node->getOperand(3), FL, FH);
5889 if (getTypeAction(NVT) == Expand)
5890 NVT = TLI.getTypeToExpandTo(NVT);
5891 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5892 Node->getOperand(1), TL, FL, Node->getOperand(4));
5894 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5895 Node->getOperand(1), TH, FH, Node->getOperand(4));
5898 case ISD::ANY_EXTEND:
5899 // The low part is any extension of the input (which degenerates to a copy).
5900 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5901 // The high part is undefined.
5902 Hi = DAG.getNode(ISD::UNDEF, NVT);
5904 case ISD::SIGN_EXTEND: {
5905 // The low part is just a sign extension of the input (which degenerates to
5907 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5909 // The high part is obtained by SRA'ing all but one of the bits of the lo
5911 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5912 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5913 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5916 case ISD::ZERO_EXTEND:
5917 // The low part is just a zero extension of the input (which degenerates to
5919 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5921 // The high part is just a zero.
5922 Hi = DAG.getConstant(0, NVT);
5925 case ISD::TRUNCATE: {
5926 // The input value must be larger than this value. Expand *it*.
5928 ExpandOp(Node->getOperand(0), NewLo, Hi);
5930 // The low part is now either the right size, or it is closer. If not the
5931 // right size, make an illegal truncate so we recursively expand it.
5932 if (NewLo.getValueType() != Node->getValueType(0))
5933 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
5934 ExpandOp(NewLo, Lo, Hi);
5938 case ISD::BIT_CONVERT: {
5940 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
5941 // If the target wants to, allow it to lower this itself.
5942 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5943 case Expand: assert(0 && "cannot expand FP!");
5944 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
5945 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
5947 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
5950 // f32 / f64 must be expanded to i32 / i64.
5951 if (VT == MVT::f32 || VT == MVT::f64) {
5952 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5953 if (getTypeAction(NVT) == Expand)
5954 ExpandOp(Lo, Lo, Hi);
5958 // If source operand will be expanded to the same type as VT, i.e.
5959 // i64 <- f64, i32 <- f32, expand the source operand instead.
5960 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
5961 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
5962 ExpandOp(Node->getOperand(0), Lo, Hi);
5966 // Turn this into a load/store pair by default.
5968 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
5970 ExpandOp(Tmp, Lo, Hi);
5974 case ISD::READCYCLECOUNTER: {
5975 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5976 TargetLowering::Custom &&
5977 "Must custom expand ReadCycleCounter");
5978 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
5979 assert(Tmp.Val && "Node must be custom expanded!");
5980 ExpandOp(Tmp.getValue(0), Lo, Hi);
5981 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5982 LegalizeOp(Tmp.getValue(1)));
5986 // These operators cannot be expanded directly, emit them as calls to
5987 // library functions.
5988 case ISD::FP_TO_SINT: {
5989 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5991 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5992 case Expand: assert(0 && "cannot expand FP!");
5993 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5994 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5997 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5999 // Now that the custom expander is done, expand the result, which is still
6002 ExpandOp(Op, Lo, Hi);
6007 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6008 if (Node->getOperand(0).getValueType() == MVT::f32)
6009 LC = RTLIB::FPTOSINT_F32_I64;
6010 else if (Node->getOperand(0).getValueType() == MVT::f64)
6011 LC = RTLIB::FPTOSINT_F64_I64;
6012 else if (Node->getOperand(0).getValueType() == MVT::f80)
6013 LC = RTLIB::FPTOSINT_F80_I64;
6014 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6015 LC = RTLIB::FPTOSINT_PPCF128_I64;
6016 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6017 false/*sign irrelevant*/, Hi);
6021 case ISD::FP_TO_UINT: {
6022 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6024 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6025 case Expand: assert(0 && "cannot expand FP!");
6026 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6027 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6030 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6032 // Now that the custom expander is done, expand the result.
6034 ExpandOp(Op, Lo, Hi);
6039 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6040 if (Node->getOperand(0).getValueType() == MVT::f32)
6041 LC = RTLIB::FPTOUINT_F32_I64;
6042 else if (Node->getOperand(0).getValueType() == MVT::f64)
6043 LC = RTLIB::FPTOUINT_F64_I64;
6044 else if (Node->getOperand(0).getValueType() == MVT::f80)
6045 LC = RTLIB::FPTOUINT_F80_I64;
6046 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6047 LC = RTLIB::FPTOUINT_PPCF128_I64;
6048 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6049 false/*sign irrelevant*/, Hi);
6054 // If the target wants custom lowering, do so.
6055 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6056 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6057 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6058 Op = TLI.LowerOperation(Op, DAG);
6060 // Now that the custom expander is done, expand the result, which is
6062 ExpandOp(Op, Lo, Hi);
6067 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6068 // this X << 1 as X+X.
6069 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6070 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6071 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6072 SDOperand LoOps[2], HiOps[3];
6073 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6074 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6075 LoOps[1] = LoOps[0];
6076 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6078 HiOps[1] = HiOps[0];
6079 HiOps[2] = Lo.getValue(1);
6080 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6085 // If we can emit an efficient shift operation, do so now.
6086 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6089 // If this target supports SHL_PARTS, use it.
6090 TargetLowering::LegalizeAction Action =
6091 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6092 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6093 Action == TargetLowering::Custom) {
6094 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6098 // Otherwise, emit a libcall.
6099 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
6100 false/*left shift=unsigned*/, Hi);
6105 // If the target wants custom lowering, do so.
6106 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6107 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6108 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6109 Op = TLI.LowerOperation(Op, DAG);
6111 // Now that the custom expander is done, expand the result, which is
6113 ExpandOp(Op, Lo, Hi);
6118 // If we can emit an efficient shift operation, do so now.
6119 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6122 // If this target supports SRA_PARTS, use it.
6123 TargetLowering::LegalizeAction Action =
6124 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6125 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6126 Action == TargetLowering::Custom) {
6127 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6131 // Otherwise, emit a libcall.
6132 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
6133 true/*ashr is signed*/, Hi);
6138 // If the target wants custom lowering, do so.
6139 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6140 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6141 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6142 Op = TLI.LowerOperation(Op, DAG);
6144 // Now that the custom expander is done, expand the result, which is
6146 ExpandOp(Op, Lo, Hi);
6151 // If we can emit an efficient shift operation, do so now.
6152 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6155 // If this target supports SRL_PARTS, use it.
6156 TargetLowering::LegalizeAction Action =
6157 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6158 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6159 Action == TargetLowering::Custom) {
6160 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6164 // Otherwise, emit a libcall.
6165 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
6166 false/*lshr is unsigned*/, Hi);
6172 // If the target wants to custom expand this, let them.
6173 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6174 TargetLowering::Custom) {
6175 Op = TLI.LowerOperation(Op, DAG);
6177 ExpandOp(Op, Lo, Hi);
6182 // Expand the subcomponents.
6183 SDOperand LHSL, LHSH, RHSL, RHSH;
6184 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6185 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6186 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6187 SDOperand LoOps[2], HiOps[3];
6192 if (Node->getOpcode() == ISD::ADD) {
6193 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6194 HiOps[2] = Lo.getValue(1);
6195 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6197 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6198 HiOps[2] = Lo.getValue(1);
6199 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6206 // Expand the subcomponents.
6207 SDOperand LHSL, LHSH, RHSL, RHSH;
6208 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6209 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6210 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6211 SDOperand LoOps[2] = { LHSL, RHSL };
6212 SDOperand HiOps[3] = { LHSH, RHSH };
6214 if (Node->getOpcode() == ISD::ADDC) {
6215 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6216 HiOps[2] = Lo.getValue(1);
6217 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6219 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6220 HiOps[2] = Lo.getValue(1);
6221 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6223 // Remember that we legalized the flag.
6224 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6229 // Expand the subcomponents.
6230 SDOperand LHSL, LHSH, RHSL, RHSH;
6231 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6232 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6233 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6234 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6235 SDOperand HiOps[3] = { LHSH, RHSH };
6237 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6238 HiOps[2] = Lo.getValue(1);
6239 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6241 // Remember that we legalized the flag.
6242 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6246 // If the target wants to custom expand this, let them.
6247 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6248 SDOperand New = TLI.LowerOperation(Op, DAG);
6250 ExpandOp(New, Lo, Hi);
6255 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6256 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6257 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6258 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6259 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6260 SDOperand LL, LH, RL, RH;
6261 ExpandOp(Node->getOperand(0), LL, LH);
6262 ExpandOp(Node->getOperand(1), RL, RH);
6263 unsigned BitSize = MVT::getSizeInBits(RH.getValueType());
6264 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6265 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6266 // FIXME: generalize this to handle other bit sizes
6267 if (LHSSB == 32 && RHSSB == 32 &&
6268 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) &&
6269 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) {
6270 // The inputs are both zero-extended.
6272 // We can emit a umul_lohi.
6273 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6274 Hi = SDOperand(Lo.Val, 1);
6278 // We can emit a mulhu+mul.
6279 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6280 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6284 if (LHSSB > BitSize && RHSSB > BitSize) {
6285 // The input values are both sign-extended.
6287 // We can emit a smul_lohi.
6288 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6289 Hi = SDOperand(Lo.Val, 1);
6293 // We can emit a mulhs+mul.
6294 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6295 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6300 // Lo,Hi = umul LHS, RHS.
6301 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6302 DAG.getVTList(NVT, NVT), LL, RL);
6304 Hi = UMulLOHI.getValue(1);
6305 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6306 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6307 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6308 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6312 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6313 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6314 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6315 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6316 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6317 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6322 // If nothing else, we can make a libcall.
6323 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
6324 false/*sign irrelevant*/, Hi);
6328 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
6331 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
6334 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
6337 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
6341 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32,
6344 RTLIB::ADD_PPCF128)),
6348 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32,
6351 RTLIB::SUB_PPCF128)),
6355 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32,
6358 RTLIB::MUL_PPCF128)),
6362 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32,
6365 RTLIB::DIV_PPCF128)),
6368 case ISD::FP_EXTEND:
6369 if (VT == MVT::ppcf128) {
6370 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6371 Node->getOperand(0).getValueType()==MVT::f64);
6372 const uint64_t zero = 0;
6373 if (Node->getOperand(0).getValueType()==MVT::f32)
6374 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6376 Hi = Node->getOperand(0);
6377 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6380 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
6383 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
6386 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32,
6389 RTLIB::POWI_PPCF128)),
6395 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6396 switch(Node->getOpcode()) {
6398 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6399 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6402 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6403 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6406 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6407 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6409 default: assert(0 && "Unreachable!");
6411 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
6415 if (VT == MVT::ppcf128) {
6417 ExpandOp(Node->getOperand(0), Lo, Tmp);
6418 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6419 // lo = hi==fabs(hi) ? lo : -lo;
6420 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6421 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6422 DAG.getCondCode(ISD::SETEQ));
6425 SDOperand Mask = (VT == MVT::f64)
6426 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6427 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6428 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6429 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6430 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6431 if (getTypeAction(NVT) == Expand)
6432 ExpandOp(Lo, Lo, Hi);
6436 if (VT == MVT::ppcf128) {
6437 ExpandOp(Node->getOperand(0), Lo, Hi);
6438 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6439 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6442 SDOperand Mask = (VT == MVT::f64)
6443 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6444 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6445 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6446 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6447 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6448 if (getTypeAction(NVT) == Expand)
6449 ExpandOp(Lo, Lo, Hi);
6452 case ISD::FCOPYSIGN: {
6453 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6454 if (getTypeAction(NVT) == Expand)
6455 ExpandOp(Lo, Lo, Hi);
6458 case ISD::SINT_TO_FP:
6459 case ISD::UINT_TO_FP: {
6460 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6461 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
6462 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) {
6463 static uint64_t zero = 0;
6465 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6466 Node->getOperand(0)));
6467 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6469 static uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6470 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6471 Node->getOperand(0)));
6472 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6473 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6474 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6475 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6476 DAG.getConstant(0, MVT::i32),
6477 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6479 APFloat(APInt(128, 2, TwoE32)),
6482 DAG.getCondCode(ISD::SETLT)),
6487 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6488 // si64->ppcf128 done by libcall, below
6489 static uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6490 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6492 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6493 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6494 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6495 DAG.getConstant(0, MVT::i64),
6496 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6498 APFloat(APInt(128, 2, TwoE64)),
6501 DAG.getCondCode(ISD::SETLT)),
6505 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6506 if (Node->getOperand(0).getValueType() == MVT::i64) {
6508 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
6509 else if (VT == MVT::f64)
6510 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
6511 else if (VT == MVT::f80) {
6513 LC = RTLIB::SINTTOFP_I64_F80;
6515 else if (VT == MVT::ppcf128) {
6517 LC = RTLIB::SINTTOFP_I64_PPCF128;
6521 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
6523 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
6526 // Promote the operand if needed.
6527 if (getTypeAction(SrcVT) == Promote) {
6528 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6530 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6531 DAG.getValueType(SrcVT))
6532 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6533 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6536 const char *LibCall = TLI.getLibcallName(LC);
6538 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
6540 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6541 Node->getOperand(0));
6542 if (getTypeAction(Lo.getValueType()) == Expand)
6543 ExpandOp(Lo, Lo, Hi);
6549 // Make sure the resultant values have been legalized themselves, unless this
6550 // is a type that requires multi-step expansion.
6551 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6552 Lo = LegalizeOp(Lo);
6554 // Don't legalize the high part if it is expanded to a single node.
6555 Hi = LegalizeOp(Hi);
6558 // Remember in a map if the values will be reused later.
6559 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6560 assert(isNew && "Value already expanded?!?");
6563 /// SplitVectorOp - Given an operand of vector type, break it down into
6564 /// two smaller values, still of vector type.
6565 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6567 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
6568 SDNode *Node = Op.Val;
6569 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
6570 assert(NumElements > 1 && "Cannot split a single element vector!");
6572 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
6574 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6575 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6577 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
6578 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
6580 // See if we already split it.
6581 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6582 = SplitNodes.find(Op);
6583 if (I != SplitNodes.end()) {
6584 Lo = I->second.first;
6585 Hi = I->second.second;
6589 switch (Node->getOpcode()) {
6594 assert(0 && "Unhandled operation in SplitVectorOp!");
6596 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6597 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6599 case ISD::BUILD_PAIR:
6600 Lo = Node->getOperand(0);
6601 Hi = Node->getOperand(1);
6603 case ISD::INSERT_VECTOR_ELT: {
6604 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6605 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
6606 SDOperand ScalarOp = Node->getOperand(1);
6607 if (Index < NewNumElts_Lo)
6608 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6609 DAG.getConstant(Index, TLI.getPointerTy()));
6611 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6612 DAG.getConstant(Index - NewNumElts_Lo,
6613 TLI.getPointerTy()));
6616 case ISD::VECTOR_SHUFFLE: {
6617 // Build the low part.
6618 SDOperand Mask = Node->getOperand(2);
6619 SmallVector<SDOperand, 8> Ops;
6620 MVT::ValueType PtrVT = TLI.getPointerTy();
6622 // Insert all of the elements from the input that are needed. We use
6623 // buildvector of extractelement here because the input vectors will have
6624 // to be legalized, so this makes the code simpler.
6625 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6626 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6627 SDOperand InVec = Node->getOperand(0);
6628 if (Idx >= NumElements) {
6629 InVec = Node->getOperand(1);
6632 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6633 DAG.getConstant(Idx, PtrVT)));
6635 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6638 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6639 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6640 SDOperand InVec = Node->getOperand(0);
6641 if (Idx >= NumElements) {
6642 InVec = Node->getOperand(1);
6645 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6646 DAG.getConstant(Idx, PtrVT)));
6648 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6651 case ISD::BUILD_VECTOR: {
6652 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6653 Node->op_begin()+NewNumElts_Lo);
6654 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6656 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6658 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6661 case ISD::CONCAT_VECTORS: {
6662 // FIXME: Handle non-power-of-two vectors?
6663 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6664 if (NewNumSubvectors == 1) {
6665 Lo = Node->getOperand(0);
6666 Hi = Node->getOperand(1);
6668 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6669 Node->op_begin()+NewNumSubvectors);
6670 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6672 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6674 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6679 SDOperand Cond = Node->getOperand(0);
6681 SDOperand LL, LH, RL, RH;
6682 SplitVectorOp(Node->getOperand(1), LL, LH);
6683 SplitVectorOp(Node->getOperand(2), RL, RH);
6685 if (MVT::isVector(Cond.getValueType())) {
6686 // Handle a vector merge.
6688 SplitVectorOp(Cond, CL, CH);
6689 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6690 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6692 // Handle a simple select with vector operands.
6693 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6694 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6714 SDOperand LL, LH, RL, RH;
6715 SplitVectorOp(Node->getOperand(0), LL, LH);
6716 SplitVectorOp(Node->getOperand(1), RL, RH);
6718 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6719 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6724 SplitVectorOp(Node->getOperand(0), L, H);
6726 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6727 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6738 case ISD::FP_TO_SINT:
6739 case ISD::FP_TO_UINT:
6740 case ISD::SINT_TO_FP:
6741 case ISD::UINT_TO_FP: {
6743 SplitVectorOp(Node->getOperand(0), L, H);
6745 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6746 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6750 LoadSDNode *LD = cast<LoadSDNode>(Node);
6751 SDOperand Ch = LD->getChain();
6752 SDOperand Ptr = LD->getBasePtr();
6753 const Value *SV = LD->getSrcValue();
6754 int SVOffset = LD->getSrcValueOffset();
6755 unsigned Alignment = LD->getAlignment();
6756 bool isVolatile = LD->isVolatile();
6758 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6759 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
6760 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6761 DAG.getIntPtrConstant(IncrementSize));
6762 SVOffset += IncrementSize;
6763 Alignment = MinAlign(Alignment, IncrementSize);
6764 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6766 // Build a factor node to remember that this load is independent of the
6768 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6771 // Remember that we legalized the chain.
6772 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6775 case ISD::BIT_CONVERT: {
6776 // We know the result is a vector. The input may be either a vector or a
6778 SDOperand InOp = Node->getOperand(0);
6779 if (!MVT::isVector(InOp.getValueType()) ||
6780 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
6781 // The input is a scalar or single-element vector.
6782 // Lower to a store/load so that it can be split.
6783 // FIXME: this could be improved probably.
6784 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6785 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val);
6787 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6789 PseudoSourceValue::getFixedStack(),
6791 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
6792 PseudoSourceValue::getFixedStack(),
6795 // Split the vector and convert each of the pieces now.
6796 SplitVectorOp(InOp, Lo, Hi);
6797 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6798 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6803 // Remember in a map if the values will be reused later.
6805 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6806 assert(isNew && "Value already split?!?");
6810 /// ScalarizeVectorOp - Given an operand of single-element vector type
6811 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6812 /// scalar (e.g. f32) value.
6813 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6814 assert(MVT::isVector(Op.getValueType()) &&
6815 "Bad ScalarizeVectorOp invocation!");
6816 SDNode *Node = Op.Val;
6817 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
6818 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
6820 // See if we already scalarized it.
6821 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
6822 if (I != ScalarizedNodes.end()) return I->second;
6825 switch (Node->getOpcode()) {
6828 Node->dump(&DAG); cerr << "\n";
6830 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
6847 Result = DAG.getNode(Node->getOpcode(),
6849 ScalarizeVectorOp(Node->getOperand(0)),
6850 ScalarizeVectorOp(Node->getOperand(1)));
6857 Result = DAG.getNode(Node->getOpcode(),
6859 ScalarizeVectorOp(Node->getOperand(0)));
6862 Result = DAG.getNode(Node->getOpcode(),
6864 ScalarizeVectorOp(Node->getOperand(0)),
6865 Node->getOperand(1));
6868 LoadSDNode *LD = cast<LoadSDNode>(Node);
6869 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
6870 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
6872 const Value *SV = LD->getSrcValue();
6873 int SVOffset = LD->getSrcValueOffset();
6874 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
6875 LD->isVolatile(), LD->getAlignment());
6877 // Remember that we legalized the chain.
6878 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
6881 case ISD::BUILD_VECTOR:
6882 Result = Node->getOperand(0);
6884 case ISD::INSERT_VECTOR_ELT:
6885 // Returning the inserted scalar element.
6886 Result = Node->getOperand(1);
6888 case ISD::CONCAT_VECTORS:
6889 assert(Node->getOperand(0).getValueType() == NewVT &&
6890 "Concat of non-legal vectors not yet supported!");
6891 Result = Node->getOperand(0);
6893 case ISD::VECTOR_SHUFFLE: {
6894 // Figure out if the scalar is the LHS or RHS and return it.
6895 SDOperand EltNum = Node->getOperand(2).getOperand(0);
6896 if (cast<ConstantSDNode>(EltNum)->getValue())
6897 Result = ScalarizeVectorOp(Node->getOperand(1));
6899 Result = ScalarizeVectorOp(Node->getOperand(0));
6902 case ISD::EXTRACT_SUBVECTOR:
6903 Result = Node->getOperand(0);
6904 assert(Result.getValueType() == NewVT);
6906 case ISD::BIT_CONVERT:
6907 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
6910 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
6911 ScalarizeVectorOp(Op.getOperand(1)),
6912 ScalarizeVectorOp(Op.getOperand(2)));
6916 if (TLI.isTypeLegal(NewVT))
6917 Result = LegalizeOp(Result);
6918 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
6919 assert(isNew && "Value already scalarized?");
6924 // SelectionDAG::Legalize - This is the entry point for the file.
6926 void SelectionDAG::Legalize() {
6927 if (ViewLegalizeDAGs) viewGraph();
6929 /// run - This is the main entry point to this class.
6931 SelectionDAGLegalize(*this).LegalizeDAG();