1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineConstantPool.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/Constants.h"
25 //===----------------------------------------------------------------------===//
26 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
27 /// hacks on it until the target machine can handle it. This involves
28 /// eliminating value sizes the machine cannot handle (promoting small sizes to
29 /// large sizes or splitting up large values into small values) as well as
30 /// eliminating operations the machine cannot handle.
32 /// This code also does a small amount of optimization and recognition of idioms
33 /// as part of its processing. For example, if a target does not support a
34 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
35 /// will attempt merge setcc and brc instructions into brcc's.
38 class SelectionDAGLegalize {
42 /// LegalizeAction - This enum indicates what action we should take for each
43 /// value type the can occur in the program.
45 Legal, // The target natively supports this value type.
46 Promote, // This should be promoted to the next larger type.
47 Expand, // This integer type should be broken into smaller pieces.
50 /// ValueTypeActions - This is a bitvector that contains two bits for each
51 /// value type, where the two bits correspond to the LegalizeAction enum.
52 /// This can be queried with "getTypeAction(VT)".
53 unsigned ValueTypeActions;
55 /// NeedsAnotherIteration - This is set when we expand a large integer
56 /// operation into smaller integer operations, but the smaller operations are
57 /// not set. This occurs only rarely in practice, for targets that don't have
58 /// 32-bit or larger integer registers.
59 bool NeedsAnotherIteration;
61 /// LegalizedNodes - For nodes that are of legal width, and that have more
62 /// than one use, this map indicates what regularized operand to use. This
63 /// allows us to avoid legalizing the same thing more than once.
64 std::map<SDOperand, SDOperand> LegalizedNodes;
66 /// PromotedNodes - For nodes that are below legal width, and that have more
67 /// than one use, this map indicates what promoted value to use. This allows
68 /// us to avoid promoting the same thing more than once.
69 std::map<SDOperand, SDOperand> PromotedNodes;
71 /// ExpandedNodes - For nodes that need to be expanded, and which have more
72 /// than one use, this map indicates which which operands are the expanded
73 /// version of the input. This allows us to avoid expanding the same node
75 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
77 void AddLegalizedOperand(SDOperand From, SDOperand To) {
78 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second;
79 assert(isNew && "Got into the map somehow?");
81 void AddPromotedOperand(SDOperand From, SDOperand To) {
82 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
83 assert(isNew && "Got into the map somehow?");
88 SelectionDAGLegalize(SelectionDAG &DAG);
90 /// Run - While there is still lowering to do, perform a pass over the DAG.
91 /// Most regularization can be done in a single pass, but targets that require
92 /// large values to be split into registers multiple times (e.g. i64 -> 4x
93 /// i16) require iteration for these values (the first iteration will demote
94 /// to i32, the second will demote to i16).
97 NeedsAnotherIteration = false;
99 } while (NeedsAnotherIteration);
102 /// getTypeAction - Return how we should legalize values of this type, either
103 /// it is already legal or we need to expand it into multiple registers of
104 /// smaller integer type, or we need to promote it to a larger type.
105 LegalizeAction getTypeAction(MVT::ValueType VT) const {
106 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3);
109 /// isTypeLegal - Return true if this type is legal on this target.
111 bool isTypeLegal(MVT::ValueType VT) const {
112 return getTypeAction(VT) == Legal;
118 SDOperand LegalizeOp(SDOperand O);
119 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
120 SDOperand PromoteOp(SDOperand O);
122 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
124 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
126 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
127 SDOperand &Lo, SDOperand &Hi);
128 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
129 SDOperand &Lo, SDOperand &Hi);
130 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
131 SDOperand &Lo, SDOperand &Hi);
133 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain);
135 SDOperand getIntPtrConstant(uint64_t Val) {
136 return DAG.getConstant(Val, TLI.getPointerTy());
142 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
143 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
144 ValueTypeActions(TLI.getValueTypeActions()) {
145 assert(MVT::LAST_VALUETYPE <= 16 &&
146 "Too many value types for ValueTypeActions to hold!");
149 void SelectionDAGLegalize::LegalizeDAG() {
150 SDOperand OldRoot = DAG.getRoot();
151 SDOperand NewRoot = LegalizeOp(OldRoot);
152 DAG.setRoot(NewRoot);
154 ExpandedNodes.clear();
155 LegalizedNodes.clear();
156 PromotedNodes.clear();
158 // Remove dead nodes now.
159 DAG.RemoveDeadNodes(OldRoot.Val);
162 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
163 assert(getTypeAction(Op.getValueType()) == Legal &&
164 "Caller should expand or promote operands that are not legal!");
166 // If this operation defines any values that cannot be represented in a
167 // register on this target, make sure to expand or promote them.
168 if (Op.Val->getNumValues() > 1) {
169 for (unsigned i = 0, e = Op.Val->getNumValues(); i != e; ++i)
170 switch (getTypeAction(Op.Val->getValueType(i))) {
171 case Legal: break; // Nothing to do.
174 ExpandOp(Op.getValue(i), T1, T2);
175 assert(LegalizedNodes.count(Op) &&
176 "Expansion didn't add legal operands!");
177 return LegalizedNodes[Op];
180 PromoteOp(Op.getValue(i));
181 assert(LegalizedNodes.count(Op) &&
182 "Expansion didn't add legal operands!");
183 return LegalizedNodes[Op];
187 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
188 if (I != LegalizedNodes.end()) return I->second;
190 SDOperand Tmp1, Tmp2, Tmp3;
192 SDOperand Result = Op;
193 SDNode *Node = Op.Val;
195 switch (Node->getOpcode()) {
197 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
198 assert(0 && "Do not know how to legalize this operator!");
200 case ISD::EntryToken:
201 case ISD::FrameIndex:
202 case ISD::GlobalAddress:
203 case ISD::ExternalSymbol:
204 case ISD::ConstantPool: // Nothing to do.
205 assert(getTypeAction(Node->getValueType(0)) == Legal &&
206 "This must be legal!");
208 case ISD::CopyFromReg:
209 Tmp1 = LegalizeOp(Node->getOperand(0));
210 if (Tmp1 != Node->getOperand(0))
211 Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(),
212 Node->getValueType(0), Tmp1);
214 Result = Op.getValue(0);
216 // Since CopyFromReg produces two values, make sure to remember that we
217 // legalized both of them.
218 AddLegalizedOperand(Op.getValue(0), Result);
219 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
220 return Result.getValue(Op.ResNo);
221 case ISD::ImplicitDef:
222 Tmp1 = LegalizeOp(Node->getOperand(0));
223 if (Tmp1 != Node->getOperand(0))
224 Result = DAG.getImplicitDef(Tmp1, cast<RegSDNode>(Node)->getReg());
227 MVT::ValueType VT = Op.getValueType();
228 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
229 default: assert(0 && "This action is not supported yet!");
230 case TargetLowering::Expand:
231 case TargetLowering::Promote:
232 if (MVT::isInteger(VT))
233 Result = DAG.getConstant(0, VT);
234 else if (MVT::isFloatingPoint(VT))
235 Result = DAG.getConstantFP(0, VT);
237 assert(0 && "Unknown value type!");
239 case TargetLowering::Legal:
245 // We know we don't need to expand constants here, constants only have one
246 // value and we check that it is fine above.
248 // FIXME: Maybe we should handle things like targets that don't support full
249 // 32-bit immediates?
251 case ISD::ConstantFP: {
252 // Spill FP immediates to the constant pool if the target cannot directly
253 // codegen them. Targets often have some immediate values that can be
254 // efficiently generated into an FP register without a load. We explicitly
255 // leave these constants as ConstantFP nodes for the target to deal with.
257 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
259 // Check to see if this FP immediate is already legal.
260 bool isLegal = false;
261 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
262 E = TLI.legal_fpimm_end(); I != E; ++I)
263 if (CFP->isExactlyValue(*I)) {
269 // Otherwise we need to spill the constant to memory.
270 MachineConstantPool *CP = DAG.getMachineFunction().getConstantPool();
274 // If a FP immediate is precise when represented as a float, we put it
275 // into the constant pool as a float, even if it's is statically typed
277 MVT::ValueType VT = CFP->getValueType(0);
278 bool isDouble = VT == MVT::f64;
279 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
280 Type::FloatTy, CFP->getValue());
281 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
282 // Only do this if the target has a native EXTLOAD instruction from
284 TLI.getOperationAction(ISD::EXTLOAD,
285 MVT::f32) == TargetLowering::Legal) {
286 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
291 SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(LLVMC),
294 Result = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), CPIdx,
295 DAG.getSrcValue(NULL), MVT::f32);
297 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
298 DAG.getSrcValue(NULL));
303 case ISD::TokenFactor: {
304 std::vector<SDOperand> Ops;
305 bool Changed = false;
306 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
307 SDOperand Op = Node->getOperand(i);
308 // Fold single-use TokenFactor nodes into this token factor as we go.
309 // FIXME: This is something that the DAGCombiner should do!!
310 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
312 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
313 Ops.push_back(LegalizeOp(Op.getOperand(j)));
315 Ops.push_back(LegalizeOp(Op)); // Legalize the operands
316 Changed |= Ops[i] != Op;
320 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
324 case ISD::ADJCALLSTACKDOWN:
325 case ISD::ADJCALLSTACKUP:
326 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
327 // There is no need to legalize the size argument (Operand #1)
328 if (Tmp1 != Node->getOperand(0))
329 Node->setAdjCallChain(Tmp1);
330 // Note that we do not create new ADJCALLSTACK DOWN/UP nodes here. These
331 // nodes are treated specially and are mutated in place. This makes the dag
332 // legalization process more efficient and also makes libcall insertion
335 case ISD::DYNAMIC_STACKALLOC:
336 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
337 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
338 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
339 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
340 Tmp3 != Node->getOperand(2))
341 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, Node->getValueType(0),
344 Result = Op.getValue(0);
346 // Since this op produces two values, make sure to remember that we
347 // legalized both of them.
348 AddLegalizedOperand(SDOperand(Node, 0), Result);
349 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
350 return Result.getValue(Op.ResNo);
353 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
354 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
356 bool Changed = false;
357 std::vector<SDOperand> Ops;
358 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
359 Ops.push_back(LegalizeOp(Node->getOperand(i)));
360 Changed |= Ops.back() != Node->getOperand(i);
363 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) {
364 std::vector<MVT::ValueType> RetTyVTs;
365 RetTyVTs.reserve(Node->getNumValues());
366 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
367 RetTyVTs.push_back(Node->getValueType(i));
368 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops), 0);
370 Result = Result.getValue(0);
372 // Since calls produce multiple values, make sure to remember that we
373 // legalized all of them.
374 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
375 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
376 return Result.getValue(Op.ResNo);
379 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
380 if (Tmp1 != Node->getOperand(0))
381 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1));
385 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
387 switch (getTypeAction(Node->getOperand(1).getValueType())) {
388 case Expand: assert(0 && "It's impossible to expand bools");
390 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
393 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
396 // Basic block destination (Op#2) is always legal.
397 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
398 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
399 Node->getOperand(2));
401 case ISD::BRCONDTWOWAY:
402 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
403 switch (getTypeAction(Node->getOperand(1).getValueType())) {
404 case Expand: assert(0 && "It's impossible to expand bools");
406 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
409 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
412 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR
414 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) {
415 case TargetLowering::Promote:
416 default: assert(0 && "This action is not supported yet!");
417 case TargetLowering::Legal:
418 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
419 std::vector<SDOperand> Ops;
422 Ops.push_back(Node->getOperand(2));
423 Ops.push_back(Node->getOperand(3));
424 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops);
427 case TargetLowering::Expand:
428 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
429 Node->getOperand(2));
430 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3));
436 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
437 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
439 if (Tmp1 != Node->getOperand(0) ||
440 Tmp2 != Node->getOperand(1))
441 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2,
442 Node->getOperand(2));
444 Result = SDOperand(Node, 0);
446 // Since loads produce two values, make sure to remember that we legalized
448 AddLegalizedOperand(SDOperand(Node, 0), Result);
449 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
450 return Result.getValue(Op.ResNo);
454 case ISD::ZEXTLOAD: {
455 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
456 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
458 MVT::ValueType SrcVT = cast<MVTSDNode>(Node)->getExtraValueType();
459 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
460 default: assert(0 && "This action is not supported yet!");
461 case TargetLowering::Promote:
462 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
463 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0),
464 Tmp1, Tmp2, Node->getOperand(2), MVT::i8);
465 // Since loads produce two values, make sure to remember that we legalized
467 AddLegalizedOperand(SDOperand(Node, 0), Result);
468 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
469 return Result.getValue(Op.ResNo);
471 case TargetLowering::Legal:
472 if (Tmp1 != Node->getOperand(0) ||
473 Tmp2 != Node->getOperand(1))
474 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0),
475 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
477 Result = SDOperand(Node, 0);
479 // Since loads produce two values, make sure to remember that we legalized
481 AddLegalizedOperand(SDOperand(Node, 0), Result);
482 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
483 return Result.getValue(Op.ResNo);
484 case TargetLowering::Expand:
485 assert(Node->getOpcode() != ISD::EXTLOAD &&
486 "EXTLOAD should always be supported!");
487 // Turn the unsupported load into an EXTLOAD followed by an explicit
488 // zero/sign extend inreg.
489 Result = DAG.getNode(ISD::EXTLOAD, Node->getValueType(0),
490 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
492 if (Node->getOpcode() == ISD::SEXTLOAD)
493 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
496 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
497 AddLegalizedOperand(SDOperand(Node, 0), ValRes);
498 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
500 return Result.getValue(1);
503 assert(0 && "Unreachable");
505 case ISD::EXTRACT_ELEMENT:
506 // Get both the low and high parts.
507 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
508 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
509 Result = Tmp2; // 1 -> Hi
511 Result = Tmp1; // 0 -> Lo
515 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
517 switch (getTypeAction(Node->getOperand(1).getValueType())) {
519 // Legalize the incoming value (must be legal).
520 Tmp2 = LegalizeOp(Node->getOperand(1));
521 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
522 Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg());
525 Tmp2 = PromoteOp(Node->getOperand(1));
526 Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg());
530 ExpandOp(Node->getOperand(1), Lo, Hi);
531 unsigned Reg = cast<RegSDNode>(Node)->getReg();
532 Lo = DAG.getCopyToReg(Tmp1, Lo, Reg);
533 Hi = DAG.getCopyToReg(Tmp1, Hi, Reg+1);
534 // Note that the copytoreg nodes are independent of each other.
535 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
536 assert(isTypeLegal(Result.getValueType()) &&
537 "Cannot expand multiple times yet (i64 -> i16)");
543 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
544 switch (Node->getNumOperands()) {
546 switch (getTypeAction(Node->getOperand(1).getValueType())) {
548 Tmp2 = LegalizeOp(Node->getOperand(1));
549 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
550 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
554 ExpandOp(Node->getOperand(1), Lo, Hi);
555 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
559 Tmp2 = PromoteOp(Node->getOperand(1));
560 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
565 if (Tmp1 != Node->getOperand(0))
566 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1);
568 default: { // ret <values>
569 std::vector<SDOperand> NewValues;
570 NewValues.push_back(Tmp1);
571 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
572 switch (getTypeAction(Node->getOperand(i).getValueType())) {
574 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
578 ExpandOp(Node->getOperand(i), Lo, Hi);
579 NewValues.push_back(Lo);
580 NewValues.push_back(Hi);
584 assert(0 && "Can't promote multiple return value yet!");
586 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
592 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
593 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
595 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
596 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
597 if (CFP->getValueType(0) == MVT::f32) {
602 V.F = CFP->getValue();
603 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
604 DAG.getConstant(V.I, MVT::i32), Tmp2,
605 Node->getOperand(3));
607 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
612 V.F = CFP->getValue();
613 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
614 DAG.getConstant(V.I, MVT::i64), Tmp2,
615 Node->getOperand(3));
620 switch (getTypeAction(Node->getOperand(1).getValueType())) {
622 SDOperand Val = LegalizeOp(Node->getOperand(1));
623 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) ||
624 Tmp2 != Node->getOperand(2))
625 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2,
626 Node->getOperand(3));
630 // Truncate the value and store the result.
631 Tmp3 = PromoteOp(Node->getOperand(1));
632 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
634 Node->getOperand(1).getValueType());
639 ExpandOp(Node->getOperand(1), Lo, Hi);
641 if (!TLI.isLittleEndian())
644 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
645 Node->getOperand(3));
646 unsigned IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
647 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
648 getIntPtrConstant(IncrementSize));
649 assert(isTypeLegal(Tmp2.getValueType()) &&
650 "Pointers must be legal!");
651 //Again, claiming both parts of the store came form the same Instr
652 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
653 Node->getOperand(3));
654 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
659 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
660 if (Tmp1 != Node->getOperand(0))
661 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1));
663 case ISD::TRUNCSTORE:
664 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
665 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
667 switch (getTypeAction(Node->getOperand(1).getValueType())) {
669 Tmp2 = LegalizeOp(Node->getOperand(1));
670 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
671 Tmp3 != Node->getOperand(2))
672 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
674 cast<MVTSDNode>(Node)->getExtraValueType());
678 assert(0 && "Cannot handle illegal TRUNCSTORE yet!");
682 switch (getTypeAction(Node->getOperand(0).getValueType())) {
683 case Expand: assert(0 && "It's impossible to expand bools");
685 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
688 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
691 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
692 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
694 switch (TLI.getOperationAction(Node->getOpcode(), Tmp2.getValueType())) {
695 default: assert(0 && "This action is not supported yet!");
696 case TargetLowering::Legal:
697 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
698 Tmp3 != Node->getOperand(2))
699 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0),
702 case TargetLowering::Promote: {
704 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
705 unsigned ExtOp, TruncOp;
706 if (MVT::isInteger(Tmp2.getValueType())) {
707 ExtOp = ISD::ZERO_EXTEND;
708 TruncOp = ISD::TRUNCATE;
710 ExtOp = ISD::FP_EXTEND;
711 TruncOp = ISD::FP_ROUND;
713 // Promote each of the values to the new type.
714 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
715 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
716 // Perform the larger operation, then round down.
717 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
718 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
724 switch (getTypeAction(Node->getOperand(0).getValueType())) {
726 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
727 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
728 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
729 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
730 Node->getValueType(0), Tmp1, Tmp2);
733 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS
734 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS
736 // If this is an FP compare, the operands have already been extended.
737 if (MVT::isInteger(Node->getOperand(0).getValueType())) {
738 MVT::ValueType VT = Node->getOperand(0).getValueType();
739 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
741 // Otherwise, we have to insert explicit sign or zero extends. Note
742 // that we could insert sign extends for ALL conditions, but zero extend
743 // is cheaper on many machines (an AND instead of two shifts), so prefer
745 switch (cast<SetCCSDNode>(Node)->getCondition()) {
746 default: assert(0 && "Unknown integer comparison!");
753 // ALL of these operations will work if we either sign or zero extend
754 // the operands (including the unsigned comparisons!). Zero extend is
755 // usually a simpler/cheaper operation, so prefer it.
756 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
757 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
763 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT);
764 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, VT);
769 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
770 Node->getValueType(0), Tmp1, Tmp2);
773 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
774 ExpandOp(Node->getOperand(0), LHSLo, LHSHi);
775 ExpandOp(Node->getOperand(1), RHSLo, RHSHi);
776 switch (cast<SetCCSDNode>(Node)->getCondition()) {
780 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
781 if (RHSCST->isAllOnesValue()) {
783 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
784 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
785 Node->getValueType(0), Tmp1, RHSLo);
789 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
790 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
791 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
792 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
793 Node->getValueType(0), Tmp1,
794 DAG.getConstant(0, Tmp1.getValueType()));
797 // If this is a comparison of the sign bit, just look at the top part.
799 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
800 if ((cast<SetCCSDNode>(Node)->getCondition() == ISD::SETLT &&
801 CST->getValue() == 0) || // X < 0
802 (cast<SetCCSDNode>(Node)->getCondition() == ISD::SETGT &&
803 (CST->isAllOnesValue()))) // X > -1
804 return DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
805 Node->getValueType(0), LHSHi, RHSHi);
807 // FIXME: This generated code sucks.
809 switch (cast<SetCCSDNode>(Node)->getCondition()) {
810 default: assert(0 && "Unknown integer setcc!");
812 case ISD::SETULT: LowCC = ISD::SETULT; break;
814 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
816 case ISD::SETULE: LowCC = ISD::SETULE; break;
818 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
821 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
822 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
823 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
825 // NOTE: on targets without efficient SELECT of bools, we can always use
826 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
827 Tmp1 = DAG.getSetCC(LowCC, Node->getValueType(0), LHSLo, RHSLo);
828 Tmp2 = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
829 Node->getValueType(0), LHSHi, RHSHi);
830 Result = DAG.getSetCC(ISD::SETEQ, Node->getValueType(0), LHSHi, RHSHi);
831 Result = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
841 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
842 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
844 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
845 switch (getTypeAction(Node->getOperand(2).getValueType())) {
846 case Expand: assert(0 && "Cannot expand a byte!");
848 Tmp3 = LegalizeOp(Node->getOperand(2));
851 Tmp3 = PromoteOp(Node->getOperand(2));
855 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
859 switch (getTypeAction(Node->getOperand(3).getValueType())) {
860 case Expand: assert(0 && "Cannot expand this yet!");
862 Tmp4 = LegalizeOp(Node->getOperand(3));
865 Tmp4 = PromoteOp(Node->getOperand(3));
870 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
871 case Expand: assert(0 && "Cannot expand this yet!");
873 Tmp5 = LegalizeOp(Node->getOperand(4));
876 Tmp5 = PromoteOp(Node->getOperand(4));
880 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
881 default: assert(0 && "This action not implemented for this operation!");
882 case TargetLowering::Legal:
883 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
884 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) ||
885 Tmp5 != Node->getOperand(4)) {
886 std::vector<SDOperand> Ops;
887 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
888 Ops.push_back(Tmp4); Ops.push_back(Tmp5);
889 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops);
892 case TargetLowering::Expand: {
893 // Otherwise, the target does not support this operation. Lower the
894 // operation to an explicit libcall as appropriate.
895 MVT::ValueType IntPtr = TLI.getPointerTy();
896 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType();
897 std::vector<std::pair<SDOperand, const Type*> > Args;
899 const char *FnName = 0;
900 if (Node->getOpcode() == ISD::MEMSET) {
901 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
902 // Extend the ubyte argument to be an int value for the call.
903 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
904 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
905 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
908 } else if (Node->getOpcode() == ISD::MEMCPY ||
909 Node->getOpcode() == ISD::MEMMOVE) {
910 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
911 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
912 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
913 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
915 assert(0 && "Unknown op!");
917 // FIXME: THESE SHOULD USE ExpandLibCall ??!?
918 std::pair<SDOperand,SDOperand> CallResult =
919 TLI.LowerCallTo(Tmp1, Type::VoidTy, false,
920 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
921 Result = LegalizeOp(CallResult.second);
924 case TargetLowering::Custom:
925 std::vector<SDOperand> Ops;
926 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
927 Ops.push_back(Tmp4); Ops.push_back(Tmp5);
928 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops);
929 Result = TLI.LowerOperation(Result);
930 Result = LegalizeOp(Result);
937 Tmp1 = LegalizeOp(Node->getOperand(0));
938 Tmp2 = LegalizeOp(Node->getOperand(1));
940 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
941 Result = DAG.getNode(ISD::READPORT, Node->getValueType(0), Tmp1, Tmp2);
943 Result = SDOperand(Node, 0);
944 // Since these produce two values, make sure to remember that we legalized
946 AddLegalizedOperand(SDOperand(Node, 0), Result);
947 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
948 return Result.getValue(Op.ResNo);
950 Tmp1 = LegalizeOp(Node->getOperand(0));
951 Tmp2 = LegalizeOp(Node->getOperand(1));
952 Tmp3 = LegalizeOp(Node->getOperand(2));
953 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
954 Tmp3 != Node->getOperand(2))
955 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
959 Tmp1 = LegalizeOp(Node->getOperand(0));
960 Tmp2 = LegalizeOp(Node->getOperand(1));
962 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
963 case TargetLowering::Custom:
964 default: assert(0 && "This action not implemented for this operation!");
965 case TargetLowering::Legal:
966 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
967 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0),
970 Result = SDOperand(Node, 0);
972 case TargetLowering::Expand:
973 // Replace this with a load from memory.
974 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0),
975 Node->getOperand(1), DAG.getSrcValue(NULL));
976 Result = LegalizeOp(Result);
980 // Since these produce two values, make sure to remember that we legalized
982 AddLegalizedOperand(SDOperand(Node, 0), Result);
983 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
984 return Result.getValue(Op.ResNo);
987 Tmp1 = LegalizeOp(Node->getOperand(0));
988 Tmp2 = LegalizeOp(Node->getOperand(1));
989 Tmp3 = LegalizeOp(Node->getOperand(2));
991 switch (TLI.getOperationAction(Node->getOpcode(),
992 Node->getOperand(1).getValueType())) {
993 case TargetLowering::Custom:
994 default: assert(0 && "This action not implemented for this operation!");
995 case TargetLowering::Legal:
996 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
997 Tmp3 != Node->getOperand(2))
998 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1000 case TargetLowering::Expand:
1001 // Replace this with a store to memory.
1002 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0),
1003 Node->getOperand(1), Node->getOperand(2),
1004 DAG.getSrcValue(NULL));
1005 Result = LegalizeOp(Result);
1010 case ISD::ADD_PARTS:
1011 case ISD::SUB_PARTS:
1012 case ISD::SHL_PARTS:
1013 case ISD::SRA_PARTS:
1014 case ISD::SRL_PARTS: {
1015 std::vector<SDOperand> Ops;
1016 bool Changed = false;
1017 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1018 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1019 Changed |= Ops.back() != Node->getOperand(i);
1022 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops);
1024 // Since these produce multiple values, make sure to remember that we
1025 // legalized all of them.
1026 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1027 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
1028 return Result.getValue(Op.ResNo);
1045 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1046 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1047 if (Tmp1 != Node->getOperand(0) ||
1048 Tmp2 != Node->getOperand(1))
1049 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
1054 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1055 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1056 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1057 case TargetLowering::Legal:
1058 if (Tmp1 != Node->getOperand(0) ||
1059 Tmp2 != Node->getOperand(1))
1060 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
1063 case TargetLowering::Promote:
1064 case TargetLowering::Custom:
1065 assert(0 && "Cannot promote/custom handle this yet!");
1066 case TargetLowering::Expand: {
1067 MVT::ValueType VT = Node->getValueType(0);
1068 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
1069 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
1070 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
1071 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
1080 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
1081 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1082 case TargetLowering::Legal:
1083 if (Tmp1 != Node->getOperand(0))
1084 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1086 case TargetLowering::Promote: {
1087 MVT::ValueType OVT = Tmp1.getValueType();
1088 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1090 // Zero extend the argument.
1091 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
1092 // Perform the larger operation, then subtract if needed.
1093 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1094 switch(Node->getOpcode())
1100 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
1101 Tmp2 = DAG.getSetCC(ISD::SETEQ, MVT::i1, Tmp1,
1102 DAG.getConstant(getSizeInBits(NVT), NVT));
1103 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
1104 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
1107 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
1108 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
1109 DAG.getConstant(getSizeInBits(NVT) -
1110 getSizeInBits(OVT), NVT));
1115 case TargetLowering::Custom:
1116 assert(0 && "Cannot custom handle this yet!");
1117 case TargetLowering::Expand:
1118 switch(Node->getOpcode())
1121 static const uint64_t mask[6] = {
1122 0x5555555555555555ULL, 0x3333333333333333ULL,
1123 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
1124 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
1126 MVT::ValueType VT = Tmp1.getValueType();
1127 MVT::ValueType ShVT = TLI.getShiftAmountTy();
1128 unsigned len = getSizeInBits(VT);
1129 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
1130 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
1131 Tmp2 = DAG.getConstant(mask[i], VT);
1132 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
1133 Tmp1 = DAG.getNode(ISD::ADD, VT,
1134 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2),
1135 DAG.getNode(ISD::AND, VT,
1136 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3),
1143 /* for now, we do this:
1148 x = x | (x >>32); // for 64-bit input
1149 return popcount(~x);
1151 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */
1152 MVT::ValueType VT = Tmp1.getValueType();
1153 MVT::ValueType ShVT = TLI.getShiftAmountTy();
1154 unsigned len = getSizeInBits(VT);
1155 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
1156 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
1157 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1,
1158 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3));
1160 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT));
1161 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
1165 // for now, we use: { return popcount(~x & (x - 1)); }
1166 // unless the target has ctlz but not ctpop, in which case we use:
1167 // { return 32 - nlz(~x & (x-1)); }
1168 // see also http://www.hackersdelight.org/HDcode/ntz.cc
1169 MVT::ValueType VT = Tmp1.getValueType();
1170 Tmp2 = DAG.getConstant(~0ULL, VT);
1171 Tmp3 = DAG.getNode(ISD::AND, VT,
1172 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2),
1173 DAG.getNode(ISD::SUB, VT, Tmp1,
1174 DAG.getConstant(1, VT)));
1175 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead
1176 if (TLI.getOperationAction(ISD::CTPOP, VT) != TargetLowering::Legal &&
1177 TLI.getOperationAction(ISD::CTLZ, VT) == TargetLowering::Legal) {
1178 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT,
1179 DAG.getConstant(getSizeInBits(VT), VT),
1180 DAG.getNode(ISD::CTLZ, VT, Tmp3)));
1182 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
1187 assert(0 && "Cannot expand this yet!");
1200 Tmp1 = LegalizeOp(Node->getOperand(0));
1201 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1202 case TargetLowering::Legal:
1203 if (Tmp1 != Node->getOperand(0))
1204 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1206 case TargetLowering::Promote:
1207 case TargetLowering::Custom:
1208 assert(0 && "Cannot promote/custom handle this yet!");
1209 case TargetLowering::Expand:
1210 switch(Node->getOpcode()) {
1212 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
1213 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
1214 Result = LegalizeOp(DAG.getNode(ISD::SUB, Node->getValueType(0),
1219 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
1220 MVT::ValueType VT = Node->getValueType(0);
1221 Tmp2 = DAG.getConstantFP(0.0, VT);
1222 Tmp2 = DAG.getSetCC(ISD::SETUGT, TLI.getSetCCResultTy(), Tmp1, Tmp2);
1223 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
1224 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
1225 Result = LegalizeOp(Result);
1231 MVT::ValueType VT = Node->getValueType(0);
1232 Type *T = VT == MVT::f32 ? Type::FloatTy : Type::DoubleTy;
1233 const char *FnName = 0;
1234 switch(Node->getOpcode()) {
1235 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
1236 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
1237 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
1238 default: assert(0 && "Unreachable!");
1240 std::vector<std::pair<SDOperand, const Type*> > Args;
1241 Args.push_back(std::make_pair(Tmp1, T));
1242 // FIXME: should use ExpandLibCall!
1243 std::pair<SDOperand,SDOperand> CallResult =
1244 TLI.LowerCallTo(DAG.getEntryNode(), T, false,
1245 DAG.getExternalSymbol(FnName, VT), Args, DAG);
1246 Result = LegalizeOp(CallResult.first);
1250 assert(0 && "Unreachable!");
1256 // Conversion operators. The source and destination have different types.
1257 case ISD::ZERO_EXTEND:
1258 case ISD::SIGN_EXTEND:
1260 case ISD::FP_EXTEND:
1262 case ISD::FP_TO_SINT:
1263 case ISD::FP_TO_UINT:
1264 case ISD::SINT_TO_FP:
1265 case ISD::UINT_TO_FP:
1266 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1268 Tmp1 = LegalizeOp(Node->getOperand(0));
1269 if (Tmp1 != Node->getOperand(0))
1270 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1273 if (Node->getOpcode() == ISD::SINT_TO_FP ||
1274 Node->getOpcode() == ISD::UINT_TO_FP) {
1275 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
1276 Node->getValueType(0), Node->getOperand(0));
1278 } else if (Node->getOpcode() == ISD::TRUNCATE) {
1279 // In the expand case, we must be dealing with a truncate, because
1280 // otherwise the result would be larger than the source.
1281 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1283 // Since the result is legal, we should just be able to truncate the low
1284 // part of the source.
1285 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
1288 assert(0 && "Shouldn't need to expand other operators here!");
1291 switch (Node->getOpcode()) {
1292 case ISD::ZERO_EXTEND:
1293 Result = PromoteOp(Node->getOperand(0));
1294 // NOTE: Any extend would work here...
1295 Result = DAG.getNode(ISD::ZERO_EXTEND, Op.getValueType(), Result);
1296 Result = DAG.getZeroExtendInReg(Result,
1297 Node->getOperand(0).getValueType());
1299 case ISD::SIGN_EXTEND:
1300 Result = PromoteOp(Node->getOperand(0));
1301 // NOTE: Any extend would work here...
1302 Result = DAG.getNode(ISD::ZERO_EXTEND, Op.getValueType(), Result);
1303 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1304 Result, Node->getOperand(0).getValueType());
1307 Result = PromoteOp(Node->getOperand(0));
1308 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
1310 case ISD::FP_EXTEND:
1311 Result = PromoteOp(Node->getOperand(0));
1312 if (Result.getValueType() != Op.getValueType())
1313 // Dynamically dead while we have only 2 FP types.
1314 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
1317 case ISD::FP_TO_SINT:
1318 case ISD::FP_TO_UINT:
1319 Result = PromoteOp(Node->getOperand(0));
1320 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
1322 case ISD::SINT_TO_FP:
1323 Result = PromoteOp(Node->getOperand(0));
1324 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1325 Result, Node->getOperand(0).getValueType());
1326 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result);
1328 case ISD::UINT_TO_FP:
1329 Result = PromoteOp(Node->getOperand(0));
1330 Result = DAG.getZeroExtendInReg(Result,
1331 Node->getOperand(0).getValueType());
1332 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result);
1337 case ISD::FP_ROUND_INREG:
1338 case ISD::SIGN_EXTEND_INREG: {
1339 Tmp1 = LegalizeOp(Node->getOperand(0));
1340 MVT::ValueType ExtraVT = cast<MVTSDNode>(Node)->getExtraValueType();
1342 // If this operation is not supported, convert it to a shl/shr or load/store
1344 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
1345 default: assert(0 && "This action not supported for this op yet!");
1346 case TargetLowering::Legal:
1347 if (Tmp1 != Node->getOperand(0))
1348 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
1351 case TargetLowering::Expand:
1352 // If this is an integer extend and shifts are supported, do that.
1353 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
1354 // NOTE: we could fall back on load/store here too for targets without
1355 // SAR. However, it is doubtful that any exist.
1356 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
1357 MVT::getSizeInBits(ExtraVT);
1358 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
1359 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
1360 Node->getOperand(0), ShiftCst);
1361 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
1363 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
1364 // The only way we can lower this is to turn it into a STORETRUNC,
1365 // EXTLOAD pair, targetting a temporary location (a stack slot).
1367 // NOTE: there is a choice here between constantly creating new stack
1368 // slots and always reusing the same one. We currently always create
1369 // new ones, as reuse may inhibit scheduling.
1370 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
1371 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
1372 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
1373 MachineFunction &MF = DAG.getMachineFunction();
1375 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
1376 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
1377 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
1378 Node->getOperand(0), StackSlot,
1379 DAG.getSrcValue(NULL), ExtraVT);
1380 Result = DAG.getNode(ISD::EXTLOAD, Node->getValueType(0),
1381 Result, StackSlot, DAG.getSrcValue(NULL), ExtraVT);
1383 assert(0 && "Unknown op");
1385 Result = LegalizeOp(Result);
1392 if (!Op.Val->hasOneUse())
1393 AddLegalizedOperand(Op, Result);
1398 /// PromoteOp - Given an operation that produces a value in an invalid type,
1399 /// promote it to compute the value into a larger type. The produced value will
1400 /// have the correct bits for the low portion of the register, but no guarantee
1401 /// is made about the top bits: it may be zero, sign-extended, or garbage.
1402 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
1403 MVT::ValueType VT = Op.getValueType();
1404 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
1405 assert(getTypeAction(VT) == Promote &&
1406 "Caller should expand or legalize operands that are not promotable!");
1407 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
1408 "Cannot promote to smaller type!");
1410 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
1411 if (I != PromotedNodes.end()) return I->second;
1413 SDOperand Tmp1, Tmp2, Tmp3;
1416 SDNode *Node = Op.Val;
1418 // Promotion needs an optimization step to clean up after it, and is not
1419 // careful to avoid operations the target does not support. Make sure that
1420 // all generated operations are legalized in the next iteration.
1421 NeedsAnotherIteration = true;
1423 switch (Node->getOpcode()) {
1425 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
1426 assert(0 && "Do not know how to promote this operator!");
1429 Result = DAG.getNode(ISD::UNDEF, NVT);
1432 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
1433 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
1435 case ISD::ConstantFP:
1436 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
1437 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
1439 case ISD::CopyFromReg:
1440 Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(), NVT,
1441 Node->getOperand(0));
1442 // Remember that we legalized the chain.
1443 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1447 assert(getTypeAction(TLI.getSetCCResultTy()) == Legal &&
1448 "SetCC type is not legal??");
1449 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
1450 TLI.getSetCCResultTy(), Node->getOperand(0),
1451 Node->getOperand(1));
1452 Result = LegalizeOp(Result);
1456 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1458 Result = LegalizeOp(Node->getOperand(0));
1459 assert(Result.getValueType() >= NVT &&
1460 "This truncation doesn't make sense!");
1461 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
1462 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
1465 // The truncation is not required, because we don't guarantee anything
1466 // about high bits anyway.
1467 Result = PromoteOp(Node->getOperand(0));
1470 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1471 // Truncate the low part of the expanded value to the result type
1472 Result = DAG.getNode(ISD::TRUNCATE, VT, Tmp1);
1475 case ISD::SIGN_EXTEND:
1476 case ISD::ZERO_EXTEND:
1477 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1478 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
1480 // Input is legal? Just do extend all the way to the larger type.
1481 Result = LegalizeOp(Node->getOperand(0));
1482 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
1485 // Promote the reg if it's smaller.
1486 Result = PromoteOp(Node->getOperand(0));
1487 // The high bits are not guaranteed to be anything. Insert an extend.
1488 if (Node->getOpcode() == ISD::SIGN_EXTEND)
1489 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
1490 Node->getOperand(0).getValueType());
1492 Result = DAG.getZeroExtendInReg(Result,
1493 Node->getOperand(0).getValueType());
1498 case ISD::FP_EXTEND:
1499 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
1501 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1502 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
1503 case Promote: assert(0 && "Unreachable with 2 FP types!");
1505 // Input is legal? Do an FP_ROUND_INREG.
1506 Result = LegalizeOp(Node->getOperand(0));
1507 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT);
1512 case ISD::SINT_TO_FP:
1513 case ISD::UINT_TO_FP:
1514 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1516 Result = LegalizeOp(Node->getOperand(0));
1517 // No extra round required here.
1518 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
1522 Result = PromoteOp(Node->getOperand(0));
1523 if (Node->getOpcode() == ISD::SINT_TO_FP)
1524 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1525 Result, Node->getOperand(0).getValueType());
1527 Result = DAG.getZeroExtendInReg(Result,
1528 Node->getOperand(0).getValueType());
1529 // No extra round required here.
1530 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
1533 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
1534 Node->getOperand(0));
1535 // Round if we cannot tolerate excess precision.
1536 if (NoExcessFPPrecision)
1537 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT);
1542 case ISD::FP_TO_SINT:
1543 case ISD::FP_TO_UINT:
1544 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1546 Tmp1 = LegalizeOp(Node->getOperand(0));
1549 // The input result is prerounded, so we don't have to do anything
1551 Tmp1 = PromoteOp(Node->getOperand(0));
1554 assert(0 && "not implemented");
1556 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
1561 Tmp1 = PromoteOp(Node->getOperand(0));
1562 assert(Tmp1.getValueType() == NVT);
1563 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
1564 // NOTE: we do not have to do any extra rounding here for
1565 // NoExcessFPPrecision, because we know the input will have the appropriate
1566 // precision, and these operations don't modify precision at all.
1572 Tmp1 = PromoteOp(Node->getOperand(0));
1573 assert(Tmp1.getValueType() == NVT);
1574 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
1575 if(NoExcessFPPrecision)
1576 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT);
1585 // The input may have strange things in the top bits of the registers, but
1586 // these operations don't care. They may have wierd bits going out, but
1587 // that too is okay if they are integer operations.
1588 Tmp1 = PromoteOp(Node->getOperand(0));
1589 Tmp2 = PromoteOp(Node->getOperand(1));
1590 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
1591 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
1593 // However, if this is a floating point operation, they will give excess
1594 // precision that we may not be able to tolerate. If we DO allow excess
1595 // precision, just leave it, otherwise excise it.
1596 // FIXME: Why would we need to round FP ops more than integer ones?
1597 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
1598 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
1599 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT);
1604 // These operators require that their input be sign extended.
1605 Tmp1 = PromoteOp(Node->getOperand(0));
1606 Tmp2 = PromoteOp(Node->getOperand(1));
1607 if (MVT::isInteger(NVT)) {
1608 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT);
1609 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, VT);
1611 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
1613 // Perform FP_ROUND: this is probably overly pessimistic.
1614 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
1615 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT);
1620 // These operators require that their input be zero extended.
1621 Tmp1 = PromoteOp(Node->getOperand(0));
1622 Tmp2 = PromoteOp(Node->getOperand(1));
1623 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
1624 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
1625 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
1626 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
1630 Tmp1 = PromoteOp(Node->getOperand(0));
1631 Tmp2 = LegalizeOp(Node->getOperand(1));
1632 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2);
1635 // The input value must be properly sign extended.
1636 Tmp1 = PromoteOp(Node->getOperand(0));
1637 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT);
1638 Tmp2 = LegalizeOp(Node->getOperand(1));
1639 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2);
1642 // The input value must be properly zero extended.
1643 Tmp1 = PromoteOp(Node->getOperand(0));
1644 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
1645 Tmp2 = LegalizeOp(Node->getOperand(1));
1646 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2);
1649 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1650 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1651 // FIXME: When the DAG combiner exists, change this to use EXTLOAD!
1652 if (MVT::isInteger(NVT))
1653 Result = DAG.getNode(ISD::ZEXTLOAD, NVT, Tmp1, Tmp2, Node->getOperand(2),
1656 Result = DAG.getNode(ISD::EXTLOAD, NVT, Tmp1, Tmp2, Node->getOperand(2),
1659 // Remember that we legalized the chain.
1660 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1663 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1664 case Expand: assert(0 && "It's impossible to expand bools");
1666 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition.
1669 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1672 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
1673 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
1674 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3);
1677 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1678 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
1680 std::vector<SDOperand> Ops;
1681 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i)
1682 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1684 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
1685 "Can only promote single result calls");
1686 std::vector<MVT::ValueType> RetTyVTs;
1687 RetTyVTs.reserve(2);
1688 RetTyVTs.push_back(NVT);
1689 RetTyVTs.push_back(MVT::Other);
1690 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops);
1691 Result = SDOperand(NC, 0);
1693 // Insert the new chain mapping.
1694 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1700 Tmp1 = Node->getOperand(0);
1701 //Zero extend the argument
1702 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
1703 // Perform the larger operation, then subtract if needed.
1704 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
1705 switch(Node->getOpcode())
1711 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
1712 Tmp2 = DAG.getSetCC(ISD::SETEQ, MVT::i1, Tmp1,
1713 DAG.getConstant(getSizeInBits(NVT), NVT));
1714 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
1715 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1);
1718 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
1719 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
1720 DAG.getConstant(getSizeInBits(NVT) -
1721 getSizeInBits(VT), NVT));
1727 assert(Result.Val && "Didn't set a result!");
1728 AddPromotedOperand(Op, Result);
1732 /// ExpandAddSub - Find a clever way to expand this add operation into
1734 void SelectionDAGLegalize::
1735 ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
1736 SDOperand &Lo, SDOperand &Hi) {
1737 // Expand the subcomponents.
1738 SDOperand LHSL, LHSH, RHSL, RHSH;
1739 ExpandOp(LHS, LHSL, LHSH);
1740 ExpandOp(RHS, RHSL, RHSH);
1742 // FIXME: this should be moved to the dag combiner someday.
1743 if (NodeOp == ISD::ADD_PARTS || NodeOp == ISD::SUB_PARTS)
1744 if (LHSL.getValueType() == MVT::i32) {
1746 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHSL))
1747 if (C->getValue() == 0)
1749 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHSL))
1750 if (C->getValue() == 0)
1753 // Turn this into an add/sub of the high part only.
1755 DAG.getNode(NodeOp == ISD::ADD_PARTS ? ISD::ADD : ISD::SUB,
1756 LowEl.getValueType(), LHSH, RHSH);
1763 std::vector<SDOperand> Ops;
1764 Ops.push_back(LHSL);
1765 Ops.push_back(LHSH);
1766 Ops.push_back(RHSL);
1767 Ops.push_back(RHSH);
1768 Lo = DAG.getNode(NodeOp, LHSL.getValueType(), Ops);
1769 Hi = Lo.getValue(1);
1772 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
1773 SDOperand Op, SDOperand Amt,
1774 SDOperand &Lo, SDOperand &Hi) {
1775 // Expand the subcomponents.
1776 SDOperand LHSL, LHSH;
1777 ExpandOp(Op, LHSL, LHSH);
1779 std::vector<SDOperand> Ops;
1780 Ops.push_back(LHSL);
1781 Ops.push_back(LHSH);
1783 Lo = DAG.getNode(NodeOp, LHSL.getValueType(), Ops);
1784 Hi = Lo.getValue(1);
1788 /// ExpandShift - Try to find a clever way to expand this shift operation out to
1789 /// smaller elements. If we can't find a way that is more efficient than a
1790 /// libcall on this target, return false. Otherwise, return true with the
1791 /// low-parts expanded into Lo and Hi.
1792 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
1793 SDOperand &Lo, SDOperand &Hi) {
1794 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
1795 "This is not a shift!");
1797 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
1798 SDOperand ShAmt = LegalizeOp(Amt);
1799 MVT::ValueType ShTy = ShAmt.getValueType();
1800 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
1801 unsigned NVTBits = MVT::getSizeInBits(NVT);
1803 // Handle the case when Amt is an immediate. Other cases are currently broken
1804 // and are disabled.
1805 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
1806 unsigned Cst = CN->getValue();
1807 // Expand the incoming operand to be shifted, so that we have its parts
1809 ExpandOp(Op, InL, InH);
1813 Lo = DAG.getConstant(0, NVT);
1814 Hi = DAG.getConstant(0, NVT);
1815 } else if (Cst > NVTBits) {
1816 Lo = DAG.getConstant(0, NVT);
1817 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
1818 } else if (Cst == NVTBits) {
1819 Lo = DAG.getConstant(0, NVT);
1822 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
1823 Hi = DAG.getNode(ISD::OR, NVT,
1824 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
1825 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
1830 Lo = DAG.getConstant(0, NVT);
1831 Hi = DAG.getConstant(0, NVT);
1832 } else if (Cst > NVTBits) {
1833 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
1834 Hi = DAG.getConstant(0, NVT);
1835 } else if (Cst == NVTBits) {
1837 Hi = DAG.getConstant(0, NVT);
1839 Lo = DAG.getNode(ISD::OR, NVT,
1840 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
1841 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
1842 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
1847 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
1848 DAG.getConstant(NVTBits-1, ShTy));
1849 } else if (Cst > NVTBits) {
1850 Lo = DAG.getNode(ISD::SRA, NVT, InH,
1851 DAG.getConstant(Cst-NVTBits, ShTy));
1852 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1853 DAG.getConstant(NVTBits-1, ShTy));
1854 } else if (Cst == NVTBits) {
1856 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1857 DAG.getConstant(NVTBits-1, ShTy));
1859 Lo = DAG.getNode(ISD::OR, NVT,
1860 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
1861 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
1862 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
1867 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy,
1868 // so disable it for now. Currently targets are handling this via SHL_PARTS
1872 // If we have an efficient select operation (or if the selects will all fold
1873 // away), lower to some complex code, otherwise just emit the libcall.
1874 if (TLI.getOperationAction(ISD::SELECT, NVT) != TargetLowering::Legal &&
1875 !isa<ConstantSDNode>(Amt))
1879 ExpandOp(Op, InL, InH);
1880 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt
1881 DAG.getConstant(NVTBits, ShTy), ShAmt);
1883 // Compare the unmasked shift amount against 32.
1884 SDOperand Cond = DAG.getSetCC(ISD::SETGE, TLI.getSetCCResultTy(), ShAmt,
1885 DAG.getConstant(NVTBits, ShTy));
1887 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) {
1888 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31
1889 DAG.getConstant(NVTBits-1, ShTy));
1890 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31
1891 DAG.getConstant(NVTBits-1, ShTy));
1894 if (Opc == ISD::SHL) {
1895 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt)
1896 DAG.getNode(ISD::SHL, NVT, InH, ShAmt),
1897 DAG.getNode(ISD::SRL, NVT, InL, NAmt));
1898 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31
1900 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
1901 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2);
1903 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT,
1904 DAG.getSetCC(ISD::SETEQ,
1905 TLI.getSetCCResultTy(), NAmt,
1906 DAG.getConstant(32, ShTy)),
1907 DAG.getConstant(0, NVT),
1908 DAG.getNode(ISD::SHL, NVT, InH, NAmt));
1909 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt)
1911 DAG.getNode(ISD::SRL, NVT, InL, ShAmt));
1912 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31
1915 if (Opc == ISD::SRA)
1916 HiPart = DAG.getNode(ISD::SRA, NVT, InH,
1917 DAG.getConstant(NVTBits-1, ShTy));
1919 HiPart = DAG.getConstant(0, NVT);
1920 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
1921 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2);
1926 /// FindLatestAdjCallStackDown - Scan up the dag to find the latest (highest
1927 /// NodeDepth) node that is an AdjCallStackDown operation and occurs later than
1929 static void FindLatestAdjCallStackDown(SDNode *Node, SDNode *&Found) {
1930 if (Node->getNodeDepth() <= Found->getNodeDepth()) return;
1932 // If we found an ADJCALLSTACKDOWN, we already know this node occurs later
1933 // than the Found node. Just remember this node and return.
1934 if (Node->getOpcode() == ISD::ADJCALLSTACKDOWN) {
1939 // Otherwise, scan the operands of Node to see if any of them is a call.
1940 assert(Node->getNumOperands() != 0 &&
1941 "All leaves should have depth equal to the entry node!");
1942 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i)
1943 FindLatestAdjCallStackDown(Node->getOperand(i).Val, Found);
1945 // Tail recurse for the last iteration.
1946 FindLatestAdjCallStackDown(Node->getOperand(Node->getNumOperands()-1).Val,
1951 /// FindEarliestAdjCallStackUp - Scan down the dag to find the earliest (lowest
1952 /// NodeDepth) node that is an AdjCallStackUp operation and occurs more recent
1954 static void FindEarliestAdjCallStackUp(SDNode *Node, SDNode *&Found) {
1955 if (Found && Node->getNodeDepth() >= Found->getNodeDepth()) return;
1957 // If we found an ADJCALLSTACKUP, we already know this node occurs earlier
1958 // than the Found node. Just remember this node and return.
1959 if (Node->getOpcode() == ISD::ADJCALLSTACKUP) {
1964 // Otherwise, scan the operands of Node to see if any of them is a call.
1965 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
1966 if (UI == E) return;
1967 for (--E; UI != E; ++UI)
1968 FindEarliestAdjCallStackUp(*UI, Found);
1970 // Tail recurse for the last iteration.
1971 FindEarliestAdjCallStackUp(*UI, Found);
1974 /// FindAdjCallStackUp - Given a chained node that is part of a call sequence,
1975 /// find the ADJCALLSTACKUP node that terminates the call sequence.
1976 static SDNode *FindAdjCallStackUp(SDNode *Node) {
1977 if (Node->getOpcode() == ISD::ADJCALLSTACKUP)
1979 if (Node->use_empty())
1980 return 0; // No adjcallstackup
1982 if (Node->hasOneUse()) // Simple case, only has one user to check.
1983 return FindAdjCallStackUp(*Node->use_begin());
1985 SDOperand TheChain(Node, Node->getNumValues()-1);
1986 assert(TheChain.getValueType() == MVT::Other && "Is not a token chain!");
1988 for (SDNode::use_iterator UI = Node->use_begin(),
1989 E = Node->use_end(); ; ++UI) {
1990 assert(UI != E && "Didn't find a user of the tokchain, no ADJCALLSTACKUP!");
1992 // Make sure to only follow users of our token chain.
1994 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
1995 if (User->getOperand(i) == TheChain)
1996 return FindAdjCallStackUp(User);
1998 assert(0 && "Unreachable");
2002 /// FindAdjCallStackDown - Given a chained node that is part of a call sequence,
2003 /// find the ADJCALLSTACKDOWN node that initiates the call sequence.
2004 static SDNode *FindAdjCallStackDown(SDNode *Node) {
2005 assert(Node && "Didn't find adjcallstackdown for a call??");
2006 if (Node->getOpcode() == ISD::ADJCALLSTACKDOWN) return Node;
2008 assert(Node->getOperand(0).getValueType() == MVT::Other &&
2009 "Node doesn't have a token chain argument!");
2010 return FindAdjCallStackDown(Node->getOperand(0).Val);
2014 /// FindInputOutputChains - If we are replacing an operation with a call we need
2015 /// to find the call that occurs before and the call that occurs after it to
2016 /// properly serialize the calls in the block. The returned operand is the
2017 /// input chain value for the new call (e.g. the entry node or the previous
2018 /// call), and OutChain is set to be the chain node to update to point to the
2019 /// end of the call chain.
2020 static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain,
2022 SDNode *LatestAdjCallStackDown = Entry.Val;
2023 SDNode *LatestAdjCallStackUp = 0;
2024 FindLatestAdjCallStackDown(OpNode, LatestAdjCallStackDown);
2025 //std::cerr<<"Found node: "; LatestAdjCallStackDown->dump(); std::cerr <<"\n";
2027 // It is possible that no ISD::ADJCALLSTACKDOWN was found because there is no
2028 // previous call in the function. LatestCallStackDown may in that case be
2029 // the entry node itself. Do not attempt to find a matching ADJCALLSTACKUP
2030 // unless LatestCallStackDown is an ADJCALLSTACKDOWN.
2031 if (LatestAdjCallStackDown->getOpcode() == ISD::ADJCALLSTACKDOWN)
2032 LatestAdjCallStackUp = FindAdjCallStackUp(LatestAdjCallStackDown);
2034 LatestAdjCallStackUp = Entry.Val;
2035 assert(LatestAdjCallStackUp && "NULL return from FindAdjCallStackUp");
2037 // Finally, find the first call that this must come before, first we find the
2038 // adjcallstackup that ends the call.
2040 FindEarliestAdjCallStackUp(OpNode, OutChain);
2042 // If we found one, translate from the adj up to the adjdown.
2044 OutChain = FindAdjCallStackDown(OutChain);
2046 return SDOperand(LatestAdjCallStackUp, 0);
2049 /// SpliceCallInto - Given the result chain of a libcall (CallResult), and a
2050 void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult,
2052 // Nothing to splice it into?
2053 if (OutChain == 0) return;
2055 assert(OutChain->getOperand(0).getValueType() == MVT::Other);
2058 // Form a token factor node merging the old inval and the new inval.
2059 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult,
2060 OutChain->getOperand(0));
2061 // Change the node to refer to the new token.
2062 OutChain->setAdjCallChain(InToken);
2066 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
2067 // does not fit into a register, return the lo part and set the hi part to the
2068 // by-reg argument. If it does fit into a single register, return the result
2069 // and leave the Hi part unset.
2070 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
2073 SDOperand InChain = FindInputOutputChains(Node, OutChain,
2074 DAG.getEntryNode());
2075 if (InChain.Val == 0)
2076 InChain = DAG.getEntryNode();
2078 TargetLowering::ArgListTy Args;
2079 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2080 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
2081 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
2082 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
2084 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
2086 // Splice the libcall in wherever FindInputOutputChains tells us to.
2087 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
2088 std::pair<SDOperand,SDOperand> CallInfo =
2089 TLI.LowerCallTo(InChain, RetTy, false, Callee, Args, DAG);
2090 SpliceCallInto(CallInfo.second, OutChain);
2092 NeedsAnotherIteration = true;
2094 switch (getTypeAction(CallInfo.first.getValueType())) {
2095 default: assert(0 && "Unknown thing");
2097 return CallInfo.first;
2099 assert(0 && "Cannot promote this yet!");
2102 ExpandOp(CallInfo.first, Lo, Hi);
2108 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
2109 /// destination type is legal.
2110 SDOperand SelectionDAGLegalize::
2111 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
2112 assert(getTypeAction(DestTy) == Legal && "Destination type is not legal!");
2113 assert(getTypeAction(Source.getValueType()) == Expand &&
2114 "This is not an expansion!");
2115 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
2118 // If this is unsigned, and not supported, first perform the conversion to
2119 // signed, then adjust the result if the sign bit is set.
2120 SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source);
2122 assert(Source.getValueType() == MVT::i64 &&
2123 "This only works for 64-bit -> FP");
2124 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
2125 // incoming integer is set. To handle this, we dynamically test to see if
2126 // it is set, and, if so, add a fudge factor.
2128 ExpandOp(Source, Lo, Hi);
2130 SDOperand SignSet = DAG.getSetCC(ISD::SETLT, TLI.getSetCCResultTy(), Hi,
2131 DAG.getConstant(0, Hi.getValueType()));
2132 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
2133 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
2134 SignSet, Four, Zero);
2135 // FIXME: This is almost certainly broken for big-endian systems. Should
2136 // this just put the fudge factor in the low bits of the uint64 constant or?
2137 static Constant *FudgeFactor =
2138 ConstantUInt::get(Type::ULongTy, 0x5f800000ULL << 32);
2140 MachineConstantPool *CP = DAG.getMachineFunction().getConstantPool();
2141 SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(FudgeFactor),
2142 TLI.getPointerTy());
2143 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
2144 SDOperand FudgeInReg;
2145 if (DestTy == MVT::f32)
2146 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
2147 DAG.getSrcValue(NULL));
2149 assert(DestTy == MVT::f64 && "Unexpected conversion");
2150 FudgeInReg = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
2151 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
2153 return DAG.getNode(ISD::ADD, DestTy, SignedConv, FudgeInReg);
2156 // Expand the source, then glue it back together for the call. We must expand
2157 // the source in case it is shared (this pass of legalize must traverse it).
2158 SDOperand SrcLo, SrcHi;
2159 ExpandOp(Source, SrcLo, SrcHi);
2160 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
2162 SDNode *OutChain = 0;
2163 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain,
2164 DAG.getEntryNode());
2165 const char *FnName = 0;
2166 if (DestTy == MVT::f32)
2167 FnName = "__floatdisf";
2169 assert(DestTy == MVT::f64 && "Unknown fp value type!");
2170 FnName = "__floatdidf";
2173 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy());
2175 TargetLowering::ArgListTy Args;
2176 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType());
2178 Args.push_back(std::make_pair(Source, ArgTy));
2180 // We don't care about token chains for libcalls. We just use the entry
2181 // node as our input and ignore the output chain. This allows us to place
2182 // calls wherever we need them to satisfy data dependences.
2183 const Type *RetTy = MVT::getTypeForValueType(DestTy);
2185 std::pair<SDOperand,SDOperand> CallResult =
2186 TLI.LowerCallTo(InChain, RetTy, false, Callee, Args, DAG);
2188 SpliceCallInto(CallResult.second, OutChain);
2189 return CallResult.first;
2194 /// ExpandOp - Expand the specified SDOperand into its two component pieces
2195 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
2196 /// LegalizeNodes map is filled in for any results that are not expanded, the
2197 /// ExpandedNodes map is filled in for any results that are expanded, and the
2198 /// Lo/Hi values are returned.
2199 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
2200 MVT::ValueType VT = Op.getValueType();
2201 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2202 SDNode *Node = Op.Val;
2203 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
2204 assert(MVT::isInteger(VT) && "Cannot expand FP values!");
2205 assert(MVT::isInteger(NVT) && NVT < VT &&
2206 "Cannot expand to FP value or to larger int value!");
2208 // If there is more than one use of this, see if we already expanded it.
2209 // There is no use remembering values that only have a single use, as the map
2210 // entries will never be reused.
2211 if (!Node->hasOneUse()) {
2212 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
2213 = ExpandedNodes.find(Op);
2214 if (I != ExpandedNodes.end()) {
2215 Lo = I->second.first;
2216 Hi = I->second.second;
2221 // Expanding to multiple registers needs to perform an optimization step, and
2222 // is not careful to avoid operations the target does not support. Make sure
2223 // that all generated operations are legalized in the next iteration.
2224 NeedsAnotherIteration = true;
2226 switch (Node->getOpcode()) {
2228 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2229 assert(0 && "Do not know how to expand this operator!");
2232 Lo = DAG.getNode(ISD::UNDEF, NVT);
2233 Hi = DAG.getNode(ISD::UNDEF, NVT);
2235 case ISD::Constant: {
2236 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
2237 Lo = DAG.getConstant(Cst, NVT);
2238 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
2242 case ISD::CopyFromReg: {
2243 unsigned Reg = cast<RegSDNode>(Node)->getReg();
2244 // Aggregate register values are always in consequtive pairs.
2245 Lo = DAG.getCopyFromReg(Reg, NVT, Node->getOperand(0));
2246 Hi = DAG.getCopyFromReg(Reg+1, NVT, Lo.getValue(1));
2248 // Remember that we legalized the chain.
2249 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
2251 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
2255 case ISD::BUILD_PAIR:
2256 // Legalize both operands. FIXME: in the future we should handle the case
2257 // where the two elements are not legal.
2258 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
2259 Lo = LegalizeOp(Node->getOperand(0));
2260 Hi = LegalizeOp(Node->getOperand(1));
2264 ExpandOp(Node->getOperand(0), Lo, Hi);
2265 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
2266 DAG.getNode(ISD::CTPOP, NVT, Lo),
2267 DAG.getNode(ISD::CTPOP, NVT, Hi));
2268 Hi = DAG.getConstant(0, NVT);
2273 assert(0 && "ct intrinsics cannot be expanded!");
2276 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2277 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2278 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
2280 // Increment the pointer to the other half.
2281 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
2282 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2283 getIntPtrConstant(IncrementSize));
2284 //Is this safe? declaring that the two parts of the split load
2285 //are from the same instruction?
2286 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
2288 // Build a factor node to remember that this load is independent of the
2290 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2293 // Remember that we legalized the chain.
2294 AddLegalizedOperand(Op.getValue(1), TF);
2295 if (!TLI.isLittleEndian())
2300 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2301 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
2303 bool Changed = false;
2304 std::vector<SDOperand> Ops;
2305 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
2306 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2307 Changed |= Ops.back() != Node->getOperand(i);
2310 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
2311 "Can only expand a call once so far, not i64 -> i16!");
2313 std::vector<MVT::ValueType> RetTyVTs;
2314 RetTyVTs.reserve(3);
2315 RetTyVTs.push_back(NVT);
2316 RetTyVTs.push_back(NVT);
2317 RetTyVTs.push_back(MVT::Other);
2318 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops);
2319 Lo = SDOperand(NC, 0);
2320 Hi = SDOperand(NC, 1);
2322 // Insert the new chain mapping.
2323 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2));
2328 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
2329 SDOperand LL, LH, RL, RH;
2330 ExpandOp(Node->getOperand(0), LL, LH);
2331 ExpandOp(Node->getOperand(1), RL, RH);
2332 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
2333 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
2337 SDOperand C, LL, LH, RL, RH;
2339 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2340 case Expand: assert(0 && "It's impossible to expand bools");
2342 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2345 C = PromoteOp(Node->getOperand(0)); // Promote the condition.
2348 ExpandOp(Node->getOperand(1), LL, LH);
2349 ExpandOp(Node->getOperand(2), RL, RH);
2350 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL);
2351 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH);
2354 case ISD::SIGN_EXTEND: {
2356 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2357 case Expand: assert(0 && "expand-expand not implemented yet!");
2358 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
2360 In = PromoteOp(Node->getOperand(0));
2361 // Emit the appropriate sign_extend_inreg to get the value we want.
2362 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In,
2363 Node->getOperand(0).getValueType());
2367 // The low part is just a sign extension of the input (which degenerates to
2369 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In);
2371 // The high part is obtained by SRA'ing all but one of the bits of the lo
2373 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
2374 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
2375 TLI.getShiftAmountTy()));
2378 case ISD::ZERO_EXTEND: {
2380 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2381 case Expand: assert(0 && "expand-expand not implemented yet!");
2382 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
2384 In = PromoteOp(Node->getOperand(0));
2385 // Emit the appropriate zero_extend_inreg to get the value we want.
2386 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType());
2390 // The low part is just a zero extension of the input (which degenerates to
2392 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In);
2394 // The high part is just a zero.
2395 Hi = DAG.getConstant(0, NVT);
2398 // These operators cannot be expanded directly, emit them as calls to
2399 // library functions.
2400 case ISD::FP_TO_SINT:
2401 if (Node->getOperand(0).getValueType() == MVT::f32)
2402 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
2404 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
2406 case ISD::FP_TO_UINT:
2407 if (Node->getOperand(0).getValueType() == MVT::f32)
2408 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
2410 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
2414 // If we can emit an efficient shift operation, do so now.
2415 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
2418 // If this target supports SHL_PARTS, use it.
2419 if (TLI.getOperationAction(ISD::SHL_PARTS, NVT) == TargetLowering::Legal) {
2420 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1),
2425 // Otherwise, emit a libcall.
2426 Lo = ExpandLibCall("__ashldi3", Node, Hi);
2430 // If we can emit an efficient shift operation, do so now.
2431 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
2434 // If this target supports SRA_PARTS, use it.
2435 if (TLI.getOperationAction(ISD::SRA_PARTS, NVT) == TargetLowering::Legal) {
2436 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1),
2441 // Otherwise, emit a libcall.
2442 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
2445 // If we can emit an efficient shift operation, do so now.
2446 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
2449 // If this target supports SRL_PARTS, use it.
2450 if (TLI.getOperationAction(ISD::SRL_PARTS, NVT) == TargetLowering::Legal) {
2451 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1),
2456 // Otherwise, emit a libcall.
2457 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
2461 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1),
2465 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1),
2469 if (TLI.getOperationAction(ISD::MULHU, NVT) == TargetLowering::Legal) {
2470 SDOperand LL, LH, RL, RH;
2471 ExpandOp(Node->getOperand(0), LL, LH);
2472 ExpandOp(Node->getOperand(1), RL, RH);
2473 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
2474 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
2475 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
2476 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
2477 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
2478 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
2480 Lo = ExpandLibCall("__muldi3" , Node, Hi); break;
2484 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
2485 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
2486 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
2487 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
2490 // Remember in a map if the values will be reused later.
2491 if (!Node->hasOneUse()) {
2492 bool isNew = ExpandedNodes.insert(std::make_pair(Op,
2493 std::make_pair(Lo, Hi))).second;
2494 assert(isNew && "Value already expanded?!?");
2499 // SelectionDAG::Legalize - This is the entry point for the file.
2501 void SelectionDAG::Legalize() {
2502 /// run - This is the main entry point to this class.
2504 SelectionDAGLegalize(*this).Run();