1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class VISIBILITY_HIDDEN SelectionDAGLegalize {
55 // Libcall insertion helpers.
57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
58 /// legalized. We use this to ensure that calls are properly serialized
59 /// against each other, including inserted libcalls.
60 SDValue LastCALLSEQ_END;
62 /// IsLegalizingCall - This member is used *only* for purposes of providing
63 /// helpful assertions that a libcall isn't created while another call is
64 /// being legalized (which could lead to non-serialized call sequences).
65 bool IsLegalizingCall;
68 Legal, // The target natively supports this operation.
69 Promote, // This operation should be executed in a larger type.
70 Expand // Try to expand this to other ops, otherwise use a libcall.
73 /// ValueTypeActions - This is a bitvector that contains two bits for each
74 /// value type, where the two bits correspond to the LegalizeAction enum.
75 /// This can be queried with "getTypeAction(VT)".
76 TargetLowering::ValueTypeActionImpl ValueTypeActions;
78 /// LegalizedNodes - For nodes that are of legal width, and that have more
79 /// than one use, this map indicates what regularized operand to use. This
80 /// allows us to avoid legalizing the same thing more than once.
81 DenseMap<SDValue, SDValue> LegalizedNodes;
83 /// PromotedNodes - For nodes that are below legal width, and that have more
84 /// than one use, this map indicates what promoted value to use. This allows
85 /// us to avoid promoting the same thing more than once.
86 DenseMap<SDValue, SDValue> PromotedNodes;
88 /// ExpandedNodes - For nodes that need to be expanded this map indicates
89 /// which which operands are the expanded version of the input. This allows
90 /// us to avoid expanding the same node more than once.
91 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
93 /// SplitNodes - For vector nodes that need to be split, this map indicates
94 /// which which operands are the split version of the input. This allows us
95 /// to avoid splitting the same node more than once.
96 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
98 /// ScalarizedNodes - For nodes that need to be converted from vector types to
99 /// scalar types, this contains the mapping of ones we have already
100 /// processed to the result.
101 std::map<SDValue, SDValue> ScalarizedNodes;
103 void AddLegalizedOperand(SDValue From, SDValue To) {
104 LegalizedNodes.insert(std::make_pair(From, To));
105 // If someone requests legalization of the new node, return itself.
107 LegalizedNodes.insert(std::make_pair(To, To));
109 void AddPromotedOperand(SDValue From, SDValue To) {
110 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
111 assert(isNew && "Got into the map somehow?");
112 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
117 explicit SelectionDAGLegalize(SelectionDAG &DAG);
119 /// getTypeAction - Return how we should legalize values of this type, either
120 /// it is already legal or we need to expand it into multiple registers of
121 /// smaller integer type, or we need to promote it to a larger type.
122 LegalizeAction getTypeAction(MVT VT) const {
123 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
126 /// isTypeLegal - Return true if this type is legal on this target.
128 bool isTypeLegal(MVT VT) const {
129 return getTypeAction(VT) == Legal;
135 /// HandleOp - Legalize, Promote, or Expand the specified operand as
136 /// appropriate for its type.
137 void HandleOp(SDValue Op);
139 /// LegalizeOp - We know that the specified value has a legal type.
140 /// Recursively ensure that the operands have legal types, then return the
142 SDValue LegalizeOp(SDValue O);
144 /// UnrollVectorOp - We know that the given vector has a legal type, however
145 /// the operation it performs is not legal and is an operation that we have
146 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
147 /// operating on each element individually.
148 SDValue UnrollVectorOp(SDValue O);
150 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
151 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
152 /// is necessary to spill the vector being inserted into to memory, perform
153 /// the insert there, and then read the result back.
154 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
157 /// PromoteOp - Given an operation that produces a value in an invalid type,
158 /// promote it to compute the value into a larger type. The produced value
159 /// will have the correct bits for the low portion of the register, but no
160 /// guarantee is made about the top bits: it may be zero, sign-extended, or
162 SDValue PromoteOp(SDValue O);
164 /// ExpandOp - Expand the specified SDValue into its two component pieces
165 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
166 /// the LegalizeNodes map is filled in for any results that are not expanded,
167 /// the ExpandedNodes map is filled in for any results that are expanded, and
168 /// the Lo/Hi values are returned. This applies to integer types and Vector
170 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
172 /// SplitVectorOp - Given an operand of vector type, break it down into
173 /// two smaller values.
174 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
176 /// ScalarizeVectorOp - Given an operand of single-element vector type
177 /// (e.g. v1f32), convert it into the equivalent operation that returns a
178 /// scalar (e.g. f32) value.
179 SDValue ScalarizeVectorOp(SDValue O);
181 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
182 /// specified mask and type. Targets can specify exactly which masks they
183 /// support and the code generator is tasked with not creating illegal masks.
185 /// Note that this will also return true for shuffles that are promoted to a
188 /// If this is a legal shuffle, this method returns the (possibly promoted)
189 /// build_vector Mask. If it's not a legal shuffle, it returns null.
190 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
192 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
193 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
195 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC);
197 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
199 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source);
201 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT);
202 SDValue ExpandBUILD_VECTOR(SDNode *Node);
203 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
204 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op);
205 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT);
206 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned);
207 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned);
209 SDValue ExpandBSWAP(SDValue Op);
210 SDValue ExpandBitCount(unsigned Opc, SDValue Op);
211 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
212 SDValue &Lo, SDValue &Hi);
213 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
214 SDValue &Lo, SDValue &Hi);
216 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
217 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
221 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
222 /// specified mask and type. Targets can specify exactly which masks they
223 /// support and the code generator is tasked with not creating illegal masks.
225 /// Note that this will also return true for shuffles that are promoted to a
227 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
228 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
230 case TargetLowering::Legal:
231 case TargetLowering::Custom:
233 case TargetLowering::Promote: {
234 // If this is promoted to a different type, convert the shuffle mask and
235 // ask if it is legal in the promoted type!
236 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
237 MVT EltVT = NVT.getVectorElementType();
239 // If we changed # elements, change the shuffle mask.
240 unsigned NumEltsGrowth =
241 NVT.getVectorNumElements() / VT.getVectorNumElements();
242 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
243 if (NumEltsGrowth > 1) {
244 // Renumber the elements.
245 SmallVector<SDValue, 8> Ops;
246 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
247 SDValue InOp = Mask.getOperand(i);
248 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
249 if (InOp.getOpcode() == ISD::UNDEF)
250 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
252 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
253 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
257 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
263 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
266 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
267 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
268 ValueTypeActions(TLI.getValueTypeActions()) {
269 assert(MVT::LAST_VALUETYPE <= 32 &&
270 "Too many value types for ValueTypeActions to hold!");
273 void SelectionDAGLegalize::LegalizeDAG() {
274 LastCALLSEQ_END = DAG.getEntryNode();
275 IsLegalizingCall = false;
277 // The legalize process is inherently a bottom-up recursive process (users
278 // legalize their uses before themselves). Given infinite stack space, we
279 // could just start legalizing on the root and traverse the whole graph. In
280 // practice however, this causes us to run out of stack space on large basic
281 // blocks. To avoid this problem, compute an ordering of the nodes where each
282 // node is only legalized after all of its operands are legalized.
283 std::vector<SDNode *> TopOrder;
284 unsigned N = DAG.AssignTopologicalOrder(TopOrder);
285 for (unsigned i = N; i != 0; --i)
286 HandleOp(SDValue(TopOrder[i-1], 0));
289 // Finally, it's possible the root changed. Get the new root.
290 SDValue OldRoot = DAG.getRoot();
291 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
292 DAG.setRoot(LegalizedNodes[OldRoot]);
294 ExpandedNodes.clear();
295 LegalizedNodes.clear();
296 PromotedNodes.clear();
298 ScalarizedNodes.clear();
300 // Remove dead nodes now.
301 DAG.RemoveDeadNodes();
305 /// FindCallEndFromCallStart - Given a chained node that is part of a call
306 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
307 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
308 if (Node->getOpcode() == ISD::CALLSEQ_END)
310 if (Node->use_empty())
311 return 0; // No CallSeqEnd
313 // The chain is usually at the end.
314 SDValue TheChain(Node, Node->getNumValues()-1);
315 if (TheChain.getValueType() != MVT::Other) {
316 // Sometimes it's at the beginning.
317 TheChain = SDValue(Node, 0);
318 if (TheChain.getValueType() != MVT::Other) {
319 // Otherwise, hunt for it.
320 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
321 if (Node->getValueType(i) == MVT::Other) {
322 TheChain = SDValue(Node, i);
326 // Otherwise, we walked into a node without a chain.
327 if (TheChain.getValueType() != MVT::Other)
332 for (SDNode::use_iterator UI = Node->use_begin(),
333 E = Node->use_end(); UI != E; ++UI) {
335 // Make sure to only follow users of our token chain.
337 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
338 if (User->getOperand(i) == TheChain)
339 if (SDNode *Result = FindCallEndFromCallStart(User))
345 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
346 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
347 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
348 assert(Node && "Didn't find callseq_start for a call??");
349 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
351 assert(Node->getOperand(0).getValueType() == MVT::Other &&
352 "Node doesn't have a token chain argument!");
353 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
356 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
357 /// see if any uses can reach Dest. If no dest operands can get to dest,
358 /// legalize them, legalize ourself, and return false, otherwise, return true.
360 /// Keep track of the nodes we fine that actually do lead to Dest in
361 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
363 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
364 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
365 if (N == Dest) return true; // N certainly leads to Dest :)
367 // If we've already processed this node and it does lead to Dest, there is no
368 // need to reprocess it.
369 if (NodesLeadingTo.count(N)) return true;
371 // If the first result of this node has been already legalized, then it cannot
373 switch (getTypeAction(N->getValueType(0))) {
375 if (LegalizedNodes.count(SDValue(N, 0))) return false;
378 if (PromotedNodes.count(SDValue(N, 0))) return false;
381 if (ExpandedNodes.count(SDValue(N, 0))) return false;
385 // Okay, this node has not already been legalized. Check and legalize all
386 // operands. If none lead to Dest, then we can legalize this node.
387 bool OperandsLeadToDest = false;
388 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
389 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
390 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
392 if (OperandsLeadToDest) {
393 NodesLeadingTo.insert(N);
397 // Okay, this node looks safe, legalize it and return false.
398 HandleOp(SDValue(N, 0));
402 /// HandleOp - Legalize, Promote, or Expand the specified operand as
403 /// appropriate for its type.
404 void SelectionDAGLegalize::HandleOp(SDValue Op) {
405 MVT VT = Op.getValueType();
406 switch (getTypeAction(VT)) {
407 default: assert(0 && "Bad type action!");
408 case Legal: (void)LegalizeOp(Op); break;
409 case Promote: (void)PromoteOp(Op); break;
411 if (!VT.isVector()) {
412 // If this is an illegal scalar, expand it into its two component
415 if (Op.getOpcode() == ISD::TargetConstant)
416 break; // Allow illegal target nodes.
418 } else if (VT.getVectorNumElements() == 1) {
419 // If this is an illegal single element vector, convert it to a
421 (void)ScalarizeVectorOp(Op);
423 // Otherwise, this is an illegal multiple element vector.
424 // Split it in half and legalize both parts.
426 SplitVectorOp(Op, X, Y);
432 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
433 /// a load from the constant pool.
434 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
435 SelectionDAG &DAG, TargetLowering &TLI) {
438 // If a FP immediate is precise when represented as a float and if the
439 // target can do an extending load from float to double, we put it into
440 // the constant pool as a float, even if it's is statically typed as a
441 // double. This shrinks FP constants and canonicalizes them for targets where
442 // an FP extending load is the same cost as a normal load (such as on the x87
443 // fp stack or PPC FP unit).
444 MVT VT = CFP->getValueType(0);
445 ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF());
447 if (VT!=MVT::f64 && VT!=MVT::f32)
448 assert(0 && "Invalid type expansion");
449 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(),
450 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
455 while (SVT != MVT::f32) {
456 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
457 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
458 // Only do this if the target has a native EXTLOAD instruction from
460 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) &&
461 TLI.ShouldShrinkFPConstant(OrigVT)) {
462 const Type *SType = SVT.getTypeForMVT();
463 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
469 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
471 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
472 CPIdx, PseudoSourceValue::getConstantPool(),
474 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
475 PseudoSourceValue::getConstantPool(), 0);
479 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
482 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
483 SelectionDAG &DAG, TargetLowering &TLI) {
484 MVT VT = Node->getValueType(0);
485 MVT SrcVT = Node->getOperand(1).getValueType();
486 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
487 "fcopysign expansion only supported for f32 and f64");
488 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
490 // First get the sign bit of second operand.
491 SDValue Mask1 = (SrcVT == MVT::f64)
492 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
493 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
494 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
495 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
496 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
497 // Shift right or sign-extend it if the two operands have different types.
498 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
500 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
501 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
502 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
503 } else if (SizeDiff < 0) {
504 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
505 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
506 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
509 // Clear the sign bit of first operand.
510 SDValue Mask2 = (VT == MVT::f64)
511 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
512 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
513 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
514 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
515 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
517 // Or the value with the sign bit.
518 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
522 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
524 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
525 TargetLowering &TLI) {
526 SDValue Chain = ST->getChain();
527 SDValue Ptr = ST->getBasePtr();
528 SDValue Val = ST->getValue();
529 MVT VT = Val.getValueType();
530 int Alignment = ST->getAlignment();
531 int SVOffset = ST->getSrcValueOffset();
532 if (ST->getMemoryVT().isFloatingPoint() ||
533 ST->getMemoryVT().isVector()) {
534 // Expand to a bitconvert of the value to the integer type of the
535 // same size, then a (misaligned) int store.
537 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128)
539 else if (VT.is64BitVector() || VT==MVT::f64)
541 else if (VT==MVT::f32)
544 assert(0 && "Unaligned store of unsupported type");
546 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
547 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
548 SVOffset, ST->isVolatile(), Alignment);
550 assert(ST->getMemoryVT().isInteger() &&
551 !ST->getMemoryVT().isVector() &&
552 "Unaligned store of unknown type.");
553 // Get the half-size VT
555 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
556 int NumBits = NewStoredVT.getSizeInBits();
557 int IncrementSize = NumBits / 8;
559 // Divide the stored value in two parts.
560 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
562 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
564 // Store the two parts
565 SDValue Store1, Store2;
566 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
567 ST->getSrcValue(), SVOffset, NewStoredVT,
568 ST->isVolatile(), Alignment);
569 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
570 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
571 Alignment = MinAlign(Alignment, IncrementSize);
572 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
573 ST->getSrcValue(), SVOffset + IncrementSize,
574 NewStoredVT, ST->isVolatile(), Alignment);
576 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
579 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
581 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
582 TargetLowering &TLI) {
583 int SVOffset = LD->getSrcValueOffset();
584 SDValue Chain = LD->getChain();
585 SDValue Ptr = LD->getBasePtr();
586 MVT VT = LD->getValueType(0);
587 MVT LoadedVT = LD->getMemoryVT();
588 if (VT.isFloatingPoint() || VT.isVector()) {
589 // Expand to a (misaligned) integer load of the same size,
590 // then bitconvert to floating point or vector.
592 if (LoadedVT.is128BitVector() ||
593 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
595 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64)
597 else if (LoadedVT == MVT::f32)
600 assert(0 && "Unaligned load of unsupported type");
602 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
603 SVOffset, LD->isVolatile(),
605 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
606 if (VT.isFloatingPoint() && LoadedVT != VT)
607 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
609 SDValue Ops[] = { Result, Chain };
610 return DAG.getMergeValues(Ops, 2);
612 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
613 "Unaligned load of unsupported type.");
615 // Compute the new VT that is half the size of the old one. This is an
617 unsigned NumBits = LoadedVT.getSizeInBits();
619 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
622 unsigned Alignment = LD->getAlignment();
623 unsigned IncrementSize = NumBits / 8;
624 ISD::LoadExtType HiExtType = LD->getExtensionType();
626 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
627 if (HiExtType == ISD::NON_EXTLOAD)
628 HiExtType = ISD::ZEXTLOAD;
630 // Load the value in two parts
632 if (TLI.isLittleEndian()) {
633 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
634 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
635 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
636 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
637 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
638 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
639 MinAlign(Alignment, IncrementSize));
641 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
642 NewLoadedVT,LD->isVolatile(), Alignment);
643 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
644 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
645 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
646 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
647 MinAlign(Alignment, IncrementSize));
650 // aggregate the two parts
651 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
652 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
653 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
655 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
658 SDValue Ops[] = { Result, TF };
659 return DAG.getMergeValues(Ops, 2);
662 /// UnrollVectorOp - We know that the given vector has a legal type, however
663 /// the operation it performs is not legal and is an operation that we have
664 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
665 /// operating on each element individually.
666 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
667 MVT VT = Op.getValueType();
668 assert(isTypeLegal(VT) &&
669 "Caller should expand or promote operands that are not legal!");
670 assert(Op.Val->getNumValues() == 1 &&
671 "Can't unroll a vector with multiple results!");
672 unsigned NE = VT.getVectorNumElements();
673 MVT EltVT = VT.getVectorElementType();
675 SmallVector<SDValue, 8> Scalars;
676 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
677 for (unsigned i = 0; i != NE; ++i) {
678 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
679 SDValue Operand = Op.getOperand(j);
680 MVT OperandVT = Operand.getValueType();
681 if (OperandVT.isVector()) {
682 // A vector operand; extract a single element.
683 MVT OperandEltVT = OperandVT.getVectorElementType();
684 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
687 DAG.getConstant(i, MVT::i32));
689 // A scalar operand; just use it as is.
690 Operands[j] = Operand;
693 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
694 &Operands[0], Operands.size()));
697 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
700 /// GetFPLibCall - Return the right libcall for the given floating point type.
701 static RTLIB::Libcall GetFPLibCall(MVT VT,
702 RTLIB::Libcall Call_F32,
703 RTLIB::Libcall Call_F64,
704 RTLIB::Libcall Call_F80,
705 RTLIB::Libcall Call_PPCF128) {
707 VT == MVT::f32 ? Call_F32 :
708 VT == MVT::f64 ? Call_F64 :
709 VT == MVT::f80 ? Call_F80 :
710 VT == MVT::ppcf128 ? Call_PPCF128 :
711 RTLIB::UNKNOWN_LIBCALL;
714 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
715 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
716 /// is necessary to spill the vector being inserted into to memory, perform
717 /// the insert there, and then read the result back.
718 SDValue SelectionDAGLegalize::
719 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) {
724 // If the target doesn't support this, we have to spill the input vector
725 // to a temporary stack slot, update the element, then reload it. This is
726 // badness. We could also load the value into a vector register (either
727 // with a "move to register" or "extload into register" instruction, then
728 // permute it into place, if the idx is a constant and if the idx is
729 // supported by the target.
730 MVT VT = Tmp1.getValueType();
731 MVT EltVT = VT.getVectorElementType();
732 MVT IdxVT = Tmp3.getValueType();
733 MVT PtrVT = TLI.getPointerTy();
734 SDValue StackPtr = DAG.CreateStackTemporary(VT);
736 int SPFI = cast<FrameIndexSDNode>(StackPtr.Val)->getIndex();
739 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
740 PseudoSourceValue::getFixedStack(SPFI), 0);
742 // Truncate or zero extend offset to target pointer type.
743 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
744 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
745 // Add the offset to the index.
746 unsigned EltSize = EltVT.getSizeInBits()/8;
747 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
748 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
749 // Store the scalar value.
750 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
751 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
752 // Load the updated vector.
753 return DAG.getLoad(VT, Ch, StackPtr,
754 PseudoSourceValue::getFixedStack(SPFI), 0);
757 /// LegalizeOp - We know that the specified value has a legal type, and
758 /// that its operands are legal. Now ensure that the operation itself
759 /// is legal, recursively ensuring that the operands' operations remain
761 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
762 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
765 assert(isTypeLegal(Op.getValueType()) &&
766 "Caller should expand or promote operands that are not legal!");
767 SDNode *Node = Op.Val;
769 // If this operation defines any values that cannot be represented in a
770 // register on this target, make sure to expand or promote them.
771 if (Node->getNumValues() > 1) {
772 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
773 if (getTypeAction(Node->getValueType(i)) != Legal) {
774 HandleOp(Op.getValue(i));
775 assert(LegalizedNodes.count(Op) &&
776 "Handling didn't add legal operands!");
777 return LegalizedNodes[Op];
781 // Note that LegalizeOp may be reentered even from single-use nodes, which
782 // means that we always must cache transformed nodes.
783 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
784 if (I != LegalizedNodes.end()) return I->second;
786 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
788 bool isCustom = false;
790 switch (Node->getOpcode()) {
791 case ISD::FrameIndex:
792 case ISD::EntryToken:
794 case ISD::BasicBlock:
795 case ISD::TargetFrameIndex:
796 case ISD::TargetJumpTable:
797 case ISD::TargetConstant:
798 case ISD::TargetConstantFP:
799 case ISD::TargetConstantPool:
800 case ISD::TargetGlobalAddress:
801 case ISD::TargetGlobalTLSAddress:
802 case ISD::TargetExternalSymbol:
805 case ISD::MEMOPERAND:
808 // Primitives must all be legal.
809 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
810 "This must be legal!");
813 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
814 // If this is a target node, legalize it by legalizing the operands then
815 // passing it through.
816 SmallVector<SDValue, 8> Ops;
817 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
818 Ops.push_back(LegalizeOp(Node->getOperand(i)));
820 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
822 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
823 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
824 return Result.getValue(Op.getResNo());
826 // Otherwise this is an unhandled builtin node. splat.
828 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
830 assert(0 && "Do not know how to legalize this operator!");
832 case ISD::GLOBAL_OFFSET_TABLE:
833 case ISD::GlobalAddress:
834 case ISD::GlobalTLSAddress:
835 case ISD::ExternalSymbol:
836 case ISD::ConstantPool:
837 case ISD::JumpTable: // Nothing to do.
838 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
839 default: assert(0 && "This action is not supported yet!");
840 case TargetLowering::Custom:
841 Tmp1 = TLI.LowerOperation(Op, DAG);
842 if (Tmp1.Val) Result = Tmp1;
843 // FALLTHROUGH if the target doesn't want to lower this op after all.
844 case TargetLowering::Legal:
849 case ISD::RETURNADDR:
850 // The only option for these nodes is to custom lower them. If the target
851 // does not custom lower them, then return zero.
852 Tmp1 = TLI.LowerOperation(Op, DAG);
856 Result = DAG.getConstant(0, TLI.getPointerTy());
858 case ISD::FRAME_TO_ARGS_OFFSET: {
859 MVT VT = Node->getValueType(0);
860 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
861 default: assert(0 && "This action is not supported yet!");
862 case TargetLowering::Custom:
863 Result = TLI.LowerOperation(Op, DAG);
864 if (Result.Val) break;
866 case TargetLowering::Legal:
867 Result = DAG.getConstant(0, VT);
872 case ISD::EXCEPTIONADDR: {
873 Tmp1 = LegalizeOp(Node->getOperand(0));
874 MVT VT = Node->getValueType(0);
875 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
876 default: assert(0 && "This action is not supported yet!");
877 case TargetLowering::Expand: {
878 unsigned Reg = TLI.getExceptionAddressRegister();
879 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
882 case TargetLowering::Custom:
883 Result = TLI.LowerOperation(Op, DAG);
884 if (Result.Val) break;
886 case TargetLowering::Legal: {
887 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
888 Result = DAG.getMergeValues(Ops, 2);
893 if (Result.Val->getNumValues() == 1) break;
895 assert(Result.Val->getNumValues() == 2 &&
896 "Cannot return more than two values!");
898 // Since we produced two values, make sure to remember that we
899 // legalized both of them.
900 Tmp1 = LegalizeOp(Result);
901 Tmp2 = LegalizeOp(Result.getValue(1));
902 AddLegalizedOperand(Op.getValue(0), Tmp1);
903 AddLegalizedOperand(Op.getValue(1), Tmp2);
904 return Op.getResNo() ? Tmp2 : Tmp1;
905 case ISD::EHSELECTION: {
906 Tmp1 = LegalizeOp(Node->getOperand(0));
907 Tmp2 = LegalizeOp(Node->getOperand(1));
908 MVT VT = Node->getValueType(0);
909 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
910 default: assert(0 && "This action is not supported yet!");
911 case TargetLowering::Expand: {
912 unsigned Reg = TLI.getExceptionSelectorRegister();
913 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
916 case TargetLowering::Custom:
917 Result = TLI.LowerOperation(Op, DAG);
918 if (Result.Val) break;
920 case TargetLowering::Legal: {
921 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
922 Result = DAG.getMergeValues(Ops, 2);
927 if (Result.Val->getNumValues() == 1) break;
929 assert(Result.Val->getNumValues() == 2 &&
930 "Cannot return more than two values!");
932 // Since we produced two values, make sure to remember that we
933 // legalized both of them.
934 Tmp1 = LegalizeOp(Result);
935 Tmp2 = LegalizeOp(Result.getValue(1));
936 AddLegalizedOperand(Op.getValue(0), Tmp1);
937 AddLegalizedOperand(Op.getValue(1), Tmp2);
938 return Op.getResNo() ? Tmp2 : Tmp1;
939 case ISD::EH_RETURN: {
940 MVT VT = Node->getValueType(0);
941 // The only "good" option for this node is to custom lower it.
942 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
943 default: assert(0 && "This action is not supported at all!");
944 case TargetLowering::Custom:
945 Result = TLI.LowerOperation(Op, DAG);
946 if (Result.Val) break;
948 case TargetLowering::Legal:
949 // Target does not know, how to lower this, lower to noop
950 Result = LegalizeOp(Node->getOperand(0));
955 case ISD::AssertSext:
956 case ISD::AssertZext:
957 Tmp1 = LegalizeOp(Node->getOperand(0));
958 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
960 case ISD::MERGE_VALUES:
961 // Legalize eliminates MERGE_VALUES nodes.
962 Result = Node->getOperand(Op.getResNo());
964 case ISD::CopyFromReg:
965 Tmp1 = LegalizeOp(Node->getOperand(0));
966 Result = Op.getValue(0);
967 if (Node->getNumValues() == 2) {
968 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
970 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
971 if (Node->getNumOperands() == 3) {
972 Tmp2 = LegalizeOp(Node->getOperand(2));
973 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
975 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
977 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
979 // Since CopyFromReg produces two values, make sure to remember that we
980 // legalized both of them.
981 AddLegalizedOperand(Op.getValue(0), Result);
982 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
983 return Result.getValue(Op.getResNo());
985 MVT VT = Op.getValueType();
986 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
987 default: assert(0 && "This action is not supported yet!");
988 case TargetLowering::Expand:
990 Result = DAG.getConstant(0, VT);
991 else if (VT.isFloatingPoint())
992 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
995 assert(0 && "Unknown value type!");
997 case TargetLowering::Legal:
1003 case ISD::INTRINSIC_W_CHAIN:
1004 case ISD::INTRINSIC_WO_CHAIN:
1005 case ISD::INTRINSIC_VOID: {
1006 SmallVector<SDValue, 8> Ops;
1007 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1008 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1009 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1011 // Allow the target to custom lower its intrinsics if it wants to.
1012 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1013 TargetLowering::Custom) {
1014 Tmp3 = TLI.LowerOperation(Result, DAG);
1015 if (Tmp3.Val) Result = Tmp3;
1018 if (Result.Val->getNumValues() == 1) break;
1020 // Must have return value and chain result.
1021 assert(Result.Val->getNumValues() == 2 &&
1022 "Cannot return more than two values!");
1024 // Since loads produce two values, make sure to remember that we
1025 // legalized both of them.
1026 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1027 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1028 return Result.getValue(Op.getResNo());
1031 case ISD::DBG_STOPPOINT:
1032 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1033 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1035 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1036 case TargetLowering::Promote:
1037 default: assert(0 && "This action is not supported yet!");
1038 case TargetLowering::Expand: {
1039 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1040 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1041 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
1043 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1044 if (MMI && (useDEBUG_LOC || useLABEL)) {
1045 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
1046 unsigned SrcFile = MMI->RecordSource(CompileUnit);
1048 unsigned Line = DSP->getLine();
1049 unsigned Col = DSP->getColumn();
1052 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1053 DAG.getConstant(Col, MVT::i32),
1054 DAG.getConstant(SrcFile, MVT::i32) };
1055 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
1057 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1058 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1061 Result = Tmp1; // chain
1065 case TargetLowering::Legal: {
1066 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1067 if (Action == Legal && Tmp1 == Node->getOperand(0))
1070 SmallVector<SDValue, 8> Ops;
1071 Ops.push_back(Tmp1);
1072 if (Action == Legal) {
1073 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1074 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1076 // Otherwise promote them.
1077 Ops.push_back(PromoteOp(Node->getOperand(1)));
1078 Ops.push_back(PromoteOp(Node->getOperand(2)));
1080 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1081 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1082 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1089 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1090 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1091 default: assert(0 && "This action is not supported yet!");
1092 case TargetLowering::Legal:
1093 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1094 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1095 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1096 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1098 case TargetLowering::Expand:
1099 Result = LegalizeOp(Node->getOperand(0));
1104 case ISD::DEBUG_LOC:
1105 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1106 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1107 default: assert(0 && "This action is not supported yet!");
1108 case TargetLowering::Legal: {
1109 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1110 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1111 if (Action == Legal && Tmp1 == Node->getOperand(0))
1113 if (Action == Legal) {
1114 Tmp2 = Node->getOperand(1);
1115 Tmp3 = Node->getOperand(2);
1116 Tmp4 = Node->getOperand(3);
1118 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1119 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1120 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1122 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1128 case ISD::DBG_LABEL:
1130 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1131 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1132 default: assert(0 && "This action is not supported yet!");
1133 case TargetLowering::Legal:
1134 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1135 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1137 case TargetLowering::Expand:
1138 Result = LegalizeOp(Node->getOperand(0));
1144 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1145 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1146 default: assert(0 && "This action is not supported yet!");
1147 case TargetLowering::Legal:
1148 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1149 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1150 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1151 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1152 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1154 case TargetLowering::Expand:
1156 Result = LegalizeOp(Node->getOperand(0));
1161 case ISD::MEMBARRIER: {
1162 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1163 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1164 default: assert(0 && "This action is not supported yet!");
1165 case TargetLowering::Legal: {
1167 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1168 for (int x = 1; x < 6; ++x) {
1169 Ops[x] = Node->getOperand(x);
1170 if (!isTypeLegal(Ops[x].getValueType()))
1171 Ops[x] = PromoteOp(Ops[x]);
1173 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1176 case TargetLowering::Expand:
1177 //There is no libgcc call for this op
1178 Result = Node->getOperand(0); // Noop
1184 case ISD::ATOMIC_CMP_SWAP: {
1185 unsigned int num_operands = 4;
1186 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1188 for (unsigned int x = 0; x < num_operands; ++x)
1189 Ops[x] = LegalizeOp(Node->getOperand(x));
1190 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1192 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1193 default: assert(0 && "This action is not supported yet!");
1194 case TargetLowering::Custom:
1195 Result = TLI.LowerOperation(Result, DAG);
1197 case TargetLowering::Legal:
1200 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1201 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1202 return Result.getValue(Op.getResNo());
1204 case ISD::ATOMIC_LOAD_ADD:
1205 case ISD::ATOMIC_LOAD_SUB:
1206 case ISD::ATOMIC_LOAD_AND:
1207 case ISD::ATOMIC_LOAD_OR:
1208 case ISD::ATOMIC_LOAD_XOR:
1209 case ISD::ATOMIC_LOAD_NAND:
1210 case ISD::ATOMIC_LOAD_MIN:
1211 case ISD::ATOMIC_LOAD_MAX:
1212 case ISD::ATOMIC_LOAD_UMIN:
1213 case ISD::ATOMIC_LOAD_UMAX:
1214 case ISD::ATOMIC_SWAP: {
1215 unsigned int num_operands = 3;
1216 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1218 for (unsigned int x = 0; x < num_operands; ++x)
1219 Ops[x] = LegalizeOp(Node->getOperand(x));
1220 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1222 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1223 default: assert(0 && "This action is not supported yet!");
1224 case TargetLowering::Custom:
1225 Result = TLI.LowerOperation(Result, DAG);
1227 case TargetLowering::Expand:
1228 Result = SDValue(TLI.ReplaceNodeResults(Op.Val, DAG),0);
1230 case TargetLowering::Legal:
1233 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1234 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1235 return Result.getValue(Op.getResNo());
1237 case ISD::Constant: {
1238 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1240 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1242 // We know we don't need to expand constants here, constants only have one
1243 // value and we check that it is fine above.
1245 if (opAction == TargetLowering::Custom) {
1246 Tmp1 = TLI.LowerOperation(Result, DAG);
1252 case ISD::ConstantFP: {
1253 // Spill FP immediates to the constant pool if the target cannot directly
1254 // codegen them. Targets often have some immediate values that can be
1255 // efficiently generated into an FP register without a load. We explicitly
1256 // leave these constants as ConstantFP nodes for the target to deal with.
1257 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1259 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1260 default: assert(0 && "This action is not supported yet!");
1261 case TargetLowering::Legal:
1263 case TargetLowering::Custom:
1264 Tmp3 = TLI.LowerOperation(Result, DAG);
1270 case TargetLowering::Expand: {
1271 // Check to see if this FP immediate is already legal.
1272 bool isLegal = false;
1273 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1274 E = TLI.legal_fpimm_end(); I != E; ++I) {
1275 if (CFP->isExactlyValue(*I)) {
1280 // If this is a legal constant, turn it into a TargetConstantFP node.
1283 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1288 case ISD::TokenFactor:
1289 if (Node->getNumOperands() == 2) {
1290 Tmp1 = LegalizeOp(Node->getOperand(0));
1291 Tmp2 = LegalizeOp(Node->getOperand(1));
1292 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1293 } else if (Node->getNumOperands() == 3) {
1294 Tmp1 = LegalizeOp(Node->getOperand(0));
1295 Tmp2 = LegalizeOp(Node->getOperand(1));
1296 Tmp3 = LegalizeOp(Node->getOperand(2));
1297 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1299 SmallVector<SDValue, 8> Ops;
1300 // Legalize the operands.
1301 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1302 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1303 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1307 case ISD::FORMAL_ARGUMENTS:
1309 // The only option for this is to custom lower it.
1310 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1311 assert(Tmp3.Val && "Target didn't custom lower this node!");
1312 // A call within a calling sequence must be legalized to something
1313 // other than the normal CALLSEQ_END. Violating this gets Legalize
1314 // into an infinite loop.
1315 assert ((!IsLegalizingCall ||
1316 Node->getOpcode() != ISD::CALL ||
1317 Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) &&
1318 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1320 // The number of incoming and outgoing values should match; unless the final
1321 // outgoing value is a flag.
1322 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1323 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1324 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1326 "Lowering call/formal_arguments produced unexpected # results!");
1328 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1329 // remember that we legalized all of them, so it doesn't get relegalized.
1330 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1331 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1333 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1334 if (Op.getResNo() == i)
1336 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1339 case ISD::EXTRACT_SUBREG: {
1340 Tmp1 = LegalizeOp(Node->getOperand(0));
1341 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1342 assert(idx && "Operand must be a constant");
1343 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1344 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1347 case ISD::INSERT_SUBREG: {
1348 Tmp1 = LegalizeOp(Node->getOperand(0));
1349 Tmp2 = LegalizeOp(Node->getOperand(1));
1350 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1351 assert(idx && "Operand must be a constant");
1352 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1353 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1356 case ISD::BUILD_VECTOR:
1357 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1358 default: assert(0 && "This action is not supported yet!");
1359 case TargetLowering::Custom:
1360 Tmp3 = TLI.LowerOperation(Result, DAG);
1366 case TargetLowering::Expand:
1367 Result = ExpandBUILD_VECTOR(Result.Val);
1371 case ISD::INSERT_VECTOR_ELT:
1372 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1373 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1375 // The type of the value to insert may not be legal, even though the vector
1376 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1378 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1379 default: assert(0 && "Cannot expand insert element operand");
1380 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1381 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1383 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1385 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1386 Node->getValueType(0))) {
1387 default: assert(0 && "This action is not supported yet!");
1388 case TargetLowering::Legal:
1390 case TargetLowering::Custom:
1391 Tmp4 = TLI.LowerOperation(Result, DAG);
1397 case TargetLowering::Expand: {
1398 // If the insert index is a constant, codegen this as a scalar_to_vector,
1399 // then a shuffle that inserts it into the right position in the vector.
1400 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1401 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1402 // match the element type of the vector being created.
1403 if (Tmp2.getValueType() ==
1404 Op.getValueType().getVectorElementType()) {
1405 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1406 Tmp1.getValueType(), Tmp2);
1408 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1410 MVT::getIntVectorWithNumElements(NumElts);
1411 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1413 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1414 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1415 // elt 0 of the RHS.
1416 SmallVector<SDValue, 8> ShufOps;
1417 for (unsigned i = 0; i != NumElts; ++i) {
1418 if (i != InsertPos->getValue())
1419 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1421 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1423 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1424 &ShufOps[0], ShufOps.size());
1426 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1427 Tmp1, ScVec, ShufMask);
1428 Result = LegalizeOp(Result);
1432 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1437 case ISD::SCALAR_TO_VECTOR:
1438 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1439 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1443 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1444 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1445 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1446 Node->getValueType(0))) {
1447 default: assert(0 && "This action is not supported yet!");
1448 case TargetLowering::Legal:
1450 case TargetLowering::Custom:
1451 Tmp3 = TLI.LowerOperation(Result, DAG);
1457 case TargetLowering::Expand:
1458 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1462 case ISD::VECTOR_SHUFFLE:
1463 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1464 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1465 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1467 // Allow targets to custom lower the SHUFFLEs they support.
1468 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1469 default: assert(0 && "Unknown operation action!");
1470 case TargetLowering::Legal:
1471 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1472 "vector shuffle should not be created if not legal!");
1474 case TargetLowering::Custom:
1475 Tmp3 = TLI.LowerOperation(Result, DAG);
1481 case TargetLowering::Expand: {
1482 MVT VT = Node->getValueType(0);
1483 MVT EltVT = VT.getVectorElementType();
1484 MVT PtrVT = TLI.getPointerTy();
1485 SDValue Mask = Node->getOperand(2);
1486 unsigned NumElems = Mask.getNumOperands();
1487 SmallVector<SDValue,8> Ops;
1488 for (unsigned i = 0; i != NumElems; ++i) {
1489 SDValue Arg = Mask.getOperand(i);
1490 if (Arg.getOpcode() == ISD::UNDEF) {
1491 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1493 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1494 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1496 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1497 DAG.getConstant(Idx, PtrVT)));
1499 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1500 DAG.getConstant(Idx - NumElems, PtrVT)));
1503 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1506 case TargetLowering::Promote: {
1507 // Change base type to a different vector type.
1508 MVT OVT = Node->getValueType(0);
1509 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1511 // Cast the two input vectors.
1512 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1513 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1515 // Convert the shuffle mask to the right # elements.
1516 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1517 assert(Tmp3.Val && "Shuffle not legal?");
1518 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1519 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1525 case ISD::EXTRACT_VECTOR_ELT:
1526 Tmp1 = Node->getOperand(0);
1527 Tmp2 = LegalizeOp(Node->getOperand(1));
1528 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1529 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1532 case ISD::EXTRACT_SUBVECTOR:
1533 Tmp1 = Node->getOperand(0);
1534 Tmp2 = LegalizeOp(Node->getOperand(1));
1535 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1536 Result = ExpandEXTRACT_SUBVECTOR(Result);
1539 case ISD::CALLSEQ_START: {
1540 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1542 // Recursively Legalize all of the inputs of the call end that do not lead
1543 // to this call start. This ensures that any libcalls that need be inserted
1544 // are inserted *before* the CALLSEQ_START.
1545 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1546 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1547 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1551 // Now that we legalized all of the inputs (which may have inserted
1552 // libcalls) create the new CALLSEQ_START node.
1553 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1555 // Merge in the last call, to ensure that this call start after the last
1557 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1558 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1559 Tmp1 = LegalizeOp(Tmp1);
1562 // Do not try to legalize the target-specific arguments (#1+).
1563 if (Tmp1 != Node->getOperand(0)) {
1564 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1566 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1569 // Remember that the CALLSEQ_START is legalized.
1570 AddLegalizedOperand(Op.getValue(0), Result);
1571 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1572 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1574 // Now that the callseq_start and all of the non-call nodes above this call
1575 // sequence have been legalized, legalize the call itself. During this
1576 // process, no libcalls can/will be inserted, guaranteeing that no calls
1578 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1579 // Note that we are selecting this call!
1580 LastCALLSEQ_END = SDValue(CallEnd, 0);
1581 IsLegalizingCall = true;
1583 // Legalize the call, starting from the CALLSEQ_END.
1584 LegalizeOp(LastCALLSEQ_END);
1585 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1588 case ISD::CALLSEQ_END:
1589 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1590 // will cause this node to be legalized as well as handling libcalls right.
1591 if (LastCALLSEQ_END.Val != Node) {
1592 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1593 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1594 assert(I != LegalizedNodes.end() &&
1595 "Legalizing the call start should have legalized this node!");
1599 // Otherwise, the call start has been legalized and everything is going
1600 // according to plan. Just legalize ourselves normally here.
1601 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1602 // Do not try to legalize the target-specific arguments (#1+), except for
1603 // an optional flag input.
1604 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1605 if (Tmp1 != Node->getOperand(0)) {
1606 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1608 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1611 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1612 if (Tmp1 != Node->getOperand(0) ||
1613 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1614 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1617 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1620 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1621 // This finishes up call legalization.
1622 IsLegalizingCall = false;
1624 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1625 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1626 if (Node->getNumValues() == 2)
1627 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1628 return Result.getValue(Op.getResNo());
1629 case ISD::DYNAMIC_STACKALLOC: {
1630 MVT VT = Node->getValueType(0);
1631 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1632 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1633 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1634 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1636 Tmp1 = Result.getValue(0);
1637 Tmp2 = Result.getValue(1);
1638 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1639 default: assert(0 && "This action is not supported yet!");
1640 case TargetLowering::Expand: {
1641 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1642 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1643 " not tell us which reg is the stack pointer!");
1644 SDValue Chain = Tmp1.getOperand(0);
1646 // Chain the dynamic stack allocation so that it doesn't modify the stack
1647 // pointer when other instructions are using the stack.
1648 Chain = DAG.getCALLSEQ_START(Chain,
1649 DAG.getConstant(0, TLI.getPointerTy()));
1651 SDValue Size = Tmp2.getOperand(1);
1652 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1653 Chain = SP.getValue(1);
1654 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1655 unsigned StackAlign =
1656 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1657 if (Align > StackAlign)
1658 SP = DAG.getNode(ISD::AND, VT, SP,
1659 DAG.getConstant(-(uint64_t)Align, VT));
1660 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1661 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1664 DAG.getCALLSEQ_END(Chain,
1665 DAG.getConstant(0, TLI.getPointerTy()),
1666 DAG.getConstant(0, TLI.getPointerTy()),
1669 Tmp1 = LegalizeOp(Tmp1);
1670 Tmp2 = LegalizeOp(Tmp2);
1673 case TargetLowering::Custom:
1674 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1676 Tmp1 = LegalizeOp(Tmp3);
1677 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1680 case TargetLowering::Legal:
1683 // Since this op produce two values, make sure to remember that we
1684 // legalized both of them.
1685 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1686 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1687 return Op.getResNo() ? Tmp2 : Tmp1;
1689 case ISD::INLINEASM: {
1690 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1691 bool Changed = false;
1692 // Legalize all of the operands of the inline asm, in case they are nodes
1693 // that need to be expanded or something. Note we skip the asm string and
1694 // all of the TargetConstant flags.
1695 SDValue Op = LegalizeOp(Ops[0]);
1696 Changed = Op != Ops[0];
1699 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1700 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1701 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1702 for (++i; NumVals; ++i, --NumVals) {
1703 SDValue Op = LegalizeOp(Ops[i]);
1712 Op = LegalizeOp(Ops.back());
1713 Changed |= Op != Ops.back();
1718 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1720 // INLINE asm returns a chain and flag, make sure to add both to the map.
1721 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1722 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1723 return Result.getValue(Op.getResNo());
1726 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1727 // Ensure that libcalls are emitted before a branch.
1728 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1729 Tmp1 = LegalizeOp(Tmp1);
1730 LastCALLSEQ_END = DAG.getEntryNode();
1732 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1735 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1736 // Ensure that libcalls are emitted before a branch.
1737 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1738 Tmp1 = LegalizeOp(Tmp1);
1739 LastCALLSEQ_END = DAG.getEntryNode();
1741 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1742 default: assert(0 && "Indirect target must be legal type (pointer)!");
1744 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1747 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1750 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1751 // Ensure that libcalls are emitted before a branch.
1752 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1753 Tmp1 = LegalizeOp(Tmp1);
1754 LastCALLSEQ_END = DAG.getEntryNode();
1756 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1757 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1759 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1760 default: assert(0 && "This action is not supported yet!");
1761 case TargetLowering::Legal: break;
1762 case TargetLowering::Custom:
1763 Tmp1 = TLI.LowerOperation(Result, DAG);
1764 if (Tmp1.Val) Result = Tmp1;
1766 case TargetLowering::Expand: {
1767 SDValue Chain = Result.getOperand(0);
1768 SDValue Table = Result.getOperand(1);
1769 SDValue Index = Result.getOperand(2);
1771 MVT PTy = TLI.getPointerTy();
1772 MachineFunction &MF = DAG.getMachineFunction();
1773 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1774 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1775 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1778 switch (EntrySize) {
1779 default: assert(0 && "Size of jump table not supported yet."); break;
1780 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1781 PseudoSourceValue::getJumpTable(), 0); break;
1782 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1783 PseudoSourceValue::getJumpTable(), 0); break;
1787 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1788 // For PIC, the sequence is:
1789 // BRIND(load(Jumptable + index) + RelocBase)
1790 // RelocBase can be JumpTable, GOT or some sort of global base.
1791 if (PTy != MVT::i32)
1792 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1793 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1794 TLI.getPICJumpTableRelocBase(Table, DAG));
1796 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1801 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1802 // Ensure that libcalls are emitted before a return.
1803 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1804 Tmp1 = LegalizeOp(Tmp1);
1805 LastCALLSEQ_END = DAG.getEntryNode();
1807 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1808 case Expand: assert(0 && "It's impossible to expand bools");
1810 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1813 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1815 // The top bits of the promoted condition are not necessarily zero, ensure
1816 // that the value is properly zero extended.
1817 unsigned BitWidth = Tmp2.getValueSizeInBits();
1818 if (!DAG.MaskedValueIsZero(Tmp2,
1819 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1820 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1825 // Basic block destination (Op#2) is always legal.
1826 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1828 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1829 default: assert(0 && "This action is not supported yet!");
1830 case TargetLowering::Legal: break;
1831 case TargetLowering::Custom:
1832 Tmp1 = TLI.LowerOperation(Result, DAG);
1833 if (Tmp1.Val) Result = Tmp1;
1835 case TargetLowering::Expand:
1836 // Expand brcond's setcc into its constituent parts and create a BR_CC
1838 if (Tmp2.getOpcode() == ISD::SETCC) {
1839 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1840 Tmp2.getOperand(0), Tmp2.getOperand(1),
1841 Node->getOperand(2));
1843 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1844 DAG.getCondCode(ISD::SETNE), Tmp2,
1845 DAG.getConstant(0, Tmp2.getValueType()),
1846 Node->getOperand(2));
1852 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1853 // Ensure that libcalls are emitted before a branch.
1854 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1855 Tmp1 = LegalizeOp(Tmp1);
1856 Tmp2 = Node->getOperand(2); // LHS
1857 Tmp3 = Node->getOperand(3); // RHS
1858 Tmp4 = Node->getOperand(1); // CC
1860 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1861 LastCALLSEQ_END = DAG.getEntryNode();
1863 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1864 // the LHS is a legal SETCC itself. In this case, we need to compare
1865 // the result against zero to select between true and false values.
1866 if (Tmp3.Val == 0) {
1867 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1868 Tmp4 = DAG.getCondCode(ISD::SETNE);
1871 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1872 Node->getOperand(4));
1874 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1875 default: assert(0 && "Unexpected action for BR_CC!");
1876 case TargetLowering::Legal: break;
1877 case TargetLowering::Custom:
1878 Tmp4 = TLI.LowerOperation(Result, DAG);
1879 if (Tmp4.Val) Result = Tmp4;
1884 LoadSDNode *LD = cast<LoadSDNode>(Node);
1885 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1886 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1888 ISD::LoadExtType ExtType = LD->getExtensionType();
1889 if (ExtType == ISD::NON_EXTLOAD) {
1890 MVT VT = Node->getValueType(0);
1891 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1892 Tmp3 = Result.getValue(0);
1893 Tmp4 = Result.getValue(1);
1895 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1896 default: assert(0 && "This action is not supported yet!");
1897 case TargetLowering::Legal:
1898 // If this is an unaligned load and the target doesn't support it,
1900 if (!TLI.allowsUnalignedMemoryAccesses()) {
1901 unsigned ABIAlignment = TLI.getTargetData()->
1902 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
1903 if (LD->getAlignment() < ABIAlignment){
1904 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1906 Tmp3 = Result.getOperand(0);
1907 Tmp4 = Result.getOperand(1);
1908 Tmp3 = LegalizeOp(Tmp3);
1909 Tmp4 = LegalizeOp(Tmp4);
1913 case TargetLowering::Custom:
1914 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1916 Tmp3 = LegalizeOp(Tmp1);
1917 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1920 case TargetLowering::Promote: {
1921 // Only promote a load of vector type to another.
1922 assert(VT.isVector() && "Cannot promote this load!");
1923 // Change base type to a different vector type.
1924 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1926 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1927 LD->getSrcValueOffset(),
1928 LD->isVolatile(), LD->getAlignment());
1929 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1930 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1934 // Since loads produce two values, make sure to remember that we
1935 // legalized both of them.
1936 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1937 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1938 return Op.getResNo() ? Tmp4 : Tmp3;
1940 MVT SrcVT = LD->getMemoryVT();
1941 unsigned SrcWidth = SrcVT.getSizeInBits();
1942 int SVOffset = LD->getSrcValueOffset();
1943 unsigned Alignment = LD->getAlignment();
1944 bool isVolatile = LD->isVolatile();
1946 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1947 // Some targets pretend to have an i1 loading operation, and actually
1948 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1949 // bits are guaranteed to be zero; it helps the optimizers understand
1950 // that these bits are zero. It is also useful for EXTLOAD, since it
1951 // tells the optimizers that those bits are undefined. It would be
1952 // nice to have an effective generic way of getting these benefits...
1953 // Until such a way is found, don't insist on promoting i1 here.
1954 (SrcVT != MVT::i1 ||
1955 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1956 // Promote to a byte-sized load if not loading an integral number of
1957 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1958 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1959 MVT NVT = MVT::getIntegerVT(NewWidth);
1962 // The extra bits are guaranteed to be zero, since we stored them that
1963 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1965 ISD::LoadExtType NewExtType =
1966 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1968 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
1969 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1970 NVT, isVolatile, Alignment);
1972 Ch = Result.getValue(1); // The chain.
1974 if (ExtType == ISD::SEXTLOAD)
1975 // Having the top bits zero doesn't help when sign extending.
1976 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1977 Result, DAG.getValueType(SrcVT));
1978 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1979 // All the top bits are guaranteed to be zero - inform the optimizers.
1980 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
1981 DAG.getValueType(SrcVT));
1983 Tmp1 = LegalizeOp(Result);
1984 Tmp2 = LegalizeOp(Ch);
1985 } else if (SrcWidth & (SrcWidth - 1)) {
1986 // If not loading a power-of-2 number of bits, expand as two loads.
1987 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
1988 "Unsupported extload!");
1989 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1990 assert(RoundWidth < SrcWidth);
1991 unsigned ExtraWidth = SrcWidth - RoundWidth;
1992 assert(ExtraWidth < RoundWidth);
1993 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1994 "Load size not an integral number of bytes!");
1995 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
1996 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
1998 unsigned IncrementSize;
2000 if (TLI.isLittleEndian()) {
2001 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2002 // Load the bottom RoundWidth bits.
2003 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2004 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2007 // Load the remaining ExtraWidth bits.
2008 IncrementSize = RoundWidth / 8;
2009 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2010 DAG.getIntPtrConstant(IncrementSize));
2011 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2012 LD->getSrcValue(), SVOffset + IncrementSize,
2013 ExtraVT, isVolatile,
2014 MinAlign(Alignment, IncrementSize));
2016 // Build a factor node to remember that this load is independent of the
2018 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2021 // Move the top bits to the right place.
2022 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2023 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2025 // Join the hi and lo parts.
2026 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2028 // Big endian - avoid unaligned loads.
2029 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2030 // Load the top RoundWidth bits.
2031 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2032 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2035 // Load the remaining ExtraWidth bits.
2036 IncrementSize = RoundWidth / 8;
2037 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2038 DAG.getIntPtrConstant(IncrementSize));
2039 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2040 LD->getSrcValue(), SVOffset + IncrementSize,
2041 ExtraVT, isVolatile,
2042 MinAlign(Alignment, IncrementSize));
2044 // Build a factor node to remember that this load is independent of the
2046 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2049 // Move the top bits to the right place.
2050 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2051 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2053 // Join the hi and lo parts.
2054 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2057 Tmp1 = LegalizeOp(Result);
2058 Tmp2 = LegalizeOp(Ch);
2060 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2061 default: assert(0 && "This action is not supported yet!");
2062 case TargetLowering::Custom:
2065 case TargetLowering::Legal:
2066 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2067 Tmp1 = Result.getValue(0);
2068 Tmp2 = Result.getValue(1);
2071 Tmp3 = TLI.LowerOperation(Result, DAG);
2073 Tmp1 = LegalizeOp(Tmp3);
2074 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2077 // If this is an unaligned load and the target doesn't support it,
2079 if (!TLI.allowsUnalignedMemoryAccesses()) {
2080 unsigned ABIAlignment = TLI.getTargetData()->
2081 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2082 if (LD->getAlignment() < ABIAlignment){
2083 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
2085 Tmp1 = Result.getOperand(0);
2086 Tmp2 = Result.getOperand(1);
2087 Tmp1 = LegalizeOp(Tmp1);
2088 Tmp2 = LegalizeOp(Tmp2);
2093 case TargetLowering::Expand:
2094 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2095 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2096 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2097 LD->getSrcValueOffset(),
2098 LD->isVolatile(), LD->getAlignment());
2099 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2100 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2101 Tmp2 = LegalizeOp(Load.getValue(1));
2104 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2105 // Turn the unsupported load into an EXTLOAD followed by an explicit
2106 // zero/sign extend inreg.
2107 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2108 Tmp1, Tmp2, LD->getSrcValue(),
2109 LD->getSrcValueOffset(), SrcVT,
2110 LD->isVolatile(), LD->getAlignment());
2112 if (ExtType == ISD::SEXTLOAD)
2113 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2114 Result, DAG.getValueType(SrcVT));
2116 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2117 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2118 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2123 // Since loads produce two values, make sure to remember that we legalized
2125 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2126 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2127 return Op.getResNo() ? Tmp2 : Tmp1;
2130 case ISD::EXTRACT_ELEMENT: {
2131 MVT OpTy = Node->getOperand(0).getValueType();
2132 switch (getTypeAction(OpTy)) {
2133 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2135 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2137 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2138 DAG.getConstant(OpTy.getSizeInBits()/2,
2139 TLI.getShiftAmountTy()));
2140 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2143 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2144 Node->getOperand(0));
2148 // Get both the low and high parts.
2149 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2150 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2151 Result = Tmp2; // 1 -> Hi
2153 Result = Tmp1; // 0 -> Lo
2159 case ISD::CopyToReg:
2160 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2162 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2163 "Register type must be legal!");
2164 // Legalize the incoming value (must be a legal type).
2165 Tmp2 = LegalizeOp(Node->getOperand(2));
2166 if (Node->getNumValues() == 1) {
2167 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2169 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2170 if (Node->getNumOperands() == 4) {
2171 Tmp3 = LegalizeOp(Node->getOperand(3));
2172 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2175 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2178 // Since this produces two values, make sure to remember that we legalized
2180 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2181 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2187 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2189 // Ensure that libcalls are emitted before a return.
2190 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2191 Tmp1 = LegalizeOp(Tmp1);
2192 LastCALLSEQ_END = DAG.getEntryNode();
2194 switch (Node->getNumOperands()) {
2196 Tmp2 = Node->getOperand(1);
2197 Tmp3 = Node->getOperand(2); // Signness
2198 switch (getTypeAction(Tmp2.getValueType())) {
2200 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2203 if (!Tmp2.getValueType().isVector()) {
2205 ExpandOp(Tmp2, Lo, Hi);
2207 // Big endian systems want the hi reg first.
2208 if (TLI.isBigEndian())
2212 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2214 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2215 Result = LegalizeOp(Result);
2217 SDNode *InVal = Tmp2.Val;
2218 int InIx = Tmp2.getResNo();
2219 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2220 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2222 // Figure out if there is a simple type corresponding to this Vector
2223 // type. If so, convert to the vector type.
2224 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2225 if (TLI.isTypeLegal(TVT)) {
2226 // Turn this into a return of the vector type.
2227 Tmp2 = LegalizeOp(Tmp2);
2228 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2229 } else if (NumElems == 1) {
2230 // Turn this into a return of the scalar type.
2231 Tmp2 = ScalarizeVectorOp(Tmp2);
2232 Tmp2 = LegalizeOp(Tmp2);
2233 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2235 // FIXME: Returns of gcc generic vectors smaller than a legal type
2236 // should be returned in integer registers!
2238 // The scalarized value type may not be legal, e.g. it might require
2239 // promotion or expansion. Relegalize the return.
2240 Result = LegalizeOp(Result);
2242 // FIXME: Returns of gcc generic vectors larger than a legal vector
2243 // type should be returned by reference!
2245 SplitVectorOp(Tmp2, Lo, Hi);
2246 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2247 Result = LegalizeOp(Result);
2252 Tmp2 = PromoteOp(Node->getOperand(1));
2253 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2254 Result = LegalizeOp(Result);
2259 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2261 default: { // ret <values>
2262 SmallVector<SDValue, 8> NewValues;
2263 NewValues.push_back(Tmp1);
2264 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2265 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2267 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2268 NewValues.push_back(Node->getOperand(i+1));
2272 assert(!Node->getOperand(i).getValueType().isExtended() &&
2273 "FIXME: TODO: implement returning non-legal vector types!");
2274 ExpandOp(Node->getOperand(i), Lo, Hi);
2275 NewValues.push_back(Lo);
2276 NewValues.push_back(Node->getOperand(i+1));
2278 NewValues.push_back(Hi);
2279 NewValues.push_back(Node->getOperand(i+1));
2284 assert(0 && "Can't promote multiple return value yet!");
2287 if (NewValues.size() == Node->getNumOperands())
2288 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2290 Result = DAG.getNode(ISD::RET, MVT::Other,
2291 &NewValues[0], NewValues.size());
2296 if (Result.getOpcode() == ISD::RET) {
2297 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2298 default: assert(0 && "This action is not supported yet!");
2299 case TargetLowering::Legal: break;
2300 case TargetLowering::Custom:
2301 Tmp1 = TLI.LowerOperation(Result, DAG);
2302 if (Tmp1.Val) Result = Tmp1;
2308 StoreSDNode *ST = cast<StoreSDNode>(Node);
2309 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2310 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2311 int SVOffset = ST->getSrcValueOffset();
2312 unsigned Alignment = ST->getAlignment();
2313 bool isVolatile = ST->isVolatile();
2315 if (!ST->isTruncatingStore()) {
2316 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2317 // FIXME: We shouldn't do this for TargetConstantFP's.
2318 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2319 // to phase ordering between legalized code and the dag combiner. This
2320 // probably means that we need to integrate dag combiner and legalizer
2322 // We generally can't do this one for long doubles.
2323 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2324 if (CFP->getValueType(0) == MVT::f32 &&
2325 getTypeAction(MVT::i32) == Legal) {
2326 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2327 convertToAPInt().zextOrTrunc(32),
2329 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2330 SVOffset, isVolatile, Alignment);
2332 } else if (CFP->getValueType(0) == MVT::f64) {
2333 // If this target supports 64-bit registers, do a single 64-bit store.
2334 if (getTypeAction(MVT::i64) == Legal) {
2335 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2336 zextOrTrunc(64), MVT::i64);
2337 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2338 SVOffset, isVolatile, Alignment);
2340 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2341 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2342 // stores. If the target supports neither 32- nor 64-bits, this
2343 // xform is certainly not worth it.
2344 const APInt &IntVal =CFP->getValueAPF().convertToAPInt();
2345 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2346 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2347 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2349 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2350 SVOffset, isVolatile, Alignment);
2351 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2352 DAG.getIntPtrConstant(4));
2353 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2354 isVolatile, MinAlign(Alignment, 4U));
2356 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2362 switch (getTypeAction(ST->getMemoryVT())) {
2364 Tmp3 = LegalizeOp(ST->getValue());
2365 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2368 MVT VT = Tmp3.getValueType();
2369 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2370 default: assert(0 && "This action is not supported yet!");
2371 case TargetLowering::Legal:
2372 // If this is an unaligned store and the target doesn't support it,
2374 if (!TLI.allowsUnalignedMemoryAccesses()) {
2375 unsigned ABIAlignment = TLI.getTargetData()->
2376 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2377 if (ST->getAlignment() < ABIAlignment)
2378 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2382 case TargetLowering::Custom:
2383 Tmp1 = TLI.LowerOperation(Result, DAG);
2384 if (Tmp1.Val) Result = Tmp1;
2386 case TargetLowering::Promote:
2387 assert(VT.isVector() && "Unknown legal promote case!");
2388 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2389 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2390 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2391 ST->getSrcValue(), SVOffset, isVolatile,
2398 // Truncate the value and store the result.
2399 Tmp3 = PromoteOp(ST->getValue());
2400 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2401 SVOffset, ST->getMemoryVT(),
2402 isVolatile, Alignment);
2406 unsigned IncrementSize = 0;
2409 // If this is a vector type, then we have to calculate the increment as
2410 // the product of the element size in bytes, and the number of elements
2411 // in the high half of the vector.
2412 if (ST->getValue().getValueType().isVector()) {
2413 SDNode *InVal = ST->getValue().Val;
2414 int InIx = ST->getValue().getResNo();
2415 MVT InVT = InVal->getValueType(InIx);
2416 unsigned NumElems = InVT.getVectorNumElements();
2417 MVT EVT = InVT.getVectorElementType();
2419 // Figure out if there is a simple type corresponding to this Vector
2420 // type. If so, convert to the vector type.
2421 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2422 if (TLI.isTypeLegal(TVT)) {
2423 // Turn this into a normal store of the vector type.
2424 Tmp3 = LegalizeOp(ST->getValue());
2425 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2426 SVOffset, isVolatile, Alignment);
2427 Result = LegalizeOp(Result);
2429 } else if (NumElems == 1) {
2430 // Turn this into a normal store of the scalar type.
2431 Tmp3 = ScalarizeVectorOp(ST->getValue());
2432 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2433 SVOffset, isVolatile, Alignment);
2434 // The scalarized value type may not be legal, e.g. it might require
2435 // promotion or expansion. Relegalize the scalar store.
2436 Result = LegalizeOp(Result);
2439 SplitVectorOp(ST->getValue(), Lo, Hi);
2440 IncrementSize = Lo.Val->getValueType(0).getVectorNumElements() *
2441 EVT.getSizeInBits()/8;
2444 ExpandOp(ST->getValue(), Lo, Hi);
2445 IncrementSize = Hi.Val ? Hi.getValueType().getSizeInBits()/8 : 0;
2447 if (TLI.isBigEndian())
2451 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2452 SVOffset, isVolatile, Alignment);
2454 if (Hi.Val == NULL) {
2455 // Must be int <-> float one-to-one expansion.
2460 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2461 DAG.getIntPtrConstant(IncrementSize));
2462 assert(isTypeLegal(Tmp2.getValueType()) &&
2463 "Pointers must be legal!");
2464 SVOffset += IncrementSize;
2465 Alignment = MinAlign(Alignment, IncrementSize);
2466 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2467 SVOffset, isVolatile, Alignment);
2468 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2472 switch (getTypeAction(ST->getValue().getValueType())) {
2474 Tmp3 = LegalizeOp(ST->getValue());
2477 // We can promote the value, the truncstore will still take care of it.
2478 Tmp3 = PromoteOp(ST->getValue());
2481 // Just store the low part. This may become a non-trunc store, so make
2482 // sure to use getTruncStore, not UpdateNodeOperands below.
2483 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2484 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2485 SVOffset, MVT::i8, isVolatile, Alignment);
2488 MVT StVT = ST->getMemoryVT();
2489 unsigned StWidth = StVT.getSizeInBits();
2491 if (StWidth != StVT.getStoreSizeInBits()) {
2492 // Promote to a byte-sized store with upper bits zero if not
2493 // storing an integral number of bytes. For example, promote
2494 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2495 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2496 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2497 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2498 SVOffset, NVT, isVolatile, Alignment);
2499 } else if (StWidth & (StWidth - 1)) {
2500 // If not storing a power-of-2 number of bits, expand as two stores.
2501 assert(StVT.isExtended() && !StVT.isVector() &&
2502 "Unsupported truncstore!");
2503 unsigned RoundWidth = 1 << Log2_32(StWidth);
2504 assert(RoundWidth < StWidth);
2505 unsigned ExtraWidth = StWidth - RoundWidth;
2506 assert(ExtraWidth < RoundWidth);
2507 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2508 "Store size not an integral number of bytes!");
2509 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2510 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2512 unsigned IncrementSize;
2514 if (TLI.isLittleEndian()) {
2515 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2516 // Store the bottom RoundWidth bits.
2517 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2519 isVolatile, Alignment);
2521 // Store the remaining ExtraWidth bits.
2522 IncrementSize = RoundWidth / 8;
2523 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2524 DAG.getIntPtrConstant(IncrementSize));
2525 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2526 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2527 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2528 SVOffset + IncrementSize, ExtraVT, isVolatile,
2529 MinAlign(Alignment, IncrementSize));
2531 // Big endian - avoid unaligned stores.
2532 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2533 // Store the top RoundWidth bits.
2534 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2535 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2536 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2537 RoundVT, isVolatile, Alignment);
2539 // Store the remaining ExtraWidth bits.
2540 IncrementSize = RoundWidth / 8;
2541 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2542 DAG.getIntPtrConstant(IncrementSize));
2543 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2544 SVOffset + IncrementSize, ExtraVT, isVolatile,
2545 MinAlign(Alignment, IncrementSize));
2548 // The order of the stores doesn't matter.
2549 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2551 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2552 Tmp2 != ST->getBasePtr())
2553 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2556 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2557 default: assert(0 && "This action is not supported yet!");
2558 case TargetLowering::Legal:
2559 // If this is an unaligned store and the target doesn't support it,
2561 if (!TLI.allowsUnalignedMemoryAccesses()) {
2562 unsigned ABIAlignment = TLI.getTargetData()->
2563 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2564 if (ST->getAlignment() < ABIAlignment)
2565 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2569 case TargetLowering::Custom:
2570 Result = TLI.LowerOperation(Result, DAG);
2573 // TRUNCSTORE:i16 i32 -> STORE i16
2574 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2575 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2576 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2577 isVolatile, Alignment);
2585 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2586 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2588 case ISD::STACKSAVE:
2589 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2590 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2591 Tmp1 = Result.getValue(0);
2592 Tmp2 = Result.getValue(1);
2594 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2595 default: assert(0 && "This action is not supported yet!");
2596 case TargetLowering::Legal: break;
2597 case TargetLowering::Custom:
2598 Tmp3 = TLI.LowerOperation(Result, DAG);
2600 Tmp1 = LegalizeOp(Tmp3);
2601 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2604 case TargetLowering::Expand:
2605 // Expand to CopyFromReg if the target set
2606 // StackPointerRegisterToSaveRestore.
2607 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2608 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2609 Node->getValueType(0));
2610 Tmp2 = Tmp1.getValue(1);
2612 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2613 Tmp2 = Node->getOperand(0);
2618 // Since stacksave produce two values, make sure to remember that we
2619 // legalized both of them.
2620 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2621 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2622 return Op.getResNo() ? Tmp2 : Tmp1;
2624 case ISD::STACKRESTORE:
2625 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2626 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2627 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2629 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2630 default: assert(0 && "This action is not supported yet!");
2631 case TargetLowering::Legal: break;
2632 case TargetLowering::Custom:
2633 Tmp1 = TLI.LowerOperation(Result, DAG);
2634 if (Tmp1.Val) Result = Tmp1;
2636 case TargetLowering::Expand:
2637 // Expand to CopyToReg if the target set
2638 // StackPointerRegisterToSaveRestore.
2639 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2640 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2648 case ISD::READCYCLECOUNTER:
2649 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2650 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2651 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2652 Node->getValueType(0))) {
2653 default: assert(0 && "This action is not supported yet!");
2654 case TargetLowering::Legal:
2655 Tmp1 = Result.getValue(0);
2656 Tmp2 = Result.getValue(1);
2658 case TargetLowering::Custom:
2659 Result = TLI.LowerOperation(Result, DAG);
2660 Tmp1 = LegalizeOp(Result.getValue(0));
2661 Tmp2 = LegalizeOp(Result.getValue(1));
2665 // Since rdcc produce two values, make sure to remember that we legalized
2667 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2668 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2672 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2673 case Expand: assert(0 && "It's impossible to expand bools");
2675 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2678 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2679 // Make sure the condition is either zero or one.
2680 unsigned BitWidth = Tmp1.getValueSizeInBits();
2681 if (!DAG.MaskedValueIsZero(Tmp1,
2682 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2683 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2687 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2688 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2690 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2692 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2693 default: assert(0 && "This action is not supported yet!");
2694 case TargetLowering::Legal: break;
2695 case TargetLowering::Custom: {
2696 Tmp1 = TLI.LowerOperation(Result, DAG);
2697 if (Tmp1.Val) Result = Tmp1;
2700 case TargetLowering::Expand:
2701 if (Tmp1.getOpcode() == ISD::SETCC) {
2702 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2704 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2706 Result = DAG.getSelectCC(Tmp1,
2707 DAG.getConstant(0, Tmp1.getValueType()),
2708 Tmp2, Tmp3, ISD::SETNE);
2711 case TargetLowering::Promote: {
2713 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2714 unsigned ExtOp, TruncOp;
2715 if (Tmp2.getValueType().isVector()) {
2716 ExtOp = ISD::BIT_CONVERT;
2717 TruncOp = ISD::BIT_CONVERT;
2718 } else if (Tmp2.getValueType().isInteger()) {
2719 ExtOp = ISD::ANY_EXTEND;
2720 TruncOp = ISD::TRUNCATE;
2722 ExtOp = ISD::FP_EXTEND;
2723 TruncOp = ISD::FP_ROUND;
2725 // Promote each of the values to the new type.
2726 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2727 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2728 // Perform the larger operation, then round down.
2729 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2730 if (TruncOp != ISD::FP_ROUND)
2731 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2733 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2734 DAG.getIntPtrConstant(0));
2739 case ISD::SELECT_CC: {
2740 Tmp1 = Node->getOperand(0); // LHS
2741 Tmp2 = Node->getOperand(1); // RHS
2742 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2743 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2744 SDValue CC = Node->getOperand(4);
2746 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2748 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2749 // the LHS is a legal SETCC itself. In this case, we need to compare
2750 // the result against zero to select between true and false values.
2751 if (Tmp2.Val == 0) {
2752 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2753 CC = DAG.getCondCode(ISD::SETNE);
2755 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2757 // Everything is legal, see if we should expand this op or something.
2758 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2759 default: assert(0 && "This action is not supported yet!");
2760 case TargetLowering::Legal: break;
2761 case TargetLowering::Custom:
2762 Tmp1 = TLI.LowerOperation(Result, DAG);
2763 if (Tmp1.Val) Result = Tmp1;
2769 Tmp1 = Node->getOperand(0);
2770 Tmp2 = Node->getOperand(1);
2771 Tmp3 = Node->getOperand(2);
2772 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2774 // If we had to Expand the SetCC operands into a SELECT node, then it may
2775 // not always be possible to return a true LHS & RHS. In this case, just
2776 // return the value we legalized, returned in the LHS
2777 if (Tmp2.Val == 0) {
2782 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2783 default: assert(0 && "Cannot handle this action for SETCC yet!");
2784 case TargetLowering::Custom:
2787 case TargetLowering::Legal:
2788 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2790 Tmp4 = TLI.LowerOperation(Result, DAG);
2791 if (Tmp4.Val) Result = Tmp4;
2794 case TargetLowering::Promote: {
2795 // First step, figure out the appropriate operation to use.
2796 // Allow SETCC to not be supported for all legal data types
2797 // Mostly this targets FP
2798 MVT NewInTy = Node->getOperand(0).getValueType();
2799 MVT OldVT = NewInTy; OldVT = OldVT;
2801 // Scan for the appropriate larger type to use.
2803 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
2805 assert(NewInTy.isInteger() == OldVT.isInteger() &&
2806 "Fell off of the edge of the integer world");
2807 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
2808 "Fell off of the edge of the floating point world");
2810 // If the target supports SETCC of this type, use it.
2811 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2814 if (NewInTy.isInteger())
2815 assert(0 && "Cannot promote Legal Integer SETCC yet");
2817 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2818 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2820 Tmp1 = LegalizeOp(Tmp1);
2821 Tmp2 = LegalizeOp(Tmp2);
2822 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2823 Result = LegalizeOp(Result);
2826 case TargetLowering::Expand:
2827 // Expand a setcc node into a select_cc of the same condition, lhs, and
2828 // rhs that selects between const 1 (true) and const 0 (false).
2829 MVT VT = Node->getValueType(0);
2830 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2831 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2837 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2838 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2839 SDValue CC = Node->getOperand(2);
2841 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
2843 // Everything is legal, see if we should expand this op or something.
2844 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
2845 default: assert(0 && "This action is not supported yet!");
2846 case TargetLowering::Legal: break;
2847 case TargetLowering::Custom:
2848 Tmp1 = TLI.LowerOperation(Result, DAG);
2849 if (Tmp1.Val) Result = Tmp1;
2855 case ISD::SHL_PARTS:
2856 case ISD::SRA_PARTS:
2857 case ISD::SRL_PARTS: {
2858 SmallVector<SDValue, 8> Ops;
2859 bool Changed = false;
2860 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2861 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2862 Changed |= Ops.back() != Node->getOperand(i);
2865 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2867 switch (TLI.getOperationAction(Node->getOpcode(),
2868 Node->getValueType(0))) {
2869 default: assert(0 && "This action is not supported yet!");
2870 case TargetLowering::Legal: break;
2871 case TargetLowering::Custom:
2872 Tmp1 = TLI.LowerOperation(Result, DAG);
2874 SDValue Tmp2, RetVal(0, 0);
2875 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2876 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2877 AddLegalizedOperand(SDValue(Node, i), Tmp2);
2878 if (i == Op.getResNo())
2881 assert(RetVal.Val && "Illegal result number");
2887 // Since these produce multiple values, make sure to remember that we
2888 // legalized all of them.
2889 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2890 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
2891 return Result.getValue(Op.getResNo());
2913 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2914 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2915 case Expand: assert(0 && "Not possible");
2917 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2920 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2924 if ((Node->getOpcode() == ISD::SHL ||
2925 Node->getOpcode() == ISD::SRL ||
2926 Node->getOpcode() == ISD::SRA) &&
2927 !Node->getValueType(0).isVector()) {
2928 if (TLI.getShiftAmountTy().bitsLT(Tmp2.getValueType()))
2929 Tmp2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Tmp2);
2930 else if (TLI.getShiftAmountTy().bitsGT(Tmp2.getValueType()))
2931 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Tmp2);
2934 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2936 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2937 default: assert(0 && "BinOp legalize operation not supported");
2938 case TargetLowering::Legal: break;
2939 case TargetLowering::Custom:
2940 Tmp1 = TLI.LowerOperation(Result, DAG);
2945 // Fall through if the custom lower can't deal with the operation
2946 case TargetLowering::Expand: {
2947 MVT VT = Op.getValueType();
2949 // See if multiply or divide can be lowered using two-result operations.
2950 SDVTList VTs = DAG.getVTList(VT, VT);
2951 if (Node->getOpcode() == ISD::MUL) {
2952 // We just need the low half of the multiply; try both the signed
2953 // and unsigned forms. If the target supports both SMUL_LOHI and
2954 // UMUL_LOHI, form a preference by checking which forms of plain
2955 // MULH it supports.
2956 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2957 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2958 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2959 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2960 unsigned OpToUse = 0;
2961 if (HasSMUL_LOHI && !HasMULHS) {
2962 OpToUse = ISD::SMUL_LOHI;
2963 } else if (HasUMUL_LOHI && !HasMULHU) {
2964 OpToUse = ISD::UMUL_LOHI;
2965 } else if (HasSMUL_LOHI) {
2966 OpToUse = ISD::SMUL_LOHI;
2967 } else if (HasUMUL_LOHI) {
2968 OpToUse = ISD::UMUL_LOHI;
2971 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
2975 if (Node->getOpcode() == ISD::MULHS &&
2976 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
2977 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2980 if (Node->getOpcode() == ISD::MULHU &&
2981 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
2982 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2985 if (Node->getOpcode() == ISD::SDIV &&
2986 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
2987 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2990 if (Node->getOpcode() == ISD::UDIV &&
2991 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
2992 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2996 // Check to see if we have a libcall for this operator.
2997 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2998 bool isSigned = false;
2999 switch (Node->getOpcode()) {
3002 if (VT == MVT::i32) {
3003 LC = Node->getOpcode() == ISD::UDIV
3004 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3005 isSigned = Node->getOpcode() == ISD::SDIV;
3009 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3010 RTLIB::POW_PPCF128);
3014 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3016 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3020 assert(Node->getValueType(0).isVector() &&
3021 "Cannot expand this binary operator!");
3022 // Expand the operation into a bunch of nasty scalar code.
3023 Result = LegalizeOp(UnrollVectorOp(Op));
3026 case TargetLowering::Promote: {
3027 switch (Node->getOpcode()) {
3028 default: assert(0 && "Do not know how to promote this BinOp!");
3032 MVT OVT = Node->getValueType(0);
3033 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3034 assert(OVT.isVector() && "Cannot promote this BinOp!");
3035 // Bit convert each of the values to the new type.
3036 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3037 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3038 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3039 // Bit convert the result back the original type.
3040 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3048 case ISD::SMUL_LOHI:
3049 case ISD::UMUL_LOHI:
3052 // These nodes will only be produced by target-specific lowering, so
3053 // they shouldn't be here if they aren't legal.
3054 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3055 "This must be legal!");
3057 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3058 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3059 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3062 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3063 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3064 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3065 case Expand: assert(0 && "Not possible");
3067 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3070 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3074 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3076 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3077 default: assert(0 && "Operation not supported");
3078 case TargetLowering::Custom:
3079 Tmp1 = TLI.LowerOperation(Result, DAG);
3080 if (Tmp1.Val) Result = Tmp1;
3082 case TargetLowering::Legal: break;
3083 case TargetLowering::Expand: {
3084 // If this target supports fabs/fneg natively and select is cheap,
3085 // do this efficiently.
3086 if (!TLI.isSelectExpensive() &&
3087 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3088 TargetLowering::Legal &&
3089 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3090 TargetLowering::Legal) {
3091 // Get the sign bit of the RHS.
3093 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3094 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3095 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3096 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3097 // Get the absolute value of the result.
3098 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3099 // Select between the nabs and abs value based on the sign bit of
3101 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3102 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3105 Result = LegalizeOp(Result);
3109 // Otherwise, do bitwise ops!
3111 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3112 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3113 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3114 Result = LegalizeOp(Result);
3122 Tmp1 = LegalizeOp(Node->getOperand(0));
3123 Tmp2 = LegalizeOp(Node->getOperand(1));
3124 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3125 // Since this produces two values, make sure to remember that we legalized
3127 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
3128 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
3133 Tmp1 = LegalizeOp(Node->getOperand(0));
3134 Tmp2 = LegalizeOp(Node->getOperand(1));
3135 Tmp3 = LegalizeOp(Node->getOperand(2));
3136 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3137 // Since this produces two values, make sure to remember that we legalized
3139 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
3140 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
3143 case ISD::BUILD_PAIR: {
3144 MVT PairTy = Node->getValueType(0);
3145 // TODO: handle the case where the Lo and Hi operands are not of legal type
3146 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3147 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3148 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3149 case TargetLowering::Promote:
3150 case TargetLowering::Custom:
3151 assert(0 && "Cannot promote/custom this yet!");
3152 case TargetLowering::Legal:
3153 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3154 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3156 case TargetLowering::Expand:
3157 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3158 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3159 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3160 DAG.getConstant(PairTy.getSizeInBits()/2,
3161 TLI.getShiftAmountTy()));
3162 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3171 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3172 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3174 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3175 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3176 case TargetLowering::Custom:
3179 case TargetLowering::Legal:
3180 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3182 Tmp1 = TLI.LowerOperation(Result, DAG);
3183 if (Tmp1.Val) Result = Tmp1;
3186 case TargetLowering::Expand: {
3187 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3188 bool isSigned = DivOpc == ISD::SDIV;
3189 MVT VT = Node->getValueType(0);
3191 // See if remainder can be lowered using two-result operations.
3192 SDVTList VTs = DAG.getVTList(VT, VT);
3193 if (Node->getOpcode() == ISD::SREM &&
3194 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3195 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3198 if (Node->getOpcode() == ISD::UREM &&
3199 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3200 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3204 if (VT.isInteger()) {
3205 if (TLI.getOperationAction(DivOpc, VT) ==
3206 TargetLowering::Legal) {
3208 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3209 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3210 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3211 } else if (VT.isVector()) {
3212 Result = LegalizeOp(UnrollVectorOp(Op));
3214 assert(VT == MVT::i32 &&
3215 "Cannot expand this binary operator!");
3216 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3217 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3219 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3222 assert(VT.isFloatingPoint() &&
3223 "remainder op must have integer or floating-point type");
3224 if (VT.isVector()) {
3225 Result = LegalizeOp(UnrollVectorOp(Op));
3227 // Floating point mod -> fmod libcall.
3228 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3229 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3231 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3239 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3240 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3242 MVT VT = Node->getValueType(0);
3243 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3244 default: assert(0 && "This action is not supported yet!");
3245 case TargetLowering::Custom:
3248 case TargetLowering::Legal:
3249 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3250 Result = Result.getValue(0);
3251 Tmp1 = Result.getValue(1);
3254 Tmp2 = TLI.LowerOperation(Result, DAG);
3256 Result = LegalizeOp(Tmp2);
3257 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3261 case TargetLowering::Expand: {
3262 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3263 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3264 // Increment the pointer, VAList, to the next vaarg
3265 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3266 DAG.getConstant(VT.getSizeInBits()/8,
3267 TLI.getPointerTy()));
3268 // Store the incremented VAList to the legalized pointer
3269 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3270 // Load the actual argument out of the pointer VAList
3271 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3272 Tmp1 = LegalizeOp(Result.getValue(1));
3273 Result = LegalizeOp(Result);
3277 // Since VAARG produces two values, make sure to remember that we
3278 // legalized both of them.
3279 AddLegalizedOperand(SDValue(Node, 0), Result);
3280 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3281 return Op.getResNo() ? Tmp1 : Result;
3285 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3286 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3287 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3289 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3290 default: assert(0 && "This action is not supported yet!");
3291 case TargetLowering::Custom:
3294 case TargetLowering::Legal:
3295 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3296 Node->getOperand(3), Node->getOperand(4));
3298 Tmp1 = TLI.LowerOperation(Result, DAG);
3299 if (Tmp1.Val) Result = Tmp1;
3302 case TargetLowering::Expand:
3303 // This defaults to loading a pointer from the input and storing it to the
3304 // output, returning the chain.
3305 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3306 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3307 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3308 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3314 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3315 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3317 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3318 default: assert(0 && "This action is not supported yet!");
3319 case TargetLowering::Custom:
3322 case TargetLowering::Legal:
3323 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3325 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3326 if (Tmp1.Val) Result = Tmp1;
3329 case TargetLowering::Expand:
3330 Result = Tmp1; // Default to a no-op, return the chain
3336 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3337 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3339 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3341 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3342 default: assert(0 && "This action is not supported yet!");
3343 case TargetLowering::Legal: break;
3344 case TargetLowering::Custom:
3345 Tmp1 = TLI.LowerOperation(Result, DAG);
3346 if (Tmp1.Val) Result = Tmp1;
3353 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3354 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3355 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3356 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3358 assert(0 && "ROTL/ROTR legalize operation not supported");
3360 case TargetLowering::Legal:
3362 case TargetLowering::Custom:
3363 Tmp1 = TLI.LowerOperation(Result, DAG);
3364 if (Tmp1.Val) Result = Tmp1;
3366 case TargetLowering::Promote:
3367 assert(0 && "Do not know how to promote ROTL/ROTR");
3369 case TargetLowering::Expand:
3370 assert(0 && "Do not know how to expand ROTL/ROTR");
3376 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3377 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3378 case TargetLowering::Custom:
3379 assert(0 && "Cannot custom legalize this yet!");
3380 case TargetLowering::Legal:
3381 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3383 case TargetLowering::Promote: {
3384 MVT OVT = Tmp1.getValueType();
3385 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3386 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3388 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3389 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3390 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3391 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3394 case TargetLowering::Expand:
3395 Result = ExpandBSWAP(Tmp1);
3403 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3404 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3405 case TargetLowering::Custom:
3406 case TargetLowering::Legal:
3407 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3408 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3409 TargetLowering::Custom) {
3410 Tmp1 = TLI.LowerOperation(Result, DAG);
3416 case TargetLowering::Promote: {
3417 MVT OVT = Tmp1.getValueType();
3418 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3420 // Zero extend the argument.
3421 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3422 // Perform the larger operation, then subtract if needed.
3423 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3424 switch (Node->getOpcode()) {
3429 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3430 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3431 DAG.getConstant(NVT.getSizeInBits(), NVT),
3433 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3434 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3437 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3438 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3439 DAG.getConstant(NVT.getSizeInBits() -
3440 OVT.getSizeInBits(), NVT));
3445 case TargetLowering::Expand:
3446 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3461 case ISD::FNEARBYINT:
3462 Tmp1 = LegalizeOp(Node->getOperand(0));
3463 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3464 case TargetLowering::Promote:
3465 case TargetLowering::Custom:
3468 case TargetLowering::Legal:
3469 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3471 Tmp1 = TLI.LowerOperation(Result, DAG);
3472 if (Tmp1.Val) Result = Tmp1;
3475 case TargetLowering::Expand:
3476 switch (Node->getOpcode()) {
3477 default: assert(0 && "Unreachable!");
3479 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3480 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3481 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3484 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3485 MVT VT = Node->getValueType(0);
3486 Tmp2 = DAG.getConstantFP(0.0, VT);
3487 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3489 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3490 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3497 case ISD::FNEARBYINT:
3501 MVT VT = Node->getValueType(0);
3503 // Expand unsupported unary vector operators by unrolling them.
3504 if (VT.isVector()) {
3505 Result = LegalizeOp(UnrollVectorOp(Op));
3509 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3510 switch(Node->getOpcode()) {
3512 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3513 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3516 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3517 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3520 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3521 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3524 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3525 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3528 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3529 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3532 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3533 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3536 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3537 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3539 case ISD::FNEARBYINT:
3540 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3541 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3543 default: assert(0 && "Unreachable!");
3546 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3554 MVT VT = Node->getValueType(0);
3556 // Expand unsupported unary vector operators by unrolling them.
3557 if (VT.isVector()) {
3558 Result = LegalizeOp(UnrollVectorOp(Op));
3562 // We always lower FPOWI into a libcall. No target support for it yet.
3563 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3564 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3566 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3569 case ISD::BIT_CONVERT:
3570 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3571 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3572 Node->getValueType(0));
3573 } else if (Op.getOperand(0).getValueType().isVector()) {
3574 // The input has to be a vector type, we have to either scalarize it, pack
3575 // it, or convert it based on whether the input vector type is legal.
3576 SDNode *InVal = Node->getOperand(0).Val;
3577 int InIx = Node->getOperand(0).getResNo();
3578 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3579 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3581 // Figure out if there is a simple type corresponding to this Vector
3582 // type. If so, convert to the vector type.
3583 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3584 if (TLI.isTypeLegal(TVT)) {
3585 // Turn this into a bit convert of the vector input.
3586 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3587 LegalizeOp(Node->getOperand(0)));
3589 } else if (NumElems == 1) {
3590 // Turn this into a bit convert of the scalar input.
3591 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3592 ScalarizeVectorOp(Node->getOperand(0)));
3595 // FIXME: UNIMP! Store then reload
3596 assert(0 && "Cast from unsupported vector type not implemented yet!");
3599 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3600 Node->getOperand(0).getValueType())) {
3601 default: assert(0 && "Unknown operation action!");
3602 case TargetLowering::Expand:
3603 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3604 Node->getValueType(0));
3606 case TargetLowering::Legal:
3607 Tmp1 = LegalizeOp(Node->getOperand(0));
3608 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3614 // Conversion operators. The source and destination have different types.
3615 case ISD::SINT_TO_FP:
3616 case ISD::UINT_TO_FP: {
3617 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3618 Result = LegalizeINT_TO_FP(Result, isSigned,
3619 Node->getValueType(0), Node->getOperand(0));
3623 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3625 Tmp1 = LegalizeOp(Node->getOperand(0));
3626 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3629 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3631 // Since the result is legal, we should just be able to truncate the low
3632 // part of the source.
3633 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3636 Result = PromoteOp(Node->getOperand(0));
3637 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3642 case ISD::FP_TO_SINT:
3643 case ISD::FP_TO_UINT:
3644 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3646 Tmp1 = LegalizeOp(Node->getOperand(0));
3648 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3649 default: assert(0 && "Unknown operation action!");
3650 case TargetLowering::Custom:
3653 case TargetLowering::Legal:
3654 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3656 Tmp1 = TLI.LowerOperation(Result, DAG);
3657 if (Tmp1.Val) Result = Tmp1;
3660 case TargetLowering::Promote:
3661 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3662 Node->getOpcode() == ISD::FP_TO_SINT);
3664 case TargetLowering::Expand:
3665 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3666 SDValue True, False;
3667 MVT VT = Node->getOperand(0).getValueType();
3668 MVT NVT = Node->getValueType(0);
3669 const uint64_t zero[] = {0, 0};
3670 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
3671 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3672 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3673 Tmp2 = DAG.getConstantFP(apf, VT);
3674 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
3675 Node->getOperand(0), Tmp2, ISD::SETLT);
3676 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3677 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3678 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3680 False = DAG.getNode(ISD::XOR, NVT, False,
3681 DAG.getConstant(x, NVT));
3682 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3685 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3691 MVT VT = Op.getValueType();
3692 MVT OVT = Node->getOperand(0).getValueType();
3693 // Convert ppcf128 to i32
3694 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3695 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3696 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3697 Node->getOperand(0), DAG.getValueType(MVT::f64));
3698 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3699 DAG.getIntPtrConstant(1));
3700 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3702 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3703 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3704 Tmp2 = DAG.getConstantFP(apf, OVT);
3705 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3706 // FIXME: generated code sucks.
3707 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3708 DAG.getNode(ISD::ADD, MVT::i32,
3709 DAG.getNode(ISD::FP_TO_SINT, VT,
3710 DAG.getNode(ISD::FSUB, OVT,
3711 Node->getOperand(0), Tmp2)),
3712 DAG.getConstant(0x80000000, MVT::i32)),
3713 DAG.getNode(ISD::FP_TO_SINT, VT,
3714 Node->getOperand(0)),
3715 DAG.getCondCode(ISD::SETGE));
3719 // Convert f32 / f64 to i32 / i64 / i128.
3720 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
3721 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
3722 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
3724 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3728 Tmp1 = PromoteOp(Node->getOperand(0));
3729 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3730 Result = LegalizeOp(Result);
3735 case ISD::FP_EXTEND: {
3736 MVT DstVT = Op.getValueType();
3737 MVT SrcVT = Op.getOperand(0).getValueType();
3738 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3739 // The only other way we can lower this is to turn it into a STORE,
3740 // LOAD pair, targetting a temporary location (a stack slot).
3741 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3744 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3745 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3747 Tmp1 = LegalizeOp(Node->getOperand(0));
3748 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3751 Tmp1 = PromoteOp(Node->getOperand(0));
3752 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3757 case ISD::FP_ROUND: {
3758 MVT DstVT = Op.getValueType();
3759 MVT SrcVT = Op.getOperand(0).getValueType();
3760 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3761 if (SrcVT == MVT::ppcf128) {
3763 ExpandOp(Node->getOperand(0), Lo, Result);
3764 // Round it the rest of the way (e.g. to f32) if needed.
3765 if (DstVT!=MVT::f64)
3766 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3769 // The only other way we can lower this is to turn it into a STORE,
3770 // LOAD pair, targetting a temporary location (a stack slot).
3771 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3774 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3775 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3777 Tmp1 = LegalizeOp(Node->getOperand(0));
3778 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3781 Tmp1 = PromoteOp(Node->getOperand(0));
3782 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3783 Node->getOperand(1));
3788 case ISD::ANY_EXTEND:
3789 case ISD::ZERO_EXTEND:
3790 case ISD::SIGN_EXTEND:
3791 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3792 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3794 Tmp1 = LegalizeOp(Node->getOperand(0));
3795 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3796 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3797 TargetLowering::Custom) {
3798 Tmp1 = TLI.LowerOperation(Result, DAG);
3799 if (Tmp1.Val) Result = Tmp1;
3803 switch (Node->getOpcode()) {
3804 case ISD::ANY_EXTEND:
3805 Tmp1 = PromoteOp(Node->getOperand(0));
3806 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3808 case ISD::ZERO_EXTEND:
3809 Result = PromoteOp(Node->getOperand(0));
3810 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3811 Result = DAG.getZeroExtendInReg(Result,
3812 Node->getOperand(0).getValueType());
3814 case ISD::SIGN_EXTEND:
3815 Result = PromoteOp(Node->getOperand(0));
3816 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3817 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3819 DAG.getValueType(Node->getOperand(0).getValueType()));
3824 case ISD::FP_ROUND_INREG:
3825 case ISD::SIGN_EXTEND_INREG: {
3826 Tmp1 = LegalizeOp(Node->getOperand(0));
3827 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3829 // If this operation is not supported, convert it to a shl/shr or load/store
3831 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3832 default: assert(0 && "This action not supported for this op yet!");
3833 case TargetLowering::Legal:
3834 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3836 case TargetLowering::Expand:
3837 // If this is an integer extend and shifts are supported, do that.
3838 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3839 // NOTE: we could fall back on load/store here too for targets without
3840 // SAR. However, it is doubtful that any exist.
3841 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
3842 ExtraVT.getSizeInBits();
3843 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3844 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3845 Node->getOperand(0), ShiftCst);
3846 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3848 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3849 // The only way we can lower this is to turn it into a TRUNCSTORE,
3850 // EXTLOAD pair, targetting a temporary location (a stack slot).
3852 // NOTE: there is a choice here between constantly creating new stack
3853 // slots and always reusing the same one. We currently always create
3854 // new ones, as reuse may inhibit scheduling.
3855 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3856 Node->getValueType(0));
3858 assert(0 && "Unknown op");
3864 case ISD::TRAMPOLINE: {
3866 for (unsigned i = 0; i != 6; ++i)
3867 Ops[i] = LegalizeOp(Node->getOperand(i));
3868 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3869 // The only option for this node is to custom lower it.
3870 Result = TLI.LowerOperation(Result, DAG);
3871 assert(Result.Val && "Should always custom lower!");
3873 // Since trampoline produces two values, make sure to remember that we
3874 // legalized both of them.
3875 Tmp1 = LegalizeOp(Result.getValue(1));
3876 Result = LegalizeOp(Result);
3877 AddLegalizedOperand(SDValue(Node, 0), Result);
3878 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3879 return Op.getResNo() ? Tmp1 : Result;
3881 case ISD::FLT_ROUNDS_: {
3882 MVT VT = Node->getValueType(0);
3883 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3884 default: assert(0 && "This action not supported for this op yet!");
3885 case TargetLowering::Custom:
3886 Result = TLI.LowerOperation(Op, DAG);
3887 if (Result.Val) break;
3889 case TargetLowering::Legal:
3890 // If this operation is not supported, lower it to constant 1
3891 Result = DAG.getConstant(1, VT);
3897 MVT VT = Node->getValueType(0);
3898 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3899 default: assert(0 && "This action not supported for this op yet!");
3900 case TargetLowering::Legal:
3901 Tmp1 = LegalizeOp(Node->getOperand(0));
3902 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3904 case TargetLowering::Custom:
3905 Result = TLI.LowerOperation(Op, DAG);
3906 if (Result.Val) break;
3908 case TargetLowering::Expand:
3909 // If this operation is not supported, lower it to 'abort()' call
3910 Tmp1 = LegalizeOp(Node->getOperand(0));
3911 TargetLowering::ArgListTy Args;
3912 std::pair<SDValue,SDValue> CallResult =
3913 TLI.LowerCallTo(Tmp1, Type::VoidTy,
3914 false, false, false, CallingConv::C, false,
3915 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3917 Result = CallResult.second;
3924 assert(Result.getValueType() == Op.getValueType() &&
3925 "Bad legalization!");
3927 // Make sure that the generated code is itself legal.
3929 Result = LegalizeOp(Result);
3931 // Note that LegalizeOp may be reentered even from single-use nodes, which
3932 // means that we always must cache transformed nodes.
3933 AddLegalizedOperand(Op, Result);
3937 /// PromoteOp - Given an operation that produces a value in an invalid type,
3938 /// promote it to compute the value into a larger type. The produced value will
3939 /// have the correct bits for the low portion of the register, but no guarantee
3940 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3941 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
3942 MVT VT = Op.getValueType();
3943 MVT NVT = TLI.getTypeToTransformTo(VT);
3944 assert(getTypeAction(VT) == Promote &&
3945 "Caller should expand or legalize operands that are not promotable!");
3946 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
3947 "Cannot promote to smaller type!");
3949 SDValue Tmp1, Tmp2, Tmp3;
3951 SDNode *Node = Op.Val;
3953 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
3954 if (I != PromotedNodes.end()) return I->second;
3956 switch (Node->getOpcode()) {
3957 case ISD::CopyFromReg:
3958 assert(0 && "CopyFromReg must be legal!");
3961 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
3963 assert(0 && "Do not know how to promote this operator!");
3966 Result = DAG.getNode(ISD::UNDEF, NVT);
3970 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3972 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3973 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3975 case ISD::ConstantFP:
3976 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3977 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3981 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
3982 && "SetCC type is not legal??");
3983 Result = DAG.getNode(ISD::SETCC,
3984 TLI.getSetCCResultType(Node->getOperand(0)),
3985 Node->getOperand(0), Node->getOperand(1),
3986 Node->getOperand(2));
3990 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3992 Result = LegalizeOp(Node->getOperand(0));
3993 assert(Result.getValueType().bitsGE(NVT) &&
3994 "This truncation doesn't make sense!");
3995 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
3996 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3999 // The truncation is not required, because we don't guarantee anything
4000 // about high bits anyway.
4001 Result = PromoteOp(Node->getOperand(0));
4004 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4005 // Truncate the low part of the expanded value to the result type
4006 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4009 case ISD::SIGN_EXTEND:
4010 case ISD::ZERO_EXTEND:
4011 case ISD::ANY_EXTEND:
4012 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4013 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4015 // Input is legal? Just do extend all the way to the larger type.
4016 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4019 // Promote the reg if it's smaller.
4020 Result = PromoteOp(Node->getOperand(0));
4021 // The high bits are not guaranteed to be anything. Insert an extend.
4022 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4023 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4024 DAG.getValueType(Node->getOperand(0).getValueType()));
4025 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4026 Result = DAG.getZeroExtendInReg(Result,
4027 Node->getOperand(0).getValueType());
4031 case ISD::BIT_CONVERT:
4032 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4033 Node->getValueType(0));
4034 Result = PromoteOp(Result);
4037 case ISD::FP_EXTEND:
4038 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4040 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4041 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4042 case Promote: assert(0 && "Unreachable with 2 FP types!");
4044 if (Node->getConstantOperandVal(1) == 0) {
4045 // Input is legal? Do an FP_ROUND_INREG.
4046 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4047 DAG.getValueType(VT));
4049 // Just remove the truncate, it isn't affecting the value.
4050 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4051 Node->getOperand(1));
4056 case ISD::SINT_TO_FP:
4057 case ISD::UINT_TO_FP:
4058 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4060 // No extra round required here.
4061 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4065 Result = PromoteOp(Node->getOperand(0));
4066 if (Node->getOpcode() == ISD::SINT_TO_FP)
4067 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4069 DAG.getValueType(Node->getOperand(0).getValueType()));
4071 Result = DAG.getZeroExtendInReg(Result,
4072 Node->getOperand(0).getValueType());
4073 // No extra round required here.
4074 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4077 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4078 Node->getOperand(0));
4079 // Round if we cannot tolerate excess precision.
4080 if (NoExcessFPPrecision)
4081 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4082 DAG.getValueType(VT));
4087 case ISD::SIGN_EXTEND_INREG:
4088 Result = PromoteOp(Node->getOperand(0));
4089 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4090 Node->getOperand(1));
4092 case ISD::FP_TO_SINT:
4093 case ISD::FP_TO_UINT:
4094 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4097 Tmp1 = Node->getOperand(0);
4100 // The input result is prerounded, so we don't have to do anything
4102 Tmp1 = PromoteOp(Node->getOperand(0));
4105 // If we're promoting a UINT to a larger size, check to see if the new node
4106 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4107 // we can use that instead. This allows us to generate better code for
4108 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4109 // legal, such as PowerPC.
4110 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4111 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4112 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4113 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4114 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4116 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4122 Tmp1 = PromoteOp(Node->getOperand(0));
4123 assert(Tmp1.getValueType() == NVT);
4124 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4125 // NOTE: we do not have to do any extra rounding here for
4126 // NoExcessFPPrecision, because we know the input will have the appropriate
4127 // precision, and these operations don't modify precision at all.
4137 case ISD::FNEARBYINT:
4138 Tmp1 = PromoteOp(Node->getOperand(0));
4139 assert(Tmp1.getValueType() == NVT);
4140 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4141 if (NoExcessFPPrecision)
4142 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4143 DAG.getValueType(VT));
4147 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4148 // directly as well, which may be better.
4149 Tmp1 = PromoteOp(Node->getOperand(0));
4150 assert(Tmp1.getValueType() == NVT);
4151 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4152 if (NoExcessFPPrecision)
4153 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4154 DAG.getValueType(VT));
4158 case ISD::ATOMIC_CMP_SWAP: {
4159 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4160 Tmp2 = PromoteOp(Node->getOperand(2));
4161 Tmp3 = PromoteOp(Node->getOperand(3));
4162 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4163 AtomNode->getBasePtr(), Tmp2, Tmp3,
4164 AtomNode->getSrcValue(),
4165 AtomNode->getAlignment());
4166 // Remember that we legalized the chain.
4167 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4170 case ISD::ATOMIC_LOAD_ADD:
4171 case ISD::ATOMIC_LOAD_SUB:
4172 case ISD::ATOMIC_LOAD_AND:
4173 case ISD::ATOMIC_LOAD_OR:
4174 case ISD::ATOMIC_LOAD_XOR:
4175 case ISD::ATOMIC_LOAD_NAND:
4176 case ISD::ATOMIC_LOAD_MIN:
4177 case ISD::ATOMIC_LOAD_MAX:
4178 case ISD::ATOMIC_LOAD_UMIN:
4179 case ISD::ATOMIC_LOAD_UMAX:
4180 case ISD::ATOMIC_SWAP: {
4181 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4182 Tmp2 = PromoteOp(Node->getOperand(2));
4183 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4184 AtomNode->getBasePtr(), Tmp2,
4185 AtomNode->getSrcValue(),
4186 AtomNode->getAlignment());
4187 // Remember that we legalized the chain.
4188 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4198 // The input may have strange things in the top bits of the registers, but
4199 // these operations don't care. They may have weird bits going out, but
4200 // that too is okay if they are integer operations.
4201 Tmp1 = PromoteOp(Node->getOperand(0));
4202 Tmp2 = PromoteOp(Node->getOperand(1));
4203 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4204 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4209 Tmp1 = PromoteOp(Node->getOperand(0));
4210 Tmp2 = PromoteOp(Node->getOperand(1));
4211 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4212 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4214 // Floating point operations will give excess precision that we may not be
4215 // able to tolerate. If we DO allow excess precision, just leave it,
4216 // otherwise excise it.
4217 // FIXME: Why would we need to round FP ops more than integer ones?
4218 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4219 if (NoExcessFPPrecision)
4220 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4221 DAG.getValueType(VT));
4226 // These operators require that their input be sign extended.
4227 Tmp1 = PromoteOp(Node->getOperand(0));
4228 Tmp2 = PromoteOp(Node->getOperand(1));
4229 if (NVT.isInteger()) {
4230 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4231 DAG.getValueType(VT));
4232 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4233 DAG.getValueType(VT));
4235 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4237 // Perform FP_ROUND: this is probably overly pessimistic.
4238 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4239 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4240 DAG.getValueType(VT));
4244 case ISD::FCOPYSIGN:
4245 // These operators require that their input be fp extended.
4246 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4247 case Expand: assert(0 && "not implemented");
4248 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4249 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4251 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4252 case Expand: assert(0 && "not implemented");
4253 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4254 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4256 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4258 // Perform FP_ROUND: this is probably overly pessimistic.
4259 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4260 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4261 DAG.getValueType(VT));
4266 // These operators require that their input be zero extended.
4267 Tmp1 = PromoteOp(Node->getOperand(0));
4268 Tmp2 = PromoteOp(Node->getOperand(1));
4269 assert(NVT.isInteger() && "Operators don't apply to FP!");
4270 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4271 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4272 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4276 Tmp1 = PromoteOp(Node->getOperand(0));
4277 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4280 // The input value must be properly sign extended.
4281 Tmp1 = PromoteOp(Node->getOperand(0));
4282 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4283 DAG.getValueType(VT));
4284 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4287 // The input value must be properly zero extended.
4288 Tmp1 = PromoteOp(Node->getOperand(0));
4289 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4290 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4294 Tmp1 = Node->getOperand(0); // Get the chain.
4295 Tmp2 = Node->getOperand(1); // Get the pointer.
4296 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4297 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4298 Result = TLI.LowerOperation(Tmp3, DAG);
4300 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4301 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4302 // Increment the pointer, VAList, to the next vaarg
4303 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4304 DAG.getConstant(VT.getSizeInBits()/8,
4305 TLI.getPointerTy()));
4306 // Store the incremented VAList to the legalized pointer
4307 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4308 // Load the actual argument out of the pointer VAList
4309 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4311 // Remember that we legalized the chain.
4312 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4316 LoadSDNode *LD = cast<LoadSDNode>(Node);
4317 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4318 ? ISD::EXTLOAD : LD->getExtensionType();
4319 Result = DAG.getExtLoad(ExtType, NVT,
4320 LD->getChain(), LD->getBasePtr(),
4321 LD->getSrcValue(), LD->getSrcValueOffset(),
4324 LD->getAlignment());
4325 // Remember that we legalized the chain.
4326 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4330 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4331 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4333 MVT VT2 = Tmp2.getValueType();
4334 assert(VT2 == Tmp3.getValueType()
4335 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4336 // Ensure that the resulting node is at least the same size as the operands'
4337 // value types, because we cannot assume that TLI.getSetCCValueType() is
4339 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4342 case ISD::SELECT_CC:
4343 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4344 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4345 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4346 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4349 Tmp1 = Node->getOperand(0);
4350 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4351 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4352 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4353 DAG.getConstant(NVT.getSizeInBits() -
4355 TLI.getShiftAmountTy()));
4360 // Zero extend the argument
4361 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4362 // Perform the larger operation, then subtract if needed.
4363 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4364 switch(Node->getOpcode()) {
4369 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4370 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4371 DAG.getConstant(NVT.getSizeInBits(), NVT),
4373 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4374 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4377 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4378 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4379 DAG.getConstant(NVT.getSizeInBits() -
4380 VT.getSizeInBits(), NVT));
4384 case ISD::EXTRACT_SUBVECTOR:
4385 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4387 case ISD::EXTRACT_VECTOR_ELT:
4388 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4392 assert(Result.Val && "Didn't set a result!");
4394 // Make sure the result is itself legal.
4395 Result = LegalizeOp(Result);
4397 // Remember that we promoted this!
4398 AddPromotedOperand(Op, Result);
4402 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4403 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4404 /// based on the vector type. The return type of this matches the element type
4405 /// of the vector, which may not be legal for the target.
4406 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
4407 // We know that operand #0 is the Vec vector. If the index is a constant
4408 // or if the invec is a supported hardware type, we can use it. Otherwise,
4409 // lower to a store then an indexed load.
4410 SDValue Vec = Op.getOperand(0);
4411 SDValue Idx = Op.getOperand(1);
4413 MVT TVT = Vec.getValueType();
4414 unsigned NumElems = TVT.getVectorNumElements();
4416 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4417 default: assert(0 && "This action is not supported yet!");
4418 case TargetLowering::Custom: {
4419 Vec = LegalizeOp(Vec);
4420 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4421 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
4426 case TargetLowering::Legal:
4427 if (isTypeLegal(TVT)) {
4428 Vec = LegalizeOp(Vec);
4429 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4433 case TargetLowering::Expand:
4437 if (NumElems == 1) {
4438 // This must be an access of the only element. Return it.
4439 Op = ScalarizeVectorOp(Vec);
4440 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4441 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4442 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4444 SplitVectorOp(Vec, Lo, Hi);
4445 if (CIdx->getValue() < NumLoElts) {
4449 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4450 Idx.getValueType());
4453 // It's now an extract from the appropriate high or low part. Recurse.
4454 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4455 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4457 // Store the value to a temporary stack slot, then LOAD the scalar
4458 // element back out.
4459 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4460 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4462 // Add the offset to the index.
4463 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
4464 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4465 DAG.getConstant(EltSize, Idx.getValueType()));
4467 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
4468 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4470 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4472 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4474 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4479 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4480 /// we assume the operation can be split if it is not already legal.
4481 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
4482 // We know that operand #0 is the Vec vector. For now we assume the index
4483 // is a constant and that the extracted result is a supported hardware type.
4484 SDValue Vec = Op.getOperand(0);
4485 SDValue Idx = LegalizeOp(Op.getOperand(1));
4487 unsigned NumElems = Vec.getValueType().getVectorNumElements();
4489 if (NumElems == Op.getValueType().getVectorNumElements()) {
4490 // This must be an access of the desired vector length. Return it.
4494 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4496 SplitVectorOp(Vec, Lo, Hi);
4497 if (CIdx->getValue() < NumElems/2) {
4501 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4504 // It's now an extract from the appropriate high or low part. Recurse.
4505 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4506 return ExpandEXTRACT_SUBVECTOR(Op);
4509 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4510 /// with condition CC on the current target. This usually involves legalizing
4511 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4512 /// there may be no choice but to create a new SetCC node to represent the
4513 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4514 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
4515 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
4518 SDValue Tmp1, Tmp2, Tmp3, Result;
4520 switch (getTypeAction(LHS.getValueType())) {
4522 Tmp1 = LegalizeOp(LHS); // LHS
4523 Tmp2 = LegalizeOp(RHS); // RHS
4526 Tmp1 = PromoteOp(LHS); // LHS
4527 Tmp2 = PromoteOp(RHS); // RHS
4529 // If this is an FP compare, the operands have already been extended.
4530 if (LHS.getValueType().isInteger()) {
4531 MVT VT = LHS.getValueType();
4532 MVT NVT = TLI.getTypeToTransformTo(VT);
4534 // Otherwise, we have to insert explicit sign or zero extends. Note
4535 // that we could insert sign extends for ALL conditions, but zero extend
4536 // is cheaper on many machines (an AND instead of two shifts), so prefer
4538 switch (cast<CondCodeSDNode>(CC)->get()) {
4539 default: assert(0 && "Unknown integer comparison!");
4546 // ALL of these operations will work if we either sign or zero extend
4547 // the operands (including the unsigned comparisons!). Zero extend is
4548 // usually a simpler/cheaper operation, so prefer it.
4549 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4550 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4556 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4557 DAG.getValueType(VT));
4558 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4559 DAG.getValueType(VT));
4565 MVT VT = LHS.getValueType();
4566 if (VT == MVT::f32 || VT == MVT::f64) {
4567 // Expand into one or more soft-fp libcall(s).
4568 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
4569 switch (cast<CondCodeSDNode>(CC)->get()) {
4572 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4576 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4580 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4584 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4588 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4592 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4595 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4598 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4601 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4602 switch (cast<CondCodeSDNode>(CC)->get()) {
4604 // SETONE = SETOLT | SETOGT
4605 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4608 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4611 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4614 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4617 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4620 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4622 default: assert(0 && "Unsupported FP setcc!");
4627 SDValue Ops[2] = { LHS, RHS };
4628 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).Val,
4629 false /*sign irrelevant*/, Dummy);
4630 Tmp2 = DAG.getConstant(0, MVT::i32);
4631 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4632 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4633 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
4635 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).Val,
4636 false /*sign irrelevant*/, Dummy);
4637 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
4638 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4639 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4642 LHS = LegalizeOp(Tmp1);
4647 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
4648 ExpandOp(LHS, LHSLo, LHSHi);
4649 ExpandOp(RHS, RHSLo, RHSHi);
4650 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4652 if (VT==MVT::ppcf128) {
4653 // FIXME: This generated code sucks. We want to generate
4654 // FCMP crN, hi1, hi2
4656 // FCMP crN, lo1, lo2
4657 // The following can be improved, but not that much.
4658 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
4659 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
4660 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4661 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE);
4662 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
4663 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4664 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4673 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4674 if (RHSCST->isAllOnesValue()) {
4675 // Comparison to -1.
4676 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4681 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4682 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4683 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4684 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4687 // If this is a comparison of the sign bit, just look at the top part.
4689 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4690 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4691 CST->isNullValue()) || // X < 0
4692 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4693 CST->isAllOnesValue())) { // X > -1
4699 // FIXME: This generated code sucks.
4700 ISD::CondCode LowCC;
4702 default: assert(0 && "Unknown integer setcc!");
4704 case ISD::SETULT: LowCC = ISD::SETULT; break;
4706 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4708 case ISD::SETULE: LowCC = ISD::SETULE; break;
4710 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4713 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4714 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4715 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4717 // NOTE: on targets without efficient SELECT of bools, we can always use
4718 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4719 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4720 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
4721 LowCC, false, DagCombineInfo);
4723 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
4724 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4725 CCCode, false, DagCombineInfo);
4727 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
4730 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4731 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4732 if ((Tmp1C && Tmp1C->isNullValue()) ||
4733 (Tmp2C && Tmp2C->isNullValue() &&
4734 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4735 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4736 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
4737 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4738 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4739 // low part is known false, returns high part.
4740 // For LE / GE, if high part is known false, ignore the low part.
4741 // For LT / GT, if high part is known true, ignore the low part.
4745 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4746 ISD::SETEQ, false, DagCombineInfo);
4748 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4750 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4751 Result, Tmp1, Tmp2));
4762 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4763 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4764 /// a load from the stack slot to DestVT, extending it if needed.
4765 /// The resultant code need not be legal.
4766 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
4769 // Create the stack frame object.
4770 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
4771 SrcOp.getValueType().getTypeForMVT());
4772 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
4774 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4775 int SPFI = StackPtrFI->getIndex();
4777 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
4778 unsigned SlotSize = SlotVT.getSizeInBits();
4779 unsigned DestSize = DestVT.getSizeInBits();
4780 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
4781 DestVT.getTypeForMVT());
4783 // Emit a store to the stack slot. Use a truncstore if the input value is
4784 // later than DestVT.
4787 if (SrcSize > SlotSize)
4788 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4789 PseudoSourceValue::getFixedStack(SPFI), 0,
4790 SlotVT, false, SrcAlign);
4792 assert(SrcSize == SlotSize && "Invalid store");
4793 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4794 PseudoSourceValue::getFixedStack(SPFI), 0,
4798 // Result is a load from the stack slot.
4799 if (SlotSize == DestSize)
4800 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
4802 assert(SlotSize < DestSize && "Unknown extension!");
4803 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
4807 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4808 // Create a vector sized/aligned stack slot, store the value to element #0,
4809 // then load the whole vector back out.
4810 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4812 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4813 int SPFI = StackPtrFI->getIndex();
4815 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4816 PseudoSourceValue::getFixedStack(SPFI), 0);
4817 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4818 PseudoSourceValue::getFixedStack(SPFI), 0);
4822 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4823 /// support the operation, but do support the resultant vector type.
4824 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4826 // If the only non-undef value is the low element, turn this into a
4827 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4828 unsigned NumElems = Node->getNumOperands();
4829 bool isOnlyLowElement = true;
4830 SDValue SplatValue = Node->getOperand(0);
4832 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
4833 // and use a bitmask instead of a list of elements.
4834 std::map<SDValue, std::vector<unsigned> > Values;
4835 Values[SplatValue].push_back(0);
4836 bool isConstant = true;
4837 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4838 SplatValue.getOpcode() != ISD::UNDEF)
4841 for (unsigned i = 1; i < NumElems; ++i) {
4842 SDValue V = Node->getOperand(i);
4843 Values[V].push_back(i);
4844 if (V.getOpcode() != ISD::UNDEF)
4845 isOnlyLowElement = false;
4846 if (SplatValue != V)
4847 SplatValue = SDValue(0,0);
4849 // If this isn't a constant element or an undef, we can't use a constant
4851 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4852 V.getOpcode() != ISD::UNDEF)
4856 if (isOnlyLowElement) {
4857 // If the low element is an undef too, then this whole things is an undef.
4858 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4859 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4860 // Otherwise, turn this into a scalar_to_vector node.
4861 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4862 Node->getOperand(0));
4865 // If all elements are constants, create a load from the constant pool.
4867 MVT VT = Node->getValueType(0);
4868 std::vector<Constant*> CV;
4869 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4870 if (ConstantFPSDNode *V =
4871 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4872 CV.push_back(ConstantFP::get(V->getValueAPF()));
4873 } else if (ConstantSDNode *V =
4874 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4875 CV.push_back(ConstantInt::get(V->getAPIntValue()));
4877 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4879 Node->getOperand(0).getValueType().getTypeForMVT();
4880 CV.push_back(UndefValue::get(OpNTy));
4883 Constant *CP = ConstantVector::get(CV);
4884 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4885 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4886 PseudoSourceValue::getConstantPool(), 0);
4889 if (SplatValue.Val) { // Splat of one value?
4890 // Build the shuffle constant vector: <0, 0, 0, 0>
4891 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
4892 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
4893 std::vector<SDValue> ZeroVec(NumElems, Zero);
4894 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4895 &ZeroVec[0], ZeroVec.size());
4897 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4898 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4899 // Get the splatted value into the low element of a vector register.
4901 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4903 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4904 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4905 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4910 // If there are only two unique elements, we may be able to turn this into a
4912 if (Values.size() == 2) {
4913 // Get the two values in deterministic order.
4914 SDValue Val1 = Node->getOperand(1);
4916 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
4917 if (MI->first != Val1)
4920 Val2 = (++MI)->first;
4922 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
4923 // vector shuffle has the undef vector on the RHS.
4924 if (Val1.getOpcode() == ISD::UNDEF)
4925 std::swap(Val1, Val2);
4927 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4928 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
4929 MVT MaskEltVT = MaskVT.getVectorElementType();
4930 std::vector<SDValue> MaskVec(NumElems);
4932 // Set elements of the shuffle mask for Val1.
4933 std::vector<unsigned> &Val1Elts = Values[Val1];
4934 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
4935 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
4937 // Set elements of the shuffle mask for Val2.
4938 std::vector<unsigned> &Val2Elts = Values[Val2];
4939 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
4940 if (Val2.getOpcode() != ISD::UNDEF)
4941 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
4943 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
4945 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4946 &MaskVec[0], MaskVec.size());
4948 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
4949 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4950 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4951 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
4952 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
4953 SDValue Ops[] = { Val1, Val2, ShuffleMask };
4955 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4956 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
4960 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4961 // aligned object on the stack, store each element into it, then load
4962 // the result as a vector.
4963 MVT VT = Node->getValueType(0);
4964 // Create the stack frame object.
4965 SDValue FIPtr = DAG.CreateStackTemporary(VT);
4967 // Emit a store of each element to the stack slot.
4968 SmallVector<SDValue, 8> Stores;
4969 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
4970 // Store (in the right endianness) the elements to memory.
4971 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4972 // Ignore undef elements.
4973 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4975 unsigned Offset = TypeByteSize*i;
4977 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4978 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4980 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4985 if (!Stores.empty()) // Not all undef elements?
4986 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4987 &Stores[0], Stores.size());
4989 StoreChain = DAG.getEntryNode();
4991 // Result is a load from the stack slot.
4992 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4995 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4996 SDValue Op, SDValue Amt,
4997 SDValue &Lo, SDValue &Hi) {
4998 // Expand the subcomponents.
5000 ExpandOp(Op, LHSL, LHSH);
5002 SDValue Ops[] = { LHSL, LHSH, Amt };
5003 MVT VT = LHSL.getValueType();
5004 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5005 Hi = Lo.getValue(1);
5009 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5010 /// smaller elements. If we can't find a way that is more efficient than a
5011 /// libcall on this target, return false. Otherwise, return true with the
5012 /// low-parts expanded into Lo and Hi.
5013 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5014 SDValue &Lo, SDValue &Hi) {
5015 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5016 "This is not a shift!");
5018 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5019 SDValue ShAmt = LegalizeOp(Amt);
5020 MVT ShTy = ShAmt.getValueType();
5021 unsigned ShBits = ShTy.getSizeInBits();
5022 unsigned VTBits = Op.getValueType().getSizeInBits();
5023 unsigned NVTBits = NVT.getSizeInBits();
5025 // Handle the case when Amt is an immediate.
5026 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
5027 unsigned Cst = CN->getValue();
5028 // Expand the incoming operand to be shifted, so that we have its parts
5030 ExpandOp(Op, InL, InH);
5034 Lo = DAG.getConstant(0, NVT);
5035 Hi = DAG.getConstant(0, NVT);
5036 } else if (Cst > NVTBits) {
5037 Lo = DAG.getConstant(0, NVT);
5038 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5039 } else if (Cst == NVTBits) {
5040 Lo = DAG.getConstant(0, NVT);
5043 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5044 Hi = DAG.getNode(ISD::OR, NVT,
5045 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5046 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5051 Lo = DAG.getConstant(0, NVT);
5052 Hi = DAG.getConstant(0, NVT);
5053 } else if (Cst > NVTBits) {
5054 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5055 Hi = DAG.getConstant(0, NVT);
5056 } else if (Cst == NVTBits) {
5058 Hi = DAG.getConstant(0, NVT);
5060 Lo = DAG.getNode(ISD::OR, NVT,
5061 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5062 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5063 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5068 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5069 DAG.getConstant(NVTBits-1, ShTy));
5070 } else if (Cst > NVTBits) {
5071 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5072 DAG.getConstant(Cst-NVTBits, ShTy));
5073 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5074 DAG.getConstant(NVTBits-1, ShTy));
5075 } else if (Cst == NVTBits) {
5077 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5078 DAG.getConstant(NVTBits-1, ShTy));
5080 Lo = DAG.getNode(ISD::OR, NVT,
5081 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5082 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5083 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5089 // Okay, the shift amount isn't constant. However, if we can tell that it is
5090 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5091 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5092 APInt KnownZero, KnownOne;
5093 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5095 // If we know that if any of the high bits of the shift amount are one, then
5096 // we can do this as a couple of simple shifts.
5097 if (KnownOne.intersects(Mask)) {
5098 // Mask out the high bit, which we know is set.
5099 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5100 DAG.getConstant(~Mask, Amt.getValueType()));
5102 // Expand the incoming operand to be shifted, so that we have its parts
5104 ExpandOp(Op, InL, InH);
5107 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5108 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5111 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5112 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5115 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5116 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5117 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5122 // If we know that the high bits of the shift amount are all zero, then we can
5123 // do this as a couple of simple shifts.
5124 if ((KnownZero & Mask) == Mask) {
5126 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5127 DAG.getConstant(NVTBits, Amt.getValueType()),
5130 // Expand the incoming operand to be shifted, so that we have its parts
5132 ExpandOp(Op, InL, InH);
5135 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5136 Hi = DAG.getNode(ISD::OR, NVT,
5137 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5138 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5141 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5142 Lo = DAG.getNode(ISD::OR, NVT,
5143 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5144 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5147 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5148 Lo = DAG.getNode(ISD::OR, NVT,
5149 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5150 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5159 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5160 // does not fit into a register, return the lo part and set the hi part to the
5161 // by-reg argument. If it does fit into a single register, return the result
5162 // and leave the Hi part unset.
5163 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5164 bool isSigned, SDValue &Hi) {
5165 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5166 // The input chain to this libcall is the entry node of the function.
5167 // Legalizing the call will automatically add the previous call to the
5169 SDValue InChain = DAG.getEntryNode();
5171 TargetLowering::ArgListTy Args;
5172 TargetLowering::ArgListEntry Entry;
5173 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5174 MVT ArgVT = Node->getOperand(i).getValueType();
5175 const Type *ArgTy = ArgVT.getTypeForMVT();
5176 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5177 Entry.isSExt = isSigned;
5178 Entry.isZExt = !isSigned;
5179 Args.push_back(Entry);
5181 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5182 TLI.getPointerTy());
5184 // Splice the libcall in wherever FindInputOutputChains tells us to.
5185 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5186 std::pair<SDValue,SDValue> CallInfo =
5187 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
5188 false, Callee, Args, DAG);
5190 // Legalize the call sequence, starting with the chain. This will advance
5191 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5192 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5193 LegalizeOp(CallInfo.second);
5195 switch (getTypeAction(CallInfo.first.getValueType())) {
5196 default: assert(0 && "Unknown thing");
5198 Result = CallInfo.first;
5201 ExpandOp(CallInfo.first, Result, Hi);
5207 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5209 SDValue SelectionDAGLegalize::
5210 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) {
5211 bool isCustom = false;
5213 switch (getTypeAction(Op.getValueType())) {
5215 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5216 Op.getValueType())) {
5217 default: assert(0 && "Unknown operation action!");
5218 case TargetLowering::Custom:
5221 case TargetLowering::Legal:
5222 Tmp1 = LegalizeOp(Op);
5224 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5226 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5229 Tmp1 = TLI.LowerOperation(Result, DAG);
5230 if (Tmp1.Val) Result = Tmp1;
5233 case TargetLowering::Expand:
5234 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy);
5236 case TargetLowering::Promote:
5237 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned);
5242 Result = ExpandIntToFP(isSigned, DestTy, Op);
5245 Tmp1 = PromoteOp(Op);
5247 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
5248 Tmp1, DAG.getValueType(Op.getValueType()));
5250 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
5254 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5256 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5258 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5264 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5266 SDValue SelectionDAGLegalize::
5267 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
5268 MVT SourceVT = Source.getValueType();
5269 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5271 // Expand unsupported int-to-fp vector casts by unrolling them.
5272 if (DestTy.isVector()) {
5274 return LegalizeOp(UnrollVectorOp(Source));
5275 MVT DestEltTy = DestTy.getVectorElementType();
5276 if (DestTy.getVectorNumElements() == 1) {
5277 SDValue Scalar = ScalarizeVectorOp(Source);
5278 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5280 return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result);
5283 SplitVectorOp(Source, Lo, Hi);
5284 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5285 DestTy.getVectorNumElements() / 2);
5286 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo);
5287 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi);
5288 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult, HiResult));
5291 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5292 if (!isSigned && SourceVT != MVT::i32) {
5293 // The integer value loaded will be incorrectly if the 'sign bit' of the
5294 // incoming integer is set. To handle this, we dynamically test to see if
5295 // it is set, and, if so, add a fudge factor.
5299 ExpandOp(Source, Lo, Hi);
5300 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5302 // The comparison for the sign bit will use the entire operand.
5306 // If this is unsigned, and not supported, first perform the conversion to
5307 // signed, then adjust the result if the sign bit is set.
5308 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
5310 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5311 DAG.getConstant(0, Hi.getValueType()),
5313 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5314 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5315 SignSet, Four, Zero);
5316 uint64_t FF = 0x5f800000ULL;
5317 if (TLI.isLittleEndian()) FF <<= 32;
5318 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5320 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5321 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5323 if (DestTy == MVT::f32)
5324 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5325 PseudoSourceValue::getConstantPool(), 0);
5326 else if (DestTy.bitsGT(MVT::f32))
5327 // FIXME: Avoid the extend by construction the right constantpool?
5328 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5330 PseudoSourceValue::getConstantPool(), 0,
5333 assert(0 && "Unexpected conversion");
5335 MVT SCVT = SignedConv.getValueType();
5336 if (SCVT != DestTy) {
5337 // Destination type needs to be expanded as well. The FADD now we are
5338 // constructing will be expanded into a libcall.
5339 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5340 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5341 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5342 SignedConv, SignedConv.getValue(1));
5344 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5346 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5349 // Check to see if the target has a custom way to lower this. If so, use it.
5350 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5351 default: assert(0 && "This action not implemented for this operation!");
5352 case TargetLowering::Legal:
5353 case TargetLowering::Expand:
5354 break; // This case is handled below.
5355 case TargetLowering::Custom: {
5356 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5359 return LegalizeOp(NV);
5360 break; // The target decided this was legal after all
5364 // Expand the source, then glue it back together for the call. We must expand
5365 // the source in case it is shared (this pass of legalize must traverse it).
5367 SDValue SrcLo, SrcHi;
5368 ExpandOp(Source, SrcLo, SrcHi);
5369 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5372 RTLIB::Libcall LC = isSigned ?
5373 RTLIB::getSINTTOFP(SourceVT, DestTy) :
5374 RTLIB::getUINTTOFP(SourceVT, DestTy);
5375 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
5377 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5379 SDValue Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart);
5380 if (Result.getValueType() != DestTy && HiPart.Val)
5381 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5385 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5386 /// INT_TO_FP operation of the specified operand when the target requests that
5387 /// we expand it. At this point, we know that the result and operand types are
5388 /// legal for the target.
5389 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5392 if (Op0.getValueType() == MVT::i32) {
5393 // simple 32-bit [signed|unsigned] integer to float/double expansion
5395 // Get the stack frame index of a 8 byte buffer.
5396 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
5398 // word offset constant for Hi/Lo address computation
5399 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5400 // set up Hi and Lo (into buffer) address based on endian
5401 SDValue Hi = StackSlot;
5402 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5403 if (TLI.isLittleEndian())
5406 // if signed map to unsigned space
5409 // constant used to invert sign bit (signed to unsigned mapping)
5410 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5411 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5415 // store the lo of the constructed double - based on integer input
5416 SDValue Store1 = DAG.getStore(DAG.getEntryNode(),
5417 Op0Mapped, Lo, NULL, 0);
5418 // initial hi portion of constructed double
5419 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5420 // store the hi of the constructed double - biased exponent
5421 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5422 // load the constructed double
5423 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5424 // FP constant to bias correct the final result
5425 SDValue Bias = DAG.getConstantFP(isSigned ?
5426 BitsToDouble(0x4330000080000000ULL)
5427 : BitsToDouble(0x4330000000000000ULL),
5429 // subtract the bias
5430 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5433 // handle final rounding
5434 if (DestVT == MVT::f64) {
5437 } else if (DestVT.bitsLT(MVT::f64)) {
5438 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5439 DAG.getIntPtrConstant(0));
5440 } else if (DestVT.bitsGT(MVT::f64)) {
5441 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5445 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5446 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5448 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
5449 DAG.getConstant(0, Op0.getValueType()),
5451 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5452 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5453 SignSet, Four, Zero);
5455 // If the sign bit of the integer is set, the large number will be treated
5456 // as a negative number. To counteract this, the dynamic code adds an
5457 // offset depending on the data type.
5459 switch (Op0.getValueType().getSimpleVT()) {
5460 default: assert(0 && "Unsupported integer type!");
5461 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5462 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5463 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5464 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5466 if (TLI.isLittleEndian()) FF <<= 32;
5467 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5469 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5470 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5472 if (DestVT == MVT::f32)
5473 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5474 PseudoSourceValue::getConstantPool(), 0);
5477 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5478 DAG.getEntryNode(), CPIdx,
5479 PseudoSourceValue::getConstantPool(), 0,
5483 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5486 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5487 /// *INT_TO_FP operation of the specified operand when the target requests that
5488 /// we promote it. At this point, we know that the result and operand types are
5489 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5490 /// operation that takes a larger input.
5491 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
5494 // First step, figure out the appropriate *INT_TO_FP operation to use.
5495 MVT NewInTy = LegalOp.getValueType();
5497 unsigned OpToUse = 0;
5499 // Scan for the appropriate larger type to use.
5501 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
5502 assert(NewInTy.isInteger() && "Ran out of possibilities!");
5504 // If the target supports SINT_TO_FP of this type, use it.
5505 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5507 case TargetLowering::Legal:
5508 if (!TLI.isTypeLegal(NewInTy))
5509 break; // Can't use this datatype.
5511 case TargetLowering::Custom:
5512 OpToUse = ISD::SINT_TO_FP;
5516 if (isSigned) continue;
5518 // If the target supports UINT_TO_FP of this type, use it.
5519 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5521 case TargetLowering::Legal:
5522 if (!TLI.isTypeLegal(NewInTy))
5523 break; // Can't use this datatype.
5525 case TargetLowering::Custom:
5526 OpToUse = ISD::UINT_TO_FP;
5531 // Otherwise, try a larger type.
5534 // Okay, we found the operation and type to use. Zero extend our input to the
5535 // desired type then run the operation on it.
5536 return DAG.getNode(OpToUse, DestVT,
5537 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5541 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5542 /// FP_TO_*INT operation of the specified operand when the target requests that
5543 /// we promote it. At this point, we know that the result and operand types are
5544 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5545 /// operation that returns a larger result.
5546 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
5549 // First step, figure out the appropriate FP_TO*INT operation to use.
5550 MVT NewOutTy = DestVT;
5552 unsigned OpToUse = 0;
5554 // Scan for the appropriate larger type to use.
5556 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
5557 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
5559 // If the target supports FP_TO_SINT returning this type, use it.
5560 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5562 case TargetLowering::Legal:
5563 if (!TLI.isTypeLegal(NewOutTy))
5564 break; // Can't use this datatype.
5566 case TargetLowering::Custom:
5567 OpToUse = ISD::FP_TO_SINT;
5572 // If the target supports FP_TO_UINT of this type, use it.
5573 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5575 case TargetLowering::Legal:
5576 if (!TLI.isTypeLegal(NewOutTy))
5577 break; // Can't use this datatype.
5579 case TargetLowering::Custom:
5580 OpToUse = ISD::FP_TO_UINT;
5585 // Otherwise, try a larger type.
5589 // Okay, we found the operation and type to use.
5590 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5592 // If the operation produces an invalid type, it must be custom lowered. Use
5593 // the target lowering hooks to expand it. Just keep the low part of the
5594 // expanded operation, we know that we're truncating anyway.
5595 if (getTypeAction(NewOutTy) == Expand) {
5596 Operation = SDValue(TLI.ReplaceNodeResults(Operation.Val, DAG), 0);
5597 assert(Operation.Val && "Didn't return anything");
5600 // Truncate the result of the extended FP_TO_*INT operation to the desired
5602 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5605 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5607 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) {
5608 MVT VT = Op.getValueType();
5609 MVT SHVT = TLI.getShiftAmountTy();
5610 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5611 switch (VT.getSimpleVT()) {
5612 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5614 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5615 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5616 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5618 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5619 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5620 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5621 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5622 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5623 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5624 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5625 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5626 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5628 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5629 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5630 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5631 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5632 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5633 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5634 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5635 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5636 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5637 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5638 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5639 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5640 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5641 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5642 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5643 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5644 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5645 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5646 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5647 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5648 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5652 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5654 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
5656 default: assert(0 && "Cannot expand this yet!");
5658 static const uint64_t mask[6] = {
5659 0x5555555555555555ULL, 0x3333333333333333ULL,
5660 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5661 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5663 MVT VT = Op.getValueType();
5664 MVT ShVT = TLI.getShiftAmountTy();
5665 unsigned len = VT.getSizeInBits();
5666 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5667 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5668 SDValue Tmp2 = DAG.getConstant(mask[i], VT);
5669 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5670 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5671 DAG.getNode(ISD::AND, VT,
5672 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5677 // for now, we do this:
5678 // x = x | (x >> 1);
5679 // x = x | (x >> 2);
5681 // x = x | (x >>16);
5682 // x = x | (x >>32); // for 64-bit input
5683 // return popcount(~x);
5685 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5686 MVT VT = Op.getValueType();
5687 MVT ShVT = TLI.getShiftAmountTy();
5688 unsigned len = VT.getSizeInBits();
5689 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5690 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5691 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5693 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5694 return DAG.getNode(ISD::CTPOP, VT, Op);
5697 // for now, we use: { return popcount(~x & (x - 1)); }
5698 // unless the target has ctlz but not ctpop, in which case we use:
5699 // { return 32 - nlz(~x & (x-1)); }
5700 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5701 MVT VT = Op.getValueType();
5702 SDValue Tmp2 = DAG.getConstant(~0ULL, VT);
5703 SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
5704 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5705 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5706 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5707 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5708 TLI.isOperationLegal(ISD::CTLZ, VT))
5709 return DAG.getNode(ISD::SUB, VT,
5710 DAG.getConstant(VT.getSizeInBits(), VT),
5711 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5712 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5717 /// ExpandOp - Expand the specified SDValue into its two component pieces
5718 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5719 /// LegalizeNodes map is filled in for any results that are not expanded, the
5720 /// ExpandedNodes map is filled in for any results that are expanded, and the
5721 /// Lo/Hi values are returned.
5722 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
5723 MVT VT = Op.getValueType();
5724 MVT NVT = TLI.getTypeToTransformTo(VT);
5725 SDNode *Node = Op.Val;
5726 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5727 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
5728 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
5730 // See if we already expanded it.
5731 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
5732 = ExpandedNodes.find(Op);
5733 if (I != ExpandedNodes.end()) {
5734 Lo = I->second.first;
5735 Hi = I->second.second;
5739 switch (Node->getOpcode()) {
5740 case ISD::CopyFromReg:
5741 assert(0 && "CopyFromReg must be legal!");
5742 case ISD::FP_ROUND_INREG:
5743 if (VT == MVT::ppcf128 &&
5744 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5745 TargetLowering::Custom) {
5746 SDValue SrcLo, SrcHi, Src;
5747 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5748 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5749 SDValue Result = TLI.LowerOperation(
5750 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5751 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5752 Lo = Result.Val->getOperand(0);
5753 Hi = Result.Val->getOperand(1);
5759 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5761 assert(0 && "Do not know how to expand this operator!");
5763 case ISD::EXTRACT_ELEMENT:
5764 ExpandOp(Node->getOperand(0), Lo, Hi);
5765 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
5766 return ExpandOp(Hi, Lo, Hi);
5767 return ExpandOp(Lo, Lo, Hi);
5768 case ISD::EXTRACT_VECTOR_ELT:
5769 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5770 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5771 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5772 return ExpandOp(Lo, Lo, Hi);
5774 Lo = DAG.getNode(ISD::UNDEF, NVT);
5775 Hi = DAG.getNode(ISD::UNDEF, NVT);
5777 case ISD::Constant: {
5778 unsigned NVTBits = NVT.getSizeInBits();
5779 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
5780 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
5781 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
5784 case ISD::ConstantFP: {
5785 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5786 if (CFP->getValueType(0) == MVT::ppcf128) {
5787 APInt api = CFP->getValueAPF().convertToAPInt();
5788 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5790 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5794 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5795 if (getTypeAction(Lo.getValueType()) == Expand)
5796 ExpandOp(Lo, Lo, Hi);
5799 case ISD::BUILD_PAIR:
5800 // Return the operands.
5801 Lo = Node->getOperand(0);
5802 Hi = Node->getOperand(1);
5805 case ISD::MERGE_VALUES:
5806 if (Node->getNumValues() == 1) {
5807 ExpandOp(Op.getOperand(0), Lo, Hi);
5810 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5811 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
5812 Op.getValue(1).getValueType() == MVT::Other &&
5813 "unhandled MERGE_VALUES");
5814 ExpandOp(Op.getOperand(0), Lo, Hi);
5815 // Remember that we legalized the chain.
5816 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5819 case ISD::SIGN_EXTEND_INREG:
5820 ExpandOp(Node->getOperand(0), Lo, Hi);
5821 // sext_inreg the low part if needed.
5822 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5824 // The high part gets the sign extension from the lo-part. This handles
5825 // things like sextinreg V:i64 from i8.
5826 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5827 DAG.getConstant(NVT.getSizeInBits()-1,
5828 TLI.getShiftAmountTy()));
5832 ExpandOp(Node->getOperand(0), Lo, Hi);
5833 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5834 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5840 ExpandOp(Node->getOperand(0), Lo, Hi);
5841 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5842 DAG.getNode(ISD::CTPOP, NVT, Lo),
5843 DAG.getNode(ISD::CTPOP, NVT, Hi));
5844 Hi = DAG.getConstant(0, NVT);
5848 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5849 ExpandOp(Node->getOperand(0), Lo, Hi);
5850 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5851 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5852 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
5854 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5855 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5857 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5858 Hi = DAG.getConstant(0, NVT);
5863 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5864 ExpandOp(Node->getOperand(0), Lo, Hi);
5865 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5866 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5867 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
5869 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5870 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5872 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5873 Hi = DAG.getConstant(0, NVT);
5878 SDValue Ch = Node->getOperand(0); // Legalize the chain.
5879 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
5880 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5881 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5883 // Remember that we legalized the chain.
5884 Hi = LegalizeOp(Hi);
5885 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5886 if (TLI.isBigEndian())
5892 LoadSDNode *LD = cast<LoadSDNode>(Node);
5893 SDValue Ch = LD->getChain(); // Legalize the chain.
5894 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
5895 ISD::LoadExtType ExtType = LD->getExtensionType();
5896 const Value *SV = LD->getSrcValue();
5897 int SVOffset = LD->getSrcValueOffset();
5898 unsigned Alignment = LD->getAlignment();
5899 bool isVolatile = LD->isVolatile();
5901 if (ExtType == ISD::NON_EXTLOAD) {
5902 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
5903 isVolatile, Alignment);
5904 if (VT == MVT::f32 || VT == MVT::f64) {
5905 // f32->i32 or f64->i64 one to one expansion.
5906 // Remember that we legalized the chain.
5907 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
5908 // Recursively expand the new load.
5909 if (getTypeAction(NVT) == Expand)
5910 ExpandOp(Lo, Lo, Hi);
5914 // Increment the pointer to the other half.
5915 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
5916 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5917 DAG.getIntPtrConstant(IncrementSize));
5918 SVOffset += IncrementSize;
5919 Alignment = MinAlign(Alignment, IncrementSize);
5920 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
5921 isVolatile, Alignment);
5923 // Build a factor node to remember that this load is independent of the
5925 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5928 // Remember that we legalized the chain.
5929 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5930 if (TLI.isBigEndian())
5933 MVT EVT = LD->getMemoryVT();
5935 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5936 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5937 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5938 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV,
5939 SVOffset, isVolatile, Alignment);
5940 // Remember that we legalized the chain.
5941 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
5942 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5947 Lo = DAG.getLoad(NVT, Ch, Ptr, SV,
5948 SVOffset, isVolatile, Alignment);
5950 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV,
5951 SVOffset, EVT, isVolatile,
5954 // Remember that we legalized the chain.
5955 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
5957 if (ExtType == ISD::SEXTLOAD) {
5958 // The high part is obtained by SRA'ing all but one of the bits of the
5960 unsigned LoSize = Lo.getValueType().getSizeInBits();
5961 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5962 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5963 } else if (ExtType == ISD::ZEXTLOAD) {
5964 // The high part is just a zero.
5965 Hi = DAG.getConstant(0, NVT);
5966 } else /* if (ExtType == ISD::EXTLOAD) */ {
5967 // The high part is undefined.
5968 Hi = DAG.getNode(ISD::UNDEF, NVT);
5975 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5976 SDValue LL, LH, RL, RH;
5977 ExpandOp(Node->getOperand(0), LL, LH);
5978 ExpandOp(Node->getOperand(1), RL, RH);
5979 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5980 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5984 SDValue LL, LH, RL, RH;
5985 ExpandOp(Node->getOperand(1), LL, LH);
5986 ExpandOp(Node->getOperand(2), RL, RH);
5987 if (getTypeAction(NVT) == Expand)
5988 NVT = TLI.getTypeToExpandTo(NVT);
5989 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5991 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5994 case ISD::SELECT_CC: {
5995 SDValue TL, TH, FL, FH;
5996 ExpandOp(Node->getOperand(2), TL, TH);
5997 ExpandOp(Node->getOperand(3), FL, FH);
5998 if (getTypeAction(NVT) == Expand)
5999 NVT = TLI.getTypeToExpandTo(NVT);
6000 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6001 Node->getOperand(1), TL, FL, Node->getOperand(4));
6003 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6004 Node->getOperand(1), TH, FH, Node->getOperand(4));
6007 case ISD::ANY_EXTEND:
6008 // The low part is any extension of the input (which degenerates to a copy).
6009 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6010 // The high part is undefined.
6011 Hi = DAG.getNode(ISD::UNDEF, NVT);
6013 case ISD::SIGN_EXTEND: {
6014 // The low part is just a sign extension of the input (which degenerates to
6016 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6018 // The high part is obtained by SRA'ing all but one of the bits of the lo
6020 unsigned LoSize = Lo.getValueType().getSizeInBits();
6021 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6022 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6025 case ISD::ZERO_EXTEND:
6026 // The low part is just a zero extension of the input (which degenerates to
6028 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6030 // The high part is just a zero.
6031 Hi = DAG.getConstant(0, NVT);
6034 case ISD::TRUNCATE: {
6035 // The input value must be larger than this value. Expand *it*.
6037 ExpandOp(Node->getOperand(0), NewLo, Hi);
6039 // The low part is now either the right size, or it is closer. If not the
6040 // right size, make an illegal truncate so we recursively expand it.
6041 if (NewLo.getValueType() != Node->getValueType(0))
6042 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6043 ExpandOp(NewLo, Lo, Hi);
6047 case ISD::BIT_CONVERT: {
6049 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6050 // If the target wants to, allow it to lower this itself.
6051 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6052 case Expand: assert(0 && "cannot expand FP!");
6053 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6054 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6056 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6059 // f32 / f64 must be expanded to i32 / i64.
6060 if (VT == MVT::f32 || VT == MVT::f64) {
6061 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6062 if (getTypeAction(NVT) == Expand)
6063 ExpandOp(Lo, Lo, Hi);
6067 // If source operand will be expanded to the same type as VT, i.e.
6068 // i64 <- f64, i32 <- f32, expand the source operand instead.
6069 MVT VT0 = Node->getOperand(0).getValueType();
6070 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6071 ExpandOp(Node->getOperand(0), Lo, Hi);
6075 // Turn this into a load/store pair by default.
6077 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6079 ExpandOp(Tmp, Lo, Hi);
6083 case ISD::READCYCLECOUNTER: {
6084 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6085 TargetLowering::Custom &&
6086 "Must custom expand ReadCycleCounter");
6087 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6088 assert(Tmp.Val && "Node must be custom expanded!");
6089 ExpandOp(Tmp.getValue(0), Lo, Hi);
6090 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6091 LegalizeOp(Tmp.getValue(1)));
6095 case ISD::ATOMIC_CMP_SWAP: {
6096 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6097 assert(Tmp.Val && "Node must be custom expanded!");
6098 ExpandOp(Tmp.getValue(0), Lo, Hi);
6099 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6100 LegalizeOp(Tmp.getValue(1)));
6106 // These operators cannot be expanded directly, emit them as calls to
6107 // library functions.
6108 case ISD::FP_TO_SINT: {
6109 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6111 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6112 case Expand: assert(0 && "cannot expand FP!");
6113 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6114 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6117 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6119 // Now that the custom expander is done, expand the result, which is still
6122 ExpandOp(Op, Lo, Hi);
6127 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6129 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6130 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6134 case ISD::FP_TO_UINT: {
6135 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6137 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6138 case Expand: assert(0 && "cannot expand FP!");
6139 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6140 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6143 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6145 // Now that the custom expander is done, expand the result.
6147 ExpandOp(Op, Lo, Hi);
6152 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6154 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6155 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6160 // If the target wants custom lowering, do so.
6161 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6162 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6163 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6164 Op = TLI.LowerOperation(Op, DAG);
6166 // Now that the custom expander is done, expand the result, which is
6168 ExpandOp(Op, Lo, Hi);
6173 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6174 // this X << 1 as X+X.
6175 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6176 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6177 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6178 SDValue LoOps[2], HiOps[3];
6179 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6180 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6181 LoOps[1] = LoOps[0];
6182 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6184 HiOps[1] = HiOps[0];
6185 HiOps[2] = Lo.getValue(1);
6186 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6191 // If we can emit an efficient shift operation, do so now.
6192 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6195 // If this target supports SHL_PARTS, use it.
6196 TargetLowering::LegalizeAction Action =
6197 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6198 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6199 Action == TargetLowering::Custom) {
6200 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6204 // Otherwise, emit a libcall.
6205 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6210 // If the target wants custom lowering, do so.
6211 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6212 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6213 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6214 Op = TLI.LowerOperation(Op, DAG);
6216 // Now that the custom expander is done, expand the result, which is
6218 ExpandOp(Op, Lo, Hi);
6223 // If we can emit an efficient shift operation, do so now.
6224 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6227 // If this target supports SRA_PARTS, use it.
6228 TargetLowering::LegalizeAction Action =
6229 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6230 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6231 Action == TargetLowering::Custom) {
6232 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6236 // Otherwise, emit a libcall.
6237 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6242 // If the target wants custom lowering, do so.
6243 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6244 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6245 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6246 Op = TLI.LowerOperation(Op, DAG);
6248 // Now that the custom expander is done, expand the result, which is
6250 ExpandOp(Op, Lo, Hi);
6255 // If we can emit an efficient shift operation, do so now.
6256 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6259 // If this target supports SRL_PARTS, use it.
6260 TargetLowering::LegalizeAction Action =
6261 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6262 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6263 Action == TargetLowering::Custom) {
6264 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6268 // Otherwise, emit a libcall.
6269 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6275 // If the target wants to custom expand this, let them.
6276 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6277 TargetLowering::Custom) {
6278 SDValue Result = TLI.LowerOperation(Op, DAG);
6280 ExpandOp(Result, Lo, Hi);
6285 // Expand the subcomponents.
6286 SDValue LHSL, LHSH, RHSL, RHSH;
6287 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6288 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6289 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6290 SDValue LoOps[2], HiOps[3];
6295 if (Node->getOpcode() == ISD::ADD) {
6296 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6297 HiOps[2] = Lo.getValue(1);
6298 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6300 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6301 HiOps[2] = Lo.getValue(1);
6302 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6309 // Expand the subcomponents.
6310 SDValue LHSL, LHSH, RHSL, RHSH;
6311 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6312 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6313 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6314 SDValue LoOps[2] = { LHSL, RHSL };
6315 SDValue HiOps[3] = { LHSH, RHSH };
6317 if (Node->getOpcode() == ISD::ADDC) {
6318 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6319 HiOps[2] = Lo.getValue(1);
6320 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6322 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6323 HiOps[2] = Lo.getValue(1);
6324 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6326 // Remember that we legalized the flag.
6327 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6332 // Expand the subcomponents.
6333 SDValue LHSL, LHSH, RHSL, RHSH;
6334 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6335 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6336 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6337 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6338 SDValue HiOps[3] = { LHSH, RHSH };
6340 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6341 HiOps[2] = Lo.getValue(1);
6342 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6344 // Remember that we legalized the flag.
6345 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6349 // If the target wants to custom expand this, let them.
6350 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6351 SDValue New = TLI.LowerOperation(Op, DAG);
6353 ExpandOp(New, Lo, Hi);
6358 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6359 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6360 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6361 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6362 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6363 SDValue LL, LH, RL, RH;
6364 ExpandOp(Node->getOperand(0), LL, LH);
6365 ExpandOp(Node->getOperand(1), RL, RH);
6366 unsigned OuterBitSize = Op.getValueSizeInBits();
6367 unsigned InnerBitSize = RH.getValueSizeInBits();
6368 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6369 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6370 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
6371 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
6372 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
6373 // The inputs are both zero-extended.
6375 // We can emit a umul_lohi.
6376 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6377 Hi = SDValue(Lo.Val, 1);
6381 // We can emit a mulhu+mul.
6382 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6383 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6387 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6388 // The input values are both sign-extended.
6390 // We can emit a smul_lohi.
6391 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6392 Hi = SDValue(Lo.Val, 1);
6396 // We can emit a mulhs+mul.
6397 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6398 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6403 // Lo,Hi = umul LHS, RHS.
6404 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6405 DAG.getVTList(NVT, NVT), LL, RL);
6407 Hi = UMulLOHI.getValue(1);
6408 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6409 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6410 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6411 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6415 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6416 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6417 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6418 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6419 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6420 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6425 // If nothing else, we can make a libcall.
6426 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
6430 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
6433 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
6436 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
6439 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
6443 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
6446 RTLIB::ADD_PPCF128),
6450 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
6453 RTLIB::SUB_PPCF128),
6457 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
6460 RTLIB::MUL_PPCF128),
6464 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
6467 RTLIB::DIV_PPCF128),
6470 case ISD::FP_EXTEND: {
6471 if (VT == MVT::ppcf128) {
6472 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6473 Node->getOperand(0).getValueType()==MVT::f64);
6474 const uint64_t zero = 0;
6475 if (Node->getOperand(0).getValueType()==MVT::f32)
6476 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6478 Hi = Node->getOperand(0);
6479 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6482 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
6483 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
6484 Lo = ExpandLibCall(LC, Node, true, Hi);
6487 case ISD::FP_ROUND: {
6488 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
6490 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
6491 Lo = ExpandLibCall(LC, Node, true, Hi);
6495 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::POWI_F32,
6498 RTLIB::POWI_PPCF128),
6505 case ISD::FNEARBYINT:
6509 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6510 switch(Node->getOpcode()) {
6512 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6513 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6516 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6517 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6520 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6521 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6524 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
6525 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
6528 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
6529 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
6532 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
6533 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
6536 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
6537 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
6539 case ISD::FNEARBYINT:
6540 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
6541 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
6543 default: assert(0 && "Unreachable!");
6545 Lo = ExpandLibCall(LC, Node, false, Hi);
6549 if (VT == MVT::ppcf128) {
6551 ExpandOp(Node->getOperand(0), Lo, Tmp);
6552 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6553 // lo = hi==fabs(hi) ? lo : -lo;
6554 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6555 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6556 DAG.getCondCode(ISD::SETEQ));
6559 SDValue Mask = (VT == MVT::f64)
6560 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6561 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6562 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6563 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6564 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6565 if (getTypeAction(NVT) == Expand)
6566 ExpandOp(Lo, Lo, Hi);
6570 if (VT == MVT::ppcf128) {
6571 ExpandOp(Node->getOperand(0), Lo, Hi);
6572 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6573 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6576 SDValue Mask = (VT == MVT::f64)
6577 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6578 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6579 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6580 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6581 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6582 if (getTypeAction(NVT) == Expand)
6583 ExpandOp(Lo, Lo, Hi);
6586 case ISD::FCOPYSIGN: {
6587 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6588 if (getTypeAction(NVT) == Expand)
6589 ExpandOp(Lo, Lo, Hi);
6592 case ISD::SINT_TO_FP:
6593 case ISD::UINT_TO_FP: {
6594 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6595 MVT SrcVT = Node->getOperand(0).getValueType();
6597 // Promote the operand if needed. Do this before checking for
6598 // ppcf128 so conversions of i16 and i8 work.
6599 if (getTypeAction(SrcVT) == Promote) {
6600 SDValue Tmp = PromoteOp(Node->getOperand(0));
6602 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6603 DAG.getValueType(SrcVT))
6604 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6605 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6606 SrcVT = Node->getOperand(0).getValueType();
6609 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
6610 static const uint64_t zero = 0;
6612 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6613 Node->getOperand(0)));
6614 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6616 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6617 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6618 Node->getOperand(0)));
6619 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6620 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6621 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6622 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6623 DAG.getConstant(0, MVT::i32),
6624 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6626 APFloat(APInt(128, 2, TwoE32)),
6629 DAG.getCondCode(ISD::SETLT)),
6634 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6635 // si64->ppcf128 done by libcall, below
6636 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6637 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6639 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6640 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6641 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6642 DAG.getConstant(0, MVT::i64),
6643 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6645 APFloat(APInt(128, 2, TwoE64)),
6648 DAG.getCondCode(ISD::SETLT)),
6653 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6654 Node->getOperand(0));
6655 if (getTypeAction(Lo.getValueType()) == Expand)
6656 // float to i32 etc. can be 'expanded' to a single node.
6657 ExpandOp(Lo, Lo, Hi);
6662 // Make sure the resultant values have been legalized themselves, unless this
6663 // is a type that requires multi-step expansion.
6664 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6665 Lo = LegalizeOp(Lo);
6667 // Don't legalize the high part if it is expanded to a single node.
6668 Hi = LegalizeOp(Hi);
6671 // Remember in a map if the values will be reused later.
6673 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6674 assert(isNew && "Value already expanded?!?");
6677 /// SplitVectorOp - Given an operand of vector type, break it down into
6678 /// two smaller values, still of vector type.
6679 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
6681 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
6682 SDNode *Node = Op.Val;
6683 unsigned NumElements = Op.getValueType().getVectorNumElements();
6684 assert(NumElements > 1 && "Cannot split a single element vector!");
6686 MVT NewEltVT = Op.getValueType().getVectorElementType();
6688 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6689 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6691 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
6692 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
6694 // See if we already split it.
6695 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
6696 = SplitNodes.find(Op);
6697 if (I != SplitNodes.end()) {
6698 Lo = I->second.first;
6699 Hi = I->second.second;
6703 switch (Node->getOpcode()) {
6708 assert(0 && "Unhandled operation in SplitVectorOp!");
6710 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6711 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6713 case ISD::BUILD_PAIR:
6714 Lo = Node->getOperand(0);
6715 Hi = Node->getOperand(1);
6717 case ISD::INSERT_VECTOR_ELT: {
6718 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
6719 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6720 unsigned Index = Idx->getValue();
6721 SDValue ScalarOp = Node->getOperand(1);
6722 if (Index < NewNumElts_Lo)
6723 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6724 DAG.getIntPtrConstant(Index));
6726 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6727 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
6730 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
6731 Node->getOperand(1),
6732 Node->getOperand(2));
6733 SplitVectorOp(Tmp, Lo, Hi);
6736 case ISD::VECTOR_SHUFFLE: {
6737 // Build the low part.
6738 SDValue Mask = Node->getOperand(2);
6739 SmallVector<SDValue, 8> Ops;
6740 MVT PtrVT = TLI.getPointerTy();
6742 // Insert all of the elements from the input that are needed. We use
6743 // buildvector of extractelement here because the input vectors will have
6744 // to be legalized, so this makes the code simpler.
6745 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6746 SDValue IdxNode = Mask.getOperand(i);
6747 if (IdxNode.getOpcode() == ISD::UNDEF) {
6748 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6751 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6752 SDValue InVec = Node->getOperand(0);
6753 if (Idx >= NumElements) {
6754 InVec = Node->getOperand(1);
6757 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6758 DAG.getConstant(Idx, PtrVT)));
6760 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6763 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6764 SDValue IdxNode = Mask.getOperand(i);
6765 if (IdxNode.getOpcode() == ISD::UNDEF) {
6766 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6769 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6770 SDValue InVec = Node->getOperand(0);
6771 if (Idx >= NumElements) {
6772 InVec = Node->getOperand(1);
6775 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6776 DAG.getConstant(Idx, PtrVT)));
6778 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size());
6781 case ISD::BUILD_VECTOR: {
6782 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
6783 Node->op_begin()+NewNumElts_Lo);
6784 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6786 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6788 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6791 case ISD::CONCAT_VECTORS: {
6792 // FIXME: Handle non-power-of-two vectors?
6793 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6794 if (NewNumSubvectors == 1) {
6795 Lo = Node->getOperand(0);
6796 Hi = Node->getOperand(1);
6798 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
6799 Node->op_begin()+NewNumSubvectors);
6800 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6802 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6804 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6809 SDValue Cond = Node->getOperand(0);
6811 SDValue LL, LH, RL, RH;
6812 SplitVectorOp(Node->getOperand(1), LL, LH);
6813 SplitVectorOp(Node->getOperand(2), RL, RH);
6815 if (Cond.getValueType().isVector()) {
6816 // Handle a vector merge.
6818 SplitVectorOp(Cond, CL, CH);
6819 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6820 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6822 // Handle a simple select with vector operands.
6823 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6824 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6828 case ISD::SELECT_CC: {
6829 SDValue CondLHS = Node->getOperand(0);
6830 SDValue CondRHS = Node->getOperand(1);
6831 SDValue CondCode = Node->getOperand(4);
6833 SDValue LL, LH, RL, RH;
6834 SplitVectorOp(Node->getOperand(2), LL, LH);
6835 SplitVectorOp(Node->getOperand(3), RL, RH);
6837 // Handle a simple select with vector operands.
6838 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
6840 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
6845 SDValue LL, LH, RL, RH;
6846 SplitVectorOp(Node->getOperand(0), LL, LH);
6847 SplitVectorOp(Node->getOperand(1), RL, RH);
6848 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
6849 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
6868 SDValue LL, LH, RL, RH;
6869 SplitVectorOp(Node->getOperand(0), LL, LH);
6870 SplitVectorOp(Node->getOperand(1), RL, RH);
6872 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6873 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6879 SplitVectorOp(Node->getOperand(0), L, H);
6881 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6882 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6893 case ISD::FP_TO_SINT:
6894 case ISD::FP_TO_UINT:
6895 case ISD::SINT_TO_FP:
6896 case ISD::UINT_TO_FP:
6898 case ISD::ANY_EXTEND:
6899 case ISD::SIGN_EXTEND:
6900 case ISD::ZERO_EXTEND:
6901 case ISD::FP_EXTEND: {
6903 SplitVectorOp(Node->getOperand(0), L, H);
6905 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6906 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6910 LoadSDNode *LD = cast<LoadSDNode>(Node);
6911 SDValue Ch = LD->getChain();
6912 SDValue Ptr = LD->getBasePtr();
6913 ISD::LoadExtType ExtType = LD->getExtensionType();
6914 const Value *SV = LD->getSrcValue();
6915 int SVOffset = LD->getSrcValueOffset();
6916 MVT MemoryVT = LD->getMemoryVT();
6917 unsigned Alignment = LD->getAlignment();
6918 bool isVolatile = LD->isVolatile();
6920 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
6921 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
6923 MVT MemNewEltVT = MemoryVT.getVectorElementType();
6924 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
6925 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
6927 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType,
6928 NewVT_Lo, Ch, Ptr, Offset,
6929 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
6930 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
6931 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6932 DAG.getIntPtrConstant(IncrementSize));
6933 SVOffset += IncrementSize;
6934 Alignment = MinAlign(Alignment, IncrementSize);
6935 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType,
6936 NewVT_Hi, Ch, Ptr, Offset,
6937 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
6939 // Build a factor node to remember that this load is independent of the
6941 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6944 // Remember that we legalized the chain.
6945 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6948 case ISD::BIT_CONVERT: {
6949 // We know the result is a vector. The input may be either a vector or a
6951 SDValue InOp = Node->getOperand(0);
6952 if (!InOp.getValueType().isVector() ||
6953 InOp.getValueType().getVectorNumElements() == 1) {
6954 // The input is a scalar or single-element vector.
6955 // Lower to a store/load so that it can be split.
6956 // FIXME: this could be improved probably.
6957 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
6958 Op.getValueType().getTypeForMVT());
6959 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
6960 int FI = cast<FrameIndexSDNode>(Ptr.Val)->getIndex();
6962 SDValue St = DAG.getStore(DAG.getEntryNode(),
6964 PseudoSourceValue::getFixedStack(FI), 0);
6965 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
6966 PseudoSourceValue::getFixedStack(FI), 0);
6968 // Split the vector and convert each of the pieces now.
6969 SplitVectorOp(InOp, Lo, Hi);
6970 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6971 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6976 // Remember in a map if the values will be reused later.
6978 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6979 assert(isNew && "Value already split?!?");
6983 /// ScalarizeVectorOp - Given an operand of single-element vector type
6984 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6985 /// scalar (e.g. f32) value.
6986 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
6987 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
6988 SDNode *Node = Op.Val;
6989 MVT NewVT = Op.getValueType().getVectorElementType();
6990 assert(Op.getValueType().getVectorNumElements() == 1);
6992 // See if we already scalarized it.
6993 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
6994 if (I != ScalarizedNodes.end()) return I->second;
6997 switch (Node->getOpcode()) {
7000 Node->dump(&DAG); cerr << "\n";
7002 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7019 Result = DAG.getNode(Node->getOpcode(),
7021 ScalarizeVectorOp(Node->getOperand(0)),
7022 ScalarizeVectorOp(Node->getOperand(1)));
7029 case ISD::FP_TO_SINT:
7030 case ISD::FP_TO_UINT:
7031 case ISD::SINT_TO_FP:
7032 case ISD::UINT_TO_FP:
7033 case ISD::SIGN_EXTEND:
7034 case ISD::ZERO_EXTEND:
7035 case ISD::ANY_EXTEND:
7037 case ISD::FP_EXTEND:
7038 Result = DAG.getNode(Node->getOpcode(),
7040 ScalarizeVectorOp(Node->getOperand(0)));
7044 Result = DAG.getNode(Node->getOpcode(),
7046 ScalarizeVectorOp(Node->getOperand(0)),
7047 Node->getOperand(1));
7050 LoadSDNode *LD = cast<LoadSDNode>(Node);
7051 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7052 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7053 ISD::LoadExtType ExtType = LD->getExtensionType();
7054 const Value *SV = LD->getSrcValue();
7055 int SVOffset = LD->getSrcValueOffset();
7056 MVT MemoryVT = LD->getMemoryVT();
7057 unsigned Alignment = LD->getAlignment();
7058 bool isVolatile = LD->isVolatile();
7060 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7061 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7063 Result = DAG.getLoad(ISD::UNINDEXED, ExtType,
7064 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7065 MemoryVT.getVectorElementType(),
7066 isVolatile, Alignment);
7068 // Remember that we legalized the chain.
7069 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7072 case ISD::BUILD_VECTOR:
7073 Result = Node->getOperand(0);
7075 case ISD::INSERT_VECTOR_ELT:
7076 // Returning the inserted scalar element.
7077 Result = Node->getOperand(1);
7079 case ISD::CONCAT_VECTORS:
7080 assert(Node->getOperand(0).getValueType() == NewVT &&
7081 "Concat of non-legal vectors not yet supported!");
7082 Result = Node->getOperand(0);
7084 case ISD::VECTOR_SHUFFLE: {
7085 // Figure out if the scalar is the LHS or RHS and return it.
7086 SDValue EltNum = Node->getOperand(2).getOperand(0);
7087 if (cast<ConstantSDNode>(EltNum)->getValue())
7088 Result = ScalarizeVectorOp(Node->getOperand(1));
7090 Result = ScalarizeVectorOp(Node->getOperand(0));
7093 case ISD::EXTRACT_SUBVECTOR:
7094 Result = Node->getOperand(0);
7095 assert(Result.getValueType() == NewVT);
7097 case ISD::BIT_CONVERT: {
7098 SDValue Op0 = Op.getOperand(0);
7099 if (Op0.getValueType().getVectorNumElements() == 1)
7100 Op0 = ScalarizeVectorOp(Op0);
7101 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7105 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7106 ScalarizeVectorOp(Op.getOperand(1)),
7107 ScalarizeVectorOp(Op.getOperand(2)));
7109 case ISD::SELECT_CC:
7110 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
7111 Node->getOperand(1),
7112 ScalarizeVectorOp(Op.getOperand(2)),
7113 ScalarizeVectorOp(Op.getOperand(3)),
7114 Node->getOperand(4));
7117 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7118 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7119 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
7121 Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7122 DAG.getConstant(-1ULL, NewVT),
7123 DAG.getConstant(0ULL, NewVT));
7128 if (TLI.isTypeLegal(NewVT))
7129 Result = LegalizeOp(Result);
7130 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7131 assert(isNew && "Value already scalarized?");
7136 // SelectionDAG::Legalize - This is the entry point for the file.
7138 void SelectionDAG::Legalize() {
7139 /// run - This is the main entry point to this class.
7141 SelectionDAGLegalize(*this).LegalizeDAG();