1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
40 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
41 cl::desc("Pop up a window to show dags before legalize"));
43 static const bool ViewLegalizeDAGs = 0;
46 //===----------------------------------------------------------------------===//
47 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
48 /// hacks on it until the target machine can handle it. This involves
49 /// eliminating value sizes the machine cannot handle (promoting small sizes to
50 /// large sizes or splitting up large values into small values) as well as
51 /// eliminating operations the machine cannot handle.
53 /// This code also does a small amount of optimization and recognition of idioms
54 /// as part of its processing. For example, if a target does not support a
55 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
56 /// will attempt merge setcc and brc instructions into brcc's.
59 class VISIBILITY_HIDDEN SelectionDAGLegalize {
63 // Libcall insertion helpers.
65 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
66 /// legalized. We use this to ensure that calls are properly serialized
67 /// against each other, including inserted libcalls.
68 SDOperand LastCALLSEQ_END;
70 /// IsLegalizingCall - This member is used *only* for purposes of providing
71 /// helpful assertions that a libcall isn't created while another call is
72 /// being legalized (which could lead to non-serialized call sequences).
73 bool IsLegalizingCall;
76 Legal, // The target natively supports this operation.
77 Promote, // This operation should be executed in a larger type.
78 Expand // Try to expand this to other ops, otherwise use a libcall.
81 /// ValueTypeActions - This is a bitvector that contains two bits for each
82 /// value type, where the two bits correspond to the LegalizeAction enum.
83 /// This can be queried with "getTypeAction(VT)".
84 TargetLowering::ValueTypeActionImpl ValueTypeActions;
86 /// LegalizedNodes - For nodes that are of legal width, and that have more
87 /// than one use, this map indicates what regularized operand to use. This
88 /// allows us to avoid legalizing the same thing more than once.
89 DenseMap<SDOperand, SDOperand> LegalizedNodes;
91 /// PromotedNodes - For nodes that are below legal width, and that have more
92 /// than one use, this map indicates what promoted value to use. This allows
93 /// us to avoid promoting the same thing more than once.
94 DenseMap<SDOperand, SDOperand> PromotedNodes;
96 /// ExpandedNodes - For nodes that need to be expanded this map indicates
97 /// which which operands are the expanded version of the input. This allows
98 /// us to avoid expanding the same node more than once.
99 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
101 /// SplitNodes - For vector nodes that need to be split, this map indicates
102 /// which which operands are the split version of the input. This allows us
103 /// to avoid splitting the same node more than once.
104 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
106 /// ScalarizedNodes - For nodes that need to be converted from vector types to
107 /// scalar types, this contains the mapping of ones we have already
108 /// processed to the result.
109 std::map<SDOperand, SDOperand> ScalarizedNodes;
111 void AddLegalizedOperand(SDOperand From, SDOperand To) {
112 LegalizedNodes.insert(std::make_pair(From, To));
113 // If someone requests legalization of the new node, return itself.
115 LegalizedNodes.insert(std::make_pair(To, To));
117 void AddPromotedOperand(SDOperand From, SDOperand To) {
118 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
119 assert(isNew && "Got into the map somehow?");
120 // If someone requests legalization of the new node, return itself.
121 LegalizedNodes.insert(std::make_pair(To, To));
126 SelectionDAGLegalize(SelectionDAG &DAG);
128 /// getTypeAction - Return how we should legalize values of this type, either
129 /// it is already legal or we need to expand it into multiple registers of
130 /// smaller integer type, or we need to promote it to a larger type.
131 LegalizeAction getTypeAction(MVT::ValueType VT) const {
132 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
135 /// isTypeLegal - Return true if this type is legal on this target.
137 bool isTypeLegal(MVT::ValueType VT) const {
138 return getTypeAction(VT) == Legal;
144 /// HandleOp - Legalize, Promote, or Expand the specified operand as
145 /// appropriate for its type.
146 void HandleOp(SDOperand Op);
148 /// LegalizeOp - We know that the specified value has a legal type.
149 /// Recursively ensure that the operands have legal types, then return the
151 SDOperand LegalizeOp(SDOperand O);
153 /// UnrollVectorOp - We know that the given vector has a legal type, however
154 /// the operation it performs is not legal and is an operation that we have
155 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
156 /// operating on each element individually.
157 SDOperand UnrollVectorOp(SDOperand O);
159 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
160 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
161 /// is necessary to spill the vector being inserted into to memory, perform
162 /// the insert there, and then read the result back.
163 SDOperand PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val,
166 /// PromoteOp - Given an operation that produces a value in an invalid type,
167 /// promote it to compute the value into a larger type. The produced value
168 /// will have the correct bits for the low portion of the register, but no
169 /// guarantee is made about the top bits: it may be zero, sign-extended, or
171 SDOperand PromoteOp(SDOperand O);
173 /// ExpandOp - Expand the specified SDOperand into its two component pieces
174 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
175 /// the LegalizeNodes map is filled in for any results that are not expanded,
176 /// the ExpandedNodes map is filled in for any results that are expanded, and
177 /// the Lo/Hi values are returned. This applies to integer types and Vector
179 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
181 /// SplitVectorOp - Given an operand of vector type, break it down into
182 /// two smaller values.
183 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
185 /// ScalarizeVectorOp - Given an operand of single-element vector type
186 /// (e.g. v1f32), convert it into the equivalent operation that returns a
187 /// scalar (e.g. f32) value.
188 SDOperand ScalarizeVectorOp(SDOperand O);
190 /// isShuffleLegal - Return true if a vector shuffle is legal with the
191 /// specified mask and type. Targets can specify exactly which masks they
192 /// support and the code generator is tasked with not creating illegal masks.
194 /// Note that this will also return true for shuffles that are promoted to a
197 /// If this is a legal shuffle, this method returns the (possibly promoted)
198 /// build_vector Mask. If it's not a legal shuffle, it returns null.
199 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
201 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
202 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
204 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
206 SDOperand ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
208 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
211 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT,
212 MVT::ValueType DestVT);
213 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
214 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
215 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
217 MVT::ValueType DestVT);
218 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
220 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
223 SDOperand ExpandBSWAP(SDOperand Op);
224 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
225 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
226 SDOperand &Lo, SDOperand &Hi);
227 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
228 SDOperand &Lo, SDOperand &Hi);
230 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
231 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
235 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
236 /// specified mask and type. Targets can specify exactly which masks they
237 /// support and the code generator is tasked with not creating illegal masks.
239 /// Note that this will also return true for shuffles that are promoted to a
241 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
242 SDOperand Mask) const {
243 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
245 case TargetLowering::Legal:
246 case TargetLowering::Custom:
248 case TargetLowering::Promote: {
249 // If this is promoted to a different type, convert the shuffle mask and
250 // ask if it is legal in the promoted type!
251 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
253 // If we changed # elements, change the shuffle mask.
254 unsigned NumEltsGrowth =
255 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
256 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
257 if (NumEltsGrowth > 1) {
258 // Renumber the elements.
259 SmallVector<SDOperand, 8> Ops;
260 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
261 SDOperand InOp = Mask.getOperand(i);
262 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
263 if (InOp.getOpcode() == ISD::UNDEF)
264 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
266 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
267 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
271 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
277 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
280 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
281 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
282 ValueTypeActions(TLI.getValueTypeActions()) {
283 assert(MVT::LAST_VALUETYPE <= 32 &&
284 "Too many value types for ValueTypeActions to hold!");
287 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
288 /// contains all of a nodes operands before it contains the node.
289 static void ComputeTopDownOrdering(SelectionDAG &DAG,
290 SmallVector<SDNode*, 64> &Order) {
292 DenseMap<SDNode*, unsigned> Visited;
293 std::vector<SDNode*> Worklist;
294 Worklist.reserve(128);
296 // Compute ordering from all of the leaves in the graphs, those (like the
297 // entry node) that have no operands.
298 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
299 E = DAG.allnodes_end(); I != E; ++I) {
300 if (I->getNumOperands() == 0) {
302 Worklist.push_back(I);
306 while (!Worklist.empty()) {
307 SDNode *N = Worklist.back();
310 if (++Visited[N] != N->getNumOperands())
311 continue; // Haven't visited all operands yet
315 // Now that we have N in, add anything that uses it if all of their operands
317 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
319 Worklist.push_back(UI->getUser());
322 assert(Order.size() == Visited.size() &&
324 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
325 "Error: DAG is cyclic!");
329 void SelectionDAGLegalize::LegalizeDAG() {
330 LastCALLSEQ_END = DAG.getEntryNode();
331 IsLegalizingCall = false;
333 // The legalize process is inherently a bottom-up recursive process (users
334 // legalize their uses before themselves). Given infinite stack space, we
335 // could just start legalizing on the root and traverse the whole graph. In
336 // practice however, this causes us to run out of stack space on large basic
337 // blocks. To avoid this problem, compute an ordering of the nodes where each
338 // node is only legalized after all of its operands are legalized.
339 SmallVector<SDNode*, 64> Order;
340 ComputeTopDownOrdering(DAG, Order);
342 for (unsigned i = 0, e = Order.size(); i != e; ++i)
343 HandleOp(SDOperand(Order[i], 0));
345 // Finally, it's possible the root changed. Get the new root.
346 SDOperand OldRoot = DAG.getRoot();
347 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
348 DAG.setRoot(LegalizedNodes[OldRoot]);
350 ExpandedNodes.clear();
351 LegalizedNodes.clear();
352 PromotedNodes.clear();
354 ScalarizedNodes.clear();
356 // Remove dead nodes now.
357 DAG.RemoveDeadNodes();
361 /// FindCallEndFromCallStart - Given a chained node that is part of a call
362 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
363 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
364 if (Node->getOpcode() == ISD::CALLSEQ_END)
366 if (Node->use_empty())
367 return 0; // No CallSeqEnd
369 // The chain is usually at the end.
370 SDOperand TheChain(Node, Node->getNumValues()-1);
371 if (TheChain.getValueType() != MVT::Other) {
372 // Sometimes it's at the beginning.
373 TheChain = SDOperand(Node, 0);
374 if (TheChain.getValueType() != MVT::Other) {
375 // Otherwise, hunt for it.
376 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
377 if (Node->getValueType(i) == MVT::Other) {
378 TheChain = SDOperand(Node, i);
382 // Otherwise, we walked into a node without a chain.
383 if (TheChain.getValueType() != MVT::Other)
388 for (SDNode::use_iterator UI = Node->use_begin(),
389 E = Node->use_end(); UI != E; ++UI) {
391 // Make sure to only follow users of our token chain.
392 SDNode *User = UI->getUser();
393 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
394 if (User->getOperand(i) == TheChain)
395 if (SDNode *Result = FindCallEndFromCallStart(User))
401 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
402 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
403 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
404 assert(Node && "Didn't find callseq_start for a call??");
405 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
407 assert(Node->getOperand(0).getValueType() == MVT::Other &&
408 "Node doesn't have a token chain argument!");
409 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
412 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
413 /// see if any uses can reach Dest. If no dest operands can get to dest,
414 /// legalize them, legalize ourself, and return false, otherwise, return true.
416 /// Keep track of the nodes we fine that actually do lead to Dest in
417 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
419 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
420 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
421 if (N == Dest) return true; // N certainly leads to Dest :)
423 // If we've already processed this node and it does lead to Dest, there is no
424 // need to reprocess it.
425 if (NodesLeadingTo.count(N)) return true;
427 // If the first result of this node has been already legalized, then it cannot
429 switch (getTypeAction(N->getValueType(0))) {
431 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
434 if (PromotedNodes.count(SDOperand(N, 0))) return false;
437 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
441 // Okay, this node has not already been legalized. Check and legalize all
442 // operands. If none lead to Dest, then we can legalize this node.
443 bool OperandsLeadToDest = false;
444 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
445 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
446 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
448 if (OperandsLeadToDest) {
449 NodesLeadingTo.insert(N);
453 // Okay, this node looks safe, legalize it and return false.
454 HandleOp(SDOperand(N, 0));
458 /// HandleOp - Legalize, Promote, or Expand the specified operand as
459 /// appropriate for its type.
460 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
461 MVT::ValueType VT = Op.getValueType();
462 switch (getTypeAction(VT)) {
463 default: assert(0 && "Bad type action!");
464 case Legal: (void)LegalizeOp(Op); break;
465 case Promote: (void)PromoteOp(Op); break;
467 if (!MVT::isVector(VT)) {
468 // If this is an illegal scalar, expand it into its two component
471 if (Op.getOpcode() == ISD::TargetConstant)
472 break; // Allow illegal target nodes.
474 } else if (MVT::getVectorNumElements(VT) == 1) {
475 // If this is an illegal single element vector, convert it to a
477 (void)ScalarizeVectorOp(Op);
479 // Otherwise, this is an illegal multiple element vector.
480 // Split it in half and legalize both parts.
482 SplitVectorOp(Op, X, Y);
488 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
489 /// a load from the constant pool.
490 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
491 SelectionDAG &DAG, TargetLowering &TLI) {
494 // If a FP immediate is precise when represented as a float and if the
495 // target can do an extending load from float to double, we put it into
496 // the constant pool as a float, even if it's is statically typed as a
497 // double. This shrinks FP constants and canonicalizes them for targets where
498 // an FP extending load is the same cost as a normal load (such as on the x87
499 // fp stack or PPC FP unit).
500 MVT::ValueType VT = CFP->getValueType(0);
501 ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF());
503 if (VT!=MVT::f64 && VT!=MVT::f32)
504 assert(0 && "Invalid type expansion");
505 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(),
506 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
509 MVT::ValueType OrigVT = VT;
510 MVT::ValueType SVT = VT;
511 while (SVT != MVT::f32) {
512 SVT = (unsigned)SVT - 1;
513 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
514 // Only do this if the target has a native EXTLOAD instruction from
516 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) &&
517 TLI.ShouldShrinkFPConstant(OrigVT)) {
518 const Type *SType = MVT::getTypeForValueType(SVT);
519 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
525 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
527 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
528 CPIdx, PseudoSourceValue::getConstantPool(),
530 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
531 PseudoSourceValue::getConstantPool(), 0);
535 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
538 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
539 SelectionDAG &DAG, TargetLowering &TLI) {
540 MVT::ValueType VT = Node->getValueType(0);
541 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
542 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
543 "fcopysign expansion only supported for f32 and f64");
544 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
546 // First get the sign bit of second operand.
547 SDOperand Mask1 = (SrcVT == MVT::f64)
548 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
549 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
550 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
551 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
552 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
553 // Shift right or sign-extend it if the two operands have different types.
554 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
556 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
557 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
558 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
559 } else if (SizeDiff < 0)
560 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
562 // Clear the sign bit of first operand.
563 SDOperand Mask2 = (VT == MVT::f64)
564 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
565 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
566 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
567 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
568 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
570 // Or the value with the sign bit.
571 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
575 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
577 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
578 TargetLowering &TLI) {
579 SDOperand Chain = ST->getChain();
580 SDOperand Ptr = ST->getBasePtr();
581 SDOperand Val = ST->getValue();
582 MVT::ValueType VT = Val.getValueType();
583 int Alignment = ST->getAlignment();
584 int SVOffset = ST->getSrcValueOffset();
585 if (MVT::isFloatingPoint(ST->getMemoryVT()) ||
586 MVT::isVector(ST->getMemoryVT())) {
587 // Expand to a bitconvert of the value to the integer type of the
588 // same size, then a (misaligned) int store.
589 MVT::ValueType intVT;
590 if (MVT::is128BitVector(VT) || VT == MVT::ppcf128 || VT == MVT::f128)
592 else if (MVT::is64BitVector(VT) || VT==MVT::f64)
594 else if (VT==MVT::f32)
597 assert(0 && "Unaligned store of unsupported type");
599 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
600 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
601 SVOffset, ST->isVolatile(), Alignment);
603 assert(MVT::isInteger(ST->getMemoryVT()) &&
604 !MVT::isVector(ST->getMemoryVT()) &&
605 "Unaligned store of unknown type.");
606 // Get the half-size VT
607 MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1;
608 int NumBits = MVT::getSizeInBits(NewStoredVT);
609 int IncrementSize = NumBits / 8;
611 // Divide the stored value in two parts.
612 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
614 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
616 // Store the two parts
617 SDOperand Store1, Store2;
618 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
619 ST->getSrcValue(), SVOffset, NewStoredVT,
620 ST->isVolatile(), Alignment);
621 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
622 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
623 Alignment = MinAlign(Alignment, IncrementSize);
624 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
625 ST->getSrcValue(), SVOffset + IncrementSize,
626 NewStoredVT, ST->isVolatile(), Alignment);
628 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
631 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
633 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
634 TargetLowering &TLI) {
635 int SVOffset = LD->getSrcValueOffset();
636 SDOperand Chain = LD->getChain();
637 SDOperand Ptr = LD->getBasePtr();
638 MVT::ValueType VT = LD->getValueType(0);
639 MVT::ValueType LoadedVT = LD->getMemoryVT();
640 if (MVT::isFloatingPoint(VT) || MVT::isVector(VT)) {
641 // Expand to a (misaligned) integer load of the same size,
642 // then bitconvert to floating point or vector.
643 MVT::ValueType intVT;
644 if (MVT::is128BitVector(LoadedVT) ||
645 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
647 else if (MVT::is64BitVector(LoadedVT) || LoadedVT == MVT::f64)
649 else if (LoadedVT == MVT::f32)
652 assert(0 && "Unaligned load of unsupported type");
654 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
655 SVOffset, LD->isVolatile(),
657 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
658 if (MVT::isFloatingPoint(VT) && LoadedVT != VT)
659 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
661 SDOperand Ops[] = { Result, Chain };
662 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
665 assert(MVT::isInteger(LoadedVT) && !MVT::isVector(LoadedVT) &&
666 "Unaligned load of unsupported type.");
668 // Compute the new VT that is half the size of the old one. This is an
670 unsigned NumBits = MVT::getSizeInBits(LoadedVT);
671 MVT::ValueType NewLoadedVT;
672 NewLoadedVT = MVT::getIntegerType(NumBits/2);
675 unsigned Alignment = LD->getAlignment();
676 unsigned IncrementSize = NumBits / 8;
677 ISD::LoadExtType HiExtType = LD->getExtensionType();
679 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
680 if (HiExtType == ISD::NON_EXTLOAD)
681 HiExtType = ISD::ZEXTLOAD;
683 // Load the value in two parts
685 if (TLI.isLittleEndian()) {
686 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
687 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
688 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
689 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
690 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
691 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
692 MinAlign(Alignment, IncrementSize));
694 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
695 NewLoadedVT,LD->isVolatile(), Alignment);
696 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
697 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
698 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
699 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
700 MinAlign(Alignment, IncrementSize));
703 // aggregate the two parts
704 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
705 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
706 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
708 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
711 SDOperand Ops[] = { Result, TF };
712 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
715 /// UnrollVectorOp - We know that the given vector has a legal type, however
716 /// the operation it performs is not legal and is an operation that we have
717 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
718 /// operating on each element individually.
719 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
720 MVT::ValueType VT = Op.getValueType();
721 assert(isTypeLegal(VT) &&
722 "Caller should expand or promote operands that are not legal!");
723 assert(Op.Val->getNumValues() == 1 &&
724 "Can't unroll a vector with multiple results!");
725 unsigned NE = MVT::getVectorNumElements(VT);
726 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
728 SmallVector<SDOperand, 8> Scalars;
729 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
730 for (unsigned i = 0; i != NE; ++i) {
731 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
732 SDOperand Operand = Op.getOperand(j);
733 MVT::ValueType OperandVT = Operand.getValueType();
734 if (MVT::isVector(OperandVT)) {
735 // A vector operand; extract a single element.
736 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
737 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
740 DAG.getConstant(i, MVT::i32));
742 // A scalar operand; just use it as is.
743 Operands[j] = Operand;
746 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
747 &Operands[0], Operands.size()));
750 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
753 /// GetFPLibCall - Return the right libcall for the given floating point type.
754 static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
755 RTLIB::Libcall Call_F32,
756 RTLIB::Libcall Call_F64,
757 RTLIB::Libcall Call_F80,
758 RTLIB::Libcall Call_PPCF128) {
760 VT == MVT::f32 ? Call_F32 :
761 VT == MVT::f64 ? Call_F64 :
762 VT == MVT::f80 ? Call_F80 :
763 VT == MVT::ppcf128 ? Call_PPCF128 :
764 RTLIB::UNKNOWN_LIBCALL;
767 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
768 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
769 /// is necessary to spill the vector being inserted into to memory, perform
770 /// the insert there, and then read the result back.
771 SDOperand SelectionDAGLegalize::
772 PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) {
773 SDOperand Tmp1 = Vec;
774 SDOperand Tmp2 = Val;
775 SDOperand Tmp3 = Idx;
777 // If the target doesn't support this, we have to spill the input vector
778 // to a temporary stack slot, update the element, then reload it. This is
779 // badness. We could also load the value into a vector register (either
780 // with a "move to register" or "extload into register" instruction, then
781 // permute it into place, if the idx is a constant and if the idx is
782 // supported by the target.
783 MVT::ValueType VT = Tmp1.getValueType();
784 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
785 MVT::ValueType IdxVT = Tmp3.getValueType();
786 MVT::ValueType PtrVT = TLI.getPointerTy();
787 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
789 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val);
790 int SPFI = StackPtrFI->getIndex();
793 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
794 PseudoSourceValue::getFixedStack(),
797 // Truncate or zero extend offset to target pointer type.
798 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
799 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
800 // Add the offset to the index.
801 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
802 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
803 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
804 // Store the scalar value.
805 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
806 PseudoSourceValue::getFixedStack(), SPFI, EltVT);
807 // Load the updated vector.
808 return DAG.getLoad(VT, Ch, StackPtr, PseudoSourceValue::getFixedStack(),SPFI);
811 /// LegalizeOp - We know that the specified value has a legal type, and
812 /// that its operands are legal. Now ensure that the operation itself
813 /// is legal, recursively ensuring that the operands' operations remain
815 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
816 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
819 assert(isTypeLegal(Op.getValueType()) &&
820 "Caller should expand or promote operands that are not legal!");
821 SDNode *Node = Op.Val;
823 // If this operation defines any values that cannot be represented in a
824 // register on this target, make sure to expand or promote them.
825 if (Node->getNumValues() > 1) {
826 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
827 if (getTypeAction(Node->getValueType(i)) != Legal) {
828 HandleOp(Op.getValue(i));
829 assert(LegalizedNodes.count(Op) &&
830 "Handling didn't add legal operands!");
831 return LegalizedNodes[Op];
835 // Note that LegalizeOp may be reentered even from single-use nodes, which
836 // means that we always must cache transformed nodes.
837 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
838 if (I != LegalizedNodes.end()) return I->second;
840 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
841 SDOperand Result = Op;
842 bool isCustom = false;
844 switch (Node->getOpcode()) {
845 case ISD::FrameIndex:
846 case ISD::EntryToken:
848 case ISD::BasicBlock:
849 case ISD::TargetFrameIndex:
850 case ISD::TargetJumpTable:
851 case ISD::TargetConstant:
852 case ISD::TargetConstantFP:
853 case ISD::TargetConstantPool:
854 case ISD::TargetGlobalAddress:
855 case ISD::TargetGlobalTLSAddress:
856 case ISD::TargetExternalSymbol:
859 case ISD::MEMOPERAND:
863 // Primitives must all be legal.
864 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
865 "This must be legal!");
868 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
869 // If this is a target node, legalize it by legalizing the operands then
870 // passing it through.
871 SmallVector<SDOperand, 8> Ops;
872 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
873 Ops.push_back(LegalizeOp(Node->getOperand(i)));
875 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
877 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
878 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
879 return Result.getValue(Op.ResNo);
881 // Otherwise this is an unhandled builtin node. splat.
883 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
885 assert(0 && "Do not know how to legalize this operator!");
887 case ISD::GLOBAL_OFFSET_TABLE:
888 case ISD::GlobalAddress:
889 case ISD::GlobalTLSAddress:
890 case ISD::ExternalSymbol:
891 case ISD::ConstantPool:
892 case ISD::JumpTable: // Nothing to do.
893 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
894 default: assert(0 && "This action is not supported yet!");
895 case TargetLowering::Custom:
896 Tmp1 = TLI.LowerOperation(Op, DAG);
897 if (Tmp1.Val) Result = Tmp1;
898 // FALLTHROUGH if the target doesn't want to lower this op after all.
899 case TargetLowering::Legal:
904 case ISD::RETURNADDR:
905 // The only option for these nodes is to custom lower them. If the target
906 // does not custom lower them, then return zero.
907 Tmp1 = TLI.LowerOperation(Op, DAG);
911 Result = DAG.getConstant(0, TLI.getPointerTy());
913 case ISD::FRAME_TO_ARGS_OFFSET: {
914 MVT::ValueType VT = Node->getValueType(0);
915 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
916 default: assert(0 && "This action is not supported yet!");
917 case TargetLowering::Custom:
918 Result = TLI.LowerOperation(Op, DAG);
919 if (Result.Val) break;
921 case TargetLowering::Legal:
922 Result = DAG.getConstant(0, VT);
927 case ISD::EXCEPTIONADDR: {
928 Tmp1 = LegalizeOp(Node->getOperand(0));
929 MVT::ValueType VT = Node->getValueType(0);
930 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
931 default: assert(0 && "This action is not supported yet!");
932 case TargetLowering::Expand: {
933 unsigned Reg = TLI.getExceptionAddressRegister();
934 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
937 case TargetLowering::Custom:
938 Result = TLI.LowerOperation(Op, DAG);
939 if (Result.Val) break;
941 case TargetLowering::Legal: {
942 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
943 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
949 if (Result.Val->getNumValues() == 1) break;
951 assert(Result.Val->getNumValues() == 2 &&
952 "Cannot return more than two values!");
954 // Since we produced two values, make sure to remember that we
955 // legalized both of them.
956 Tmp1 = LegalizeOp(Result);
957 Tmp2 = LegalizeOp(Result.getValue(1));
958 AddLegalizedOperand(Op.getValue(0), Tmp1);
959 AddLegalizedOperand(Op.getValue(1), Tmp2);
960 return Op.ResNo ? Tmp2 : Tmp1;
961 case ISD::EHSELECTION: {
962 Tmp1 = LegalizeOp(Node->getOperand(0));
963 Tmp2 = LegalizeOp(Node->getOperand(1));
964 MVT::ValueType VT = Node->getValueType(0);
965 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
966 default: assert(0 && "This action is not supported yet!");
967 case TargetLowering::Expand: {
968 unsigned Reg = TLI.getExceptionSelectorRegister();
969 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
972 case TargetLowering::Custom:
973 Result = TLI.LowerOperation(Op, DAG);
974 if (Result.Val) break;
976 case TargetLowering::Legal: {
977 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
978 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
984 if (Result.Val->getNumValues() == 1) break;
986 assert(Result.Val->getNumValues() == 2 &&
987 "Cannot return more than two values!");
989 // Since we produced two values, make sure to remember that we
990 // legalized both of them.
991 Tmp1 = LegalizeOp(Result);
992 Tmp2 = LegalizeOp(Result.getValue(1));
993 AddLegalizedOperand(Op.getValue(0), Tmp1);
994 AddLegalizedOperand(Op.getValue(1), Tmp2);
995 return Op.ResNo ? Tmp2 : Tmp1;
996 case ISD::EH_RETURN: {
997 MVT::ValueType VT = Node->getValueType(0);
998 // The only "good" option for this node is to custom lower it.
999 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1000 default: assert(0 && "This action is not supported at all!");
1001 case TargetLowering::Custom:
1002 Result = TLI.LowerOperation(Op, DAG);
1003 if (Result.Val) break;
1005 case TargetLowering::Legal:
1006 // Target does not know, how to lower this, lower to noop
1007 Result = LegalizeOp(Node->getOperand(0));
1012 case ISD::AssertSext:
1013 case ISD::AssertZext:
1014 Tmp1 = LegalizeOp(Node->getOperand(0));
1015 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1017 case ISD::MERGE_VALUES:
1018 // Legalize eliminates MERGE_VALUES nodes.
1019 Result = Node->getOperand(Op.ResNo);
1021 case ISD::CopyFromReg:
1022 Tmp1 = LegalizeOp(Node->getOperand(0));
1023 Result = Op.getValue(0);
1024 if (Node->getNumValues() == 2) {
1025 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1027 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1028 if (Node->getNumOperands() == 3) {
1029 Tmp2 = LegalizeOp(Node->getOperand(2));
1030 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1032 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1034 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1036 // Since CopyFromReg produces two values, make sure to remember that we
1037 // legalized both of them.
1038 AddLegalizedOperand(Op.getValue(0), Result);
1039 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1040 return Result.getValue(Op.ResNo);
1042 MVT::ValueType VT = Op.getValueType();
1043 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1044 default: assert(0 && "This action is not supported yet!");
1045 case TargetLowering::Expand:
1046 if (MVT::isInteger(VT))
1047 Result = DAG.getConstant(0, VT);
1048 else if (MVT::isFloatingPoint(VT))
1049 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
1052 assert(0 && "Unknown value type!");
1054 case TargetLowering::Legal:
1060 case ISD::INTRINSIC_W_CHAIN:
1061 case ISD::INTRINSIC_WO_CHAIN:
1062 case ISD::INTRINSIC_VOID: {
1063 SmallVector<SDOperand, 8> Ops;
1064 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1065 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1066 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1068 // Allow the target to custom lower its intrinsics if it wants to.
1069 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1070 TargetLowering::Custom) {
1071 Tmp3 = TLI.LowerOperation(Result, DAG);
1072 if (Tmp3.Val) Result = Tmp3;
1075 if (Result.Val->getNumValues() == 1) break;
1077 // Must have return value and chain result.
1078 assert(Result.Val->getNumValues() == 2 &&
1079 "Cannot return more than two values!");
1081 // Since loads produce two values, make sure to remember that we
1082 // legalized both of them.
1083 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1084 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1085 return Result.getValue(Op.ResNo);
1089 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
1090 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1092 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
1093 case TargetLowering::Promote:
1094 default: assert(0 && "This action is not supported yet!");
1095 case TargetLowering::Expand: {
1096 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1097 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1098 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
1100 if (MMI && (useDEBUG_LOC || useLABEL)) {
1101 const std::string &FName =
1102 cast<StringSDNode>(Node->getOperand(3))->getValue();
1103 const std::string &DirName =
1104 cast<StringSDNode>(Node->getOperand(4))->getValue();
1105 unsigned SrcFile = MMI->RecordSource(DirName, FName);
1107 SmallVector<SDOperand, 8> Ops;
1108 Ops.push_back(Tmp1); // chain
1109 SDOperand LineOp = Node->getOperand(1);
1110 SDOperand ColOp = Node->getOperand(2);
1113 Ops.push_back(LineOp); // line #
1114 Ops.push_back(ColOp); // col #
1115 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1116 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1118 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
1119 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
1120 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1121 Ops.push_back(DAG.getConstant(ID, MVT::i32));
1122 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label
1123 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size());
1126 Result = Tmp1; // chain
1130 case TargetLowering::Legal:
1131 if (Tmp1 != Node->getOperand(0) ||
1132 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1133 SmallVector<SDOperand, 8> Ops;
1134 Ops.push_back(Tmp1);
1135 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1136 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1137 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1139 // Otherwise promote them.
1140 Ops.push_back(PromoteOp(Node->getOperand(1)));
1141 Ops.push_back(PromoteOp(Node->getOperand(2)));
1143 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1144 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1145 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1152 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1153 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1154 default: assert(0 && "This action is not supported yet!");
1155 case TargetLowering::Legal:
1156 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1157 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1158 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1159 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1161 case TargetLowering::Expand:
1162 Result = LegalizeOp(Node->getOperand(0));
1167 case ISD::DEBUG_LOC:
1168 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1169 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1170 default: assert(0 && "This action is not supported yet!");
1171 case TargetLowering::Legal:
1172 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1173 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1174 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1175 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1176 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1182 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!");
1183 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1184 default: assert(0 && "This action is not supported yet!");
1185 case TargetLowering::Legal:
1186 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1187 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1188 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand.
1189 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1191 case TargetLowering::Expand:
1192 Result = LegalizeOp(Node->getOperand(0));
1198 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1199 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1200 default: assert(0 && "This action is not supported yet!");
1201 case TargetLowering::Legal:
1202 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1203 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1204 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1205 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1206 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1208 case TargetLowering::Expand:
1210 Result = LegalizeOp(Node->getOperand(0));
1215 case ISD::MEMBARRIER: {
1216 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1217 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1218 default: assert(0 && "This action is not supported yet!");
1219 case TargetLowering::Legal: {
1221 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1222 for (int x = 1; x < 6; ++x) {
1223 Ops[x] = Node->getOperand(x);
1224 if (!isTypeLegal(Ops[x].getValueType()))
1225 Ops[x] = PromoteOp(Ops[x]);
1227 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1230 case TargetLowering::Expand:
1231 //There is no libgcc call for this op
1232 Result = Node->getOperand(0); // Noop
1238 case ISD::ATOMIC_LCS:
1239 case ISD::ATOMIC_LAS:
1240 case ISD::ATOMIC_SWAP: {
1241 assert(((Node->getNumOperands() == 4 && Node->getOpcode() == ISD::ATOMIC_LCS) ||
1242 (Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_LAS) ||
1243 (Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_SWAP)) &&
1244 "Invalid Atomic node!");
1245 int num = Node->getOpcode() == ISD::ATOMIC_LCS ? 4 : 3;
1247 for (int x = 0; x < num; ++x)
1248 Ops[x] = LegalizeOp(Node->getOperand(x));
1249 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num);
1251 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1252 default: assert(0 && "This action is not supported yet!");
1253 case TargetLowering::Custom:
1254 Result = TLI.LowerOperation(Result, DAG);
1256 case TargetLowering::Legal:
1259 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1260 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1261 return Result.getValue(Op.ResNo);
1264 case ISD::Constant: {
1265 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1267 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1269 // We know we don't need to expand constants here, constants only have one
1270 // value and we check that it is fine above.
1272 if (opAction == TargetLowering::Custom) {
1273 Tmp1 = TLI.LowerOperation(Result, DAG);
1279 case ISD::ConstantFP: {
1280 // Spill FP immediates to the constant pool if the target cannot directly
1281 // codegen them. Targets often have some immediate values that can be
1282 // efficiently generated into an FP register without a load. We explicitly
1283 // leave these constants as ConstantFP nodes for the target to deal with.
1284 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1286 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1287 default: assert(0 && "This action is not supported yet!");
1288 case TargetLowering::Legal:
1290 case TargetLowering::Custom:
1291 Tmp3 = TLI.LowerOperation(Result, DAG);
1297 case TargetLowering::Expand: {
1298 // Check to see if this FP immediate is already legal.
1299 bool isLegal = false;
1300 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1301 E = TLI.legal_fpimm_end(); I != E; ++I) {
1302 if (CFP->isExactlyValue(*I)) {
1307 // If this is a legal constant, turn it into a TargetConstantFP node.
1310 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1315 case ISD::TokenFactor:
1316 if (Node->getNumOperands() == 2) {
1317 Tmp1 = LegalizeOp(Node->getOperand(0));
1318 Tmp2 = LegalizeOp(Node->getOperand(1));
1319 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1320 } else if (Node->getNumOperands() == 3) {
1321 Tmp1 = LegalizeOp(Node->getOperand(0));
1322 Tmp2 = LegalizeOp(Node->getOperand(1));
1323 Tmp3 = LegalizeOp(Node->getOperand(2));
1324 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1326 SmallVector<SDOperand, 8> Ops;
1327 // Legalize the operands.
1328 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1329 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1330 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1334 case ISD::FORMAL_ARGUMENTS:
1336 // The only option for this is to custom lower it.
1337 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1338 assert(Tmp3.Val && "Target didn't custom lower this node!");
1339 // A call within a calling sequence must be legalized to something
1340 // other than the normal CALLSEQ_END. Violating this gets Legalize
1341 // into an infinite loop.
1342 assert ((!IsLegalizingCall ||
1343 Node->getOpcode() != ISD::CALL ||
1344 Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) &&
1345 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1347 // The number of incoming and outgoing values should match; unless the final
1348 // outgoing value is a flag.
1349 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1350 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1351 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1353 "Lowering call/formal_arguments produced unexpected # results!");
1355 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1356 // remember that we legalized all of them, so it doesn't get relegalized.
1357 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1358 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1360 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1363 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1366 case ISD::EXTRACT_SUBREG: {
1367 Tmp1 = LegalizeOp(Node->getOperand(0));
1368 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1369 assert(idx && "Operand must be a constant");
1370 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1371 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1374 case ISD::INSERT_SUBREG: {
1375 Tmp1 = LegalizeOp(Node->getOperand(0));
1376 Tmp2 = LegalizeOp(Node->getOperand(1));
1377 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1378 assert(idx && "Operand must be a constant");
1379 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1380 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1383 case ISD::BUILD_VECTOR:
1384 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1385 default: assert(0 && "This action is not supported yet!");
1386 case TargetLowering::Custom:
1387 Tmp3 = TLI.LowerOperation(Result, DAG);
1393 case TargetLowering::Expand:
1394 Result = ExpandBUILD_VECTOR(Result.Val);
1398 case ISD::INSERT_VECTOR_ELT:
1399 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1400 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1402 // The type of the value to insert may not be legal, even though the vector
1403 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1405 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1406 default: assert(0 && "Cannot expand insert element operand");
1407 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1408 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1410 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1412 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1413 Node->getValueType(0))) {
1414 default: assert(0 && "This action is not supported yet!");
1415 case TargetLowering::Legal:
1417 case TargetLowering::Custom:
1418 Tmp4 = TLI.LowerOperation(Result, DAG);
1424 case TargetLowering::Expand: {
1425 // If the insert index is a constant, codegen this as a scalar_to_vector,
1426 // then a shuffle that inserts it into the right position in the vector.
1427 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1428 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1429 // match the element type of the vector being created.
1430 if (Tmp2.getValueType() ==
1431 MVT::getVectorElementType(Op.getValueType())) {
1432 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1433 Tmp1.getValueType(), Tmp2);
1435 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1436 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1437 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1439 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1440 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1441 // elt 0 of the RHS.
1442 SmallVector<SDOperand, 8> ShufOps;
1443 for (unsigned i = 0; i != NumElts; ++i) {
1444 if (i != InsertPos->getValue())
1445 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1447 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1449 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1450 &ShufOps[0], ShufOps.size());
1452 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1453 Tmp1, ScVec, ShufMask);
1454 Result = LegalizeOp(Result);
1458 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1463 case ISD::SCALAR_TO_VECTOR:
1464 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1465 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1469 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1470 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1471 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1472 Node->getValueType(0))) {
1473 default: assert(0 && "This action is not supported yet!");
1474 case TargetLowering::Legal:
1476 case TargetLowering::Custom:
1477 Tmp3 = TLI.LowerOperation(Result, DAG);
1483 case TargetLowering::Expand:
1484 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1488 case ISD::VECTOR_SHUFFLE:
1489 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1490 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1491 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1493 // Allow targets to custom lower the SHUFFLEs they support.
1494 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1495 default: assert(0 && "Unknown operation action!");
1496 case TargetLowering::Legal:
1497 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1498 "vector shuffle should not be created if not legal!");
1500 case TargetLowering::Custom:
1501 Tmp3 = TLI.LowerOperation(Result, DAG);
1507 case TargetLowering::Expand: {
1508 MVT::ValueType VT = Node->getValueType(0);
1509 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1510 MVT::ValueType PtrVT = TLI.getPointerTy();
1511 SDOperand Mask = Node->getOperand(2);
1512 unsigned NumElems = Mask.getNumOperands();
1513 SmallVector<SDOperand,8> Ops;
1514 for (unsigned i = 0; i != NumElems; ++i) {
1515 SDOperand Arg = Mask.getOperand(i);
1516 if (Arg.getOpcode() == ISD::UNDEF) {
1517 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1519 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1520 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1522 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1523 DAG.getConstant(Idx, PtrVT)));
1525 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1526 DAG.getConstant(Idx - NumElems, PtrVT)));
1529 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1532 case TargetLowering::Promote: {
1533 // Change base type to a different vector type.
1534 MVT::ValueType OVT = Node->getValueType(0);
1535 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1537 // Cast the two input vectors.
1538 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1539 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1541 // Convert the shuffle mask to the right # elements.
1542 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1543 assert(Tmp3.Val && "Shuffle not legal?");
1544 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1545 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1551 case ISD::EXTRACT_VECTOR_ELT:
1552 Tmp1 = Node->getOperand(0);
1553 Tmp2 = LegalizeOp(Node->getOperand(1));
1554 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1555 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1558 case ISD::EXTRACT_SUBVECTOR:
1559 Tmp1 = Node->getOperand(0);
1560 Tmp2 = LegalizeOp(Node->getOperand(1));
1561 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1562 Result = ExpandEXTRACT_SUBVECTOR(Result);
1565 case ISD::CALLSEQ_START: {
1566 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1568 // Recursively Legalize all of the inputs of the call end that do not lead
1569 // to this call start. This ensures that any libcalls that need be inserted
1570 // are inserted *before* the CALLSEQ_START.
1571 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1572 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1573 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1577 // Now that we legalized all of the inputs (which may have inserted
1578 // libcalls) create the new CALLSEQ_START node.
1579 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1581 // Merge in the last call, to ensure that this call start after the last
1583 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1584 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1585 Tmp1 = LegalizeOp(Tmp1);
1588 // Do not try to legalize the target-specific arguments (#1+).
1589 if (Tmp1 != Node->getOperand(0)) {
1590 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1592 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1595 // Remember that the CALLSEQ_START is legalized.
1596 AddLegalizedOperand(Op.getValue(0), Result);
1597 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1598 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1600 // Now that the callseq_start and all of the non-call nodes above this call
1601 // sequence have been legalized, legalize the call itself. During this
1602 // process, no libcalls can/will be inserted, guaranteeing that no calls
1604 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1605 SDOperand InCallSEQ = LastCALLSEQ_END;
1606 // Note that we are selecting this call!
1607 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1608 IsLegalizingCall = true;
1610 // Legalize the call, starting from the CALLSEQ_END.
1611 LegalizeOp(LastCALLSEQ_END);
1612 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1615 case ISD::CALLSEQ_END:
1616 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1617 // will cause this node to be legalized as well as handling libcalls right.
1618 if (LastCALLSEQ_END.Val != Node) {
1619 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1620 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1621 assert(I != LegalizedNodes.end() &&
1622 "Legalizing the call start should have legalized this node!");
1626 // Otherwise, the call start has been legalized and everything is going
1627 // according to plan. Just legalize ourselves normally here.
1628 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1629 // Do not try to legalize the target-specific arguments (#1+), except for
1630 // an optional flag input.
1631 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1632 if (Tmp1 != Node->getOperand(0)) {
1633 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1635 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1638 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1639 if (Tmp1 != Node->getOperand(0) ||
1640 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1641 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1644 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1647 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1648 // This finishes up call legalization.
1649 IsLegalizingCall = false;
1651 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1652 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1653 if (Node->getNumValues() == 2)
1654 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1655 return Result.getValue(Op.ResNo);
1656 case ISD::DYNAMIC_STACKALLOC: {
1657 MVT::ValueType VT = Node->getValueType(0);
1658 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1659 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1660 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1661 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1663 Tmp1 = Result.getValue(0);
1664 Tmp2 = Result.getValue(1);
1665 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1666 default: assert(0 && "This action is not supported yet!");
1667 case TargetLowering::Expand: {
1668 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1669 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1670 " not tell us which reg is the stack pointer!");
1671 SDOperand Chain = Tmp1.getOperand(0);
1673 // Chain the dynamic stack allocation so that it doesn't modify the stack
1674 // pointer when other instructions are using the stack.
1675 Chain = DAG.getCALLSEQ_START(Chain,
1676 DAG.getConstant(0, TLI.getPointerTy()));
1678 SDOperand Size = Tmp2.getOperand(1);
1679 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1680 Chain = SP.getValue(1);
1681 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1682 unsigned StackAlign =
1683 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1684 if (Align > StackAlign)
1685 SP = DAG.getNode(ISD::AND, VT, SP,
1686 DAG.getConstant(-(uint64_t)Align, VT));
1687 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1688 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1691 DAG.getCALLSEQ_END(Chain,
1692 DAG.getConstant(0, TLI.getPointerTy()),
1693 DAG.getConstant(0, TLI.getPointerTy()),
1696 Tmp1 = LegalizeOp(Tmp1);
1697 Tmp2 = LegalizeOp(Tmp2);
1700 case TargetLowering::Custom:
1701 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1703 Tmp1 = LegalizeOp(Tmp3);
1704 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1707 case TargetLowering::Legal:
1710 // Since this op produce two values, make sure to remember that we
1711 // legalized both of them.
1712 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1713 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1714 return Op.ResNo ? Tmp2 : Tmp1;
1716 case ISD::INLINEASM: {
1717 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1718 bool Changed = false;
1719 // Legalize all of the operands of the inline asm, in case they are nodes
1720 // that need to be expanded or something. Note we skip the asm string and
1721 // all of the TargetConstant flags.
1722 SDOperand Op = LegalizeOp(Ops[0]);
1723 Changed = Op != Ops[0];
1726 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1727 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1728 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1729 for (++i; NumVals; ++i, --NumVals) {
1730 SDOperand Op = LegalizeOp(Ops[i]);
1739 Op = LegalizeOp(Ops.back());
1740 Changed |= Op != Ops.back();
1745 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1747 // INLINE asm returns a chain and flag, make sure to add both to the map.
1748 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1749 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1750 return Result.getValue(Op.ResNo);
1753 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1754 // Ensure that libcalls are emitted before a branch.
1755 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1756 Tmp1 = LegalizeOp(Tmp1);
1757 LastCALLSEQ_END = DAG.getEntryNode();
1759 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1762 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1763 // Ensure that libcalls are emitted before a branch.
1764 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1765 Tmp1 = LegalizeOp(Tmp1);
1766 LastCALLSEQ_END = DAG.getEntryNode();
1768 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1769 default: assert(0 && "Indirect target must be legal type (pointer)!");
1771 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1774 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1777 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1778 // Ensure that libcalls are emitted before a branch.
1779 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1780 Tmp1 = LegalizeOp(Tmp1);
1781 LastCALLSEQ_END = DAG.getEntryNode();
1783 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1784 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1786 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1787 default: assert(0 && "This action is not supported yet!");
1788 case TargetLowering::Legal: break;
1789 case TargetLowering::Custom:
1790 Tmp1 = TLI.LowerOperation(Result, DAG);
1791 if (Tmp1.Val) Result = Tmp1;
1793 case TargetLowering::Expand: {
1794 SDOperand Chain = Result.getOperand(0);
1795 SDOperand Table = Result.getOperand(1);
1796 SDOperand Index = Result.getOperand(2);
1798 MVT::ValueType PTy = TLI.getPointerTy();
1799 MachineFunction &MF = DAG.getMachineFunction();
1800 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1801 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1802 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1805 switch (EntrySize) {
1806 default: assert(0 && "Size of jump table not supported yet."); break;
1807 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1808 PseudoSourceValue::getJumpTable(), 0); break;
1809 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1810 PseudoSourceValue::getJumpTable(), 0); break;
1814 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1815 // For PIC, the sequence is:
1816 // BRIND(load(Jumptable + index) + RelocBase)
1817 // RelocBase can be JumpTable, GOT or some sort of global base.
1818 if (PTy != MVT::i32)
1819 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1820 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1821 TLI.getPICJumpTableRelocBase(Table, DAG));
1823 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1828 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1829 // Ensure that libcalls are emitted before a return.
1830 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1831 Tmp1 = LegalizeOp(Tmp1);
1832 LastCALLSEQ_END = DAG.getEntryNode();
1834 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1835 case Expand: assert(0 && "It's impossible to expand bools");
1837 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1840 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1842 // The top bits of the promoted condition are not necessarily zero, ensure
1843 // that the value is properly zero extended.
1844 unsigned BitWidth = Tmp2.getValueSizeInBits();
1845 if (!DAG.MaskedValueIsZero(Tmp2,
1846 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1847 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1852 // Basic block destination (Op#2) is always legal.
1853 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1855 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1856 default: assert(0 && "This action is not supported yet!");
1857 case TargetLowering::Legal: break;
1858 case TargetLowering::Custom:
1859 Tmp1 = TLI.LowerOperation(Result, DAG);
1860 if (Tmp1.Val) Result = Tmp1;
1862 case TargetLowering::Expand:
1863 // Expand brcond's setcc into its constituent parts and create a BR_CC
1865 if (Tmp2.getOpcode() == ISD::SETCC) {
1866 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1867 Tmp2.getOperand(0), Tmp2.getOperand(1),
1868 Node->getOperand(2));
1870 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1871 DAG.getCondCode(ISD::SETNE), Tmp2,
1872 DAG.getConstant(0, Tmp2.getValueType()),
1873 Node->getOperand(2));
1879 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1880 // Ensure that libcalls are emitted before a branch.
1881 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1882 Tmp1 = LegalizeOp(Tmp1);
1883 Tmp2 = Node->getOperand(2); // LHS
1884 Tmp3 = Node->getOperand(3); // RHS
1885 Tmp4 = Node->getOperand(1); // CC
1887 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1888 LastCALLSEQ_END = DAG.getEntryNode();
1890 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1891 // the LHS is a legal SETCC itself. In this case, we need to compare
1892 // the result against zero to select between true and false values.
1893 if (Tmp3.Val == 0) {
1894 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1895 Tmp4 = DAG.getCondCode(ISD::SETNE);
1898 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1899 Node->getOperand(4));
1901 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1902 default: assert(0 && "Unexpected action for BR_CC!");
1903 case TargetLowering::Legal: break;
1904 case TargetLowering::Custom:
1905 Tmp4 = TLI.LowerOperation(Result, DAG);
1906 if (Tmp4.Val) Result = Tmp4;
1911 LoadSDNode *LD = cast<LoadSDNode>(Node);
1912 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1913 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1915 ISD::LoadExtType ExtType = LD->getExtensionType();
1916 if (ExtType == ISD::NON_EXTLOAD) {
1917 MVT::ValueType VT = Node->getValueType(0);
1918 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1919 Tmp3 = Result.getValue(0);
1920 Tmp4 = Result.getValue(1);
1922 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1923 default: assert(0 && "This action is not supported yet!");
1924 case TargetLowering::Legal:
1925 // If this is an unaligned load and the target doesn't support it,
1927 if (!TLI.allowsUnalignedMemoryAccesses()) {
1928 unsigned ABIAlignment = TLI.getTargetData()->
1929 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
1930 if (LD->getAlignment() < ABIAlignment){
1931 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1933 Tmp3 = Result.getOperand(0);
1934 Tmp4 = Result.getOperand(1);
1935 Tmp3 = LegalizeOp(Tmp3);
1936 Tmp4 = LegalizeOp(Tmp4);
1940 case TargetLowering::Custom:
1941 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1943 Tmp3 = LegalizeOp(Tmp1);
1944 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1947 case TargetLowering::Promote: {
1948 // Only promote a load of vector type to another.
1949 assert(MVT::isVector(VT) && "Cannot promote this load!");
1950 // Change base type to a different vector type.
1951 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1953 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1954 LD->getSrcValueOffset(),
1955 LD->isVolatile(), LD->getAlignment());
1956 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1957 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1961 // Since loads produce two values, make sure to remember that we
1962 // legalized both of them.
1963 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1964 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1965 return Op.ResNo ? Tmp4 : Tmp3;
1967 MVT::ValueType SrcVT = LD->getMemoryVT();
1968 unsigned SrcWidth = MVT::getSizeInBits(SrcVT);
1969 int SVOffset = LD->getSrcValueOffset();
1970 unsigned Alignment = LD->getAlignment();
1971 bool isVolatile = LD->isVolatile();
1973 if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) &&
1974 // Some targets pretend to have an i1 loading operation, and actually
1975 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1976 // bits are guaranteed to be zero; it helps the optimizers understand
1977 // that these bits are zero. It is also useful for EXTLOAD, since it
1978 // tells the optimizers that those bits are undefined. It would be
1979 // nice to have an effective generic way of getting these benefits...
1980 // Until such a way is found, don't insist on promoting i1 here.
1981 (SrcVT != MVT::i1 ||
1982 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1983 // Promote to a byte-sized load if not loading an integral number of
1984 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1985 unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT);
1986 MVT::ValueType NVT = MVT::getIntegerType(NewWidth);
1989 // The extra bits are guaranteed to be zero, since we stored them that
1990 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1992 ISD::LoadExtType NewExtType =
1993 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1995 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
1996 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1997 NVT, isVolatile, Alignment);
1999 Ch = Result.getValue(1); // The chain.
2001 if (ExtType == ISD::SEXTLOAD)
2002 // Having the top bits zero doesn't help when sign extending.
2003 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2004 Result, DAG.getValueType(SrcVT));
2005 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2006 // All the top bits are guaranteed to be zero - inform the optimizers.
2007 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2008 DAG.getValueType(SrcVT));
2010 Tmp1 = LegalizeOp(Result);
2011 Tmp2 = LegalizeOp(Ch);
2012 } else if (SrcWidth & (SrcWidth - 1)) {
2013 // If not loading a power-of-2 number of bits, expand as two loads.
2014 assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) &&
2015 "Unsupported extload!");
2016 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2017 assert(RoundWidth < SrcWidth);
2018 unsigned ExtraWidth = SrcWidth - RoundWidth;
2019 assert(ExtraWidth < RoundWidth);
2020 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2021 "Load size not an integral number of bytes!");
2022 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
2023 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
2024 SDOperand Lo, Hi, Ch;
2025 unsigned IncrementSize;
2027 if (TLI.isLittleEndian()) {
2028 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2029 // Load the bottom RoundWidth bits.
2030 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2031 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2034 // Load the remaining ExtraWidth bits.
2035 IncrementSize = RoundWidth / 8;
2036 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2037 DAG.getIntPtrConstant(IncrementSize));
2038 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2039 LD->getSrcValue(), SVOffset + IncrementSize,
2040 ExtraVT, isVolatile,
2041 MinAlign(Alignment, IncrementSize));
2043 // Build a factor node to remember that this load is independent of the
2045 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2048 // Move the top bits to the right place.
2049 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2050 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2052 // Join the hi and lo parts.
2053 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2055 // Big endian - avoid unaligned loads.
2056 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2057 // Load the top RoundWidth bits.
2058 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2059 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2062 // Load the remaining ExtraWidth bits.
2063 IncrementSize = RoundWidth / 8;
2064 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2065 DAG.getIntPtrConstant(IncrementSize));
2066 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2067 LD->getSrcValue(), SVOffset + IncrementSize,
2068 ExtraVT, isVolatile,
2069 MinAlign(Alignment, IncrementSize));
2071 // Build a factor node to remember that this load is independent of the
2073 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2076 // Move the top bits to the right place.
2077 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2078 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2080 // Join the hi and lo parts.
2081 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2084 Tmp1 = LegalizeOp(Result);
2085 Tmp2 = LegalizeOp(Ch);
2087 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2088 default: assert(0 && "This action is not supported yet!");
2089 case TargetLowering::Custom:
2092 case TargetLowering::Legal:
2093 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2094 Tmp1 = Result.getValue(0);
2095 Tmp2 = Result.getValue(1);
2098 Tmp3 = TLI.LowerOperation(Result, DAG);
2100 Tmp1 = LegalizeOp(Tmp3);
2101 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2104 // If this is an unaligned load and the target doesn't support it,
2106 if (!TLI.allowsUnalignedMemoryAccesses()) {
2107 unsigned ABIAlignment = TLI.getTargetData()->
2108 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
2109 if (LD->getAlignment() < ABIAlignment){
2110 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
2112 Tmp1 = Result.getOperand(0);
2113 Tmp2 = Result.getOperand(1);
2114 Tmp1 = LegalizeOp(Tmp1);
2115 Tmp2 = LegalizeOp(Tmp2);
2120 case TargetLowering::Expand:
2121 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2122 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2123 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2124 LD->getSrcValueOffset(),
2125 LD->isVolatile(), LD->getAlignment());
2126 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2127 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2128 Tmp2 = LegalizeOp(Load.getValue(1));
2131 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2132 // Turn the unsupported load into an EXTLOAD followed by an explicit
2133 // zero/sign extend inreg.
2134 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2135 Tmp1, Tmp2, LD->getSrcValue(),
2136 LD->getSrcValueOffset(), SrcVT,
2137 LD->isVolatile(), LD->getAlignment());
2139 if (ExtType == ISD::SEXTLOAD)
2140 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2141 Result, DAG.getValueType(SrcVT));
2143 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2144 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2145 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2150 // Since loads produce two values, make sure to remember that we legalized
2152 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2153 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2154 return Op.ResNo ? Tmp2 : Tmp1;
2157 case ISD::EXTRACT_ELEMENT: {
2158 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
2159 switch (getTypeAction(OpTy)) {
2160 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2162 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2164 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2165 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
2166 TLI.getShiftAmountTy()));
2167 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2170 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2171 Node->getOperand(0));
2175 // Get both the low and high parts.
2176 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2177 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2178 Result = Tmp2; // 1 -> Hi
2180 Result = Tmp1; // 0 -> Lo
2186 case ISD::CopyToReg:
2187 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2189 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2190 "Register type must be legal!");
2191 // Legalize the incoming value (must be a legal type).
2192 Tmp2 = LegalizeOp(Node->getOperand(2));
2193 if (Node->getNumValues() == 1) {
2194 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2196 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2197 if (Node->getNumOperands() == 4) {
2198 Tmp3 = LegalizeOp(Node->getOperand(3));
2199 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2202 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2205 // Since this produces two values, make sure to remember that we legalized
2207 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2208 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2214 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2216 // Ensure that libcalls are emitted before a return.
2217 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2218 Tmp1 = LegalizeOp(Tmp1);
2219 LastCALLSEQ_END = DAG.getEntryNode();
2221 switch (Node->getNumOperands()) {
2223 Tmp2 = Node->getOperand(1);
2224 Tmp3 = Node->getOperand(2); // Signness
2225 switch (getTypeAction(Tmp2.getValueType())) {
2227 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2230 if (!MVT::isVector(Tmp2.getValueType())) {
2232 ExpandOp(Tmp2, Lo, Hi);
2234 // Big endian systems want the hi reg first.
2235 if (TLI.isBigEndian())
2239 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2241 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2242 Result = LegalizeOp(Result);
2244 SDNode *InVal = Tmp2.Val;
2245 int InIx = Tmp2.ResNo;
2246 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
2247 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
2249 // Figure out if there is a simple type corresponding to this Vector
2250 // type. If so, convert to the vector type.
2251 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2252 if (TLI.isTypeLegal(TVT)) {
2253 // Turn this into a return of the vector type.
2254 Tmp2 = LegalizeOp(Tmp2);
2255 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2256 } else if (NumElems == 1) {
2257 // Turn this into a return of the scalar type.
2258 Tmp2 = ScalarizeVectorOp(Tmp2);
2259 Tmp2 = LegalizeOp(Tmp2);
2260 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2262 // FIXME: Returns of gcc generic vectors smaller than a legal type
2263 // should be returned in integer registers!
2265 // The scalarized value type may not be legal, e.g. it might require
2266 // promotion or expansion. Relegalize the return.
2267 Result = LegalizeOp(Result);
2269 // FIXME: Returns of gcc generic vectors larger than a legal vector
2270 // type should be returned by reference!
2272 SplitVectorOp(Tmp2, Lo, Hi);
2273 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2274 Result = LegalizeOp(Result);
2279 Tmp2 = PromoteOp(Node->getOperand(1));
2280 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2281 Result = LegalizeOp(Result);
2286 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2288 default: { // ret <values>
2289 SmallVector<SDOperand, 8> NewValues;
2290 NewValues.push_back(Tmp1);
2291 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2292 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2294 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2295 NewValues.push_back(Node->getOperand(i+1));
2299 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
2300 "FIXME: TODO: implement returning non-legal vector types!");
2301 ExpandOp(Node->getOperand(i), Lo, Hi);
2302 NewValues.push_back(Lo);
2303 NewValues.push_back(Node->getOperand(i+1));
2305 NewValues.push_back(Hi);
2306 NewValues.push_back(Node->getOperand(i+1));
2311 assert(0 && "Can't promote multiple return value yet!");
2314 if (NewValues.size() == Node->getNumOperands())
2315 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2317 Result = DAG.getNode(ISD::RET, MVT::Other,
2318 &NewValues[0], NewValues.size());
2323 if (Result.getOpcode() == ISD::RET) {
2324 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2325 default: assert(0 && "This action is not supported yet!");
2326 case TargetLowering::Legal: break;
2327 case TargetLowering::Custom:
2328 Tmp1 = TLI.LowerOperation(Result, DAG);
2329 if (Tmp1.Val) Result = Tmp1;
2335 StoreSDNode *ST = cast<StoreSDNode>(Node);
2336 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2337 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2338 int SVOffset = ST->getSrcValueOffset();
2339 unsigned Alignment = ST->getAlignment();
2340 bool isVolatile = ST->isVolatile();
2342 if (!ST->isTruncatingStore()) {
2343 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2344 // FIXME: We shouldn't do this for TargetConstantFP's.
2345 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2346 // to phase ordering between legalized code and the dag combiner. This
2347 // probably means that we need to integrate dag combiner and legalizer
2349 // We generally can't do this one for long doubles.
2350 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2351 if (CFP->getValueType(0) == MVT::f32 &&
2352 getTypeAction(MVT::i32) == Legal) {
2353 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2354 convertToAPInt().zextOrTrunc(32),
2356 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2357 SVOffset, isVolatile, Alignment);
2359 } else if (CFP->getValueType(0) == MVT::f64) {
2360 // If this target supports 64-bit registers, do a single 64-bit store.
2361 if (getTypeAction(MVT::i64) == Legal) {
2362 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2363 zextOrTrunc(64), MVT::i64);
2364 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2365 SVOffset, isVolatile, Alignment);
2367 } else if (getTypeAction(MVT::i32) == Legal) {
2368 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2369 // stores. If the target supports neither 32- nor 64-bits, this
2370 // xform is certainly not worth it.
2371 const APInt &IntVal =CFP->getValueAPF().convertToAPInt();
2372 SDOperand Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2373 SDOperand Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2374 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2376 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2377 SVOffset, isVolatile, Alignment);
2378 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2379 DAG.getIntPtrConstant(4));
2380 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2381 isVolatile, MinAlign(Alignment, 4U));
2383 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2389 switch (getTypeAction(ST->getMemoryVT())) {
2391 Tmp3 = LegalizeOp(ST->getValue());
2392 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2395 MVT::ValueType VT = Tmp3.getValueType();
2396 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2397 default: assert(0 && "This action is not supported yet!");
2398 case TargetLowering::Legal:
2399 // If this is an unaligned store and the target doesn't support it,
2401 if (!TLI.allowsUnalignedMemoryAccesses()) {
2402 unsigned ABIAlignment = TLI.getTargetData()->
2403 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2404 if (ST->getAlignment() < ABIAlignment)
2405 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2409 case TargetLowering::Custom:
2410 Tmp1 = TLI.LowerOperation(Result, DAG);
2411 if (Tmp1.Val) Result = Tmp1;
2413 case TargetLowering::Promote:
2414 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2415 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2416 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2417 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2418 ST->getSrcValue(), SVOffset, isVolatile,
2425 // Truncate the value and store the result.
2426 Tmp3 = PromoteOp(ST->getValue());
2427 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2428 SVOffset, ST->getMemoryVT(),
2429 isVolatile, Alignment);
2433 unsigned IncrementSize = 0;
2436 // If this is a vector type, then we have to calculate the increment as
2437 // the product of the element size in bytes, and the number of elements
2438 // in the high half of the vector.
2439 if (MVT::isVector(ST->getValue().getValueType())) {
2440 SDNode *InVal = ST->getValue().Val;
2441 int InIx = ST->getValue().ResNo;
2442 MVT::ValueType InVT = InVal->getValueType(InIx);
2443 unsigned NumElems = MVT::getVectorNumElements(InVT);
2444 MVT::ValueType EVT = MVT::getVectorElementType(InVT);
2446 // Figure out if there is a simple type corresponding to this Vector
2447 // type. If so, convert to the vector type.
2448 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2449 if (TLI.isTypeLegal(TVT)) {
2450 // Turn this into a normal store of the vector type.
2451 Tmp3 = LegalizeOp(ST->getValue());
2452 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2453 SVOffset, isVolatile, Alignment);
2454 Result = LegalizeOp(Result);
2456 } else if (NumElems == 1) {
2457 // Turn this into a normal store of the scalar type.
2458 Tmp3 = ScalarizeVectorOp(ST->getValue());
2459 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2460 SVOffset, isVolatile, Alignment);
2461 // The scalarized value type may not be legal, e.g. it might require
2462 // promotion or expansion. Relegalize the scalar store.
2463 Result = LegalizeOp(Result);
2466 SplitVectorOp(ST->getValue(), Lo, Hi);
2467 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
2468 MVT::getSizeInBits(EVT)/8;
2471 ExpandOp(ST->getValue(), Lo, Hi);
2472 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2474 if (TLI.isBigEndian())
2478 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2479 SVOffset, isVolatile, Alignment);
2481 if (Hi.Val == NULL) {
2482 // Must be int <-> float one-to-one expansion.
2487 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2488 DAG.getIntPtrConstant(IncrementSize));
2489 assert(isTypeLegal(Tmp2.getValueType()) &&
2490 "Pointers must be legal!");
2491 SVOffset += IncrementSize;
2492 Alignment = MinAlign(Alignment, IncrementSize);
2493 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2494 SVOffset, isVolatile, Alignment);
2495 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2499 switch (getTypeAction(ST->getValue().getValueType())) {
2501 Tmp3 = LegalizeOp(ST->getValue());
2504 // We can promote the value, the truncstore will still take care of it.
2505 Tmp3 = PromoteOp(ST->getValue());
2508 // Just store the low part. This may become a non-trunc store, so make
2509 // sure to use getTruncStore, not UpdateNodeOperands below.
2510 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2511 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2512 SVOffset, MVT::i8, isVolatile, Alignment);
2515 MVT::ValueType StVT = ST->getMemoryVT();
2516 unsigned StWidth = MVT::getSizeInBits(StVT);
2518 if (StWidth != MVT::getStoreSizeInBits(StVT)) {
2519 // Promote to a byte-sized store with upper bits zero if not
2520 // storing an integral number of bytes. For example, promote
2521 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2522 MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT));
2523 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2524 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2525 SVOffset, NVT, isVolatile, Alignment);
2526 } else if (StWidth & (StWidth - 1)) {
2527 // If not storing a power-of-2 number of bits, expand as two stores.
2528 assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) &&
2529 "Unsupported truncstore!");
2530 unsigned RoundWidth = 1 << Log2_32(StWidth);
2531 assert(RoundWidth < StWidth);
2532 unsigned ExtraWidth = StWidth - RoundWidth;
2533 assert(ExtraWidth < RoundWidth);
2534 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2535 "Store size not an integral number of bytes!");
2536 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
2537 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
2539 unsigned IncrementSize;
2541 if (TLI.isLittleEndian()) {
2542 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2543 // Store the bottom RoundWidth bits.
2544 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2546 isVolatile, Alignment);
2548 // Store the remaining ExtraWidth bits.
2549 IncrementSize = RoundWidth / 8;
2550 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2551 DAG.getIntPtrConstant(IncrementSize));
2552 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2553 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2554 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2555 SVOffset + IncrementSize, ExtraVT, isVolatile,
2556 MinAlign(Alignment, IncrementSize));
2558 // Big endian - avoid unaligned stores.
2559 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2560 // Store the top RoundWidth bits.
2561 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2562 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2563 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2564 RoundVT, isVolatile, Alignment);
2566 // Store the remaining ExtraWidth bits.
2567 IncrementSize = RoundWidth / 8;
2568 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2569 DAG.getIntPtrConstant(IncrementSize));
2570 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2571 SVOffset + IncrementSize, ExtraVT, isVolatile,
2572 MinAlign(Alignment, IncrementSize));
2575 // The order of the stores doesn't matter.
2576 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2578 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2579 Tmp2 != ST->getBasePtr())
2580 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2583 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2584 default: assert(0 && "This action is not supported yet!");
2585 case TargetLowering::Legal:
2586 // If this is an unaligned store and the target doesn't support it,
2588 if (!TLI.allowsUnalignedMemoryAccesses()) {
2589 unsigned ABIAlignment = TLI.getTargetData()->
2590 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2591 if (ST->getAlignment() < ABIAlignment)
2592 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2596 case TargetLowering::Custom:
2597 Result = TLI.LowerOperation(Result, DAG);
2600 // TRUNCSTORE:i16 i32 -> STORE i16
2601 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2602 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2603 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2604 isVolatile, Alignment);
2612 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2613 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2615 case ISD::STACKSAVE:
2616 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2617 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2618 Tmp1 = Result.getValue(0);
2619 Tmp2 = Result.getValue(1);
2621 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2622 default: assert(0 && "This action is not supported yet!");
2623 case TargetLowering::Legal: break;
2624 case TargetLowering::Custom:
2625 Tmp3 = TLI.LowerOperation(Result, DAG);
2627 Tmp1 = LegalizeOp(Tmp3);
2628 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2631 case TargetLowering::Expand:
2632 // Expand to CopyFromReg if the target set
2633 // StackPointerRegisterToSaveRestore.
2634 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2635 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2636 Node->getValueType(0));
2637 Tmp2 = Tmp1.getValue(1);
2639 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2640 Tmp2 = Node->getOperand(0);
2645 // Since stacksave produce two values, make sure to remember that we
2646 // legalized both of them.
2647 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2648 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2649 return Op.ResNo ? Tmp2 : Tmp1;
2651 case ISD::STACKRESTORE:
2652 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2653 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2654 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2656 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2657 default: assert(0 && "This action is not supported yet!");
2658 case TargetLowering::Legal: break;
2659 case TargetLowering::Custom:
2660 Tmp1 = TLI.LowerOperation(Result, DAG);
2661 if (Tmp1.Val) Result = Tmp1;
2663 case TargetLowering::Expand:
2664 // Expand to CopyToReg if the target set
2665 // StackPointerRegisterToSaveRestore.
2666 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2667 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2675 case ISD::READCYCLECOUNTER:
2676 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2677 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2678 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2679 Node->getValueType(0))) {
2680 default: assert(0 && "This action is not supported yet!");
2681 case TargetLowering::Legal:
2682 Tmp1 = Result.getValue(0);
2683 Tmp2 = Result.getValue(1);
2685 case TargetLowering::Custom:
2686 Result = TLI.LowerOperation(Result, DAG);
2687 Tmp1 = LegalizeOp(Result.getValue(0));
2688 Tmp2 = LegalizeOp(Result.getValue(1));
2692 // Since rdcc produce two values, make sure to remember that we legalized
2694 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2695 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2699 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2700 case Expand: assert(0 && "It's impossible to expand bools");
2702 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2705 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2706 // Make sure the condition is either zero or one.
2707 unsigned BitWidth = Tmp1.getValueSizeInBits();
2708 if (!DAG.MaskedValueIsZero(Tmp1,
2709 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2710 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2714 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2715 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2717 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2719 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2720 default: assert(0 && "This action is not supported yet!");
2721 case TargetLowering::Legal: break;
2722 case TargetLowering::Custom: {
2723 Tmp1 = TLI.LowerOperation(Result, DAG);
2724 if (Tmp1.Val) Result = Tmp1;
2727 case TargetLowering::Expand:
2728 if (Tmp1.getOpcode() == ISD::SETCC) {
2729 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2731 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2733 Result = DAG.getSelectCC(Tmp1,
2734 DAG.getConstant(0, Tmp1.getValueType()),
2735 Tmp2, Tmp3, ISD::SETNE);
2738 case TargetLowering::Promote: {
2739 MVT::ValueType NVT =
2740 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2741 unsigned ExtOp, TruncOp;
2742 if (MVT::isVector(Tmp2.getValueType())) {
2743 ExtOp = ISD::BIT_CONVERT;
2744 TruncOp = ISD::BIT_CONVERT;
2745 } else if (MVT::isInteger(Tmp2.getValueType())) {
2746 ExtOp = ISD::ANY_EXTEND;
2747 TruncOp = ISD::TRUNCATE;
2749 ExtOp = ISD::FP_EXTEND;
2750 TruncOp = ISD::FP_ROUND;
2752 // Promote each of the values to the new type.
2753 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2754 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2755 // Perform the larger operation, then round down.
2756 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2757 if (TruncOp != ISD::FP_ROUND)
2758 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2760 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2761 DAG.getIntPtrConstant(0));
2766 case ISD::SELECT_CC: {
2767 Tmp1 = Node->getOperand(0); // LHS
2768 Tmp2 = Node->getOperand(1); // RHS
2769 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2770 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2771 SDOperand CC = Node->getOperand(4);
2773 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2775 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2776 // the LHS is a legal SETCC itself. In this case, we need to compare
2777 // the result against zero to select between true and false values.
2778 if (Tmp2.Val == 0) {
2779 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2780 CC = DAG.getCondCode(ISD::SETNE);
2782 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2784 // Everything is legal, see if we should expand this op or something.
2785 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2786 default: assert(0 && "This action is not supported yet!");
2787 case TargetLowering::Legal: break;
2788 case TargetLowering::Custom:
2789 Tmp1 = TLI.LowerOperation(Result, DAG);
2790 if (Tmp1.Val) Result = Tmp1;
2796 Tmp1 = Node->getOperand(0);
2797 Tmp2 = Node->getOperand(1);
2798 Tmp3 = Node->getOperand(2);
2799 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2801 // If we had to Expand the SetCC operands into a SELECT node, then it may
2802 // not always be possible to return a true LHS & RHS. In this case, just
2803 // return the value we legalized, returned in the LHS
2804 if (Tmp2.Val == 0) {
2809 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2810 default: assert(0 && "Cannot handle this action for SETCC yet!");
2811 case TargetLowering::Custom:
2814 case TargetLowering::Legal:
2815 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2817 Tmp4 = TLI.LowerOperation(Result, DAG);
2818 if (Tmp4.Val) Result = Tmp4;
2821 case TargetLowering::Promote: {
2822 // First step, figure out the appropriate operation to use.
2823 // Allow SETCC to not be supported for all legal data types
2824 // Mostly this targets FP
2825 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2826 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2828 // Scan for the appropriate larger type to use.
2830 NewInTy = (MVT::ValueType)(NewInTy+1);
2832 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2833 "Fell off of the edge of the integer world");
2834 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2835 "Fell off of the edge of the floating point world");
2837 // If the target supports SETCC of this type, use it.
2838 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2841 if (MVT::isInteger(NewInTy))
2842 assert(0 && "Cannot promote Legal Integer SETCC yet");
2844 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2845 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2847 Tmp1 = LegalizeOp(Tmp1);
2848 Tmp2 = LegalizeOp(Tmp2);
2849 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2850 Result = LegalizeOp(Result);
2853 case TargetLowering::Expand:
2854 // Expand a setcc node into a select_cc of the same condition, lhs, and
2855 // rhs that selects between const 1 (true) and const 0 (false).
2856 MVT::ValueType VT = Node->getValueType(0);
2857 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2858 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2864 case ISD::SHL_PARTS:
2865 case ISD::SRA_PARTS:
2866 case ISD::SRL_PARTS: {
2867 SmallVector<SDOperand, 8> Ops;
2868 bool Changed = false;
2869 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2870 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2871 Changed |= Ops.back() != Node->getOperand(i);
2874 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2876 switch (TLI.getOperationAction(Node->getOpcode(),
2877 Node->getValueType(0))) {
2878 default: assert(0 && "This action is not supported yet!");
2879 case TargetLowering::Legal: break;
2880 case TargetLowering::Custom:
2881 Tmp1 = TLI.LowerOperation(Result, DAG);
2883 SDOperand Tmp2, RetVal(0, 0);
2884 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2885 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2886 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2890 assert(RetVal.Val && "Illegal result number");
2896 // Since these produce multiple values, make sure to remember that we
2897 // legalized all of them.
2898 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2899 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2900 return Result.getValue(Op.ResNo);
2922 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2923 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2924 case Expand: assert(0 && "Not possible");
2926 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2929 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2933 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2935 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2936 default: assert(0 && "BinOp legalize operation not supported");
2937 case TargetLowering::Legal: break;
2938 case TargetLowering::Custom:
2939 Tmp1 = TLI.LowerOperation(Result, DAG);
2940 if (Tmp1.Val) Result = Tmp1;
2942 case TargetLowering::Expand: {
2943 MVT::ValueType VT = Op.getValueType();
2945 // See if multiply or divide can be lowered using two-result operations.
2946 SDVTList VTs = DAG.getVTList(VT, VT);
2947 if (Node->getOpcode() == ISD::MUL) {
2948 // We just need the low half of the multiply; try both the signed
2949 // and unsigned forms. If the target supports both SMUL_LOHI and
2950 // UMUL_LOHI, form a preference by checking which forms of plain
2951 // MULH it supports.
2952 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2953 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2954 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2955 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2956 unsigned OpToUse = 0;
2957 if (HasSMUL_LOHI && !HasMULHS) {
2958 OpToUse = ISD::SMUL_LOHI;
2959 } else if (HasUMUL_LOHI && !HasMULHU) {
2960 OpToUse = ISD::UMUL_LOHI;
2961 } else if (HasSMUL_LOHI) {
2962 OpToUse = ISD::SMUL_LOHI;
2963 } else if (HasUMUL_LOHI) {
2964 OpToUse = ISD::UMUL_LOHI;
2967 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
2971 if (Node->getOpcode() == ISD::MULHS &&
2972 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
2973 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2976 if (Node->getOpcode() == ISD::MULHU &&
2977 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
2978 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2981 if (Node->getOpcode() == ISD::SDIV &&
2982 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
2983 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2986 if (Node->getOpcode() == ISD::UDIV &&
2987 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
2988 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2992 // Check to see if we have a libcall for this operator.
2993 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2994 bool isSigned = false;
2995 switch (Node->getOpcode()) {
2998 if (VT == MVT::i32) {
2999 LC = Node->getOpcode() == ISD::UDIV
3000 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3001 isSigned = Node->getOpcode() == ISD::SDIV;
3005 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3006 RTLIB::POW_PPCF128);
3010 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3012 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3016 assert(MVT::isVector(Node->getValueType(0)) &&
3017 "Cannot expand this binary operator!");
3018 // Expand the operation into a bunch of nasty scalar code.
3019 Result = LegalizeOp(UnrollVectorOp(Op));
3022 case TargetLowering::Promote: {
3023 switch (Node->getOpcode()) {
3024 default: assert(0 && "Do not know how to promote this BinOp!");
3028 MVT::ValueType OVT = Node->getValueType(0);
3029 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3030 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
3031 // Bit convert each of the values to the new type.
3032 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3033 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3034 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3035 // Bit convert the result back the original type.
3036 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3044 case ISD::SMUL_LOHI:
3045 case ISD::UMUL_LOHI:
3048 // These nodes will only be produced by target-specific lowering, so
3049 // they shouldn't be here if they aren't legal.
3050 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3051 "This must be legal!");
3053 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3054 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3055 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3058 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3059 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3060 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3061 case Expand: assert(0 && "Not possible");
3063 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3066 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3070 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3072 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3073 default: assert(0 && "Operation not supported");
3074 case TargetLowering::Custom:
3075 Tmp1 = TLI.LowerOperation(Result, DAG);
3076 if (Tmp1.Val) Result = Tmp1;
3078 case TargetLowering::Legal: break;
3079 case TargetLowering::Expand: {
3080 // If this target supports fabs/fneg natively and select is cheap,
3081 // do this efficiently.
3082 if (!TLI.isSelectExpensive() &&
3083 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3084 TargetLowering::Legal &&
3085 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3086 TargetLowering::Legal) {
3087 // Get the sign bit of the RHS.
3088 MVT::ValueType IVT =
3089 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3090 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3091 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3092 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3093 // Get the absolute value of the result.
3094 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3095 // Select between the nabs and abs value based on the sign bit of
3097 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3098 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3101 Result = LegalizeOp(Result);
3105 // Otherwise, do bitwise ops!
3106 MVT::ValueType NVT =
3107 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3108 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3109 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3110 Result = LegalizeOp(Result);
3118 Tmp1 = LegalizeOp(Node->getOperand(0));
3119 Tmp2 = LegalizeOp(Node->getOperand(1));
3120 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3121 // Since this produces two values, make sure to remember that we legalized
3123 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3124 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3129 Tmp1 = LegalizeOp(Node->getOperand(0));
3130 Tmp2 = LegalizeOp(Node->getOperand(1));
3131 Tmp3 = LegalizeOp(Node->getOperand(2));
3132 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3133 // Since this produces two values, make sure to remember that we legalized
3135 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3136 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3139 case ISD::BUILD_PAIR: {
3140 MVT::ValueType PairTy = Node->getValueType(0);
3141 // TODO: handle the case where the Lo and Hi operands are not of legal type
3142 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3143 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3144 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3145 case TargetLowering::Promote:
3146 case TargetLowering::Custom:
3147 assert(0 && "Cannot promote/custom this yet!");
3148 case TargetLowering::Legal:
3149 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3150 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3152 case TargetLowering::Expand:
3153 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3154 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3155 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3156 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
3157 TLI.getShiftAmountTy()));
3158 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3167 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3168 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3170 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3171 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3172 case TargetLowering::Custom:
3175 case TargetLowering::Legal:
3176 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3178 Tmp1 = TLI.LowerOperation(Result, DAG);
3179 if (Tmp1.Val) Result = Tmp1;
3182 case TargetLowering::Expand: {
3183 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3184 bool isSigned = DivOpc == ISD::SDIV;
3185 MVT::ValueType VT = Node->getValueType(0);
3187 // See if remainder can be lowered using two-result operations.
3188 SDVTList VTs = DAG.getVTList(VT, VT);
3189 if (Node->getOpcode() == ISD::SREM &&
3190 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3191 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3194 if (Node->getOpcode() == ISD::UREM &&
3195 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3196 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3200 if (MVT::isInteger(VT)) {
3201 if (TLI.getOperationAction(DivOpc, VT) ==
3202 TargetLowering::Legal) {
3204 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3205 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3206 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3207 } else if (MVT::isVector(VT)) {
3208 Result = LegalizeOp(UnrollVectorOp(Op));
3210 assert(VT == MVT::i32 &&
3211 "Cannot expand this binary operator!");
3212 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3213 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3215 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3218 assert(MVT::isFloatingPoint(VT) &&
3219 "remainder op must have integer or floating-point type");
3220 if (MVT::isVector(VT)) {
3221 Result = LegalizeOp(UnrollVectorOp(Op));
3223 // Floating point mod -> fmod libcall.
3224 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3225 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3227 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3235 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3236 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3238 MVT::ValueType VT = Node->getValueType(0);
3239 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3240 default: assert(0 && "This action is not supported yet!");
3241 case TargetLowering::Custom:
3244 case TargetLowering::Legal:
3245 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3246 Result = Result.getValue(0);
3247 Tmp1 = Result.getValue(1);
3250 Tmp2 = TLI.LowerOperation(Result, DAG);
3252 Result = LegalizeOp(Tmp2);
3253 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3257 case TargetLowering::Expand: {
3258 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3259 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3260 // Increment the pointer, VAList, to the next vaarg
3261 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3262 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3263 TLI.getPointerTy()));
3264 // Store the incremented VAList to the legalized pointer
3265 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3266 // Load the actual argument out of the pointer VAList
3267 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3268 Tmp1 = LegalizeOp(Result.getValue(1));
3269 Result = LegalizeOp(Result);
3273 // Since VAARG produces two values, make sure to remember that we
3274 // legalized both of them.
3275 AddLegalizedOperand(SDOperand(Node, 0), Result);
3276 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3277 return Op.ResNo ? Tmp1 : Result;
3281 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3282 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3283 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3285 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3286 default: assert(0 && "This action is not supported yet!");
3287 case TargetLowering::Custom:
3290 case TargetLowering::Legal:
3291 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3292 Node->getOperand(3), Node->getOperand(4));
3294 Tmp1 = TLI.LowerOperation(Result, DAG);
3295 if (Tmp1.Val) Result = Tmp1;
3298 case TargetLowering::Expand:
3299 // This defaults to loading a pointer from the input and storing it to the
3300 // output, returning the chain.
3301 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3302 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3303 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3304 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3310 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3311 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3313 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3314 default: assert(0 && "This action is not supported yet!");
3315 case TargetLowering::Custom:
3318 case TargetLowering::Legal:
3319 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3321 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3322 if (Tmp1.Val) Result = Tmp1;
3325 case TargetLowering::Expand:
3326 Result = Tmp1; // Default to a no-op, return the chain
3332 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3333 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3335 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3337 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3338 default: assert(0 && "This action is not supported yet!");
3339 case TargetLowering::Legal: break;
3340 case TargetLowering::Custom:
3341 Tmp1 = TLI.LowerOperation(Result, DAG);
3342 if (Tmp1.Val) Result = Tmp1;
3349 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3350 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3351 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3352 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3354 assert(0 && "ROTL/ROTR legalize operation not supported");
3356 case TargetLowering::Legal:
3358 case TargetLowering::Custom:
3359 Tmp1 = TLI.LowerOperation(Result, DAG);
3360 if (Tmp1.Val) Result = Tmp1;
3362 case TargetLowering::Promote:
3363 assert(0 && "Do not know how to promote ROTL/ROTR");
3365 case TargetLowering::Expand:
3366 assert(0 && "Do not know how to expand ROTL/ROTR");
3372 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3373 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3374 case TargetLowering::Custom:
3375 assert(0 && "Cannot custom legalize this yet!");
3376 case TargetLowering::Legal:
3377 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3379 case TargetLowering::Promote: {
3380 MVT::ValueType OVT = Tmp1.getValueType();
3381 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3382 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
3384 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3385 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3386 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3387 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3390 case TargetLowering::Expand:
3391 Result = ExpandBSWAP(Tmp1);
3399 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3400 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3401 case TargetLowering::Custom:
3402 case TargetLowering::Legal:
3403 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3404 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3405 TargetLowering::Custom) {
3406 Tmp1 = TLI.LowerOperation(Result, DAG);
3412 case TargetLowering::Promote: {
3413 MVT::ValueType OVT = Tmp1.getValueType();
3414 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3416 // Zero extend the argument.
3417 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3418 // Perform the larger operation, then subtract if needed.
3419 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3420 switch (Node->getOpcode()) {
3425 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3426 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3427 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3429 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3430 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
3433 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3434 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3435 DAG.getConstant(MVT::getSizeInBits(NVT) -
3436 MVT::getSizeInBits(OVT), NVT));
3441 case TargetLowering::Expand:
3442 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3453 Tmp1 = LegalizeOp(Node->getOperand(0));
3454 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3455 case TargetLowering::Promote:
3456 case TargetLowering::Custom:
3459 case TargetLowering::Legal:
3460 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3462 Tmp1 = TLI.LowerOperation(Result, DAG);
3463 if (Tmp1.Val) Result = Tmp1;
3466 case TargetLowering::Expand:
3467 switch (Node->getOpcode()) {
3468 default: assert(0 && "Unreachable!");
3470 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3471 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3472 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3475 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3476 MVT::ValueType VT = Node->getValueType(0);
3477 Tmp2 = DAG.getConstantFP(0.0, VT);
3478 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3480 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3481 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3487 MVT::ValueType VT = Node->getValueType(0);
3489 // Expand unsupported unary vector operators by unrolling them.
3490 if (MVT::isVector(VT)) {
3491 Result = LegalizeOp(UnrollVectorOp(Op));
3495 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3496 switch(Node->getOpcode()) {
3498 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3499 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3502 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3503 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3506 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3507 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3509 default: assert(0 && "Unreachable!");
3512 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3520 MVT::ValueType VT = Node->getValueType(0);
3522 // Expand unsupported unary vector operators by unrolling them.
3523 if (MVT::isVector(VT)) {
3524 Result = LegalizeOp(UnrollVectorOp(Op));
3528 // We always lower FPOWI into a libcall. No target support for it yet.
3529 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3530 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3532 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3535 case ISD::BIT_CONVERT:
3536 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3537 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3538 Node->getValueType(0));
3539 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3540 // The input has to be a vector type, we have to either scalarize it, pack
3541 // it, or convert it based on whether the input vector type is legal.
3542 SDNode *InVal = Node->getOperand(0).Val;
3543 int InIx = Node->getOperand(0).ResNo;
3544 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
3545 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
3547 // Figure out if there is a simple type corresponding to this Vector
3548 // type. If so, convert to the vector type.
3549 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3550 if (TLI.isTypeLegal(TVT)) {
3551 // Turn this into a bit convert of the vector input.
3552 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3553 LegalizeOp(Node->getOperand(0)));
3555 } else if (NumElems == 1) {
3556 // Turn this into a bit convert of the scalar input.
3557 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3558 ScalarizeVectorOp(Node->getOperand(0)));
3561 // FIXME: UNIMP! Store then reload
3562 assert(0 && "Cast from unsupported vector type not implemented yet!");
3565 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3566 Node->getOperand(0).getValueType())) {
3567 default: assert(0 && "Unknown operation action!");
3568 case TargetLowering::Expand:
3569 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3570 Node->getValueType(0));
3572 case TargetLowering::Legal:
3573 Tmp1 = LegalizeOp(Node->getOperand(0));
3574 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3580 // Conversion operators. The source and destination have different types.
3581 case ISD::SINT_TO_FP:
3582 case ISD::UINT_TO_FP: {
3583 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3584 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3586 switch (TLI.getOperationAction(Node->getOpcode(),
3587 Node->getOperand(0).getValueType())) {
3588 default: assert(0 && "Unknown operation action!");
3589 case TargetLowering::Custom:
3592 case TargetLowering::Legal:
3593 Tmp1 = LegalizeOp(Node->getOperand(0));
3594 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3596 Tmp1 = TLI.LowerOperation(Result, DAG);
3597 if (Tmp1.Val) Result = Tmp1;
3600 case TargetLowering::Expand:
3601 Result = ExpandLegalINT_TO_FP(isSigned,
3602 LegalizeOp(Node->getOperand(0)),
3603 Node->getValueType(0));
3605 case TargetLowering::Promote:
3606 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3607 Node->getValueType(0),
3613 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3614 Node->getValueType(0), Node->getOperand(0));
3617 Tmp1 = PromoteOp(Node->getOperand(0));
3619 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3620 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3622 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3623 Node->getOperand(0).getValueType());
3625 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3626 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3632 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3634 Tmp1 = LegalizeOp(Node->getOperand(0));
3635 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3638 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3640 // Since the result is legal, we should just be able to truncate the low
3641 // part of the source.
3642 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3645 Result = PromoteOp(Node->getOperand(0));
3646 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3651 case ISD::FP_TO_SINT:
3652 case ISD::FP_TO_UINT:
3653 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3655 Tmp1 = LegalizeOp(Node->getOperand(0));
3657 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3658 default: assert(0 && "Unknown operation action!");
3659 case TargetLowering::Custom:
3662 case TargetLowering::Legal:
3663 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3665 Tmp1 = TLI.LowerOperation(Result, DAG);
3666 if (Tmp1.Val) Result = Tmp1;
3669 case TargetLowering::Promote:
3670 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3671 Node->getOpcode() == ISD::FP_TO_SINT);
3673 case TargetLowering::Expand:
3674 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3675 SDOperand True, False;
3676 MVT::ValueType VT = Node->getOperand(0).getValueType();
3677 MVT::ValueType NVT = Node->getValueType(0);
3678 const uint64_t zero[] = {0, 0};
3679 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3680 APInt x = APInt::getSignBit(MVT::getSizeInBits(NVT));
3681 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3682 Tmp2 = DAG.getConstantFP(apf, VT);
3683 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
3684 Node->getOperand(0), Tmp2, ISD::SETLT);
3685 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3686 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3687 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3689 False = DAG.getNode(ISD::XOR, NVT, False,
3690 DAG.getConstant(x, NVT));
3691 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3694 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3700 MVT::ValueType VT = Op.getValueType();
3701 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3702 // Convert ppcf128 to i32
3703 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3704 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3705 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3706 Node->getOperand(0), DAG.getValueType(MVT::f64));
3707 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3708 DAG.getIntPtrConstant(1));
3709 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3711 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3712 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3713 Tmp2 = DAG.getConstantFP(apf, OVT);
3714 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3715 // FIXME: generated code sucks.
3716 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3717 DAG.getNode(ISD::ADD, MVT::i32,
3718 DAG.getNode(ISD::FP_TO_SINT, VT,
3719 DAG.getNode(ISD::FSUB, OVT,
3720 Node->getOperand(0), Tmp2)),
3721 DAG.getConstant(0x80000000, MVT::i32)),
3722 DAG.getNode(ISD::FP_TO_SINT, VT,
3723 Node->getOperand(0)),
3724 DAG.getCondCode(ISD::SETGE));
3728 // Convert f32 / f64 to i32 / i64 / i128.
3729 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3730 switch (Node->getOpcode()) {
3731 case ISD::FP_TO_SINT: {
3732 if (VT == MVT::i32) {
3733 if (OVT == MVT::f32)
3734 LC = RTLIB::FPTOSINT_F32_I32;
3735 else if (OVT == MVT::f64)
3736 LC = RTLIB::FPTOSINT_F64_I32;
3738 assert(0 && "Unexpected i32-to-fp conversion!");
3739 } else if (VT == MVT::i64) {
3740 if (OVT == MVT::f32)
3741 LC = RTLIB::FPTOSINT_F32_I64;
3742 else if (OVT == MVT::f64)
3743 LC = RTLIB::FPTOSINT_F64_I64;
3744 else if (OVT == MVT::f80)
3745 LC = RTLIB::FPTOSINT_F80_I64;
3746 else if (OVT == MVT::ppcf128)
3747 LC = RTLIB::FPTOSINT_PPCF128_I64;
3749 assert(0 && "Unexpected i64-to-fp conversion!");
3750 } else if (VT == MVT::i128) {
3751 if (OVT == MVT::f32)
3752 LC = RTLIB::FPTOSINT_F32_I128;
3753 else if (OVT == MVT::f64)
3754 LC = RTLIB::FPTOSINT_F64_I128;
3755 else if (OVT == MVT::f80)
3756 LC = RTLIB::FPTOSINT_F80_I128;
3757 else if (OVT == MVT::ppcf128)
3758 LC = RTLIB::FPTOSINT_PPCF128_I128;
3760 assert(0 && "Unexpected i128-to-fp conversion!");
3762 assert(0 && "Unexpectd int-to-fp conversion!");
3766 case ISD::FP_TO_UINT: {
3767 if (VT == MVT::i32) {
3768 if (OVT == MVT::f32)
3769 LC = RTLIB::FPTOUINT_F32_I32;
3770 else if (OVT == MVT::f64)
3771 LC = RTLIB::FPTOUINT_F64_I32;
3772 else if (OVT == MVT::f80)
3773 LC = RTLIB::FPTOUINT_F80_I32;
3775 assert(0 && "Unexpected i32-to-fp conversion!");
3776 } else if (VT == MVT::i64) {
3777 if (OVT == MVT::f32)
3778 LC = RTLIB::FPTOUINT_F32_I64;
3779 else if (OVT == MVT::f64)
3780 LC = RTLIB::FPTOUINT_F64_I64;
3781 else if (OVT == MVT::f80)
3782 LC = RTLIB::FPTOUINT_F80_I64;
3783 else if (OVT == MVT::ppcf128)
3784 LC = RTLIB::FPTOUINT_PPCF128_I64;
3786 assert(0 && "Unexpected i64-to-fp conversion!");
3787 } else if (VT == MVT::i128) {
3788 if (OVT == MVT::f32)
3789 LC = RTLIB::FPTOUINT_F32_I128;
3790 else if (OVT == MVT::f64)
3791 LC = RTLIB::FPTOUINT_F64_I128;
3792 else if (OVT == MVT::f80)
3793 LC = RTLIB::FPTOUINT_F80_I128;
3794 else if (OVT == MVT::ppcf128)
3795 LC = RTLIB::FPTOUINT_PPCF128_I128;
3797 assert(0 && "Unexpected i128-to-fp conversion!");
3799 assert(0 && "Unexpectd int-to-fp conversion!");
3803 default: assert(0 && "Unreachable!");
3806 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3810 Tmp1 = PromoteOp(Node->getOperand(0));
3811 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3812 Result = LegalizeOp(Result);
3817 case ISD::FP_EXTEND: {
3818 MVT::ValueType DstVT = Op.getValueType();
3819 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3820 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3821 // The only other way we can lower this is to turn it into a STORE,
3822 // LOAD pair, targetting a temporary location (a stack slot).
3823 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3826 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3827 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3829 Tmp1 = LegalizeOp(Node->getOperand(0));
3830 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3833 Tmp1 = PromoteOp(Node->getOperand(0));
3834 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3839 case ISD::FP_ROUND: {
3840 MVT::ValueType DstVT = Op.getValueType();
3841 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3842 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3843 if (SrcVT == MVT::ppcf128) {
3845 ExpandOp(Node->getOperand(0), Lo, Result);
3846 // Round it the rest of the way (e.g. to f32) if needed.
3847 if (DstVT!=MVT::f64)
3848 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3851 // The only other way we can lower this is to turn it into a STORE,
3852 // LOAD pair, targetting a temporary location (a stack slot).
3853 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3856 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3857 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3859 Tmp1 = LegalizeOp(Node->getOperand(0));
3860 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3863 Tmp1 = PromoteOp(Node->getOperand(0));
3864 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3865 Node->getOperand(1));
3870 case ISD::ANY_EXTEND:
3871 case ISD::ZERO_EXTEND:
3872 case ISD::SIGN_EXTEND:
3873 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3874 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3876 Tmp1 = LegalizeOp(Node->getOperand(0));
3877 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3878 TargetLowering::Custom) {
3879 Tmp2 = TLI.LowerOperation(Result, DAG);
3884 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3887 switch (Node->getOpcode()) {
3888 case ISD::ANY_EXTEND:
3889 Tmp1 = PromoteOp(Node->getOperand(0));
3890 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3892 case ISD::ZERO_EXTEND:
3893 Result = PromoteOp(Node->getOperand(0));
3894 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3895 Result = DAG.getZeroExtendInReg(Result,
3896 Node->getOperand(0).getValueType());
3898 case ISD::SIGN_EXTEND:
3899 Result = PromoteOp(Node->getOperand(0));
3900 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3901 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3903 DAG.getValueType(Node->getOperand(0).getValueType()));
3908 case ISD::FP_ROUND_INREG:
3909 case ISD::SIGN_EXTEND_INREG: {
3910 Tmp1 = LegalizeOp(Node->getOperand(0));
3911 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3913 // If this operation is not supported, convert it to a shl/shr or load/store
3915 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3916 default: assert(0 && "This action not supported for this op yet!");
3917 case TargetLowering::Legal:
3918 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3920 case TargetLowering::Expand:
3921 // If this is an integer extend and shifts are supported, do that.
3922 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3923 // NOTE: we could fall back on load/store here too for targets without
3924 // SAR. However, it is doubtful that any exist.
3925 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3926 MVT::getSizeInBits(ExtraVT);
3927 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3928 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3929 Node->getOperand(0), ShiftCst);
3930 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3932 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3933 // The only way we can lower this is to turn it into a TRUNCSTORE,
3934 // EXTLOAD pair, targetting a temporary location (a stack slot).
3936 // NOTE: there is a choice here between constantly creating new stack
3937 // slots and always reusing the same one. We currently always create
3938 // new ones, as reuse may inhibit scheduling.
3939 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3940 Node->getValueType(0));
3942 assert(0 && "Unknown op");
3948 case ISD::TRAMPOLINE: {
3950 for (unsigned i = 0; i != 6; ++i)
3951 Ops[i] = LegalizeOp(Node->getOperand(i));
3952 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3953 // The only option for this node is to custom lower it.
3954 Result = TLI.LowerOperation(Result, DAG);
3955 assert(Result.Val && "Should always custom lower!");
3957 // Since trampoline produces two values, make sure to remember that we
3958 // legalized both of them.
3959 Tmp1 = LegalizeOp(Result.getValue(1));
3960 Result = LegalizeOp(Result);
3961 AddLegalizedOperand(SDOperand(Node, 0), Result);
3962 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3963 return Op.ResNo ? Tmp1 : Result;
3965 case ISD::FLT_ROUNDS_: {
3966 MVT::ValueType VT = Node->getValueType(0);
3967 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3968 default: assert(0 && "This action not supported for this op yet!");
3969 case TargetLowering::Custom:
3970 Result = TLI.LowerOperation(Op, DAG);
3971 if (Result.Val) break;
3973 case TargetLowering::Legal:
3974 // If this operation is not supported, lower it to constant 1
3975 Result = DAG.getConstant(1, VT);
3980 MVT::ValueType VT = Node->getValueType(0);
3981 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3982 default: assert(0 && "This action not supported for this op yet!");
3983 case TargetLowering::Legal:
3984 Tmp1 = LegalizeOp(Node->getOperand(0));
3985 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3987 case TargetLowering::Custom:
3988 Result = TLI.LowerOperation(Op, DAG);
3989 if (Result.Val) break;
3991 case TargetLowering::Expand:
3992 // If this operation is not supported, lower it to 'abort()' call
3993 Tmp1 = LegalizeOp(Node->getOperand(0));
3994 TargetLowering::ArgListTy Args;
3995 std::pair<SDOperand,SDOperand> CallResult =
3996 TLI.LowerCallTo(Tmp1, Type::VoidTy,
3997 false, false, false, CallingConv::C, false,
3998 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4000 Result = CallResult.second;
4007 assert(Result.getValueType() == Op.getValueType() &&
4008 "Bad legalization!");
4010 // Make sure that the generated code is itself legal.
4012 Result = LegalizeOp(Result);
4014 // Note that LegalizeOp may be reentered even from single-use nodes, which
4015 // means that we always must cache transformed nodes.
4016 AddLegalizedOperand(Op, Result);
4020 /// PromoteOp - Given an operation that produces a value in an invalid type,
4021 /// promote it to compute the value into a larger type. The produced value will
4022 /// have the correct bits for the low portion of the register, but no guarantee
4023 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4024 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
4025 MVT::ValueType VT = Op.getValueType();
4026 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4027 assert(getTypeAction(VT) == Promote &&
4028 "Caller should expand or legalize operands that are not promotable!");
4029 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
4030 "Cannot promote to smaller type!");
4032 SDOperand Tmp1, Tmp2, Tmp3;
4034 SDNode *Node = Op.Val;
4036 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
4037 if (I != PromotedNodes.end()) return I->second;
4039 switch (Node->getOpcode()) {
4040 case ISD::CopyFromReg:
4041 assert(0 && "CopyFromReg must be legal!");
4044 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4046 assert(0 && "Do not know how to promote this operator!");
4049 Result = DAG.getNode(ISD::UNDEF, NVT);
4053 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4055 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4056 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4058 case ISD::ConstantFP:
4059 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4060 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4064 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
4065 && "SetCC type is not legal??");
4066 Result = DAG.getNode(ISD::SETCC,
4067 TLI.getSetCCResultType(Node->getOperand(0)),
4068 Node->getOperand(0), Node->getOperand(1),
4069 Node->getOperand(2));
4073 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4075 Result = LegalizeOp(Node->getOperand(0));
4076 assert(Result.getValueType() >= NVT &&
4077 "This truncation doesn't make sense!");
4078 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
4079 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4082 // The truncation is not required, because we don't guarantee anything
4083 // about high bits anyway.
4084 Result = PromoteOp(Node->getOperand(0));
4087 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4088 // Truncate the low part of the expanded value to the result type
4089 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4092 case ISD::SIGN_EXTEND:
4093 case ISD::ZERO_EXTEND:
4094 case ISD::ANY_EXTEND:
4095 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4096 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4098 // Input is legal? Just do extend all the way to the larger type.
4099 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4102 // Promote the reg if it's smaller.
4103 Result = PromoteOp(Node->getOperand(0));
4104 // The high bits are not guaranteed to be anything. Insert an extend.
4105 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4106 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4107 DAG.getValueType(Node->getOperand(0).getValueType()));
4108 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4109 Result = DAG.getZeroExtendInReg(Result,
4110 Node->getOperand(0).getValueType());
4114 case ISD::BIT_CONVERT:
4115 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4116 Node->getValueType(0));
4117 Result = PromoteOp(Result);
4120 case ISD::FP_EXTEND:
4121 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4123 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4124 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4125 case Promote: assert(0 && "Unreachable with 2 FP types!");
4127 if (Node->getConstantOperandVal(1) == 0) {
4128 // Input is legal? Do an FP_ROUND_INREG.
4129 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4130 DAG.getValueType(VT));
4132 // Just remove the truncate, it isn't affecting the value.
4133 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4134 Node->getOperand(1));
4139 case ISD::SINT_TO_FP:
4140 case ISD::UINT_TO_FP:
4141 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4143 // No extra round required here.
4144 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4148 Result = PromoteOp(Node->getOperand(0));
4149 if (Node->getOpcode() == ISD::SINT_TO_FP)
4150 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4152 DAG.getValueType(Node->getOperand(0).getValueType()));
4154 Result = DAG.getZeroExtendInReg(Result,
4155 Node->getOperand(0).getValueType());
4156 // No extra round required here.
4157 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4160 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4161 Node->getOperand(0));
4162 // Round if we cannot tolerate excess precision.
4163 if (NoExcessFPPrecision)
4164 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4165 DAG.getValueType(VT));
4170 case ISD::SIGN_EXTEND_INREG:
4171 Result = PromoteOp(Node->getOperand(0));
4172 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4173 Node->getOperand(1));
4175 case ISD::FP_TO_SINT:
4176 case ISD::FP_TO_UINT:
4177 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4180 Tmp1 = Node->getOperand(0);
4183 // The input result is prerounded, so we don't have to do anything
4185 Tmp1 = PromoteOp(Node->getOperand(0));
4188 // If we're promoting a UINT to a larger size, check to see if the new node
4189 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4190 // we can use that instead. This allows us to generate better code for
4191 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4192 // legal, such as PowerPC.
4193 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4194 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4195 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4196 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4197 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4199 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4205 Tmp1 = PromoteOp(Node->getOperand(0));
4206 assert(Tmp1.getValueType() == NVT);
4207 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4208 // NOTE: we do not have to do any extra rounding here for
4209 // NoExcessFPPrecision, because we know the input will have the appropriate
4210 // precision, and these operations don't modify precision at all.
4216 Tmp1 = PromoteOp(Node->getOperand(0));
4217 assert(Tmp1.getValueType() == NVT);
4218 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4219 if (NoExcessFPPrecision)
4220 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4221 DAG.getValueType(VT));
4225 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4226 // directly as well, which may be better.
4227 Tmp1 = PromoteOp(Node->getOperand(0));
4228 assert(Tmp1.getValueType() == NVT);
4229 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4230 if (NoExcessFPPrecision)
4231 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4232 DAG.getValueType(VT));
4236 case ISD::ATOMIC_LCS: {
4237 Tmp2 = PromoteOp(Node->getOperand(2));
4238 Tmp3 = PromoteOp(Node->getOperand(3));
4239 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0),
4240 Node->getOperand(1), Tmp2, Tmp3,
4241 cast<AtomicSDNode>(Node)->getVT());
4242 // Remember that we legalized the chain.
4243 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4246 case ISD::ATOMIC_LAS:
4247 case ISD::ATOMIC_SWAP: {
4248 Tmp2 = PromoteOp(Node->getOperand(2));
4249 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0),
4250 Node->getOperand(1), Tmp2,
4251 cast<AtomicSDNode>(Node)->getVT());
4252 // Remember that we legalized the chain.
4253 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4263 // The input may have strange things in the top bits of the registers, but
4264 // these operations don't care. They may have weird bits going out, but
4265 // that too is okay if they are integer operations.
4266 Tmp1 = PromoteOp(Node->getOperand(0));
4267 Tmp2 = PromoteOp(Node->getOperand(1));
4268 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4269 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4274 Tmp1 = PromoteOp(Node->getOperand(0));
4275 Tmp2 = PromoteOp(Node->getOperand(1));
4276 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4277 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4279 // Floating point operations will give excess precision that we may not be
4280 // able to tolerate. If we DO allow excess precision, just leave it,
4281 // otherwise excise it.
4282 // FIXME: Why would we need to round FP ops more than integer ones?
4283 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4284 if (NoExcessFPPrecision)
4285 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4286 DAG.getValueType(VT));
4291 // These operators require that their input be sign extended.
4292 Tmp1 = PromoteOp(Node->getOperand(0));
4293 Tmp2 = PromoteOp(Node->getOperand(1));
4294 if (MVT::isInteger(NVT)) {
4295 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4296 DAG.getValueType(VT));
4297 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4298 DAG.getValueType(VT));
4300 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4302 // Perform FP_ROUND: this is probably overly pessimistic.
4303 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
4304 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4305 DAG.getValueType(VT));
4309 case ISD::FCOPYSIGN:
4310 // These operators require that their input be fp extended.
4311 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4312 case Expand: assert(0 && "not implemented");
4313 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4314 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4316 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4317 case Expand: assert(0 && "not implemented");
4318 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4319 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4321 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4323 // Perform FP_ROUND: this is probably overly pessimistic.
4324 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4325 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4326 DAG.getValueType(VT));
4331 // These operators require that their input be zero extended.
4332 Tmp1 = PromoteOp(Node->getOperand(0));
4333 Tmp2 = PromoteOp(Node->getOperand(1));
4334 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
4335 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4336 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4337 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4341 Tmp1 = PromoteOp(Node->getOperand(0));
4342 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4345 // The input value must be properly sign extended.
4346 Tmp1 = PromoteOp(Node->getOperand(0));
4347 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4348 DAG.getValueType(VT));
4349 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4352 // The input value must be properly zero extended.
4353 Tmp1 = PromoteOp(Node->getOperand(0));
4354 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4355 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4359 Tmp1 = Node->getOperand(0); // Get the chain.
4360 Tmp2 = Node->getOperand(1); // Get the pointer.
4361 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4362 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4363 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
4365 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4366 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4367 // Increment the pointer, VAList, to the next vaarg
4368 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4369 DAG.getConstant(MVT::getSizeInBits(VT)/8,
4370 TLI.getPointerTy()));
4371 // Store the incremented VAList to the legalized pointer
4372 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4373 // Load the actual argument out of the pointer VAList
4374 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4376 // Remember that we legalized the chain.
4377 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4381 LoadSDNode *LD = cast<LoadSDNode>(Node);
4382 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4383 ? ISD::EXTLOAD : LD->getExtensionType();
4384 Result = DAG.getExtLoad(ExtType, NVT,
4385 LD->getChain(), LD->getBasePtr(),
4386 LD->getSrcValue(), LD->getSrcValueOffset(),
4389 LD->getAlignment());
4390 // Remember that we legalized the chain.
4391 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4395 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4396 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4397 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
4399 case ISD::SELECT_CC:
4400 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4401 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4402 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4403 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4406 Tmp1 = Node->getOperand(0);
4407 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4408 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4409 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4410 DAG.getConstant(MVT::getSizeInBits(NVT) -
4411 MVT::getSizeInBits(VT),
4412 TLI.getShiftAmountTy()));
4417 // Zero extend the argument
4418 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4419 // Perform the larger operation, then subtract if needed.
4420 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4421 switch(Node->getOpcode()) {
4426 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4427 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4428 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
4430 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4431 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
4434 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4435 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4436 DAG.getConstant(MVT::getSizeInBits(NVT) -
4437 MVT::getSizeInBits(VT), NVT));
4441 case ISD::EXTRACT_SUBVECTOR:
4442 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4444 case ISD::EXTRACT_VECTOR_ELT:
4445 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4449 assert(Result.Val && "Didn't set a result!");
4451 // Make sure the result is itself legal.
4452 Result = LegalizeOp(Result);
4454 // Remember that we promoted this!
4455 AddPromotedOperand(Op, Result);
4459 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4460 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4461 /// based on the vector type. The return type of this matches the element type
4462 /// of the vector, which may not be legal for the target.
4463 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4464 // We know that operand #0 is the Vec vector. If the index is a constant
4465 // or if the invec is a supported hardware type, we can use it. Otherwise,
4466 // lower to a store then an indexed load.
4467 SDOperand Vec = Op.getOperand(0);
4468 SDOperand Idx = Op.getOperand(1);
4470 MVT::ValueType TVT = Vec.getValueType();
4471 unsigned NumElems = MVT::getVectorNumElements(TVT);
4473 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4474 default: assert(0 && "This action is not supported yet!");
4475 case TargetLowering::Custom: {
4476 Vec = LegalizeOp(Vec);
4477 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4478 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4483 case TargetLowering::Legal:
4484 if (isTypeLegal(TVT)) {
4485 Vec = LegalizeOp(Vec);
4486 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4490 case TargetLowering::Expand:
4494 if (NumElems == 1) {
4495 // This must be an access of the only element. Return it.
4496 Op = ScalarizeVectorOp(Vec);
4497 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4498 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4499 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4501 SplitVectorOp(Vec, Lo, Hi);
4502 if (CIdx->getValue() < NumLoElts) {
4506 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4507 Idx.getValueType());
4510 // It's now an extract from the appropriate high or low part. Recurse.
4511 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4512 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4514 // Store the value to a temporary stack slot, then LOAD the scalar
4515 // element back out.
4516 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4517 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4519 // Add the offset to the index.
4520 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
4521 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4522 DAG.getConstant(EltSize, Idx.getValueType()));
4524 if (MVT::getSizeInBits(Idx.getValueType()) >
4525 MVT::getSizeInBits(TLI.getPointerTy()))
4526 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4528 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4530 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4532 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4537 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4538 /// we assume the operation can be split if it is not already legal.
4539 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4540 // We know that operand #0 is the Vec vector. For now we assume the index
4541 // is a constant and that the extracted result is a supported hardware type.
4542 SDOperand Vec = Op.getOperand(0);
4543 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4545 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
4547 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
4548 // This must be an access of the desired vector length. Return it.
4552 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4554 SplitVectorOp(Vec, Lo, Hi);
4555 if (CIdx->getValue() < NumElems/2) {
4559 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4562 // It's now an extract from the appropriate high or low part. Recurse.
4563 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4564 return ExpandEXTRACT_SUBVECTOR(Op);
4567 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4568 /// with condition CC on the current target. This usually involves legalizing
4569 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4570 /// there may be no choice but to create a new SetCC node to represent the
4571 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4572 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4573 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4576 SDOperand Tmp1, Tmp2, Tmp3, Result;
4578 switch (getTypeAction(LHS.getValueType())) {
4580 Tmp1 = LegalizeOp(LHS); // LHS
4581 Tmp2 = LegalizeOp(RHS); // RHS
4584 Tmp1 = PromoteOp(LHS); // LHS
4585 Tmp2 = PromoteOp(RHS); // RHS
4587 // If this is an FP compare, the operands have already been extended.
4588 if (MVT::isInteger(LHS.getValueType())) {
4589 MVT::ValueType VT = LHS.getValueType();
4590 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4592 // Otherwise, we have to insert explicit sign or zero extends. Note
4593 // that we could insert sign extends for ALL conditions, but zero extend
4594 // is cheaper on many machines (an AND instead of two shifts), so prefer
4596 switch (cast<CondCodeSDNode>(CC)->get()) {
4597 default: assert(0 && "Unknown integer comparison!");
4604 // ALL of these operations will work if we either sign or zero extend
4605 // the operands (including the unsigned comparisons!). Zero extend is
4606 // usually a simpler/cheaper operation, so prefer it.
4607 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4608 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4614 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4615 DAG.getValueType(VT));
4616 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4617 DAG.getValueType(VT));
4623 MVT::ValueType VT = LHS.getValueType();
4624 if (VT == MVT::f32 || VT == MVT::f64) {
4625 // Expand into one or more soft-fp libcall(s).
4626 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4627 switch (cast<CondCodeSDNode>(CC)->get()) {
4630 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4634 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4638 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4642 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4646 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4650 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4653 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4656 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4659 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4660 switch (cast<CondCodeSDNode>(CC)->get()) {
4662 // SETONE = SETOLT | SETOGT
4663 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4666 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4669 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4672 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4675 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4678 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4680 default: assert(0 && "Unsupported FP setcc!");
4685 Tmp1 = ExpandLibCall(LC1,
4686 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4687 false /*sign irrelevant*/, Dummy);
4688 Tmp2 = DAG.getConstant(0, MVT::i32);
4689 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4690 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4691 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
4693 LHS = ExpandLibCall(LC2,
4694 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4695 false /*sign irrelevant*/, Dummy);
4696 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
4697 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4698 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4706 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4707 ExpandOp(LHS, LHSLo, LHSHi);
4708 ExpandOp(RHS, RHSLo, RHSHi);
4709 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4711 if (VT==MVT::ppcf128) {
4712 // FIXME: This generated code sucks. We want to generate
4713 // FCMP crN, hi1, hi2
4715 // FCMP crN, lo1, lo2
4716 // The following can be improved, but not that much.
4717 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
4718 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
4719 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4720 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE);
4721 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
4722 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4723 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4732 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4733 if (RHSCST->isAllOnesValue()) {
4734 // Comparison to -1.
4735 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4740 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4741 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4742 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4743 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4746 // If this is a comparison of the sign bit, just look at the top part.
4748 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4749 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4750 CST->isNullValue()) || // X < 0
4751 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4752 CST->isAllOnesValue())) { // X > -1
4758 // FIXME: This generated code sucks.
4759 ISD::CondCode LowCC;
4761 default: assert(0 && "Unknown integer setcc!");
4763 case ISD::SETULT: LowCC = ISD::SETULT; break;
4765 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4767 case ISD::SETULE: LowCC = ISD::SETULE; break;
4769 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4772 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4773 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4774 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4776 // NOTE: on targets without efficient SELECT of bools, we can always use
4777 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4778 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4779 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
4780 LowCC, false, DagCombineInfo);
4782 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
4783 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4784 CCCode, false, DagCombineInfo);
4786 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
4789 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4790 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4791 if ((Tmp1C && Tmp1C->isNullValue()) ||
4792 (Tmp2C && Tmp2C->isNullValue() &&
4793 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4794 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4795 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
4796 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4797 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4798 // low part is known false, returns high part.
4799 // For LE / GE, if high part is known false, ignore the low part.
4800 // For LT / GT, if high part is known true, ignore the low part.
4804 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4805 ISD::SETEQ, false, DagCombineInfo);
4807 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4809 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4810 Result, Tmp1, Tmp2));
4821 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4822 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4823 /// a load from the stack slot to DestVT, extending it if needed.
4824 /// The resultant code need not be legal.
4825 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4826 MVT::ValueType SlotVT,
4827 MVT::ValueType DestVT) {
4828 // Create the stack frame object.
4829 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
4831 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4832 int SPFI = StackPtrFI->getIndex();
4834 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType());
4835 unsigned SlotSize = MVT::getSizeInBits(SlotVT);
4836 unsigned DestSize = MVT::getSizeInBits(DestVT);
4838 // Emit a store to the stack slot. Use a truncstore if the input value is
4839 // later than DestVT.
4841 if (SrcSize > SlotSize)
4842 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4843 PseudoSourceValue::getFixedStack(),
4846 assert(SrcSize == SlotSize && "Invalid store");
4847 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4848 PseudoSourceValue::getFixedStack(),
4852 // Result is a load from the stack slot.
4853 if (SlotSize == DestSize)
4854 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4856 assert(SlotSize < DestSize && "Unknown extension!");
4857 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT);
4860 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4861 // Create a vector sized/aligned stack slot, store the value to element #0,
4862 // then load the whole vector back out.
4863 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4865 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4866 int SPFI = StackPtrFI->getIndex();
4868 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4869 PseudoSourceValue::getFixedStack(), SPFI);
4870 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4871 PseudoSourceValue::getFixedStack(), SPFI);
4875 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4876 /// support the operation, but do support the resultant vector type.
4877 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4879 // If the only non-undef value is the low element, turn this into a
4880 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4881 unsigned NumElems = Node->getNumOperands();
4882 bool isOnlyLowElement = true;
4883 SDOperand SplatValue = Node->getOperand(0);
4885 // FIXME: it would be far nicer to change this into map<SDOperand,uint64_t>
4886 // and use a bitmask instead of a list of elements.
4887 std::map<SDOperand, std::vector<unsigned> > Values;
4888 Values[SplatValue].push_back(0);
4889 bool isConstant = true;
4890 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4891 SplatValue.getOpcode() != ISD::UNDEF)
4894 for (unsigned i = 1; i < NumElems; ++i) {
4895 SDOperand V = Node->getOperand(i);
4896 Values[V].push_back(i);
4897 if (V.getOpcode() != ISD::UNDEF)
4898 isOnlyLowElement = false;
4899 if (SplatValue != V)
4900 SplatValue = SDOperand(0,0);
4902 // If this isn't a constant element or an undef, we can't use a constant
4904 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4905 V.getOpcode() != ISD::UNDEF)
4909 if (isOnlyLowElement) {
4910 // If the low element is an undef too, then this whole things is an undef.
4911 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4912 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4913 // Otherwise, turn this into a scalar_to_vector node.
4914 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4915 Node->getOperand(0));
4918 // If all elements are constants, create a load from the constant pool.
4920 MVT::ValueType VT = Node->getValueType(0);
4921 std::vector<Constant*> CV;
4922 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4923 if (ConstantFPSDNode *V =
4924 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4925 CV.push_back(ConstantFP::get(V->getValueAPF()));
4926 } else if (ConstantSDNode *V =
4927 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4928 CV.push_back(ConstantInt::get(V->getAPIntValue()));
4930 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4932 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4933 CV.push_back(UndefValue::get(OpNTy));
4936 Constant *CP = ConstantVector::get(CV);
4937 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4938 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4939 PseudoSourceValue::getConstantPool(), 0);
4942 if (SplatValue.Val) { // Splat of one value?
4943 // Build the shuffle constant vector: <0, 0, 0, 0>
4944 MVT::ValueType MaskVT =
4945 MVT::getIntVectorWithNumElements(NumElems);
4946 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4947 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4948 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4949 &ZeroVec[0], ZeroVec.size());
4951 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4952 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4953 // Get the splatted value into the low element of a vector register.
4954 SDOperand LowValVec =
4955 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4957 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4958 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4959 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4964 // If there are only two unique elements, we may be able to turn this into a
4966 if (Values.size() == 2) {
4967 // Get the two values in deterministic order.
4968 SDOperand Val1 = Node->getOperand(1);
4970 std::map<SDOperand, std::vector<unsigned> >::iterator MI = Values.begin();
4971 if (MI->first != Val1)
4974 Val2 = (++MI)->first;
4976 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
4977 // vector shuffle has the undef vector on the RHS.
4978 if (Val1.getOpcode() == ISD::UNDEF)
4979 std::swap(Val1, Val2);
4981 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4982 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
4983 MVT::ValueType MaskEltVT = MVT::getVectorElementType(MaskVT);
4984 std::vector<SDOperand> MaskVec(NumElems);
4986 // Set elements of the shuffle mask for Val1.
4987 std::vector<unsigned> &Val1Elts = Values[Val1];
4988 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
4989 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
4991 // Set elements of the shuffle mask for Val2.
4992 std::vector<unsigned> &Val2Elts = Values[Val2];
4993 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
4994 if (Val2.getOpcode() != ISD::UNDEF)
4995 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
4997 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
4999 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5000 &MaskVec[0], MaskVec.size());
5002 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5003 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5004 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5005 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
5006 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
5007 SDOperand Ops[] = { Val1, Val2, ShuffleMask };
5009 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5010 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5014 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5015 // aligned object on the stack, store each element into it, then load
5016 // the result as a vector.
5017 MVT::ValueType VT = Node->getValueType(0);
5018 // Create the stack frame object.
5019 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
5021 // Emit a store of each element to the stack slot.
5022 SmallVector<SDOperand, 8> Stores;
5023 unsigned TypeByteSize =
5024 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
5025 // Store (in the right endianness) the elements to memory.
5026 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5027 // Ignore undef elements.
5028 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5030 unsigned Offset = TypeByteSize*i;
5032 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5033 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5035 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5039 SDOperand StoreChain;
5040 if (!Stores.empty()) // Not all undef elements?
5041 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5042 &Stores[0], Stores.size());
5044 StoreChain = DAG.getEntryNode();
5046 // Result is a load from the stack slot.
5047 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5050 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5051 SDOperand Op, SDOperand Amt,
5052 SDOperand &Lo, SDOperand &Hi) {
5053 // Expand the subcomponents.
5054 SDOperand LHSL, LHSH;
5055 ExpandOp(Op, LHSL, LHSH);
5057 SDOperand Ops[] = { LHSL, LHSH, Amt };
5058 MVT::ValueType VT = LHSL.getValueType();
5059 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5060 Hi = Lo.getValue(1);
5064 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5065 /// smaller elements. If we can't find a way that is more efficient than a
5066 /// libcall on this target, return false. Otherwise, return true with the
5067 /// low-parts expanded into Lo and Hi.
5068 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
5069 SDOperand &Lo, SDOperand &Hi) {
5070 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5071 "This is not a shift!");
5073 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
5074 SDOperand ShAmt = LegalizeOp(Amt);
5075 MVT::ValueType ShTy = ShAmt.getValueType();
5076 unsigned ShBits = MVT::getSizeInBits(ShTy);
5077 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
5078 unsigned NVTBits = MVT::getSizeInBits(NVT);
5080 // Handle the case when Amt is an immediate.
5081 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
5082 unsigned Cst = CN->getValue();
5083 // Expand the incoming operand to be shifted, so that we have its parts
5085 ExpandOp(Op, InL, InH);
5089 Lo = DAG.getConstant(0, NVT);
5090 Hi = DAG.getConstant(0, NVT);
5091 } else if (Cst > NVTBits) {
5092 Lo = DAG.getConstant(0, NVT);
5093 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5094 } else if (Cst == NVTBits) {
5095 Lo = DAG.getConstant(0, NVT);
5098 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5099 Hi = DAG.getNode(ISD::OR, NVT,
5100 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5101 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5106 Lo = DAG.getConstant(0, NVT);
5107 Hi = DAG.getConstant(0, NVT);
5108 } else if (Cst > NVTBits) {
5109 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5110 Hi = DAG.getConstant(0, NVT);
5111 } else if (Cst == NVTBits) {
5113 Hi = DAG.getConstant(0, NVT);
5115 Lo = DAG.getNode(ISD::OR, NVT,
5116 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5117 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5118 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5123 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5124 DAG.getConstant(NVTBits-1, ShTy));
5125 } else if (Cst > NVTBits) {
5126 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5127 DAG.getConstant(Cst-NVTBits, ShTy));
5128 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5129 DAG.getConstant(NVTBits-1, ShTy));
5130 } else if (Cst == NVTBits) {
5132 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5133 DAG.getConstant(NVTBits-1, ShTy));
5135 Lo = DAG.getNode(ISD::OR, NVT,
5136 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5137 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5138 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5144 // Okay, the shift amount isn't constant. However, if we can tell that it is
5145 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5146 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5147 APInt KnownZero, KnownOne;
5148 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5150 // If we know that if any of the high bits of the shift amount are one, then
5151 // we can do this as a couple of simple shifts.
5152 if (KnownOne.intersects(Mask)) {
5153 // Mask out the high bit, which we know is set.
5154 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5155 DAG.getConstant(~Mask, Amt.getValueType()));
5157 // Expand the incoming operand to be shifted, so that we have its parts
5159 ExpandOp(Op, InL, InH);
5162 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5163 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5166 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5167 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5170 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5171 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5172 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5177 // If we know that the high bits of the shift amount are all zero, then we can
5178 // do this as a couple of simple shifts.
5179 if ((KnownZero & Mask) == Mask) {
5181 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5182 DAG.getConstant(NVTBits, Amt.getValueType()),
5185 // Expand the incoming operand to be shifted, so that we have its parts
5187 ExpandOp(Op, InL, InH);
5190 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5191 Hi = DAG.getNode(ISD::OR, NVT,
5192 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5193 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5196 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5197 Lo = DAG.getNode(ISD::OR, NVT,
5198 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5199 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5202 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5203 Lo = DAG.getNode(ISD::OR, NVT,
5204 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5205 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5214 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5215 // does not fit into a register, return the lo part and set the hi part to the
5216 // by-reg argument. If it does fit into a single register, return the result
5217 // and leave the Hi part unset.
5218 SDOperand SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5219 bool isSigned, SDOperand &Hi) {
5220 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5221 // The input chain to this libcall is the entry node of the function.
5222 // Legalizing the call will automatically add the previous call to the
5224 SDOperand InChain = DAG.getEntryNode();
5226 TargetLowering::ArgListTy Args;
5227 TargetLowering::ArgListEntry Entry;
5228 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5229 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
5230 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
5231 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5232 Entry.isSExt = isSigned;
5233 Entry.isZExt = !isSigned;
5234 Args.push_back(Entry);
5236 SDOperand Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5237 TLI.getPointerTy());
5239 // Splice the libcall in wherever FindInputOutputChains tells us to.
5240 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
5241 std::pair<SDOperand,SDOperand> CallInfo =
5242 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
5243 false, Callee, Args, DAG);
5245 // Legalize the call sequence, starting with the chain. This will advance
5246 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5247 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5248 LegalizeOp(CallInfo.second);
5250 switch (getTypeAction(CallInfo.first.getValueType())) {
5251 default: assert(0 && "Unknown thing");
5253 Result = CallInfo.first;
5256 ExpandOp(CallInfo.first, Result, Hi);
5263 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5265 SDOperand SelectionDAGLegalize::
5266 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
5267 MVT::ValueType SourceVT = Source.getValueType();
5268 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5270 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5271 if (!isSigned && SourceVT != MVT::i32) {
5272 // The integer value loaded will be incorrectly if the 'sign bit' of the
5273 // incoming integer is set. To handle this, we dynamically test to see if
5274 // it is set, and, if so, add a fudge factor.
5278 ExpandOp(Source, Lo, Hi);
5279 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5281 // The comparison for the sign bit will use the entire operand.
5285 // If this is unsigned, and not supported, first perform the conversion to
5286 // signed, then adjust the result if the sign bit is set.
5287 SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source);
5289 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5290 DAG.getConstant(0, Hi.getValueType()),
5292 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5293 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5294 SignSet, Four, Zero);
5295 uint64_t FF = 0x5f800000ULL;
5296 if (TLI.isLittleEndian()) FF <<= 32;
5297 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5299 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5300 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5301 SDOperand FudgeInReg;
5302 if (DestTy == MVT::f32)
5303 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5304 PseudoSourceValue::getConstantPool(), 0);
5305 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
5306 // FIXME: Avoid the extend by construction the right constantpool?
5307 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5309 PseudoSourceValue::getConstantPool(), 0,
5312 assert(0 && "Unexpected conversion");
5314 MVT::ValueType SCVT = SignedConv.getValueType();
5315 if (SCVT != DestTy) {
5316 // Destination type needs to be expanded as well. The FADD now we are
5317 // constructing will be expanded into a libcall.
5318 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
5319 assert(MVT::getSizeInBits(SCVT) * 2 == MVT::getSizeInBits(DestTy));
5320 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5321 SignedConv, SignedConv.getValue(1));
5323 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5325 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5328 // Check to see if the target has a custom way to lower this. If so, use it.
5329 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5330 default: assert(0 && "This action not implemented for this operation!");
5331 case TargetLowering::Legal:
5332 case TargetLowering::Expand:
5333 break; // This case is handled below.
5334 case TargetLowering::Custom: {
5335 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5338 return LegalizeOp(NV);
5339 break; // The target decided this was legal after all
5343 // Expand the source, then glue it back together for the call. We must expand
5344 // the source in case it is shared (this pass of legalize must traverse it).
5346 SDOperand SrcLo, SrcHi;
5347 ExpandOp(Source, SrcLo, SrcHi);
5348 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5352 if (SourceVT == MVT::i32) {
5353 if (DestTy == MVT::f32)
5354 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
5356 assert(DestTy == MVT::f64 && "Unknown fp value type!");
5357 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
5359 } else if (SourceVT == MVT::i64) {
5360 if (DestTy == MVT::f32)
5361 LC = RTLIB::SINTTOFP_I64_F32;
5362 else if (DestTy == MVT::f64)
5363 LC = RTLIB::SINTTOFP_I64_F64;
5364 else if (DestTy == MVT::f80)
5365 LC = RTLIB::SINTTOFP_I64_F80;
5367 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
5368 LC = RTLIB::SINTTOFP_I64_PPCF128;
5370 } else if (SourceVT == MVT::i128) {
5371 if (DestTy == MVT::f32)
5372 LC = RTLIB::SINTTOFP_I128_F32;
5373 else if (DestTy == MVT::f64)
5374 LC = RTLIB::SINTTOFP_I128_F64;
5375 else if (DestTy == MVT::f80)
5376 LC = RTLIB::SINTTOFP_I128_F80;
5378 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
5379 LC = RTLIB::SINTTOFP_I128_PPCF128;
5382 assert(0 && "Unknown int value type");
5385 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
5386 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5388 SDOperand Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart);
5389 if (Result.getValueType() != DestTy && HiPart.Val)
5390 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5394 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5395 /// INT_TO_FP operation of the specified operand when the target requests that
5396 /// we expand it. At this point, we know that the result and operand types are
5397 /// legal for the target.
5398 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5400 MVT::ValueType DestVT) {
5401 if (Op0.getValueType() == MVT::i32) {
5402 // simple 32-bit [signed|unsigned] integer to float/double expansion
5404 // Get the stack frame index of a 8 byte buffer.
5405 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5407 // word offset constant for Hi/Lo address computation
5408 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5409 // set up Hi and Lo (into buffer) address based on endian
5410 SDOperand Hi = StackSlot;
5411 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5412 if (TLI.isLittleEndian())
5415 // if signed map to unsigned space
5416 SDOperand Op0Mapped;
5418 // constant used to invert sign bit (signed to unsigned mapping)
5419 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5420 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5424 // store the lo of the constructed double - based on integer input
5425 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5426 Op0Mapped, Lo, NULL, 0);
5427 // initial hi portion of constructed double
5428 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5429 // store the hi of the constructed double - biased exponent
5430 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5431 // load the constructed double
5432 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5433 // FP constant to bias correct the final result
5434 SDOperand Bias = DAG.getConstantFP(isSigned ?
5435 BitsToDouble(0x4330000080000000ULL)
5436 : BitsToDouble(0x4330000000000000ULL),
5438 // subtract the bias
5439 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5442 // handle final rounding
5443 if (DestVT == MVT::f64) {
5446 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
5447 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5448 DAG.getIntPtrConstant(0));
5449 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
5450 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5454 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5455 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5457 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
5458 DAG.getConstant(0, Op0.getValueType()),
5460 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5461 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5462 SignSet, Four, Zero);
5464 // If the sign bit of the integer is set, the large number will be treated
5465 // as a negative number. To counteract this, the dynamic code adds an
5466 // offset depending on the data type.
5468 switch (Op0.getValueType()) {
5469 default: assert(0 && "Unsupported integer type!");
5470 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5471 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5472 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5473 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5475 if (TLI.isLittleEndian()) FF <<= 32;
5476 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5478 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5479 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5480 SDOperand FudgeInReg;
5481 if (DestVT == MVT::f32)
5482 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5483 PseudoSourceValue::getConstantPool(), 0);
5486 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5487 DAG.getEntryNode(), CPIdx,
5488 PseudoSourceValue::getConstantPool(), 0,
5492 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5495 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5496 /// *INT_TO_FP operation of the specified operand when the target requests that
5497 /// we promote it. At this point, we know that the result and operand types are
5498 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5499 /// operation that takes a larger input.
5500 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5501 MVT::ValueType DestVT,
5503 // First step, figure out the appropriate *INT_TO_FP operation to use.
5504 MVT::ValueType NewInTy = LegalOp.getValueType();
5506 unsigned OpToUse = 0;
5508 // Scan for the appropriate larger type to use.
5510 NewInTy = (MVT::ValueType)(NewInTy+1);
5511 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
5513 // If the target supports SINT_TO_FP of this type, use it.
5514 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5516 case TargetLowering::Legal:
5517 if (!TLI.isTypeLegal(NewInTy))
5518 break; // Can't use this datatype.
5520 case TargetLowering::Custom:
5521 OpToUse = ISD::SINT_TO_FP;
5525 if (isSigned) continue;
5527 // If the target supports UINT_TO_FP of this type, use it.
5528 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5530 case TargetLowering::Legal:
5531 if (!TLI.isTypeLegal(NewInTy))
5532 break; // Can't use this datatype.
5534 case TargetLowering::Custom:
5535 OpToUse = ISD::UINT_TO_FP;
5540 // Otherwise, try a larger type.
5543 // Okay, we found the operation and type to use. Zero extend our input to the
5544 // desired type then run the operation on it.
5545 return DAG.getNode(OpToUse, DestVT,
5546 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5550 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5551 /// FP_TO_*INT operation of the specified operand when the target requests that
5552 /// we promote it. At this point, we know that the result and operand types are
5553 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5554 /// operation that returns a larger result.
5555 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5556 MVT::ValueType DestVT,
5558 // First step, figure out the appropriate FP_TO*INT operation to use.
5559 MVT::ValueType NewOutTy = DestVT;
5561 unsigned OpToUse = 0;
5563 // Scan for the appropriate larger type to use.
5565 NewOutTy = (MVT::ValueType)(NewOutTy+1);
5566 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
5568 // If the target supports FP_TO_SINT returning this type, use it.
5569 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5571 case TargetLowering::Legal:
5572 if (!TLI.isTypeLegal(NewOutTy))
5573 break; // Can't use this datatype.
5575 case TargetLowering::Custom:
5576 OpToUse = ISD::FP_TO_SINT;
5581 // If the target supports FP_TO_UINT of this type, use it.
5582 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5584 case TargetLowering::Legal:
5585 if (!TLI.isTypeLegal(NewOutTy))
5586 break; // Can't use this datatype.
5588 case TargetLowering::Custom:
5589 OpToUse = ISD::FP_TO_UINT;
5594 // Otherwise, try a larger type.
5598 // Okay, we found the operation and type to use.
5599 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5601 // If the operation produces an invalid type, it must be custom lowered. Use
5602 // the target lowering hooks to expand it. Just keep the low part of the
5603 // expanded operation, we know that we're truncating anyway.
5604 if (getTypeAction(NewOutTy) == Expand) {
5605 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
5606 assert(Operation.Val && "Didn't return anything");
5609 // Truncate the result of the extended FP_TO_*INT operation to the desired
5611 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5614 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5616 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5617 MVT::ValueType VT = Op.getValueType();
5618 MVT::ValueType SHVT = TLI.getShiftAmountTy();
5619 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5621 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5623 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5624 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5625 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5627 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5628 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5629 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5630 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5631 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5632 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5633 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5634 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5635 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5637 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5638 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5639 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5640 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5641 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5642 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5643 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5644 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5645 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5646 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5647 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5648 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5649 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5650 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5651 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5652 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5653 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5654 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5655 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5656 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5657 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5661 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5663 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5665 default: assert(0 && "Cannot expand this yet!");
5667 static const uint64_t mask[6] = {
5668 0x5555555555555555ULL, 0x3333333333333333ULL,
5669 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5670 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5672 MVT::ValueType VT = Op.getValueType();
5673 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5674 unsigned len = MVT::getSizeInBits(VT);
5675 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5676 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5677 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5678 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5679 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5680 DAG.getNode(ISD::AND, VT,
5681 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5686 // for now, we do this:
5687 // x = x | (x >> 1);
5688 // x = x | (x >> 2);
5690 // x = x | (x >>16);
5691 // x = x | (x >>32); // for 64-bit input
5692 // return popcount(~x);
5694 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5695 MVT::ValueType VT = Op.getValueType();
5696 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5697 unsigned len = MVT::getSizeInBits(VT);
5698 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5699 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5700 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5702 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5703 return DAG.getNode(ISD::CTPOP, VT, Op);
5706 // for now, we use: { return popcount(~x & (x - 1)); }
5707 // unless the target has ctlz but not ctpop, in which case we use:
5708 // { return 32 - nlz(~x & (x-1)); }
5709 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5710 MVT::ValueType VT = Op.getValueType();
5711 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5712 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5713 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5714 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5715 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5716 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5717 TLI.isOperationLegal(ISD::CTLZ, VT))
5718 return DAG.getNode(ISD::SUB, VT,
5719 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5720 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5721 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5726 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5727 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5728 /// LegalizeNodes map is filled in for any results that are not expanded, the
5729 /// ExpandedNodes map is filled in for any results that are expanded, and the
5730 /// Lo/Hi values are returned.
5731 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5732 MVT::ValueType VT = Op.getValueType();
5733 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5734 SDNode *Node = Op.Val;
5735 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5736 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5737 MVT::isVector(VT)) &&
5738 "Cannot expand to FP value or to larger int value!");
5740 // See if we already expanded it.
5741 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5742 = ExpandedNodes.find(Op);
5743 if (I != ExpandedNodes.end()) {
5744 Lo = I->second.first;
5745 Hi = I->second.second;
5749 switch (Node->getOpcode()) {
5750 case ISD::CopyFromReg:
5751 assert(0 && "CopyFromReg must be legal!");
5752 case ISD::FP_ROUND_INREG:
5753 if (VT == MVT::ppcf128 &&
5754 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5755 TargetLowering::Custom) {
5756 SDOperand SrcLo, SrcHi, Src;
5757 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5758 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5759 SDOperand Result = TLI.LowerOperation(
5760 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5761 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5762 Lo = Result.Val->getOperand(0);
5763 Hi = Result.Val->getOperand(1);
5769 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5771 assert(0 && "Do not know how to expand this operator!");
5773 case ISD::EXTRACT_ELEMENT:
5774 ExpandOp(Node->getOperand(0), Lo, Hi);
5775 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
5776 return ExpandOp(Hi, Lo, Hi);
5777 return ExpandOp(Lo, Lo, Hi);
5778 case ISD::EXTRACT_VECTOR_ELT:
5779 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5780 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5781 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5782 return ExpandOp(Lo, Lo, Hi);
5784 NVT = TLI.getTypeToExpandTo(VT);
5785 Lo = DAG.getNode(ISD::UNDEF, NVT);
5786 Hi = DAG.getNode(ISD::UNDEF, NVT);
5788 case ISD::Constant: {
5789 unsigned NVTBits = MVT::getSizeInBits(NVT);
5790 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
5791 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
5792 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
5795 case ISD::ConstantFP: {
5796 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5797 if (CFP->getValueType(0) == MVT::ppcf128) {
5798 APInt api = CFP->getValueAPF().convertToAPInt();
5799 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5801 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5805 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5806 if (getTypeAction(Lo.getValueType()) == Expand)
5807 ExpandOp(Lo, Lo, Hi);
5810 case ISD::BUILD_PAIR:
5811 // Return the operands.
5812 Lo = Node->getOperand(0);
5813 Hi = Node->getOperand(1);
5816 case ISD::MERGE_VALUES:
5817 if (Node->getNumValues() == 1) {
5818 ExpandOp(Op.getOperand(0), Lo, Hi);
5821 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5822 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5823 Op.getValue(1).getValueType() == MVT::Other &&
5824 "unhandled MERGE_VALUES");
5825 ExpandOp(Op.getOperand(0), Lo, Hi);
5826 // Remember that we legalized the chain.
5827 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5830 case ISD::SIGN_EXTEND_INREG:
5831 ExpandOp(Node->getOperand(0), Lo, Hi);
5832 // sext_inreg the low part if needed.
5833 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5835 // The high part gets the sign extension from the lo-part. This handles
5836 // things like sextinreg V:i64 from i8.
5837 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5838 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5839 TLI.getShiftAmountTy()));
5843 ExpandOp(Node->getOperand(0), Lo, Hi);
5844 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5845 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5851 ExpandOp(Node->getOperand(0), Lo, Hi);
5852 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5853 DAG.getNode(ISD::CTPOP, NVT, Lo),
5854 DAG.getNode(ISD::CTPOP, NVT, Hi));
5855 Hi = DAG.getConstant(0, NVT);
5859 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5860 ExpandOp(Node->getOperand(0), Lo, Hi);
5861 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5862 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5863 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
5865 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5866 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5868 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5869 Hi = DAG.getConstant(0, NVT);
5874 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5875 ExpandOp(Node->getOperand(0), Lo, Hi);
5876 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5877 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5878 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
5880 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5881 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5883 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5884 Hi = DAG.getConstant(0, NVT);
5889 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5890 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5891 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5892 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5894 // Remember that we legalized the chain.
5895 Hi = LegalizeOp(Hi);
5896 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5897 if (TLI.isBigEndian())
5903 LoadSDNode *LD = cast<LoadSDNode>(Node);
5904 SDOperand Ch = LD->getChain(); // Legalize the chain.
5905 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5906 ISD::LoadExtType ExtType = LD->getExtensionType();
5907 int SVOffset = LD->getSrcValueOffset();
5908 unsigned Alignment = LD->getAlignment();
5909 bool isVolatile = LD->isVolatile();
5911 if (ExtType == ISD::NON_EXTLOAD) {
5912 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5913 isVolatile, Alignment);
5914 if (VT == MVT::f32 || VT == MVT::f64) {
5915 // f32->i32 or f64->i64 one to one expansion.
5916 // Remember that we legalized the chain.
5917 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5918 // Recursively expand the new load.
5919 if (getTypeAction(NVT) == Expand)
5920 ExpandOp(Lo, Lo, Hi);
5924 // Increment the pointer to the other half.
5925 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5926 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5927 DAG.getIntPtrConstant(IncrementSize));
5928 SVOffset += IncrementSize;
5929 Alignment = MinAlign(Alignment, IncrementSize);
5930 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5931 isVolatile, Alignment);
5933 // Build a factor node to remember that this load is independent of the
5935 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5938 // Remember that we legalized the chain.
5939 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5940 if (TLI.isBigEndian())
5943 MVT::ValueType EVT = LD->getMemoryVT();
5945 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5946 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5947 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5948 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5949 SVOffset, isVolatile, Alignment);
5950 // Remember that we legalized the chain.
5951 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5952 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5957 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5958 SVOffset, isVolatile, Alignment);
5960 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5961 SVOffset, EVT, isVolatile,
5964 // Remember that we legalized the chain.
5965 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5967 if (ExtType == ISD::SEXTLOAD) {
5968 // The high part is obtained by SRA'ing all but one of the bits of the
5970 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5971 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5972 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5973 } else if (ExtType == ISD::ZEXTLOAD) {
5974 // The high part is just a zero.
5975 Hi = DAG.getConstant(0, NVT);
5976 } else /* if (ExtType == ISD::EXTLOAD) */ {
5977 // The high part is undefined.
5978 Hi = DAG.getNode(ISD::UNDEF, NVT);
5985 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5986 SDOperand LL, LH, RL, RH;
5987 ExpandOp(Node->getOperand(0), LL, LH);
5988 ExpandOp(Node->getOperand(1), RL, RH);
5989 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5990 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5994 SDOperand LL, LH, RL, RH;
5995 ExpandOp(Node->getOperand(1), LL, LH);
5996 ExpandOp(Node->getOperand(2), RL, RH);
5997 if (getTypeAction(NVT) == Expand)
5998 NVT = TLI.getTypeToExpandTo(NVT);
5999 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
6001 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
6004 case ISD::SELECT_CC: {
6005 SDOperand TL, TH, FL, FH;
6006 ExpandOp(Node->getOperand(2), TL, TH);
6007 ExpandOp(Node->getOperand(3), FL, FH);
6008 if (getTypeAction(NVT) == Expand)
6009 NVT = TLI.getTypeToExpandTo(NVT);
6010 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6011 Node->getOperand(1), TL, FL, Node->getOperand(4));
6013 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6014 Node->getOperand(1), TH, FH, Node->getOperand(4));
6017 case ISD::ANY_EXTEND:
6018 // The low part is any extension of the input (which degenerates to a copy).
6019 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6020 // The high part is undefined.
6021 Hi = DAG.getNode(ISD::UNDEF, NVT);
6023 case ISD::SIGN_EXTEND: {
6024 // The low part is just a sign extension of the input (which degenerates to
6026 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6028 // The high part is obtained by SRA'ing all but one of the bits of the lo
6030 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
6031 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6032 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6035 case ISD::ZERO_EXTEND:
6036 // The low part is just a zero extension of the input (which degenerates to
6038 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6040 // The high part is just a zero.
6041 Hi = DAG.getConstant(0, NVT);
6044 case ISD::TRUNCATE: {
6045 // The input value must be larger than this value. Expand *it*.
6047 ExpandOp(Node->getOperand(0), NewLo, Hi);
6049 // The low part is now either the right size, or it is closer. If not the
6050 // right size, make an illegal truncate so we recursively expand it.
6051 if (NewLo.getValueType() != Node->getValueType(0))
6052 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6053 ExpandOp(NewLo, Lo, Hi);
6057 case ISD::BIT_CONVERT: {
6059 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6060 // If the target wants to, allow it to lower this itself.
6061 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6062 case Expand: assert(0 && "cannot expand FP!");
6063 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6064 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6066 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6069 // f32 / f64 must be expanded to i32 / i64.
6070 if (VT == MVT::f32 || VT == MVT::f64) {
6071 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6072 if (getTypeAction(NVT) == Expand)
6073 ExpandOp(Lo, Lo, Hi);
6077 // If source operand will be expanded to the same type as VT, i.e.
6078 // i64 <- f64, i32 <- f32, expand the source operand instead.
6079 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
6080 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6081 ExpandOp(Node->getOperand(0), Lo, Hi);
6085 // Turn this into a load/store pair by default.
6087 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6089 ExpandOp(Tmp, Lo, Hi);
6093 case ISD::READCYCLECOUNTER: {
6094 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6095 TargetLowering::Custom &&
6096 "Must custom expand ReadCycleCounter");
6097 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6098 assert(Tmp.Val && "Node must be custom expanded!");
6099 ExpandOp(Tmp.getValue(0), Lo, Hi);
6100 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6101 LegalizeOp(Tmp.getValue(1)));
6105 case ISD::ATOMIC_LCS: {
6106 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6107 assert(Tmp.Val && "Node must be custom expanded!");
6108 ExpandOp(Tmp.getValue(0), Lo, Hi);
6109 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6110 LegalizeOp(Tmp.getValue(1)));
6116 // These operators cannot be expanded directly, emit them as calls to
6117 // library functions.
6118 case ISD::FP_TO_SINT: {
6119 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6121 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6122 case Expand: assert(0 && "cannot expand FP!");
6123 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6124 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6127 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6129 // Now that the custom expander is done, expand the result, which is still
6132 ExpandOp(Op, Lo, Hi);
6137 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6138 if (VT == MVT::i64) {
6139 if (Node->getOperand(0).getValueType() == MVT::f32)
6140 LC = RTLIB::FPTOSINT_F32_I64;
6141 else if (Node->getOperand(0).getValueType() == MVT::f64)
6142 LC = RTLIB::FPTOSINT_F64_I64;
6143 else if (Node->getOperand(0).getValueType() == MVT::f80)
6144 LC = RTLIB::FPTOSINT_F80_I64;
6145 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6146 LC = RTLIB::FPTOSINT_PPCF128_I64;
6147 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6148 } else if (VT == MVT::i128) {
6149 if (Node->getOperand(0).getValueType() == MVT::f32)
6150 LC = RTLIB::FPTOSINT_F32_I128;
6151 else if (Node->getOperand(0).getValueType() == MVT::f64)
6152 LC = RTLIB::FPTOSINT_F64_I128;
6153 else if (Node->getOperand(0).getValueType() == MVT::f80)
6154 LC = RTLIB::FPTOSINT_F80_I128;
6155 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6156 LC = RTLIB::FPTOSINT_PPCF128_I128;
6157 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6159 assert(0 && "Unexpected uint-to-fp conversion!");
6164 case ISD::FP_TO_UINT: {
6165 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6167 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6168 case Expand: assert(0 && "cannot expand FP!");
6169 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6170 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6173 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6175 // Now that the custom expander is done, expand the result.
6177 ExpandOp(Op, Lo, Hi);
6182 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6183 if (VT == MVT::i64) {
6184 if (Node->getOperand(0).getValueType() == MVT::f32)
6185 LC = RTLIB::FPTOUINT_F32_I64;
6186 else if (Node->getOperand(0).getValueType() == MVT::f64)
6187 LC = RTLIB::FPTOUINT_F64_I64;
6188 else if (Node->getOperand(0).getValueType() == MVT::f80)
6189 LC = RTLIB::FPTOUINT_F80_I64;
6190 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6191 LC = RTLIB::FPTOUINT_PPCF128_I64;
6192 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6193 } else if (VT == MVT::i128) {
6194 if (Node->getOperand(0).getValueType() == MVT::f32)
6195 LC = RTLIB::FPTOUINT_F32_I128;
6196 else if (Node->getOperand(0).getValueType() == MVT::f64)
6197 LC = RTLIB::FPTOUINT_F64_I128;
6198 else if (Node->getOperand(0).getValueType() == MVT::f80)
6199 LC = RTLIB::FPTOUINT_F80_I128;
6200 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6201 LC = RTLIB::FPTOUINT_PPCF128_I128;
6202 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6204 assert(0 && "Unexpected uint-to-fp conversion!");
6210 // If the target wants custom lowering, do so.
6211 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6212 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6213 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6214 Op = TLI.LowerOperation(Op, DAG);
6216 // Now that the custom expander is done, expand the result, which is
6218 ExpandOp(Op, Lo, Hi);
6223 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6224 // this X << 1 as X+X.
6225 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6226 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6227 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6228 SDOperand LoOps[2], HiOps[3];
6229 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6230 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6231 LoOps[1] = LoOps[0];
6232 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6234 HiOps[1] = HiOps[0];
6235 HiOps[2] = Lo.getValue(1);
6236 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6241 // If we can emit an efficient shift operation, do so now.
6242 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6245 // If this target supports SHL_PARTS, use it.
6246 TargetLowering::LegalizeAction Action =
6247 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6248 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6249 Action == TargetLowering::Custom) {
6250 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6254 // Otherwise, emit a libcall.
6255 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6260 // If the target wants custom lowering, do so.
6261 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6262 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6263 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6264 Op = TLI.LowerOperation(Op, DAG);
6266 // Now that the custom expander is done, expand the result, which is
6268 ExpandOp(Op, Lo, Hi);
6273 // If we can emit an efficient shift operation, do so now.
6274 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6277 // If this target supports SRA_PARTS, use it.
6278 TargetLowering::LegalizeAction Action =
6279 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6280 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6281 Action == TargetLowering::Custom) {
6282 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6286 // Otherwise, emit a libcall.
6287 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6292 // If the target wants custom lowering, do so.
6293 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6294 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6295 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6296 Op = TLI.LowerOperation(Op, DAG);
6298 // Now that the custom expander is done, expand the result, which is
6300 ExpandOp(Op, Lo, Hi);
6305 // If we can emit an efficient shift operation, do so now.
6306 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6309 // If this target supports SRL_PARTS, use it.
6310 TargetLowering::LegalizeAction Action =
6311 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6312 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6313 Action == TargetLowering::Custom) {
6314 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6318 // Otherwise, emit a libcall.
6319 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6325 // If the target wants to custom expand this, let them.
6326 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6327 TargetLowering::Custom) {
6328 Op = TLI.LowerOperation(Op, DAG);
6330 ExpandOp(Op, Lo, Hi);
6335 // Expand the subcomponents.
6336 SDOperand LHSL, LHSH, RHSL, RHSH;
6337 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6338 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6339 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6340 SDOperand LoOps[2], HiOps[3];
6345 if (Node->getOpcode() == ISD::ADD) {
6346 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6347 HiOps[2] = Lo.getValue(1);
6348 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6350 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6351 HiOps[2] = Lo.getValue(1);
6352 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6359 // Expand the subcomponents.
6360 SDOperand LHSL, LHSH, RHSL, RHSH;
6361 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6362 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6363 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6364 SDOperand LoOps[2] = { LHSL, RHSL };
6365 SDOperand HiOps[3] = { LHSH, RHSH };
6367 if (Node->getOpcode() == ISD::ADDC) {
6368 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6369 HiOps[2] = Lo.getValue(1);
6370 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6372 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6373 HiOps[2] = Lo.getValue(1);
6374 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6376 // Remember that we legalized the flag.
6377 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6382 // Expand the subcomponents.
6383 SDOperand LHSL, LHSH, RHSL, RHSH;
6384 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6385 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6386 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6387 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6388 SDOperand HiOps[3] = { LHSH, RHSH };
6390 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6391 HiOps[2] = Lo.getValue(1);
6392 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6394 // Remember that we legalized the flag.
6395 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6399 // If the target wants to custom expand this, let them.
6400 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6401 SDOperand New = TLI.LowerOperation(Op, DAG);
6403 ExpandOp(New, Lo, Hi);
6408 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6409 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6410 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6411 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6412 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6413 SDOperand LL, LH, RL, RH;
6414 ExpandOp(Node->getOperand(0), LL, LH);
6415 ExpandOp(Node->getOperand(1), RL, RH);
6416 unsigned OuterBitSize = Op.getValueSizeInBits();
6417 unsigned InnerBitSize = RH.getValueSizeInBits();
6418 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6419 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6420 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
6421 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
6422 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
6423 // The inputs are both zero-extended.
6425 // We can emit a umul_lohi.
6426 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6427 Hi = SDOperand(Lo.Val, 1);
6431 // We can emit a mulhu+mul.
6432 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6433 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6437 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6438 // The input values are both sign-extended.
6440 // We can emit a smul_lohi.
6441 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6442 Hi = SDOperand(Lo.Val, 1);
6446 // We can emit a mulhs+mul.
6447 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6448 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6453 // Lo,Hi = umul LHS, RHS.
6454 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6455 DAG.getVTList(NVT, NVT), LL, RL);
6457 Hi = UMulLOHI.getValue(1);
6458 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6459 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6460 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6461 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6465 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6466 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6467 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6468 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6469 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6470 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6475 // If nothing else, we can make a libcall.
6476 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
6480 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
6483 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
6486 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
6489 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
6493 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
6496 RTLIB::ADD_PPCF128),
6500 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
6503 RTLIB::SUB_PPCF128),
6507 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
6510 RTLIB::MUL_PPCF128),
6514 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
6517 RTLIB::DIV_PPCF128),
6520 case ISD::FP_EXTEND:
6521 if (VT == MVT::ppcf128) {
6522 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6523 Node->getOperand(0).getValueType()==MVT::f64);
6524 const uint64_t zero = 0;
6525 if (Node->getOperand(0).getValueType()==MVT::f32)
6526 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6528 Hi = Node->getOperand(0);
6529 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6532 Lo = ExpandLibCall(RTLIB::FPEXT_F32_F64, Node, true, Hi);
6535 Lo = ExpandLibCall(RTLIB::FPROUND_F64_F32, Node, true, Hi);
6538 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::POWI_F32,
6541 RTLIB::POWI_PPCF128),
6547 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6548 switch(Node->getOpcode()) {
6550 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6551 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6554 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6555 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6558 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6559 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6561 default: assert(0 && "Unreachable!");
6563 Lo = ExpandLibCall(LC, Node, false, Hi);
6567 if (VT == MVT::ppcf128) {
6569 ExpandOp(Node->getOperand(0), Lo, Tmp);
6570 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6571 // lo = hi==fabs(hi) ? lo : -lo;
6572 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6573 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6574 DAG.getCondCode(ISD::SETEQ));
6577 SDOperand Mask = (VT == MVT::f64)
6578 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6579 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6580 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6581 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6582 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6583 if (getTypeAction(NVT) == Expand)
6584 ExpandOp(Lo, Lo, Hi);
6588 if (VT == MVT::ppcf128) {
6589 ExpandOp(Node->getOperand(0), Lo, Hi);
6590 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6591 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6594 SDOperand Mask = (VT == MVT::f64)
6595 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6596 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6597 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6598 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6599 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6600 if (getTypeAction(NVT) == Expand)
6601 ExpandOp(Lo, Lo, Hi);
6604 case ISD::FCOPYSIGN: {
6605 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6606 if (getTypeAction(NVT) == Expand)
6607 ExpandOp(Lo, Lo, Hi);
6610 case ISD::SINT_TO_FP:
6611 case ISD::UINT_TO_FP: {
6612 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6613 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
6615 // Promote the operand if needed. Do this before checking for
6616 // ppcf128 so conversions of i16 and i8 work.
6617 if (getTypeAction(SrcVT) == Promote) {
6618 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6620 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6621 DAG.getValueType(SrcVT))
6622 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6623 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6624 SrcVT = Node->getOperand(0).getValueType();
6627 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
6628 static const uint64_t zero = 0;
6630 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6631 Node->getOperand(0)));
6632 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6634 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6635 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6636 Node->getOperand(0)));
6637 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6638 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6639 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6640 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6641 DAG.getConstant(0, MVT::i32),
6642 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6644 APFloat(APInt(128, 2, TwoE32)),
6647 DAG.getCondCode(ISD::SETLT)),
6652 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6653 // si64->ppcf128 done by libcall, below
6654 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6655 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6657 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6658 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6659 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6660 DAG.getConstant(0, MVT::i64),
6661 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6663 APFloat(APInt(128, 2, TwoE64)),
6666 DAG.getCondCode(ISD::SETLT)),
6671 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6672 Node->getOperand(0));
6673 if (getTypeAction(Lo.getValueType()) == Expand)
6674 // float to i32 etc. can be 'expanded' to a single node.
6675 ExpandOp(Lo, Lo, Hi);
6680 // Make sure the resultant values have been legalized themselves, unless this
6681 // is a type that requires multi-step expansion.
6682 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6683 Lo = LegalizeOp(Lo);
6685 // Don't legalize the high part if it is expanded to a single node.
6686 Hi = LegalizeOp(Hi);
6689 // Remember in a map if the values will be reused later.
6690 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6691 assert(isNew && "Value already expanded?!?");
6694 /// SplitVectorOp - Given an operand of vector type, break it down into
6695 /// two smaller values, still of vector type.
6696 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6698 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
6699 SDNode *Node = Op.Val;
6700 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
6701 assert(NumElements > 1 && "Cannot split a single element vector!");
6703 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
6705 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6706 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6708 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
6709 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
6711 // See if we already split it.
6712 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6713 = SplitNodes.find(Op);
6714 if (I != SplitNodes.end()) {
6715 Lo = I->second.first;
6716 Hi = I->second.second;
6720 switch (Node->getOpcode()) {
6725 assert(0 && "Unhandled operation in SplitVectorOp!");
6727 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6728 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6730 case ISD::BUILD_PAIR:
6731 Lo = Node->getOperand(0);
6732 Hi = Node->getOperand(1);
6734 case ISD::INSERT_VECTOR_ELT: {
6735 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
6736 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6737 unsigned Index = Idx->getValue();
6738 SDOperand ScalarOp = Node->getOperand(1);
6739 if (Index < NewNumElts_Lo)
6740 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6741 DAG.getIntPtrConstant(Index));
6743 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6744 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
6747 SDOperand Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
6748 Node->getOperand(1),
6749 Node->getOperand(2));
6750 SplitVectorOp(Tmp, Lo, Hi);
6753 case ISD::VECTOR_SHUFFLE: {
6754 // Build the low part.
6755 SDOperand Mask = Node->getOperand(2);
6756 SmallVector<SDOperand, 8> Ops;
6757 MVT::ValueType PtrVT = TLI.getPointerTy();
6759 // Insert all of the elements from the input that are needed. We use
6760 // buildvector of extractelement here because the input vectors will have
6761 // to be legalized, so this makes the code simpler.
6762 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6763 SDOperand IdxNode = Mask.getOperand(i);
6764 if (IdxNode.getOpcode() == ISD::UNDEF) {
6765 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6768 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6769 SDOperand InVec = Node->getOperand(0);
6770 if (Idx >= NumElements) {
6771 InVec = Node->getOperand(1);
6774 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6775 DAG.getConstant(Idx, PtrVT)));
6777 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6780 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6781 SDOperand IdxNode = Mask.getOperand(i);
6782 if (IdxNode.getOpcode() == ISD::UNDEF) {
6783 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6786 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6787 SDOperand InVec = Node->getOperand(0);
6788 if (Idx >= NumElements) {
6789 InVec = Node->getOperand(1);
6792 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6793 DAG.getConstant(Idx, PtrVT)));
6795 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6798 case ISD::BUILD_VECTOR: {
6799 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6800 Node->op_begin()+NewNumElts_Lo);
6801 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6803 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6805 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6808 case ISD::CONCAT_VECTORS: {
6809 // FIXME: Handle non-power-of-two vectors?
6810 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6811 if (NewNumSubvectors == 1) {
6812 Lo = Node->getOperand(0);
6813 Hi = Node->getOperand(1);
6815 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6816 Node->op_begin()+NewNumSubvectors);
6817 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6819 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6821 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6826 SDOperand Cond = Node->getOperand(0);
6828 SDOperand LL, LH, RL, RH;
6829 SplitVectorOp(Node->getOperand(1), LL, LH);
6830 SplitVectorOp(Node->getOperand(2), RL, RH);
6832 if (MVT::isVector(Cond.getValueType())) {
6833 // Handle a vector merge.
6835 SplitVectorOp(Cond, CL, CH);
6836 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6837 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6839 // Handle a simple select with vector operands.
6840 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6841 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6861 SDOperand LL, LH, RL, RH;
6862 SplitVectorOp(Node->getOperand(0), LL, LH);
6863 SplitVectorOp(Node->getOperand(1), RL, RH);
6865 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6866 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6871 SplitVectorOp(Node->getOperand(0), L, H);
6873 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6874 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6885 case ISD::FP_TO_SINT:
6886 case ISD::FP_TO_UINT:
6887 case ISD::SINT_TO_FP:
6888 case ISD::UINT_TO_FP: {
6890 SplitVectorOp(Node->getOperand(0), L, H);
6892 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6893 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6897 LoadSDNode *LD = cast<LoadSDNode>(Node);
6898 SDOperand Ch = LD->getChain();
6899 SDOperand Ptr = LD->getBasePtr();
6900 const Value *SV = LD->getSrcValue();
6901 int SVOffset = LD->getSrcValueOffset();
6902 unsigned Alignment = LD->getAlignment();
6903 bool isVolatile = LD->isVolatile();
6905 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6906 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
6907 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6908 DAG.getIntPtrConstant(IncrementSize));
6909 SVOffset += IncrementSize;
6910 Alignment = MinAlign(Alignment, IncrementSize);
6911 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6913 // Build a factor node to remember that this load is independent of the
6915 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6918 // Remember that we legalized the chain.
6919 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6922 case ISD::BIT_CONVERT: {
6923 // We know the result is a vector. The input may be either a vector or a
6925 SDOperand InOp = Node->getOperand(0);
6926 if (!MVT::isVector(InOp.getValueType()) ||
6927 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
6928 // The input is a scalar or single-element vector.
6929 // Lower to a store/load so that it can be split.
6930 // FIXME: this could be improved probably.
6931 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6932 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val);
6934 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6936 PseudoSourceValue::getFixedStack(),
6938 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
6939 PseudoSourceValue::getFixedStack(),
6942 // Split the vector and convert each of the pieces now.
6943 SplitVectorOp(InOp, Lo, Hi);
6944 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6945 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6950 // Remember in a map if the values will be reused later.
6952 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6953 assert(isNew && "Value already split?!?");
6957 /// ScalarizeVectorOp - Given an operand of single-element vector type
6958 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6959 /// scalar (e.g. f32) value.
6960 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6961 assert(MVT::isVector(Op.getValueType()) &&
6962 "Bad ScalarizeVectorOp invocation!");
6963 SDNode *Node = Op.Val;
6964 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
6965 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
6967 // See if we already scalarized it.
6968 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
6969 if (I != ScalarizedNodes.end()) return I->second;
6972 switch (Node->getOpcode()) {
6975 Node->dump(&DAG); cerr << "\n";
6977 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
6994 Result = DAG.getNode(Node->getOpcode(),
6996 ScalarizeVectorOp(Node->getOperand(0)),
6997 ScalarizeVectorOp(Node->getOperand(1)));
7004 Result = DAG.getNode(Node->getOpcode(),
7006 ScalarizeVectorOp(Node->getOperand(0)));
7009 Result = DAG.getNode(Node->getOpcode(),
7011 ScalarizeVectorOp(Node->getOperand(0)),
7012 Node->getOperand(1));
7015 LoadSDNode *LD = cast<LoadSDNode>(Node);
7016 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7017 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7019 const Value *SV = LD->getSrcValue();
7020 int SVOffset = LD->getSrcValueOffset();
7021 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
7022 LD->isVolatile(), LD->getAlignment());
7024 // Remember that we legalized the chain.
7025 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7028 case ISD::BUILD_VECTOR:
7029 Result = Node->getOperand(0);
7031 case ISD::INSERT_VECTOR_ELT:
7032 // Returning the inserted scalar element.
7033 Result = Node->getOperand(1);
7035 case ISD::CONCAT_VECTORS:
7036 assert(Node->getOperand(0).getValueType() == NewVT &&
7037 "Concat of non-legal vectors not yet supported!");
7038 Result = Node->getOperand(0);
7040 case ISD::VECTOR_SHUFFLE: {
7041 // Figure out if the scalar is the LHS or RHS and return it.
7042 SDOperand EltNum = Node->getOperand(2).getOperand(0);
7043 if (cast<ConstantSDNode>(EltNum)->getValue())
7044 Result = ScalarizeVectorOp(Node->getOperand(1));
7046 Result = ScalarizeVectorOp(Node->getOperand(0));
7049 case ISD::EXTRACT_SUBVECTOR:
7050 Result = Node->getOperand(0);
7051 assert(Result.getValueType() == NewVT);
7053 case ISD::BIT_CONVERT:
7054 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
7057 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7058 ScalarizeVectorOp(Op.getOperand(1)),
7059 ScalarizeVectorOp(Op.getOperand(2)));
7063 if (TLI.isTypeLegal(NewVT))
7064 Result = LegalizeOp(Result);
7065 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7066 assert(isNew && "Value already scalarized?");
7071 // SelectionDAG::Legalize - This is the entry point for the file.
7073 void SelectionDAG::Legalize() {
7074 if (ViewLegalizeDAGs) viewGraph();
7076 /// run - This is the main entry point to this class.
7078 SelectionDAGLegalize(*this).LegalizeDAG();