1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class VISIBILITY_HIDDEN SelectionDAGLegalize {
55 // Libcall insertion helpers.
57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
58 /// legalized. We use this to ensure that calls are properly serialized
59 /// against each other, including inserted libcalls.
60 SDValue LastCALLSEQ_END;
62 /// IsLegalizingCall - This member is used *only* for purposes of providing
63 /// helpful assertions that a libcall isn't created while another call is
64 /// being legalized (which could lead to non-serialized call sequences).
65 bool IsLegalizingCall;
68 Legal, // The target natively supports this operation.
69 Promote, // This operation should be executed in a larger type.
70 Expand // Try to expand this to other ops, otherwise use a libcall.
73 /// ValueTypeActions - This is a bitvector that contains two bits for each
74 /// value type, where the two bits correspond to the LegalizeAction enum.
75 /// This can be queried with "getTypeAction(VT)".
76 TargetLowering::ValueTypeActionImpl ValueTypeActions;
78 /// LegalizedNodes - For nodes that are of legal width, and that have more
79 /// than one use, this map indicates what regularized operand to use. This
80 /// allows us to avoid legalizing the same thing more than once.
81 DenseMap<SDValue, SDValue> LegalizedNodes;
83 /// PromotedNodes - For nodes that are below legal width, and that have more
84 /// than one use, this map indicates what promoted value to use. This allows
85 /// us to avoid promoting the same thing more than once.
86 DenseMap<SDValue, SDValue> PromotedNodes;
88 /// ExpandedNodes - For nodes that need to be expanded this map indicates
89 /// which operands are the expanded version of the input. This allows
90 /// us to avoid expanding the same node more than once.
91 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
93 /// SplitNodes - For vector nodes that need to be split, this map indicates
94 /// which operands are the split version of the input. This allows us
95 /// to avoid splitting the same node more than once.
96 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
98 /// ScalarizedNodes - For nodes that need to be converted from vector types to
99 /// scalar types, this contains the mapping of ones we have already
100 /// processed to the result.
101 std::map<SDValue, SDValue> ScalarizedNodes;
103 /// WidenNodes - For nodes that need to be widened from one vector type to
104 /// another, this contains the mapping of those that we have already widen.
105 /// This allows us to avoid widening more than once.
106 std::map<SDValue, SDValue> WidenNodes;
108 void AddLegalizedOperand(SDValue From, SDValue To) {
109 LegalizedNodes.insert(std::make_pair(From, To));
110 // If someone requests legalization of the new node, return itself.
112 LegalizedNodes.insert(std::make_pair(To, To));
114 void AddPromotedOperand(SDValue From, SDValue To) {
115 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
116 assert(isNew && "Got into the map somehow?");
117 // If someone requests legalization of the new node, return itself.
118 LegalizedNodes.insert(std::make_pair(To, To));
120 void AddWidenedOperand(SDValue From, SDValue To) {
121 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second;
122 assert(isNew && "Got into the map somehow?");
123 // If someone requests legalization of the new node, return itself.
124 LegalizedNodes.insert(std::make_pair(To, To));
128 explicit SelectionDAGLegalize(SelectionDAG &DAG);
130 /// getTypeAction - Return how we should legalize values of this type, either
131 /// it is already legal or we need to expand it into multiple registers of
132 /// smaller integer type, or we need to promote it to a larger type.
133 LegalizeAction getTypeAction(MVT VT) const {
134 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
137 /// isTypeLegal - Return true if this type is legal on this target.
139 bool isTypeLegal(MVT VT) const {
140 return getTypeAction(VT) == Legal;
146 /// HandleOp - Legalize, Promote, or Expand the specified operand as
147 /// appropriate for its type.
148 void HandleOp(SDValue Op);
150 /// LegalizeOp - We know that the specified value has a legal type.
151 /// Recursively ensure that the operands have legal types, then return the
153 SDValue LegalizeOp(SDValue O);
155 /// UnrollVectorOp - We know that the given vector has a legal type, however
156 /// the operation it performs is not legal and is an operation that we have
157 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
158 /// operating on each element individually.
159 SDValue UnrollVectorOp(SDValue O);
161 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
162 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
163 /// is necessary to spill the vector being inserted into to memory, perform
164 /// the insert there, and then read the result back.
165 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
168 /// PromoteOp - Given an operation that produces a value in an invalid type,
169 /// promote it to compute the value into a larger type. The produced value
170 /// will have the correct bits for the low portion of the register, but no
171 /// guarantee is made about the top bits: it may be zero, sign-extended, or
173 SDValue PromoteOp(SDValue O);
175 /// ExpandOp - Expand the specified SDValue into its two component pieces
176 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
177 /// the LegalizedNodes map is filled in for any results that are not expanded,
178 /// the ExpandedNodes map is filled in for any results that are expanded, and
179 /// the Lo/Hi values are returned. This applies to integer types and Vector
181 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
183 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
184 /// (e.g., v3i32 to v4i32). The produced value will have the correct value
185 /// for the existing elements but no guarantee is made about the new elements
186 /// at the end of the vector: it may be zero, ones, or garbage. This is useful
187 /// when we have an instruction operating on an illegal vector type and we
188 /// want to widen it to do the computation on a legal wider vector type.
189 SDValue WidenVectorOp(SDValue Op, MVT WidenVT);
191 /// SplitVectorOp - Given an operand of vector type, break it down into
192 /// two smaller values.
193 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
195 /// ScalarizeVectorOp - Given an operand of single-element vector type
196 /// (e.g. v1f32), convert it into the equivalent operation that returns a
197 /// scalar (e.g. f32) value.
198 SDValue ScalarizeVectorOp(SDValue O);
200 /// Useful 16 element vector type that is used to pass operands for widening.
201 typedef SmallVector<SDValue, 16> SDValueVector;
203 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if
204 /// the LdChain contains a single load and false if it contains a token
205 /// factor for multiple loads. It takes
206 /// Result: location to return the result
207 /// LdChain: location to return the load chain
208 /// Op: load operation to widen
209 /// NVT: widen vector result type we want for the load
210 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
211 SDValue Op, MVT NVT);
213 /// Helper genWidenVectorLoads - Helper function to generate a set of
214 /// loads to load a vector with a resulting wider type. It takes
215 /// LdChain: list of chains for the load we have generated
216 /// Chain: incoming chain for the ld vector
217 /// BasePtr: base pointer to load from
218 /// SV: memory disambiguation source value
219 /// SVOffset: memory disambiugation offset
220 /// Alignment: alignment of the memory
221 /// isVolatile: volatile load
222 /// LdWidth: width of memory that we want to load
223 /// ResType: the wider result result type for the resulting loaded vector
224 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain,
225 SDValue BasePtr, const Value *SV,
226 int SVOffset, unsigned Alignment,
227 bool isVolatile, unsigned LdWidth,
230 /// StoreWidenVectorOp - Stores a widen vector into non widen memory
231 /// location. It takes
232 /// ST: store node that we want to replace
233 /// Chain: incoming store chain
234 /// BasePtr: base address of where we want to store into
235 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
238 /// Helper genWidenVectorStores - Helper function to generate a set of
239 /// stores to store a widen vector into non widen memory
241 // StChain: list of chains for the stores we have generated
242 // Chain: incoming chain for the ld vector
243 // BasePtr: base pointer to load from
244 // SV: memory disambiguation source value
245 // SVOffset: memory disambiugation offset
246 // Alignment: alignment of the memory
247 // isVolatile: volatile lod
248 // ValOp: value to store
249 // StWidth: width of memory that we want to store
250 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain,
251 SDValue BasePtr, const Value *SV,
252 int SVOffset, unsigned Alignment,
253 bool isVolatile, SDValue ValOp,
256 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
257 /// specified mask and type. Targets can specify exactly which masks they
258 /// support and the code generator is tasked with not creating illegal masks.
260 /// Note that this will also return true for shuffles that are promoted to a
263 /// If this is a legal shuffle, this method returns the (possibly promoted)
264 /// build_vector Mask. If it's not a legal shuffle, it returns null.
265 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
267 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
268 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
270 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC);
271 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC);
272 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC) {
273 LegalizeSetCCOperands(LHS, RHS, CC);
274 LegalizeSetCCCondCode(VT, LHS, RHS, CC);
277 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
279 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source);
281 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT);
282 SDValue ExpandBUILD_VECTOR(SDNode *Node);
283 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
284 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op);
285 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT);
286 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned);
287 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned);
289 SDValue ExpandBSWAP(SDValue Op);
290 SDValue ExpandBitCount(unsigned Opc, SDValue Op);
291 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
292 SDValue &Lo, SDValue &Hi);
293 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
294 SDValue &Lo, SDValue &Hi);
296 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
297 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
301 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
302 /// specified mask and type. Targets can specify exactly which masks they
303 /// support and the code generator is tasked with not creating illegal masks.
305 /// Note that this will also return true for shuffles that are promoted to a
307 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
308 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
310 case TargetLowering::Legal:
311 case TargetLowering::Custom:
313 case TargetLowering::Promote: {
314 // If this is promoted to a different type, convert the shuffle mask and
315 // ask if it is legal in the promoted type!
316 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
317 MVT EltVT = NVT.getVectorElementType();
319 // If we changed # elements, change the shuffle mask.
320 unsigned NumEltsGrowth =
321 NVT.getVectorNumElements() / VT.getVectorNumElements();
322 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
323 if (NumEltsGrowth > 1) {
324 // Renumber the elements.
325 SmallVector<SDValue, 8> Ops;
326 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
327 SDValue InOp = Mask.getOperand(i);
328 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
329 if (InOp.getOpcode() == ISD::UNDEF)
330 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
332 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
333 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
337 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
343 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
346 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
347 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
348 ValueTypeActions(TLI.getValueTypeActions()) {
349 assert(MVT::LAST_VALUETYPE <= 32 &&
350 "Too many value types for ValueTypeActions to hold!");
353 void SelectionDAGLegalize::LegalizeDAG() {
354 LastCALLSEQ_END = DAG.getEntryNode();
355 IsLegalizingCall = false;
357 // The legalize process is inherently a bottom-up recursive process (users
358 // legalize their uses before themselves). Given infinite stack space, we
359 // could just start legalizing on the root and traverse the whole graph. In
360 // practice however, this causes us to run out of stack space on large basic
361 // blocks. To avoid this problem, compute an ordering of the nodes where each
362 // node is only legalized after all of its operands are legalized.
363 DAG.AssignTopologicalOrder();
364 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
365 E = prior(DAG.allnodes_end()); I != next(E); ++I)
366 HandleOp(SDValue(I, 0));
368 // Finally, it's possible the root changed. Get the new root.
369 SDValue OldRoot = DAG.getRoot();
370 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
371 DAG.setRoot(LegalizedNodes[OldRoot]);
373 ExpandedNodes.clear();
374 LegalizedNodes.clear();
375 PromotedNodes.clear();
377 ScalarizedNodes.clear();
380 // Remove dead nodes now.
381 DAG.RemoveDeadNodes();
385 /// FindCallEndFromCallStart - Given a chained node that is part of a call
386 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
387 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
388 if (Node->getOpcode() == ISD::CALLSEQ_END)
390 if (Node->use_empty())
391 return 0; // No CallSeqEnd
393 // The chain is usually at the end.
394 SDValue TheChain(Node, Node->getNumValues()-1);
395 if (TheChain.getValueType() != MVT::Other) {
396 // Sometimes it's at the beginning.
397 TheChain = SDValue(Node, 0);
398 if (TheChain.getValueType() != MVT::Other) {
399 // Otherwise, hunt for it.
400 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
401 if (Node->getValueType(i) == MVT::Other) {
402 TheChain = SDValue(Node, i);
406 // Otherwise, we walked into a node without a chain.
407 if (TheChain.getValueType() != MVT::Other)
412 for (SDNode::use_iterator UI = Node->use_begin(),
413 E = Node->use_end(); UI != E; ++UI) {
415 // Make sure to only follow users of our token chain.
417 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
418 if (User->getOperand(i) == TheChain)
419 if (SDNode *Result = FindCallEndFromCallStart(User))
425 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
426 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
427 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
428 assert(Node && "Didn't find callseq_start for a call??");
429 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
431 assert(Node->getOperand(0).getValueType() == MVT::Other &&
432 "Node doesn't have a token chain argument!");
433 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
436 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
437 /// see if any uses can reach Dest. If no dest operands can get to dest,
438 /// legalize them, legalize ourself, and return false, otherwise, return true.
440 /// Keep track of the nodes we fine that actually do lead to Dest in
441 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
443 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
444 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
445 if (N == Dest) return true; // N certainly leads to Dest :)
447 // If we've already processed this node and it does lead to Dest, there is no
448 // need to reprocess it.
449 if (NodesLeadingTo.count(N)) return true;
451 // If the first result of this node has been already legalized, then it cannot
453 switch (getTypeAction(N->getValueType(0))) {
455 if (LegalizedNodes.count(SDValue(N, 0))) return false;
458 if (PromotedNodes.count(SDValue(N, 0))) return false;
461 if (ExpandedNodes.count(SDValue(N, 0))) return false;
465 // Okay, this node has not already been legalized. Check and legalize all
466 // operands. If none lead to Dest, then we can legalize this node.
467 bool OperandsLeadToDest = false;
468 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
469 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
470 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
472 if (OperandsLeadToDest) {
473 NodesLeadingTo.insert(N);
477 // Okay, this node looks safe, legalize it and return false.
478 HandleOp(SDValue(N, 0));
482 /// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as
483 /// appropriate for its type.
484 void SelectionDAGLegalize::HandleOp(SDValue Op) {
485 MVT VT = Op.getValueType();
486 switch (getTypeAction(VT)) {
487 default: assert(0 && "Bad type action!");
488 case Legal: (void)LegalizeOp(Op); break;
490 if (!VT.isVector()) {
495 // See if we can widen otherwise use Expand to either scalarize or split
496 MVT WidenVT = TLI.getWidenVectorType(VT);
497 if (WidenVT != MVT::Other) {
498 (void) WidenVectorOp(Op, WidenVT);
501 // else fall thru to expand since we can't widen the vector
504 if (!VT.isVector()) {
505 // If this is an illegal scalar, expand it into its two component
508 if (Op.getOpcode() == ISD::TargetConstant)
509 break; // Allow illegal target nodes.
511 } else if (VT.getVectorNumElements() == 1) {
512 // If this is an illegal single element vector, convert it to a
514 (void)ScalarizeVectorOp(Op);
516 // This is an illegal multiple element vector.
517 // Split it in half and legalize both parts.
519 SplitVectorOp(Op, X, Y);
525 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
526 /// a load from the constant pool.
527 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
528 SelectionDAG &DAG, TargetLowering &TLI) {
531 // If a FP immediate is precise when represented as a float and if the
532 // target can do an extending load from float to double, we put it into
533 // the constant pool as a float, even if it's is statically typed as a
534 // double. This shrinks FP constants and canonicalizes them for targets where
535 // an FP extending load is the same cost as a normal load (such as on the x87
536 // fp stack or PPC FP unit).
537 MVT VT = CFP->getValueType(0);
538 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
540 if (VT!=MVT::f64 && VT!=MVT::f32)
541 assert(0 && "Invalid type expansion");
542 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
543 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
548 while (SVT != MVT::f32) {
549 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
550 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
551 // Only do this if the target has a native EXTLOAD instruction from
553 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
554 TLI.ShouldShrinkFPConstant(OrigVT)) {
555 const Type *SType = SVT.getTypeForMVT();
556 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
562 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
563 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
565 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
566 CPIdx, PseudoSourceValue::getConstantPool(),
567 0, VT, false, Alignment);
568 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
569 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
573 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
576 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
577 SelectionDAG &DAG, TargetLowering &TLI) {
578 MVT VT = Node->getValueType(0);
579 MVT SrcVT = Node->getOperand(1).getValueType();
580 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
581 "fcopysign expansion only supported for f32 and f64");
582 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
584 // First get the sign bit of second operand.
585 SDValue Mask1 = (SrcVT == MVT::f64)
586 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
587 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
588 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
589 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
590 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
591 // Shift right or sign-extend it if the two operands have different types.
592 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
594 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
595 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
596 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
597 } else if (SizeDiff < 0) {
598 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
599 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
600 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
603 // Clear the sign bit of first operand.
604 SDValue Mask2 = (VT == MVT::f64)
605 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
606 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
607 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
608 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
609 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
611 // Or the value with the sign bit.
612 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
616 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
618 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
619 TargetLowering &TLI) {
620 SDValue Chain = ST->getChain();
621 SDValue Ptr = ST->getBasePtr();
622 SDValue Val = ST->getValue();
623 MVT VT = Val.getValueType();
624 int Alignment = ST->getAlignment();
625 int SVOffset = ST->getSrcValueOffset();
626 if (ST->getMemoryVT().isFloatingPoint() ||
627 ST->getMemoryVT().isVector()) {
628 // Expand to a bitconvert of the value to the integer type of the
629 // same size, then a (misaligned) int store.
631 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128)
633 else if (VT.is64BitVector() || VT==MVT::f64)
635 else if (VT==MVT::f32)
638 assert(0 && "Unaligned store of unsupported type");
640 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
641 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
642 SVOffset, ST->isVolatile(), Alignment);
644 assert(ST->getMemoryVT().isInteger() &&
645 !ST->getMemoryVT().isVector() &&
646 "Unaligned store of unknown type.");
647 // Get the half-size VT
649 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
650 int NumBits = NewStoredVT.getSizeInBits();
651 int IncrementSize = NumBits / 8;
653 // Divide the stored value in two parts.
654 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
656 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
658 // Store the two parts
659 SDValue Store1, Store2;
660 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
661 ST->getSrcValue(), SVOffset, NewStoredVT,
662 ST->isVolatile(), Alignment);
663 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
664 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
665 Alignment = MinAlign(Alignment, IncrementSize);
666 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
667 ST->getSrcValue(), SVOffset + IncrementSize,
668 NewStoredVT, ST->isVolatile(), Alignment);
670 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
673 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
675 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
676 TargetLowering &TLI) {
677 int SVOffset = LD->getSrcValueOffset();
678 SDValue Chain = LD->getChain();
679 SDValue Ptr = LD->getBasePtr();
680 MVT VT = LD->getValueType(0);
681 MVT LoadedVT = LD->getMemoryVT();
682 if (VT.isFloatingPoint() || VT.isVector()) {
683 // Expand to a (misaligned) integer load of the same size,
684 // then bitconvert to floating point or vector.
686 if (LoadedVT.is128BitVector() ||
687 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
689 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64)
691 else if (LoadedVT == MVT::f32)
694 assert(0 && "Unaligned load of unsupported type");
696 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
697 SVOffset, LD->isVolatile(),
699 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
700 if (VT.isFloatingPoint() && LoadedVT != VT)
701 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
703 SDValue Ops[] = { Result, Chain };
704 return DAG.getMergeValues(Ops, 2);
706 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
707 "Unaligned load of unsupported type.");
709 // Compute the new VT that is half the size of the old one. This is an
711 unsigned NumBits = LoadedVT.getSizeInBits();
713 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
716 unsigned Alignment = LD->getAlignment();
717 unsigned IncrementSize = NumBits / 8;
718 ISD::LoadExtType HiExtType = LD->getExtensionType();
720 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
721 if (HiExtType == ISD::NON_EXTLOAD)
722 HiExtType = ISD::ZEXTLOAD;
724 // Load the value in two parts
726 if (TLI.isLittleEndian()) {
727 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
728 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
729 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
730 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
731 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
732 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
733 MinAlign(Alignment, IncrementSize));
735 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
736 NewLoadedVT,LD->isVolatile(), Alignment);
737 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
738 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
739 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
740 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
741 MinAlign(Alignment, IncrementSize));
744 // aggregate the two parts
745 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
746 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
747 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
749 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
752 SDValue Ops[] = { Result, TF };
753 return DAG.getMergeValues(Ops, 2);
756 /// UnrollVectorOp - We know that the given vector has a legal type, however
757 /// the operation it performs is not legal and is an operation that we have
758 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
759 /// operating on each element individually.
760 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
761 MVT VT = Op.getValueType();
762 assert(isTypeLegal(VT) &&
763 "Caller should expand or promote operands that are not legal!");
764 assert(Op.getNode()->getNumValues() == 1 &&
765 "Can't unroll a vector with multiple results!");
766 unsigned NE = VT.getVectorNumElements();
767 MVT EltVT = VT.getVectorElementType();
769 SmallVector<SDValue, 8> Scalars;
770 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
771 for (unsigned i = 0; i != NE; ++i) {
772 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
773 SDValue Operand = Op.getOperand(j);
774 MVT OperandVT = Operand.getValueType();
775 if (OperandVT.isVector()) {
776 // A vector operand; extract a single element.
777 MVT OperandEltVT = OperandVT.getVectorElementType();
778 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
781 DAG.getConstant(i, MVT::i32));
783 // A scalar operand; just use it as is.
784 Operands[j] = Operand;
787 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
788 &Operands[0], Operands.size()));
791 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
794 /// GetFPLibCall - Return the right libcall for the given floating point type.
795 static RTLIB::Libcall GetFPLibCall(MVT VT,
796 RTLIB::Libcall Call_F32,
797 RTLIB::Libcall Call_F64,
798 RTLIB::Libcall Call_F80,
799 RTLIB::Libcall Call_PPCF128) {
801 VT == MVT::f32 ? Call_F32 :
802 VT == MVT::f64 ? Call_F64 :
803 VT == MVT::f80 ? Call_F80 :
804 VT == MVT::ppcf128 ? Call_PPCF128 :
805 RTLIB::UNKNOWN_LIBCALL;
808 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
809 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
810 /// is necessary to spill the vector being inserted into to memory, perform
811 /// the insert there, and then read the result back.
812 SDValue SelectionDAGLegalize::
813 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) {
818 // If the target doesn't support this, we have to spill the input vector
819 // to a temporary stack slot, update the element, then reload it. This is
820 // badness. We could also load the value into a vector register (either
821 // with a "move to register" or "extload into register" instruction, then
822 // permute it into place, if the idx is a constant and if the idx is
823 // supported by the target.
824 MVT VT = Tmp1.getValueType();
825 MVT EltVT = VT.getVectorElementType();
826 MVT IdxVT = Tmp3.getValueType();
827 MVT PtrVT = TLI.getPointerTy();
828 SDValue StackPtr = DAG.CreateStackTemporary(VT);
830 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
833 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
834 PseudoSourceValue::getFixedStack(SPFI), 0);
836 // Truncate or zero extend offset to target pointer type.
837 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
838 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
839 // Add the offset to the index.
840 unsigned EltSize = EltVT.getSizeInBits()/8;
841 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
842 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
843 // Store the scalar value.
844 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
845 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
846 // Load the updated vector.
847 return DAG.getLoad(VT, Ch, StackPtr,
848 PseudoSourceValue::getFixedStack(SPFI), 0);
851 /// LegalizeOp - We know that the specified value has a legal type, and
852 /// that its operands are legal. Now ensure that the operation itself
853 /// is legal, recursively ensuring that the operands' operations remain
855 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
856 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
859 assert(isTypeLegal(Op.getValueType()) &&
860 "Caller should expand or promote operands that are not legal!");
861 SDNode *Node = Op.getNode();
863 // If this operation defines any values that cannot be represented in a
864 // register on this target, make sure to expand or promote them.
865 if (Node->getNumValues() > 1) {
866 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
867 if (getTypeAction(Node->getValueType(i)) != Legal) {
868 HandleOp(Op.getValue(i));
869 assert(LegalizedNodes.count(Op) &&
870 "Handling didn't add legal operands!");
871 return LegalizedNodes[Op];
875 // Note that LegalizeOp may be reentered even from single-use nodes, which
876 // means that we always must cache transformed nodes.
877 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
878 if (I != LegalizedNodes.end()) return I->second;
880 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
882 bool isCustom = false;
884 switch (Node->getOpcode()) {
885 case ISD::FrameIndex:
886 case ISD::EntryToken:
888 case ISD::BasicBlock:
889 case ISD::TargetFrameIndex:
890 case ISD::TargetJumpTable:
891 case ISD::TargetConstant:
892 case ISD::TargetConstantFP:
893 case ISD::TargetConstantPool:
894 case ISD::TargetGlobalAddress:
895 case ISD::TargetGlobalTLSAddress:
896 case ISD::TargetExternalSymbol:
899 case ISD::MEMOPERAND:
902 // Primitives must all be legal.
903 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
904 "This must be legal!");
907 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
908 // If this is a target node, legalize it by legalizing the operands then
909 // passing it through.
910 SmallVector<SDValue, 8> Ops;
911 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
912 Ops.push_back(LegalizeOp(Node->getOperand(i)));
914 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
916 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
917 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
918 return Result.getValue(Op.getResNo());
920 // Otherwise this is an unhandled builtin node. splat.
922 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
924 assert(0 && "Do not know how to legalize this operator!");
926 case ISD::GLOBAL_OFFSET_TABLE:
927 case ISD::GlobalAddress:
928 case ISD::GlobalTLSAddress:
929 case ISD::ExternalSymbol:
930 case ISD::ConstantPool:
931 case ISD::JumpTable: // Nothing to do.
932 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
933 default: assert(0 && "This action is not supported yet!");
934 case TargetLowering::Custom:
935 Tmp1 = TLI.LowerOperation(Op, DAG);
936 if (Tmp1.getNode()) Result = Tmp1;
937 // FALLTHROUGH if the target doesn't want to lower this op after all.
938 case TargetLowering::Legal:
943 case ISD::RETURNADDR:
944 // The only option for these nodes is to custom lower them. If the target
945 // does not custom lower them, then return zero.
946 Tmp1 = TLI.LowerOperation(Op, DAG);
950 Result = DAG.getConstant(0, TLI.getPointerTy());
952 case ISD::FRAME_TO_ARGS_OFFSET: {
953 MVT VT = Node->getValueType(0);
954 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
955 default: assert(0 && "This action is not supported yet!");
956 case TargetLowering::Custom:
957 Result = TLI.LowerOperation(Op, DAG);
958 if (Result.getNode()) break;
960 case TargetLowering::Legal:
961 Result = DAG.getConstant(0, VT);
966 case ISD::EXCEPTIONADDR: {
967 Tmp1 = LegalizeOp(Node->getOperand(0));
968 MVT VT = Node->getValueType(0);
969 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
970 default: assert(0 && "This action is not supported yet!");
971 case TargetLowering::Expand: {
972 unsigned Reg = TLI.getExceptionAddressRegister();
973 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
976 case TargetLowering::Custom:
977 Result = TLI.LowerOperation(Op, DAG);
978 if (Result.getNode()) break;
980 case TargetLowering::Legal: {
981 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
982 Result = DAG.getMergeValues(Ops, 2);
987 if (Result.getNode()->getNumValues() == 1) break;
989 assert(Result.getNode()->getNumValues() == 2 &&
990 "Cannot return more than two values!");
992 // Since we produced two values, make sure to remember that we
993 // legalized both of them.
994 Tmp1 = LegalizeOp(Result);
995 Tmp2 = LegalizeOp(Result.getValue(1));
996 AddLegalizedOperand(Op.getValue(0), Tmp1);
997 AddLegalizedOperand(Op.getValue(1), Tmp2);
998 return Op.getResNo() ? Tmp2 : Tmp1;
999 case ISD::EHSELECTION: {
1000 Tmp1 = LegalizeOp(Node->getOperand(0));
1001 Tmp2 = LegalizeOp(Node->getOperand(1));
1002 MVT VT = Node->getValueType(0);
1003 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1004 default: assert(0 && "This action is not supported yet!");
1005 case TargetLowering::Expand: {
1006 unsigned Reg = TLI.getExceptionSelectorRegister();
1007 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
1010 case TargetLowering::Custom:
1011 Result = TLI.LowerOperation(Op, DAG);
1012 if (Result.getNode()) break;
1014 case TargetLowering::Legal: {
1015 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
1016 Result = DAG.getMergeValues(Ops, 2);
1021 if (Result.getNode()->getNumValues() == 1) break;
1023 assert(Result.getNode()->getNumValues() == 2 &&
1024 "Cannot return more than two values!");
1026 // Since we produced two values, make sure to remember that we
1027 // legalized both of them.
1028 Tmp1 = LegalizeOp(Result);
1029 Tmp2 = LegalizeOp(Result.getValue(1));
1030 AddLegalizedOperand(Op.getValue(0), Tmp1);
1031 AddLegalizedOperand(Op.getValue(1), Tmp2);
1032 return Op.getResNo() ? Tmp2 : Tmp1;
1033 case ISD::EH_RETURN: {
1034 MVT VT = Node->getValueType(0);
1035 // The only "good" option for this node is to custom lower it.
1036 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1037 default: assert(0 && "This action is not supported at all!");
1038 case TargetLowering::Custom:
1039 Result = TLI.LowerOperation(Op, DAG);
1040 if (Result.getNode()) break;
1042 case TargetLowering::Legal:
1043 // Target does not know, how to lower this, lower to noop
1044 Result = LegalizeOp(Node->getOperand(0));
1049 case ISD::AssertSext:
1050 case ISD::AssertZext:
1051 Tmp1 = LegalizeOp(Node->getOperand(0));
1052 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1054 case ISD::MERGE_VALUES:
1055 // Legalize eliminates MERGE_VALUES nodes.
1056 Result = Node->getOperand(Op.getResNo());
1058 case ISD::CopyFromReg:
1059 Tmp1 = LegalizeOp(Node->getOperand(0));
1060 Result = Op.getValue(0);
1061 if (Node->getNumValues() == 2) {
1062 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1064 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1065 if (Node->getNumOperands() == 3) {
1066 Tmp2 = LegalizeOp(Node->getOperand(2));
1067 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1069 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1071 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1073 // Since CopyFromReg produces two values, make sure to remember that we
1074 // legalized both of them.
1075 AddLegalizedOperand(Op.getValue(0), Result);
1076 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1077 return Result.getValue(Op.getResNo());
1079 MVT VT = Op.getValueType();
1080 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1081 default: assert(0 && "This action is not supported yet!");
1082 case TargetLowering::Expand:
1084 Result = DAG.getConstant(0, VT);
1085 else if (VT.isFloatingPoint())
1086 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1089 assert(0 && "Unknown value type!");
1091 case TargetLowering::Legal:
1097 case ISD::INTRINSIC_W_CHAIN:
1098 case ISD::INTRINSIC_WO_CHAIN:
1099 case ISD::INTRINSIC_VOID: {
1100 SmallVector<SDValue, 8> Ops;
1101 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1102 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1103 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1105 // Allow the target to custom lower its intrinsics if it wants to.
1106 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1107 TargetLowering::Custom) {
1108 Tmp3 = TLI.LowerOperation(Result, DAG);
1109 if (Tmp3.getNode()) Result = Tmp3;
1112 if (Result.getNode()->getNumValues() == 1) break;
1114 // Must have return value and chain result.
1115 assert(Result.getNode()->getNumValues() == 2 &&
1116 "Cannot return more than two values!");
1118 // Since loads produce two values, make sure to remember that we
1119 // legalized both of them.
1120 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1121 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1122 return Result.getValue(Op.getResNo());
1125 case ISD::DBG_STOPPOINT:
1126 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1127 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1129 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1130 case TargetLowering::Promote:
1131 default: assert(0 && "This action is not supported yet!");
1132 case TargetLowering::Expand: {
1133 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1134 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1135 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
1137 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1138 if (MMI && (useDEBUG_LOC || useLABEL)) {
1139 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
1140 unsigned SrcFile = MMI->RecordSource(CompileUnit);
1142 unsigned Line = DSP->getLine();
1143 unsigned Col = DSP->getColumn();
1146 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1147 DAG.getConstant(Col, MVT::i32),
1148 DAG.getConstant(SrcFile, MVT::i32) };
1149 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
1151 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1152 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1155 Result = Tmp1; // chain
1159 case TargetLowering::Legal: {
1160 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1161 if (Action == Legal && Tmp1 == Node->getOperand(0))
1164 SmallVector<SDValue, 8> Ops;
1165 Ops.push_back(Tmp1);
1166 if (Action == Legal) {
1167 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1168 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1170 // Otherwise promote them.
1171 Ops.push_back(PromoteOp(Node->getOperand(1)));
1172 Ops.push_back(PromoteOp(Node->getOperand(2)));
1174 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1175 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1176 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1183 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1184 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1185 default: assert(0 && "This action is not supported yet!");
1186 case TargetLowering::Legal:
1187 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1188 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1189 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1190 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1192 case TargetLowering::Expand:
1193 Result = LegalizeOp(Node->getOperand(0));
1198 case ISD::DEBUG_LOC:
1199 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1200 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1201 default: assert(0 && "This action is not supported yet!");
1202 case TargetLowering::Legal: {
1203 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1204 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1205 if (Action == Legal && Tmp1 == Node->getOperand(0))
1207 if (Action == Legal) {
1208 Tmp2 = Node->getOperand(1);
1209 Tmp3 = Node->getOperand(2);
1210 Tmp4 = Node->getOperand(3);
1212 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1213 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1214 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1216 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1222 case ISD::DBG_LABEL:
1224 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1225 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1226 default: assert(0 && "This action is not supported yet!");
1227 case TargetLowering::Legal:
1228 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1229 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1231 case TargetLowering::Expand:
1232 Result = LegalizeOp(Node->getOperand(0));
1238 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1239 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1240 default: assert(0 && "This action is not supported yet!");
1241 case TargetLowering::Legal:
1242 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1243 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1244 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1245 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1246 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1248 case TargetLowering::Expand:
1250 Result = LegalizeOp(Node->getOperand(0));
1255 case ISD::MEMBARRIER: {
1256 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1257 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1258 default: assert(0 && "This action is not supported yet!");
1259 case TargetLowering::Legal: {
1261 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1262 for (int x = 1; x < 6; ++x) {
1263 Ops[x] = Node->getOperand(x);
1264 if (!isTypeLegal(Ops[x].getValueType()))
1265 Ops[x] = PromoteOp(Ops[x]);
1267 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1270 case TargetLowering::Expand:
1271 //There is no libgcc call for this op
1272 Result = Node->getOperand(0); // Noop
1278 case ISD::ATOMIC_CMP_SWAP_8:
1279 case ISD::ATOMIC_CMP_SWAP_16:
1280 case ISD::ATOMIC_CMP_SWAP_32:
1281 case ISD::ATOMIC_CMP_SWAP_64: {
1282 unsigned int num_operands = 4;
1283 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1285 for (unsigned int x = 0; x < num_operands; ++x)
1286 Ops[x] = LegalizeOp(Node->getOperand(x));
1287 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1289 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1290 default: assert(0 && "This action is not supported yet!");
1291 case TargetLowering::Custom:
1292 Result = TLI.LowerOperation(Result, DAG);
1294 case TargetLowering::Legal:
1297 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1298 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1299 return Result.getValue(Op.getResNo());
1301 case ISD::ATOMIC_LOAD_ADD_8:
1302 case ISD::ATOMIC_LOAD_SUB_8:
1303 case ISD::ATOMIC_LOAD_AND_8:
1304 case ISD::ATOMIC_LOAD_OR_8:
1305 case ISD::ATOMIC_LOAD_XOR_8:
1306 case ISD::ATOMIC_LOAD_NAND_8:
1307 case ISD::ATOMIC_LOAD_MIN_8:
1308 case ISD::ATOMIC_LOAD_MAX_8:
1309 case ISD::ATOMIC_LOAD_UMIN_8:
1310 case ISD::ATOMIC_LOAD_UMAX_8:
1311 case ISD::ATOMIC_SWAP_8:
1312 case ISD::ATOMIC_LOAD_ADD_16:
1313 case ISD::ATOMIC_LOAD_SUB_16:
1314 case ISD::ATOMIC_LOAD_AND_16:
1315 case ISD::ATOMIC_LOAD_OR_16:
1316 case ISD::ATOMIC_LOAD_XOR_16:
1317 case ISD::ATOMIC_LOAD_NAND_16:
1318 case ISD::ATOMIC_LOAD_MIN_16:
1319 case ISD::ATOMIC_LOAD_MAX_16:
1320 case ISD::ATOMIC_LOAD_UMIN_16:
1321 case ISD::ATOMIC_LOAD_UMAX_16:
1322 case ISD::ATOMIC_SWAP_16:
1323 case ISD::ATOMIC_LOAD_ADD_32:
1324 case ISD::ATOMIC_LOAD_SUB_32:
1325 case ISD::ATOMIC_LOAD_AND_32:
1326 case ISD::ATOMIC_LOAD_OR_32:
1327 case ISD::ATOMIC_LOAD_XOR_32:
1328 case ISD::ATOMIC_LOAD_NAND_32:
1329 case ISD::ATOMIC_LOAD_MIN_32:
1330 case ISD::ATOMIC_LOAD_MAX_32:
1331 case ISD::ATOMIC_LOAD_UMIN_32:
1332 case ISD::ATOMIC_LOAD_UMAX_32:
1333 case ISD::ATOMIC_SWAP_32:
1334 case ISD::ATOMIC_LOAD_ADD_64:
1335 case ISD::ATOMIC_LOAD_SUB_64:
1336 case ISD::ATOMIC_LOAD_AND_64:
1337 case ISD::ATOMIC_LOAD_OR_64:
1338 case ISD::ATOMIC_LOAD_XOR_64:
1339 case ISD::ATOMIC_LOAD_NAND_64:
1340 case ISD::ATOMIC_LOAD_MIN_64:
1341 case ISD::ATOMIC_LOAD_MAX_64:
1342 case ISD::ATOMIC_LOAD_UMIN_64:
1343 case ISD::ATOMIC_LOAD_UMAX_64:
1344 case ISD::ATOMIC_SWAP_64: {
1345 unsigned int num_operands = 3;
1346 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1348 for (unsigned int x = 0; x < num_operands; ++x)
1349 Ops[x] = LegalizeOp(Node->getOperand(x));
1350 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1352 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1353 default: assert(0 && "This action is not supported yet!");
1354 case TargetLowering::Custom:
1355 Result = TLI.LowerOperation(Result, DAG);
1357 case TargetLowering::Legal:
1360 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1361 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1362 return Result.getValue(Op.getResNo());
1364 case ISD::Constant: {
1365 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1367 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1369 // We know we don't need to expand constants here, constants only have one
1370 // value and we check that it is fine above.
1372 if (opAction == TargetLowering::Custom) {
1373 Tmp1 = TLI.LowerOperation(Result, DAG);
1379 case ISD::ConstantFP: {
1380 // Spill FP immediates to the constant pool if the target cannot directly
1381 // codegen them. Targets often have some immediate values that can be
1382 // efficiently generated into an FP register without a load. We explicitly
1383 // leave these constants as ConstantFP nodes for the target to deal with.
1384 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1386 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1387 default: assert(0 && "This action is not supported yet!");
1388 case TargetLowering::Legal:
1390 case TargetLowering::Custom:
1391 Tmp3 = TLI.LowerOperation(Result, DAG);
1392 if (Tmp3.getNode()) {
1397 case TargetLowering::Expand: {
1398 // Check to see if this FP immediate is already legal.
1399 bool isLegal = false;
1400 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1401 E = TLI.legal_fpimm_end(); I != E; ++I) {
1402 if (CFP->isExactlyValue(*I)) {
1407 // If this is a legal constant, turn it into a TargetConstantFP node.
1410 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1415 case ISD::TokenFactor:
1416 if (Node->getNumOperands() == 2) {
1417 Tmp1 = LegalizeOp(Node->getOperand(0));
1418 Tmp2 = LegalizeOp(Node->getOperand(1));
1419 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1420 } else if (Node->getNumOperands() == 3) {
1421 Tmp1 = LegalizeOp(Node->getOperand(0));
1422 Tmp2 = LegalizeOp(Node->getOperand(1));
1423 Tmp3 = LegalizeOp(Node->getOperand(2));
1424 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1426 SmallVector<SDValue, 8> Ops;
1427 // Legalize the operands.
1428 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1429 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1430 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1434 case ISD::FORMAL_ARGUMENTS:
1436 // The only option for this is to custom lower it.
1437 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1438 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1439 // A call within a calling sequence must be legalized to something
1440 // other than the normal CALLSEQ_END. Violating this gets Legalize
1441 // into an infinite loop.
1442 assert ((!IsLegalizingCall ||
1443 Node->getOpcode() != ISD::CALL ||
1444 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1445 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1447 // The number of incoming and outgoing values should match; unless the final
1448 // outgoing value is a flag.
1449 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1450 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1451 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1453 "Lowering call/formal_arguments produced unexpected # results!");
1455 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1456 // remember that we legalized all of them, so it doesn't get relegalized.
1457 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1458 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1460 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1461 if (Op.getResNo() == i)
1463 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1466 case ISD::EXTRACT_SUBREG: {
1467 Tmp1 = LegalizeOp(Node->getOperand(0));
1468 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1469 assert(idx && "Operand must be a constant");
1470 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1471 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1474 case ISD::INSERT_SUBREG: {
1475 Tmp1 = LegalizeOp(Node->getOperand(0));
1476 Tmp2 = LegalizeOp(Node->getOperand(1));
1477 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1478 assert(idx && "Operand must be a constant");
1479 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1480 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1483 case ISD::BUILD_VECTOR:
1484 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1485 default: assert(0 && "This action is not supported yet!");
1486 case TargetLowering::Custom:
1487 Tmp3 = TLI.LowerOperation(Result, DAG);
1488 if (Tmp3.getNode()) {
1493 case TargetLowering::Expand:
1494 Result = ExpandBUILD_VECTOR(Result.getNode());
1498 case ISD::INSERT_VECTOR_ELT:
1499 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1500 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1502 // The type of the value to insert may not be legal, even though the vector
1503 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1505 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1506 default: assert(0 && "Cannot expand insert element operand");
1507 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1508 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1510 // FIXME: An alternative would be to check to see if the target is not
1511 // going to custom lower this operation, we could bitcast to half elt
1512 // width and perform two inserts at that width, if that is legal.
1513 Tmp2 = Node->getOperand(1);
1516 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1518 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1519 Node->getValueType(0))) {
1520 default: assert(0 && "This action is not supported yet!");
1521 case TargetLowering::Legal:
1523 case TargetLowering::Custom:
1524 Tmp4 = TLI.LowerOperation(Result, DAG);
1525 if (Tmp4.getNode()) {
1530 case TargetLowering::Promote:
1531 // Fall thru for vector case
1532 case TargetLowering::Expand: {
1533 // If the insert index is a constant, codegen this as a scalar_to_vector,
1534 // then a shuffle that inserts it into the right position in the vector.
1535 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1536 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1537 // match the element type of the vector being created.
1538 if (Tmp2.getValueType() ==
1539 Op.getValueType().getVectorElementType()) {
1540 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1541 Tmp1.getValueType(), Tmp2);
1543 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1545 MVT::getIntVectorWithNumElements(NumElts);
1546 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1548 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1549 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1550 // elt 0 of the RHS.
1551 SmallVector<SDValue, 8> ShufOps;
1552 for (unsigned i = 0; i != NumElts; ++i) {
1553 if (i != InsertPos->getZExtValue())
1554 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1556 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1558 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1559 &ShufOps[0], ShufOps.size());
1561 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1562 Tmp1, ScVec, ShufMask);
1563 Result = LegalizeOp(Result);
1567 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1572 case ISD::SCALAR_TO_VECTOR:
1573 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1574 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1578 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1579 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1580 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1581 Node->getValueType(0))) {
1582 default: assert(0 && "This action is not supported yet!");
1583 case TargetLowering::Legal:
1585 case TargetLowering::Custom:
1586 Tmp3 = TLI.LowerOperation(Result, DAG);
1587 if (Tmp3.getNode()) {
1592 case TargetLowering::Expand:
1593 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1597 case ISD::VECTOR_SHUFFLE:
1598 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1599 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1600 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1602 // Allow targets to custom lower the SHUFFLEs they support.
1603 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1604 default: assert(0 && "Unknown operation action!");
1605 case TargetLowering::Legal:
1606 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1607 "vector shuffle should not be created if not legal!");
1609 case TargetLowering::Custom:
1610 Tmp3 = TLI.LowerOperation(Result, DAG);
1611 if (Tmp3.getNode()) {
1616 case TargetLowering::Expand: {
1617 MVT VT = Node->getValueType(0);
1618 MVT EltVT = VT.getVectorElementType();
1619 MVT PtrVT = TLI.getPointerTy();
1620 SDValue Mask = Node->getOperand(2);
1621 unsigned NumElems = Mask.getNumOperands();
1622 SmallVector<SDValue,8> Ops;
1623 for (unsigned i = 0; i != NumElems; ++i) {
1624 SDValue Arg = Mask.getOperand(i);
1625 if (Arg.getOpcode() == ISD::UNDEF) {
1626 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1628 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1629 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1631 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1632 DAG.getConstant(Idx, PtrVT)));
1634 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1635 DAG.getConstant(Idx - NumElems, PtrVT)));
1638 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1641 case TargetLowering::Promote: {
1642 // Change base type to a different vector type.
1643 MVT OVT = Node->getValueType(0);
1644 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1646 // Cast the two input vectors.
1647 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1648 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1650 // Convert the shuffle mask to the right # elements.
1651 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1652 assert(Tmp3.getNode() && "Shuffle not legal?");
1653 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1654 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1660 case ISD::EXTRACT_VECTOR_ELT:
1661 Tmp1 = Node->getOperand(0);
1662 Tmp2 = LegalizeOp(Node->getOperand(1));
1663 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1664 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1667 case ISD::EXTRACT_SUBVECTOR:
1668 Tmp1 = Node->getOperand(0);
1669 Tmp2 = LegalizeOp(Node->getOperand(1));
1670 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1671 Result = ExpandEXTRACT_SUBVECTOR(Result);
1674 case ISD::CONCAT_VECTORS: {
1675 // Use extract/insert/build vector for now. We might try to be
1676 // more clever later.
1677 MVT PtrVT = TLI.getPointerTy();
1678 SmallVector<SDValue, 8> Ops;
1679 unsigned NumOperands = Node->getNumOperands();
1680 for (unsigned i=0; i < NumOperands; ++i) {
1681 SDValue SubOp = Node->getOperand(i);
1682 MVT VVT = SubOp.getNode()->getValueType(0);
1683 MVT EltVT = VVT.getVectorElementType();
1684 unsigned NumSubElem = VVT.getVectorNumElements();
1685 for (unsigned j=0; j < NumSubElem; ++j) {
1686 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, SubOp,
1687 DAG.getConstant(j, PtrVT)));
1690 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
1691 &Ops[0], Ops.size()));
1694 case ISD::CALLSEQ_START: {
1695 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1697 // Recursively Legalize all of the inputs of the call end that do not lead
1698 // to this call start. This ensures that any libcalls that need be inserted
1699 // are inserted *before* the CALLSEQ_START.
1700 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1701 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1702 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1706 // Now that we legalized all of the inputs (which may have inserted
1707 // libcalls) create the new CALLSEQ_START node.
1708 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1710 // Merge in the last call, to ensure that this call start after the last
1712 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1713 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1714 Tmp1 = LegalizeOp(Tmp1);
1717 // Do not try to legalize the target-specific arguments (#1+).
1718 if (Tmp1 != Node->getOperand(0)) {
1719 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1721 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1724 // Remember that the CALLSEQ_START is legalized.
1725 AddLegalizedOperand(Op.getValue(0), Result);
1726 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1727 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1729 // Now that the callseq_start and all of the non-call nodes above this call
1730 // sequence have been legalized, legalize the call itself. During this
1731 // process, no libcalls can/will be inserted, guaranteeing that no calls
1733 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1734 // Note that we are selecting this call!
1735 LastCALLSEQ_END = SDValue(CallEnd, 0);
1736 IsLegalizingCall = true;
1738 // Legalize the call, starting from the CALLSEQ_END.
1739 LegalizeOp(LastCALLSEQ_END);
1740 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1743 case ISD::CALLSEQ_END:
1744 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1745 // will cause this node to be legalized as well as handling libcalls right.
1746 if (LastCALLSEQ_END.getNode() != Node) {
1747 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1748 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1749 assert(I != LegalizedNodes.end() &&
1750 "Legalizing the call start should have legalized this node!");
1754 // Otherwise, the call start has been legalized and everything is going
1755 // according to plan. Just legalize ourselves normally here.
1756 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1757 // Do not try to legalize the target-specific arguments (#1+), except for
1758 // an optional flag input.
1759 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1760 if (Tmp1 != Node->getOperand(0)) {
1761 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1763 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1766 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1767 if (Tmp1 != Node->getOperand(0) ||
1768 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1769 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1772 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1775 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1776 // This finishes up call legalization.
1777 IsLegalizingCall = false;
1779 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1780 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1781 if (Node->getNumValues() == 2)
1782 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1783 return Result.getValue(Op.getResNo());
1784 case ISD::DYNAMIC_STACKALLOC: {
1785 MVT VT = Node->getValueType(0);
1786 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1787 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1788 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1789 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1791 Tmp1 = Result.getValue(0);
1792 Tmp2 = Result.getValue(1);
1793 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1794 default: assert(0 && "This action is not supported yet!");
1795 case TargetLowering::Expand: {
1796 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1797 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1798 " not tell us which reg is the stack pointer!");
1799 SDValue Chain = Tmp1.getOperand(0);
1801 // Chain the dynamic stack allocation so that it doesn't modify the stack
1802 // pointer when other instructions are using the stack.
1803 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1805 SDValue Size = Tmp2.getOperand(1);
1806 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1807 Chain = SP.getValue(1);
1808 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1809 unsigned StackAlign =
1810 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1811 if (Align > StackAlign)
1812 SP = DAG.getNode(ISD::AND, VT, SP,
1813 DAG.getConstant(-(uint64_t)Align, VT));
1814 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1815 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1817 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1818 DAG.getIntPtrConstant(0, true), SDValue());
1820 Tmp1 = LegalizeOp(Tmp1);
1821 Tmp2 = LegalizeOp(Tmp2);
1824 case TargetLowering::Custom:
1825 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1826 if (Tmp3.getNode()) {
1827 Tmp1 = LegalizeOp(Tmp3);
1828 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1831 case TargetLowering::Legal:
1834 // Since this op produce two values, make sure to remember that we
1835 // legalized both of them.
1836 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1837 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1838 return Op.getResNo() ? Tmp2 : Tmp1;
1840 case ISD::INLINEASM: {
1841 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1842 bool Changed = false;
1843 // Legalize all of the operands of the inline asm, in case they are nodes
1844 // that need to be expanded or something. Note we skip the asm string and
1845 // all of the TargetConstant flags.
1846 SDValue Op = LegalizeOp(Ops[0]);
1847 Changed = Op != Ops[0];
1850 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1851 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1852 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3;
1853 for (++i; NumVals; ++i, --NumVals) {
1854 SDValue Op = LegalizeOp(Ops[i]);
1863 Op = LegalizeOp(Ops.back());
1864 Changed |= Op != Ops.back();
1869 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1871 // INLINE asm returns a chain and flag, make sure to add both to the map.
1872 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1873 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1874 return Result.getValue(Op.getResNo());
1877 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1878 // Ensure that libcalls are emitted before a branch.
1879 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1880 Tmp1 = LegalizeOp(Tmp1);
1881 LastCALLSEQ_END = DAG.getEntryNode();
1883 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1886 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1887 // Ensure that libcalls are emitted before a branch.
1888 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1889 Tmp1 = LegalizeOp(Tmp1);
1890 LastCALLSEQ_END = DAG.getEntryNode();
1892 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1893 default: assert(0 && "Indirect target must be legal type (pointer)!");
1895 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1898 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1901 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1902 // Ensure that libcalls are emitted before a branch.
1903 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1904 Tmp1 = LegalizeOp(Tmp1);
1905 LastCALLSEQ_END = DAG.getEntryNode();
1907 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1908 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1910 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1911 default: assert(0 && "This action is not supported yet!");
1912 case TargetLowering::Legal: break;
1913 case TargetLowering::Custom:
1914 Tmp1 = TLI.LowerOperation(Result, DAG);
1915 if (Tmp1.getNode()) Result = Tmp1;
1917 case TargetLowering::Expand: {
1918 SDValue Chain = Result.getOperand(0);
1919 SDValue Table = Result.getOperand(1);
1920 SDValue Index = Result.getOperand(2);
1922 MVT PTy = TLI.getPointerTy();
1923 MachineFunction &MF = DAG.getMachineFunction();
1924 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1925 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1926 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1929 switch (EntrySize) {
1930 default: assert(0 && "Size of jump table not supported yet."); break;
1931 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1932 PseudoSourceValue::getJumpTable(), 0); break;
1933 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1934 PseudoSourceValue::getJumpTable(), 0); break;
1938 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1939 // For PIC, the sequence is:
1940 // BRIND(load(Jumptable + index) + RelocBase)
1941 // RelocBase can be JumpTable, GOT or some sort of global base.
1942 if (PTy != MVT::i32)
1943 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1944 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1945 TLI.getPICJumpTableRelocBase(Table, DAG));
1947 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1952 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1953 // Ensure that libcalls are emitted before a return.
1954 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1955 Tmp1 = LegalizeOp(Tmp1);
1956 LastCALLSEQ_END = DAG.getEntryNode();
1958 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1959 case Expand: assert(0 && "It's impossible to expand bools");
1961 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1964 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1966 // The top bits of the promoted condition are not necessarily zero, ensure
1967 // that the value is properly zero extended.
1968 unsigned BitWidth = Tmp2.getValueSizeInBits();
1969 if (!DAG.MaskedValueIsZero(Tmp2,
1970 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1971 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1976 // Basic block destination (Op#2) is always legal.
1977 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1979 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1980 default: assert(0 && "This action is not supported yet!");
1981 case TargetLowering::Legal: break;
1982 case TargetLowering::Custom:
1983 Tmp1 = TLI.LowerOperation(Result, DAG);
1984 if (Tmp1.getNode()) Result = Tmp1;
1986 case TargetLowering::Expand:
1987 // Expand brcond's setcc into its constituent parts and create a BR_CC
1989 if (Tmp2.getOpcode() == ISD::SETCC) {
1990 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1991 Tmp2.getOperand(0), Tmp2.getOperand(1),
1992 Node->getOperand(2));
1994 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1995 DAG.getCondCode(ISD::SETNE), Tmp2,
1996 DAG.getConstant(0, Tmp2.getValueType()),
1997 Node->getOperand(2));
2003 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2004 // Ensure that libcalls are emitted before a branch.
2005 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2006 Tmp1 = LegalizeOp(Tmp1);
2007 Tmp2 = Node->getOperand(2); // LHS
2008 Tmp3 = Node->getOperand(3); // RHS
2009 Tmp4 = Node->getOperand(1); // CC
2011 LegalizeSetCC(Node->getValueType(0), Tmp2, Tmp3, Tmp4);
2012 LastCALLSEQ_END = DAG.getEntryNode();
2014 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2015 // the LHS is a legal SETCC itself. In this case, we need to compare
2016 // the result against zero to select between true and false values.
2017 if (Tmp3.getNode() == 0) {
2018 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2019 Tmp4 = DAG.getCondCode(ISD::SETNE);
2022 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
2023 Node->getOperand(4));
2025 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
2026 default: assert(0 && "Unexpected action for BR_CC!");
2027 case TargetLowering::Legal: break;
2028 case TargetLowering::Custom:
2029 Tmp4 = TLI.LowerOperation(Result, DAG);
2030 if (Tmp4.getNode()) Result = Tmp4;
2035 LoadSDNode *LD = cast<LoadSDNode>(Node);
2036 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
2037 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
2039 ISD::LoadExtType ExtType = LD->getExtensionType();
2040 if (ExtType == ISD::NON_EXTLOAD) {
2041 MVT VT = Node->getValueType(0);
2042 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2043 Tmp3 = Result.getValue(0);
2044 Tmp4 = Result.getValue(1);
2046 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
2047 default: assert(0 && "This action is not supported yet!");
2048 case TargetLowering::Legal:
2049 // If this is an unaligned load and the target doesn't support it,
2051 if (!TLI.allowsUnalignedMemoryAccesses()) {
2052 unsigned ABIAlignment = TLI.getTargetData()->
2053 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2054 if (LD->getAlignment() < ABIAlignment){
2055 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2057 Tmp3 = Result.getOperand(0);
2058 Tmp4 = Result.getOperand(1);
2059 Tmp3 = LegalizeOp(Tmp3);
2060 Tmp4 = LegalizeOp(Tmp4);
2064 case TargetLowering::Custom:
2065 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
2066 if (Tmp1.getNode()) {
2067 Tmp3 = LegalizeOp(Tmp1);
2068 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2071 case TargetLowering::Promote: {
2072 // Only promote a load of vector type to another.
2073 assert(VT.isVector() && "Cannot promote this load!");
2074 // Change base type to a different vector type.
2075 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
2077 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
2078 LD->getSrcValueOffset(),
2079 LD->isVolatile(), LD->getAlignment());
2080 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
2081 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2085 // Since loads produce two values, make sure to remember that we
2086 // legalized both of them.
2087 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
2088 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
2089 return Op.getResNo() ? Tmp4 : Tmp3;
2091 MVT SrcVT = LD->getMemoryVT();
2092 unsigned SrcWidth = SrcVT.getSizeInBits();
2093 int SVOffset = LD->getSrcValueOffset();
2094 unsigned Alignment = LD->getAlignment();
2095 bool isVolatile = LD->isVolatile();
2097 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
2098 // Some targets pretend to have an i1 loading operation, and actually
2099 // load an i8. This trick is correct for ZEXTLOAD because the top 7
2100 // bits are guaranteed to be zero; it helps the optimizers understand
2101 // that these bits are zero. It is also useful for EXTLOAD, since it
2102 // tells the optimizers that those bits are undefined. It would be
2103 // nice to have an effective generic way of getting these benefits...
2104 // Until such a way is found, don't insist on promoting i1 here.
2105 (SrcVT != MVT::i1 ||
2106 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2107 // Promote to a byte-sized load if not loading an integral number of
2108 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2109 unsigned NewWidth = SrcVT.getStoreSizeInBits();
2110 MVT NVT = MVT::getIntegerVT(NewWidth);
2113 // The extra bits are guaranteed to be zero, since we stored them that
2114 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2116 ISD::LoadExtType NewExtType =
2117 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2119 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2120 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2121 NVT, isVolatile, Alignment);
2123 Ch = Result.getValue(1); // The chain.
2125 if (ExtType == ISD::SEXTLOAD)
2126 // Having the top bits zero doesn't help when sign extending.
2127 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2128 Result, DAG.getValueType(SrcVT));
2129 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2130 // All the top bits are guaranteed to be zero - inform the optimizers.
2131 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2132 DAG.getValueType(SrcVT));
2134 Tmp1 = LegalizeOp(Result);
2135 Tmp2 = LegalizeOp(Ch);
2136 } else if (SrcWidth & (SrcWidth - 1)) {
2137 // If not loading a power-of-2 number of bits, expand as two loads.
2138 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2139 "Unsupported extload!");
2140 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2141 assert(RoundWidth < SrcWidth);
2142 unsigned ExtraWidth = SrcWidth - RoundWidth;
2143 assert(ExtraWidth < RoundWidth);
2144 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2145 "Load size not an integral number of bytes!");
2146 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2147 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2149 unsigned IncrementSize;
2151 if (TLI.isLittleEndian()) {
2152 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2153 // Load the bottom RoundWidth bits.
2154 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2155 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2158 // Load the remaining ExtraWidth bits.
2159 IncrementSize = RoundWidth / 8;
2160 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2161 DAG.getIntPtrConstant(IncrementSize));
2162 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2163 LD->getSrcValue(), SVOffset + IncrementSize,
2164 ExtraVT, isVolatile,
2165 MinAlign(Alignment, IncrementSize));
2167 // Build a factor node to remember that this load is independent of the
2169 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2172 // Move the top bits to the right place.
2173 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2174 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2176 // Join the hi and lo parts.
2177 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2179 // Big endian - avoid unaligned loads.
2180 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2181 // Load the top RoundWidth bits.
2182 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2183 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2186 // Load the remaining ExtraWidth bits.
2187 IncrementSize = RoundWidth / 8;
2188 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2189 DAG.getIntPtrConstant(IncrementSize));
2190 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2191 LD->getSrcValue(), SVOffset + IncrementSize,
2192 ExtraVT, isVolatile,
2193 MinAlign(Alignment, IncrementSize));
2195 // Build a factor node to remember that this load is independent of the
2197 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2200 // Move the top bits to the right place.
2201 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2202 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2204 // Join the hi and lo parts.
2205 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2208 Tmp1 = LegalizeOp(Result);
2209 Tmp2 = LegalizeOp(Ch);
2211 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
2212 default: assert(0 && "This action is not supported yet!");
2213 case TargetLowering::Custom:
2216 case TargetLowering::Legal:
2217 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2218 Tmp1 = Result.getValue(0);
2219 Tmp2 = Result.getValue(1);
2222 Tmp3 = TLI.LowerOperation(Result, DAG);
2223 if (Tmp3.getNode()) {
2224 Tmp1 = LegalizeOp(Tmp3);
2225 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2228 // If this is an unaligned load and the target doesn't support it,
2230 if (!TLI.allowsUnalignedMemoryAccesses()) {
2231 unsigned ABIAlignment = TLI.getTargetData()->
2232 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2233 if (LD->getAlignment() < ABIAlignment){
2234 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2236 Tmp1 = Result.getOperand(0);
2237 Tmp2 = Result.getOperand(1);
2238 Tmp1 = LegalizeOp(Tmp1);
2239 Tmp2 = LegalizeOp(Tmp2);
2244 case TargetLowering::Expand:
2245 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2246 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2247 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2248 LD->getSrcValueOffset(),
2249 LD->isVolatile(), LD->getAlignment());
2250 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2251 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2252 Tmp2 = LegalizeOp(Load.getValue(1));
2255 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2256 // Turn the unsupported load into an EXTLOAD followed by an explicit
2257 // zero/sign extend inreg.
2258 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2259 Tmp1, Tmp2, LD->getSrcValue(),
2260 LD->getSrcValueOffset(), SrcVT,
2261 LD->isVolatile(), LD->getAlignment());
2263 if (ExtType == ISD::SEXTLOAD)
2264 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2265 Result, DAG.getValueType(SrcVT));
2267 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2268 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2269 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2274 // Since loads produce two values, make sure to remember that we legalized
2276 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2277 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2278 return Op.getResNo() ? Tmp2 : Tmp1;
2281 case ISD::EXTRACT_ELEMENT: {
2282 MVT OpTy = Node->getOperand(0).getValueType();
2283 switch (getTypeAction(OpTy)) {
2284 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2286 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2288 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2289 DAG.getConstant(OpTy.getSizeInBits()/2,
2290 TLI.getShiftAmountTy()));
2291 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2294 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2295 Node->getOperand(0));
2299 // Get both the low and high parts.
2300 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2301 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2302 Result = Tmp2; // 1 -> Hi
2304 Result = Tmp1; // 0 -> Lo
2310 case ISD::CopyToReg:
2311 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2313 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2314 "Register type must be legal!");
2315 // Legalize the incoming value (must be a legal type).
2316 Tmp2 = LegalizeOp(Node->getOperand(2));
2317 if (Node->getNumValues() == 1) {
2318 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2320 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2321 if (Node->getNumOperands() == 4) {
2322 Tmp3 = LegalizeOp(Node->getOperand(3));
2323 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2326 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2329 // Since this produces two values, make sure to remember that we legalized
2331 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2332 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2338 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2340 // Ensure that libcalls are emitted before a return.
2341 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2342 Tmp1 = LegalizeOp(Tmp1);
2343 LastCALLSEQ_END = DAG.getEntryNode();
2345 switch (Node->getNumOperands()) {
2347 Tmp2 = Node->getOperand(1);
2348 Tmp3 = Node->getOperand(2); // Signness
2349 switch (getTypeAction(Tmp2.getValueType())) {
2351 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2354 if (!Tmp2.getValueType().isVector()) {
2356 ExpandOp(Tmp2, Lo, Hi);
2358 // Big endian systems want the hi reg first.
2359 if (TLI.isBigEndian())
2363 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2365 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2366 Result = LegalizeOp(Result);
2368 SDNode *InVal = Tmp2.getNode();
2369 int InIx = Tmp2.getResNo();
2370 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2371 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2373 // Figure out if there is a simple type corresponding to this Vector
2374 // type. If so, convert to the vector type.
2375 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2376 if (TLI.isTypeLegal(TVT)) {
2377 // Turn this into a return of the vector type.
2378 Tmp2 = LegalizeOp(Tmp2);
2379 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2380 } else if (NumElems == 1) {
2381 // Turn this into a return of the scalar type.
2382 Tmp2 = ScalarizeVectorOp(Tmp2);
2383 Tmp2 = LegalizeOp(Tmp2);
2384 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2386 // FIXME: Returns of gcc generic vectors smaller than a legal type
2387 // should be returned in integer registers!
2389 // The scalarized value type may not be legal, e.g. it might require
2390 // promotion or expansion. Relegalize the return.
2391 Result = LegalizeOp(Result);
2393 // FIXME: Returns of gcc generic vectors larger than a legal vector
2394 // type should be returned by reference!
2396 SplitVectorOp(Tmp2, Lo, Hi);
2397 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2398 Result = LegalizeOp(Result);
2403 Tmp2 = PromoteOp(Node->getOperand(1));
2404 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2405 Result = LegalizeOp(Result);
2410 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2412 default: { // ret <values>
2413 SmallVector<SDValue, 8> NewValues;
2414 NewValues.push_back(Tmp1);
2415 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2416 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2418 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2419 NewValues.push_back(Node->getOperand(i+1));
2423 assert(!Node->getOperand(i).getValueType().isExtended() &&
2424 "FIXME: TODO: implement returning non-legal vector types!");
2425 ExpandOp(Node->getOperand(i), Lo, Hi);
2426 NewValues.push_back(Lo);
2427 NewValues.push_back(Node->getOperand(i+1));
2429 NewValues.push_back(Hi);
2430 NewValues.push_back(Node->getOperand(i+1));
2435 assert(0 && "Can't promote multiple return value yet!");
2438 if (NewValues.size() == Node->getNumOperands())
2439 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2441 Result = DAG.getNode(ISD::RET, MVT::Other,
2442 &NewValues[0], NewValues.size());
2447 if (Result.getOpcode() == ISD::RET) {
2448 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2449 default: assert(0 && "This action is not supported yet!");
2450 case TargetLowering::Legal: break;
2451 case TargetLowering::Custom:
2452 Tmp1 = TLI.LowerOperation(Result, DAG);
2453 if (Tmp1.getNode()) Result = Tmp1;
2459 StoreSDNode *ST = cast<StoreSDNode>(Node);
2460 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2461 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2462 int SVOffset = ST->getSrcValueOffset();
2463 unsigned Alignment = ST->getAlignment();
2464 bool isVolatile = ST->isVolatile();
2466 if (!ST->isTruncatingStore()) {
2467 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2468 // FIXME: We shouldn't do this for TargetConstantFP's.
2469 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2470 // to phase ordering between legalized code and the dag combiner. This
2471 // probably means that we need to integrate dag combiner and legalizer
2473 // We generally can't do this one for long doubles.
2474 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2475 if (CFP->getValueType(0) == MVT::f32 &&
2476 getTypeAction(MVT::i32) == Legal) {
2477 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2478 bitcastToAPInt().zextOrTrunc(32),
2480 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2481 SVOffset, isVolatile, Alignment);
2483 } else if (CFP->getValueType(0) == MVT::f64) {
2484 // If this target supports 64-bit registers, do a single 64-bit store.
2485 if (getTypeAction(MVT::i64) == Legal) {
2486 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
2487 zextOrTrunc(64), MVT::i64);
2488 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2489 SVOffset, isVolatile, Alignment);
2491 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2492 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2493 // stores. If the target supports neither 32- nor 64-bits, this
2494 // xform is certainly not worth it.
2495 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
2496 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2497 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2498 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2500 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2501 SVOffset, isVolatile, Alignment);
2502 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2503 DAG.getIntPtrConstant(4));
2504 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2505 isVolatile, MinAlign(Alignment, 4U));
2507 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2513 switch (getTypeAction(ST->getMemoryVT())) {
2515 Tmp3 = LegalizeOp(ST->getValue());
2516 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2519 MVT VT = Tmp3.getValueType();
2520 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2521 default: assert(0 && "This action is not supported yet!");
2522 case TargetLowering::Legal:
2523 // If this is an unaligned store and the target doesn't support it,
2525 if (!TLI.allowsUnalignedMemoryAccesses()) {
2526 unsigned ABIAlignment = TLI.getTargetData()->
2527 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2528 if (ST->getAlignment() < ABIAlignment)
2529 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2533 case TargetLowering::Custom:
2534 Tmp1 = TLI.LowerOperation(Result, DAG);
2535 if (Tmp1.getNode()) Result = Tmp1;
2537 case TargetLowering::Promote:
2538 assert(VT.isVector() && "Unknown legal promote case!");
2539 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2540 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2541 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2542 ST->getSrcValue(), SVOffset, isVolatile,
2549 if (!ST->getMemoryVT().isVector()) {
2550 // Truncate the value and store the result.
2551 Tmp3 = PromoteOp(ST->getValue());
2552 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2553 SVOffset, ST->getMemoryVT(),
2554 isVolatile, Alignment);
2557 // Fall thru to expand for vector
2559 unsigned IncrementSize = 0;
2562 // If this is a vector type, then we have to calculate the increment as
2563 // the product of the element size in bytes, and the number of elements
2564 // in the high half of the vector.
2565 if (ST->getValue().getValueType().isVector()) {
2566 SDNode *InVal = ST->getValue().getNode();
2567 int InIx = ST->getValue().getResNo();
2568 MVT InVT = InVal->getValueType(InIx);
2569 unsigned NumElems = InVT.getVectorNumElements();
2570 MVT EVT = InVT.getVectorElementType();
2572 // Figure out if there is a simple type corresponding to this Vector
2573 // type. If so, convert to the vector type.
2574 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2575 if (TLI.isTypeLegal(TVT)) {
2576 // Turn this into a normal store of the vector type.
2577 Tmp3 = LegalizeOp(ST->getValue());
2578 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2579 SVOffset, isVolatile, Alignment);
2580 Result = LegalizeOp(Result);
2582 } else if (NumElems == 1) {
2583 // Turn this into a normal store of the scalar type.
2584 Tmp3 = ScalarizeVectorOp(ST->getValue());
2585 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2586 SVOffset, isVolatile, Alignment);
2587 // The scalarized value type may not be legal, e.g. it might require
2588 // promotion or expansion. Relegalize the scalar store.
2589 Result = LegalizeOp(Result);
2592 // Check if we have widen this node with another value
2593 std::map<SDValue, SDValue>::iterator I =
2594 WidenNodes.find(ST->getValue());
2595 if (I != WidenNodes.end()) {
2596 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2);
2600 SplitVectorOp(ST->getValue(), Lo, Hi);
2601 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2602 EVT.getSizeInBits()/8;
2606 ExpandOp(ST->getValue(), Lo, Hi);
2607 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2609 if (Hi.getNode() && TLI.isBigEndian())
2613 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2614 SVOffset, isVolatile, Alignment);
2616 if (Hi.getNode() == NULL) {
2617 // Must be int <-> float one-to-one expansion.
2622 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2623 DAG.getIntPtrConstant(IncrementSize));
2624 assert(isTypeLegal(Tmp2.getValueType()) &&
2625 "Pointers must be legal!");
2626 SVOffset += IncrementSize;
2627 Alignment = MinAlign(Alignment, IncrementSize);
2628 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2629 SVOffset, isVolatile, Alignment);
2630 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2635 switch (getTypeAction(ST->getValue().getValueType())) {
2637 Tmp3 = LegalizeOp(ST->getValue());
2640 if (!ST->getValue().getValueType().isVector()) {
2641 // We can promote the value, the truncstore will still take care of it.
2642 Tmp3 = PromoteOp(ST->getValue());
2645 // Vector case falls through to expand
2647 // Just store the low part. This may become a non-trunc store, so make
2648 // sure to use getTruncStore, not UpdateNodeOperands below.
2649 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2650 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2651 SVOffset, MVT::i8, isVolatile, Alignment);
2654 MVT StVT = ST->getMemoryVT();
2655 unsigned StWidth = StVT.getSizeInBits();
2657 if (StWidth != StVT.getStoreSizeInBits()) {
2658 // Promote to a byte-sized store with upper bits zero if not
2659 // storing an integral number of bytes. For example, promote
2660 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2661 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2662 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2663 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2664 SVOffset, NVT, isVolatile, Alignment);
2665 } else if (StWidth & (StWidth - 1)) {
2666 // If not storing a power-of-2 number of bits, expand as two stores.
2667 assert(StVT.isExtended() && !StVT.isVector() &&
2668 "Unsupported truncstore!");
2669 unsigned RoundWidth = 1 << Log2_32(StWidth);
2670 assert(RoundWidth < StWidth);
2671 unsigned ExtraWidth = StWidth - RoundWidth;
2672 assert(ExtraWidth < RoundWidth);
2673 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2674 "Store size not an integral number of bytes!");
2675 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2676 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2678 unsigned IncrementSize;
2680 if (TLI.isLittleEndian()) {
2681 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2682 // Store the bottom RoundWidth bits.
2683 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2685 isVolatile, Alignment);
2687 // Store the remaining ExtraWidth bits.
2688 IncrementSize = RoundWidth / 8;
2689 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2690 DAG.getIntPtrConstant(IncrementSize));
2691 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2692 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2693 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2694 SVOffset + IncrementSize, ExtraVT, isVolatile,
2695 MinAlign(Alignment, IncrementSize));
2697 // Big endian - avoid unaligned stores.
2698 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2699 // Store the top RoundWidth bits.
2700 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2701 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2702 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2703 RoundVT, isVolatile, Alignment);
2705 // Store the remaining ExtraWidth bits.
2706 IncrementSize = RoundWidth / 8;
2707 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2708 DAG.getIntPtrConstant(IncrementSize));
2709 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2710 SVOffset + IncrementSize, ExtraVT, isVolatile,
2711 MinAlign(Alignment, IncrementSize));
2714 // The order of the stores doesn't matter.
2715 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2717 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2718 Tmp2 != ST->getBasePtr())
2719 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2722 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2723 default: assert(0 && "This action is not supported yet!");
2724 case TargetLowering::Legal:
2725 // If this is an unaligned store and the target doesn't support it,
2727 if (!TLI.allowsUnalignedMemoryAccesses()) {
2728 unsigned ABIAlignment = TLI.getTargetData()->
2729 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2730 if (ST->getAlignment() < ABIAlignment)
2731 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2735 case TargetLowering::Custom:
2736 Result = TLI.LowerOperation(Result, DAG);
2739 // TRUNCSTORE:i16 i32 -> STORE i16
2740 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2741 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2742 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2743 isVolatile, Alignment);
2751 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2752 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2754 case ISD::STACKSAVE:
2755 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2756 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2757 Tmp1 = Result.getValue(0);
2758 Tmp2 = Result.getValue(1);
2760 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2761 default: assert(0 && "This action is not supported yet!");
2762 case TargetLowering::Legal: break;
2763 case TargetLowering::Custom:
2764 Tmp3 = TLI.LowerOperation(Result, DAG);
2765 if (Tmp3.getNode()) {
2766 Tmp1 = LegalizeOp(Tmp3);
2767 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2770 case TargetLowering::Expand:
2771 // Expand to CopyFromReg if the target set
2772 // StackPointerRegisterToSaveRestore.
2773 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2774 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2775 Node->getValueType(0));
2776 Tmp2 = Tmp1.getValue(1);
2778 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2779 Tmp2 = Node->getOperand(0);
2784 // Since stacksave produce two values, make sure to remember that we
2785 // legalized both of them.
2786 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2787 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2788 return Op.getResNo() ? Tmp2 : Tmp1;
2790 case ISD::STACKRESTORE:
2791 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2792 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2793 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2795 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2796 default: assert(0 && "This action is not supported yet!");
2797 case TargetLowering::Legal: break;
2798 case TargetLowering::Custom:
2799 Tmp1 = TLI.LowerOperation(Result, DAG);
2800 if (Tmp1.getNode()) Result = Tmp1;
2802 case TargetLowering::Expand:
2803 // Expand to CopyToReg if the target set
2804 // StackPointerRegisterToSaveRestore.
2805 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2806 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2814 case ISD::READCYCLECOUNTER:
2815 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2816 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2817 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2818 Node->getValueType(0))) {
2819 default: assert(0 && "This action is not supported yet!");
2820 case TargetLowering::Legal:
2821 Tmp1 = Result.getValue(0);
2822 Tmp2 = Result.getValue(1);
2824 case TargetLowering::Custom:
2825 Result = TLI.LowerOperation(Result, DAG);
2826 Tmp1 = LegalizeOp(Result.getValue(0));
2827 Tmp2 = LegalizeOp(Result.getValue(1));
2831 // Since rdcc produce two values, make sure to remember that we legalized
2833 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2834 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2838 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2839 case Expand: assert(0 && "It's impossible to expand bools");
2841 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2844 assert(!Node->getOperand(0).getValueType().isVector() && "not possible");
2845 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2846 // Make sure the condition is either zero or one.
2847 unsigned BitWidth = Tmp1.getValueSizeInBits();
2848 if (!DAG.MaskedValueIsZero(Tmp1,
2849 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2850 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2854 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2855 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2857 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2859 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2860 default: assert(0 && "This action is not supported yet!");
2861 case TargetLowering::Legal: break;
2862 case TargetLowering::Custom: {
2863 Tmp1 = TLI.LowerOperation(Result, DAG);
2864 if (Tmp1.getNode()) Result = Tmp1;
2867 case TargetLowering::Expand:
2868 if (Tmp1.getOpcode() == ISD::SETCC) {
2869 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2871 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2873 Result = DAG.getSelectCC(Tmp1,
2874 DAG.getConstant(0, Tmp1.getValueType()),
2875 Tmp2, Tmp3, ISD::SETNE);
2878 case TargetLowering::Promote: {
2880 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2881 unsigned ExtOp, TruncOp;
2882 if (Tmp2.getValueType().isVector()) {
2883 ExtOp = ISD::BIT_CONVERT;
2884 TruncOp = ISD::BIT_CONVERT;
2885 } else if (Tmp2.getValueType().isInteger()) {
2886 ExtOp = ISD::ANY_EXTEND;
2887 TruncOp = ISD::TRUNCATE;
2889 ExtOp = ISD::FP_EXTEND;
2890 TruncOp = ISD::FP_ROUND;
2892 // Promote each of the values to the new type.
2893 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2894 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2895 // Perform the larger operation, then round down.
2896 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2897 if (TruncOp != ISD::FP_ROUND)
2898 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2900 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2901 DAG.getIntPtrConstant(0));
2906 case ISD::SELECT_CC: {
2907 Tmp1 = Node->getOperand(0); // LHS
2908 Tmp2 = Node->getOperand(1); // RHS
2909 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2910 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2911 SDValue CC = Node->getOperand(4);
2913 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, CC);
2915 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2916 // the LHS is a legal SETCC itself. In this case, we need to compare
2917 // the result against zero to select between true and false values.
2918 if (Tmp2.getNode() == 0) {
2919 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2920 CC = DAG.getCondCode(ISD::SETNE);
2922 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2924 // Everything is legal, see if we should expand this op or something.
2925 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2926 default: assert(0 && "This action is not supported yet!");
2927 case TargetLowering::Legal: break;
2928 case TargetLowering::Custom:
2929 Tmp1 = TLI.LowerOperation(Result, DAG);
2930 if (Tmp1.getNode()) Result = Tmp1;
2936 Tmp1 = Node->getOperand(0);
2937 Tmp2 = Node->getOperand(1);
2938 Tmp3 = Node->getOperand(2);
2939 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3);
2941 // If we had to Expand the SetCC operands into a SELECT node, then it may
2942 // not always be possible to return a true LHS & RHS. In this case, just
2943 // return the value we legalized, returned in the LHS
2944 if (Tmp2.getNode() == 0) {
2949 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2950 default: assert(0 && "Cannot handle this action for SETCC yet!");
2951 case TargetLowering::Custom:
2954 case TargetLowering::Legal:
2955 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2957 Tmp4 = TLI.LowerOperation(Result, DAG);
2958 if (Tmp4.getNode()) Result = Tmp4;
2961 case TargetLowering::Promote: {
2962 // First step, figure out the appropriate operation to use.
2963 // Allow SETCC to not be supported for all legal data types
2964 // Mostly this targets FP
2965 MVT NewInTy = Node->getOperand(0).getValueType();
2966 MVT OldVT = NewInTy; OldVT = OldVT;
2968 // Scan for the appropriate larger type to use.
2970 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
2972 assert(NewInTy.isInteger() == OldVT.isInteger() &&
2973 "Fell off of the edge of the integer world");
2974 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
2975 "Fell off of the edge of the floating point world");
2977 // If the target supports SETCC of this type, use it.
2978 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2981 if (NewInTy.isInteger())
2982 assert(0 && "Cannot promote Legal Integer SETCC yet");
2984 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2985 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2987 Tmp1 = LegalizeOp(Tmp1);
2988 Tmp2 = LegalizeOp(Tmp2);
2989 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2990 Result = LegalizeOp(Result);
2993 case TargetLowering::Expand:
2994 // Expand a setcc node into a select_cc of the same condition, lhs, and
2995 // rhs that selects between const 1 (true) and const 0 (false).
2996 MVT VT = Node->getValueType(0);
2997 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2998 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3004 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3005 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3006 SDValue CC = Node->getOperand(2);
3008 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
3010 // Everything is legal, see if we should expand this op or something.
3011 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
3012 default: assert(0 && "This action is not supported yet!");
3013 case TargetLowering::Legal: break;
3014 case TargetLowering::Custom:
3015 Tmp1 = TLI.LowerOperation(Result, DAG);
3016 if (Tmp1.getNode()) Result = Tmp1;
3022 case ISD::SHL_PARTS:
3023 case ISD::SRA_PARTS:
3024 case ISD::SRL_PARTS: {
3025 SmallVector<SDValue, 8> Ops;
3026 bool Changed = false;
3027 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3028 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3029 Changed |= Ops.back() != Node->getOperand(i);
3032 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
3034 switch (TLI.getOperationAction(Node->getOpcode(),
3035 Node->getValueType(0))) {
3036 default: assert(0 && "This action is not supported yet!");
3037 case TargetLowering::Legal: break;
3038 case TargetLowering::Custom:
3039 Tmp1 = TLI.LowerOperation(Result, DAG);
3040 if (Tmp1.getNode()) {
3041 SDValue Tmp2, RetVal(0, 0);
3042 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
3043 Tmp2 = LegalizeOp(Tmp1.getValue(i));
3044 AddLegalizedOperand(SDValue(Node, i), Tmp2);
3045 if (i == Op.getResNo())
3048 assert(RetVal.getNode() && "Illegal result number");
3054 // Since these produce multiple values, make sure to remember that we
3055 // legalized all of them.
3056 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3057 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
3058 return Result.getValue(Op.getResNo());
3080 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3081 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3082 case Expand: assert(0 && "Not possible");
3084 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3087 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3091 if ((Node->getOpcode() == ISD::SHL ||
3092 Node->getOpcode() == ISD::SRL ||
3093 Node->getOpcode() == ISD::SRA) &&
3094 !Node->getValueType(0).isVector()) {
3095 if (TLI.getShiftAmountTy().bitsLT(Tmp2.getValueType()))
3096 Tmp2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Tmp2);
3097 else if (TLI.getShiftAmountTy().bitsGT(Tmp2.getValueType()))
3098 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Tmp2);
3101 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3103 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3104 default: assert(0 && "BinOp legalize operation not supported");
3105 case TargetLowering::Legal: break;
3106 case TargetLowering::Custom:
3107 Tmp1 = TLI.LowerOperation(Result, DAG);
3108 if (Tmp1.getNode()) {
3112 // Fall through if the custom lower can't deal with the operation
3113 case TargetLowering::Expand: {
3114 MVT VT = Op.getValueType();
3116 // See if multiply or divide can be lowered using two-result operations.
3117 SDVTList VTs = DAG.getVTList(VT, VT);
3118 if (Node->getOpcode() == ISD::MUL) {
3119 // We just need the low half of the multiply; try both the signed
3120 // and unsigned forms. If the target supports both SMUL_LOHI and
3121 // UMUL_LOHI, form a preference by checking which forms of plain
3122 // MULH it supports.
3123 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
3124 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
3125 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
3126 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
3127 unsigned OpToUse = 0;
3128 if (HasSMUL_LOHI && !HasMULHS) {
3129 OpToUse = ISD::SMUL_LOHI;
3130 } else if (HasUMUL_LOHI && !HasMULHU) {
3131 OpToUse = ISD::UMUL_LOHI;
3132 } else if (HasSMUL_LOHI) {
3133 OpToUse = ISD::SMUL_LOHI;
3134 } else if (HasUMUL_LOHI) {
3135 OpToUse = ISD::UMUL_LOHI;
3138 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0);
3142 if (Node->getOpcode() == ISD::MULHS &&
3143 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3144 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3148 if (Node->getOpcode() == ISD::MULHU &&
3149 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3150 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3154 if (Node->getOpcode() == ISD::SDIV &&
3155 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3156 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(),
3160 if (Node->getOpcode() == ISD::UDIV &&
3161 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3162 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(),
3167 // Check to see if we have a libcall for this operator.
3168 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3169 bool isSigned = false;
3170 switch (Node->getOpcode()) {
3173 if (VT == MVT::i32) {
3174 LC = Node->getOpcode() == ISD::UDIV
3175 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3176 isSigned = Node->getOpcode() == ISD::SDIV;
3181 LC = RTLIB::MUL_I32;
3184 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3185 RTLIB::POW_PPCF128);
3189 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3191 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3195 assert(Node->getValueType(0).isVector() &&
3196 "Cannot expand this binary operator!");
3197 // Expand the operation into a bunch of nasty scalar code.
3198 Result = LegalizeOp(UnrollVectorOp(Op));
3201 case TargetLowering::Promote: {
3202 switch (Node->getOpcode()) {
3203 default: assert(0 && "Do not know how to promote this BinOp!");
3207 MVT OVT = Node->getValueType(0);
3208 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3209 assert(OVT.isVector() && "Cannot promote this BinOp!");
3210 // Bit convert each of the values to the new type.
3211 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3212 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3213 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3214 // Bit convert the result back the original type.
3215 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3223 case ISD::SMUL_LOHI:
3224 case ISD::UMUL_LOHI:
3227 // These nodes will only be produced by target-specific lowering, so
3228 // they shouldn't be here if they aren't legal.
3229 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3230 "This must be legal!");
3232 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3233 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3234 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3237 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3238 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3239 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3240 case Expand: assert(0 && "Not possible");
3242 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3245 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3249 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3251 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3252 default: assert(0 && "Operation not supported");
3253 case TargetLowering::Custom:
3254 Tmp1 = TLI.LowerOperation(Result, DAG);
3255 if (Tmp1.getNode()) Result = Tmp1;
3257 case TargetLowering::Legal: break;
3258 case TargetLowering::Expand: {
3259 // If this target supports fabs/fneg natively and select is cheap,
3260 // do this efficiently.
3261 if (!TLI.isSelectExpensive() &&
3262 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3263 TargetLowering::Legal &&
3264 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3265 TargetLowering::Legal) {
3266 // Get the sign bit of the RHS.
3268 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3269 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3270 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3271 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3272 // Get the absolute value of the result.
3273 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3274 // Select between the nabs and abs value based on the sign bit of
3276 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3277 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3280 Result = LegalizeOp(Result);
3284 // Otherwise, do bitwise ops!
3286 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3287 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3288 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3289 Result = LegalizeOp(Result);
3297 Tmp1 = LegalizeOp(Node->getOperand(0));
3298 Tmp2 = LegalizeOp(Node->getOperand(1));
3299 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3300 // Since this produces two values, make sure to remember that we legalized
3302 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
3303 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
3308 Tmp1 = LegalizeOp(Node->getOperand(0));
3309 Tmp2 = LegalizeOp(Node->getOperand(1));
3310 Tmp3 = LegalizeOp(Node->getOperand(2));
3311 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3312 // Since this produces two values, make sure to remember that we legalized
3314 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
3315 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
3318 case ISD::BUILD_PAIR: {
3319 MVT PairTy = Node->getValueType(0);
3320 // TODO: handle the case where the Lo and Hi operands are not of legal type
3321 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3322 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3323 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3324 case TargetLowering::Promote:
3325 case TargetLowering::Custom:
3326 assert(0 && "Cannot promote/custom this yet!");
3327 case TargetLowering::Legal:
3328 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3329 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3331 case TargetLowering::Expand:
3332 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3333 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3334 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3335 DAG.getConstant(PairTy.getSizeInBits()/2,
3336 TLI.getShiftAmountTy()));
3337 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3346 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3347 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3349 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3350 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3351 case TargetLowering::Custom:
3354 case TargetLowering::Legal:
3355 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3357 Tmp1 = TLI.LowerOperation(Result, DAG);
3358 if (Tmp1.getNode()) Result = Tmp1;
3361 case TargetLowering::Expand: {
3362 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3363 bool isSigned = DivOpc == ISD::SDIV;
3364 MVT VT = Node->getValueType(0);
3366 // See if remainder can be lowered using two-result operations.
3367 SDVTList VTs = DAG.getVTList(VT, VT);
3368 if (Node->getOpcode() == ISD::SREM &&
3369 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3370 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3373 if (Node->getOpcode() == ISD::UREM &&
3374 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3375 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3379 if (VT.isInteger()) {
3380 if (TLI.getOperationAction(DivOpc, VT) ==
3381 TargetLowering::Legal) {
3383 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3384 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3385 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3386 } else if (VT.isVector()) {
3387 Result = LegalizeOp(UnrollVectorOp(Op));
3389 assert(VT == MVT::i32 &&
3390 "Cannot expand this binary operator!");
3391 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3392 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3394 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3397 assert(VT.isFloatingPoint() &&
3398 "remainder op must have integer or floating-point type");
3399 if (VT.isVector()) {
3400 Result = LegalizeOp(UnrollVectorOp(Op));
3402 // Floating point mod -> fmod libcall.
3403 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3404 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3406 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3414 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3415 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3417 MVT VT = Node->getValueType(0);
3418 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3419 default: assert(0 && "This action is not supported yet!");
3420 case TargetLowering::Custom:
3423 case TargetLowering::Legal:
3424 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3425 Result = Result.getValue(0);
3426 Tmp1 = Result.getValue(1);
3429 Tmp2 = TLI.LowerOperation(Result, DAG);
3430 if (Tmp2.getNode()) {
3431 Result = LegalizeOp(Tmp2);
3432 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3436 case TargetLowering::Expand: {
3437 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3438 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3439 // Increment the pointer, VAList, to the next vaarg
3440 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3441 DAG.getConstant(TLI.getTargetData()->getABITypeSize(VT.getTypeForMVT()),
3442 TLI.getPointerTy()));
3443 // Store the incremented VAList to the legalized pointer
3444 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3445 // Load the actual argument out of the pointer VAList
3446 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3447 Tmp1 = LegalizeOp(Result.getValue(1));
3448 Result = LegalizeOp(Result);
3452 // Since VAARG produces two values, make sure to remember that we
3453 // legalized both of them.
3454 AddLegalizedOperand(SDValue(Node, 0), Result);
3455 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3456 return Op.getResNo() ? Tmp1 : Result;
3460 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3461 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3462 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3464 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3465 default: assert(0 && "This action is not supported yet!");
3466 case TargetLowering::Custom:
3469 case TargetLowering::Legal:
3470 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3471 Node->getOperand(3), Node->getOperand(4));
3473 Tmp1 = TLI.LowerOperation(Result, DAG);
3474 if (Tmp1.getNode()) Result = Tmp1;
3477 case TargetLowering::Expand:
3478 // This defaults to loading a pointer from the input and storing it to the
3479 // output, returning the chain.
3480 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3481 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3482 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3483 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3489 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3490 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3492 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3493 default: assert(0 && "This action is not supported yet!");
3494 case TargetLowering::Custom:
3497 case TargetLowering::Legal:
3498 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3500 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3501 if (Tmp1.getNode()) Result = Tmp1;
3504 case TargetLowering::Expand:
3505 Result = Tmp1; // Default to a no-op, return the chain
3511 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3512 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3514 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3516 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3517 default: assert(0 && "This action is not supported yet!");
3518 case TargetLowering::Legal: break;
3519 case TargetLowering::Custom:
3520 Tmp1 = TLI.LowerOperation(Result, DAG);
3521 if (Tmp1.getNode()) Result = Tmp1;
3528 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3529 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3530 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3531 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3533 assert(0 && "ROTL/ROTR legalize operation not supported");
3535 case TargetLowering::Legal:
3537 case TargetLowering::Custom:
3538 Tmp1 = TLI.LowerOperation(Result, DAG);
3539 if (Tmp1.getNode()) Result = Tmp1;
3541 case TargetLowering::Promote:
3542 assert(0 && "Do not know how to promote ROTL/ROTR");
3544 case TargetLowering::Expand:
3545 assert(0 && "Do not know how to expand ROTL/ROTR");
3551 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3552 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3553 case TargetLowering::Custom:
3554 assert(0 && "Cannot custom legalize this yet!");
3555 case TargetLowering::Legal:
3556 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3558 case TargetLowering::Promote: {
3559 MVT OVT = Tmp1.getValueType();
3560 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3561 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3563 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3564 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3565 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3566 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3569 case TargetLowering::Expand:
3570 Result = ExpandBSWAP(Tmp1);
3578 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3579 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3580 case TargetLowering::Custom:
3581 case TargetLowering::Legal:
3582 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3583 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3584 TargetLowering::Custom) {
3585 Tmp1 = TLI.LowerOperation(Result, DAG);
3586 if (Tmp1.getNode()) {
3591 case TargetLowering::Promote: {
3592 MVT OVT = Tmp1.getValueType();
3593 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3595 // Zero extend the argument.
3596 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3597 // Perform the larger operation, then subtract if needed.
3598 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3599 switch (Node->getOpcode()) {
3604 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3605 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3606 DAG.getConstant(NVT.getSizeInBits(), NVT),
3608 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3609 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3612 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3613 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3614 DAG.getConstant(NVT.getSizeInBits() -
3615 OVT.getSizeInBits(), NVT));
3620 case TargetLowering::Expand:
3621 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3641 case ISD::FNEARBYINT:
3642 Tmp1 = LegalizeOp(Node->getOperand(0));
3643 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3644 case TargetLowering::Promote:
3645 case TargetLowering::Custom:
3648 case TargetLowering::Legal:
3649 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3651 Tmp1 = TLI.LowerOperation(Result, DAG);
3652 if (Tmp1.getNode()) Result = Tmp1;
3655 case TargetLowering::Expand:
3656 switch (Node->getOpcode()) {
3657 default: assert(0 && "Unreachable!");
3659 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3660 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3661 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3664 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3665 MVT VT = Node->getValueType(0);
3666 Tmp2 = DAG.getConstantFP(0.0, VT);
3667 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3669 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3670 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3685 case ISD::FNEARBYINT: {
3686 MVT VT = Node->getValueType(0);
3688 // Expand unsupported unary vector operators by unrolling them.
3689 if (VT.isVector()) {
3690 Result = LegalizeOp(UnrollVectorOp(Op));
3694 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3695 switch(Node->getOpcode()) {
3697 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3698 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3701 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3702 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3705 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3706 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3709 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3710 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3713 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3714 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3717 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3718 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3721 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3722 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3725 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3726 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3729 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3730 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3733 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3734 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3737 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3738 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3741 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3742 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3744 case ISD::FNEARBYINT:
3745 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3746 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3749 default: assert(0 && "Unreachable!");
3752 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3760 MVT VT = Node->getValueType(0);
3762 // Expand unsupported unary vector operators by unrolling them.
3763 if (VT.isVector()) {
3764 Result = LegalizeOp(UnrollVectorOp(Op));
3768 // We always lower FPOWI into a libcall. No target support for it yet.
3769 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3770 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3772 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3775 case ISD::BIT_CONVERT:
3776 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3777 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3778 Node->getValueType(0));
3779 } else if (Op.getOperand(0).getValueType().isVector()) {
3780 // The input has to be a vector type, we have to either scalarize it, pack
3781 // it, or convert it based on whether the input vector type is legal.
3782 SDNode *InVal = Node->getOperand(0).getNode();
3783 int InIx = Node->getOperand(0).getResNo();
3784 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3785 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3787 // Figure out if there is a simple type corresponding to this Vector
3788 // type. If so, convert to the vector type.
3789 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3790 if (TLI.isTypeLegal(TVT)) {
3791 // Turn this into a bit convert of the vector input.
3792 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3793 LegalizeOp(Node->getOperand(0)));
3795 } else if (NumElems == 1) {
3796 // Turn this into a bit convert of the scalar input.
3797 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3798 ScalarizeVectorOp(Node->getOperand(0)));
3801 // FIXME: UNIMP! Store then reload
3802 assert(0 && "Cast from unsupported vector type not implemented yet!");
3805 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3806 Node->getOperand(0).getValueType())) {
3807 default: assert(0 && "Unknown operation action!");
3808 case TargetLowering::Expand:
3809 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3810 Node->getValueType(0));
3812 case TargetLowering::Legal:
3813 Tmp1 = LegalizeOp(Node->getOperand(0));
3814 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3820 // Conversion operators. The source and destination have different types.
3821 case ISD::SINT_TO_FP:
3822 case ISD::UINT_TO_FP: {
3823 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3824 Result = LegalizeINT_TO_FP(Result, isSigned,
3825 Node->getValueType(0), Node->getOperand(0));
3829 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3831 Tmp1 = LegalizeOp(Node->getOperand(0));
3832 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3835 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3837 // Since the result is legal, we should just be able to truncate the low
3838 // part of the source.
3839 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3842 Result = PromoteOp(Node->getOperand(0));
3843 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3848 case ISD::FP_TO_SINT:
3849 case ISD::FP_TO_UINT:
3850 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3852 Tmp1 = LegalizeOp(Node->getOperand(0));
3854 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3855 default: assert(0 && "Unknown operation action!");
3856 case TargetLowering::Custom:
3859 case TargetLowering::Legal:
3860 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3862 Tmp1 = TLI.LowerOperation(Result, DAG);
3863 if (Tmp1.getNode()) Result = Tmp1;
3866 case TargetLowering::Promote:
3867 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3868 Node->getOpcode() == ISD::FP_TO_SINT);
3870 case TargetLowering::Expand:
3871 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3872 SDValue True, False;
3873 MVT VT = Node->getOperand(0).getValueType();
3874 MVT NVT = Node->getValueType(0);
3875 const uint64_t zero[] = {0, 0};
3876 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
3877 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3878 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3879 Tmp2 = DAG.getConstantFP(apf, VT);
3880 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
3881 Node->getOperand(0), Tmp2, ISD::SETLT);
3882 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3883 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3884 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3886 False = DAG.getNode(ISD::XOR, NVT, False,
3887 DAG.getConstant(x, NVT));
3888 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3891 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3897 MVT VT = Op.getValueType();
3898 MVT OVT = Node->getOperand(0).getValueType();
3899 // Convert ppcf128 to i32
3900 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3901 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3902 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3903 Node->getOperand(0), DAG.getValueType(MVT::f64));
3904 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3905 DAG.getIntPtrConstant(1));
3906 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3908 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3909 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3910 Tmp2 = DAG.getConstantFP(apf, OVT);
3911 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3912 // FIXME: generated code sucks.
3913 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3914 DAG.getNode(ISD::ADD, MVT::i32,
3915 DAG.getNode(ISD::FP_TO_SINT, VT,
3916 DAG.getNode(ISD::FSUB, OVT,
3917 Node->getOperand(0), Tmp2)),
3918 DAG.getConstant(0x80000000, MVT::i32)),
3919 DAG.getNode(ISD::FP_TO_SINT, VT,
3920 Node->getOperand(0)),
3921 DAG.getCondCode(ISD::SETGE));
3925 // Convert f32 / f64 to i32 / i64 / i128.
3926 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
3927 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
3928 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
3930 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3934 Tmp1 = PromoteOp(Node->getOperand(0));
3935 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3936 Result = LegalizeOp(Result);
3941 case ISD::FP_EXTEND: {
3942 MVT DstVT = Op.getValueType();
3943 MVT SrcVT = Op.getOperand(0).getValueType();
3944 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3945 // The only other way we can lower this is to turn it into a STORE,
3946 // LOAD pair, targetting a temporary location (a stack slot).
3947 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3950 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3951 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3953 Tmp1 = LegalizeOp(Node->getOperand(0));
3954 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3957 Tmp1 = PromoteOp(Node->getOperand(0));
3958 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3963 case ISD::FP_ROUND: {
3964 MVT DstVT = Op.getValueType();
3965 MVT SrcVT = Op.getOperand(0).getValueType();
3966 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3967 if (SrcVT == MVT::ppcf128) {
3969 ExpandOp(Node->getOperand(0), Lo, Result);
3970 // Round it the rest of the way (e.g. to f32) if needed.
3971 if (DstVT!=MVT::f64)
3972 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3975 // The only other way we can lower this is to turn it into a STORE,
3976 // LOAD pair, targetting a temporary location (a stack slot).
3977 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3980 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3981 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3983 Tmp1 = LegalizeOp(Node->getOperand(0));
3984 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3987 Tmp1 = PromoteOp(Node->getOperand(0));
3988 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3989 Node->getOperand(1));
3994 case ISD::ANY_EXTEND:
3995 case ISD::ZERO_EXTEND:
3996 case ISD::SIGN_EXTEND:
3997 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3998 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4000 Tmp1 = LegalizeOp(Node->getOperand(0));
4001 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4002 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4003 TargetLowering::Custom) {
4004 Tmp1 = TLI.LowerOperation(Result, DAG);
4005 if (Tmp1.getNode()) Result = Tmp1;
4009 switch (Node->getOpcode()) {
4010 case ISD::ANY_EXTEND:
4011 Tmp1 = PromoteOp(Node->getOperand(0));
4012 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
4014 case ISD::ZERO_EXTEND:
4015 Result = PromoteOp(Node->getOperand(0));
4016 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
4017 Result = DAG.getZeroExtendInReg(Result,
4018 Node->getOperand(0).getValueType());
4020 case ISD::SIGN_EXTEND:
4021 Result = PromoteOp(Node->getOperand(0));
4022 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
4023 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4025 DAG.getValueType(Node->getOperand(0).getValueType()));
4030 case ISD::FP_ROUND_INREG:
4031 case ISD::SIGN_EXTEND_INREG: {
4032 Tmp1 = LegalizeOp(Node->getOperand(0));
4033 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
4035 // If this operation is not supported, convert it to a shl/shr or load/store
4037 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
4038 default: assert(0 && "This action not supported for this op yet!");
4039 case TargetLowering::Legal:
4040 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4042 case TargetLowering::Expand:
4043 // If this is an integer extend and shifts are supported, do that.
4044 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
4045 // NOTE: we could fall back on load/store here too for targets without
4046 // SAR. However, it is doubtful that any exist.
4047 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
4048 ExtraVT.getSizeInBits();
4049 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
4050 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
4051 Node->getOperand(0), ShiftCst);
4052 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
4054 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
4055 // The only way we can lower this is to turn it into a TRUNCSTORE,
4056 // EXTLOAD pair, targetting a temporary location (a stack slot).
4058 // NOTE: there is a choice here between constantly creating new stack
4059 // slots and always reusing the same one. We currently always create
4060 // new ones, as reuse may inhibit scheduling.
4061 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
4062 Node->getValueType(0));
4064 assert(0 && "Unknown op");
4070 case ISD::TRAMPOLINE: {
4072 for (unsigned i = 0; i != 6; ++i)
4073 Ops[i] = LegalizeOp(Node->getOperand(i));
4074 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
4075 // The only option for this node is to custom lower it.
4076 Result = TLI.LowerOperation(Result, DAG);
4077 assert(Result.getNode() && "Should always custom lower!");
4079 // Since trampoline produces two values, make sure to remember that we
4080 // legalized both of them.
4081 Tmp1 = LegalizeOp(Result.getValue(1));
4082 Result = LegalizeOp(Result);
4083 AddLegalizedOperand(SDValue(Node, 0), Result);
4084 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
4085 return Op.getResNo() ? Tmp1 : Result;
4087 case ISD::FLT_ROUNDS_: {
4088 MVT VT = Node->getValueType(0);
4089 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4090 default: assert(0 && "This action not supported for this op yet!");
4091 case TargetLowering::Custom:
4092 Result = TLI.LowerOperation(Op, DAG);
4093 if (Result.getNode()) break;
4095 case TargetLowering::Legal:
4096 // If this operation is not supported, lower it to constant 1
4097 Result = DAG.getConstant(1, VT);
4103 MVT VT = Node->getValueType(0);
4104 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4105 default: assert(0 && "This action not supported for this op yet!");
4106 case TargetLowering::Legal:
4107 Tmp1 = LegalizeOp(Node->getOperand(0));
4108 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4110 case TargetLowering::Custom:
4111 Result = TLI.LowerOperation(Op, DAG);
4112 if (Result.getNode()) break;
4114 case TargetLowering::Expand:
4115 // If this operation is not supported, lower it to 'abort()' call
4116 Tmp1 = LegalizeOp(Node->getOperand(0));
4117 TargetLowering::ArgListTy Args;
4118 std::pair<SDValue,SDValue> CallResult =
4119 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4120 false, false, false, false, CallingConv::C, false,
4121 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4123 Result = CallResult.second;
4130 assert(Result.getValueType() == Op.getValueType() &&
4131 "Bad legalization!");
4133 // Make sure that the generated code is itself legal.
4135 Result = LegalizeOp(Result);
4137 // Note that LegalizeOp may be reentered even from single-use nodes, which
4138 // means that we always must cache transformed nodes.
4139 AddLegalizedOperand(Op, Result);
4143 /// PromoteOp - Given an operation that produces a value in an invalid type,
4144 /// promote it to compute the value into a larger type. The produced value will
4145 /// have the correct bits for the low portion of the register, but no guarantee
4146 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4147 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4148 MVT VT = Op.getValueType();
4149 MVT NVT = TLI.getTypeToTransformTo(VT);
4150 assert(getTypeAction(VT) == Promote &&
4151 "Caller should expand or legalize operands that are not promotable!");
4152 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4153 "Cannot promote to smaller type!");
4155 SDValue Tmp1, Tmp2, Tmp3;
4157 SDNode *Node = Op.getNode();
4159 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4160 if (I != PromotedNodes.end()) return I->second;
4162 switch (Node->getOpcode()) {
4163 case ISD::CopyFromReg:
4164 assert(0 && "CopyFromReg must be legal!");
4167 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4169 assert(0 && "Do not know how to promote this operator!");
4172 Result = DAG.getNode(ISD::UNDEF, NVT);
4176 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4178 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4179 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4181 case ISD::ConstantFP:
4182 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4183 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4187 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
4188 && "SetCC type is not legal??");
4189 Result = DAG.getNode(ISD::SETCC,
4190 TLI.getSetCCResultType(Node->getOperand(0)),
4191 Node->getOperand(0), Node->getOperand(1),
4192 Node->getOperand(2));
4196 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4198 Result = LegalizeOp(Node->getOperand(0));
4199 assert(Result.getValueType().bitsGE(NVT) &&
4200 "This truncation doesn't make sense!");
4201 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4202 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4205 // The truncation is not required, because we don't guarantee anything
4206 // about high bits anyway.
4207 Result = PromoteOp(Node->getOperand(0));
4210 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4211 // Truncate the low part of the expanded value to the result type
4212 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4215 case ISD::SIGN_EXTEND:
4216 case ISD::ZERO_EXTEND:
4217 case ISD::ANY_EXTEND:
4218 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4219 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4221 // Input is legal? Just do extend all the way to the larger type.
4222 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4225 // Promote the reg if it's smaller.
4226 Result = PromoteOp(Node->getOperand(0));
4227 // The high bits are not guaranteed to be anything. Insert an extend.
4228 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4229 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4230 DAG.getValueType(Node->getOperand(0).getValueType()));
4231 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4232 Result = DAG.getZeroExtendInReg(Result,
4233 Node->getOperand(0).getValueType());
4237 case ISD::BIT_CONVERT:
4238 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4239 Node->getValueType(0));
4240 Result = PromoteOp(Result);
4243 case ISD::FP_EXTEND:
4244 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4246 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4247 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4248 case Promote: assert(0 && "Unreachable with 2 FP types!");
4250 if (Node->getConstantOperandVal(1) == 0) {
4251 // Input is legal? Do an FP_ROUND_INREG.
4252 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4253 DAG.getValueType(VT));
4255 // Just remove the truncate, it isn't affecting the value.
4256 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4257 Node->getOperand(1));
4262 case ISD::SINT_TO_FP:
4263 case ISD::UINT_TO_FP:
4264 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4266 // No extra round required here.
4267 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4271 Result = PromoteOp(Node->getOperand(0));
4272 if (Node->getOpcode() == ISD::SINT_TO_FP)
4273 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4275 DAG.getValueType(Node->getOperand(0).getValueType()));
4277 Result = DAG.getZeroExtendInReg(Result,
4278 Node->getOperand(0).getValueType());
4279 // No extra round required here.
4280 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4283 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4284 Node->getOperand(0));
4285 // Round if we cannot tolerate excess precision.
4286 if (NoExcessFPPrecision)
4287 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4288 DAG.getValueType(VT));
4293 case ISD::SIGN_EXTEND_INREG:
4294 Result = PromoteOp(Node->getOperand(0));
4295 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4296 Node->getOperand(1));
4298 case ISD::FP_TO_SINT:
4299 case ISD::FP_TO_UINT:
4300 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4303 Tmp1 = Node->getOperand(0);
4306 // The input result is prerounded, so we don't have to do anything
4308 Tmp1 = PromoteOp(Node->getOperand(0));
4311 // If we're promoting a UINT to a larger size, check to see if the new node
4312 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4313 // we can use that instead. This allows us to generate better code for
4314 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4315 // legal, such as PowerPC.
4316 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4317 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4318 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4319 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4320 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4322 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4328 Tmp1 = PromoteOp(Node->getOperand(0));
4329 assert(Tmp1.getValueType() == NVT);
4330 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4331 // NOTE: we do not have to do any extra rounding here for
4332 // NoExcessFPPrecision, because we know the input will have the appropriate
4333 // precision, and these operations don't modify precision at all.
4348 case ISD::FNEARBYINT:
4349 Tmp1 = PromoteOp(Node->getOperand(0));
4350 assert(Tmp1.getValueType() == NVT);
4351 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4352 if (NoExcessFPPrecision)
4353 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4354 DAG.getValueType(VT));
4359 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4360 // directly as well, which may be better.
4361 Tmp1 = PromoteOp(Node->getOperand(0));
4362 Tmp2 = Node->getOperand(1);
4363 if (Node->getOpcode() == ISD::FPOW)
4364 Tmp2 = PromoteOp(Tmp2);
4365 assert(Tmp1.getValueType() == NVT);
4366 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4367 if (NoExcessFPPrecision)
4368 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4369 DAG.getValueType(VT));
4373 case ISD::ATOMIC_CMP_SWAP_8:
4374 case ISD::ATOMIC_CMP_SWAP_16:
4375 case ISD::ATOMIC_CMP_SWAP_32:
4376 case ISD::ATOMIC_CMP_SWAP_64: {
4377 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4378 Tmp2 = PromoteOp(Node->getOperand(2));
4379 Tmp3 = PromoteOp(Node->getOperand(3));
4380 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4381 AtomNode->getBasePtr(), Tmp2, Tmp3,
4382 AtomNode->getSrcValue(),
4383 AtomNode->getAlignment());
4384 // Remember that we legalized the chain.
4385 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4388 case ISD::ATOMIC_LOAD_ADD_8:
4389 case ISD::ATOMIC_LOAD_SUB_8:
4390 case ISD::ATOMIC_LOAD_AND_8:
4391 case ISD::ATOMIC_LOAD_OR_8:
4392 case ISD::ATOMIC_LOAD_XOR_8:
4393 case ISD::ATOMIC_LOAD_NAND_8:
4394 case ISD::ATOMIC_LOAD_MIN_8:
4395 case ISD::ATOMIC_LOAD_MAX_8:
4396 case ISD::ATOMIC_LOAD_UMIN_8:
4397 case ISD::ATOMIC_LOAD_UMAX_8:
4398 case ISD::ATOMIC_SWAP_8:
4399 case ISD::ATOMIC_LOAD_ADD_16:
4400 case ISD::ATOMIC_LOAD_SUB_16:
4401 case ISD::ATOMIC_LOAD_AND_16:
4402 case ISD::ATOMIC_LOAD_OR_16:
4403 case ISD::ATOMIC_LOAD_XOR_16:
4404 case ISD::ATOMIC_LOAD_NAND_16:
4405 case ISD::ATOMIC_LOAD_MIN_16:
4406 case ISD::ATOMIC_LOAD_MAX_16:
4407 case ISD::ATOMIC_LOAD_UMIN_16:
4408 case ISD::ATOMIC_LOAD_UMAX_16:
4409 case ISD::ATOMIC_SWAP_16:
4410 case ISD::ATOMIC_LOAD_ADD_32:
4411 case ISD::ATOMIC_LOAD_SUB_32:
4412 case ISD::ATOMIC_LOAD_AND_32:
4413 case ISD::ATOMIC_LOAD_OR_32:
4414 case ISD::ATOMIC_LOAD_XOR_32:
4415 case ISD::ATOMIC_LOAD_NAND_32:
4416 case ISD::ATOMIC_LOAD_MIN_32:
4417 case ISD::ATOMIC_LOAD_MAX_32:
4418 case ISD::ATOMIC_LOAD_UMIN_32:
4419 case ISD::ATOMIC_LOAD_UMAX_32:
4420 case ISD::ATOMIC_SWAP_32:
4421 case ISD::ATOMIC_LOAD_ADD_64:
4422 case ISD::ATOMIC_LOAD_SUB_64:
4423 case ISD::ATOMIC_LOAD_AND_64:
4424 case ISD::ATOMIC_LOAD_OR_64:
4425 case ISD::ATOMIC_LOAD_XOR_64:
4426 case ISD::ATOMIC_LOAD_NAND_64:
4427 case ISD::ATOMIC_LOAD_MIN_64:
4428 case ISD::ATOMIC_LOAD_MAX_64:
4429 case ISD::ATOMIC_LOAD_UMIN_64:
4430 case ISD::ATOMIC_LOAD_UMAX_64:
4431 case ISD::ATOMIC_SWAP_64: {
4432 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4433 Tmp2 = PromoteOp(Node->getOperand(2));
4434 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4435 AtomNode->getBasePtr(), Tmp2,
4436 AtomNode->getSrcValue(),
4437 AtomNode->getAlignment());
4438 // Remember that we legalized the chain.
4439 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4449 // The input may have strange things in the top bits of the registers, but
4450 // these operations don't care. They may have weird bits going out, but
4451 // that too is okay if they are integer operations.
4452 Tmp1 = PromoteOp(Node->getOperand(0));
4453 Tmp2 = PromoteOp(Node->getOperand(1));
4454 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4455 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4460 Tmp1 = PromoteOp(Node->getOperand(0));
4461 Tmp2 = PromoteOp(Node->getOperand(1));
4462 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4463 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4465 // Floating point operations will give excess precision that we may not be
4466 // able to tolerate. If we DO allow excess precision, just leave it,
4467 // otherwise excise it.
4468 // FIXME: Why would we need to round FP ops more than integer ones?
4469 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4470 if (NoExcessFPPrecision)
4471 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4472 DAG.getValueType(VT));
4477 // These operators require that their input be sign extended.
4478 Tmp1 = PromoteOp(Node->getOperand(0));
4479 Tmp2 = PromoteOp(Node->getOperand(1));
4480 if (NVT.isInteger()) {
4481 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4482 DAG.getValueType(VT));
4483 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4484 DAG.getValueType(VT));
4486 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4488 // Perform FP_ROUND: this is probably overly pessimistic.
4489 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4490 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4491 DAG.getValueType(VT));
4495 case ISD::FCOPYSIGN:
4496 // These operators require that their input be fp extended.
4497 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4498 case Expand: assert(0 && "not implemented");
4499 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4500 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4502 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4503 case Expand: assert(0 && "not implemented");
4504 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4505 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4507 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4509 // Perform FP_ROUND: this is probably overly pessimistic.
4510 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4511 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4512 DAG.getValueType(VT));
4517 // These operators require that their input be zero extended.
4518 Tmp1 = PromoteOp(Node->getOperand(0));
4519 Tmp2 = PromoteOp(Node->getOperand(1));
4520 assert(NVT.isInteger() && "Operators don't apply to FP!");
4521 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4522 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4523 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4527 Tmp1 = PromoteOp(Node->getOperand(0));
4528 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4531 // The input value must be properly sign extended.
4532 Tmp1 = PromoteOp(Node->getOperand(0));
4533 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4534 DAG.getValueType(VT));
4535 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4538 // The input value must be properly zero extended.
4539 Tmp1 = PromoteOp(Node->getOperand(0));
4540 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4541 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4545 Tmp1 = Node->getOperand(0); // Get the chain.
4546 Tmp2 = Node->getOperand(1); // Get the pointer.
4547 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4548 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4549 Result = TLI.LowerOperation(Tmp3, DAG);
4551 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4552 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4553 // Increment the pointer, VAList, to the next vaarg
4554 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4555 DAG.getConstant(VT.getSizeInBits()/8,
4556 TLI.getPointerTy()));
4557 // Store the incremented VAList to the legalized pointer
4558 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4559 // Load the actual argument out of the pointer VAList
4560 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4562 // Remember that we legalized the chain.
4563 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4567 LoadSDNode *LD = cast<LoadSDNode>(Node);
4568 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4569 ? ISD::EXTLOAD : LD->getExtensionType();
4570 Result = DAG.getExtLoad(ExtType, NVT,
4571 LD->getChain(), LD->getBasePtr(),
4572 LD->getSrcValue(), LD->getSrcValueOffset(),
4575 LD->getAlignment());
4576 // Remember that we legalized the chain.
4577 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4581 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4582 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4584 MVT VT2 = Tmp2.getValueType();
4585 assert(VT2 == Tmp3.getValueType()
4586 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4587 // Ensure that the resulting node is at least the same size as the operands'
4588 // value types, because we cannot assume that TLI.getSetCCValueType() is
4590 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4593 case ISD::SELECT_CC:
4594 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4595 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4596 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4597 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4600 Tmp1 = Node->getOperand(0);
4601 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4602 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4603 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4604 DAG.getConstant(NVT.getSizeInBits() -
4606 TLI.getShiftAmountTy()));
4611 // Zero extend the argument
4612 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4613 // Perform the larger operation, then subtract if needed.
4614 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4615 switch(Node->getOpcode()) {
4620 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4621 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4622 DAG.getConstant(NVT.getSizeInBits(), NVT),
4624 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4625 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4628 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4629 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4630 DAG.getConstant(NVT.getSizeInBits() -
4631 VT.getSizeInBits(), NVT));
4635 case ISD::EXTRACT_SUBVECTOR:
4636 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4638 case ISD::EXTRACT_VECTOR_ELT:
4639 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4643 assert(Result.getNode() && "Didn't set a result!");
4645 // Make sure the result is itself legal.
4646 Result = LegalizeOp(Result);
4648 // Remember that we promoted this!
4649 AddPromotedOperand(Op, Result);
4653 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4654 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4655 /// based on the vector type. The return type of this matches the element type
4656 /// of the vector, which may not be legal for the target.
4657 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
4658 // We know that operand #0 is the Vec vector. If the index is a constant
4659 // or if the invec is a supported hardware type, we can use it. Otherwise,
4660 // lower to a store then an indexed load.
4661 SDValue Vec = Op.getOperand(0);
4662 SDValue Idx = Op.getOperand(1);
4664 MVT TVT = Vec.getValueType();
4665 unsigned NumElems = TVT.getVectorNumElements();
4667 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4668 default: assert(0 && "This action is not supported yet!");
4669 case TargetLowering::Custom: {
4670 Vec = LegalizeOp(Vec);
4671 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4672 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
4677 case TargetLowering::Legal:
4678 if (isTypeLegal(TVT)) {
4679 Vec = LegalizeOp(Vec);
4680 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4684 case TargetLowering::Promote:
4685 assert(TVT.isVector() && "not vector type");
4686 // fall thru to expand since vectors are by default are promote
4687 case TargetLowering::Expand:
4691 if (NumElems == 1) {
4692 // This must be an access of the only element. Return it.
4693 Op = ScalarizeVectorOp(Vec);
4694 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4695 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4696 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4698 SplitVectorOp(Vec, Lo, Hi);
4699 if (CIdx->getZExtValue() < NumLoElts) {
4703 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
4704 Idx.getValueType());
4707 // It's now an extract from the appropriate high or low part. Recurse.
4708 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4709 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4711 // Store the value to a temporary stack slot, then LOAD the scalar
4712 // element back out.
4713 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4714 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4716 // Add the offset to the index.
4717 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
4718 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4719 DAG.getConstant(EltSize, Idx.getValueType()));
4721 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
4722 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4724 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4726 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4728 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4733 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4734 /// we assume the operation can be split if it is not already legal.
4735 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
4736 // We know that operand #0 is the Vec vector. For now we assume the index
4737 // is a constant and that the extracted result is a supported hardware type.
4738 SDValue Vec = Op.getOperand(0);
4739 SDValue Idx = LegalizeOp(Op.getOperand(1));
4741 unsigned NumElems = Vec.getValueType().getVectorNumElements();
4743 if (NumElems == Op.getValueType().getVectorNumElements()) {
4744 // This must be an access of the desired vector length. Return it.
4748 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4750 SplitVectorOp(Vec, Lo, Hi);
4751 if (CIdx->getZExtValue() < NumElems/2) {
4755 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
4756 Idx.getValueType());
4759 // It's now an extract from the appropriate high or low part. Recurse.
4760 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4761 return ExpandEXTRACT_SUBVECTOR(Op);
4764 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4765 /// with condition CC on the current target. This usually involves legalizing
4766 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4767 /// there may be no choice but to create a new SetCC node to represent the
4768 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4769 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
4770 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
4773 SDValue Tmp1, Tmp2, Tmp3, Result;
4775 switch (getTypeAction(LHS.getValueType())) {
4777 Tmp1 = LegalizeOp(LHS); // LHS
4778 Tmp2 = LegalizeOp(RHS); // RHS
4781 Tmp1 = PromoteOp(LHS); // LHS
4782 Tmp2 = PromoteOp(RHS); // RHS
4784 // If this is an FP compare, the operands have already been extended.
4785 if (LHS.getValueType().isInteger()) {
4786 MVT VT = LHS.getValueType();
4787 MVT NVT = TLI.getTypeToTransformTo(VT);
4789 // Otherwise, we have to insert explicit sign or zero extends. Note
4790 // that we could insert sign extends for ALL conditions, but zero extend
4791 // is cheaper on many machines (an AND instead of two shifts), so prefer
4793 switch (cast<CondCodeSDNode>(CC)->get()) {
4794 default: assert(0 && "Unknown integer comparison!");
4801 // ALL of these operations will work if we either sign or zero extend
4802 // the operands (including the unsigned comparisons!). Zero extend is
4803 // usually a simpler/cheaper operation, so prefer it.
4804 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4805 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4811 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4812 DAG.getValueType(VT));
4813 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4814 DAG.getValueType(VT));
4815 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
4816 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
4822 MVT VT = LHS.getValueType();
4823 if (VT == MVT::f32 || VT == MVT::f64) {
4824 // Expand into one or more soft-fp libcall(s).
4825 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
4826 switch (cast<CondCodeSDNode>(CC)->get()) {
4829 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4833 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4837 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4841 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4845 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4849 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4852 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4855 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4858 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4859 switch (cast<CondCodeSDNode>(CC)->get()) {
4861 // SETONE = SETOLT | SETOGT
4862 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4865 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4868 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4871 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4874 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4877 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4879 default: assert(0 && "Unsupported FP setcc!");
4884 SDValue Ops[2] = { LHS, RHS };
4885 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(),
4886 false /*sign irrelevant*/, Dummy);
4887 Tmp2 = DAG.getConstant(0, MVT::i32);
4888 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4889 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4890 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
4892 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(),
4893 false /*sign irrelevant*/, Dummy);
4894 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
4895 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4896 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4899 LHS = LegalizeOp(Tmp1);
4904 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
4905 ExpandOp(LHS, LHSLo, LHSHi);
4906 ExpandOp(RHS, RHSLo, RHSHi);
4907 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4909 if (VT==MVT::ppcf128) {
4910 // FIXME: This generated code sucks. We want to generate
4911 // FCMPU crN, hi1, hi2
4913 // FCMPU crN, lo1, lo2
4914 // The following can be improved, but not that much.
4915 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4917 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
4918 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4919 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4921 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
4922 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4923 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4932 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4933 if (RHSCST->isAllOnesValue()) {
4934 // Comparison to -1.
4935 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4940 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4941 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4942 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4943 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4946 // If this is a comparison of the sign bit, just look at the top part.
4948 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4949 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4950 CST->isNullValue()) || // X < 0
4951 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4952 CST->isAllOnesValue())) { // X > -1
4958 // FIXME: This generated code sucks.
4959 ISD::CondCode LowCC;
4961 default: assert(0 && "Unknown integer setcc!");
4963 case ISD::SETULT: LowCC = ISD::SETULT; break;
4965 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4967 case ISD::SETULE: LowCC = ISD::SETULE; break;
4969 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4972 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4973 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4974 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4976 // NOTE: on targets without efficient SELECT of bools, we can always use
4977 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4978 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4979 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
4980 LowCC, false, DagCombineInfo);
4981 if (!Tmp1.getNode())
4982 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
4983 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4984 CCCode, false, DagCombineInfo);
4985 if (!Tmp2.getNode())
4986 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
4989 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
4990 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
4991 if ((Tmp1C && Tmp1C->isNullValue()) ||
4992 (Tmp2C && Tmp2C->isNullValue() &&
4993 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4994 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4995 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
4996 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4997 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4998 // low part is known false, returns high part.
4999 // For LE / GE, if high part is known false, ignore the low part.
5000 // For LT / GT, if high part is known true, ignore the low part.
5004 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5005 ISD::SETEQ, false, DagCombineInfo);
5006 if (!Result.getNode())
5007 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5009 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
5010 Result, Tmp1, Tmp2));
5021 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
5022 /// condition code CC on the current target. This routine assumes LHS and rHS
5023 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
5024 /// illegal condition code into AND / OR of multiple SETCC values.
5025 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
5026 SDValue &LHS, SDValue &RHS,
5028 MVT OpVT = LHS.getValueType();
5029 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5030 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
5031 default: assert(0 && "Unknown condition code action!");
5032 case TargetLowering::Legal:
5035 case TargetLowering::Expand: {
5036 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
5039 default: assert(0 && "Don't know how to expand this condition!"); abort();
5040 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
5041 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5042 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5043 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5044 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5045 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5046 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5047 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5048 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5049 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5050 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5051 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5052 // FIXME: Implement more expansions.
5055 SDValue SetCC1 = DAG.getSetCC(VT, LHS, RHS, CC1);
5056 SDValue SetCC2 = DAG.getSetCC(VT, LHS, RHS, CC2);
5057 LHS = DAG.getNode(Opc, VT, SetCC1, SetCC2);
5065 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
5066 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
5067 /// a load from the stack slot to DestVT, extending it if needed.
5068 /// The resultant code need not be legal.
5069 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
5072 // Create the stack frame object.
5073 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
5074 SrcOp.getValueType().getTypeForMVT());
5075 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
5077 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
5078 int SPFI = StackPtrFI->getIndex();
5080 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
5081 unsigned SlotSize = SlotVT.getSizeInBits();
5082 unsigned DestSize = DestVT.getSizeInBits();
5083 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
5084 DestVT.getTypeForMVT());
5086 // Emit a store to the stack slot. Use a truncstore if the input value is
5087 // later than DestVT.
5090 if (SrcSize > SlotSize)
5091 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
5092 PseudoSourceValue::getFixedStack(SPFI), 0,
5093 SlotVT, false, SrcAlign);
5095 assert(SrcSize == SlotSize && "Invalid store");
5096 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
5097 PseudoSourceValue::getFixedStack(SPFI), 0,
5101 // Result is a load from the stack slot.
5102 if (SlotSize == DestSize)
5103 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
5105 assert(SlotSize < DestSize && "Unknown extension!");
5106 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
5110 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
5111 // Create a vector sized/aligned stack slot, store the value to element #0,
5112 // then load the whole vector back out.
5113 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
5115 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
5116 int SPFI = StackPtrFI->getIndex();
5118 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
5119 PseudoSourceValue::getFixedStack(SPFI), 0);
5120 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
5121 PseudoSourceValue::getFixedStack(SPFI), 0);
5125 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
5126 /// support the operation, but do support the resultant vector type.
5127 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
5129 // If the only non-undef value is the low element, turn this into a
5130 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
5131 unsigned NumElems = Node->getNumOperands();
5132 bool isOnlyLowElement = true;
5133 SDValue SplatValue = Node->getOperand(0);
5135 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
5136 // and use a bitmask instead of a list of elements.
5137 std::map<SDValue, std::vector<unsigned> > Values;
5138 Values[SplatValue].push_back(0);
5139 bool isConstant = true;
5140 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
5141 SplatValue.getOpcode() != ISD::UNDEF)
5144 for (unsigned i = 1; i < NumElems; ++i) {
5145 SDValue V = Node->getOperand(i);
5146 Values[V].push_back(i);
5147 if (V.getOpcode() != ISD::UNDEF)
5148 isOnlyLowElement = false;
5149 if (SplatValue != V)
5150 SplatValue = SDValue(0,0);
5152 // If this isn't a constant element or an undef, we can't use a constant
5154 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
5155 V.getOpcode() != ISD::UNDEF)
5159 if (isOnlyLowElement) {
5160 // If the low element is an undef too, then this whole things is an undef.
5161 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
5162 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
5163 // Otherwise, turn this into a scalar_to_vector node.
5164 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
5165 Node->getOperand(0));
5168 // If all elements are constants, create a load from the constant pool.
5170 MVT VT = Node->getValueType(0);
5171 std::vector<Constant*> CV;
5172 for (unsigned i = 0, e = NumElems; i != e; ++i) {
5173 if (ConstantFPSDNode *V =
5174 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
5175 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
5176 } else if (ConstantSDNode *V =
5177 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
5178 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
5180 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
5182 Node->getOperand(0).getValueType().getTypeForMVT();
5183 CV.push_back(UndefValue::get(OpNTy));
5186 Constant *CP = ConstantVector::get(CV);
5187 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5188 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5189 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
5190 PseudoSourceValue::getConstantPool(), 0,
5194 if (SplatValue.getNode()) { // Splat of one value?
5195 // Build the shuffle constant vector: <0, 0, 0, 0>
5196 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5197 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5198 std::vector<SDValue> ZeroVec(NumElems, Zero);
5199 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5200 &ZeroVec[0], ZeroVec.size());
5202 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5203 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5204 // Get the splatted value into the low element of a vector register.
5206 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
5208 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5209 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
5210 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
5215 // If there are only two unique elements, we may be able to turn this into a
5217 if (Values.size() == 2) {
5218 // Get the two values in deterministic order.
5219 SDValue Val1 = Node->getOperand(1);
5221 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5222 if (MI->first != Val1)
5225 Val2 = (++MI)->first;
5227 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5228 // vector shuffle has the undef vector on the RHS.
5229 if (Val1.getOpcode() == ISD::UNDEF)
5230 std::swap(Val1, Val2);
5232 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5233 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5234 MVT MaskEltVT = MaskVT.getVectorElementType();
5235 std::vector<SDValue> MaskVec(NumElems);
5237 // Set elements of the shuffle mask for Val1.
5238 std::vector<unsigned> &Val1Elts = Values[Val1];
5239 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5240 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5242 // Set elements of the shuffle mask for Val2.
5243 std::vector<unsigned> &Val2Elts = Values[Val2];
5244 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5245 if (Val2.getOpcode() != ISD::UNDEF)
5246 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5248 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
5250 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5251 &MaskVec[0], MaskVec.size());
5253 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5254 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5255 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5256 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
5257 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
5258 SDValue Ops[] = { Val1, Val2, ShuffleMask };
5260 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5261 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5265 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5266 // aligned object on the stack, store each element into it, then load
5267 // the result as a vector.
5268 MVT VT = Node->getValueType(0);
5269 // Create the stack frame object.
5270 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5272 // Emit a store of each element to the stack slot.
5273 SmallVector<SDValue, 8> Stores;
5274 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5275 // Store (in the right endianness) the elements to memory.
5276 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5277 // Ignore undef elements.
5278 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5280 unsigned Offset = TypeByteSize*i;
5282 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5283 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5285 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5290 if (!Stores.empty()) // Not all undef elements?
5291 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5292 &Stores[0], Stores.size());
5294 StoreChain = DAG.getEntryNode();
5296 // Result is a load from the stack slot.
5297 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5300 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5301 SDValue Op, SDValue Amt,
5302 SDValue &Lo, SDValue &Hi) {
5303 // Expand the subcomponents.
5305 ExpandOp(Op, LHSL, LHSH);
5307 SDValue Ops[] = { LHSL, LHSH, Amt };
5308 MVT VT = LHSL.getValueType();
5309 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5310 Hi = Lo.getValue(1);
5314 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5315 /// smaller elements. If we can't find a way that is more efficient than a
5316 /// libcall on this target, return false. Otherwise, return true with the
5317 /// low-parts expanded into Lo and Hi.
5318 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5319 SDValue &Lo, SDValue &Hi) {
5320 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5321 "This is not a shift!");
5323 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5324 SDValue ShAmt = LegalizeOp(Amt);
5325 MVT ShTy = ShAmt.getValueType();
5326 unsigned ShBits = ShTy.getSizeInBits();
5327 unsigned VTBits = Op.getValueType().getSizeInBits();
5328 unsigned NVTBits = NVT.getSizeInBits();
5330 // Handle the case when Amt is an immediate.
5331 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5332 unsigned Cst = CN->getZExtValue();
5333 // Expand the incoming operand to be shifted, so that we have its parts
5335 ExpandOp(Op, InL, InH);
5339 Lo = DAG.getConstant(0, NVT);
5340 Hi = DAG.getConstant(0, NVT);
5341 } else if (Cst > NVTBits) {
5342 Lo = DAG.getConstant(0, NVT);
5343 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5344 } else if (Cst == NVTBits) {
5345 Lo = DAG.getConstant(0, NVT);
5348 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5349 Hi = DAG.getNode(ISD::OR, NVT,
5350 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5351 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5356 Lo = DAG.getConstant(0, NVT);
5357 Hi = DAG.getConstant(0, NVT);
5358 } else if (Cst > NVTBits) {
5359 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5360 Hi = DAG.getConstant(0, NVT);
5361 } else if (Cst == NVTBits) {
5363 Hi = DAG.getConstant(0, NVT);
5365 Lo = DAG.getNode(ISD::OR, NVT,
5366 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5367 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5368 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5373 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5374 DAG.getConstant(NVTBits-1, ShTy));
5375 } else if (Cst > NVTBits) {
5376 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5377 DAG.getConstant(Cst-NVTBits, ShTy));
5378 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5379 DAG.getConstant(NVTBits-1, ShTy));
5380 } else if (Cst == NVTBits) {
5382 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5383 DAG.getConstant(NVTBits-1, ShTy));
5385 Lo = DAG.getNode(ISD::OR, NVT,
5386 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5387 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5388 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5394 // Okay, the shift amount isn't constant. However, if we can tell that it is
5395 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5396 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5397 APInt KnownZero, KnownOne;
5398 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5400 // If we know that if any of the high bits of the shift amount are one, then
5401 // we can do this as a couple of simple shifts.
5402 if (KnownOne.intersects(Mask)) {
5403 // Mask out the high bit, which we know is set.
5404 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5405 DAG.getConstant(~Mask, Amt.getValueType()));
5407 // Expand the incoming operand to be shifted, so that we have its parts
5409 ExpandOp(Op, InL, InH);
5412 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5413 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5416 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5417 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5420 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5421 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5422 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5427 // If we know that the high bits of the shift amount are all zero, then we can
5428 // do this as a couple of simple shifts.
5429 if ((KnownZero & Mask) == Mask) {
5431 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5432 DAG.getConstant(NVTBits, Amt.getValueType()),
5435 // Expand the incoming operand to be shifted, so that we have its parts
5437 ExpandOp(Op, InL, InH);
5440 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5441 Hi = DAG.getNode(ISD::OR, NVT,
5442 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5443 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5446 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5447 Lo = DAG.getNode(ISD::OR, NVT,
5448 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5449 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5452 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5453 Lo = DAG.getNode(ISD::OR, NVT,
5454 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5455 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5464 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5465 // does not fit into a register, return the lo part and set the hi part to the
5466 // by-reg argument. If it does fit into a single register, return the result
5467 // and leave the Hi part unset.
5468 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5469 bool isSigned, SDValue &Hi) {
5470 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5471 // The input chain to this libcall is the entry node of the function.
5472 // Legalizing the call will automatically add the previous call to the
5474 SDValue InChain = DAG.getEntryNode();
5476 TargetLowering::ArgListTy Args;
5477 TargetLowering::ArgListEntry Entry;
5478 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5479 MVT ArgVT = Node->getOperand(i).getValueType();
5480 const Type *ArgTy = ArgVT.getTypeForMVT();
5481 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5482 Entry.isSExt = isSigned;
5483 Entry.isZExt = !isSigned;
5484 Args.push_back(Entry);
5486 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5487 TLI.getPointerTy());
5489 // Splice the libcall in wherever FindInputOutputChains tells us to.
5490 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5491 std::pair<SDValue,SDValue> CallInfo =
5492 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5493 CallingConv::C, false, Callee, Args, DAG);
5495 // Legalize the call sequence, starting with the chain. This will advance
5496 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5497 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5498 LegalizeOp(CallInfo.second);
5500 switch (getTypeAction(CallInfo.first.getValueType())) {
5501 default: assert(0 && "Unknown thing");
5503 Result = CallInfo.first;
5506 ExpandOp(CallInfo.first, Result, Hi);
5512 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5514 SDValue SelectionDAGLegalize::
5515 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) {
5516 bool isCustom = false;
5518 switch (getTypeAction(Op.getValueType())) {
5520 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5521 Op.getValueType())) {
5522 default: assert(0 && "Unknown operation action!");
5523 case TargetLowering::Custom:
5526 case TargetLowering::Legal:
5527 Tmp1 = LegalizeOp(Op);
5528 if (Result.getNode())
5529 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5531 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5534 Tmp1 = TLI.LowerOperation(Result, DAG);
5535 if (Tmp1.getNode()) Result = Tmp1;
5538 case TargetLowering::Expand:
5539 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy);
5541 case TargetLowering::Promote:
5542 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned);
5547 Result = ExpandIntToFP(isSigned, DestTy, Op);
5550 Tmp1 = PromoteOp(Op);
5552 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
5553 Tmp1, DAG.getValueType(Op.getValueType()));
5555 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
5558 if (Result.getNode())
5559 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5561 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5563 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5569 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5571 SDValue SelectionDAGLegalize::
5572 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
5573 MVT SourceVT = Source.getValueType();
5574 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5576 // Expand unsupported int-to-fp vector casts by unrolling them.
5577 if (DestTy.isVector()) {
5579 return LegalizeOp(UnrollVectorOp(Source));
5580 MVT DestEltTy = DestTy.getVectorElementType();
5581 if (DestTy.getVectorNumElements() == 1) {
5582 SDValue Scalar = ScalarizeVectorOp(Source);
5583 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5585 return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result);
5588 SplitVectorOp(Source, Lo, Hi);
5589 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5590 DestTy.getVectorNumElements() / 2);
5591 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo);
5592 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi);
5593 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult,
5597 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5598 if (!isSigned && SourceVT != MVT::i32) {
5599 // The integer value loaded will be incorrectly if the 'sign bit' of the
5600 // incoming integer is set. To handle this, we dynamically test to see if
5601 // it is set, and, if so, add a fudge factor.
5605 ExpandOp(Source, Lo, Hi);
5606 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5608 // The comparison for the sign bit will use the entire operand.
5612 // Check to see if the target has a custom way to lower this. If so, use
5613 // it. (Note we've already expanded the operand in this case.)
5614 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) {
5615 default: assert(0 && "This action not implemented for this operation!");
5616 case TargetLowering::Legal:
5617 case TargetLowering::Expand:
5618 break; // This case is handled below.
5619 case TargetLowering::Custom: {
5620 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, DestTy,
5623 return LegalizeOp(NV);
5624 break; // The target decided this was legal after all
5628 // If this is unsigned, and not supported, first perform the conversion to
5629 // signed, then adjust the result if the sign bit is set.
5630 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
5632 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5633 DAG.getConstant(0, Hi.getValueType()),
5635 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5636 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5637 SignSet, Four, Zero);
5638 uint64_t FF = 0x5f800000ULL;
5639 if (TLI.isLittleEndian()) FF <<= 32;
5640 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5642 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5643 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5644 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5645 Alignment = std::min(Alignment, 4u);
5647 if (DestTy == MVT::f32)
5648 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5649 PseudoSourceValue::getConstantPool(), 0,
5651 else if (DestTy.bitsGT(MVT::f32))
5652 // FIXME: Avoid the extend by construction the right constantpool?
5653 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5655 PseudoSourceValue::getConstantPool(), 0,
5656 MVT::f32, false, Alignment);
5658 assert(0 && "Unexpected conversion");
5660 MVT SCVT = SignedConv.getValueType();
5661 if (SCVT != DestTy) {
5662 // Destination type needs to be expanded as well. The FADD now we are
5663 // constructing will be expanded into a libcall.
5664 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5665 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5666 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5667 SignedConv, SignedConv.getValue(1));
5669 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5671 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5674 // Check to see if the target has a custom way to lower this. If so, use it.
5675 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5676 default: assert(0 && "This action not implemented for this operation!");
5677 case TargetLowering::Legal:
5678 case TargetLowering::Expand:
5679 break; // This case is handled below.
5680 case TargetLowering::Custom: {
5681 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5684 return LegalizeOp(NV);
5685 break; // The target decided this was legal after all
5689 // Expand the source, then glue it back together for the call. We must expand
5690 // the source in case it is shared (this pass of legalize must traverse it).
5692 SDValue SrcLo, SrcHi;
5693 ExpandOp(Source, SrcLo, SrcHi);
5694 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5697 RTLIB::Libcall LC = isSigned ?
5698 RTLIB::getSINTTOFP(SourceVT, DestTy) :
5699 RTLIB::getUINTTOFP(SourceVT, DestTy);
5700 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
5702 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5704 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
5705 if (Result.getValueType() != DestTy && HiPart.getNode())
5706 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5710 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5711 /// INT_TO_FP operation of the specified operand when the target requests that
5712 /// we expand it. At this point, we know that the result and operand types are
5713 /// legal for the target.
5714 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5717 if (Op0.getValueType() == MVT::i32) {
5718 // simple 32-bit [signed|unsigned] integer to float/double expansion
5720 // Get the stack frame index of a 8 byte buffer.
5721 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
5723 // word offset constant for Hi/Lo address computation
5724 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5725 // set up Hi and Lo (into buffer) address based on endian
5726 SDValue Hi = StackSlot;
5727 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5728 if (TLI.isLittleEndian())
5731 // if signed map to unsigned space
5734 // constant used to invert sign bit (signed to unsigned mapping)
5735 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5736 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5740 // store the lo of the constructed double - based on integer input
5741 SDValue Store1 = DAG.getStore(DAG.getEntryNode(),
5742 Op0Mapped, Lo, NULL, 0);
5743 // initial hi portion of constructed double
5744 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5745 // store the hi of the constructed double - biased exponent
5746 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5747 // load the constructed double
5748 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5749 // FP constant to bias correct the final result
5750 SDValue Bias = DAG.getConstantFP(isSigned ?
5751 BitsToDouble(0x4330000080000000ULL)
5752 : BitsToDouble(0x4330000000000000ULL),
5754 // subtract the bias
5755 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5758 // handle final rounding
5759 if (DestVT == MVT::f64) {
5762 } else if (DestVT.bitsLT(MVT::f64)) {
5763 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5764 DAG.getIntPtrConstant(0));
5765 } else if (DestVT.bitsGT(MVT::f64)) {
5766 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5770 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5771 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5773 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
5774 DAG.getConstant(0, Op0.getValueType()),
5776 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5777 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5778 SignSet, Four, Zero);
5780 // If the sign bit of the integer is set, the large number will be treated
5781 // as a negative number. To counteract this, the dynamic code adds an
5782 // offset depending on the data type.
5784 switch (Op0.getValueType().getSimpleVT()) {
5785 default: assert(0 && "Unsupported integer type!");
5786 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5787 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5788 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5789 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5791 if (TLI.isLittleEndian()) FF <<= 32;
5792 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5794 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5795 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5796 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5797 Alignment = std::min(Alignment, 4u);
5799 if (DestVT == MVT::f32)
5800 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5801 PseudoSourceValue::getConstantPool(), 0,
5805 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5806 DAG.getEntryNode(), CPIdx,
5807 PseudoSourceValue::getConstantPool(), 0,
5808 MVT::f32, false, Alignment));
5811 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5814 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5815 /// *INT_TO_FP operation of the specified operand when the target requests that
5816 /// we promote it. At this point, we know that the result and operand types are
5817 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5818 /// operation that takes a larger input.
5819 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
5822 // First step, figure out the appropriate *INT_TO_FP operation to use.
5823 MVT NewInTy = LegalOp.getValueType();
5825 unsigned OpToUse = 0;
5827 // Scan for the appropriate larger type to use.
5829 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
5830 assert(NewInTy.isInteger() && "Ran out of possibilities!");
5832 // If the target supports SINT_TO_FP of this type, use it.
5833 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5835 case TargetLowering::Legal:
5836 if (!TLI.isTypeLegal(NewInTy))
5837 break; // Can't use this datatype.
5839 case TargetLowering::Custom:
5840 OpToUse = ISD::SINT_TO_FP;
5844 if (isSigned) continue;
5846 // If the target supports UINT_TO_FP of this type, use it.
5847 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5849 case TargetLowering::Legal:
5850 if (!TLI.isTypeLegal(NewInTy))
5851 break; // Can't use this datatype.
5853 case TargetLowering::Custom:
5854 OpToUse = ISD::UINT_TO_FP;
5859 // Otherwise, try a larger type.
5862 // Okay, we found the operation and type to use. Zero extend our input to the
5863 // desired type then run the operation on it.
5864 return DAG.getNode(OpToUse, DestVT,
5865 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5869 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5870 /// FP_TO_*INT operation of the specified operand when the target requests that
5871 /// we promote it. At this point, we know that the result and operand types are
5872 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5873 /// operation that returns a larger result.
5874 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
5877 // First step, figure out the appropriate FP_TO*INT operation to use.
5878 MVT NewOutTy = DestVT;
5880 unsigned OpToUse = 0;
5882 // Scan for the appropriate larger type to use.
5884 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
5885 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
5887 // If the target supports FP_TO_SINT returning this type, use it.
5888 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5890 case TargetLowering::Legal:
5891 if (!TLI.isTypeLegal(NewOutTy))
5892 break; // Can't use this datatype.
5894 case TargetLowering::Custom:
5895 OpToUse = ISD::FP_TO_SINT;
5900 // If the target supports FP_TO_UINT of this type, use it.
5901 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5903 case TargetLowering::Legal:
5904 if (!TLI.isTypeLegal(NewOutTy))
5905 break; // Can't use this datatype.
5907 case TargetLowering::Custom:
5908 OpToUse = ISD::FP_TO_UINT;
5913 // Otherwise, try a larger type.
5917 // Okay, we found the operation and type to use.
5918 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5920 // If the operation produces an invalid type, it must be custom lowered. Use
5921 // the target lowering hooks to expand it. Just keep the low part of the
5922 // expanded operation, we know that we're truncating anyway.
5923 if (getTypeAction(NewOutTy) == Expand) {
5924 Operation = SDValue(TLI.ReplaceNodeResults(Operation.getNode(), DAG), 0);
5925 assert(Operation.getNode() && "Didn't return anything");
5928 // Truncate the result of the extended FP_TO_*INT operation to the desired
5930 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5933 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5935 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) {
5936 MVT VT = Op.getValueType();
5937 MVT SHVT = TLI.getShiftAmountTy();
5938 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5939 switch (VT.getSimpleVT()) {
5940 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5942 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5943 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5944 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5946 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5947 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5948 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5949 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5950 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5951 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5952 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5953 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5954 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5956 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5957 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5958 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5959 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5960 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5961 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5962 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5963 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5964 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5965 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5966 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5967 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5968 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5969 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5970 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5971 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5972 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5973 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5974 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5975 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5976 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5980 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5982 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
5984 default: assert(0 && "Cannot expand this yet!");
5986 static const uint64_t mask[6] = {
5987 0x5555555555555555ULL, 0x3333333333333333ULL,
5988 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5989 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5991 MVT VT = Op.getValueType();
5992 MVT ShVT = TLI.getShiftAmountTy();
5993 unsigned len = VT.getSizeInBits();
5994 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5995 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5996 SDValue Tmp2 = DAG.getConstant(mask[i], VT);
5997 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5998 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5999 DAG.getNode(ISD::AND, VT,
6000 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
6005 // for now, we do this:
6006 // x = x | (x >> 1);
6007 // x = x | (x >> 2);
6009 // x = x | (x >>16);
6010 // x = x | (x >>32); // for 64-bit input
6011 // return popcount(~x);
6013 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
6014 MVT VT = Op.getValueType();
6015 MVT ShVT = TLI.getShiftAmountTy();
6016 unsigned len = VT.getSizeInBits();
6017 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6018 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6019 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
6021 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
6022 return DAG.getNode(ISD::CTPOP, VT, Op);
6025 // for now, we use: { return popcount(~x & (x - 1)); }
6026 // unless the target has ctlz but not ctpop, in which case we use:
6027 // { return 32 - nlz(~x & (x-1)); }
6028 // see also http://www.hackersdelight.org/HDcode/ntz.cc
6029 MVT VT = Op.getValueType();
6030 SDValue Tmp2 = DAG.getConstant(~0ULL, VT);
6031 SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
6032 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
6033 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
6034 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6035 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
6036 TLI.isOperationLegal(ISD::CTLZ, VT))
6037 return DAG.getNode(ISD::SUB, VT,
6038 DAG.getConstant(VT.getSizeInBits(), VT),
6039 DAG.getNode(ISD::CTLZ, VT, Tmp3));
6040 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
6045 /// ExpandOp - Expand the specified SDValue into its two component pieces
6046 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
6047 /// LegalizedNodes map is filled in for any results that are not expanded, the
6048 /// ExpandedNodes map is filled in for any results that are expanded, and the
6049 /// Lo/Hi values are returned.
6050 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
6051 MVT VT = Op.getValueType();
6052 MVT NVT = TLI.getTypeToTransformTo(VT);
6053 SDNode *Node = Op.getNode();
6054 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
6055 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
6056 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
6058 // See if we already expanded it.
6059 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
6060 = ExpandedNodes.find(Op);
6061 if (I != ExpandedNodes.end()) {
6062 Lo = I->second.first;
6063 Hi = I->second.second;
6067 switch (Node->getOpcode()) {
6068 case ISD::CopyFromReg:
6069 assert(0 && "CopyFromReg must be legal!");
6070 case ISD::FP_ROUND_INREG:
6071 if (VT == MVT::ppcf128 &&
6072 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
6073 TargetLowering::Custom) {
6074 SDValue SrcLo, SrcHi, Src;
6075 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
6076 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
6077 SDValue Result = TLI.LowerOperation(
6078 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
6079 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
6080 Lo = Result.getNode()->getOperand(0);
6081 Hi = Result.getNode()->getOperand(1);
6087 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
6089 assert(0 && "Do not know how to expand this operator!");
6091 case ISD::EXTRACT_ELEMENT:
6092 ExpandOp(Node->getOperand(0), Lo, Hi);
6093 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
6094 return ExpandOp(Hi, Lo, Hi);
6095 return ExpandOp(Lo, Lo, Hi);
6096 case ISD::EXTRACT_VECTOR_ELT:
6097 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
6098 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
6099 return ExpandOp(Lo, Lo, Hi);
6101 Lo = DAG.getNode(ISD::UNDEF, NVT);
6102 Hi = DAG.getNode(ISD::UNDEF, NVT);
6104 case ISD::Constant: {
6105 unsigned NVTBits = NVT.getSizeInBits();
6106 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
6107 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
6108 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
6111 case ISD::ConstantFP: {
6112 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
6113 if (CFP->getValueType(0) == MVT::ppcf128) {
6114 APInt api = CFP->getValueAPF().bitcastToAPInt();
6115 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
6117 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
6121 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
6122 if (getTypeAction(Lo.getValueType()) == Expand)
6123 ExpandOp(Lo, Lo, Hi);
6126 case ISD::BUILD_PAIR:
6127 // Return the operands.
6128 Lo = Node->getOperand(0);
6129 Hi = Node->getOperand(1);
6132 case ISD::MERGE_VALUES:
6133 if (Node->getNumValues() == 1) {
6134 ExpandOp(Op.getOperand(0), Lo, Hi);
6137 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
6138 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
6139 Op.getValue(1).getValueType() == MVT::Other &&
6140 "unhandled MERGE_VALUES");
6141 ExpandOp(Op.getOperand(0), Lo, Hi);
6142 // Remember that we legalized the chain.
6143 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
6146 case ISD::SIGN_EXTEND_INREG:
6147 ExpandOp(Node->getOperand(0), Lo, Hi);
6148 // sext_inreg the low part if needed.
6149 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
6151 // The high part gets the sign extension from the lo-part. This handles
6152 // things like sextinreg V:i64 from i8.
6153 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6154 DAG.getConstant(NVT.getSizeInBits()-1,
6155 TLI.getShiftAmountTy()));
6159 ExpandOp(Node->getOperand(0), Lo, Hi);
6160 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
6161 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
6167 ExpandOp(Node->getOperand(0), Lo, Hi);
6168 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
6169 DAG.getNode(ISD::CTPOP, NVT, Lo),
6170 DAG.getNode(ISD::CTPOP, NVT, Hi));
6171 Hi = DAG.getConstant(0, NVT);
6175 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
6176 ExpandOp(Node->getOperand(0), Lo, Hi);
6177 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6178 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
6179 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
6181 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
6182 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
6184 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
6185 Hi = DAG.getConstant(0, NVT);
6190 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
6191 ExpandOp(Node->getOperand(0), Lo, Hi);
6192 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6193 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
6194 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
6196 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
6197 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
6199 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
6200 Hi = DAG.getConstant(0, NVT);
6205 SDValue Ch = Node->getOperand(0); // Legalize the chain.
6206 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6207 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
6208 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
6210 // Remember that we legalized the chain.
6211 Hi = LegalizeOp(Hi);
6212 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6213 if (TLI.isBigEndian())
6219 LoadSDNode *LD = cast<LoadSDNode>(Node);
6220 SDValue Ch = LD->getChain(); // Legalize the chain.
6221 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6222 ISD::LoadExtType ExtType = LD->getExtensionType();
6223 const Value *SV = LD->getSrcValue();
6224 int SVOffset = LD->getSrcValueOffset();
6225 unsigned Alignment = LD->getAlignment();
6226 bool isVolatile = LD->isVolatile();
6228 if (ExtType == ISD::NON_EXTLOAD) {
6229 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6230 isVolatile, Alignment);
6231 if (VT == MVT::f32 || VT == MVT::f64) {
6232 // f32->i32 or f64->i64 one to one expansion.
6233 // Remember that we legalized the chain.
6234 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6235 // Recursively expand the new load.
6236 if (getTypeAction(NVT) == Expand)
6237 ExpandOp(Lo, Lo, Hi);
6241 // Increment the pointer to the other half.
6242 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6243 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6244 DAG.getIntPtrConstant(IncrementSize));
6245 SVOffset += IncrementSize;
6246 Alignment = MinAlign(Alignment, IncrementSize);
6247 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6248 isVolatile, Alignment);
6250 // Build a factor node to remember that this load is independent of the
6252 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6255 // Remember that we legalized the chain.
6256 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6257 if (TLI.isBigEndian())
6260 MVT EVT = LD->getMemoryVT();
6262 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6263 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6264 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6265 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV,
6266 SVOffset, isVolatile, Alignment);
6267 // Remember that we legalized the chain.
6268 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6269 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
6274 Lo = DAG.getLoad(NVT, Ch, Ptr, SV,
6275 SVOffset, isVolatile, Alignment);
6277 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV,
6278 SVOffset, EVT, isVolatile,
6281 // Remember that we legalized the chain.
6282 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6284 if (ExtType == ISD::SEXTLOAD) {
6285 // The high part is obtained by SRA'ing all but one of the bits of the
6287 unsigned LoSize = Lo.getValueType().getSizeInBits();
6288 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6289 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6290 } else if (ExtType == ISD::ZEXTLOAD) {
6291 // The high part is just a zero.
6292 Hi = DAG.getConstant(0, NVT);
6293 } else /* if (ExtType == ISD::EXTLOAD) */ {
6294 // The high part is undefined.
6295 Hi = DAG.getNode(ISD::UNDEF, NVT);
6302 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6303 SDValue LL, LH, RL, RH;
6304 ExpandOp(Node->getOperand(0), LL, LH);
6305 ExpandOp(Node->getOperand(1), RL, RH);
6306 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
6307 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
6311 SDValue LL, LH, RL, RH;
6312 ExpandOp(Node->getOperand(1), LL, LH);
6313 ExpandOp(Node->getOperand(2), RL, RH);
6314 if (getTypeAction(NVT) == Expand)
6315 NVT = TLI.getTypeToExpandTo(NVT);
6316 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
6318 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
6321 case ISD::SELECT_CC: {
6322 SDValue TL, TH, FL, FH;
6323 ExpandOp(Node->getOperand(2), TL, TH);
6324 ExpandOp(Node->getOperand(3), FL, FH);
6325 if (getTypeAction(NVT) == Expand)
6326 NVT = TLI.getTypeToExpandTo(NVT);
6327 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6328 Node->getOperand(1), TL, FL, Node->getOperand(4));
6330 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6331 Node->getOperand(1), TH, FH, Node->getOperand(4));
6334 case ISD::ANY_EXTEND:
6335 // The low part is any extension of the input (which degenerates to a copy).
6336 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6337 // The high part is undefined.
6338 Hi = DAG.getNode(ISD::UNDEF, NVT);
6340 case ISD::SIGN_EXTEND: {
6341 // The low part is just a sign extension of the input (which degenerates to
6343 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6345 // The high part is obtained by SRA'ing all but one of the bits of the lo
6347 unsigned LoSize = Lo.getValueType().getSizeInBits();
6348 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6349 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6352 case ISD::ZERO_EXTEND:
6353 // The low part is just a zero extension of the input (which degenerates to
6355 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6357 // The high part is just a zero.
6358 Hi = DAG.getConstant(0, NVT);
6361 case ISD::TRUNCATE: {
6362 // The input value must be larger than this value. Expand *it*.
6364 ExpandOp(Node->getOperand(0), NewLo, Hi);
6366 // The low part is now either the right size, or it is closer. If not the
6367 // right size, make an illegal truncate so we recursively expand it.
6368 if (NewLo.getValueType() != Node->getValueType(0))
6369 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6370 ExpandOp(NewLo, Lo, Hi);
6374 case ISD::BIT_CONVERT: {
6376 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6377 // If the target wants to, allow it to lower this itself.
6378 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6379 case Expand: assert(0 && "cannot expand FP!");
6380 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6381 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6383 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6386 // f32 / f64 must be expanded to i32 / i64.
6387 if (VT == MVT::f32 || VT == MVT::f64) {
6388 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6389 if (getTypeAction(NVT) == Expand)
6390 ExpandOp(Lo, Lo, Hi);
6394 // If source operand will be expanded to the same type as VT, i.e.
6395 // i64 <- f64, i32 <- f32, expand the source operand instead.
6396 MVT VT0 = Node->getOperand(0).getValueType();
6397 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6398 ExpandOp(Node->getOperand(0), Lo, Hi);
6402 // Turn this into a load/store pair by default.
6403 if (Tmp.getNode() == 0)
6404 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6406 ExpandOp(Tmp, Lo, Hi);
6410 case ISD::READCYCLECOUNTER: {
6411 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6412 TargetLowering::Custom &&
6413 "Must custom expand ReadCycleCounter");
6414 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6415 assert(Tmp.getNode() && "Node must be custom expanded!");
6416 ExpandOp(Tmp.getValue(0), Lo, Hi);
6417 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6418 LegalizeOp(Tmp.getValue(1)));
6422 case ISD::ATOMIC_CMP_SWAP_64: {
6423 // This operation does not need a loop.
6424 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6425 assert(Tmp.getNode() && "Node must be custom expanded!");
6426 ExpandOp(Tmp.getValue(0), Lo, Hi);
6427 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6428 LegalizeOp(Tmp.getValue(1)));
6432 case ISD::ATOMIC_LOAD_ADD_64:
6433 case ISD::ATOMIC_LOAD_SUB_64:
6434 case ISD::ATOMIC_LOAD_AND_64:
6435 case ISD::ATOMIC_LOAD_OR_64:
6436 case ISD::ATOMIC_LOAD_XOR_64:
6437 case ISD::ATOMIC_LOAD_NAND_64:
6438 case ISD::ATOMIC_SWAP_64: {
6439 // These operations require a loop to be generated. We can't do that yet,
6440 // so substitute a target-dependent pseudo and expand that later.
6441 SDValue In2Lo, In2Hi, In2;
6442 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6443 In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi);
6444 AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
6446 DAG.getAtomic(Op.getOpcode(), Op.getOperand(0), Op.getOperand(1), In2,
6447 Anode->getSrcValue(), Anode->getAlignment());
6448 SDValue Result = TLI.LowerOperation(Replace, DAG);
6449 ExpandOp(Result.getValue(0), Lo, Hi);
6450 // Remember that we legalized the chain.
6451 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
6455 // These operators cannot be expanded directly, emit them as calls to
6456 // library functions.
6457 case ISD::FP_TO_SINT: {
6458 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6460 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6461 case Expand: assert(0 && "cannot expand FP!");
6462 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6463 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6466 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6468 // Now that the custom expander is done, expand the result, which is still
6471 ExpandOp(Op, Lo, Hi);
6476 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6478 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6479 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6483 case ISD::FP_TO_UINT: {
6484 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6486 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6487 case Expand: assert(0 && "cannot expand FP!");
6488 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6489 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6492 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6494 // Now that the custom expander is done, expand the result.
6496 ExpandOp(Op, Lo, Hi);
6501 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6503 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6504 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6509 // If the target wants custom lowering, do so.
6510 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6511 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6512 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6513 Op = TLI.LowerOperation(Op, DAG);
6515 // Now that the custom expander is done, expand the result, which is
6517 ExpandOp(Op, Lo, Hi);
6522 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6523 // this X << 1 as X+X.
6524 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6525 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6526 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6527 SDValue LoOps[2], HiOps[3];
6528 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6529 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6530 LoOps[1] = LoOps[0];
6531 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6533 HiOps[1] = HiOps[0];
6534 HiOps[2] = Lo.getValue(1);
6535 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6540 // If we can emit an efficient shift operation, do so now.
6541 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6544 // If this target supports SHL_PARTS, use it.
6545 TargetLowering::LegalizeAction Action =
6546 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6547 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6548 Action == TargetLowering::Custom) {
6549 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6553 // Otherwise, emit a libcall.
6554 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6559 // If the target wants custom lowering, do so.
6560 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6561 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6562 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6563 Op = TLI.LowerOperation(Op, DAG);
6565 // Now that the custom expander is done, expand the result, which is
6567 ExpandOp(Op, Lo, Hi);
6572 // If we can emit an efficient shift operation, do so now.
6573 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6576 // If this target supports SRA_PARTS, use it.
6577 TargetLowering::LegalizeAction Action =
6578 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6579 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6580 Action == TargetLowering::Custom) {
6581 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6585 // Otherwise, emit a libcall.
6586 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6591 // If the target wants custom lowering, do so.
6592 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6593 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6594 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6595 Op = TLI.LowerOperation(Op, DAG);
6597 // Now that the custom expander is done, expand the result, which is
6599 ExpandOp(Op, Lo, Hi);
6604 // If we can emit an efficient shift operation, do so now.
6605 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6608 // If this target supports SRL_PARTS, use it.
6609 TargetLowering::LegalizeAction Action =
6610 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6611 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6612 Action == TargetLowering::Custom) {
6613 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6617 // Otherwise, emit a libcall.
6618 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6624 // If the target wants to custom expand this, let them.
6625 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6626 TargetLowering::Custom) {
6627 SDValue Result = TLI.LowerOperation(Op, DAG);
6628 if (Result.getNode()) {
6629 ExpandOp(Result, Lo, Hi);
6633 // Expand the subcomponents.
6634 SDValue LHSL, LHSH, RHSL, RHSH;
6635 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6636 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6637 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6638 SDValue LoOps[2], HiOps[3];
6644 //cascaded check to see if any smaller size has a a carry flag.
6645 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
6646 bool hasCarry = false;
6647 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
6648 MVT AVT = MVT::getIntegerVT(BitSize);
6649 if (TLI.isOperationLegal(OpV, AVT)) {
6656 if (Node->getOpcode() == ISD::ADD) {
6657 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6658 HiOps[2] = Lo.getValue(1);
6659 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6661 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6662 HiOps[2] = Lo.getValue(1);
6663 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6667 if (Node->getOpcode() == ISD::ADD) {
6668 Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2);
6669 Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2);
6670 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
6671 Lo, LoOps[0], ISD::SETULT);
6672 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
6673 DAG.getConstant(1, NVT),
6674 DAG.getConstant(0, NVT));
6675 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
6676 Lo, LoOps[1], ISD::SETULT);
6677 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
6678 DAG.getConstant(1, NVT),
6680 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
6682 Lo = DAG.getNode(ISD::SUB, VTList, LoOps, 2);
6683 Hi = DAG.getNode(ISD::SUB, VTList, HiOps, 2);
6684 SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT);
6685 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
6686 DAG.getConstant(1, NVT),
6687 DAG.getConstant(0, NVT));
6688 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow);
6696 // Expand the subcomponents.
6697 SDValue LHSL, LHSH, RHSL, RHSH;
6698 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6699 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6700 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6701 SDValue LoOps[2] = { LHSL, RHSL };
6702 SDValue HiOps[3] = { LHSH, RHSH };
6704 if (Node->getOpcode() == ISD::ADDC) {
6705 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6706 HiOps[2] = Lo.getValue(1);
6707 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6709 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6710 HiOps[2] = Lo.getValue(1);
6711 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6713 // Remember that we legalized the flag.
6714 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6719 // Expand the subcomponents.
6720 SDValue LHSL, LHSH, RHSL, RHSH;
6721 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6722 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6723 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6724 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6725 SDValue HiOps[3] = { LHSH, RHSH };
6727 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6728 HiOps[2] = Lo.getValue(1);
6729 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6731 // Remember that we legalized the flag.
6732 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6736 // If the target wants to custom expand this, let them.
6737 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6738 SDValue New = TLI.LowerOperation(Op, DAG);
6739 if (New.getNode()) {
6740 ExpandOp(New, Lo, Hi);
6745 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6746 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6747 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6748 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6749 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6750 SDValue LL, LH, RL, RH;
6751 ExpandOp(Node->getOperand(0), LL, LH);
6752 ExpandOp(Node->getOperand(1), RL, RH);
6753 unsigned OuterBitSize = Op.getValueSizeInBits();
6754 unsigned InnerBitSize = RH.getValueSizeInBits();
6755 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6756 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6757 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
6758 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
6759 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
6760 // The inputs are both zero-extended.
6762 // We can emit a umul_lohi.
6763 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6764 Hi = SDValue(Lo.getNode(), 1);
6768 // We can emit a mulhu+mul.
6769 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6770 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6774 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6775 // The input values are both sign-extended.
6777 // We can emit a smul_lohi.
6778 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6779 Hi = SDValue(Lo.getNode(), 1);
6783 // We can emit a mulhs+mul.
6784 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6785 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6790 // Lo,Hi = umul LHS, RHS.
6791 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6792 DAG.getVTList(NVT, NVT), LL, RL);
6794 Hi = UMulLOHI.getValue(1);
6795 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6796 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6797 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6798 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6802 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6803 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6804 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6805 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6806 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6807 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6812 // If nothing else, we can make a libcall.
6813 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
6817 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
6820 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
6823 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
6826 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
6830 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
6833 RTLIB::ADD_PPCF128),
6837 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
6840 RTLIB::SUB_PPCF128),
6844 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
6847 RTLIB::MUL_PPCF128),
6851 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
6854 RTLIB::DIV_PPCF128),
6857 case ISD::FP_EXTEND: {
6858 if (VT == MVT::ppcf128) {
6859 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6860 Node->getOperand(0).getValueType()==MVT::f64);
6861 const uint64_t zero = 0;
6862 if (Node->getOperand(0).getValueType()==MVT::f32)
6863 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6865 Hi = Node->getOperand(0);
6866 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6869 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
6870 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
6871 Lo = ExpandLibCall(LC, Node, true, Hi);
6874 case ISD::FP_ROUND: {
6875 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
6877 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
6878 Lo = ExpandLibCall(LC, Node, true, Hi);
6893 case ISD::FNEARBYINT:
6896 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6897 switch(Node->getOpcode()) {
6899 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6900 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6903 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6904 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6907 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6908 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6911 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
6912 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
6915 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
6916 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
6919 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
6920 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
6923 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
6924 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
6927 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
6928 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
6931 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
6932 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
6935 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
6936 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
6939 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
6940 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
6943 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
6944 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
6946 case ISD::FNEARBYINT:
6947 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
6948 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
6951 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
6952 RTLIB::POW_PPCF128);
6955 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
6956 RTLIB::POWI_PPCF128);
6958 default: assert(0 && "Unreachable!");
6960 Lo = ExpandLibCall(LC, Node, false, Hi);
6964 if (VT == MVT::ppcf128) {
6966 ExpandOp(Node->getOperand(0), Lo, Tmp);
6967 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6968 // lo = hi==fabs(hi) ? lo : -lo;
6969 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6970 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6971 DAG.getCondCode(ISD::SETEQ));
6974 SDValue Mask = (VT == MVT::f64)
6975 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6976 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6977 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6978 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6979 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6980 if (getTypeAction(NVT) == Expand)
6981 ExpandOp(Lo, Lo, Hi);
6985 if (VT == MVT::ppcf128) {
6986 ExpandOp(Node->getOperand(0), Lo, Hi);
6987 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6988 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6991 SDValue Mask = (VT == MVT::f64)
6992 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6993 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6994 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6995 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6996 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6997 if (getTypeAction(NVT) == Expand)
6998 ExpandOp(Lo, Lo, Hi);
7001 case ISD::FCOPYSIGN: {
7002 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
7003 if (getTypeAction(NVT) == Expand)
7004 ExpandOp(Lo, Lo, Hi);
7007 case ISD::SINT_TO_FP:
7008 case ISD::UINT_TO_FP: {
7009 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
7010 MVT SrcVT = Node->getOperand(0).getValueType();
7012 // Promote the operand if needed. Do this before checking for
7013 // ppcf128 so conversions of i16 and i8 work.
7014 if (getTypeAction(SrcVT) == Promote) {
7015 SDValue Tmp = PromoteOp(Node->getOperand(0));
7017 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
7018 DAG.getValueType(SrcVT))
7019 : DAG.getZeroExtendInReg(Tmp, SrcVT);
7020 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
7021 SrcVT = Node->getOperand(0).getValueType();
7024 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
7025 static const uint64_t zero = 0;
7027 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
7028 Node->getOperand(0)));
7029 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7031 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
7032 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
7033 Node->getOperand(0)));
7034 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7035 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
7036 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
7037 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
7038 DAG.getConstant(0, MVT::i32),
7039 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
7041 APFloat(APInt(128, 2, TwoE32)),
7044 DAG.getCondCode(ISD::SETLT)),
7049 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
7050 // si64->ppcf128 done by libcall, below
7051 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
7052 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
7054 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
7055 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
7056 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
7057 DAG.getConstant(0, MVT::i64),
7058 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
7060 APFloat(APInt(128, 2, TwoE64)),
7063 DAG.getCondCode(ISD::SETLT)),
7068 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
7069 Node->getOperand(0));
7070 if (getTypeAction(Lo.getValueType()) == Expand)
7071 // float to i32 etc. can be 'expanded' to a single node.
7072 ExpandOp(Lo, Lo, Hi);
7077 // Make sure the resultant values have been legalized themselves, unless this
7078 // is a type that requires multi-step expansion.
7079 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
7080 Lo = LegalizeOp(Lo);
7082 // Don't legalize the high part if it is expanded to a single node.
7083 Hi = LegalizeOp(Hi);
7086 // Remember in a map if the values will be reused later.
7088 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7089 assert(isNew && "Value already expanded?!?");
7092 /// SplitVectorOp - Given an operand of vector type, break it down into
7093 /// two smaller values, still of vector type.
7094 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
7096 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
7097 SDNode *Node = Op.getNode();
7098 unsigned NumElements = Op.getValueType().getVectorNumElements();
7099 assert(NumElements > 1 && "Cannot split a single element vector!");
7101 MVT NewEltVT = Op.getValueType().getVectorElementType();
7103 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
7104 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
7106 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
7107 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
7109 // See if we already split it.
7110 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
7111 = SplitNodes.find(Op);
7112 if (I != SplitNodes.end()) {
7113 Lo = I->second.first;
7114 Hi = I->second.second;
7118 switch (Node->getOpcode()) {
7123 assert(0 && "Unhandled operation in SplitVectorOp!");
7125 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
7126 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
7128 case ISD::BUILD_PAIR:
7129 Lo = Node->getOperand(0);
7130 Hi = Node->getOperand(1);
7132 case ISD::INSERT_VECTOR_ELT: {
7133 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
7134 SplitVectorOp(Node->getOperand(0), Lo, Hi);
7135 unsigned Index = Idx->getZExtValue();
7136 SDValue ScalarOp = Node->getOperand(1);
7137 if (Index < NewNumElts_Lo)
7138 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
7139 DAG.getIntPtrConstant(Index));
7141 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
7142 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
7145 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
7146 Node->getOperand(1),
7147 Node->getOperand(2));
7148 SplitVectorOp(Tmp, Lo, Hi);
7151 case ISD::VECTOR_SHUFFLE: {
7152 // Build the low part.
7153 SDValue Mask = Node->getOperand(2);
7154 SmallVector<SDValue, 8> Ops;
7155 MVT PtrVT = TLI.getPointerTy();
7157 // Insert all of the elements from the input that are needed. We use
7158 // buildvector of extractelement here because the input vectors will have
7159 // to be legalized, so this makes the code simpler.
7160 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
7161 SDValue IdxNode = Mask.getOperand(i);
7162 if (IdxNode.getOpcode() == ISD::UNDEF) {
7163 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
7166 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7167 SDValue InVec = Node->getOperand(0);
7168 if (Idx >= NumElements) {
7169 InVec = Node->getOperand(1);
7172 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
7173 DAG.getConstant(Idx, PtrVT)));
7175 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
7178 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
7179 SDValue IdxNode = Mask.getOperand(i);
7180 if (IdxNode.getOpcode() == ISD::UNDEF) {
7181 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
7184 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7185 SDValue InVec = Node->getOperand(0);
7186 if (Idx >= NumElements) {
7187 InVec = Node->getOperand(1);
7190 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
7191 DAG.getConstant(Idx, PtrVT)));
7193 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size());
7196 case ISD::BUILD_VECTOR: {
7197 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7198 Node->op_begin()+NewNumElts_Lo);
7199 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
7201 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
7203 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
7206 case ISD::CONCAT_VECTORS: {
7207 // FIXME: Handle non-power-of-two vectors?
7208 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
7209 if (NewNumSubvectors == 1) {
7210 Lo = Node->getOperand(0);
7211 Hi = Node->getOperand(1);
7213 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7214 Node->op_begin()+NewNumSubvectors);
7215 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
7217 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
7219 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
7224 SDValue Cond = Node->getOperand(0);
7226 SDValue LL, LH, RL, RH;
7227 SplitVectorOp(Node->getOperand(1), LL, LH);
7228 SplitVectorOp(Node->getOperand(2), RL, RH);
7230 if (Cond.getValueType().isVector()) {
7231 // Handle a vector merge.
7233 SplitVectorOp(Cond, CL, CH);
7234 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
7235 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
7237 // Handle a simple select with vector operands.
7238 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
7239 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
7243 case ISD::SELECT_CC: {
7244 SDValue CondLHS = Node->getOperand(0);
7245 SDValue CondRHS = Node->getOperand(1);
7246 SDValue CondCode = Node->getOperand(4);
7248 SDValue LL, LH, RL, RH;
7249 SplitVectorOp(Node->getOperand(2), LL, LH);
7250 SplitVectorOp(Node->getOperand(3), RL, RH);
7252 // Handle a simple select with vector operands.
7253 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
7255 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
7260 SDValue LL, LH, RL, RH;
7261 SplitVectorOp(Node->getOperand(0), LL, LH);
7262 SplitVectorOp(Node->getOperand(1), RL, RH);
7263 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
7264 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
7283 SDValue LL, LH, RL, RH;
7284 SplitVectorOp(Node->getOperand(0), LL, LH);
7285 SplitVectorOp(Node->getOperand(1), RL, RH);
7287 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
7288 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
7294 SplitVectorOp(Node->getOperand(0), L, H);
7296 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
7297 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
7313 case ISD::FP_TO_SINT:
7314 case ISD::FP_TO_UINT:
7315 case ISD::SINT_TO_FP:
7316 case ISD::UINT_TO_FP:
7318 case ISD::ANY_EXTEND:
7319 case ISD::SIGN_EXTEND:
7320 case ISD::ZERO_EXTEND:
7321 case ISD::FP_EXTEND: {
7323 SplitVectorOp(Node->getOperand(0), L, H);
7325 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
7326 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
7330 LoadSDNode *LD = cast<LoadSDNode>(Node);
7331 SDValue Ch = LD->getChain();
7332 SDValue Ptr = LD->getBasePtr();
7333 ISD::LoadExtType ExtType = LD->getExtensionType();
7334 const Value *SV = LD->getSrcValue();
7335 int SVOffset = LD->getSrcValueOffset();
7336 MVT MemoryVT = LD->getMemoryVT();
7337 unsigned Alignment = LD->getAlignment();
7338 bool isVolatile = LD->isVolatile();
7340 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7341 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7343 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7344 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7345 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7347 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType,
7348 NewVT_Lo, Ch, Ptr, Offset,
7349 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7350 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7351 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
7352 DAG.getIntPtrConstant(IncrementSize));
7353 SVOffset += IncrementSize;
7354 Alignment = MinAlign(Alignment, IncrementSize);
7355 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType,
7356 NewVT_Hi, Ch, Ptr, Offset,
7357 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7359 // Build a factor node to remember that this load is independent of the
7361 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
7364 // Remember that we legalized the chain.
7365 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7368 case ISD::BIT_CONVERT: {
7369 // We know the result is a vector. The input may be either a vector or a
7371 SDValue InOp = Node->getOperand(0);
7372 if (!InOp.getValueType().isVector() ||
7373 InOp.getValueType().getVectorNumElements() == 1) {
7374 // The input is a scalar or single-element vector.
7375 // Lower to a store/load so that it can be split.
7376 // FIXME: this could be improved probably.
7377 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
7378 Op.getValueType().getTypeForMVT());
7379 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7380 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7382 SDValue St = DAG.getStore(DAG.getEntryNode(),
7384 PseudoSourceValue::getFixedStack(FI), 0);
7385 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
7386 PseudoSourceValue::getFixedStack(FI), 0);
7388 // Split the vector and convert each of the pieces now.
7389 SplitVectorOp(InOp, Lo, Hi);
7390 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
7391 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
7396 // Remember in a map if the values will be reused later.
7398 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7399 assert(isNew && "Value already split?!?");
7403 /// ScalarizeVectorOp - Given an operand of single-element vector type
7404 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7405 /// scalar (e.g. f32) value.
7406 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7407 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7408 SDNode *Node = Op.getNode();
7409 MVT NewVT = Op.getValueType().getVectorElementType();
7410 assert(Op.getValueType().getVectorNumElements() == 1);
7412 // See if we already scalarized it.
7413 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7414 if (I != ScalarizedNodes.end()) return I->second;
7417 switch (Node->getOpcode()) {
7420 Node->dump(&DAG); cerr << "\n";
7422 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7439 Result = DAG.getNode(Node->getOpcode(),
7441 ScalarizeVectorOp(Node->getOperand(0)),
7442 ScalarizeVectorOp(Node->getOperand(1)));
7454 case ISD::FP_TO_SINT:
7455 case ISD::FP_TO_UINT:
7456 case ISD::SINT_TO_FP:
7457 case ISD::UINT_TO_FP:
7458 case ISD::SIGN_EXTEND:
7459 case ISD::ZERO_EXTEND:
7460 case ISD::ANY_EXTEND:
7462 case ISD::FP_EXTEND:
7463 Result = DAG.getNode(Node->getOpcode(),
7465 ScalarizeVectorOp(Node->getOperand(0)));
7469 Result = DAG.getNode(Node->getOpcode(),
7471 ScalarizeVectorOp(Node->getOperand(0)),
7472 Node->getOperand(1));
7475 LoadSDNode *LD = cast<LoadSDNode>(Node);
7476 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7477 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7478 ISD::LoadExtType ExtType = LD->getExtensionType();
7479 const Value *SV = LD->getSrcValue();
7480 int SVOffset = LD->getSrcValueOffset();
7481 MVT MemoryVT = LD->getMemoryVT();
7482 unsigned Alignment = LD->getAlignment();
7483 bool isVolatile = LD->isVolatile();
7485 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7486 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7488 Result = DAG.getLoad(ISD::UNINDEXED, ExtType,
7489 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7490 MemoryVT.getVectorElementType(),
7491 isVolatile, Alignment);
7493 // Remember that we legalized the chain.
7494 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7497 case ISD::BUILD_VECTOR:
7498 Result = Node->getOperand(0);
7500 case ISD::INSERT_VECTOR_ELT:
7501 // Returning the inserted scalar element.
7502 Result = Node->getOperand(1);
7504 case ISD::CONCAT_VECTORS:
7505 assert(Node->getOperand(0).getValueType() == NewVT &&
7506 "Concat of non-legal vectors not yet supported!");
7507 Result = Node->getOperand(0);
7509 case ISD::VECTOR_SHUFFLE: {
7510 // Figure out if the scalar is the LHS or RHS and return it.
7511 SDValue EltNum = Node->getOperand(2).getOperand(0);
7512 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7513 Result = ScalarizeVectorOp(Node->getOperand(1));
7515 Result = ScalarizeVectorOp(Node->getOperand(0));
7518 case ISD::EXTRACT_SUBVECTOR:
7519 Result = Node->getOperand(0);
7520 assert(Result.getValueType() == NewVT);
7522 case ISD::BIT_CONVERT: {
7523 SDValue Op0 = Op.getOperand(0);
7524 if (Op0.getValueType().getVectorNumElements() == 1)
7525 Op0 = ScalarizeVectorOp(Op0);
7526 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7530 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7531 ScalarizeVectorOp(Op.getOperand(1)),
7532 ScalarizeVectorOp(Op.getOperand(2)));
7534 case ISD::SELECT_CC:
7535 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
7536 Node->getOperand(1),
7537 ScalarizeVectorOp(Op.getOperand(2)),
7538 ScalarizeVectorOp(Op.getOperand(3)),
7539 Node->getOperand(4));
7542 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7543 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7544 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
7546 Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7547 DAG.getConstant(-1ULL, NewVT),
7548 DAG.getConstant(0ULL, NewVT));
7553 if (TLI.isTypeLegal(NewVT))
7554 Result = LegalizeOp(Result);
7555 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7556 assert(isNew && "Value already scalarized?");
7561 SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
7562 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op);
7563 if (I != WidenNodes.end()) return I->second;
7565 MVT VT = Op.getValueType();
7566 assert(VT.isVector() && "Cannot widen non-vector type!");
7569 SDNode *Node = Op.getNode();
7570 MVT EVT = VT.getVectorElementType();
7572 unsigned NumElts = VT.getVectorNumElements();
7573 unsigned NewNumElts = WidenVT.getVectorNumElements();
7574 assert(NewNumElts > NumElts && "Cannot widen to smaller type!");
7575 assert(NewNumElts < 17);
7577 // When widen is called, it is assumed that it is more efficient to use a
7578 // wide type. The default action is to widen to operation to a wider legal
7579 // vector type and then do the operation if it is legal by calling LegalizeOp
7580 // again. If there is no vector equivalent, we will unroll the operation, do
7581 // it, and rebuild the vector. If most of the operations are vectorizible to
7582 // the legal type, the resulting code will be more efficient. If this is not
7583 // the case, the resulting code will preform badly as we end up generating
7584 // code to pack/unpack the results. It is the function that calls widen
7585 // that is responsible for seeing this doesn't happen.
7586 switch (Node->getOpcode()) {
7591 assert(0 && "Unexpected operation in WidenVectorOp!");
7593 case ISD::CopyFromReg:
7594 assert(0 && "CopyFromReg must be legal!");
7597 case ISD::ConstantFP:
7598 // To build a vector of these elements, clients should call BuildVector
7599 // and with each element instead of creating a node with a vector type
7600 assert(0 && "Unexpected operation in WidenVectorOp!");
7602 // Variable Arguments with vector types doesn't make any sense to me
7603 assert(0 && "Unexpected operation in WidenVectorOp!");
7605 case ISD::BUILD_VECTOR: {
7606 // Build a vector with undefined for the new nodes
7607 SDValueVector NewOps(Node->op_begin(), Node->op_end());
7608 for (unsigned i = NumElts; i < NewNumElts; ++i) {
7609 NewOps.push_back(DAG.getNode(ISD::UNDEF,EVT));
7611 Result = DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &NewOps[0], NewOps.size());
7614 case ISD::INSERT_VECTOR_ELT: {
7615 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7616 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, WidenVT, Tmp1,
7617 Node->getOperand(1), Node->getOperand(2));
7620 case ISD::VECTOR_SHUFFLE: {
7621 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7622 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
7623 // VECTOR_SHUFFLE 3rd operand must be a constant build vector that is
7624 // used as permutation array. We build the vector here instead of widening
7625 // because we don't want to legalize and have it turned to something else.
7626 SDValue PermOp = Node->getOperand(2);
7627 SDValueVector NewOps;
7628 MVT PVT = PermOp.getValueType().getVectorElementType();
7629 for (unsigned i = 0; i < NumElts; ++i) {
7630 if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) {
7631 NewOps.push_back(PermOp.getOperand(i));
7634 cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue();
7635 if (Idx < NumElts) {
7636 NewOps.push_back(PermOp.getOperand(i));
7639 NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts,
7640 PermOp.getOperand(i).getValueType()));
7644 for (unsigned i = NumElts; i < NewNumElts; ++i) {
7645 NewOps.push_back(DAG.getNode(ISD::UNDEF,PVT));
7648 SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR,
7649 MVT::getVectorVT(PVT, NewOps.size()),
7650 &NewOps[0], NewOps.size());
7652 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, WidenVT, Tmp1, Tmp2, Tmp3);
7656 // If the load widen returns true, we can use a single load for the
7657 // vector. Otherwise, it is returning a token factor for multiple
7660 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT))
7661 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1)));
7663 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0)));
7667 case ISD::BIT_CONVERT: {
7668 SDValue Tmp1 = Node->getOperand(0);
7669 // Converts between two different types so we need to determine
7670 // the correct widen type for the input operand.
7671 MVT TVT = Tmp1.getValueType();
7672 assert(TVT.isVector() && "can not widen non vector type");
7673 MVT TEVT = TVT.getVectorElementType();
7674 assert(WidenVT.getSizeInBits() % EVT.getSizeInBits() == 0 &&
7675 "can not widen bit bit convert that are not multiple of element type");
7676 MVT TWidenVT = MVT::getVectorVT(TEVT,
7677 WidenVT.getSizeInBits()/EVT.getSizeInBits());
7678 Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
7679 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
7680 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
7682 TargetLowering::LegalizeAction action =
7683 TLI.getOperationAction(Node->getOpcode(), WidenVT);
7685 default: assert(0 && "action not supported");
7686 case TargetLowering::Legal:
7688 case TargetLowering::Promote:
7689 // We defer the promotion to when we legalize the op
7691 case TargetLowering::Expand:
7692 // Expand the operation into a bunch of nasty scalar code.
7693 Result = LegalizeOp(UnrollVectorOp(Result));
7699 case ISD::SINT_TO_FP:
7700 case ISD::UINT_TO_FP:
7701 case ISD::FP_TO_SINT:
7702 case ISD::FP_TO_UINT: {
7703 SDValue Tmp1 = Node->getOperand(0);
7704 // Converts between two different types so we need to determine
7705 // the correct widen type for the input operand.
7706 MVT TVT = Tmp1.getValueType();
7707 assert(TVT.isVector() && "can not widen non vector type");
7708 MVT TEVT = TVT.getVectorElementType();
7709 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts);
7710 Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
7711 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts);
7712 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
7714 TargetLowering::LegalizeAction action =
7715 TLI.getOperationAction(Node->getOpcode(), WidenVT);
7717 default: assert(0 && "action not supported");
7718 case TargetLowering::Legal:
7720 case TargetLowering::Promote:
7721 // We defer the promotion to when we legalize the op
7723 case TargetLowering::Expand:
7724 // Expand the operation into a bunch of nasty scalar code.
7725 Result = LegalizeOp(UnrollVectorOp(Result));
7731 case ISD::FP_EXTEND:
7732 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
7734 case ISD::SIGN_EXTEND:
7735 case ISD::ZERO_EXTEND:
7736 case ISD::ANY_EXTEND:
7738 case ISD::SIGN_EXTEND_INREG:
7744 // Unary op widening
7746 TargetLowering::LegalizeAction action =
7747 TLI.getOperationAction(Node->getOpcode(), WidenVT);
7749 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7750 assert(Tmp1.getValueType() == WidenVT);
7751 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
7753 default: assert(0 && "action not supported");
7754 case TargetLowering::Legal:
7756 case TargetLowering::Promote:
7757 // We defer the promotion to when we legalize the op
7759 case TargetLowering::Expand:
7760 // Expand the operation into a bunch of nasty scalar code.
7761 Result = LegalizeOp(UnrollVectorOp(Result));
7783 case ISD::FCOPYSIGN:
7787 // Binary op widening
7788 TargetLowering::LegalizeAction action =
7789 TLI.getOperationAction(Node->getOpcode(), WidenVT);
7791 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7792 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
7793 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
7794 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2);
7796 default: assert(0 && "action not supported");
7797 case TargetLowering::Legal:
7799 case TargetLowering::Promote:
7800 // We defer the promotion to when we legalize the op
7802 case TargetLowering::Expand:
7803 // Expand the operation into a bunch of nasty scalar code by first
7804 // Widening to the right type and then unroll the beast.
7805 Result = LegalizeOp(UnrollVectorOp(Result));
7814 // Binary op with one non vector operand
7815 TargetLowering::LegalizeAction action =
7816 TLI.getOperationAction(Node->getOpcode(), WidenVT);
7818 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7819 assert(Tmp1.getValueType() == WidenVT);
7820 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Node->getOperand(1));
7822 default: assert(0 && "action not supported");
7823 case TargetLowering::Legal:
7825 case TargetLowering::Promote:
7826 // We defer the promotion to when we legalize the op
7828 case TargetLowering::Expand:
7829 // Expand the operation into a bunch of nasty scalar code.
7830 Result = LegalizeOp(UnrollVectorOp(Result));
7835 case ISD::EXTRACT_VECTOR_ELT: {
7836 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7837 assert(Tmp1.getValueType() == WidenVT);
7838 Result = DAG.getNode(Node->getOpcode(), EVT, Tmp1, Node->getOperand(1));
7841 case ISD::CONCAT_VECTORS: {
7842 // We concurrently support only widen on a multiple of the incoming vector.
7843 // We could widen on a multiple of the incoming operand if necessary.
7844 unsigned NumConcat = NewNumElts / NumElts;
7845 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
7846 std::vector<SDValue> UnOps(NumElts, DAG.getNode(ISD::UNDEF,
7847 VT.getVectorElementType()));
7848 SDValue UndefVal = DAG.getNode(ISD::BUILD_VECTOR, VT,
7849 &UnOps[0], UnOps.size());
7850 SmallVector<SDValue, 8> MOps;
7852 for (unsigned i = 1; i != NumConcat; ++i) {
7853 MOps.push_back(UndefVal);
7855 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
7856 &MOps[0], MOps.size()));
7859 case ISD::EXTRACT_SUBVECTOR: {
7862 // The incoming vector might already be the proper type
7863 if (Node->getOperand(0).getValueType() != WidenVT)
7864 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7866 Tmp1 = Node->getOperand(0);
7867 assert(Tmp1.getValueType() == WidenVT);
7868 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Node->getOperand(1));
7873 TargetLowering::LegalizeAction action =
7874 TLI.getOperationAction(Node->getOpcode(), WidenVT);
7876 // Determine new condition widen type and widen
7877 SDValue Cond1 = Node->getOperand(0);
7878 MVT CondVT = Cond1.getValueType();
7879 assert(CondVT.isVector() && "can not widen non vector type");
7880 MVT CondEVT = CondVT.getVectorElementType();
7881 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
7882 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
7883 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen");
7885 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT);
7886 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT);
7887 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
7888 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Tmp1, Tmp2);
7890 default: assert(0 && "action not supported");
7891 case TargetLowering::Legal:
7893 case TargetLowering::Promote:
7894 // We defer the promotion to when we legalize the op
7896 case TargetLowering::Expand:
7897 // Expand the operation into a bunch of nasty scalar code by first
7898 // Widening to the right type and then unroll the beast.
7899 Result = LegalizeOp(UnrollVectorOp(Result));
7905 case ISD::SELECT_CC: {
7906 TargetLowering::LegalizeAction action =
7907 TLI.getOperationAction(Node->getOpcode(), WidenVT);
7909 // Determine new condition widen type and widen
7910 SDValue Cond1 = Node->getOperand(0);
7911 SDValue Cond2 = Node->getOperand(1);
7912 MVT CondVT = Cond1.getValueType();
7913 assert(CondVT.isVector() && "can not widen non vector type");
7914 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs");
7915 MVT CondEVT = CondVT.getVectorElementType();
7916 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
7917 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
7918 Cond2 = WidenVectorOp(Cond2, CondWidenVT);
7919 assert(Cond1.getValueType() == CondWidenVT &&
7920 Cond2.getValueType() == CondWidenVT && "condition not widen");
7922 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT);
7923 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT);
7924 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT &&
7925 "operands not widen");
7926 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Cond2, Tmp1,
7927 Tmp2, Node->getOperand(4));
7929 default: assert(0 && "action not supported");
7930 case TargetLowering::Legal:
7932 case TargetLowering::Promote:
7933 // We defer the promotion to when we legalize the op
7935 case TargetLowering::Expand:
7936 // Expand the operation into a bunch of nasty scalar code by first
7937 // Widening to the right type and then unroll the beast.
7938 Result = LegalizeOp(UnrollVectorOp(Result));
7944 // Determine widen for the operand
7945 SDValue Tmp1 = Node->getOperand(0);
7946 MVT TmpVT = Tmp1.getValueType();
7947 assert(TmpVT.isVector() && "can not widen non vector type");
7948 MVT TmpEVT = TmpVT.getVectorElementType();
7949 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts);
7950 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT);
7951 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT);
7952 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2,
7953 Node->getOperand(2));
7956 case ISD::ATOMIC_CMP_SWAP_8:
7957 case ISD::ATOMIC_CMP_SWAP_16:
7958 case ISD::ATOMIC_CMP_SWAP_32:
7959 case ISD::ATOMIC_CMP_SWAP_64:
7960 case ISD::ATOMIC_LOAD_ADD_8:
7961 case ISD::ATOMIC_LOAD_SUB_8:
7962 case ISD::ATOMIC_LOAD_AND_8:
7963 case ISD::ATOMIC_LOAD_OR_8:
7964 case ISD::ATOMIC_LOAD_XOR_8:
7965 case ISD::ATOMIC_LOAD_NAND_8:
7966 case ISD::ATOMIC_LOAD_MIN_8:
7967 case ISD::ATOMIC_LOAD_MAX_8:
7968 case ISD::ATOMIC_LOAD_UMIN_8:
7969 case ISD::ATOMIC_LOAD_UMAX_8:
7970 case ISD::ATOMIC_SWAP_8:
7971 case ISD::ATOMIC_LOAD_ADD_16:
7972 case ISD::ATOMIC_LOAD_SUB_16:
7973 case ISD::ATOMIC_LOAD_AND_16:
7974 case ISD::ATOMIC_LOAD_OR_16:
7975 case ISD::ATOMIC_LOAD_XOR_16:
7976 case ISD::ATOMIC_LOAD_NAND_16:
7977 case ISD::ATOMIC_LOAD_MIN_16:
7978 case ISD::ATOMIC_LOAD_MAX_16:
7979 case ISD::ATOMIC_LOAD_UMIN_16:
7980 case ISD::ATOMIC_LOAD_UMAX_16:
7981 case ISD::ATOMIC_SWAP_16:
7982 case ISD::ATOMIC_LOAD_ADD_32:
7983 case ISD::ATOMIC_LOAD_SUB_32:
7984 case ISD::ATOMIC_LOAD_AND_32:
7985 case ISD::ATOMIC_LOAD_OR_32:
7986 case ISD::ATOMIC_LOAD_XOR_32:
7987 case ISD::ATOMIC_LOAD_NAND_32:
7988 case ISD::ATOMIC_LOAD_MIN_32:
7989 case ISD::ATOMIC_LOAD_MAX_32:
7990 case ISD::ATOMIC_LOAD_UMIN_32:
7991 case ISD::ATOMIC_LOAD_UMAX_32:
7992 case ISD::ATOMIC_SWAP_32:
7993 case ISD::ATOMIC_LOAD_ADD_64:
7994 case ISD::ATOMIC_LOAD_SUB_64:
7995 case ISD::ATOMIC_LOAD_AND_64:
7996 case ISD::ATOMIC_LOAD_OR_64:
7997 case ISD::ATOMIC_LOAD_XOR_64:
7998 case ISD::ATOMIC_LOAD_NAND_64:
7999 case ISD::ATOMIC_LOAD_MIN_64:
8000 case ISD::ATOMIC_LOAD_MAX_64:
8001 case ISD::ATOMIC_LOAD_UMIN_64:
8002 case ISD::ATOMIC_LOAD_UMAX_64:
8003 case ISD::ATOMIC_SWAP_64: {
8004 // For now, we assume that using vectors for these operations don't make
8005 // much sense so we just split it. We return an empty result
8007 SplitVectorOp(Op, X, Y);
8012 } // end switch (Node->getOpcode())
8014 assert(Result.getNode() && "Didn't set a result!");
8016 Result = LegalizeOp(Result);
8018 AddWidenedOperand(Op, Result);
8022 // Utility function to find a legal vector type and its associated element
8023 // type from a preferred width and whose vector type must be the same size
8025 // TLI: Target lowering used to determine legal types
8026 // Width: Preferred width of element type
8027 // VVT: Vector value type whose size we must match.
8028 // Returns VecEVT and EVT - the vector type and its associated element type
8029 static void FindWidenVecType(TargetLowering &TLI, unsigned Width, MVT VVT,
8030 MVT& EVT, MVT& VecEVT) {
8031 // We start with the preferred width, make it a power of 2 and see if
8032 // we can find a vector type of that width. If not, we reduce it by
8033 // another power of 2. If we have widen the type, a vector of bytes should
8035 assert(TLI.isTypeLegal(VVT));
8036 unsigned EWidth = Width + 1;
8039 EWidth = (1 << Log2_32(EWidth-1));
8040 EVT = MVT::getIntegerVT(EWidth);
8041 unsigned NumEVT = VVT.getSizeInBits()/EWidth;
8042 VecEVT = MVT::getVectorVT(EVT, NumEVT);
8043 } while (!TLI.isTypeLegal(VecEVT) ||
8044 VVT.getSizeInBits() != VecEVT.getSizeInBits());
8047 SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
8056 // We assume that we have good rules to handle loading power of two loads so
8057 // we break down the operations to power of 2 loads. The strategy is to
8058 // load the largest power of 2 that we can easily transform to a legal vector
8059 // and then insert into that vector, and the cast the result into the legal
8060 // vector that we want. This avoids unnecessary stack converts.
8061 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
8062 // the load is nonvolatile, we an use a wider load for the value.
8063 // Find a vector length we can load a large chunk
8066 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8067 EVTWidth = EVT.getSizeInBits();
8069 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV, SVOffset,
8070 isVolatile, Alignment);
8071 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecEVT, LdOp);
8072 LdChain.push_back(LdOp.getValue(1));
8074 // Check if we can load the element with one instruction
8075 if (LdWidth == EVTWidth) {
8076 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
8079 // The vector element order is endianness dependent.
8081 LdWidth -= EVTWidth;
8082 unsigned Offset = 0;
8084 while (LdWidth > 0) {
8085 unsigned Increment = EVTWidth / 8;
8086 Offset += Increment;
8087 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
8088 DAG.getIntPtrConstant(Increment));
8090 if (LdWidth < EVTWidth) {
8091 // Our current type we are using is too large, use a smaller size by
8092 // using a smaller power of 2
8093 unsigned oEVTWidth = EVTWidth;
8094 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8095 EVTWidth = EVT.getSizeInBits();
8096 // Readjust position and vector position based on new load type
8097 Idx = Idx * (oEVTWidth/EVTWidth)+1;
8098 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
8101 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV,
8102 SVOffset+Offset, isVolatile,
8103 MinAlign(Alignment, Offset));
8104 LdChain.push_back(LdOp.getValue(1));
8105 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, VecEVT, VecOp, LdOp,
8106 DAG.getIntPtrConstant(Idx++));
8108 LdWidth -= EVTWidth;
8111 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
8114 bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
8118 // TODO: Add support for ConcatVec and the ability to load many vector
8119 // types (e.g., v4i8). This will not work when a vector register
8120 // to memory mapping is strange (e.g., vector elements are not
8121 // stored in some sequential order).
8123 // It must be true that the widen vector type is bigger than where
8124 // we need to load from.
8125 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
8126 MVT LdVT = LD->getMemoryVT();
8127 assert(LdVT.isVector() && NVT.isVector());
8128 assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
8131 SDValue Chain = LD->getChain();
8132 SDValue BasePtr = LD->getBasePtr();
8133 int SVOffset = LD->getSrcValueOffset();
8134 unsigned Alignment = LD->getAlignment();
8135 bool isVolatile = LD->isVolatile();
8136 const Value *SV = LD->getSrcValue();
8137 unsigned int LdWidth = LdVT.getSizeInBits();
8139 // Load value as a large register
8140 SDValueVector LdChain;
8141 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
8142 Alignment, isVolatile, LdWidth, NVT);
8144 if (LdChain.size() == 1) {
8149 TFOp=DAG.getNode(ISD::TokenFactor, MVT::Other, &LdChain[0], LdChain.size());
8155 void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
8164 // Breaks the stores into a series of power of 2 width stores. For any
8165 // width, we convert the vector to the vector of element size that we
8166 // want to store. This avoids requiring a stack convert.
8168 // Find a width of the element type we can store with
8169 MVT VVT = ValOp.getValueType();
8172 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8173 EVTWidth = EVT.getSizeInBits();
8175 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, ValOp);
8176 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
8177 DAG.getIntPtrConstant(0));
8178 SDValue StOp = DAG.getStore(Chain, EOp, BasePtr, SV, SVOffset,
8179 isVolatile, Alignment);
8180 StChain.push_back(StOp);
8182 // Check if we are done
8183 if (StWidth == EVTWidth) {
8188 StWidth -= EVTWidth;
8189 unsigned Offset = 0;
8191 while (StWidth > 0) {
8192 unsigned Increment = EVTWidth / 8;
8193 Offset += Increment;
8194 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
8195 DAG.getIntPtrConstant(Increment));
8197 if (StWidth < EVTWidth) {
8198 // Our current type we are using is too large, use a smaller size by
8199 // using a smaller power of 2
8200 unsigned oEVTWidth = EVTWidth;
8201 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8202 EVTWidth = EVT.getSizeInBits();
8203 // Readjust position and vector position based on new load type
8204 Idx = Idx * (oEVTWidth/EVTWidth)+1;
8205 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
8208 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
8209 DAG.getIntPtrConstant(Idx));
8210 StChain.push_back(DAG.getStore(Chain, EOp, BasePtr, SV,
8211 SVOffset + Offset, isVolatile,
8212 MinAlign(Alignment, Offset)));
8213 StWidth -= EVTWidth;
8218 SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
8221 // TODO: It might be cleaner if we can use SplitVector and have more legal
8222 // vector types that can be stored into memory (e.g., v4xi8 can
8223 // be stored as a word). This will not work when a vector register
8224 // to memory mapping is strange (e.g., vector elements are not
8225 // stored in some sequential order).
8227 MVT StVT = ST->getMemoryVT();
8228 SDValue ValOp = ST->getValue();
8230 // Check if we have widen this node with another value
8231 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
8232 if (I != WidenNodes.end())
8235 MVT VVT = ValOp.getValueType();
8237 // It must be true that we the widen vector type is bigger than where
8238 // we need to store.
8239 assert(StVT.isVector() && VVT.isVector());
8240 assert(StVT.getSizeInBits() < VVT.getSizeInBits());
8241 assert(StVT.getVectorElementType() == VVT.getVectorElementType());
8244 SDValueVector StChain;
8245 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(),
8246 ST->getSrcValueOffset(), ST->getAlignment(),
8247 ST->isVolatile(), ValOp, StVT.getSizeInBits());
8248 if (StChain.size() == 1)
8251 return DAG.getNode(ISD::TokenFactor, MVT::Other,&StChain[0],StChain.size());
8255 // SelectionDAG::Legalize - This is the entry point for the file.
8257 void SelectionDAG::Legalize() {
8258 /// run - This is the main entry point to this class.
8260 SelectionDAGLegalize(*this).LegalizeDAG();