1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/SetVector.h"
16 #include "llvm/ADT/SmallPtrSet.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/Analysis.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineJumpTableInfo.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/DebugInfo.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetSubtargetInfo.h"
40 #define DEBUG_TYPE "legalizedag"
42 //===----------------------------------------------------------------------===//
43 /// This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class SelectionDAGLegalize {
56 const TargetMachine &TM;
57 const TargetLowering &TLI;
60 /// \brief The set of nodes which have already been legalized. We hold a
61 /// reference to it in order to update as necessary on node deletion.
62 SmallPtrSetImpl<SDNode *> &LegalizedNodes;
64 /// \brief A set of all the nodes updated during legalization.
65 SmallSetVector<SDNode *, 16> *UpdatedNodes;
67 EVT getSetCCResultType(EVT VT) const {
68 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
71 // Libcall insertion helpers.
74 SelectionDAGLegalize(SelectionDAG &DAG,
75 SmallPtrSetImpl<SDNode *> &LegalizedNodes,
76 SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
77 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
78 LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
80 /// \brief Legalizes the given operation.
81 void LegalizeOp(SDNode *Node);
84 SDValue OptimizeFloatStore(StoreSDNode *ST);
86 void LegalizeLoadOps(SDNode *Node);
87 void LegalizeStoreOps(SDNode *Node);
89 /// Some targets cannot handle a variable
90 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
91 /// is necessary to spill the vector being inserted into to memory, perform
92 /// the insert there, and then read the result back.
93 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
94 SDValue Idx, SDLoc dl);
95 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
96 SDValue Idx, SDLoc dl);
98 /// Return a vector shuffle operation which
99 /// performs the same shuffe in terms of order or result bytes, but on a type
100 /// whose vector element type is narrower than the original shuffle type.
101 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
102 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
103 SDValue N1, SDValue N2,
104 ArrayRef<int> Mask) const;
106 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
107 bool &NeedInvert, SDLoc dl);
109 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
110 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
111 unsigned NumOps, bool isSigned, SDLoc dl);
113 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
114 SDNode *Node, bool isSigned);
115 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
116 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
117 RTLIB::Libcall Call_F128,
118 RTLIB::Libcall Call_PPCF128);
119 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
120 RTLIB::Libcall Call_I8,
121 RTLIB::Libcall Call_I16,
122 RTLIB::Libcall Call_I32,
123 RTLIB::Libcall Call_I64,
124 RTLIB::Libcall Call_I128);
125 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
126 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
128 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
129 SDValue ExpandBUILD_VECTOR(SDNode *Node);
130 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
131 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
132 SmallVectorImpl<SDValue> &Results);
133 SDValue ExpandFCOPYSIGN(SDNode *Node);
134 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
136 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
138 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
141 SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
142 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
144 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
145 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
146 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
148 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
150 // if ExpandNode returns false, LegalizeOp falls back to ConvertNodeToLibcall
151 bool ExpandNode(SDNode *Node);
152 void ConvertNodeToLibcall(SDNode *Node);
153 void PromoteNode(SDNode *Node);
156 // Node replacement helpers
157 void ReplacedNode(SDNode *N) {
158 LegalizedNodes.erase(N);
160 UpdatedNodes->insert(N);
162 void ReplaceNode(SDNode *Old, SDNode *New) {
163 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
164 dbgs() << " with: "; New->dump(&DAG));
166 assert(Old->getNumValues() == New->getNumValues() &&
167 "Replacing one node with another that produces a different number "
169 DAG.ReplaceAllUsesWith(Old, New);
170 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i)
171 DAG.TransferDbgValues(SDValue(Old, i), SDValue(New, i));
173 UpdatedNodes->insert(New);
176 void ReplaceNode(SDValue Old, SDValue New) {
177 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
178 dbgs() << " with: "; New->dump(&DAG));
180 DAG.ReplaceAllUsesWith(Old, New);
181 DAG.TransferDbgValues(Old, New);
183 UpdatedNodes->insert(New.getNode());
184 ReplacedNode(Old.getNode());
186 void ReplaceNode(SDNode *Old, const SDValue *New) {
187 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
189 DAG.ReplaceAllUsesWith(Old, New);
190 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
191 DEBUG(dbgs() << (i == 0 ? " with: "
194 DAG.TransferDbgValues(SDValue(Old, i), New[i]);
196 UpdatedNodes->insert(New[i].getNode());
203 /// Return a vector shuffle operation which
204 /// performs the same shuffe in terms of order or result bytes, but on a type
205 /// whose vector element type is narrower than the original shuffle type.
206 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
208 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
209 SDValue N1, SDValue N2,
210 ArrayRef<int> Mask) const {
211 unsigned NumMaskElts = VT.getVectorNumElements();
212 unsigned NumDestElts = NVT.getVectorNumElements();
213 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
215 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
217 if (NumEltsGrowth == 1)
218 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
220 SmallVector<int, 8> NewMask;
221 for (unsigned i = 0; i != NumMaskElts; ++i) {
223 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
225 NewMask.push_back(-1);
227 NewMask.push_back(Idx * NumEltsGrowth + j);
230 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
231 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
232 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
235 /// Expands the ConstantFP node to an integer constant or
236 /// a load from the constant pool.
238 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
242 // If a FP immediate is precise when represented as a float and if the
243 // target can do an extending load from float to double, we put it into
244 // the constant pool as a float, even if it's is statically typed as a
245 // double. This shrinks FP constants and canonicalizes them for targets where
246 // an FP extending load is the same cost as a normal load (such as on the x87
247 // fp stack or PPC FP unit).
248 EVT VT = CFP->getValueType(0);
249 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
251 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
252 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), dl,
253 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
258 while (SVT != MVT::f32 && SVT != MVT::f16) {
259 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
260 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
261 // Only do this if the target has a native EXTLOAD instruction from
263 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
264 TLI.ShouldShrinkFPConstant(OrigVT)) {
265 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
266 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
273 DAG.getConstantPool(LLVMC, TLI.getPointerTy(DAG.getDataLayout()));
274 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
276 SDValue Result = DAG.getExtLoad(
277 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx,
278 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), VT,
279 false, false, false, Alignment);
283 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
284 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
285 false, false, false, Alignment);
289 /// Expands an unaligned store to 2 half-size stores.
290 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
291 const TargetLowering &TLI,
292 SelectionDAGLegalize *DAGLegalize) {
293 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
294 "unaligned indexed stores not implemented!");
295 SDValue Chain = ST->getChain();
296 SDValue Ptr = ST->getBasePtr();
297 SDValue Val = ST->getValue();
298 EVT VT = Val.getValueType();
299 int Alignment = ST->getAlignment();
300 unsigned AS = ST->getAddressSpace();
303 if (ST->getMemoryVT().isFloatingPoint() ||
304 ST->getMemoryVT().isVector()) {
305 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
306 if (TLI.isTypeLegal(intVT)) {
307 // Expand to a bitconvert of the value to the integer type of the
308 // same size, then a (misaligned) int store.
309 // FIXME: Does not handle truncating floating point stores!
310 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
311 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
312 ST->isVolatile(), ST->isNonTemporal(), Alignment);
313 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
316 // Do a (aligned) store to a stack slot, then copy from the stack slot
317 // to the final destination using (unaligned) integer loads and stores.
318 EVT StoredVT = ST->getMemoryVT();
320 TLI.getRegisterType(*DAG.getContext(),
321 EVT::getIntegerVT(*DAG.getContext(),
322 StoredVT.getSizeInBits()));
323 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
324 unsigned RegBytes = RegVT.getSizeInBits() / 8;
325 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
327 // Make sure the stack slot is also aligned for the register type.
328 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
330 // Perform the original store, only redirected to the stack slot.
331 SDValue Store = DAG.getTruncStore(Chain, dl,
332 Val, StackPtr, MachinePointerInfo(),
333 StoredVT, false, false, 0);
334 SDValue Increment = DAG.getConstant(
335 RegBytes, dl, TLI.getPointerTy(DAG.getDataLayout(), AS));
336 SmallVector<SDValue, 8> Stores;
339 // Do all but one copies using the full register width.
340 for (unsigned i = 1; i < NumRegs; i++) {
341 // Load one integer register's worth from the stack slot.
342 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
343 MachinePointerInfo(),
344 false, false, false, 0);
345 // Store it to the final location. Remember the store.
346 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
347 ST->getPointerInfo().getWithOffset(Offset),
348 ST->isVolatile(), ST->isNonTemporal(),
349 MinAlign(ST->getAlignment(), Offset)));
350 // Increment the pointers.
352 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
354 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
357 // The last store may be partial. Do a truncating store. On big-endian
358 // machines this requires an extending load from the stack slot to ensure
359 // that the bits are in the right place.
360 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
361 8 * (StoredBytes - Offset));
363 // Load from the stack slot.
364 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
365 MachinePointerInfo(),
366 MemVT, false, false, false, 0);
368 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
370 .getWithOffset(Offset),
371 MemVT, ST->isVolatile(),
373 MinAlign(ST->getAlignment(), Offset),
375 // The order of the stores doesn't matter - say it with a TokenFactor.
376 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
377 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
380 assert(ST->getMemoryVT().isInteger() &&
381 !ST->getMemoryVT().isVector() &&
382 "Unaligned store of unknown type.");
383 // Get the half-size VT
384 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
385 int NumBits = NewStoredVT.getSizeInBits();
386 int IncrementSize = NumBits / 8;
388 // Divide the stored value in two parts.
389 SDValue ShiftAmount =
390 DAG.getConstant(NumBits, dl, TLI.getShiftAmountTy(Val.getValueType(),
391 DAG.getDataLayout()));
393 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
395 // Store the two parts
396 SDValue Store1, Store2;
397 Store1 = DAG.getTruncStore(Chain, dl,
398 DAG.getDataLayout().isLittleEndian() ? Lo : Hi,
399 Ptr, ST->getPointerInfo(), NewStoredVT,
400 ST->isVolatile(), ST->isNonTemporal(), Alignment);
402 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
403 DAG.getConstant(IncrementSize, dl,
404 TLI.getPointerTy(DAG.getDataLayout(), AS)));
405 Alignment = MinAlign(Alignment, IncrementSize);
406 Store2 = DAG.getTruncStore(
407 Chain, dl, DAG.getDataLayout().isLittleEndian() ? Hi : Lo, Ptr,
408 ST->getPointerInfo().getWithOffset(IncrementSize), NewStoredVT,
409 ST->isVolatile(), ST->isNonTemporal(), Alignment, ST->getAAInfo());
412 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
413 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
416 /// Expands an unaligned load to 2 half-size loads.
418 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
419 const TargetLowering &TLI,
420 SDValue &ValResult, SDValue &ChainResult) {
421 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
422 "unaligned indexed loads not implemented!");
423 SDValue Chain = LD->getChain();
424 SDValue Ptr = LD->getBasePtr();
425 EVT VT = LD->getValueType(0);
426 EVT LoadedVT = LD->getMemoryVT();
428 if (VT.isFloatingPoint() || VT.isVector()) {
429 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
430 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
431 // Expand to a (misaligned) integer load of the same size,
432 // then bitconvert to floating point or vector.
433 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
434 LD->getMemOperand());
435 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
437 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
438 ISD::ANY_EXTEND, dl, VT, Result);
441 ChainResult = newLoad.getValue(1);
445 // Copy the value to a (aligned) stack slot using (unaligned) integer
446 // loads and stores, then do a (aligned) load from the stack slot.
447 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
448 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
449 unsigned RegBytes = RegVT.getSizeInBits() / 8;
450 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
452 // Make sure the stack slot is also aligned for the register type.
453 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
456 DAG.getConstant(RegBytes, dl, TLI.getPointerTy(DAG.getDataLayout()));
457 SmallVector<SDValue, 8> Stores;
458 SDValue StackPtr = StackBase;
461 // Do all but one copies using the full register width.
462 for (unsigned i = 1; i < NumRegs; i++) {
463 // Load one integer register's worth from the original location.
464 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
465 LD->getPointerInfo().getWithOffset(Offset),
466 LD->isVolatile(), LD->isNonTemporal(),
468 MinAlign(LD->getAlignment(), Offset),
470 // Follow the load with a store to the stack slot. Remember the store.
471 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
472 MachinePointerInfo(), false, false, 0));
473 // Increment the pointers.
475 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
476 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
480 // The last copy may be partial. Do an extending load.
481 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
482 8 * (LoadedBytes - Offset));
483 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
484 LD->getPointerInfo().getWithOffset(Offset),
485 MemVT, LD->isVolatile(),
488 MinAlign(LD->getAlignment(), Offset),
490 // Follow the load with a store to the stack slot. Remember the store.
491 // On big-endian machines this requires a truncating store to ensure
492 // that the bits end up in the right place.
493 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
494 MachinePointerInfo(), MemVT,
497 // The order of the stores doesn't matter - say it with a TokenFactor.
498 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
500 // Finally, perform the original load only redirected to the stack slot.
501 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
502 MachinePointerInfo(), LoadedVT, false,false, false,
505 // Callers expect a MERGE_VALUES node.
510 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
511 "Unaligned load of unsupported type.");
513 // Compute the new VT that is half the size of the old one. This is an
515 unsigned NumBits = LoadedVT.getSizeInBits();
517 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
520 unsigned Alignment = LD->getAlignment();
521 unsigned IncrementSize = NumBits / 8;
522 ISD::LoadExtType HiExtType = LD->getExtensionType();
524 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
525 if (HiExtType == ISD::NON_EXTLOAD)
526 HiExtType = ISD::ZEXTLOAD;
528 // Load the value in two parts
530 if (DAG.getDataLayout().isLittleEndian()) {
531 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
532 NewLoadedVT, LD->isVolatile(),
533 LD->isNonTemporal(), LD->isInvariant(), Alignment,
535 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
536 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
537 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
538 LD->getPointerInfo().getWithOffset(IncrementSize),
539 NewLoadedVT, LD->isVolatile(),
540 LD->isNonTemporal(),LD->isInvariant(),
541 MinAlign(Alignment, IncrementSize), LD->getAAInfo());
543 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
544 NewLoadedVT, LD->isVolatile(),
545 LD->isNonTemporal(), LD->isInvariant(), Alignment,
547 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
548 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
549 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
550 LD->getPointerInfo().getWithOffset(IncrementSize),
551 NewLoadedVT, LD->isVolatile(),
552 LD->isNonTemporal(), LD->isInvariant(),
553 MinAlign(Alignment, IncrementSize), LD->getAAInfo());
556 // aggregate the two parts
557 SDValue ShiftAmount =
558 DAG.getConstant(NumBits, dl, TLI.getShiftAmountTy(Hi.getValueType(),
559 DAG.getDataLayout()));
560 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
561 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
563 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
570 /// Some target cannot handle a variable insertion index for the
571 /// INSERT_VECTOR_ELT instruction. In this case, it
572 /// is necessary to spill the vector being inserted into to memory, perform
573 /// the insert there, and then read the result back.
574 SDValue SelectionDAGLegalize::
575 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
581 // If the target doesn't support this, we have to spill the input vector
582 // to a temporary stack slot, update the element, then reload it. This is
583 // badness. We could also load the value into a vector register (either
584 // with a "move to register" or "extload into register" instruction, then
585 // permute it into place, if the idx is a constant and if the idx is
586 // supported by the target.
587 EVT VT = Tmp1.getValueType();
588 EVT EltVT = VT.getVectorElementType();
589 EVT IdxVT = Tmp3.getValueType();
590 EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
591 SDValue StackPtr = DAG.CreateStackTemporary(VT);
593 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
596 SDValue Ch = DAG.getStore(
597 DAG.getEntryNode(), dl, Tmp1, StackPtr,
598 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI), false,
601 // Truncate or zero extend offset to target pointer type.
602 Tmp3 = DAG.getZExtOrTrunc(Tmp3, dl, PtrVT);
603 // Add the offset to the index.
604 unsigned EltSize = EltVT.getSizeInBits()/8;
605 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,
606 DAG.getConstant(EltSize, dl, IdxVT));
607 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
608 // Store the scalar value.
609 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
611 // Load the updated vector.
612 return DAG.getLoad(VT, dl, Ch, StackPtr, MachinePointerInfo::getFixedStack(
613 DAG.getMachineFunction(), SPFI),
614 false, false, false, 0);
618 SDValue SelectionDAGLegalize::
619 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
620 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
621 // SCALAR_TO_VECTOR requires that the type of the value being inserted
622 // match the element type of the vector being created, except for
623 // integers in which case the inserted value can be over width.
624 EVT EltVT = Vec.getValueType().getVectorElementType();
625 if (Val.getValueType() == EltVT ||
626 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
627 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
628 Vec.getValueType(), Val);
630 unsigned NumElts = Vec.getValueType().getVectorNumElements();
631 // We generate a shuffle of InVec and ScVec, so the shuffle mask
632 // should be 0,1,2,3,4,5... with the appropriate element replaced with
634 SmallVector<int, 8> ShufOps;
635 for (unsigned i = 0; i != NumElts; ++i)
636 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
638 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
642 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
645 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
646 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
647 // FIXME: We shouldn't do this for TargetConstantFP's.
648 // FIXME: move this to the DAG Combiner! Note that we can't regress due
649 // to phase ordering between legalized code and the dag combiner. This
650 // probably means that we need to integrate dag combiner and legalizer
652 // We generally can't do this one for long doubles.
653 SDValue Chain = ST->getChain();
654 SDValue Ptr = ST->getBasePtr();
655 unsigned Alignment = ST->getAlignment();
656 bool isVolatile = ST->isVolatile();
657 bool isNonTemporal = ST->isNonTemporal();
658 AAMDNodes AAInfo = ST->getAAInfo();
660 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
661 if (CFP->getValueType(0) == MVT::f32 &&
662 TLI.isTypeLegal(MVT::i32)) {
663 SDValue Con = DAG.getConstant(CFP->getValueAPF().
664 bitcastToAPInt().zextOrTrunc(32),
665 SDLoc(CFP), MVT::i32);
666 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
667 isVolatile, isNonTemporal, Alignment, AAInfo);
670 if (CFP->getValueType(0) == MVT::f64) {
671 // If this target supports 64-bit registers, do a single 64-bit store.
672 if (TLI.isTypeLegal(MVT::i64)) {
673 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
674 zextOrTrunc(64), SDLoc(CFP), MVT::i64);
675 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
676 isVolatile, isNonTemporal, Alignment, AAInfo);
679 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
680 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
681 // stores. If the target supports neither 32- nor 64-bits, this
682 // xform is certainly not worth it.
683 const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt();
684 SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32);
685 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32);
686 if (DAG.getDataLayout().isBigEndian())
689 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
690 isNonTemporal, Alignment, AAInfo);
691 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
692 DAG.getConstant(4, dl, Ptr.getValueType()));
693 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
694 ST->getPointerInfo().getWithOffset(4),
695 isVolatile, isNonTemporal, MinAlign(Alignment, 4U),
698 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
702 return SDValue(nullptr, 0);
705 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
706 StoreSDNode *ST = cast<StoreSDNode>(Node);
707 SDValue Chain = ST->getChain();
708 SDValue Ptr = ST->getBasePtr();
711 unsigned Alignment = ST->getAlignment();
712 bool isVolatile = ST->isVolatile();
713 bool isNonTemporal = ST->isNonTemporal();
714 AAMDNodes AAInfo = ST->getAAInfo();
716 if (!ST->isTruncatingStore()) {
717 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
718 ReplaceNode(ST, OptStore);
723 SDValue Value = ST->getValue();
724 MVT VT = Value.getSimpleValueType();
725 switch (TLI.getOperationAction(ISD::STORE, VT)) {
726 default: llvm_unreachable("This action is not supported yet!");
727 case TargetLowering::Legal: {
728 // If this is an unaligned store and the target doesn't support it,
730 EVT MemVT = ST->getMemoryVT();
731 unsigned AS = ST->getAddressSpace();
732 unsigned Align = ST->getAlignment();
733 const DataLayout &DL = DAG.getDataLayout();
734 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
735 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
738 case TargetLowering::Custom: {
739 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
740 if (Res && Res != SDValue(Node, 0))
741 ReplaceNode(SDValue(Node, 0), Res);
744 case TargetLowering::Promote: {
745 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
746 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
747 "Can only promote stores to same size type");
748 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
750 DAG.getStore(Chain, dl, Value, Ptr,
751 ST->getPointerInfo(), isVolatile,
752 isNonTemporal, Alignment, AAInfo);
753 ReplaceNode(SDValue(Node, 0), Result);
760 SDValue Value = ST->getValue();
762 EVT StVT = ST->getMemoryVT();
763 unsigned StWidth = StVT.getSizeInBits();
764 auto &DL = DAG.getDataLayout();
766 if (StWidth != StVT.getStoreSizeInBits()) {
767 // Promote to a byte-sized store with upper bits zero if not
768 // storing an integral number of bytes. For example, promote
769 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
770 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
771 StVT.getStoreSizeInBits());
772 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
774 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
775 NVT, isVolatile, isNonTemporal, Alignment, AAInfo);
776 ReplaceNode(SDValue(Node, 0), Result);
777 } else if (StWidth & (StWidth - 1)) {
778 // If not storing a power-of-2 number of bits, expand as two stores.
779 assert(!StVT.isVector() && "Unsupported truncstore!");
780 unsigned RoundWidth = 1 << Log2_32(StWidth);
781 assert(RoundWidth < StWidth);
782 unsigned ExtraWidth = StWidth - RoundWidth;
783 assert(ExtraWidth < RoundWidth);
784 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
785 "Store size not an integral number of bytes!");
786 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
787 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
789 unsigned IncrementSize;
791 if (DL.isLittleEndian()) {
792 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
793 // Store the bottom RoundWidth bits.
794 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
796 isVolatile, isNonTemporal, Alignment,
799 // Store the remaining ExtraWidth bits.
800 IncrementSize = RoundWidth / 8;
801 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
802 DAG.getConstant(IncrementSize, dl,
803 Ptr.getValueType()));
805 ISD::SRL, dl, Value.getValueType(), Value,
806 DAG.getConstant(RoundWidth, dl,
807 TLI.getShiftAmountTy(Value.getValueType(), DL)));
808 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
809 ST->getPointerInfo().getWithOffset(IncrementSize),
810 ExtraVT, isVolatile, isNonTemporal,
811 MinAlign(Alignment, IncrementSize), AAInfo);
813 // Big endian - avoid unaligned stores.
814 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
815 // Store the top RoundWidth bits.
817 ISD::SRL, dl, Value.getValueType(), Value,
818 DAG.getConstant(ExtraWidth, dl,
819 TLI.getShiftAmountTy(Value.getValueType(), DL)));
820 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
821 RoundVT, isVolatile, isNonTemporal, Alignment,
824 // Store the remaining ExtraWidth bits.
825 IncrementSize = RoundWidth / 8;
826 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
827 DAG.getConstant(IncrementSize, dl,
828 Ptr.getValueType()));
829 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
830 ST->getPointerInfo().getWithOffset(IncrementSize),
831 ExtraVT, isVolatile, isNonTemporal,
832 MinAlign(Alignment, IncrementSize), AAInfo);
835 // The order of the stores doesn't matter.
836 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
837 ReplaceNode(SDValue(Node, 0), Result);
839 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(),
840 StVT.getSimpleVT())) {
841 default: llvm_unreachable("This action is not supported yet!");
842 case TargetLowering::Legal: {
843 EVT MemVT = ST->getMemoryVT();
844 unsigned AS = ST->getAddressSpace();
845 unsigned Align = ST->getAlignment();
846 // If this is an unaligned store and the target doesn't support it,
848 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
849 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
852 case TargetLowering::Custom: {
853 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
854 if (Res && Res != SDValue(Node, 0))
855 ReplaceNode(SDValue(Node, 0), Res);
858 case TargetLowering::Expand:
859 assert(!StVT.isVector() &&
860 "Vector Stores are handled in LegalizeVectorOps");
862 // TRUNCSTORE:i16 i32 -> STORE i16
863 assert(TLI.isTypeLegal(StVT) &&
864 "Do not know how to expand this store!");
865 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
867 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
868 isVolatile, isNonTemporal, Alignment, AAInfo);
869 ReplaceNode(SDValue(Node, 0), Result);
876 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
877 LoadSDNode *LD = cast<LoadSDNode>(Node);
878 SDValue Chain = LD->getChain(); // The chain.
879 SDValue Ptr = LD->getBasePtr(); // The base pointer.
880 SDValue Value; // The value returned by the load op.
883 ISD::LoadExtType ExtType = LD->getExtensionType();
884 if (ExtType == ISD::NON_EXTLOAD) {
885 MVT VT = Node->getSimpleValueType(0);
886 SDValue RVal = SDValue(Node, 0);
887 SDValue RChain = SDValue(Node, 1);
889 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
890 default: llvm_unreachable("This action is not supported yet!");
891 case TargetLowering::Legal: {
892 EVT MemVT = LD->getMemoryVT();
893 unsigned AS = LD->getAddressSpace();
894 unsigned Align = LD->getAlignment();
895 const DataLayout &DL = DAG.getDataLayout();
896 // If this is an unaligned load and the target doesn't support it,
898 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
899 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
902 case TargetLowering::Custom: {
903 SDValue Res = TLI.LowerOperation(RVal, DAG);
906 RChain = Res.getValue(1);
910 case TargetLowering::Promote: {
911 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
912 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
913 "Can only promote loads to same size type");
915 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
916 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
917 RChain = Res.getValue(1);
921 if (RChain.getNode() != Node) {
922 assert(RVal.getNode() != Node && "Load must be completely replaced");
923 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
924 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
926 UpdatedNodes->insert(RVal.getNode());
927 UpdatedNodes->insert(RChain.getNode());
934 EVT SrcVT = LD->getMemoryVT();
935 unsigned SrcWidth = SrcVT.getSizeInBits();
936 unsigned Alignment = LD->getAlignment();
937 bool isVolatile = LD->isVolatile();
938 bool isNonTemporal = LD->isNonTemporal();
939 bool isInvariant = LD->isInvariant();
940 AAMDNodes AAInfo = LD->getAAInfo();
942 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
943 // Some targets pretend to have an i1 loading operation, and actually
944 // load an i8. This trick is correct for ZEXTLOAD because the top 7
945 // bits are guaranteed to be zero; it helps the optimizers understand
946 // that these bits are zero. It is also useful for EXTLOAD, since it
947 // tells the optimizers that those bits are undefined. It would be
948 // nice to have an effective generic way of getting these benefits...
949 // Until such a way is found, don't insist on promoting i1 here.
951 TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
952 TargetLowering::Promote)) {
953 // Promote to a byte-sized load if not loading an integral number of
954 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
955 unsigned NewWidth = SrcVT.getStoreSizeInBits();
956 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
959 // The extra bits are guaranteed to be zero, since we stored them that
960 // way. A zext load from NVT thus automatically gives zext from SrcVT.
962 ISD::LoadExtType NewExtType =
963 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
966 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
967 Chain, Ptr, LD->getPointerInfo(),
968 NVT, isVolatile, isNonTemporal, isInvariant, Alignment,
971 Ch = Result.getValue(1); // The chain.
973 if (ExtType == ISD::SEXTLOAD)
974 // Having the top bits zero doesn't help when sign extending.
975 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
976 Result.getValueType(),
977 Result, DAG.getValueType(SrcVT));
978 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
979 // All the top bits are guaranteed to be zero - inform the optimizers.
980 Result = DAG.getNode(ISD::AssertZext, dl,
981 Result.getValueType(), Result,
982 DAG.getValueType(SrcVT));
986 } else if (SrcWidth & (SrcWidth - 1)) {
987 // If not loading a power-of-2 number of bits, expand as two loads.
988 assert(!SrcVT.isVector() && "Unsupported extload!");
989 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
990 assert(RoundWidth < SrcWidth);
991 unsigned ExtraWidth = SrcWidth - RoundWidth;
992 assert(ExtraWidth < RoundWidth);
993 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
994 "Load size not an integral number of bytes!");
995 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
996 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
998 unsigned IncrementSize;
999 auto &DL = DAG.getDataLayout();
1001 if (DL.isLittleEndian()) {
1002 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1003 // Load the bottom RoundWidth bits.
1004 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1006 LD->getPointerInfo(), RoundVT, isVolatile,
1007 isNonTemporal, isInvariant, Alignment, AAInfo);
1009 // Load the remaining ExtraWidth bits.
1010 IncrementSize = RoundWidth / 8;
1011 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1012 DAG.getConstant(IncrementSize, dl,
1013 Ptr.getValueType()));
1014 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1015 LD->getPointerInfo().getWithOffset(IncrementSize),
1016 ExtraVT, isVolatile, isNonTemporal, isInvariant,
1017 MinAlign(Alignment, IncrementSize), AAInfo);
1019 // Build a factor node to remember that this load is independent of
1021 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1024 // Move the top bits to the right place.
1026 ISD::SHL, dl, Hi.getValueType(), Hi,
1027 DAG.getConstant(RoundWidth, dl,
1028 TLI.getShiftAmountTy(Hi.getValueType(), DL)));
1030 // Join the hi and lo parts.
1031 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1033 // Big endian - avoid unaligned loads.
1034 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1035 // Load the top RoundWidth bits.
1036 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1037 LD->getPointerInfo(), RoundVT, isVolatile,
1038 isNonTemporal, isInvariant, Alignment, AAInfo);
1040 // Load the remaining ExtraWidth bits.
1041 IncrementSize = RoundWidth / 8;
1042 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1043 DAG.getConstant(IncrementSize, dl,
1044 Ptr.getValueType()));
1045 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1046 dl, Node->getValueType(0), Chain, Ptr,
1047 LD->getPointerInfo().getWithOffset(IncrementSize),
1048 ExtraVT, isVolatile, isNonTemporal, isInvariant,
1049 MinAlign(Alignment, IncrementSize), AAInfo);
1051 // Build a factor node to remember that this load is independent of
1053 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1056 // Move the top bits to the right place.
1058 ISD::SHL, dl, Hi.getValueType(), Hi,
1059 DAG.getConstant(ExtraWidth, dl,
1060 TLI.getShiftAmountTy(Hi.getValueType(), DL)));
1062 // Join the hi and lo parts.
1063 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1068 bool isCustom = false;
1069 switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0),
1070 SrcVT.getSimpleVT())) {
1071 default: llvm_unreachable("This action is not supported yet!");
1072 case TargetLowering::Custom:
1075 case TargetLowering::Legal: {
1076 Value = SDValue(Node, 0);
1077 Chain = SDValue(Node, 1);
1080 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1081 if (Res.getNode()) {
1083 Chain = Res.getValue(1);
1086 // If this is an unaligned load and the target doesn't support it,
1088 EVT MemVT = LD->getMemoryVT();
1089 unsigned AS = LD->getAddressSpace();
1090 unsigned Align = LD->getAlignment();
1091 const DataLayout &DL = DAG.getDataLayout();
1092 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
1093 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, Value, Chain);
1097 case TargetLowering::Expand:
1098 EVT DestVT = Node->getValueType(0);
1099 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
1100 // If the source type is not legal, see if there is a legal extload to
1101 // an intermediate type that we can then extend further.
1102 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
1103 if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
1104 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) {
1105 // If we are loading a legal type, this is a non-extload followed by a
1107 ISD::LoadExtType MidExtType =
1108 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
1110 SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr,
1111 SrcVT, LD->getMemOperand());
1113 ISD::getExtForLoadExtType(SrcVT.isFloatingPoint(), ExtType);
1114 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1115 Chain = Load.getValue(1);
1119 // Handle the special case of fp16 extloads. EXTLOAD doesn't have the
1120 // normal undefined upper bits behavior to allow using an in-reg extend
1121 // with the illegal FP type, so load as an integer and do the
1122 // from-integer conversion.
1123 if (SrcVT.getScalarType() == MVT::f16) {
1124 EVT ISrcVT = SrcVT.changeTypeToInteger();
1125 EVT IDestVT = DestVT.changeTypeToInteger();
1126 EVT LoadVT = TLI.getRegisterType(IDestVT.getSimpleVT());
1128 SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, LoadVT,
1130 LD->getMemOperand());
1131 Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result);
1132 Chain = Result.getValue(1);
1137 assert(!SrcVT.isVector() &&
1138 "Vector Loads are handled in LegalizeVectorOps");
1140 // FIXME: This does not work for vectors on most targets. Sign-
1141 // and zero-extend operations are currently folded into extending
1142 // loads, whether they are legal or not, and then we end up here
1143 // without any support for legalizing them.
1144 assert(ExtType != ISD::EXTLOAD &&
1145 "EXTLOAD should always be supported!");
1146 // Turn the unsupported load into an EXTLOAD followed by an
1147 // explicit zero/sign extend inreg.
1148 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1149 Node->getValueType(0),
1151 LD->getMemOperand());
1153 if (ExtType == ISD::SEXTLOAD)
1154 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1155 Result.getValueType(),
1156 Result, DAG.getValueType(SrcVT));
1158 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1160 Chain = Result.getValue(1);
1165 // Since loads produce two values, make sure to remember that we legalized
1167 if (Chain.getNode() != Node) {
1168 assert(Value.getNode() != Node && "Load must be completely replaced");
1169 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1170 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1172 UpdatedNodes->insert(Value.getNode());
1173 UpdatedNodes->insert(Chain.getNode());
1179 /// Return a legal replacement for the given operation, with all legal operands.
1180 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1181 DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
1183 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1187 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1188 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1189 TargetLowering::TypeLegal &&
1190 "Unexpected illegal type!");
1192 for (const SDValue &Op : Node->op_values())
1193 assert((TLI.getTypeAction(*DAG.getContext(),
1194 Op.getValueType()) == TargetLowering::TypeLegal ||
1195 Op.getOpcode() == ISD::TargetConstant) &&
1196 "Unexpected illegal type!");
1199 // Figure out the correct action; the way to query this varies by opcode
1200 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1201 bool SimpleFinishLegalizing = true;
1202 switch (Node->getOpcode()) {
1203 case ISD::INTRINSIC_W_CHAIN:
1204 case ISD::INTRINSIC_WO_CHAIN:
1205 case ISD::INTRINSIC_VOID:
1206 case ISD::STACKSAVE:
1207 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1210 Action = TLI.getOperationAction(Node->getOpcode(),
1211 Node->getValueType(0));
1212 if (Action != TargetLowering::Promote)
1213 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1215 case ISD::FP_TO_FP16:
1216 case ISD::SINT_TO_FP:
1217 case ISD::UINT_TO_FP:
1218 case ISD::EXTRACT_VECTOR_ELT:
1219 Action = TLI.getOperationAction(Node->getOpcode(),
1220 Node->getOperand(0).getValueType());
1222 case ISD::FP_ROUND_INREG:
1223 case ISD::SIGN_EXTEND_INREG: {
1224 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1225 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1228 case ISD::ATOMIC_STORE: {
1229 Action = TLI.getOperationAction(Node->getOpcode(),
1230 Node->getOperand(2).getValueType());
1233 case ISD::SELECT_CC:
1236 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1237 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1238 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1239 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1240 ISD::CondCode CCCode =
1241 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1242 Action = TLI.getCondCodeAction(CCCode, OpVT);
1243 if (Action == TargetLowering::Legal) {
1244 if (Node->getOpcode() == ISD::SELECT_CC)
1245 Action = TLI.getOperationAction(Node->getOpcode(),
1246 Node->getValueType(0));
1248 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1254 // FIXME: Model these properly. LOAD and STORE are complicated, and
1255 // STORE expects the unlegalized operand in some cases.
1256 SimpleFinishLegalizing = false;
1258 case ISD::CALLSEQ_START:
1259 case ISD::CALLSEQ_END:
1260 // FIXME: This shouldn't be necessary. These nodes have special properties
1261 // dealing with the recursive nature of legalization. Removing this
1262 // special case should be done as part of making LegalizeDAG non-recursive.
1263 SimpleFinishLegalizing = false;
1265 case ISD::EXTRACT_ELEMENT:
1266 case ISD::FLT_ROUNDS_:
1268 case ISD::MERGE_VALUES:
1269 case ISD::EH_RETURN:
1270 case ISD::FRAME_TO_ARGS_OFFSET:
1271 case ISD::EH_SJLJ_SETJMP:
1272 case ISD::EH_SJLJ_LONGJMP:
1273 case ISD::EH_SJLJ_SETUP_DISPATCH:
1274 // These operations lie about being legal: when they claim to be legal,
1275 // they should actually be expanded.
1276 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1277 if (Action == TargetLowering::Legal)
1278 Action = TargetLowering::Expand;
1280 case ISD::INIT_TRAMPOLINE:
1281 case ISD::ADJUST_TRAMPOLINE:
1282 case ISD::FRAMEADDR:
1283 case ISD::RETURNADDR:
1284 // These operations lie about being legal: when they claim to be legal,
1285 // they should actually be custom-lowered.
1286 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1287 if (Action == TargetLowering::Legal)
1288 Action = TargetLowering::Custom;
1290 case ISD::READCYCLECOUNTER:
1291 // READCYCLECOUNTER returns an i64, even if type legalization might have
1292 // expanded that to several smaller types.
1293 Action = TLI.getOperationAction(Node->getOpcode(), MVT::i64);
1295 case ISD::READ_REGISTER:
1296 case ISD::WRITE_REGISTER:
1297 // Named register is legal in the DAG, but blocked by register name
1298 // selection if not implemented by target (to chose the correct register)
1299 // They'll be converted to Copy(To/From)Reg.
1300 Action = TargetLowering::Legal;
1302 case ISD::DEBUGTRAP:
1303 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1304 if (Action == TargetLowering::Expand) {
1305 // replace ISD::DEBUGTRAP with ISD::TRAP
1307 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1308 Node->getOperand(0));
1309 ReplaceNode(Node, NewVal.getNode());
1310 LegalizeOp(NewVal.getNode());
1316 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1317 Action = TargetLowering::Legal;
1319 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1324 if (SimpleFinishLegalizing) {
1325 SDNode *NewNode = Node;
1326 switch (Node->getOpcode()) {
1333 // Legalizing shifts/rotates requires adjusting the shift amount
1334 // to the appropriate width.
1335 if (!Node->getOperand(1).getValueType().isVector()) {
1337 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1338 Node->getOperand(1));
1339 HandleSDNode Handle(SAO);
1340 LegalizeOp(SAO.getNode());
1341 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1345 case ISD::SRL_PARTS:
1346 case ISD::SRA_PARTS:
1347 case ISD::SHL_PARTS:
1348 // Legalizing shifts/rotates requires adjusting the shift amount
1349 // to the appropriate width.
1350 if (!Node->getOperand(2).getValueType().isVector()) {
1352 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1353 Node->getOperand(2));
1354 HandleSDNode Handle(SAO);
1355 LegalizeOp(SAO.getNode());
1356 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1357 Node->getOperand(1),
1363 if (NewNode != Node) {
1364 ReplaceNode(Node, NewNode);
1368 case TargetLowering::Legal:
1370 case TargetLowering::Custom: {
1371 // FIXME: The handling for custom lowering with multiple results is
1373 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1374 if (Res.getNode()) {
1375 if (!(Res.getNode() != Node || Res.getResNo() != 0))
1378 if (Node->getNumValues() == 1) {
1379 // We can just directly replace this node with the lowered value.
1380 ReplaceNode(SDValue(Node, 0), Res);
1384 SmallVector<SDValue, 8> ResultVals;
1385 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1386 ResultVals.push_back(Res.getValue(i));
1387 ReplaceNode(Node, ResultVals.data());
1392 case TargetLowering::Expand:
1393 if (ExpandNode(Node))
1396 case TargetLowering::LibCall:
1397 ConvertNodeToLibcall(Node);
1399 case TargetLowering::Promote:
1405 switch (Node->getOpcode()) {
1412 llvm_unreachable("Do not know how to legalize this operator!");
1414 case ISD::CALLSEQ_START:
1415 case ISD::CALLSEQ_END:
1418 return LegalizeLoadOps(Node);
1421 return LegalizeStoreOps(Node);
1426 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1427 SDValue Vec = Op.getOperand(0);
1428 SDValue Idx = Op.getOperand(1);
1431 // Before we generate a new store to a temporary stack slot, see if there is
1432 // already one that we can use. There often is because when we scalarize
1433 // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1434 // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1435 // the vector. If all are expanded here, we don't want one store per vector
1437 SDValue StackPtr, Ch;
1438 for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1439 UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1441 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1442 if (ST->isIndexed() || ST->isTruncatingStore() ||
1443 ST->getValue() != Vec)
1446 // Make sure that nothing else could have stored into the destination of
1448 if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1451 StackPtr = ST->getBasePtr();
1452 Ch = SDValue(ST, 0);
1457 if (!Ch.getNode()) {
1458 // Store the value to a temporary stack slot, then LOAD the returned part.
1459 StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1460 Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1461 MachinePointerInfo(), false, false, 0);
1464 // Add the offset to the index.
1466 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1467 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1468 DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
1470 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy(DAG.getDataLayout()));
1471 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1475 if (Op.getValueType().isVector())
1476 NewLoad = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,
1477 MachinePointerInfo(), false, false, false, 0);
1479 NewLoad = DAG.getExtLoad(
1480 ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, MachinePointerInfo(),
1481 Vec.getValueType().getVectorElementType(), false, false, false, 0);
1483 // Replace the chain going out of the store, by the one out of the load.
1484 DAG.ReplaceAllUsesOfValueWith(Ch, SDValue(NewLoad.getNode(), 1));
1486 // We introduced a cycle though, so update the loads operands, making sure
1487 // to use the original store's chain as an incoming chain.
1488 SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1490 NewLoadOperands[0] = Ch;
1492 SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0);
1496 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1497 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1499 SDValue Vec = Op.getOperand(0);
1500 SDValue Part = Op.getOperand(1);
1501 SDValue Idx = Op.getOperand(2);
1504 // Store the value to a temporary stack slot, then LOAD the returned part.
1506 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1507 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1508 MachinePointerInfo PtrInfo =
1509 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1511 // First store the whole vector.
1512 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1515 // Then store the inserted part.
1517 // Add the offset to the index.
1519 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1521 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1522 DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
1523 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy(DAG.getDataLayout()));
1525 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1528 // Store the subvector.
1529 Ch = DAG.getStore(Ch, dl, Part, SubStackPtr,
1530 MachinePointerInfo(), false, false, 0);
1532 // Finally, load the updated vector.
1533 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1534 false, false, false, 0);
1537 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1538 // We can't handle this case efficiently. Allocate a sufficiently
1539 // aligned object on the stack, store each element into it, then load
1540 // the result as a vector.
1541 // Create the stack frame object.
1542 EVT VT = Node->getValueType(0);
1543 EVT EltVT = VT.getVectorElementType();
1545 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1546 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1547 MachinePointerInfo PtrInfo =
1548 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1550 // Emit a store of each element to the stack slot.
1551 SmallVector<SDValue, 8> Stores;
1552 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1553 // Store (in the right endianness) the elements to memory.
1554 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1555 // Ignore undef elements.
1556 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1558 unsigned Offset = TypeByteSize*i;
1560 SDValue Idx = DAG.getConstant(Offset, dl, FIPtr.getValueType());
1561 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1563 // If the destination vector element type is narrower than the source
1564 // element type, only store the bits necessary.
1565 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1566 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1567 Node->getOperand(i), Idx,
1568 PtrInfo.getWithOffset(Offset),
1569 EltVT, false, false, 0));
1571 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1572 Node->getOperand(i), Idx,
1573 PtrInfo.getWithOffset(Offset),
1578 if (!Stores.empty()) // Not all undef elements?
1579 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1581 StoreChain = DAG.getEntryNode();
1583 // Result is a load from the stack slot.
1584 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1585 false, false, false, 0);
1588 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1590 SDValue Tmp1 = Node->getOperand(0);
1591 SDValue Tmp2 = Node->getOperand(1);
1593 // Get the sign bit of the RHS. First obtain a value that has the same
1594 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1596 EVT FloatVT = Tmp2.getValueType();
1597 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1598 if (TLI.isTypeLegal(IVT)) {
1599 // Convert to an integer with the same sign bit.
1600 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1602 auto &DL = DAG.getDataLayout();
1603 // Store the float to memory, then load the sign part out as an integer.
1604 MVT LoadTy = TLI.getPointerTy(DL);
1605 // First create a temporary that is aligned for both the load and store.
1606 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1607 // Then store the float to it.
1609 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1611 if (DL.isBigEndian()) {
1612 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1613 // Load out a legal integer with the same sign bit as the float.
1614 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1615 false, false, false, 0);
1616 } else { // Little endian
1617 SDValue LoadPtr = StackPtr;
1618 // The float may be wider than the integer we are going to load. Advance
1619 // the pointer so that the loaded integer will contain the sign bit.
1620 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1621 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1622 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), LoadPtr,
1623 DAG.getConstant(ByteOffset, dl,
1624 LoadPtr.getValueType()));
1625 // Load a legal integer containing the sign bit.
1626 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1627 false, false, false, 0);
1628 // Move the sign bit to the top bit of the loaded integer.
1629 unsigned BitShift = LoadTy.getSizeInBits() -
1630 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1631 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1633 SignBit = DAG.getNode(
1634 ISD::SHL, dl, LoadTy, SignBit,
1635 DAG.getConstant(BitShift, dl,
1636 TLI.getShiftAmountTy(SignBit.getValueType(), DL)));
1639 // Now get the sign bit proper, by seeing whether the value is negative.
1640 SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
1642 DAG.getConstant(0, dl, SignBit.getValueType()),
1644 // Get the absolute value of the result.
1645 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1646 // Select between the nabs and abs value based on the sign bit of
1648 return DAG.getSelect(dl, AbsVal.getValueType(), SignBit,
1649 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1653 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1654 SmallVectorImpl<SDValue> &Results) {
1655 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1656 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1657 " not tell us which reg is the stack pointer!");
1659 EVT VT = Node->getValueType(0);
1660 SDValue Tmp1 = SDValue(Node, 0);
1661 SDValue Tmp2 = SDValue(Node, 1);
1662 SDValue Tmp3 = Node->getOperand(2);
1663 SDValue Chain = Tmp1.getOperand(0);
1665 // Chain the dynamic stack allocation so that it doesn't modify the stack
1666 // pointer when other instructions are using the stack.
1667 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
1669 SDValue Size = Tmp2.getOperand(1);
1670 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1671 Chain = SP.getValue(1);
1672 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1673 unsigned StackAlign =
1674 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
1675 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1676 if (Align > StackAlign)
1677 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1678 DAG.getConstant(-(uint64_t)Align, dl, VT));
1679 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1681 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
1682 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
1684 Results.push_back(Tmp1);
1685 Results.push_back(Tmp2);
1688 /// Legalize a SETCC with given LHS and RHS and condition code CC on the current
1691 /// If the SETCC has been legalized using AND / OR, then the legalized node
1692 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1693 /// will be set to false.
1695 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1696 /// then the values of LHS and RHS will be swapped, CC will be set to the
1697 /// new condition, and NeedInvert will be set to false.
1699 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1700 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1701 /// will be set to true. The caller must invert the result of the SETCC with
1702 /// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1703 /// of a true/false result.
1705 /// \returns true if the SetCC has been legalized, false if it hasn't.
1706 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1707 SDValue &LHS, SDValue &RHS,
1711 MVT OpVT = LHS.getSimpleValueType();
1712 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1714 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1715 default: llvm_unreachable("Unknown condition code action!");
1716 case TargetLowering::Legal:
1719 case TargetLowering::Expand: {
1720 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1721 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1722 std::swap(LHS, RHS);
1723 CC = DAG.getCondCode(InvCC);
1726 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1729 default: llvm_unreachable("Don't know how to expand this condition!");
1731 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1732 == TargetLowering::Legal
1733 && "If SETO is expanded, SETOEQ must be legal!");
1734 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1736 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1737 == TargetLowering::Legal
1738 && "If SETUO is expanded, SETUNE must be legal!");
1739 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1752 // If we are floating point, assign and break, otherwise fall through.
1753 if (!OpVT.isInteger()) {
1754 // We can use the 4th bit to tell if we are the unordered
1755 // or ordered version of the opcode.
1756 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1757 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1758 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1761 // Fallthrough if we are unsigned integer.
1766 // We only support using the inverted operation, which is computed above
1767 // and not a different manner of supporting expanding these cases.
1768 llvm_unreachable("Don't know how to expand this condition!");
1771 // Try inverting the result of the inverse condition.
1772 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1773 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1774 CC = DAG.getCondCode(InvCC);
1778 // If inverting the condition didn't work then we have no means to expand
1780 llvm_unreachable("Don't know how to expand this condition!");
1783 SDValue SetCC1, SetCC2;
1784 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1785 // If we aren't the ordered or unorder operation,
1786 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1787 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1788 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1790 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1791 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1792 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1794 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1803 /// Emit a store/load combination to the stack. This stores
1804 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1805 /// a load from the stack slot to DestVT, extending it if needed.
1806 /// The resultant code need not be legal.
1807 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1811 // Create the stack frame object.
1812 unsigned SrcAlign = DAG.getDataLayout().getPrefTypeAlignment(
1813 SrcOp.getValueType().getTypeForEVT(*DAG.getContext()));
1814 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1816 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1817 int SPFI = StackPtrFI->getIndex();
1818 MachinePointerInfo PtrInfo =
1819 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
1821 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1822 unsigned SlotSize = SlotVT.getSizeInBits();
1823 unsigned DestSize = DestVT.getSizeInBits();
1824 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1825 unsigned DestAlign = DAG.getDataLayout().getPrefTypeAlignment(DestType);
1827 // Emit a store to the stack slot. Use a truncstore if the input value is
1828 // later than DestVT.
1831 if (SrcSize > SlotSize)
1832 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1833 PtrInfo, SlotVT, false, false, SrcAlign);
1835 assert(SrcSize == SlotSize && "Invalid store");
1836 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1837 PtrInfo, false, false, SrcAlign);
1840 // Result is a load from the stack slot.
1841 if (SlotSize == DestSize)
1842 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1843 false, false, false, DestAlign);
1845 assert(SlotSize < DestSize && "Unknown extension!");
1846 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1847 PtrInfo, SlotVT, false, false, false, DestAlign);
1850 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1852 // Create a vector sized/aligned stack slot, store the value to element #0,
1853 // then load the whole vector back out.
1854 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1856 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1857 int SPFI = StackPtrFI->getIndex();
1859 SDValue Ch = DAG.getTruncStore(
1860 DAG.getEntryNode(), dl, Node->getOperand(0), StackPtr,
1861 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI),
1862 Node->getValueType(0).getVectorElementType(), false, false, 0);
1864 Node->getValueType(0), dl, Ch, StackPtr,
1865 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI), false,
1870 ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
1871 const TargetLowering &TLI, SDValue &Res) {
1872 unsigned NumElems = Node->getNumOperands();
1874 EVT VT = Node->getValueType(0);
1876 // Try to group the scalars into pairs, shuffle the pairs together, then
1877 // shuffle the pairs of pairs together, etc. until the vector has
1878 // been built. This will work only if all of the necessary shuffle masks
1881 // We do this in two phases; first to check the legality of the shuffles,
1882 // and next, assuming that all shuffles are legal, to create the new nodes.
1883 for (int Phase = 0; Phase < 2; ++Phase) {
1884 SmallVector<std::pair<SDValue, SmallVector<int, 16> >, 16> IntermedVals,
1886 for (unsigned i = 0; i < NumElems; ++i) {
1887 SDValue V = Node->getOperand(i);
1888 if (V.getOpcode() == ISD::UNDEF)
1893 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1894 IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
1897 while (IntermedVals.size() > 2) {
1898 NewIntermedVals.clear();
1899 for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1900 // This vector and the next vector are shuffled together (simply to
1901 // append the one to the other).
1902 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1904 SmallVector<int, 16> FinalIndices;
1905 FinalIndices.reserve(IntermedVals[i].second.size() +
1906 IntermedVals[i+1].second.size());
1909 for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1912 FinalIndices.push_back(IntermedVals[i].second[j]);
1914 for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1916 ShuffleVec[k] = NumElems + j;
1917 FinalIndices.push_back(IntermedVals[i+1].second[j]);
1922 Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
1923 IntermedVals[i+1].first,
1925 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1927 NewIntermedVals.push_back(
1928 std::make_pair(Shuffle, std::move(FinalIndices)));
1931 // If we had an odd number of defined values, then append the last
1932 // element to the array of new vectors.
1933 if ((IntermedVals.size() & 1) != 0)
1934 NewIntermedVals.push_back(IntermedVals.back());
1936 IntermedVals.swap(NewIntermedVals);
1939 assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1940 "Invalid number of intermediate vectors");
1941 SDValue Vec1 = IntermedVals[0].first;
1943 if (IntermedVals.size() > 1)
1944 Vec2 = IntermedVals[1].first;
1946 Vec2 = DAG.getUNDEF(VT);
1948 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1949 for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1950 ShuffleVec[IntermedVals[0].second[i]] = i;
1951 for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1952 ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1955 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1956 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1963 /// Expand a BUILD_VECTOR node on targets that don't
1964 /// support the operation, but do support the resultant vector type.
1965 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1966 unsigned NumElems = Node->getNumOperands();
1967 SDValue Value1, Value2;
1969 EVT VT = Node->getValueType(0);
1970 EVT OpVT = Node->getOperand(0).getValueType();
1971 EVT EltVT = VT.getVectorElementType();
1973 // If the only non-undef value is the low element, turn this into a
1974 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1975 bool isOnlyLowElement = true;
1976 bool MoreThanTwoValues = false;
1977 bool isConstant = true;
1978 for (unsigned i = 0; i < NumElems; ++i) {
1979 SDValue V = Node->getOperand(i);
1980 if (V.getOpcode() == ISD::UNDEF)
1983 isOnlyLowElement = false;
1984 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1987 if (!Value1.getNode()) {
1989 } else if (!Value2.getNode()) {
1992 } else if (V != Value1 && V != Value2) {
1993 MoreThanTwoValues = true;
1997 if (!Value1.getNode())
1998 return DAG.getUNDEF(VT);
2000 if (isOnlyLowElement)
2001 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
2003 // If all elements are constants, create a load from the constant pool.
2005 SmallVector<Constant*, 16> CV;
2006 for (unsigned i = 0, e = NumElems; i != e; ++i) {
2007 if (ConstantFPSDNode *V =
2008 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
2009 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
2010 } else if (ConstantSDNode *V =
2011 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
2013 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
2015 // If OpVT and EltVT don't match, EltVT is not legal and the
2016 // element values have been promoted/truncated earlier. Undo this;
2017 // we don't want a v16i8 to become a v16i32 for example.
2018 const ConstantInt *CI = V->getConstantIntValue();
2019 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
2020 CI->getZExtValue()));
2023 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
2024 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
2025 CV.push_back(UndefValue::get(OpNTy));
2028 Constant *CP = ConstantVector::get(CV);
2030 DAG.getConstantPool(CP, TLI.getPointerTy(DAG.getDataLayout()));
2031 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2033 VT, dl, DAG.getEntryNode(), CPIdx,
2034 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2035 false, false, Alignment);
2038 SmallSet<SDValue, 16> DefinedValues;
2039 for (unsigned i = 0; i < NumElems; ++i) {
2040 if (Node->getOperand(i).getOpcode() == ISD::UNDEF)
2042 DefinedValues.insert(Node->getOperand(i));
2045 if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
2046 if (!MoreThanTwoValues) {
2047 SmallVector<int, 8> ShuffleVec(NumElems, -1);
2048 for (unsigned i = 0; i < NumElems; ++i) {
2049 SDValue V = Node->getOperand(i);
2050 if (V.getOpcode() == ISD::UNDEF)
2052 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2054 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
2055 // Get the splatted value into the low element of a vector register.
2056 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2058 if (Value2.getNode())
2059 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2061 Vec2 = DAG.getUNDEF(VT);
2063 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2064 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2068 if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
2073 // Otherwise, we can't handle this case efficiently.
2074 return ExpandVectorBuildThroughStack(Node);
2077 // Expand a node into a call to a libcall. If the result value
2078 // does not fit into a register, return the lo part and set the hi part to the
2079 // by-reg argument. If it does fit into a single register, return the result
2080 // and leave the Hi part unset.
2081 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2083 TargetLowering::ArgListTy Args;
2084 TargetLowering::ArgListEntry Entry;
2085 for (const SDValue &Op : Node->op_values()) {
2086 EVT ArgVT = Op.getValueType();
2087 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2090 Entry.isSExt = isSigned;
2091 Entry.isZExt = !isSigned;
2092 Args.push_back(Entry);
2094 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2095 TLI.getPointerTy(DAG.getDataLayout()));
2097 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2099 // By default, the input chain to this libcall is the entry node of the
2100 // function. If the libcall is going to be emitted as a tail call then
2101 // TLI.isUsedByReturnOnly will change it to the right chain if the return
2102 // node which is being folded has a non-entry input chain.
2103 SDValue InChain = DAG.getEntryNode();
2105 // isTailCall may be true since the callee does not reference caller stack
2106 // frame. Check if it's in the right position.
2107 SDValue TCChain = InChain;
2108 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
2112 TargetLowering::CallLoweringInfo CLI(DAG);
2113 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2114 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2115 .setTailCall(isTailCall).setSExtResult(isSigned).setZExtResult(!isSigned);
2117 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2119 if (!CallInfo.second.getNode())
2120 // It's a tailcall, return the chain (which is the DAG root).
2121 return DAG.getRoot();
2123 return CallInfo.first;
2126 /// Generate a libcall taking the given operands as arguments
2127 /// and returning a result of type RetVT.
2128 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2129 const SDValue *Ops, unsigned NumOps,
2130 bool isSigned, SDLoc dl) {
2131 TargetLowering::ArgListTy Args;
2132 Args.reserve(NumOps);
2134 TargetLowering::ArgListEntry Entry;
2135 for (unsigned i = 0; i != NumOps; ++i) {
2136 Entry.Node = Ops[i];
2137 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2138 Entry.isSExt = isSigned;
2139 Entry.isZExt = !isSigned;
2140 Args.push_back(Entry);
2142 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2143 TLI.getPointerTy(DAG.getDataLayout()));
2145 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2147 TargetLowering::CallLoweringInfo CLI(DAG);
2148 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
2149 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2150 .setSExtResult(isSigned).setZExtResult(!isSigned);
2152 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
2154 return CallInfo.first;
2157 // Expand a node into a call to a libcall. Similar to
2158 // ExpandLibCall except that the first operand is the in-chain.
2159 std::pair<SDValue, SDValue>
2160 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2163 SDValue InChain = Node->getOperand(0);
2165 TargetLowering::ArgListTy Args;
2166 TargetLowering::ArgListEntry Entry;
2167 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2168 EVT ArgVT = Node->getOperand(i).getValueType();
2169 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2170 Entry.Node = Node->getOperand(i);
2172 Entry.isSExt = isSigned;
2173 Entry.isZExt = !isSigned;
2174 Args.push_back(Entry);
2176 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2177 TLI.getPointerTy(DAG.getDataLayout()));
2179 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2181 TargetLowering::CallLoweringInfo CLI(DAG);
2182 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2183 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2184 .setSExtResult(isSigned).setZExtResult(!isSigned);
2186 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2191 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2192 RTLIB::Libcall Call_F32,
2193 RTLIB::Libcall Call_F64,
2194 RTLIB::Libcall Call_F80,
2195 RTLIB::Libcall Call_F128,
2196 RTLIB::Libcall Call_PPCF128) {
2198 switch (Node->getSimpleValueType(0).SimpleTy) {
2199 default: llvm_unreachable("Unexpected request for libcall!");
2200 case MVT::f32: LC = Call_F32; break;
2201 case MVT::f64: LC = Call_F64; break;
2202 case MVT::f80: LC = Call_F80; break;
2203 case MVT::f128: LC = Call_F128; break;
2204 case MVT::ppcf128: LC = Call_PPCF128; break;
2206 return ExpandLibCall(LC, Node, false);
2209 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2210 RTLIB::Libcall Call_I8,
2211 RTLIB::Libcall Call_I16,
2212 RTLIB::Libcall Call_I32,
2213 RTLIB::Libcall Call_I64,
2214 RTLIB::Libcall Call_I128) {
2216 switch (Node->getSimpleValueType(0).SimpleTy) {
2217 default: llvm_unreachable("Unexpected request for libcall!");
2218 case MVT::i8: LC = Call_I8; break;
2219 case MVT::i16: LC = Call_I16; break;
2220 case MVT::i32: LC = Call_I32; break;
2221 case MVT::i64: LC = Call_I64; break;
2222 case MVT::i128: LC = Call_I128; break;
2224 return ExpandLibCall(LC, Node, isSigned);
2227 /// Issue libcalls to __{u}divmod to compute div / rem pairs.
2229 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2230 SmallVectorImpl<SDValue> &Results) {
2231 unsigned Opcode = Node->getOpcode();
2232 bool isSigned = Opcode == ISD::SDIVREM;
2235 switch (Node->getSimpleValueType(0).SimpleTy) {
2236 default: llvm_unreachable("Unexpected request for libcall!");
2237 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2238 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2239 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2240 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2241 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2244 // The input chain to this libcall is the entry node of the function.
2245 // Legalizing the call will automatically add the previous call to the
2247 SDValue InChain = DAG.getEntryNode();
2249 EVT RetVT = Node->getValueType(0);
2250 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2252 TargetLowering::ArgListTy Args;
2253 TargetLowering::ArgListEntry Entry;
2254 for (const SDValue &Op : Node->op_values()) {
2255 EVT ArgVT = Op.getValueType();
2256 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2259 Entry.isSExt = isSigned;
2260 Entry.isZExt = !isSigned;
2261 Args.push_back(Entry);
2264 // Also pass the return address of the remainder.
2265 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2267 Entry.Ty = RetTy->getPointerTo();
2268 Entry.isSExt = isSigned;
2269 Entry.isZExt = !isSigned;
2270 Args.push_back(Entry);
2272 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2273 TLI.getPointerTy(DAG.getDataLayout()));
2276 TargetLowering::CallLoweringInfo CLI(DAG);
2277 CLI.setDebugLoc(dl).setChain(InChain)
2278 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2279 .setSExtResult(isSigned).setZExtResult(!isSigned);
2281 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2283 // Remainder is loaded back from the stack frame.
2284 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2285 MachinePointerInfo(), false, false, false, 0);
2286 Results.push_back(CallInfo.first);
2287 Results.push_back(Rem);
2290 /// Return true if sincos libcall is available.
2291 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2293 switch (Node->getSimpleValueType(0).SimpleTy) {
2294 default: llvm_unreachable("Unexpected request for libcall!");
2295 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2296 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2297 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2298 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2299 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2301 return TLI.getLibcallName(LC) != nullptr;
2304 /// Return true if sincos libcall is available and can be used to combine sin
2306 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2307 const TargetMachine &TM) {
2308 if (!isSinCosLibcallAvailable(Node, TLI))
2310 // GNU sin/cos functions set errno while sincos does not. Therefore
2311 // combining sin and cos is only safe if unsafe-fpmath is enabled.
2312 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2313 if (isGNU && !TM.Options.UnsafeFPMath)
2318 /// Only issue sincos libcall if both sin and cos are needed.
2319 static bool useSinCos(SDNode *Node) {
2320 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2321 ? ISD::FCOS : ISD::FSIN;
2323 SDValue Op0 = Node->getOperand(0);
2324 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2325 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2329 // The other user might have been turned into sincos already.
2330 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2336 /// Issue libcalls to sincos to compute sin / cos pairs.
2338 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2339 SmallVectorImpl<SDValue> &Results) {
2341 switch (Node->getSimpleValueType(0).SimpleTy) {
2342 default: llvm_unreachable("Unexpected request for libcall!");
2343 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2344 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2345 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2346 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2347 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2350 // The input chain to this libcall is the entry node of the function.
2351 // Legalizing the call will automatically add the previous call to the
2353 SDValue InChain = DAG.getEntryNode();
2355 EVT RetVT = Node->getValueType(0);
2356 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2358 TargetLowering::ArgListTy Args;
2359 TargetLowering::ArgListEntry Entry;
2361 // Pass the argument.
2362 Entry.Node = Node->getOperand(0);
2364 Entry.isSExt = false;
2365 Entry.isZExt = false;
2366 Args.push_back(Entry);
2368 // Pass the return address of sin.
2369 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2370 Entry.Node = SinPtr;
2371 Entry.Ty = RetTy->getPointerTo();
2372 Entry.isSExt = false;
2373 Entry.isZExt = false;
2374 Args.push_back(Entry);
2376 // Also pass the return address of the cos.
2377 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2378 Entry.Node = CosPtr;
2379 Entry.Ty = RetTy->getPointerTo();
2380 Entry.isSExt = false;
2381 Entry.isZExt = false;
2382 Args.push_back(Entry);
2384 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2385 TLI.getPointerTy(DAG.getDataLayout()));
2388 TargetLowering::CallLoweringInfo CLI(DAG);
2389 CLI.setDebugLoc(dl).setChain(InChain)
2390 .setCallee(TLI.getLibcallCallingConv(LC),
2391 Type::getVoidTy(*DAG.getContext()), Callee, std::move(Args), 0);
2393 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2395 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2396 MachinePointerInfo(), false, false, false, 0));
2397 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2398 MachinePointerInfo(), false, false, false, 0));
2401 /// This function is responsible for legalizing a
2402 /// INT_TO_FP operation of the specified operand when the target requests that
2403 /// we expand it. At this point, we know that the result and operand types are
2404 /// legal for the target.
2405 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2409 // TODO: Should any fast-math-flags be set for the created nodes?
2411 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2412 // simple 32-bit [signed|unsigned] integer to float/double expansion
2414 // Get the stack frame index of a 8 byte buffer.
2415 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2417 // word offset constant for Hi/Lo address computation
2418 SDValue WordOff = DAG.getConstant(sizeof(int), dl,
2419 StackSlot.getValueType());
2420 // set up Hi and Lo (into buffer) address based on endian
2421 SDValue Hi = StackSlot;
2422 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2423 StackSlot, WordOff);
2424 if (DAG.getDataLayout().isLittleEndian())
2427 // if signed map to unsigned space
2430 // constant used to invert sign bit (signed to unsigned mapping)
2431 SDValue SignBit = DAG.getConstant(0x80000000u, dl, MVT::i32);
2432 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2436 // store the lo of the constructed double - based on integer input
2437 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2438 Op0Mapped, Lo, MachinePointerInfo(),
2440 // initial hi portion of constructed double
2441 SDValue InitialHi = DAG.getConstant(0x43300000u, dl, MVT::i32);
2442 // store the hi of the constructed double - biased exponent
2443 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2444 MachinePointerInfo(),
2446 // load the constructed double
2447 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2448 MachinePointerInfo(), false, false, false, 0);
2449 // FP constant to bias correct the final result
2450 SDValue Bias = DAG.getConstantFP(isSigned ?
2451 BitsToDouble(0x4330000080000000ULL) :
2452 BitsToDouble(0x4330000000000000ULL),
2454 // subtract the bias
2455 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2458 // handle final rounding
2459 if (DestVT == MVT::f64) {
2462 } else if (DestVT.bitsLT(MVT::f64)) {
2463 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2464 DAG.getIntPtrConstant(0, dl));
2465 } else if (DestVT.bitsGT(MVT::f64)) {
2466 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2470 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2471 // Code below here assumes !isSigned without checking again.
2473 // Implementation of unsigned i64 to f64 following the algorithm in
2474 // __floatundidf in compiler_rt. This implementation has the advantage
2475 // of performing rounding correctly, both in the default rounding mode
2476 // and in all alternate rounding modes.
2477 // TODO: Generalize this for use with other types.
2478 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2480 DAG.getConstant(UINT64_C(0x4330000000000000), dl, MVT::i64);
2481 SDValue TwoP84PlusTwoP52 =
2482 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), dl,
2485 DAG.getConstant(UINT64_C(0x4530000000000000), dl, MVT::i64);
2487 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2488 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2489 DAG.getConstant(32, dl, MVT::i64));
2490 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2491 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2492 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2493 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2494 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2496 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2499 // Implementation of unsigned i64 to f32.
2500 // TODO: Generalize this for use with other types.
2501 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2502 // For unsigned conversions, convert them to signed conversions using the
2503 // algorithm from the x86_64 __floatundidf in compiler_rt.
2505 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2507 SDValue ShiftConst = DAG.getConstant(
2508 1, dl, TLI.getShiftAmountTy(Op0.getValueType(), DAG.getDataLayout()));
2509 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2510 SDValue AndConst = DAG.getConstant(1, dl, MVT::i64);
2511 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2512 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2514 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2515 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2517 // TODO: This really should be implemented using a branch rather than a
2518 // select. We happen to get lucky and machinesink does the right
2519 // thing most of the time. This would be a good candidate for a
2520 //pseudo-op, or, even better, for whole-function isel.
2521 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2522 Op0, DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
2523 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2526 // Otherwise, implement the fully general conversion.
2528 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2529 DAG.getConstant(UINT64_C(0xfffffffffffff800), dl, MVT::i64));
2530 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2531 DAG.getConstant(UINT64_C(0x800), dl, MVT::i64));
2532 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2533 DAG.getConstant(UINT64_C(0x7ff), dl, MVT::i64));
2534 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), And2,
2535 DAG.getConstant(UINT64_C(0), dl, MVT::i64),
2537 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2538 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), Op0,
2539 DAG.getConstant(UINT64_C(0x0020000000000000), dl,
2542 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2543 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType(), DAG.getDataLayout());
2545 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2546 DAG.getConstant(32, dl, SHVT));
2547 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2548 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2550 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), dl,
2552 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2553 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2554 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2555 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2556 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2557 DAG.getIntPtrConstant(0, dl));
2560 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2562 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2564 DAG.getConstant(0, dl, Op0.getValueType()),
2566 SDValue Zero = DAG.getIntPtrConstant(0, dl),
2567 Four = DAG.getIntPtrConstant(4, dl);
2568 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2569 SignSet, Four, Zero);
2571 // If the sign bit of the integer is set, the large number will be treated
2572 // as a negative number. To counteract this, the dynamic code adds an
2573 // offset depending on the data type.
2575 switch (Op0.getSimpleValueType().SimpleTy) {
2576 default: llvm_unreachable("Unsupported integer type!");
2577 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2578 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2579 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2580 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2582 if (DAG.getDataLayout().isLittleEndian())
2584 Constant *FudgeFactor = ConstantInt::get(
2585 Type::getInt64Ty(*DAG.getContext()), FF);
2588 DAG.getConstantPool(FudgeFactor, TLI.getPointerTy(DAG.getDataLayout()));
2589 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2590 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2591 Alignment = std::min(Alignment, 4u);
2593 if (DestVT == MVT::f32)
2594 FudgeInReg = DAG.getLoad(
2595 MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2596 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2597 false, false, Alignment);
2599 SDValue Load = DAG.getExtLoad(
2600 ISD::EXTLOAD, dl, DestVT, DAG.getEntryNode(), CPIdx,
2601 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
2602 false, false, false, Alignment);
2603 HandleSDNode Handle(Load);
2604 LegalizeOp(Load.getNode());
2605 FudgeInReg = Handle.getValue();
2608 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2611 /// This function is responsible for legalizing a
2612 /// *INT_TO_FP operation of the specified operand when the target requests that
2613 /// we promote it. At this point, we know that the result and operand types are
2614 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2615 /// operation that takes a larger input.
2616 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2620 // First step, figure out the appropriate *INT_TO_FP operation to use.
2621 EVT NewInTy = LegalOp.getValueType();
2623 unsigned OpToUse = 0;
2625 // Scan for the appropriate larger type to use.
2627 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2628 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2630 // If the target supports SINT_TO_FP of this type, use it.
2631 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2632 OpToUse = ISD::SINT_TO_FP;
2635 if (isSigned) continue;
2637 // If the target supports UINT_TO_FP of this type, use it.
2638 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2639 OpToUse = ISD::UINT_TO_FP;
2643 // Otherwise, try a larger type.
2646 // Okay, we found the operation and type to use. Zero extend our input to the
2647 // desired type then run the operation on it.
2648 return DAG.getNode(OpToUse, dl, DestVT,
2649 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2650 dl, NewInTy, LegalOp));
2653 /// This function is responsible for legalizing a
2654 /// FP_TO_*INT operation of the specified operand when the target requests that
2655 /// we promote it. At this point, we know that the result and operand types are
2656 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2657 /// operation that returns a larger result.
2658 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2662 // First step, figure out the appropriate FP_TO*INT operation to use.
2663 EVT NewOutTy = DestVT;
2665 unsigned OpToUse = 0;
2667 // Scan for the appropriate larger type to use.
2669 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2670 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2672 // A larger signed type can hold all unsigned values of the requested type,
2673 // so using FP_TO_SINT is valid
2674 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2675 OpToUse = ISD::FP_TO_SINT;
2679 // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2680 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2681 OpToUse = ISD::FP_TO_UINT;
2685 // Otherwise, try a larger type.
2689 // Okay, we found the operation and type to use.
2690 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2692 // Truncate the result of the extended FP_TO_*INT operation to the desired
2694 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2697 /// Open code the operations for BSWAP of the specified operation.
2698 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2699 EVT VT = Op.getValueType();
2700 EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2701 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2702 switch (VT.getSimpleVT().SimpleTy) {
2703 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2705 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2706 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2707 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2709 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2710 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2711 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2712 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2713 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2714 DAG.getConstant(0xFF0000, dl, VT));
2715 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
2716 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2717 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2718 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2720 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2721 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2722 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2723 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2724 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2725 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2726 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2727 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2728 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7,
2729 DAG.getConstant(255ULL<<48, dl, VT));
2730 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6,
2731 DAG.getConstant(255ULL<<40, dl, VT));
2732 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5,
2733 DAG.getConstant(255ULL<<32, dl, VT));
2734 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4,
2735 DAG.getConstant(255ULL<<24, dl, VT));
2736 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2737 DAG.getConstant(255ULL<<16, dl, VT));
2738 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2,
2739 DAG.getConstant(255ULL<<8 , dl, VT));
2740 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2741 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2742 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2743 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2744 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2745 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2746 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2750 /// Expand the specified bitcount instruction into operations.
2751 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2754 default: llvm_unreachable("Cannot expand this yet!");
2756 EVT VT = Op.getValueType();
2757 EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2758 unsigned Len = VT.getSizeInBits();
2760 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2761 "CTPOP not implemented for this type.");
2763 // This is the "best" algorithm from
2764 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2766 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)),
2768 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)),
2770 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)),
2772 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)),
2775 // v = v - ((v >> 1) & 0x55555555...)
2776 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2777 DAG.getNode(ISD::AND, dl, VT,
2778 DAG.getNode(ISD::SRL, dl, VT, Op,
2779 DAG.getConstant(1, dl, ShVT)),
2781 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2782 Op = DAG.getNode(ISD::ADD, dl, VT,
2783 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2784 DAG.getNode(ISD::AND, dl, VT,
2785 DAG.getNode(ISD::SRL, dl, VT, Op,
2786 DAG.getConstant(2, dl, ShVT)),
2788 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2789 Op = DAG.getNode(ISD::AND, dl, VT,
2790 DAG.getNode(ISD::ADD, dl, VT, Op,
2791 DAG.getNode(ISD::SRL, dl, VT, Op,
2792 DAG.getConstant(4, dl, ShVT))),
2794 // v = (v * 0x01010101...) >> (Len - 8)
2795 Op = DAG.getNode(ISD::SRL, dl, VT,
2796 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2797 DAG.getConstant(Len - 8, dl, ShVT));
2801 case ISD::CTLZ_ZERO_UNDEF:
2802 // This trivially expands to CTLZ.
2803 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2805 // for now, we do this:
2806 // x = x | (x >> 1);
2807 // x = x | (x >> 2);
2809 // x = x | (x >>16);
2810 // x = x | (x >>32); // for 64-bit input
2811 // return popcount(~x);
2813 // Ref: "Hacker's Delight" by Henry Warren
2814 EVT VT = Op.getValueType();
2815 EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2816 unsigned len = VT.getSizeInBits();
2817 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2818 SDValue Tmp3 = DAG.getConstant(1ULL << i, dl, ShVT);
2819 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2820 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2822 Op = DAG.getNOT(dl, Op, VT);
2823 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2825 case ISD::CTTZ_ZERO_UNDEF:
2826 // This trivially expands to CTTZ.
2827 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2829 // for now, we use: { return popcount(~x & (x - 1)); }
2830 // unless the target has ctlz but not ctpop, in which case we use:
2831 // { return 32 - nlz(~x & (x-1)); }
2832 // Ref: "Hacker's Delight" by Henry Warren
2833 EVT VT = Op.getValueType();
2834 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2835 DAG.getNOT(dl, Op, VT),
2836 DAG.getNode(ISD::SUB, dl, VT, Op,
2837 DAG.getConstant(1, dl, VT)));
2838 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2839 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2840 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2841 return DAG.getNode(ISD::SUB, dl, VT,
2842 DAG.getConstant(VT.getSizeInBits(), dl, VT),
2843 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2844 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2849 bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2850 SmallVector<SDValue, 8> Results;
2852 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2854 switch (Node->getOpcode()) {
2857 case ISD::CTLZ_ZERO_UNDEF:
2859 case ISD::CTTZ_ZERO_UNDEF:
2860 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2861 Results.push_back(Tmp1);
2864 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2866 case ISD::FRAMEADDR:
2867 case ISD::RETURNADDR:
2868 case ISD::FRAME_TO_ARGS_OFFSET:
2869 Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
2871 case ISD::FLT_ROUNDS_:
2872 Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0)));
2874 case ISD::EH_RETURN:
2878 case ISD::EH_SJLJ_LONGJMP:
2879 // If the target didn't expand these, there's nothing to do, so just
2880 // preserve the chain and be done.
2881 Results.push_back(Node->getOperand(0));
2883 case ISD::READCYCLECOUNTER:
2884 // If the target didn't expand this, just return 'zero' and preserve the
2886 Results.append(Node->getNumValues() - 1,
2887 DAG.getConstant(0, dl, Node->getValueType(0)));
2888 Results.push_back(Node->getOperand(0));
2890 case ISD::EH_SJLJ_SETJMP:
2891 // If the target didn't expand this, just return 'zero' and preserve the
2893 Results.push_back(DAG.getConstant(0, dl, MVT::i32));
2894 Results.push_back(Node->getOperand(0));
2896 case ISD::ATOMIC_LOAD: {
2897 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2898 SDValue Zero = DAG.getConstant(0, dl, Node->getValueType(0));
2899 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2900 SDValue Swap = DAG.getAtomicCmpSwap(
2901 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2902 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
2903 cast<AtomicSDNode>(Node)->getMemOperand(),
2904 cast<AtomicSDNode>(Node)->getOrdering(),
2905 cast<AtomicSDNode>(Node)->getOrdering(),
2906 cast<AtomicSDNode>(Node)->getSynchScope());
2907 Results.push_back(Swap.getValue(0));
2908 Results.push_back(Swap.getValue(1));
2911 case ISD::ATOMIC_STORE: {
2912 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2913 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2914 cast<AtomicSDNode>(Node)->getMemoryVT(),
2915 Node->getOperand(0),
2916 Node->getOperand(1), Node->getOperand(2),
2917 cast<AtomicSDNode>(Node)->getMemOperand(),
2918 cast<AtomicSDNode>(Node)->getOrdering(),
2919 cast<AtomicSDNode>(Node)->getSynchScope());
2920 Results.push_back(Swap.getValue(1));
2923 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
2924 // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
2925 // splits out the success value as a comparison. Expanding the resulting
2926 // ATOMIC_CMP_SWAP will produce a libcall.
2927 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2928 SDValue Res = DAG.getAtomicCmpSwap(
2929 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2930 Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
2931 Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand(),
2932 cast<AtomicSDNode>(Node)->getSuccessOrdering(),
2933 cast<AtomicSDNode>(Node)->getFailureOrdering(),
2934 cast<AtomicSDNode>(Node)->getSynchScope());
2936 SDValue Success = DAG.getSetCC(SDLoc(Node), Node->getValueType(1),
2937 Res, Node->getOperand(2), ISD::SETEQ);
2939 Results.push_back(Res.getValue(0));
2940 Results.push_back(Success);
2941 Results.push_back(Res.getValue(1));
2944 case ISD::DYNAMIC_STACKALLOC:
2945 ExpandDYNAMIC_STACKALLOC(Node, Results);
2947 case ISD::MERGE_VALUES:
2948 for (unsigned i = 0; i < Node->getNumValues(); i++)
2949 Results.push_back(Node->getOperand(i));
2952 EVT VT = Node->getValueType(0);
2954 Results.push_back(DAG.getConstant(0, dl, VT));
2956 assert(VT.isFloatingPoint() && "Unknown value type!");
2957 Results.push_back(DAG.getConstantFP(0, dl, VT));
2963 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2964 Node->getValueType(0), dl);
2965 Results.push_back(Tmp1);
2967 case ISD::FP_EXTEND:
2968 Tmp1 = EmitStackConvert(Node->getOperand(0),
2969 Node->getOperand(0).getValueType(),
2970 Node->getValueType(0), dl);
2971 Results.push_back(Tmp1);
2973 case ISD::SIGN_EXTEND_INREG: {
2974 // NOTE: we could fall back on load/store here too for targets without
2975 // SAR. However, it is doubtful that any exist.
2976 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2977 EVT VT = Node->getValueType(0);
2978 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2981 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2982 ExtraVT.getScalarType().getSizeInBits();
2983 SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
2984 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2985 Node->getOperand(0), ShiftCst);
2986 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2987 Results.push_back(Tmp1);
2990 case ISD::FP_ROUND_INREG: {
2991 // The only way we can lower this is to turn it into a TRUNCSTORE,
2992 // EXTLOAD pair, targeting a temporary location (a stack slot).
2994 // NOTE: there is a choice here between constantly creating new stack
2995 // slots and always reusing the same one. We currently always create
2996 // new ones, as reuse may inhibit scheduling.
2997 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2998 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2999 Node->getValueType(0), dl);
3000 Results.push_back(Tmp1);
3003 case ISD::SINT_TO_FP:
3004 case ISD::UINT_TO_FP:
3005 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3006 Node->getOperand(0), Node->getValueType(0), dl);
3007 Results.push_back(Tmp1);
3009 case ISD::FP_TO_SINT:
3010 if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
3011 Results.push_back(Tmp1);
3013 case ISD::FP_TO_UINT: {
3014 SDValue True, False;
3015 EVT VT = Node->getOperand(0).getValueType();
3016 EVT NVT = Node->getValueType(0);
3017 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
3018 APInt::getNullValue(VT.getSizeInBits()));
3019 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3020 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3021 Tmp1 = DAG.getConstantFP(apf, dl, VT);
3022 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
3023 Node->getOperand(0),
3025 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3026 // TODO: Should any fast-math-flags be set for the FSUB?
3027 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3028 DAG.getNode(ISD::FSUB, dl, VT,
3029 Node->getOperand(0), Tmp1));
3030 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3031 DAG.getConstant(x, dl, NVT));
3032 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
3033 Results.push_back(Tmp1);
3037 Results.push_back(DAG.expandVAArg(Node));
3038 Results.push_back(Results[0].getValue(1));
3041 Results.push_back(DAG.expandVACopy(Node));
3043 case ISD::EXTRACT_VECTOR_ELT:
3044 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3045 // This must be an access of the only element. Return it.
3046 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3047 Node->getOperand(0));
3049 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3050 Results.push_back(Tmp1);
3052 case ISD::EXTRACT_SUBVECTOR:
3053 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3055 case ISD::INSERT_SUBVECTOR:
3056 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3058 case ISD::CONCAT_VECTORS: {
3059 Results.push_back(ExpandVectorBuildThroughStack(Node));
3062 case ISD::SCALAR_TO_VECTOR:
3063 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3065 case ISD::INSERT_VECTOR_ELT:
3066 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3067 Node->getOperand(1),
3068 Node->getOperand(2), dl));
3070 case ISD::VECTOR_SHUFFLE: {
3071 SmallVector<int, 32> NewMask;
3072 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3074 EVT VT = Node->getValueType(0);
3075 EVT EltVT = VT.getVectorElementType();
3076 SDValue Op0 = Node->getOperand(0);
3077 SDValue Op1 = Node->getOperand(1);
3078 if (!TLI.isTypeLegal(EltVT)) {
3080 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3082 // BUILD_VECTOR operands are allowed to be wider than the element type.
3083 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3085 if (NewEltVT.bitsLT(EltVT)) {
3087 // Convert shuffle node.
3088 // If original node was v4i64 and the new EltVT is i32,
3089 // cast operands to v8i32 and re-build the mask.
3091 // Calculate new VT, the size of the new VT should be equal to original.
3093 EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3094 VT.getSizeInBits() / NewEltVT.getSizeInBits());
3095 assert(NewVT.bitsEq(VT));
3097 // cast operands to new VT
3098 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3099 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3101 // Convert the shuffle mask
3102 unsigned int factor =
3103 NewVT.getVectorNumElements()/VT.getVectorNumElements();
3105 // EltVT gets smaller
3108 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3110 for (unsigned fi = 0; fi < factor; ++fi)
3111 NewMask.push_back(Mask[i]);
3114 for (unsigned fi = 0; fi < factor; ++fi)
3115 NewMask.push_back(Mask[i]*factor+fi);
3123 unsigned NumElems = VT.getVectorNumElements();
3124 SmallVector<SDValue, 16> Ops;
3125 for (unsigned i = 0; i != NumElems; ++i) {
3127 Ops.push_back(DAG.getUNDEF(EltVT));
3130 unsigned Idx = Mask[i];
3132 Ops.push_back(DAG.getNode(
3133 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
3134 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3136 Ops.push_back(DAG.getNode(
3137 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1,
3138 DAG.getConstant(Idx - NumElems, dl,
3139 TLI.getVectorIdxTy(DAG.getDataLayout()))));
3142 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3143 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3144 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3145 Results.push_back(Tmp1);
3148 case ISD::EXTRACT_ELEMENT: {
3149 EVT OpTy = Node->getOperand(0).getValueType();
3150 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3152 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3153 DAG.getConstant(OpTy.getSizeInBits() / 2, dl,
3154 TLI.getShiftAmountTy(
3155 Node->getOperand(0).getValueType(),
3156 DAG.getDataLayout())));
3157 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3160 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3161 Node->getOperand(0));
3163 Results.push_back(Tmp1);
3166 case ISD::STACKSAVE:
3167 // Expand to CopyFromReg if the target set
3168 // StackPointerRegisterToSaveRestore.
3169 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3170 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3171 Node->getValueType(0)));
3172 Results.push_back(Results[0].getValue(1));
3174 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3175 Results.push_back(Node->getOperand(0));
3178 case ISD::STACKRESTORE:
3179 // Expand to CopyToReg if the target set
3180 // StackPointerRegisterToSaveRestore.
3181 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3182 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3183 Node->getOperand(1)));
3185 Results.push_back(Node->getOperand(0));
3188 case ISD::FCOPYSIGN:
3189 Results.push_back(ExpandFCOPYSIGN(Node));
3192 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3193 Tmp1 = DAG.getConstantFP(-0.0, dl, Node->getValueType(0));
3194 // TODO: If FNEG has fast-math-flags, propagate them to the FSUB.
3195 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3196 Node->getOperand(0));
3197 Results.push_back(Tmp1);
3200 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3201 EVT VT = Node->getValueType(0);
3202 Tmp1 = Node->getOperand(0);
3203 Tmp2 = DAG.getConstantFP(0.0, dl, VT);
3204 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
3205 Tmp1, Tmp2, ISD::SETUGT);
3206 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3207 Tmp1 = DAG.getSelect(dl, VT, Tmp2, Tmp1, Tmp3);
3208 Results.push_back(Tmp1);
3215 // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
3217 switch (Node->getOpcode()) {
3218 default: llvm_unreachable("How did we get here?");
3219 case ISD::SMAX: Pred = ISD::SETGT; break;
3220 case ISD::SMIN: Pred = ISD::SETLT; break;
3221 case ISD::UMAX: Pred = ISD::SETUGT; break;
3222 case ISD::UMIN: Pred = ISD::SETULT; break;
3224 Tmp1 = Node->getOperand(0);
3225 Tmp2 = Node->getOperand(1);
3226 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp1, Tmp2, Pred);
3227 Results.push_back(Tmp1);
3233 EVT VT = Node->getValueType(0);
3234 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3235 // fcos which share the same operand and both are used.
3236 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3237 canCombineSinCosLibcall(Node, TLI, TM))
3238 && useSinCos(Node)) {
3239 SDVTList VTs = DAG.getVTList(VT, VT);
3240 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3241 if (Node->getOpcode() == ISD::FCOS)
3242 Tmp1 = Tmp1.getValue(1);
3243 Results.push_back(Tmp1);
3248 llvm_unreachable("Illegal fmad should never be formed");
3250 case ISD::FP16_TO_FP:
3251 if (Node->getValueType(0) != MVT::f32) {
3252 // We can extend to types bigger than f32 in two steps without changing
3253 // the result. Since "f16 -> f32" is much more commonly available, give
3254 // CodeGen the option of emitting that before resorting to a libcall.
3256 DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3258 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
3261 case ISD::FP_TO_FP16:
3262 if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {
3263 SDValue Op = Node->getOperand(0);
3264 MVT SVT = Op.getSimpleValueType();
3265 if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3266 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3267 // Under fastmath, we can expand this node into a fround followed by
3268 // a float-half conversion.
3269 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
3270 DAG.getIntPtrConstant(0, dl));
3272 DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, FloatVal));
3276 case ISD::ConstantFP: {
3277 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3278 // Check to see if this FP immediate is already legal.
3279 // If this is a legal constant, turn it into a TargetConstantFP node.
3280 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3281 Results.push_back(ExpandConstantFP(CFP, true));
3285 EVT VT = Node->getValueType(0);
3286 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3287 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3288 const SDNodeFlags *Flags = &cast<BinaryWithFlagsSDNode>(Node)->Flags;
3289 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3290 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags);
3291 Results.push_back(Tmp1);
3296 EVT VT = Node->getValueType(0);
3297 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3298 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3299 "Don't know how to expand this subtraction!");
3300 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3301 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
3303 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT));
3304 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3309 EVT VT = Node->getValueType(0);
3310 bool isSigned = Node->getOpcode() == ISD::SREM;
3311 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3312 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3313 Tmp2 = Node->getOperand(0);
3314 Tmp3 = Node->getOperand(1);
3315 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3316 SDVTList VTs = DAG.getVTList(VT, VT);
3317 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3318 Results.push_back(Tmp1);
3319 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3321 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3322 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3323 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3324 Results.push_back(Tmp1);
3330 bool isSigned = Node->getOpcode() == ISD::SDIV;
3331 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3332 EVT VT = Node->getValueType(0);
3333 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3334 SDVTList VTs = DAG.getVTList(VT, VT);
3335 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3336 Node->getOperand(1));
3337 Results.push_back(Tmp1);
3343 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3345 EVT VT = Node->getValueType(0);
3346 SDVTList VTs = DAG.getVTList(VT, VT);
3347 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3348 "If this wasn't legal, it shouldn't have been created!");
3349 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3350 Node->getOperand(1));
3351 Results.push_back(Tmp1.getValue(1));
3355 EVT VT = Node->getValueType(0);
3356 SDVTList VTs = DAG.getVTList(VT, VT);
3357 // See if multiply or divide can be lowered using two-result operations.
3358 // We just need the low half of the multiply; try both the signed
3359 // and unsigned forms. If the target supports both SMUL_LOHI and
3360 // UMUL_LOHI, form a preference by checking which forms of plain
3361 // MULH it supports.
3362 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3363 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3364 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3365 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3366 unsigned OpToUse = 0;
3367 if (HasSMUL_LOHI && !HasMULHS) {
3368 OpToUse = ISD::SMUL_LOHI;
3369 } else if (HasUMUL_LOHI && !HasMULHU) {
3370 OpToUse = ISD::UMUL_LOHI;
3371 } else if (HasSMUL_LOHI) {
3372 OpToUse = ISD::SMUL_LOHI;
3373 } else if (HasUMUL_LOHI) {
3374 OpToUse = ISD::UMUL_LOHI;
3377 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3378 Node->getOperand(1)));
3383 EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3384 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3385 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3386 TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3387 TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3388 TLI.expandMUL(Node, Lo, Hi, HalfType, DAG)) {
3389 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3390 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3392 DAG.getConstant(HalfType.getSizeInBits(), dl,
3393 TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3394 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3395 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3401 SDValue LHS = Node->getOperand(0);
3402 SDValue RHS = Node->getOperand(1);
3403 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3404 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3406 Results.push_back(Sum);
3407 EVT ResultType = Node->getValueType(1);
3408 EVT OType = getSetCCResultType(Node->getValueType(0));
3410 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
3412 // LHSSign -> LHS >= 0
3413 // RHSSign -> RHS >= 0
3414 // SumSign -> Sum >= 0
3417 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3419 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3421 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3422 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3423 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3424 Node->getOpcode() == ISD::SADDO ?
3425 ISD::SETEQ : ISD::SETNE);
3427 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3428 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3430 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3431 Results.push_back(DAG.getBoolExtOrTrunc(Cmp, dl, ResultType, ResultType));
3436 SDValue LHS = Node->getOperand(0);
3437 SDValue RHS = Node->getOperand(1);
3438 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3439 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3441 Results.push_back(Sum);
3443 EVT ResultType = Node->getValueType(1);
3444 EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3446 = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT;
3447 SDValue SetCC = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3449 Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType));
3454 EVT VT = Node->getValueType(0);
3455 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3456 SDValue LHS = Node->getOperand(0);
3457 SDValue RHS = Node->getOperand(1);
3460 static const unsigned Ops[2][3] =
3461 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3462 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3463 bool isSigned = Node->getOpcode() == ISD::SMULO;
3464 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3465 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3466 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3467 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3468 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3470 TopHalf = BottomHalf.getValue(1);
3471 } else if (TLI.isTypeLegal(WideVT)) {
3472 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3473 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3474 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3475 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3476 DAG.getIntPtrConstant(0, dl));
3477 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3478 DAG.getIntPtrConstant(1, dl));
3480 // We can fall back to a libcall with an illegal type for the MUL if we
3481 // have a libcall big enough.
3482 // Also, we can fall back to a division in some cases, but that's a big
3483 // performance hit in the general case.
3484 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3485 if (WideVT == MVT::i16)
3486 LC = RTLIB::MUL_I16;
3487 else if (WideVT == MVT::i32)
3488 LC = RTLIB::MUL_I32;
3489 else if (WideVT == MVT::i64)
3490 LC = RTLIB::MUL_I64;
3491 else if (WideVT == MVT::i128)
3492 LC = RTLIB::MUL_I128;
3493 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3495 // The high part is obtained by SRA'ing all but one of the bits of low
3497 unsigned LoSize = VT.getSizeInBits();
3499 DAG.getNode(ISD::SRA, dl, VT, RHS,
3500 DAG.getConstant(LoSize - 1, dl,
3501 TLI.getPointerTy(DAG.getDataLayout())));
3503 DAG.getNode(ISD::SRA, dl, VT, LHS,
3504 DAG.getConstant(LoSize - 1, dl,
3505 TLI.getPointerTy(DAG.getDataLayout())));
3507 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3508 // pre-lowered to the correct types. This all depends upon WideVT not
3509 // being a legal type for the architecture and thus has to be split to
3511 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3512 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3513 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3514 DAG.getIntPtrConstant(0, dl));
3515 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3516 DAG.getIntPtrConstant(1, dl));
3517 // Ret is a node with an illegal type. Because such things are not
3518 // generally permitted during this phase of legalization, make sure the
3519 // node has no more uses. The above EXTRACT_ELEMENT nodes should have been
3521 assert(Ret->use_empty() &&
3522 "Unexpected uses of illegally type from expanded lib call.");
3526 Tmp1 = DAG.getConstant(
3527 VT.getSizeInBits() - 1, dl,
3528 TLI.getShiftAmountTy(BottomHalf.getValueType(), DAG.getDataLayout()));
3529 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3530 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3533 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3534 DAG.getConstant(0, dl, VT), ISD::SETNE);
3536 Results.push_back(BottomHalf);
3537 Results.push_back(TopHalf);
3540 case ISD::BUILD_PAIR: {
3541 EVT PairTy = Node->getValueType(0);
3542 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3543 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3545 ISD::SHL, dl, PairTy, Tmp2,
3546 DAG.getConstant(PairTy.getSizeInBits() / 2, dl,
3547 TLI.getShiftAmountTy(PairTy, DAG.getDataLayout())));
3548 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3552 Tmp1 = Node->getOperand(0);
3553 Tmp2 = Node->getOperand(1);
3554 Tmp3 = Node->getOperand(2);
3555 if (Tmp1.getOpcode() == ISD::SETCC) {
3556 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3558 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3560 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3561 DAG.getConstant(0, dl, Tmp1.getValueType()),
3562 Tmp2, Tmp3, ISD::SETNE);
3564 Results.push_back(Tmp1);
3567 SDValue Chain = Node->getOperand(0);
3568 SDValue Table = Node->getOperand(1);
3569 SDValue Index = Node->getOperand(2);
3571 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
3573 const DataLayout &TD = DAG.getDataLayout();
3574 unsigned EntrySize =
3575 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3577 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
3578 DAG.getConstant(EntrySize, dl, Index.getValueType()));
3579 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3582 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3583 SDValue LD = DAG.getExtLoad(
3584 ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3585 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), MemVT,
3586 false, false, false, 0);
3588 if (TM.getRelocationModel() == Reloc::PIC_) {
3589 // For PIC, the sequence is:
3590 // BRIND(load(Jumptable + index) + RelocBase)
3591 // RelocBase can be JumpTable, GOT or some sort of global base.
3592 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3593 TLI.getPICJumpTableRelocBase(Table, DAG));
3595 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3596 Results.push_back(Tmp1);
3600 // Expand brcond's setcc into its constituent parts and create a BR_CC
3602 Tmp1 = Node->getOperand(0);
3603 Tmp2 = Node->getOperand(1);
3604 if (Tmp2.getOpcode() == ISD::SETCC) {
3605 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3606 Tmp1, Tmp2.getOperand(2),
3607 Tmp2.getOperand(0), Tmp2.getOperand(1),
3608 Node->getOperand(2));
3610 // We test only the i1 bit. Skip the AND if UNDEF.
3611 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3612 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3613 DAG.getConstant(1, dl, Tmp2.getValueType()));
3614 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3615 DAG.getCondCode(ISD::SETNE), Tmp3,
3616 DAG.getConstant(0, dl, Tmp3.getValueType()),
3617 Node->getOperand(2));
3619 Results.push_back(Tmp1);
3622 Tmp1 = Node->getOperand(0);
3623 Tmp2 = Node->getOperand(1);
3624 Tmp3 = Node->getOperand(2);
3625 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3626 Tmp3, NeedInvert, dl);
3629 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3630 // condition code, create a new SETCC node.
3632 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3635 // If we expanded the SETCC by inverting the condition code, then wrap
3636 // the existing SETCC in a NOT to restore the intended condition.
3638 Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3640 Results.push_back(Tmp1);
3644 // Otherwise, SETCC for the given comparison type must be completely
3645 // illegal; expand it into a SELECT_CC.
3646 EVT VT = Node->getValueType(0);
3648 switch (TLI.getBooleanContents(Tmp1->getValueType(0))) {
3649 case TargetLowering::ZeroOrOneBooleanContent:
3650 case TargetLowering::UndefinedBooleanContent:
3653 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3657 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3658 DAG.getConstant(TrueValue, dl, VT),
3659 DAG.getConstant(0, dl, VT),
3661 Results.push_back(Tmp1);
3664 case ISD::SELECT_CC: {
3665 Tmp1 = Node->getOperand(0); // LHS
3666 Tmp2 = Node->getOperand(1); // RHS
3667 Tmp3 = Node->getOperand(2); // True
3668 Tmp4 = Node->getOperand(3); // False
3669 EVT VT = Node->getValueType(0);
3670 SDValue CC = Node->getOperand(4);
3671 ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3673 if (TLI.isCondCodeLegal(CCOp, Tmp1.getSimpleValueType())) {
3674 // If the condition code is legal, then we need to expand this
3675 // node using SETCC and SELECT.
3676 EVT CmpVT = Tmp1.getValueType();
3677 assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3678 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3681 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), CmpVT);
3682 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
3683 Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
3687 // SELECT_CC is legal, so the condition code must not be.
3688 bool Legalized = false;
3689 // Try to legalize by inverting the condition. This is for targets that
3690 // might support an ordered version of a condition, but not the unordered
3691 // version (or vice versa).
3692 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
3693 Tmp1.getValueType().isInteger());
3694 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
3695 // Use the new condition code and swap true and false
3697 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3699 // If The inverse is not legal, then try to swap the arguments using
3700 // the inverse condition code.
3701 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3702 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
3703 // The swapped inverse condition is legal, so swap true and false,
3706 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3711 Legalized = LegalizeSetCCCondCode(
3712 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3715 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3717 // If we expanded the SETCC by inverting the condition code, then swap
3718 // the True/False operands to match.
3720 std::swap(Tmp3, Tmp4);
3722 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3723 // condition code, create a new SELECT_CC node.
3725 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3726 Tmp1, Tmp2, Tmp3, Tmp4, CC);
3728 Tmp2 = DAG.getConstant(0, dl, Tmp1.getValueType());
3729 CC = DAG.getCondCode(ISD::SETNE);
3730 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3731 Tmp2, Tmp3, Tmp4, CC);
3734 Results.push_back(Tmp1);
3738 Tmp1 = Node->getOperand(0); // Chain
3739 Tmp2 = Node->getOperand(2); // LHS
3740 Tmp3 = Node->getOperand(3); // RHS
3741 Tmp4 = Node->getOperand(1); // CC
3743 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3744 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
3746 assert(Legalized && "Can't legalize BR_CC with legal condition!");
3748 // If we expanded the SETCC by inverting the condition code, then wrap
3749 // the existing SETCC in a NOT to restore the intended condition.
3751 Tmp4 = DAG.getNOT(dl, Tmp4, Tmp4->getValueType(0));
3753 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3755 if (Tmp4.getNode()) {
3756 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3757 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3759 Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
3760 Tmp4 = DAG.getCondCode(ISD::SETNE);
3761 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
3762 Tmp2, Tmp3, Node->getOperand(4));
3764 Results.push_back(Tmp1);
3767 case ISD::BUILD_VECTOR:
3768 Results.push_back(ExpandBUILD_VECTOR(Node));
3773 // Scalarize vector SRA/SRL/SHL.
3774 EVT VT = Node->getValueType(0);
3775 assert(VT.isVector() && "Unable to legalize non-vector shift");
3776 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3777 unsigned NumElem = VT.getVectorNumElements();
3779 SmallVector<SDValue, 8> Scalars;
3780 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3781 SDValue Ex = DAG.getNode(
3782 ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(0),
3783 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3784 SDValue Sh = DAG.getNode(
3785 ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(1),
3786 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3787 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3788 VT.getScalarType(), Ex, Sh));
3791 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Scalars);
3792 ReplaceNode(SDValue(Node, 0), Result);
3795 case ISD::GLOBAL_OFFSET_TABLE:
3796 case ISD::GlobalAddress:
3797 case ISD::GlobalTLSAddress:
3798 case ISD::ExternalSymbol:
3799 case ISD::ConstantPool:
3800 case ISD::JumpTable:
3801 case ISD::INTRINSIC_W_CHAIN:
3802 case ISD::INTRINSIC_WO_CHAIN:
3803 case ISD::INTRINSIC_VOID:
3804 // FIXME: Custom lowering for these operations shouldn't return null!
3808 // Replace the original node with the legalized result.
3809 if (Results.empty())
3812 ReplaceNode(Node, Results.data());
3816 void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
3817 SmallVector<SDValue, 8> Results;
3819 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
3820 unsigned Opc = Node->getOpcode();
3822 case ISD::ATOMIC_FENCE: {
3823 // If the target didn't lower this, lower it to '__sync_synchronize()' call
3824 // FIXME: handle "fence singlethread" more efficiently.
3825 TargetLowering::ArgListTy Args;
3827 TargetLowering::CallLoweringInfo CLI(DAG);
3829 .setChain(Node->getOperand(0))
3830 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3831 DAG.getExternalSymbol("__sync_synchronize",
3832 TLI.getPointerTy(DAG.getDataLayout())),
3833 std::move(Args), 0);
3835 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3837 Results.push_back(CallResult.second);
3840 // By default, atomic intrinsics are marked Legal and lowered. Targets
3841 // which don't support them directly, however, may want libcalls, in which
3842 // case they mark them Expand, and we get here.
3843 case ISD::ATOMIC_SWAP:
3844 case ISD::ATOMIC_LOAD_ADD:
3845 case ISD::ATOMIC_LOAD_SUB:
3846 case ISD::ATOMIC_LOAD_AND:
3847 case ISD::ATOMIC_LOAD_OR:
3848 case ISD::ATOMIC_LOAD_XOR:
3849 case ISD::ATOMIC_LOAD_NAND:
3850 case ISD::ATOMIC_LOAD_MIN:
3851 case ISD::ATOMIC_LOAD_MAX:
3852 case ISD::ATOMIC_LOAD_UMIN:
3853 case ISD::ATOMIC_LOAD_UMAX:
3854 case ISD::ATOMIC_CMP_SWAP: {
3855 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
3856 RTLIB::Libcall LC = RTLIB::getATOMIC(Opc, VT);
3857 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
3859 std::pair<SDValue, SDValue> Tmp = ExpandChainLibCall(LC, Node, false);
3860 Results.push_back(Tmp.first);
3861 Results.push_back(Tmp.second);
3865 // If this operation is not supported, lower it to 'abort()' call
3866 TargetLowering::ArgListTy Args;
3867 TargetLowering::CallLoweringInfo CLI(DAG);
3869 .setChain(Node->getOperand(0))
3870 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3871 DAG.getExternalSymbol("abort",
3872 TLI.getPointerTy(DAG.getDataLayout())),
3873 std::move(Args), 0);
3874 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3876 Results.push_back(CallResult.second);
3880 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
3881 RTLIB::FMIN_F80, RTLIB::FMIN_F128,
3882 RTLIB::FMIN_PPCF128));
3885 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
3886 RTLIB::FMAX_F80, RTLIB::FMAX_F128,
3887 RTLIB::FMAX_PPCF128));
3890 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3891 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3892 RTLIB::SQRT_PPCF128));
3895 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3896 RTLIB::SIN_F80, RTLIB::SIN_F128,
3897 RTLIB::SIN_PPCF128));
3900 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3901 RTLIB::COS_F80, RTLIB::COS_F128,
3902 RTLIB::COS_PPCF128));
3905 // Expand into sincos libcall.
3906 ExpandSinCosLibCall(Node, Results);
3909 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3910 RTLIB::LOG_F80, RTLIB::LOG_F128,
3911 RTLIB::LOG_PPCF128));
3914 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3915 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3916 RTLIB::LOG2_PPCF128));
3919 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3920 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3921 RTLIB::LOG10_PPCF128));
3924 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3925 RTLIB::EXP_F80, RTLIB::EXP_F128,
3926 RTLIB::EXP_PPCF128));
3929 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3930 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3931 RTLIB::EXP2_PPCF128));
3934 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3935 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3936 RTLIB::TRUNC_PPCF128));
3939 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3940 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3941 RTLIB::FLOOR_PPCF128));
3944 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3945 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3946 RTLIB::CEIL_PPCF128));
3949 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3950 RTLIB::RINT_F80, RTLIB::RINT_F128,
3951 RTLIB::RINT_PPCF128));
3953 case ISD::FNEARBYINT:
3954 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3955 RTLIB::NEARBYINT_F64,
3956 RTLIB::NEARBYINT_F80,
3957 RTLIB::NEARBYINT_F128,
3958 RTLIB::NEARBYINT_PPCF128));
3961 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3965 RTLIB::ROUND_PPCF128));
3968 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3969 RTLIB::POWI_F80, RTLIB::POWI_F128,
3970 RTLIB::POWI_PPCF128));
3973 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3974 RTLIB::POW_F80, RTLIB::POW_F128,
3975 RTLIB::POW_PPCF128));
3978 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3979 RTLIB::DIV_F80, RTLIB::DIV_F128,
3980 RTLIB::DIV_PPCF128));
3983 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3984 RTLIB::REM_F80, RTLIB::REM_F128,
3985 RTLIB::REM_PPCF128));
3988 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3989 RTLIB::FMA_F80, RTLIB::FMA_F128,
3990 RTLIB::FMA_PPCF128));
3993 Results.push_back(ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
3994 RTLIB::ADD_F80, RTLIB::ADD_F128,
3995 RTLIB::ADD_PPCF128));
3998 Results.push_back(ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
3999 RTLIB::MUL_F80, RTLIB::MUL_F128,
4000 RTLIB::MUL_PPCF128));
4002 case ISD::FP16_TO_FP:
4003 if (Node->getValueType(0) == MVT::f32) {
4004 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
4007 case ISD::FP_TO_FP16: {
4009 RTLIB::getFPROUND(Node->getOperand(0).getValueType(), MVT::f16);
4010 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
4011 Results.push_back(ExpandLibCall(LC, Node, false));
4015 Results.push_back(ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
4016 RTLIB::SUB_F80, RTLIB::SUB_F128,
4017 RTLIB::SUB_PPCF128));
4020 Results.push_back(ExpandIntLibCall(Node, true,
4022 RTLIB::SREM_I16, RTLIB::SREM_I32,
4023 RTLIB::SREM_I64, RTLIB::SREM_I128));
4026 Results.push_back(ExpandIntLibCall(Node, false,
4028 RTLIB::UREM_I16, RTLIB::UREM_I32,
4029 RTLIB::UREM_I64, RTLIB::UREM_I128));
4032 Results.push_back(ExpandIntLibCall(Node, true,
4034 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
4035 RTLIB::SDIV_I64, RTLIB::SDIV_I128));
4038 Results.push_back(ExpandIntLibCall(Node, false,
4040 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
4041 RTLIB::UDIV_I64, RTLIB::UDIV_I128));
4045 // Expand into divrem libcall
4046 ExpandDivRemLibCall(Node, Results);
4049 Results.push_back(ExpandIntLibCall(Node, false,
4051 RTLIB::MUL_I16, RTLIB::MUL_I32,
4052 RTLIB::MUL_I64, RTLIB::MUL_I128));
4056 // Replace the original node with the legalized result.
4057 if (!Results.empty())
4058 ReplaceNode(Node, Results.data());
4061 // Determine the vector type to use in place of an original scalar element when
4062 // promoting equally sized vectors.
4063 static MVT getPromotedVectorElementType(const TargetLowering &TLI,
4064 MVT EltVT, MVT NewEltVT) {
4065 unsigned OldEltsPerNewElt = EltVT.getSizeInBits() / NewEltVT.getSizeInBits();
4066 MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt);
4067 assert(TLI.isTypeLegal(MidVT) && "unexpected");
4071 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4072 SmallVector<SDValue, 8> Results;
4073 MVT OVT = Node->getSimpleValueType(0);
4074 if (Node->getOpcode() == ISD::UINT_TO_FP ||
4075 Node->getOpcode() == ISD::SINT_TO_FP ||
4076 Node->getOpcode() == ISD::SETCC ||
4077 Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
4078 Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
4079 OVT = Node->getOperand(0).getSimpleValueType();
4081 if (Node->getOpcode() == ISD::BR_CC)
4082 OVT = Node->getOperand(2).getSimpleValueType();
4083 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4085 SDValue Tmp1, Tmp2, Tmp3;
4086 switch (Node->getOpcode()) {
4088 case ISD::CTTZ_ZERO_UNDEF:
4090 case ISD::CTLZ_ZERO_UNDEF:
4092 // Zero extend the argument.
4093 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4094 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4095 // already the correct result.
4096 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4097 if (Node->getOpcode() == ISD::CTTZ) {
4098 // FIXME: This should set a bit in the zero extended value instead.
4099 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
4100 Tmp1, DAG.getConstant(NVT.getSizeInBits(), dl, NVT),
4102 Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
4103 DAG.getConstant(OVT.getSizeInBits(), dl, NVT), Tmp1);
4104 } else if (Node->getOpcode() == ISD::CTLZ ||
4105 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4106 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4107 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4108 DAG.getConstant(NVT.getSizeInBits() -
4109 OVT.getSizeInBits(), dl, NVT));
4111 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4114 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4115 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4116 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4118 ISD::SRL, dl, NVT, Tmp1,
4119 DAG.getConstant(DiffBits, dl,
4120 TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
4121 Results.push_back(Tmp1);
4124 case ISD::FP_TO_UINT:
4125 case ISD::FP_TO_SINT:
4126 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4127 Node->getOpcode() == ISD::FP_TO_SINT, dl);
4128 Results.push_back(Tmp1);
4130 case ISD::UINT_TO_FP:
4131 case ISD::SINT_TO_FP:
4132 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4133 Node->getOpcode() == ISD::SINT_TO_FP, dl);
4134 Results.push_back(Tmp1);
4137 SDValue Chain = Node->getOperand(0); // Get the chain.
4138 SDValue Ptr = Node->getOperand(1); // Get the pointer.
4141 if (OVT.isVector()) {
4142 TruncOp = ISD::BITCAST;
4144 assert(OVT.isInteger()
4145 && "VAARG promotion is supported only for vectors or integer types");
4146 TruncOp = ISD::TRUNCATE;
4149 // Perform the larger operation, then convert back
4150 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4151 Node->getConstantOperandVal(3));
4152 Chain = Tmp1.getValue(1);
4154 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4156 // Modified the chain result - switch anything that used the old chain to
4158 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4159 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4161 UpdatedNodes->insert(Tmp2.getNode());
4162 UpdatedNodes->insert(Chain.getNode());
4170 unsigned ExtOp, TruncOp;
4171 if (OVT.isVector()) {
4172 ExtOp = ISD::BITCAST;
4173 TruncOp = ISD::BITCAST;
4175 assert(OVT.isInteger() && "Cannot promote logic operation");
4176 ExtOp = ISD::ANY_EXTEND;
4177 TruncOp = ISD::TRUNCATE;
4179 // Promote each of the values to the new type.
4180 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4181 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4182 // Perform the larger operation, then convert back
4183 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4184 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4188 unsigned ExtOp, TruncOp;
4189 if (Node->getValueType(0).isVector() ||
4190 Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4191 ExtOp = ISD::BITCAST;
4192 TruncOp = ISD::BITCAST;
4193 } else if (Node->getValueType(0).isInteger()) {
4194 ExtOp = ISD::ANY_EXTEND;
4195 TruncOp = ISD::TRUNCATE;
4197 ExtOp = ISD::FP_EXTEND;
4198 TruncOp = ISD::FP_ROUND;
4200 Tmp1 = Node->getOperand(0);
4201 // Promote each of the values to the new type.
4202 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4203 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4204 // Perform the larger operation, then round down.
4205 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4206 if (TruncOp != ISD::FP_ROUND)
4207 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4209 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4210 DAG.getIntPtrConstant(0, dl));
4211 Results.push_back(Tmp1);
4214 case ISD::VECTOR_SHUFFLE: {
4215 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4217 // Cast the two input vectors.
4218 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4219 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4221 // Convert the shuffle mask to the right # elements.
4222 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4223 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4224 Results.push_back(Tmp1);
4228 unsigned ExtOp = ISD::FP_EXTEND;
4229 if (NVT.isInteger()) {
4230 ISD::CondCode CCCode =
4231 cast<CondCodeSDNode>(Node->getOperand(2))->get();
4232 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4234 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4235 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4236 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4237 Tmp1, Tmp2, Node->getOperand(2)));
4241 unsigned ExtOp = ISD::FP_EXTEND;
4242 if (NVT.isInteger()) {
4243 ISD::CondCode CCCode =
4244 cast<CondCodeSDNode>(Node->getOperand(1))->get();
4245 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4247 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4248 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
4249 Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0),
4250 Node->getOperand(0), Node->getOperand(1),
4251 Tmp1, Tmp2, Node->getOperand(4)));
4262 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4263 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4264 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2,
4266 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4267 Tmp3, DAG.getIntPtrConstant(0, dl)));
4271 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4272 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4273 Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
4275 DAG.getNode(ISD::FP_ROUND, dl, OVT,
4276 DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
4277 DAG.getIntPtrConstant(0, dl)));
4280 case ISD::FCOPYSIGN:
4282 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4283 Tmp2 = Node->getOperand(1);
4284 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4286 // fcopysign doesn't change anything but the sign bit, so
4287 // (fp_round (fcopysign (fpext a), b))
4289 // (fp_round (fpext a))
4290 // which is a no-op. Mark it as a TRUNCating FP_ROUND.
4291 const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN);
4292 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4293 Tmp3, DAG.getIntPtrConstant(isTrunc, dl)));
4299 case ISD::FNEARBYINT:
4312 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4313 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4314 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4315 Tmp2, DAG.getIntPtrConstant(0, dl)));
4318 case ISD::BUILD_VECTOR: {
4319 MVT EltVT = OVT.getVectorElementType();
4320 MVT NewEltVT = NVT.getVectorElementType();
4322 // Handle bitcasts to a different vector type with the same total bit size
4324 // e.g. v2i64 = build_vector i64:x, i64:y => v4i32
4326 // v4i32 = concat_vectors (v2i32 (bitcast i64:x)), (v2i32 (bitcast i64:y))
4328 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4329 "Invalid promote type for build_vector");
4330 assert(NewEltVT.bitsLT(EltVT) && "not handled");
4332 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4334 SmallVector<SDValue, 8> NewOps;
4335 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) {
4336 SDValue Op = Node->getOperand(I);
4337 NewOps.push_back(DAG.getNode(ISD::BITCAST, SDLoc(Op), MidVT, Op));
4341 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps);
4342 SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4343 Results.push_back(CvtVec);
4346 case ISD::EXTRACT_VECTOR_ELT: {
4347 MVT EltVT = OVT.getVectorElementType();
4348 MVT NewEltVT = NVT.getVectorElementType();
4350 // Handle bitcasts to a different vector type with the same total bit size.
4352 // e.g. v2i64 = extract_vector_elt x:v2i64, y:i32
4354 // v4i32:castx = bitcast x:v2i64
4357 // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))),
4358 // (i32 (extract_vector_elt castx, (2 * y + 1)))
4361 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4362 "Invalid promote type for extract_vector_elt");
4363 assert(NewEltVT.bitsLT(EltVT) && "not handled");
4365 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4366 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4368 SDValue Idx = Node->getOperand(1);
4369 EVT IdxVT = Idx.getValueType();
4371 SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SL, IdxVT);
4372 SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4374 SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4376 SmallVector<SDValue, 8> NewOps;
4377 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4378 SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4379 SDValue TmpIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4381 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4383 NewOps.push_back(Elt);
4386 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, SL, MidVT, NewOps);
4388 Results.push_back(DAG.getNode(ISD::BITCAST, SL, EltVT, NewVec));
4391 case ISD::INSERT_VECTOR_ELT: {
4392 MVT EltVT = OVT.getVectorElementType();
4393 MVT NewEltVT = NVT.getVectorElementType();
4395 // Handle bitcasts to a different vector type with the same total bit size
4397 // e.g. v2i64 = insert_vector_elt x:v2i64, y:i64, z:i32
4399 // v4i32:castx = bitcast x:v2i64
4400 // v2i32:casty = bitcast y:i64
4403 // (v4i32 insert_vector_elt
4404 // (v4i32 insert_vector_elt v4i32:castx,
4405 // (extract_vector_elt casty, 0), 2 * z),
4406 // (extract_vector_elt casty, 1), (2 * z + 1))
4408 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4409 "Invalid promote type for insert_vector_elt");
4410 assert(NewEltVT.bitsLT(EltVT) && "not handled");
4412 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4413 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4415 SDValue Val = Node->getOperand(1);
4416 SDValue Idx = Node->getOperand(2);
4417 EVT IdxVT = Idx.getValueType();
4420 SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SDLoc(), IdxVT);
4421 SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4423 SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4424 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4426 SDValue NewVec = CastVec;
4427 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4428 SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4429 SDValue InEltIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4431 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4432 CastVal, IdxOffset);
4434 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT,
4435 NewVec, Elt, InEltIdx);
4438 Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewVec));
4441 case ISD::SCALAR_TO_VECTOR: {
4442 MVT EltVT = OVT.getVectorElementType();
4443 MVT NewEltVT = NVT.getVectorElementType();
4445 // Handle bitcasts to different vector type with the smae total bit size.
4447 // e.g. v2i64 = scalar_to_vector x:i64
4449 // concat_vectors (v2i32 bitcast x:i64), (v2i32 undef)
4452 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4453 SDValue Val = Node->getOperand(0);
4456 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4457 SDValue Undef = DAG.getUNDEF(MidVT);
4459 SmallVector<SDValue, 8> NewElts;
4460 NewElts.push_back(CastVal);
4461 for (unsigned I = 1, NElts = OVT.getVectorNumElements(); I != NElts; ++I)
4462 NewElts.push_back(Undef);
4464 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts);
4465 SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4466 Results.push_back(CvtVec);
4471 // Replace the original node with the legalized result.
4472 if (!Results.empty())
4473 ReplaceNode(Node, Results.data());
4476 /// This is the entry point for the file.
4477 void SelectionDAG::Legalize() {
4478 AssignTopologicalOrder();
4480 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4481 SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
4483 // Visit all the nodes. We start in topological order, so that we see
4484 // nodes with their original operands intact. Legalization can produce
4485 // new nodes which may themselves need to be legalized. Iterate until all
4486 // nodes have been legalized.
4488 bool AnyLegalized = false;
4489 for (auto NI = allnodes_end(); NI != allnodes_begin();) {
4493 if (N->use_empty() && N != getRoot().getNode()) {
4499 if (LegalizedNodes.insert(N).second) {
4500 AnyLegalized = true;
4501 Legalizer.LegalizeOp(N);
4503 if (N->use_empty() && N != getRoot().getNode()) {
4514 // Remove dead nodes now.
4518 bool SelectionDAG::LegalizeOp(SDNode *N,
4519 SmallSetVector<SDNode *, 16> &UpdatedNodes) {
4520 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4521 SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
4523 // Directly insert the node in question, and legalize it. This will recurse
4524 // as needed through operands.
4525 LegalizedNodes.insert(N);
4526 Legalizer.LegalizeOp(N);
4528 return LegalizedNodes.count(N);