1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/SmallPtrSet.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/CodeGen/Analysis.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/DebugInfo.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/IR/DerivedTypes.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/LLVMContext.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetFrameLowering.h"
33 #include "llvm/Target/TargetLowering.h"
34 #include "llvm/Target/TargetMachine.h"
37 //===----------------------------------------------------------------------===//
38 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
39 /// hacks on it until the target machine can handle it. This involves
40 /// eliminating value sizes the machine cannot handle (promoting small sizes to
41 /// large sizes or splitting up large values into small values) as well as
42 /// eliminating operations the machine cannot handle.
44 /// This code also does a small amount of optimization and recognition of idioms
45 /// as part of its processing. For example, if a target does not support a
46 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
47 /// will attempt merge setcc and brc instructions into brcc's.
50 class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
51 const TargetMachine &TM;
52 const TargetLowering &TLI;
55 /// LegalizePosition - The iterator for walking through the node list.
56 SelectionDAG::allnodes_iterator LegalizePosition;
58 /// LegalizedNodes - The set of nodes which have already been legalized.
59 SmallPtrSet<SDNode *, 16> LegalizedNodes;
61 // Libcall insertion helpers.
64 explicit SelectionDAGLegalize(SelectionDAG &DAG);
69 /// LegalizeOp - Legalizes the given operation.
70 void LegalizeOp(SDNode *Node);
72 SDValue OptimizeFloatStore(StoreSDNode *ST);
74 void LegalizeLoadOps(SDNode *Node);
75 void LegalizeStoreOps(SDNode *Node);
77 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
78 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
79 /// is necessary to spill the vector being inserted into to memory, perform
80 /// the insert there, and then read the result back.
81 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
82 SDValue Idx, DebugLoc dl);
83 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
84 SDValue Idx, DebugLoc dl);
86 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
87 /// performs the same shuffe in terms of order or result bytes, but on a type
88 /// whose vector element type is narrower than the original shuffle type.
89 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
90 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
91 SDValue N1, SDValue N2,
92 ArrayRef<int> Mask) const;
94 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
97 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
98 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
99 unsigned NumOps, bool isSigned, DebugLoc dl);
101 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
102 SDNode *Node, bool isSigned);
103 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
104 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
105 RTLIB::Libcall Call_F128, RTLIB::Libcall Call_PPCF128);
106 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
107 RTLIB::Libcall Call_I8,
108 RTLIB::Libcall Call_I16,
109 RTLIB::Libcall Call_I32,
110 RTLIB::Libcall Call_I64,
111 RTLIB::Libcall Call_I128);
112 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
114 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
115 SDValue ExpandBUILD_VECTOR(SDNode *Node);
116 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
117 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
118 SmallVectorImpl<SDValue> &Results);
119 SDValue ExpandFCOPYSIGN(SDNode *Node);
120 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
122 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
124 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
127 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
128 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
130 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
131 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
132 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
134 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
136 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
138 void ExpandNode(SDNode *Node);
139 void PromoteNode(SDNode *Node);
141 void ForgetNode(SDNode *N) {
142 LegalizedNodes.erase(N);
143 if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
148 // DAGUpdateListener implementation.
149 virtual void NodeDeleted(SDNode *N, SDNode *E) {
152 virtual void NodeUpdated(SDNode *N) {}
154 // Node replacement helpers
155 void ReplacedNode(SDNode *N) {
156 if (N->use_empty()) {
157 DAG.RemoveDeadNode(N);
162 void ReplaceNode(SDNode *Old, SDNode *New) {
163 DAG.ReplaceAllUsesWith(Old, New);
166 void ReplaceNode(SDValue Old, SDValue New) {
167 DAG.ReplaceAllUsesWith(Old, New);
168 ReplacedNode(Old.getNode());
170 void ReplaceNode(SDNode *Old, const SDValue *New) {
171 DAG.ReplaceAllUsesWith(Old, New);
177 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
178 /// performs the same shuffe in terms of order or result bytes, but on a type
179 /// whose vector element type is narrower than the original shuffle type.
180 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
182 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
183 SDValue N1, SDValue N2,
184 ArrayRef<int> Mask) const {
185 unsigned NumMaskElts = VT.getVectorNumElements();
186 unsigned NumDestElts = NVT.getVectorNumElements();
187 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
189 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
191 if (NumEltsGrowth == 1)
192 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
194 SmallVector<int, 8> NewMask;
195 for (unsigned i = 0; i != NumMaskElts; ++i) {
197 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
199 NewMask.push_back(-1);
201 NewMask.push_back(Idx * NumEltsGrowth + j);
204 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
205 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
206 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
209 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
210 : SelectionDAG::DAGUpdateListener(dag),
211 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
215 void SelectionDAGLegalize::LegalizeDAG() {
216 DAG.AssignTopologicalOrder();
218 // Visit all the nodes. We start in topological order, so that we see
219 // nodes with their original operands intact. Legalization can produce
220 // new nodes which may themselves need to be legalized. Iterate until all
221 // nodes have been legalized.
223 bool AnyLegalized = false;
224 for (LegalizePosition = DAG.allnodes_end();
225 LegalizePosition != DAG.allnodes_begin(); ) {
228 SDNode *N = LegalizePosition;
229 if (LegalizedNodes.insert(N)) {
239 // Remove dead nodes now.
240 DAG.RemoveDeadNodes();
243 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
244 /// a load from the constant pool.
246 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
248 DebugLoc dl = CFP->getDebugLoc();
250 // If a FP immediate is precise when represented as a float and if the
251 // target can do an extending load from float to double, we put it into
252 // the constant pool as a float, even if it's is statically typed as a
253 // double. This shrinks FP constants and canonicalizes them for targets where
254 // an FP extending load is the same cost as a normal load (such as on the x87
255 // fp stack or PPC FP unit).
256 EVT VT = CFP->getValueType(0);
257 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
259 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
260 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
261 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
266 while (SVT != MVT::f32) {
267 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
268 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
269 // Only do this if the target has a native EXTLOAD instruction from
271 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
272 TLI.ShouldShrinkFPConstant(OrigVT)) {
273 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
274 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
280 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
281 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
284 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
286 CPIdx, MachinePointerInfo::getConstantPool(),
287 VT, false, false, Alignment);
291 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
292 MachinePointerInfo::getConstantPool(), false, false, false,
297 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
298 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
299 const TargetLowering &TLI,
300 SelectionDAGLegalize *DAGLegalize) {
301 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
302 "unaligned indexed stores not implemented!");
303 SDValue Chain = ST->getChain();
304 SDValue Ptr = ST->getBasePtr();
305 SDValue Val = ST->getValue();
306 EVT VT = Val.getValueType();
307 int Alignment = ST->getAlignment();
308 DebugLoc dl = ST->getDebugLoc();
309 if (ST->getMemoryVT().isFloatingPoint() ||
310 ST->getMemoryVT().isVector()) {
311 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
312 if (TLI.isTypeLegal(intVT)) {
313 // Expand to a bitconvert of the value to the integer type of the
314 // same size, then a (misaligned) int store.
315 // FIXME: Does not handle truncating floating point stores!
316 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
317 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
318 ST->isVolatile(), ST->isNonTemporal(), Alignment);
319 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
322 // Do a (aligned) store to a stack slot, then copy from the stack slot
323 // to the final destination using (unaligned) integer loads and stores.
324 EVT StoredVT = ST->getMemoryVT();
326 TLI.getRegisterType(*DAG.getContext(),
327 EVT::getIntegerVT(*DAG.getContext(),
328 StoredVT.getSizeInBits()));
329 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
330 unsigned RegBytes = RegVT.getSizeInBits() / 8;
331 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
333 // Make sure the stack slot is also aligned for the register type.
334 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
336 // Perform the original store, only redirected to the stack slot.
337 SDValue Store = DAG.getTruncStore(Chain, dl,
338 Val, StackPtr, MachinePointerInfo(),
339 StoredVT, false, false, 0);
340 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
341 SmallVector<SDValue, 8> Stores;
344 // Do all but one copies using the full register width.
345 for (unsigned i = 1; i < NumRegs; i++) {
346 // Load one integer register's worth from the stack slot.
347 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
348 MachinePointerInfo(),
349 false, false, false, 0);
350 // Store it to the final location. Remember the store.
351 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
352 ST->getPointerInfo().getWithOffset(Offset),
353 ST->isVolatile(), ST->isNonTemporal(),
354 MinAlign(ST->getAlignment(), Offset)));
355 // Increment the pointers.
357 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
359 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
362 // The last store may be partial. Do a truncating store. On big-endian
363 // machines this requires an extending load from the stack slot to ensure
364 // that the bits are in the right place.
365 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
366 8 * (StoredBytes - Offset));
368 // Load from the stack slot.
369 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
370 MachinePointerInfo(),
371 MemVT, false, false, 0);
373 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
375 .getWithOffset(Offset),
376 MemVT, ST->isVolatile(),
378 MinAlign(ST->getAlignment(), Offset)));
379 // The order of the stores doesn't matter - say it with a TokenFactor.
381 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
383 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
386 assert(ST->getMemoryVT().isInteger() &&
387 !ST->getMemoryVT().isVector() &&
388 "Unaligned store of unknown type.");
389 // Get the half-size VT
390 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
391 int NumBits = NewStoredVT.getSizeInBits();
392 int IncrementSize = NumBits / 8;
394 // Divide the stored value in two parts.
395 SDValue ShiftAmount = DAG.getConstant(NumBits,
396 TLI.getShiftAmountTy(Val.getValueType()));
398 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
400 // Store the two parts
401 SDValue Store1, Store2;
402 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
403 ST->getPointerInfo(), NewStoredVT,
404 ST->isVolatile(), ST->isNonTemporal(), Alignment);
405 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
406 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
407 Alignment = MinAlign(Alignment, IncrementSize);
408 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
409 ST->getPointerInfo().getWithOffset(IncrementSize),
410 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
414 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
415 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
418 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
420 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
421 const TargetLowering &TLI,
422 SDValue &ValResult, SDValue &ChainResult) {
423 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
424 "unaligned indexed loads not implemented!");
425 SDValue Chain = LD->getChain();
426 SDValue Ptr = LD->getBasePtr();
427 EVT VT = LD->getValueType(0);
428 EVT LoadedVT = LD->getMemoryVT();
429 DebugLoc dl = LD->getDebugLoc();
430 if (VT.isFloatingPoint() || VT.isVector()) {
431 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
432 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
433 // Expand to a (misaligned) integer load of the same size,
434 // then bitconvert to floating point or vector.
435 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
438 LD->isInvariant(), LD->getAlignment());
439 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
441 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
442 ISD::ANY_EXTEND, dl, VT, Result);
449 // Copy the value to a (aligned) stack slot using (unaligned) integer
450 // loads and stores, then do a (aligned) load from the stack slot.
451 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
452 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
453 unsigned RegBytes = RegVT.getSizeInBits() / 8;
454 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
456 // Make sure the stack slot is also aligned for the register type.
457 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
459 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
460 SmallVector<SDValue, 8> Stores;
461 SDValue StackPtr = StackBase;
464 // Do all but one copies using the full register width.
465 for (unsigned i = 1; i < NumRegs; i++) {
466 // Load one integer register's worth from the original location.
467 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
468 LD->getPointerInfo().getWithOffset(Offset),
469 LD->isVolatile(), LD->isNonTemporal(),
471 MinAlign(LD->getAlignment(), Offset));
472 // Follow the load with a store to the stack slot. Remember the store.
473 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
474 MachinePointerInfo(), false, false, 0));
475 // Increment the pointers.
477 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
478 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
482 // The last copy may be partial. Do an extending load.
483 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
484 8 * (LoadedBytes - Offset));
485 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
486 LD->getPointerInfo().getWithOffset(Offset),
487 MemVT, LD->isVolatile(),
489 MinAlign(LD->getAlignment(), Offset));
490 // Follow the load with a store to the stack slot. Remember the store.
491 // On big-endian machines this requires a truncating store to ensure
492 // that the bits end up in the right place.
493 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
494 MachinePointerInfo(), MemVT,
497 // The order of the stores doesn't matter - say it with a TokenFactor.
498 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
501 // Finally, perform the original load only redirected to the stack slot.
502 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
503 MachinePointerInfo(), LoadedVT, false, false, 0);
505 // Callers expect a MERGE_VALUES node.
510 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
511 "Unaligned load of unsupported type.");
513 // Compute the new VT that is half the size of the old one. This is an
515 unsigned NumBits = LoadedVT.getSizeInBits();
517 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
520 unsigned Alignment = LD->getAlignment();
521 unsigned IncrementSize = NumBits / 8;
522 ISD::LoadExtType HiExtType = LD->getExtensionType();
524 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
525 if (HiExtType == ISD::NON_EXTLOAD)
526 HiExtType = ISD::ZEXTLOAD;
528 // Load the value in two parts
530 if (TLI.isLittleEndian()) {
531 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
532 NewLoadedVT, LD->isVolatile(),
533 LD->isNonTemporal(), Alignment);
534 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
535 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
536 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
537 LD->getPointerInfo().getWithOffset(IncrementSize),
538 NewLoadedVT, LD->isVolatile(),
539 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
541 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
542 NewLoadedVT, LD->isVolatile(),
543 LD->isNonTemporal(), Alignment);
544 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
545 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
546 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
547 LD->getPointerInfo().getWithOffset(IncrementSize),
548 NewLoadedVT, LD->isVolatile(),
549 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
552 // aggregate the two parts
553 SDValue ShiftAmount = DAG.getConstant(NumBits,
554 TLI.getShiftAmountTy(Hi.getValueType()));
555 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
556 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
558 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
565 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
566 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
567 /// is necessary to spill the vector being inserted into to memory, perform
568 /// the insert there, and then read the result back.
569 SDValue SelectionDAGLegalize::
570 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
576 // If the target doesn't support this, we have to spill the input vector
577 // to a temporary stack slot, update the element, then reload it. This is
578 // badness. We could also load the value into a vector register (either
579 // with a "move to register" or "extload into register" instruction, then
580 // permute it into place, if the idx is a constant and if the idx is
581 // supported by the target.
582 EVT VT = Tmp1.getValueType();
583 EVT EltVT = VT.getVectorElementType();
584 EVT IdxVT = Tmp3.getValueType();
585 EVT PtrVT = TLI.getPointerTy();
586 SDValue StackPtr = DAG.CreateStackTemporary(VT);
588 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
591 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
592 MachinePointerInfo::getFixedStack(SPFI),
595 // Truncate or zero extend offset to target pointer type.
596 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
597 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
598 // Add the offset to the index.
599 unsigned EltSize = EltVT.getSizeInBits()/8;
600 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
601 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
602 // Store the scalar value.
603 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
605 // Load the updated vector.
606 return DAG.getLoad(VT, dl, Ch, StackPtr,
607 MachinePointerInfo::getFixedStack(SPFI), false, false,
612 SDValue SelectionDAGLegalize::
613 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
614 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
615 // SCALAR_TO_VECTOR requires that the type of the value being inserted
616 // match the element type of the vector being created, except for
617 // integers in which case the inserted value can be over width.
618 EVT EltVT = Vec.getValueType().getVectorElementType();
619 if (Val.getValueType() == EltVT ||
620 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
621 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
622 Vec.getValueType(), Val);
624 unsigned NumElts = Vec.getValueType().getVectorNumElements();
625 // We generate a shuffle of InVec and ScVec, so the shuffle mask
626 // should be 0,1,2,3,4,5... with the appropriate element replaced with
628 SmallVector<int, 8> ShufOps;
629 for (unsigned i = 0; i != NumElts; ++i)
630 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
632 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
636 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
639 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
640 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
641 // FIXME: We shouldn't do this for TargetConstantFP's.
642 // FIXME: move this to the DAG Combiner! Note that we can't regress due
643 // to phase ordering between legalized code and the dag combiner. This
644 // probably means that we need to integrate dag combiner and legalizer
646 // We generally can't do this one for long doubles.
647 SDValue Chain = ST->getChain();
648 SDValue Ptr = ST->getBasePtr();
649 unsigned Alignment = ST->getAlignment();
650 bool isVolatile = ST->isVolatile();
651 bool isNonTemporal = ST->isNonTemporal();
652 DebugLoc dl = ST->getDebugLoc();
653 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
654 if (CFP->getValueType(0) == MVT::f32 &&
655 TLI.isTypeLegal(MVT::i32)) {
656 SDValue Con = DAG.getConstant(CFP->getValueAPF().
657 bitcastToAPInt().zextOrTrunc(32),
659 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
660 isVolatile, isNonTemporal, Alignment);
663 if (CFP->getValueType(0) == MVT::f64) {
664 // If this target supports 64-bit registers, do a single 64-bit store.
665 if (TLI.isTypeLegal(MVT::i64)) {
666 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
667 zextOrTrunc(64), MVT::i64);
668 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
669 isVolatile, isNonTemporal, Alignment);
672 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
673 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
674 // stores. If the target supports neither 32- nor 64-bits, this
675 // xform is certainly not worth it.
676 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
677 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
678 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
679 if (TLI.isBigEndian()) std::swap(Lo, Hi);
681 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
682 isNonTemporal, Alignment);
683 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
684 DAG.getIntPtrConstant(4));
685 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
686 ST->getPointerInfo().getWithOffset(4),
687 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
689 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
693 return SDValue(0, 0);
696 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
697 StoreSDNode *ST = cast<StoreSDNode>(Node);
698 SDValue Chain = ST->getChain();
699 SDValue Ptr = ST->getBasePtr();
700 DebugLoc dl = Node->getDebugLoc();
702 unsigned Alignment = ST->getAlignment();
703 bool isVolatile = ST->isVolatile();
704 bool isNonTemporal = ST->isNonTemporal();
706 if (!ST->isTruncatingStore()) {
707 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
708 ReplaceNode(ST, OptStore);
713 SDValue Value = ST->getValue();
714 MVT VT = Value.getSimpleValueType();
715 switch (TLI.getOperationAction(ISD::STORE, VT)) {
716 default: llvm_unreachable("This action is not supported yet!");
717 case TargetLowering::Legal:
718 // If this is an unaligned store and the target doesn't support it,
720 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
721 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
722 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
723 if (ST->getAlignment() < ABIAlignment)
724 ExpandUnalignedStore(cast<StoreSDNode>(Node),
728 case TargetLowering::Custom: {
729 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
731 ReplaceNode(SDValue(Node, 0), Res);
734 case TargetLowering::Promote: {
735 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
736 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
737 "Can only promote stores to same size type");
738 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
740 DAG.getStore(Chain, dl, Value, Ptr,
741 ST->getPointerInfo(), isVolatile,
742 isNonTemporal, Alignment);
743 ReplaceNode(SDValue(Node, 0), Result);
750 SDValue Value = ST->getValue();
752 EVT StVT = ST->getMemoryVT();
753 unsigned StWidth = StVT.getSizeInBits();
755 if (StWidth != StVT.getStoreSizeInBits()) {
756 // Promote to a byte-sized store with upper bits zero if not
757 // storing an integral number of bytes. For example, promote
758 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
759 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
760 StVT.getStoreSizeInBits());
761 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
763 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
764 NVT, isVolatile, isNonTemporal, Alignment);
765 ReplaceNode(SDValue(Node, 0), Result);
766 } else if (StWidth & (StWidth - 1)) {
767 // If not storing a power-of-2 number of bits, expand as two stores.
768 assert(!StVT.isVector() && "Unsupported truncstore!");
769 unsigned RoundWidth = 1 << Log2_32(StWidth);
770 assert(RoundWidth < StWidth);
771 unsigned ExtraWidth = StWidth - RoundWidth;
772 assert(ExtraWidth < RoundWidth);
773 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
774 "Store size not an integral number of bytes!");
775 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
776 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
778 unsigned IncrementSize;
780 if (TLI.isLittleEndian()) {
781 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
782 // Store the bottom RoundWidth bits.
783 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
785 isVolatile, isNonTemporal, Alignment);
787 // Store the remaining ExtraWidth bits.
788 IncrementSize = RoundWidth / 8;
789 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
790 DAG.getIntPtrConstant(IncrementSize));
791 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
792 DAG.getConstant(RoundWidth,
793 TLI.getShiftAmountTy(Value.getValueType())));
794 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
795 ST->getPointerInfo().getWithOffset(IncrementSize),
796 ExtraVT, isVolatile, isNonTemporal,
797 MinAlign(Alignment, IncrementSize));
799 // Big endian - avoid unaligned stores.
800 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
801 // Store the top RoundWidth bits.
802 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
803 DAG.getConstant(ExtraWidth,
804 TLI.getShiftAmountTy(Value.getValueType())));
805 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
806 RoundVT, isVolatile, isNonTemporal, Alignment);
808 // Store the remaining ExtraWidth bits.
809 IncrementSize = RoundWidth / 8;
810 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
811 DAG.getIntPtrConstant(IncrementSize));
812 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
813 ST->getPointerInfo().getWithOffset(IncrementSize),
814 ExtraVT, isVolatile, isNonTemporal,
815 MinAlign(Alignment, IncrementSize));
818 // The order of the stores doesn't matter.
819 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
820 ReplaceNode(SDValue(Node, 0), Result);
822 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(),
823 StVT.getSimpleVT())) {
824 default: llvm_unreachable("This action is not supported yet!");
825 case TargetLowering::Legal:
826 // If this is an unaligned store and the target doesn't support it,
828 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
829 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
830 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
831 if (ST->getAlignment() < ABIAlignment)
832 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
835 case TargetLowering::Custom: {
836 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
838 ReplaceNode(SDValue(Node, 0), Res);
841 case TargetLowering::Expand:
842 assert(!StVT.isVector() &&
843 "Vector Stores are handled in LegalizeVectorOps");
845 // TRUNCSTORE:i16 i32 -> STORE i16
846 assert(TLI.isTypeLegal(StVT) &&
847 "Do not know how to expand this store!");
848 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
850 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
851 isVolatile, isNonTemporal, Alignment);
852 ReplaceNode(SDValue(Node, 0), Result);
859 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
860 LoadSDNode *LD = cast<LoadSDNode>(Node);
861 SDValue Chain = LD->getChain(); // The chain.
862 SDValue Ptr = LD->getBasePtr(); // The base pointer.
863 SDValue Value; // The value returned by the load op.
864 DebugLoc dl = Node->getDebugLoc();
866 ISD::LoadExtType ExtType = LD->getExtensionType();
867 if (ExtType == ISD::NON_EXTLOAD) {
868 MVT VT = Node->getSimpleValueType(0);
869 SDValue RVal = SDValue(Node, 0);
870 SDValue RChain = SDValue(Node, 1);
872 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
873 default: llvm_unreachable("This action is not supported yet!");
874 case TargetLowering::Legal:
875 // If this is an unaligned load and the target doesn't support it,
877 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
878 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
879 unsigned ABIAlignment =
880 TLI.getDataLayout()->getABITypeAlignment(Ty);
881 if (LD->getAlignment() < ABIAlignment){
882 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
886 case TargetLowering::Custom: {
887 SDValue Res = TLI.LowerOperation(RVal, DAG);
890 RChain = Res.getValue(1);
894 case TargetLowering::Promote: {
895 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
896 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
897 "Can only promote loads to same size type");
899 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getPointerInfo(),
900 LD->isVolatile(), LD->isNonTemporal(),
901 LD->isInvariant(), LD->getAlignment());
902 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
903 RChain = Res.getValue(1);
907 if (RChain.getNode() != Node) {
908 assert(RVal.getNode() != Node && "Load must be completely replaced");
909 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
910 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
916 EVT SrcVT = LD->getMemoryVT();
917 unsigned SrcWidth = SrcVT.getSizeInBits();
918 unsigned Alignment = LD->getAlignment();
919 bool isVolatile = LD->isVolatile();
920 bool isNonTemporal = LD->isNonTemporal();
922 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
923 // Some targets pretend to have an i1 loading operation, and actually
924 // load an i8. This trick is correct for ZEXTLOAD because the top 7
925 // bits are guaranteed to be zero; it helps the optimizers understand
926 // that these bits are zero. It is also useful for EXTLOAD, since it
927 // tells the optimizers that those bits are undefined. It would be
928 // nice to have an effective generic way of getting these benefits...
929 // Until such a way is found, don't insist on promoting i1 here.
931 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
932 // Promote to a byte-sized load if not loading an integral number of
933 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
934 unsigned NewWidth = SrcVT.getStoreSizeInBits();
935 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
938 // The extra bits are guaranteed to be zero, since we stored them that
939 // way. A zext load from NVT thus automatically gives zext from SrcVT.
941 ISD::LoadExtType NewExtType =
942 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
945 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
946 Chain, Ptr, LD->getPointerInfo(),
947 NVT, isVolatile, isNonTemporal, Alignment);
949 Ch = Result.getValue(1); // The chain.
951 if (ExtType == ISD::SEXTLOAD)
952 // Having the top bits zero doesn't help when sign extending.
953 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
954 Result.getValueType(),
955 Result, DAG.getValueType(SrcVT));
956 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
957 // All the top bits are guaranteed to be zero - inform the optimizers.
958 Result = DAG.getNode(ISD::AssertZext, dl,
959 Result.getValueType(), Result,
960 DAG.getValueType(SrcVT));
964 } else if (SrcWidth & (SrcWidth - 1)) {
965 // If not loading a power-of-2 number of bits, expand as two loads.
966 assert(!SrcVT.isVector() && "Unsupported extload!");
967 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
968 assert(RoundWidth < SrcWidth);
969 unsigned ExtraWidth = SrcWidth - RoundWidth;
970 assert(ExtraWidth < RoundWidth);
971 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
972 "Load size not an integral number of bytes!");
973 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
974 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
976 unsigned IncrementSize;
978 if (TLI.isLittleEndian()) {
979 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
980 // Load the bottom RoundWidth bits.
981 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
983 LD->getPointerInfo(), RoundVT, isVolatile,
984 isNonTemporal, Alignment);
986 // Load the remaining ExtraWidth bits.
987 IncrementSize = RoundWidth / 8;
988 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
989 DAG.getIntPtrConstant(IncrementSize));
990 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
991 LD->getPointerInfo().getWithOffset(IncrementSize),
992 ExtraVT, isVolatile, isNonTemporal,
993 MinAlign(Alignment, IncrementSize));
995 // Build a factor node to remember that this load is independent of
997 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1000 // Move the top bits to the right place.
1001 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1002 DAG.getConstant(RoundWidth,
1003 TLI.getShiftAmountTy(Hi.getValueType())));
1005 // Join the hi and lo parts.
1006 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1008 // Big endian - avoid unaligned loads.
1009 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1010 // Load the top RoundWidth bits.
1011 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1012 LD->getPointerInfo(), RoundVT, isVolatile,
1013 isNonTemporal, Alignment);
1015 // Load the remaining ExtraWidth bits.
1016 IncrementSize = RoundWidth / 8;
1017 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1018 DAG.getIntPtrConstant(IncrementSize));
1019 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1020 dl, Node->getValueType(0), Chain, Ptr,
1021 LD->getPointerInfo().getWithOffset(IncrementSize),
1022 ExtraVT, isVolatile, isNonTemporal,
1023 MinAlign(Alignment, IncrementSize));
1025 // Build a factor node to remember that this load is independent of
1027 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1030 // Move the top bits to the right place.
1031 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1032 DAG.getConstant(ExtraWidth,
1033 TLI.getShiftAmountTy(Hi.getValueType())));
1035 // Join the hi and lo parts.
1036 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1041 bool isCustom = false;
1042 switch (TLI.getLoadExtAction(ExtType, SrcVT.getSimpleVT())) {
1043 default: llvm_unreachable("This action is not supported yet!");
1044 case TargetLowering::Custom:
1047 case TargetLowering::Legal: {
1048 Value = SDValue(Node, 0);
1049 Chain = SDValue(Node, 1);
1052 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1053 if (Res.getNode()) {
1055 Chain = Res.getValue(1);
1058 // If this is an unaligned load and the target doesn't support it,
1060 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1062 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1063 unsigned ABIAlignment =
1064 TLI.getDataLayout()->getABITypeAlignment(Ty);
1065 if (LD->getAlignment() < ABIAlignment){
1066 ExpandUnalignedLoad(cast<LoadSDNode>(Node),
1067 DAG, TLI, Value, Chain);
1073 case TargetLowering::Expand:
1074 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
1075 SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr,
1076 LD->getPointerInfo(),
1077 LD->isVolatile(), LD->isNonTemporal(),
1078 LD->isInvariant(), LD->getAlignment());
1082 ExtendOp = (SrcVT.isFloatingPoint() ?
1083 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1085 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1086 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1087 default: llvm_unreachable("Unexpected extend load type!");
1089 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1090 Chain = Load.getValue(1);
1094 assert(!SrcVT.isVector() &&
1095 "Vector Loads are handled in LegalizeVectorOps");
1097 // FIXME: This does not work for vectors on most targets. Sign- and
1098 // zero-extend operations are currently folded into extending loads,
1099 // whether they are legal or not, and then we end up here without any
1100 // support for legalizing them.
1101 assert(ExtType != ISD::EXTLOAD &&
1102 "EXTLOAD should always be supported!");
1103 // Turn the unsupported load into an EXTLOAD followed by an explicit
1104 // zero/sign extend inreg.
1105 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1106 Chain, Ptr, LD->getPointerInfo(), SrcVT,
1107 LD->isVolatile(), LD->isNonTemporal(),
1108 LD->getAlignment());
1110 if (ExtType == ISD::SEXTLOAD)
1111 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1112 Result.getValueType(),
1113 Result, DAG.getValueType(SrcVT));
1115 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1117 Chain = Result.getValue(1);
1122 // Since loads produce two values, make sure to remember that we legalized
1124 if (Chain.getNode() != Node) {
1125 assert(Value.getNode() != Node && "Load must be completely replaced");
1126 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1127 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1132 /// LegalizeOp - Return a legal replacement for the given operation, with
1133 /// all legal operands.
1134 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1135 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1138 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1139 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1140 TargetLowering::TypeLegal &&
1141 "Unexpected illegal type!");
1143 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1144 assert((TLI.getTypeAction(*DAG.getContext(),
1145 Node->getOperand(i).getValueType()) ==
1146 TargetLowering::TypeLegal ||
1147 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1148 "Unexpected illegal type!");
1150 // Figure out the correct action; the way to query this varies by opcode
1151 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1152 bool SimpleFinishLegalizing = true;
1153 switch (Node->getOpcode()) {
1154 case ISD::INTRINSIC_W_CHAIN:
1155 case ISD::INTRINSIC_WO_CHAIN:
1156 case ISD::INTRINSIC_VOID:
1157 case ISD::STACKSAVE:
1158 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1161 Action = TLI.getOperationAction(Node->getOpcode(),
1162 Node->getValueType(0));
1163 if (Action != TargetLowering::Promote)
1164 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1166 case ISD::SINT_TO_FP:
1167 case ISD::UINT_TO_FP:
1168 case ISD::EXTRACT_VECTOR_ELT:
1169 Action = TLI.getOperationAction(Node->getOpcode(),
1170 Node->getOperand(0).getValueType());
1172 case ISD::FP_ROUND_INREG:
1173 case ISD::SIGN_EXTEND_INREG: {
1174 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1175 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1178 case ISD::ATOMIC_STORE: {
1179 Action = TLI.getOperationAction(Node->getOpcode(),
1180 Node->getOperand(2).getValueType());
1183 case ISD::SELECT_CC:
1186 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1187 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1188 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1189 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1190 ISD::CondCode CCCode =
1191 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1192 Action = TLI.getCondCodeAction(CCCode, OpVT);
1193 if (Action == TargetLowering::Legal) {
1194 if (Node->getOpcode() == ISD::SELECT_CC)
1195 Action = TLI.getOperationAction(Node->getOpcode(),
1196 Node->getValueType(0));
1198 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1204 // FIXME: Model these properly. LOAD and STORE are complicated, and
1205 // STORE expects the unlegalized operand in some cases.
1206 SimpleFinishLegalizing = false;
1208 case ISD::CALLSEQ_START:
1209 case ISD::CALLSEQ_END:
1210 // FIXME: This shouldn't be necessary. These nodes have special properties
1211 // dealing with the recursive nature of legalization. Removing this
1212 // special case should be done as part of making LegalizeDAG non-recursive.
1213 SimpleFinishLegalizing = false;
1215 case ISD::EXTRACT_ELEMENT:
1216 case ISD::FLT_ROUNDS_:
1224 case ISD::MERGE_VALUES:
1225 case ISD::EH_RETURN:
1226 case ISD::FRAME_TO_ARGS_OFFSET:
1227 case ISD::EH_SJLJ_SETJMP:
1228 case ISD::EH_SJLJ_LONGJMP:
1229 // These operations lie about being legal: when they claim to be legal,
1230 // they should actually be expanded.
1231 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1232 if (Action == TargetLowering::Legal)
1233 Action = TargetLowering::Expand;
1235 case ISD::INIT_TRAMPOLINE:
1236 case ISD::ADJUST_TRAMPOLINE:
1237 case ISD::FRAMEADDR:
1238 case ISD::RETURNADDR:
1239 // These operations lie about being legal: when they claim to be legal,
1240 // they should actually be custom-lowered.
1241 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1242 if (Action == TargetLowering::Legal)
1243 Action = TargetLowering::Custom;
1245 case ISD::DEBUGTRAP:
1246 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1247 if (Action == TargetLowering::Expand) {
1248 // replace ISD::DEBUGTRAP with ISD::TRAP
1250 NewVal = DAG.getNode(ISD::TRAP, Node->getDebugLoc(), Node->getVTList(),
1251 Node->getOperand(0));
1252 ReplaceNode(Node, NewVal.getNode());
1253 LegalizeOp(NewVal.getNode());
1259 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1260 Action = TargetLowering::Legal;
1262 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1267 if (SimpleFinishLegalizing) {
1268 SDNode *NewNode = Node;
1269 switch (Node->getOpcode()) {
1276 // Legalizing shifts/rotates requires adjusting the shift amount
1277 // to the appropriate width.
1278 if (!Node->getOperand(1).getValueType().isVector()) {
1280 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1281 Node->getOperand(1));
1282 HandleSDNode Handle(SAO);
1283 LegalizeOp(SAO.getNode());
1284 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1288 case ISD::SRL_PARTS:
1289 case ISD::SRA_PARTS:
1290 case ISD::SHL_PARTS:
1291 // Legalizing shifts/rotates requires adjusting the shift amount
1292 // to the appropriate width.
1293 if (!Node->getOperand(2).getValueType().isVector()) {
1295 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1296 Node->getOperand(2));
1297 HandleSDNode Handle(SAO);
1298 LegalizeOp(SAO.getNode());
1299 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1300 Node->getOperand(1),
1306 if (NewNode != Node) {
1307 DAG.ReplaceAllUsesWith(Node, NewNode);
1308 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1309 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
1314 case TargetLowering::Legal:
1316 case TargetLowering::Custom: {
1317 // FIXME: The handling for custom lowering with multiple results is
1319 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1320 if (Res.getNode()) {
1321 SmallVector<SDValue, 8> ResultVals;
1322 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1324 ResultVals.push_back(Res);
1326 ResultVals.push_back(Res.getValue(i));
1328 if (Res.getNode() != Node || Res.getResNo() != 0) {
1329 DAG.ReplaceAllUsesWith(Node, ResultVals.data());
1330 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1331 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
1338 case TargetLowering::Expand:
1341 case TargetLowering::Promote:
1347 switch (Node->getOpcode()) {
1354 llvm_unreachable("Do not know how to legalize this operator!");
1356 case ISD::CALLSEQ_START:
1357 case ISD::CALLSEQ_END:
1360 return LegalizeLoadOps(Node);
1363 return LegalizeStoreOps(Node);
1368 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1369 SDValue Vec = Op.getOperand(0);
1370 SDValue Idx = Op.getOperand(1);
1371 DebugLoc dl = Op.getDebugLoc();
1372 // Store the value to a temporary stack slot, then LOAD the returned part.
1373 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1374 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1375 MachinePointerInfo(), false, false, 0);
1377 // Add the offset to the index.
1379 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1380 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1381 DAG.getConstant(EltSize, Idx.getValueType()));
1383 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1384 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1386 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1388 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1390 if (Op.getValueType().isVector())
1391 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1392 false, false, false, 0);
1393 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1394 MachinePointerInfo(),
1395 Vec.getValueType().getVectorElementType(),
1399 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1400 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1402 SDValue Vec = Op.getOperand(0);
1403 SDValue Part = Op.getOperand(1);
1404 SDValue Idx = Op.getOperand(2);
1405 DebugLoc dl = Op.getDebugLoc();
1407 // Store the value to a temporary stack slot, then LOAD the returned part.
1409 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1410 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1411 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1413 // First store the whole vector.
1414 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1417 // Then store the inserted part.
1419 // Add the offset to the index.
1421 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1423 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1424 DAG.getConstant(EltSize, Idx.getValueType()));
1426 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1427 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1429 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1431 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1434 // Store the subvector.
1435 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1436 MachinePointerInfo(), false, false, 0);
1438 // Finally, load the updated vector.
1439 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1440 false, false, false, 0);
1443 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1444 // We can't handle this case efficiently. Allocate a sufficiently
1445 // aligned object on the stack, store each element into it, then load
1446 // the result as a vector.
1447 // Create the stack frame object.
1448 EVT VT = Node->getValueType(0);
1449 EVT EltVT = VT.getVectorElementType();
1450 DebugLoc dl = Node->getDebugLoc();
1451 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1452 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1453 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1455 // Emit a store of each element to the stack slot.
1456 SmallVector<SDValue, 8> Stores;
1457 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1458 // Store (in the right endianness) the elements to memory.
1459 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1460 // Ignore undef elements.
1461 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1463 unsigned Offset = TypeByteSize*i;
1465 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1466 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1468 // If the destination vector element type is narrower than the source
1469 // element type, only store the bits necessary.
1470 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1471 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1472 Node->getOperand(i), Idx,
1473 PtrInfo.getWithOffset(Offset),
1474 EltVT, false, false, 0));
1476 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1477 Node->getOperand(i), Idx,
1478 PtrInfo.getWithOffset(Offset),
1483 if (!Stores.empty()) // Not all undef elements?
1484 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1485 &Stores[0], Stores.size());
1487 StoreChain = DAG.getEntryNode();
1489 // Result is a load from the stack slot.
1490 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1491 false, false, false, 0);
1494 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1495 DebugLoc dl = Node->getDebugLoc();
1496 SDValue Tmp1 = Node->getOperand(0);
1497 SDValue Tmp2 = Node->getOperand(1);
1499 // Get the sign bit of the RHS. First obtain a value that has the same
1500 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1502 EVT FloatVT = Tmp2.getValueType();
1503 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1504 if (TLI.isTypeLegal(IVT)) {
1505 // Convert to an integer with the same sign bit.
1506 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1508 // Store the float to memory, then load the sign part out as an integer.
1509 MVT LoadTy = TLI.getPointerTy();
1510 // First create a temporary that is aligned for both the load and store.
1511 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1512 // Then store the float to it.
1514 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1516 if (TLI.isBigEndian()) {
1517 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1518 // Load out a legal integer with the same sign bit as the float.
1519 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1520 false, false, false, 0);
1521 } else { // Little endian
1522 SDValue LoadPtr = StackPtr;
1523 // The float may be wider than the integer we are going to load. Advance
1524 // the pointer so that the loaded integer will contain the sign bit.
1525 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1526 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1527 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1528 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1529 // Load a legal integer containing the sign bit.
1530 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1531 false, false, false, 0);
1532 // Move the sign bit to the top bit of the loaded integer.
1533 unsigned BitShift = LoadTy.getSizeInBits() -
1534 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1535 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1537 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1538 DAG.getConstant(BitShift,
1539 TLI.getShiftAmountTy(SignBit.getValueType())));
1542 // Now get the sign bit proper, by seeing whether the value is negative.
1543 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1544 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1546 // Get the absolute value of the result.
1547 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1548 // Select between the nabs and abs value based on the sign bit of
1550 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1551 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1555 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1556 SmallVectorImpl<SDValue> &Results) {
1557 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1558 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1559 " not tell us which reg is the stack pointer!");
1560 DebugLoc dl = Node->getDebugLoc();
1561 EVT VT = Node->getValueType(0);
1562 SDValue Tmp1 = SDValue(Node, 0);
1563 SDValue Tmp2 = SDValue(Node, 1);
1564 SDValue Tmp3 = Node->getOperand(2);
1565 SDValue Chain = Tmp1.getOperand(0);
1567 // Chain the dynamic stack allocation so that it doesn't modify the stack
1568 // pointer when other instructions are using the stack.
1569 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1571 SDValue Size = Tmp2.getOperand(1);
1572 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1573 Chain = SP.getValue(1);
1574 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1575 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1576 if (Align > StackAlign)
1577 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1578 DAG.getConstant(-(uint64_t)Align, VT));
1579 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1580 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1582 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1583 DAG.getIntPtrConstant(0, true), SDValue());
1585 Results.push_back(Tmp1);
1586 Results.push_back(Tmp2);
1589 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1590 /// condition code CC on the current target. This routine expands SETCC with
1591 /// illegal condition code into AND / OR of multiple SETCC values.
1592 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1593 SDValue &LHS, SDValue &RHS,
1596 MVT OpVT = LHS.getSimpleValueType();
1597 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1598 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1599 default: llvm_unreachable("Unknown condition code action!");
1600 case TargetLowering::Legal:
1603 case TargetLowering::Expand: {
1604 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1605 ISD::CondCode InvCC = ISD::SETCC_INVALID;
1608 default: llvm_unreachable("Don't know how to expand this condition!");
1610 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1611 == TargetLowering::Legal
1612 && "If SETO is expanded, SETOEQ must be legal!");
1613 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1615 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1616 == TargetLowering::Legal
1617 && "If SETUO is expanded, SETUNE must be legal!");
1618 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1631 // If we are floating point, assign and break, otherwise fall through.
1632 if (!OpVT.isInteger()) {
1633 // We can use the 4th bit to tell if we are the unordered
1634 // or ordered version of the opcode.
1635 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1636 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1637 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1640 // Fallthrough if we are unsigned integer.
1647 InvCC = ISD::getSetCCSwappedOperands(CCCode);
1648 if (TLI.getCondCodeAction(InvCC, OpVT) == TargetLowering::Expand) {
1649 // We only support using the inverted operation and not a
1650 // different manner of supporting expanding these cases.
1651 llvm_unreachable("Don't know how to expand this condition!");
1653 LHS = DAG.getSetCC(dl, VT, RHS, LHS, InvCC);
1659 SDValue SetCC1, SetCC2;
1660 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1661 // If we aren't the ordered or unorder operation,
1662 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1663 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1664 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1666 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1667 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1668 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1670 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1678 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1679 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1680 /// a load from the stack slot to DestVT, extending it if needed.
1681 /// The resultant code need not be legal.
1682 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1686 // Create the stack frame object.
1688 TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType().
1689 getTypeForEVT(*DAG.getContext()));
1690 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1692 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1693 int SPFI = StackPtrFI->getIndex();
1694 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1696 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1697 unsigned SlotSize = SlotVT.getSizeInBits();
1698 unsigned DestSize = DestVT.getSizeInBits();
1699 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1700 unsigned DestAlign = TLI.getDataLayout()->getPrefTypeAlignment(DestType);
1702 // Emit a store to the stack slot. Use a truncstore if the input value is
1703 // later than DestVT.
1706 if (SrcSize > SlotSize)
1707 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1708 PtrInfo, SlotVT, false, false, SrcAlign);
1710 assert(SrcSize == SlotSize && "Invalid store");
1711 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1712 PtrInfo, false, false, SrcAlign);
1715 // Result is a load from the stack slot.
1716 if (SlotSize == DestSize)
1717 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1718 false, false, false, DestAlign);
1720 assert(SlotSize < DestSize && "Unknown extension!");
1721 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1722 PtrInfo, SlotVT, false, false, DestAlign);
1725 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1726 DebugLoc dl = Node->getDebugLoc();
1727 // Create a vector sized/aligned stack slot, store the value to element #0,
1728 // then load the whole vector back out.
1729 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1731 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1732 int SPFI = StackPtrFI->getIndex();
1734 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1736 MachinePointerInfo::getFixedStack(SPFI),
1737 Node->getValueType(0).getVectorElementType(),
1739 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1740 MachinePointerInfo::getFixedStack(SPFI),
1741 false, false, false, 0);
1745 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1746 /// support the operation, but do support the resultant vector type.
1747 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1748 unsigned NumElems = Node->getNumOperands();
1749 SDValue Value1, Value2;
1750 DebugLoc dl = Node->getDebugLoc();
1751 EVT VT = Node->getValueType(0);
1752 EVT OpVT = Node->getOperand(0).getValueType();
1753 EVT EltVT = VT.getVectorElementType();
1755 // If the only non-undef value is the low element, turn this into a
1756 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1757 bool isOnlyLowElement = true;
1758 bool MoreThanTwoValues = false;
1759 bool isConstant = true;
1760 for (unsigned i = 0; i < NumElems; ++i) {
1761 SDValue V = Node->getOperand(i);
1762 if (V.getOpcode() == ISD::UNDEF)
1765 isOnlyLowElement = false;
1766 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1769 if (!Value1.getNode()) {
1771 } else if (!Value2.getNode()) {
1774 } else if (V != Value1 && V != Value2) {
1775 MoreThanTwoValues = true;
1779 if (!Value1.getNode())
1780 return DAG.getUNDEF(VT);
1782 if (isOnlyLowElement)
1783 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1785 // If all elements are constants, create a load from the constant pool.
1787 SmallVector<Constant*, 16> CV;
1788 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1789 if (ConstantFPSDNode *V =
1790 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1791 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1792 } else if (ConstantSDNode *V =
1793 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1795 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1797 // If OpVT and EltVT don't match, EltVT is not legal and the
1798 // element values have been promoted/truncated earlier. Undo this;
1799 // we don't want a v16i8 to become a v16i32 for example.
1800 const ConstantInt *CI = V->getConstantIntValue();
1801 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1802 CI->getZExtValue()));
1805 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1806 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1807 CV.push_back(UndefValue::get(OpNTy));
1810 Constant *CP = ConstantVector::get(CV);
1811 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1812 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1813 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1814 MachinePointerInfo::getConstantPool(),
1815 false, false, false, Alignment);
1818 if (!MoreThanTwoValues) {
1819 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1820 for (unsigned i = 0; i < NumElems; ++i) {
1821 SDValue V = Node->getOperand(i);
1822 if (V.getOpcode() == ISD::UNDEF)
1824 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1826 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1827 // Get the splatted value into the low element of a vector register.
1828 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1830 if (Value2.getNode())
1831 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1833 Vec2 = DAG.getUNDEF(VT);
1835 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1836 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1840 // Otherwise, we can't handle this case efficiently.
1841 return ExpandVectorBuildThroughStack(Node);
1844 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1845 // does not fit into a register, return the lo part and set the hi part to the
1846 // by-reg argument. If it does fit into a single register, return the result
1847 // and leave the Hi part unset.
1848 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1850 TargetLowering::ArgListTy Args;
1851 TargetLowering::ArgListEntry Entry;
1852 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1853 EVT ArgVT = Node->getOperand(i).getValueType();
1854 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1855 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1856 Entry.isSExt = isSigned;
1857 Entry.isZExt = !isSigned;
1858 Args.push_back(Entry);
1860 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1861 TLI.getPointerTy());
1863 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1865 // By default, the input chain to this libcall is the entry node of the
1866 // function. If the libcall is going to be emitted as a tail call then
1867 // TLI.isUsedByReturnOnly will change it to the right chain if the return
1868 // node which is being folded has a non-entry input chain.
1869 SDValue InChain = DAG.getEntryNode();
1871 // isTailCall may be true since the callee does not reference caller stack
1872 // frame. Check if it's in the right position.
1873 SDValue TCChain = InChain;
1874 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
1879 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1880 0, TLI.getLibcallCallingConv(LC), isTailCall,
1881 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1882 Callee, Args, DAG, Node->getDebugLoc());
1883 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1886 if (!CallInfo.second.getNode())
1887 // It's a tailcall, return the chain (which is the DAG root).
1888 return DAG.getRoot();
1890 return CallInfo.first;
1893 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
1894 /// and returning a result of type RetVT.
1895 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
1896 const SDValue *Ops, unsigned NumOps,
1897 bool isSigned, DebugLoc dl) {
1898 TargetLowering::ArgListTy Args;
1899 Args.reserve(NumOps);
1901 TargetLowering::ArgListEntry Entry;
1902 for (unsigned i = 0; i != NumOps; ++i) {
1903 Entry.Node = Ops[i];
1904 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
1905 Entry.isSExt = isSigned;
1906 Entry.isZExt = !isSigned;
1907 Args.push_back(Entry);
1909 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1910 TLI.getPointerTy());
1912 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
1914 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
1915 false, 0, TLI.getLibcallCallingConv(LC),
1916 /*isTailCall=*/false,
1917 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1918 Callee, Args, DAG, dl);
1919 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
1921 return CallInfo.first;
1924 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
1925 // ExpandLibCall except that the first operand is the in-chain.
1926 std::pair<SDValue, SDValue>
1927 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
1930 SDValue InChain = Node->getOperand(0);
1932 TargetLowering::ArgListTy Args;
1933 TargetLowering::ArgListEntry Entry;
1934 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
1935 EVT ArgVT = Node->getOperand(i).getValueType();
1936 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1937 Entry.Node = Node->getOperand(i);
1939 Entry.isSExt = isSigned;
1940 Entry.isZExt = !isSigned;
1941 Args.push_back(Entry);
1943 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1944 TLI.getPointerTy());
1946 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1948 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1949 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
1950 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1951 Callee, Args, DAG, Node->getDebugLoc());
1952 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1957 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1958 RTLIB::Libcall Call_F32,
1959 RTLIB::Libcall Call_F64,
1960 RTLIB::Libcall Call_F80,
1961 RTLIB::Libcall Call_F128,
1962 RTLIB::Libcall Call_PPCF128) {
1964 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1965 default: llvm_unreachable("Unexpected request for libcall!");
1966 case MVT::f32: LC = Call_F32; break;
1967 case MVT::f64: LC = Call_F64; break;
1968 case MVT::f80: LC = Call_F80; break;
1969 case MVT::f128: LC = Call_F128; break;
1970 case MVT::ppcf128: LC = Call_PPCF128; break;
1972 return ExpandLibCall(LC, Node, false);
1975 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1976 RTLIB::Libcall Call_I8,
1977 RTLIB::Libcall Call_I16,
1978 RTLIB::Libcall Call_I32,
1979 RTLIB::Libcall Call_I64,
1980 RTLIB::Libcall Call_I128) {
1982 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1983 default: llvm_unreachable("Unexpected request for libcall!");
1984 case MVT::i8: LC = Call_I8; break;
1985 case MVT::i16: LC = Call_I16; break;
1986 case MVT::i32: LC = Call_I32; break;
1987 case MVT::i64: LC = Call_I64; break;
1988 case MVT::i128: LC = Call_I128; break;
1990 return ExpandLibCall(LC, Node, isSigned);
1993 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
1994 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
1995 const TargetLowering &TLI) {
1997 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1998 default: llvm_unreachable("Unexpected request for libcall!");
1999 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2000 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2001 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2002 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2003 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2006 return TLI.getLibcallName(LC) != 0;
2009 /// useDivRem - Only issue divrem libcall if both quotient and remainder are
2011 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2012 // The other use might have been replaced with a divrem already.
2013 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2014 unsigned OtherOpcode = 0;
2016 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2018 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2020 SDValue Op0 = Node->getOperand(0);
2021 SDValue Op1 = Node->getOperand(1);
2022 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2023 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2027 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2028 User->getOperand(0) == Op0 &&
2029 User->getOperand(1) == Op1)
2035 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2038 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2039 SmallVectorImpl<SDValue> &Results) {
2040 unsigned Opcode = Node->getOpcode();
2041 bool isSigned = Opcode == ISD::SDIVREM;
2044 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2045 default: llvm_unreachable("Unexpected request for libcall!");
2046 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2047 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2048 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2049 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2050 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2053 // The input chain to this libcall is the entry node of the function.
2054 // Legalizing the call will automatically add the previous call to the
2056 SDValue InChain = DAG.getEntryNode();
2058 EVT RetVT = Node->getValueType(0);
2059 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2061 TargetLowering::ArgListTy Args;
2062 TargetLowering::ArgListEntry Entry;
2063 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2064 EVT ArgVT = Node->getOperand(i).getValueType();
2065 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2066 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2067 Entry.isSExt = isSigned;
2068 Entry.isZExt = !isSigned;
2069 Args.push_back(Entry);
2072 // Also pass the return address of the remainder.
2073 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2075 Entry.Ty = RetTy->getPointerTo();
2076 Entry.isSExt = isSigned;
2077 Entry.isZExt = !isSigned;
2078 Args.push_back(Entry);
2080 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2081 TLI.getPointerTy());
2083 DebugLoc dl = Node->getDebugLoc();
2085 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2086 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2087 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2088 Callee, Args, DAG, dl);
2089 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2091 // Remainder is loaded back from the stack frame.
2092 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2093 MachinePointerInfo(), false, false, false, 0);
2094 Results.push_back(CallInfo.first);
2095 Results.push_back(Rem);
2098 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2099 /// INT_TO_FP operation of the specified operand when the target requests that
2100 /// we expand it. At this point, we know that the result and operand types are
2101 /// legal for the target.
2102 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2106 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2107 // simple 32-bit [signed|unsigned] integer to float/double expansion
2109 // Get the stack frame index of a 8 byte buffer.
2110 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2112 // word offset constant for Hi/Lo address computation
2113 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2114 // set up Hi and Lo (into buffer) address based on endian
2115 SDValue Hi = StackSlot;
2116 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2117 TLI.getPointerTy(), StackSlot, WordOff);
2118 if (TLI.isLittleEndian())
2121 // if signed map to unsigned space
2124 // constant used to invert sign bit (signed to unsigned mapping)
2125 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2126 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2130 // store the lo of the constructed double - based on integer input
2131 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2132 Op0Mapped, Lo, MachinePointerInfo(),
2134 // initial hi portion of constructed double
2135 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2136 // store the hi of the constructed double - biased exponent
2137 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2138 MachinePointerInfo(),
2140 // load the constructed double
2141 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2142 MachinePointerInfo(), false, false, false, 0);
2143 // FP constant to bias correct the final result
2144 SDValue Bias = DAG.getConstantFP(isSigned ?
2145 BitsToDouble(0x4330000080000000ULL) :
2146 BitsToDouble(0x4330000000000000ULL),
2148 // subtract the bias
2149 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2152 // handle final rounding
2153 if (DestVT == MVT::f64) {
2156 } else if (DestVT.bitsLT(MVT::f64)) {
2157 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2158 DAG.getIntPtrConstant(0));
2159 } else if (DestVT.bitsGT(MVT::f64)) {
2160 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2164 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2165 // Code below here assumes !isSigned without checking again.
2167 // Implementation of unsigned i64 to f64 following the algorithm in
2168 // __floatundidf in compiler_rt. This implementation has the advantage
2169 // of performing rounding correctly, both in the default rounding mode
2170 // and in all alternate rounding modes.
2171 // TODO: Generalize this for use with other types.
2172 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2174 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2175 SDValue TwoP84PlusTwoP52 =
2176 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2178 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2180 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2181 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2182 DAG.getConstant(32, MVT::i64));
2183 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2184 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2185 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2186 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2187 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2189 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2192 // Implementation of unsigned i64 to f32.
2193 // TODO: Generalize this for use with other types.
2194 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2195 // For unsigned conversions, convert them to signed conversions using the
2196 // algorithm from the x86_64 __floatundidf in compiler_rt.
2198 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2200 SDValue ShiftConst =
2201 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2202 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2203 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2204 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2205 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2207 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2208 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2210 // TODO: This really should be implemented using a branch rather than a
2211 // select. We happen to get lucky and machinesink does the right
2212 // thing most of the time. This would be a good candidate for a
2213 //pseudo-op, or, even better, for whole-function isel.
2214 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2215 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2216 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast);
2219 // Otherwise, implement the fully general conversion.
2221 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2222 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2223 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2224 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2225 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2226 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2227 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2228 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2229 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2230 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2231 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2233 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2234 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2236 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2237 DAG.getConstant(32, SHVT));
2238 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2239 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2241 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2242 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2243 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2244 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2245 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2246 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2247 DAG.getIntPtrConstant(0));
2250 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2252 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2253 Op0, DAG.getConstant(0, Op0.getValueType()),
2255 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2256 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2257 SignSet, Four, Zero);
2259 // If the sign bit of the integer is set, the large number will be treated
2260 // as a negative number. To counteract this, the dynamic code adds an
2261 // offset depending on the data type.
2263 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2264 default: llvm_unreachable("Unsupported integer type!");
2265 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2266 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2267 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2268 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2270 if (TLI.isLittleEndian()) FF <<= 32;
2271 Constant *FudgeFactor = ConstantInt::get(
2272 Type::getInt64Ty(*DAG.getContext()), FF);
2274 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2275 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2276 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2277 Alignment = std::min(Alignment, 4u);
2279 if (DestVT == MVT::f32)
2280 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2281 MachinePointerInfo::getConstantPool(),
2282 false, false, false, Alignment);
2284 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2285 DAG.getEntryNode(), CPIdx,
2286 MachinePointerInfo::getConstantPool(),
2287 MVT::f32, false, false, Alignment);
2288 HandleSDNode Handle(Load);
2289 LegalizeOp(Load.getNode());
2290 FudgeInReg = Handle.getValue();
2293 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2296 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2297 /// *INT_TO_FP operation of the specified operand when the target requests that
2298 /// we promote it. At this point, we know that the result and operand types are
2299 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2300 /// operation that takes a larger input.
2301 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2305 // First step, figure out the appropriate *INT_TO_FP operation to use.
2306 EVT NewInTy = LegalOp.getValueType();
2308 unsigned OpToUse = 0;
2310 // Scan for the appropriate larger type to use.
2312 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2313 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2315 // If the target supports SINT_TO_FP of this type, use it.
2316 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2317 OpToUse = ISD::SINT_TO_FP;
2320 if (isSigned) continue;
2322 // If the target supports UINT_TO_FP of this type, use it.
2323 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2324 OpToUse = ISD::UINT_TO_FP;
2328 // Otherwise, try a larger type.
2331 // Okay, we found the operation and type to use. Zero extend our input to the
2332 // desired type then run the operation on it.
2333 return DAG.getNode(OpToUse, dl, DestVT,
2334 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2335 dl, NewInTy, LegalOp));
2338 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2339 /// FP_TO_*INT operation of the specified operand when the target requests that
2340 /// we promote it. At this point, we know that the result and operand types are
2341 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2342 /// operation that returns a larger result.
2343 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2347 // First step, figure out the appropriate FP_TO*INT operation to use.
2348 EVT NewOutTy = DestVT;
2350 unsigned OpToUse = 0;
2352 // Scan for the appropriate larger type to use.
2354 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2355 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2357 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2358 OpToUse = ISD::FP_TO_SINT;
2362 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2363 OpToUse = ISD::FP_TO_UINT;
2367 // Otherwise, try a larger type.
2371 // Okay, we found the operation and type to use.
2372 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2374 // Truncate the result of the extended FP_TO_*INT operation to the desired
2376 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2379 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2381 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2382 EVT VT = Op.getValueType();
2383 EVT SHVT = TLI.getShiftAmountTy(VT);
2384 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2385 switch (VT.getSimpleVT().SimpleTy) {
2386 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2388 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2389 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2390 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2392 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2393 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2394 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2395 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2396 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2397 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2398 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2399 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2400 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2402 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2403 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2404 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2405 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2406 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2407 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2408 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2409 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2410 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2411 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2412 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2413 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2414 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2415 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2416 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2417 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2418 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2419 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2420 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2421 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2422 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2426 /// SplatByte - Distribute ByteVal over NumBits bits.
2427 // FIXME: Move this helper to a common place.
2428 static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) {
2429 APInt Val = APInt(NumBits, ByteVal);
2431 for (unsigned i = NumBits; i > 8; i >>= 1) {
2432 Val = (Val << Shift) | Val;
2438 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2440 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2443 default: llvm_unreachable("Cannot expand this yet!");
2445 EVT VT = Op.getValueType();
2446 EVT ShVT = TLI.getShiftAmountTy(VT);
2447 unsigned Len = VT.getSizeInBits();
2449 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2450 "CTPOP not implemented for this type.");
2452 // This is the "best" algorithm from
2453 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2455 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT);
2456 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT);
2457 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT);
2458 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT);
2460 // v = v - ((v >> 1) & 0x55555555...)
2461 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2462 DAG.getNode(ISD::AND, dl, VT,
2463 DAG.getNode(ISD::SRL, dl, VT, Op,
2464 DAG.getConstant(1, ShVT)),
2466 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2467 Op = DAG.getNode(ISD::ADD, dl, VT,
2468 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2469 DAG.getNode(ISD::AND, dl, VT,
2470 DAG.getNode(ISD::SRL, dl, VT, Op,
2471 DAG.getConstant(2, ShVT)),
2473 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2474 Op = DAG.getNode(ISD::AND, dl, VT,
2475 DAG.getNode(ISD::ADD, dl, VT, Op,
2476 DAG.getNode(ISD::SRL, dl, VT, Op,
2477 DAG.getConstant(4, ShVT))),
2479 // v = (v * 0x01010101...) >> (Len - 8)
2480 Op = DAG.getNode(ISD::SRL, dl, VT,
2481 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2482 DAG.getConstant(Len - 8, ShVT));
2486 case ISD::CTLZ_ZERO_UNDEF:
2487 // This trivially expands to CTLZ.
2488 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2490 // for now, we do this:
2491 // x = x | (x >> 1);
2492 // x = x | (x >> 2);
2494 // x = x | (x >>16);
2495 // x = x | (x >>32); // for 64-bit input
2496 // return popcount(~x);
2498 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2499 EVT VT = Op.getValueType();
2500 EVT ShVT = TLI.getShiftAmountTy(VT);
2501 unsigned len = VT.getSizeInBits();
2502 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2503 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2504 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2505 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2507 Op = DAG.getNOT(dl, Op, VT);
2508 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2510 case ISD::CTTZ_ZERO_UNDEF:
2511 // This trivially expands to CTTZ.
2512 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2514 // for now, we use: { return popcount(~x & (x - 1)); }
2515 // unless the target has ctlz but not ctpop, in which case we use:
2516 // { return 32 - nlz(~x & (x-1)); }
2517 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2518 EVT VT = Op.getValueType();
2519 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2520 DAG.getNOT(dl, Op, VT),
2521 DAG.getNode(ISD::SUB, dl, VT, Op,
2522 DAG.getConstant(1, VT)));
2523 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2524 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2525 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2526 return DAG.getNode(ISD::SUB, dl, VT,
2527 DAG.getConstant(VT.getSizeInBits(), VT),
2528 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2529 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2534 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2535 unsigned Opc = Node->getOpcode();
2536 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2541 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2542 case ISD::ATOMIC_SWAP:
2543 switch (VT.SimpleTy) {
2544 default: llvm_unreachable("Unexpected value type for atomic!");
2545 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2546 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2547 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2548 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2551 case ISD::ATOMIC_CMP_SWAP:
2552 switch (VT.SimpleTy) {
2553 default: llvm_unreachable("Unexpected value type for atomic!");
2554 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2555 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2556 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2557 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2560 case ISD::ATOMIC_LOAD_ADD:
2561 switch (VT.SimpleTy) {
2562 default: llvm_unreachable("Unexpected value type for atomic!");
2563 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2564 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2565 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2566 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2569 case ISD::ATOMIC_LOAD_SUB:
2570 switch (VT.SimpleTy) {
2571 default: llvm_unreachable("Unexpected value type for atomic!");
2572 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2573 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2574 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2575 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2578 case ISD::ATOMIC_LOAD_AND:
2579 switch (VT.SimpleTy) {
2580 default: llvm_unreachable("Unexpected value type for atomic!");
2581 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2582 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2583 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2584 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2587 case ISD::ATOMIC_LOAD_OR:
2588 switch (VT.SimpleTy) {
2589 default: llvm_unreachable("Unexpected value type for atomic!");
2590 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2591 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2592 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2593 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2596 case ISD::ATOMIC_LOAD_XOR:
2597 switch (VT.SimpleTy) {
2598 default: llvm_unreachable("Unexpected value type for atomic!");
2599 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2600 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2601 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2602 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2605 case ISD::ATOMIC_LOAD_NAND:
2606 switch (VT.SimpleTy) {
2607 default: llvm_unreachable("Unexpected value type for atomic!");
2608 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2609 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2610 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2611 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2616 return ExpandChainLibCall(LC, Node, false);
2619 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2620 SmallVector<SDValue, 8> Results;
2621 DebugLoc dl = Node->getDebugLoc();
2622 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2623 switch (Node->getOpcode()) {
2626 case ISD::CTLZ_ZERO_UNDEF:
2628 case ISD::CTTZ_ZERO_UNDEF:
2629 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2630 Results.push_back(Tmp1);
2633 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2635 case ISD::FRAMEADDR:
2636 case ISD::RETURNADDR:
2637 case ISD::FRAME_TO_ARGS_OFFSET:
2638 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2640 case ISD::FLT_ROUNDS_:
2641 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2643 case ISD::EH_RETURN:
2647 case ISD::EH_SJLJ_LONGJMP:
2648 // If the target didn't expand these, there's nothing to do, so just
2649 // preserve the chain and be done.
2650 Results.push_back(Node->getOperand(0));
2652 case ISD::EH_SJLJ_SETJMP:
2653 // If the target didn't expand this, just return 'zero' and preserve the
2655 Results.push_back(DAG.getConstant(0, MVT::i32));
2656 Results.push_back(Node->getOperand(0));
2658 case ISD::ATOMIC_FENCE:
2659 case ISD::MEMBARRIER: {
2660 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2661 // FIXME: handle "fence singlethread" more efficiently.
2662 TargetLowering::ArgListTy Args;
2664 CallLoweringInfo CLI(Node->getOperand(0),
2665 Type::getVoidTy(*DAG.getContext()),
2666 false, false, false, false, 0, CallingConv::C,
2667 /*isTailCall=*/false,
2668 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2669 DAG.getExternalSymbol("__sync_synchronize",
2670 TLI.getPointerTy()),
2672 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2674 Results.push_back(CallResult.second);
2677 case ISD::ATOMIC_LOAD: {
2678 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2679 SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
2680 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
2681 cast<AtomicSDNode>(Node)->getMemoryVT(),
2682 Node->getOperand(0),
2683 Node->getOperand(1), Zero, Zero,
2684 cast<AtomicSDNode>(Node)->getMemOperand(),
2685 cast<AtomicSDNode>(Node)->getOrdering(),
2686 cast<AtomicSDNode>(Node)->getSynchScope());
2687 Results.push_back(Swap.getValue(0));
2688 Results.push_back(Swap.getValue(1));
2691 case ISD::ATOMIC_STORE: {
2692 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2693 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2694 cast<AtomicSDNode>(Node)->getMemoryVT(),
2695 Node->getOperand(0),
2696 Node->getOperand(1), Node->getOperand(2),
2697 cast<AtomicSDNode>(Node)->getMemOperand(),
2698 cast<AtomicSDNode>(Node)->getOrdering(),
2699 cast<AtomicSDNode>(Node)->getSynchScope());
2700 Results.push_back(Swap.getValue(1));
2703 // By default, atomic intrinsics are marked Legal and lowered. Targets
2704 // which don't support them directly, however, may want libcalls, in which
2705 // case they mark them Expand, and we get here.
2706 case ISD::ATOMIC_SWAP:
2707 case ISD::ATOMIC_LOAD_ADD:
2708 case ISD::ATOMIC_LOAD_SUB:
2709 case ISD::ATOMIC_LOAD_AND:
2710 case ISD::ATOMIC_LOAD_OR:
2711 case ISD::ATOMIC_LOAD_XOR:
2712 case ISD::ATOMIC_LOAD_NAND:
2713 case ISD::ATOMIC_LOAD_MIN:
2714 case ISD::ATOMIC_LOAD_MAX:
2715 case ISD::ATOMIC_LOAD_UMIN:
2716 case ISD::ATOMIC_LOAD_UMAX:
2717 case ISD::ATOMIC_CMP_SWAP: {
2718 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2719 Results.push_back(Tmp.first);
2720 Results.push_back(Tmp.second);
2723 case ISD::DYNAMIC_STACKALLOC:
2724 ExpandDYNAMIC_STACKALLOC(Node, Results);
2726 case ISD::MERGE_VALUES:
2727 for (unsigned i = 0; i < Node->getNumValues(); i++)
2728 Results.push_back(Node->getOperand(i));
2731 EVT VT = Node->getValueType(0);
2733 Results.push_back(DAG.getConstant(0, VT));
2735 assert(VT.isFloatingPoint() && "Unknown value type!");
2736 Results.push_back(DAG.getConstantFP(0, VT));
2741 // If this operation is not supported, lower it to 'abort()' call
2742 TargetLowering::ArgListTy Args;
2744 CallLoweringInfo CLI(Node->getOperand(0),
2745 Type::getVoidTy(*DAG.getContext()),
2746 false, false, false, false, 0, CallingConv::C,
2747 /*isTailCall=*/false,
2748 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2749 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2751 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2753 Results.push_back(CallResult.second);
2758 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2759 Node->getValueType(0), dl);
2760 Results.push_back(Tmp1);
2762 case ISD::FP_EXTEND:
2763 Tmp1 = EmitStackConvert(Node->getOperand(0),
2764 Node->getOperand(0).getValueType(),
2765 Node->getValueType(0), dl);
2766 Results.push_back(Tmp1);
2768 case ISD::SIGN_EXTEND_INREG: {
2769 // NOTE: we could fall back on load/store here too for targets without
2770 // SAR. However, it is doubtful that any exist.
2771 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2772 EVT VT = Node->getValueType(0);
2773 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
2776 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2777 ExtraVT.getScalarType().getSizeInBits();
2778 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2779 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2780 Node->getOperand(0), ShiftCst);
2781 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2782 Results.push_back(Tmp1);
2785 case ISD::FP_ROUND_INREG: {
2786 // The only way we can lower this is to turn it into a TRUNCSTORE,
2787 // EXTLOAD pair, targeting a temporary location (a stack slot).
2789 // NOTE: there is a choice here between constantly creating new stack
2790 // slots and always reusing the same one. We currently always create
2791 // new ones, as reuse may inhibit scheduling.
2792 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2793 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2794 Node->getValueType(0), dl);
2795 Results.push_back(Tmp1);
2798 case ISD::SINT_TO_FP:
2799 case ISD::UINT_TO_FP:
2800 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2801 Node->getOperand(0), Node->getValueType(0), dl);
2802 Results.push_back(Tmp1);
2804 case ISD::FP_TO_UINT: {
2805 SDValue True, False;
2806 EVT VT = Node->getOperand(0).getValueType();
2807 EVT NVT = Node->getValueType(0);
2808 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
2809 APInt::getNullValue(VT.getSizeInBits()));
2810 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2811 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2812 Tmp1 = DAG.getConstantFP(apf, VT);
2813 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2814 Node->getOperand(0),
2816 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2817 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2818 DAG.getNode(ISD::FSUB, dl, VT,
2819 Node->getOperand(0), Tmp1));
2820 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2821 DAG.getConstant(x, NVT));
2822 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2823 Results.push_back(Tmp1);
2827 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2828 EVT VT = Node->getValueType(0);
2829 Tmp1 = Node->getOperand(0);
2830 Tmp2 = Node->getOperand(1);
2831 unsigned Align = Node->getConstantOperandVal(3);
2833 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
2834 MachinePointerInfo(V),
2835 false, false, false, 0);
2836 SDValue VAList = VAListLoad;
2838 if (Align > TLI.getMinStackArgumentAlignment()) {
2839 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2841 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2842 DAG.getConstant(Align - 1,
2843 TLI.getPointerTy()));
2845 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
2846 DAG.getConstant(-(int64_t)Align,
2847 TLI.getPointerTy()));
2850 // Increment the pointer, VAList, to the next vaarg
2851 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2852 DAG.getConstant(TLI.getDataLayout()->
2853 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2854 TLI.getPointerTy()));
2855 // Store the incremented VAList to the legalized pointer
2856 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
2857 MachinePointerInfo(V), false, false, 0);
2858 // Load the actual argument out of the pointer VAList
2859 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
2860 false, false, false, 0));
2861 Results.push_back(Results[0].getValue(1));
2865 // This defaults to loading a pointer from the input and storing it to the
2866 // output, returning the chain.
2867 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2868 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2869 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2870 Node->getOperand(2), MachinePointerInfo(VS),
2871 false, false, false, 0);
2872 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
2873 MachinePointerInfo(VD), false, false, 0);
2874 Results.push_back(Tmp1);
2877 case ISD::EXTRACT_VECTOR_ELT:
2878 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2879 // This must be an access of the only element. Return it.
2880 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
2881 Node->getOperand(0));
2883 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2884 Results.push_back(Tmp1);
2886 case ISD::EXTRACT_SUBVECTOR:
2887 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2889 case ISD::INSERT_SUBVECTOR:
2890 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
2892 case ISD::CONCAT_VECTORS: {
2893 Results.push_back(ExpandVectorBuildThroughStack(Node));
2896 case ISD::SCALAR_TO_VECTOR:
2897 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2899 case ISD::INSERT_VECTOR_ELT:
2900 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2901 Node->getOperand(1),
2902 Node->getOperand(2), dl));
2904 case ISD::VECTOR_SHUFFLE: {
2905 SmallVector<int, 32> NewMask;
2906 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
2908 EVT VT = Node->getValueType(0);
2909 EVT EltVT = VT.getVectorElementType();
2910 SDValue Op0 = Node->getOperand(0);
2911 SDValue Op1 = Node->getOperand(1);
2912 if (!TLI.isTypeLegal(EltVT)) {
2914 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
2916 // BUILD_VECTOR operands are allowed to be wider than the element type.
2917 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept it
2918 if (NewEltVT.bitsLT(EltVT)) {
2920 // Convert shuffle node.
2921 // If original node was v4i64 and the new EltVT is i32,
2922 // cast operands to v8i32 and re-build the mask.
2924 // Calculate new VT, the size of the new VT should be equal to original.
2925 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT,
2926 VT.getSizeInBits()/NewEltVT.getSizeInBits());
2927 assert(NewVT.bitsEq(VT));
2929 // cast operands to new VT
2930 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
2931 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
2933 // Convert the shuffle mask
2934 unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements();
2936 // EltVT gets smaller
2939 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
2941 for (unsigned fi = 0; fi < factor; ++fi)
2942 NewMask.push_back(Mask[i]);
2945 for (unsigned fi = 0; fi < factor; ++fi)
2946 NewMask.push_back(Mask[i]*factor+fi);
2954 unsigned NumElems = VT.getVectorNumElements();
2955 SmallVector<SDValue, 16> Ops;
2956 for (unsigned i = 0; i != NumElems; ++i) {
2958 Ops.push_back(DAG.getUNDEF(EltVT));
2961 unsigned Idx = Mask[i];
2963 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2965 DAG.getIntPtrConstant(Idx)));
2967 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2969 DAG.getIntPtrConstant(Idx - NumElems)));
2972 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2973 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
2974 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
2975 Results.push_back(Tmp1);
2978 case ISD::EXTRACT_ELEMENT: {
2979 EVT OpTy = Node->getOperand(0).getValueType();
2980 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2982 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2983 DAG.getConstant(OpTy.getSizeInBits()/2,
2984 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
2985 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2988 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2989 Node->getOperand(0));
2991 Results.push_back(Tmp1);
2994 case ISD::STACKSAVE:
2995 // Expand to CopyFromReg if the target set
2996 // StackPointerRegisterToSaveRestore.
2997 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2998 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2999 Node->getValueType(0)));
3000 Results.push_back(Results[0].getValue(1));
3002 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3003 Results.push_back(Node->getOperand(0));
3006 case ISD::STACKRESTORE:
3007 // Expand to CopyToReg if the target set
3008 // StackPointerRegisterToSaveRestore.
3009 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3010 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3011 Node->getOperand(1)));
3013 Results.push_back(Node->getOperand(0));
3016 case ISD::FCOPYSIGN:
3017 Results.push_back(ExpandFCOPYSIGN(Node));
3020 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3021 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3022 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3023 Node->getOperand(0));
3024 Results.push_back(Tmp1);
3027 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3028 EVT VT = Node->getValueType(0);
3029 Tmp1 = Node->getOperand(0);
3030 Tmp2 = DAG.getConstantFP(0.0, VT);
3031 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3032 Tmp1, Tmp2, ISD::SETUGT);
3033 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3034 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3035 Results.push_back(Tmp1);
3039 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3040 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3041 RTLIB::SQRT_PPCF128));
3044 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3045 RTLIB::SIN_F80, RTLIB::SIN_F128,
3046 RTLIB::SIN_PPCF128));
3049 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3050 RTLIB::COS_F80, RTLIB::COS_F128,
3051 RTLIB::COS_PPCF128));
3054 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3055 RTLIB::LOG_F80, RTLIB::LOG_F128,
3056 RTLIB::LOG_PPCF128));
3059 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3060 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3061 RTLIB::LOG2_PPCF128));
3064 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3065 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3066 RTLIB::LOG10_PPCF128));
3069 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3070 RTLIB::EXP_F80, RTLIB::EXP_F128,
3071 RTLIB::EXP_PPCF128));
3074 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3075 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3076 RTLIB::EXP2_PPCF128));
3079 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3080 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3081 RTLIB::TRUNC_PPCF128));
3084 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3085 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3086 RTLIB::FLOOR_PPCF128));
3089 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3090 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3091 RTLIB::CEIL_PPCF128));
3094 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3095 RTLIB::RINT_F80, RTLIB::RINT_F128,
3096 RTLIB::RINT_PPCF128));
3098 case ISD::FNEARBYINT:
3099 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3100 RTLIB::NEARBYINT_F64,
3101 RTLIB::NEARBYINT_F80,
3102 RTLIB::NEARBYINT_F128,
3103 RTLIB::NEARBYINT_PPCF128));
3106 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3107 RTLIB::POWI_F80, RTLIB::POWI_F128,
3108 RTLIB::POWI_PPCF128));
3111 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3112 RTLIB::POW_F80, RTLIB::POW_F128,
3113 RTLIB::POW_PPCF128));
3116 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3117 RTLIB::DIV_F80, RTLIB::DIV_F128,
3118 RTLIB::DIV_PPCF128));
3121 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3122 RTLIB::REM_F80, RTLIB::REM_F128,
3123 RTLIB::REM_PPCF128));
3126 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3127 RTLIB::FMA_F80, RTLIB::FMA_F128,
3128 RTLIB::FMA_PPCF128));
3130 case ISD::FP16_TO_FP32:
3131 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3133 case ISD::FP32_TO_FP16:
3134 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3136 case ISD::ConstantFP: {
3137 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3138 // Check to see if this FP immediate is already legal.
3139 // If this is a legal constant, turn it into a TargetConstantFP node.
3140 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3141 Results.push_back(ExpandConstantFP(CFP, true));
3144 case ISD::EHSELECTION: {
3145 unsigned Reg = TLI.getExceptionSelectorRegister();
3146 assert(Reg && "Can't expand to unknown register!");
3147 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
3148 Node->getValueType(0)));
3149 Results.push_back(Results[0].getValue(1));
3152 case ISD::EXCEPTIONADDR: {
3153 unsigned Reg = TLI.getExceptionPointerRegister();
3154 assert(Reg && "Can't expand to unknown register!");
3155 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
3156 Node->getValueType(0)));
3157 Results.push_back(Results[0].getValue(1));
3161 EVT VT = Node->getValueType(0);
3162 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3163 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3164 "Don't know how to expand this FP subtraction!");
3165 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3166 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3167 Results.push_back(Tmp1);
3171 EVT VT = Node->getValueType(0);
3172 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3173 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3174 "Don't know how to expand this subtraction!");
3175 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3176 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3177 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3178 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3183 EVT VT = Node->getValueType(0);
3184 SDVTList VTs = DAG.getVTList(VT, VT);
3185 bool isSigned = Node->getOpcode() == ISD::SREM;
3186 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3187 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3188 Tmp2 = Node->getOperand(0);
3189 Tmp3 = Node->getOperand(1);
3190 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3191 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3192 // If div is legal, it's better to do the normal expansion
3193 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
3194 useDivRem(Node, isSigned, false))) {
3195 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3196 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3198 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3199 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3200 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3201 } else if (isSigned)
3202 Tmp1 = ExpandIntLibCall(Node, true,
3204 RTLIB::SREM_I16, RTLIB::SREM_I32,
3205 RTLIB::SREM_I64, RTLIB::SREM_I128);
3207 Tmp1 = ExpandIntLibCall(Node, false,
3209 RTLIB::UREM_I16, RTLIB::UREM_I32,
3210 RTLIB::UREM_I64, RTLIB::UREM_I128);
3211 Results.push_back(Tmp1);
3216 bool isSigned = Node->getOpcode() == ISD::SDIV;
3217 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3218 EVT VT = Node->getValueType(0);
3219 SDVTList VTs = DAG.getVTList(VT, VT);
3220 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3221 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3222 useDivRem(Node, isSigned, true)))
3223 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3224 Node->getOperand(1));
3226 Tmp1 = ExpandIntLibCall(Node, true,
3228 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3229 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3231 Tmp1 = ExpandIntLibCall(Node, false,
3233 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3234 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3235 Results.push_back(Tmp1);
3240 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3242 EVT VT = Node->getValueType(0);
3243 SDVTList VTs = DAG.getVTList(VT, VT);
3244 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3245 "If this wasn't legal, it shouldn't have been created!");
3246 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3247 Node->getOperand(1));
3248 Results.push_back(Tmp1.getValue(1));
3253 // Expand into divrem libcall
3254 ExpandDivRemLibCall(Node, Results);
3257 EVT VT = Node->getValueType(0);
3258 SDVTList VTs = DAG.getVTList(VT, VT);
3259 // See if multiply or divide can be lowered using two-result operations.
3260 // We just need the low half of the multiply; try both the signed
3261 // and unsigned forms. If the target supports both SMUL_LOHI and
3262 // UMUL_LOHI, form a preference by checking which forms of plain
3263 // MULH it supports.
3264 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3265 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3266 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3267 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3268 unsigned OpToUse = 0;
3269 if (HasSMUL_LOHI && !HasMULHS) {
3270 OpToUse = ISD::SMUL_LOHI;
3271 } else if (HasUMUL_LOHI && !HasMULHU) {
3272 OpToUse = ISD::UMUL_LOHI;
3273 } else if (HasSMUL_LOHI) {
3274 OpToUse = ISD::SMUL_LOHI;
3275 } else if (HasUMUL_LOHI) {
3276 OpToUse = ISD::UMUL_LOHI;
3279 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3280 Node->getOperand(1)));
3283 Tmp1 = ExpandIntLibCall(Node, false,
3285 RTLIB::MUL_I16, RTLIB::MUL_I32,
3286 RTLIB::MUL_I64, RTLIB::MUL_I128);
3287 Results.push_back(Tmp1);
3292 SDValue LHS = Node->getOperand(0);
3293 SDValue RHS = Node->getOperand(1);
3294 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3295 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3297 Results.push_back(Sum);
3298 EVT OType = Node->getValueType(1);
3300 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3302 // LHSSign -> LHS >= 0
3303 // RHSSign -> RHS >= 0
3304 // SumSign -> Sum >= 0
3307 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3309 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3311 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3312 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3313 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3314 Node->getOpcode() == ISD::SADDO ?
3315 ISD::SETEQ : ISD::SETNE);
3317 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3318 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3320 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3321 Results.push_back(Cmp);
3326 SDValue LHS = Node->getOperand(0);
3327 SDValue RHS = Node->getOperand(1);
3328 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3329 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3331 Results.push_back(Sum);
3332 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3333 Node->getOpcode () == ISD::UADDO ?
3334 ISD::SETULT : ISD::SETUGT));
3339 EVT VT = Node->getValueType(0);
3340 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3341 SDValue LHS = Node->getOperand(0);
3342 SDValue RHS = Node->getOperand(1);
3345 static const unsigned Ops[2][3] =
3346 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3347 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3348 bool isSigned = Node->getOpcode() == ISD::SMULO;
3349 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3350 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3351 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3352 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3353 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3355 TopHalf = BottomHalf.getValue(1);
3356 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3357 VT.getSizeInBits() * 2))) {
3358 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3359 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3360 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3361 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3362 DAG.getIntPtrConstant(0));
3363 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3364 DAG.getIntPtrConstant(1));
3366 // We can fall back to a libcall with an illegal type for the MUL if we
3367 // have a libcall big enough.
3368 // Also, we can fall back to a division in some cases, but that's a big
3369 // performance hit in the general case.
3370 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3371 if (WideVT == MVT::i16)
3372 LC = RTLIB::MUL_I16;
3373 else if (WideVT == MVT::i32)
3374 LC = RTLIB::MUL_I32;
3375 else if (WideVT == MVT::i64)
3376 LC = RTLIB::MUL_I64;
3377 else if (WideVT == MVT::i128)
3378 LC = RTLIB::MUL_I128;
3379 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3381 // The high part is obtained by SRA'ing all but one of the bits of low
3383 unsigned LoSize = VT.getSizeInBits();
3384 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3385 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3386 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3387 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3389 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3390 // pre-lowered to the correct types. This all depends upon WideVT not
3391 // being a legal type for the architecture and thus has to be split to
3393 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3394 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3395 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3396 DAG.getIntPtrConstant(0));
3397 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3398 DAG.getIntPtrConstant(1));
3399 // Ret is a node with an illegal type. Because such things are not
3400 // generally permitted during this phase of legalization, delete the
3401 // node. The above EXTRACT_ELEMENT nodes should have been folded.
3402 DAG.DeleteNode(Ret.getNode());
3406 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3407 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3408 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3409 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3412 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3413 DAG.getConstant(0, VT), ISD::SETNE);
3415 Results.push_back(BottomHalf);
3416 Results.push_back(TopHalf);
3419 case ISD::BUILD_PAIR: {
3420 EVT PairTy = Node->getValueType(0);
3421 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3422 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3423 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3424 DAG.getConstant(PairTy.getSizeInBits()/2,
3425 TLI.getShiftAmountTy(PairTy)));
3426 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3430 Tmp1 = Node->getOperand(0);
3431 Tmp2 = Node->getOperand(1);
3432 Tmp3 = Node->getOperand(2);
3433 if (Tmp1.getOpcode() == ISD::SETCC) {
3434 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3436 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3438 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3439 DAG.getConstant(0, Tmp1.getValueType()),
3440 Tmp2, Tmp3, ISD::SETNE);
3442 Results.push_back(Tmp1);
3445 SDValue Chain = Node->getOperand(0);
3446 SDValue Table = Node->getOperand(1);
3447 SDValue Index = Node->getOperand(2);
3449 EVT PTy = TLI.getPointerTy();
3451 const DataLayout &TD = *TLI.getDataLayout();
3452 unsigned EntrySize =
3453 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3455 Index = DAG.getNode(ISD::MUL, dl, PTy,
3456 Index, DAG.getConstant(EntrySize, PTy));
3457 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3459 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3460 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3461 MachinePointerInfo::getJumpTable(), MemVT,
3464 if (TM.getRelocationModel() == Reloc::PIC_) {
3465 // For PIC, the sequence is:
3466 // BRIND(load(Jumptable + index) + RelocBase)
3467 // RelocBase can be JumpTable, GOT or some sort of global base.
3468 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3469 TLI.getPICJumpTableRelocBase(Table, DAG));
3471 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3472 Results.push_back(Tmp1);
3476 // Expand brcond's setcc into its constituent parts and create a BR_CC
3478 Tmp1 = Node->getOperand(0);
3479 Tmp2 = Node->getOperand(1);
3480 if (Tmp2.getOpcode() == ISD::SETCC) {
3481 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3482 Tmp1, Tmp2.getOperand(2),
3483 Tmp2.getOperand(0), Tmp2.getOperand(1),
3484 Node->getOperand(2));
3486 // We test only the i1 bit. Skip the AND if UNDEF.
3487 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3488 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3489 DAG.getConstant(1, Tmp2.getValueType()));
3490 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3491 DAG.getCondCode(ISD::SETNE), Tmp3,
3492 DAG.getConstant(0, Tmp3.getValueType()),
3493 Node->getOperand(2));
3495 Results.push_back(Tmp1);
3498 Tmp1 = Node->getOperand(0);
3499 Tmp2 = Node->getOperand(1);
3500 Tmp3 = Node->getOperand(2);
3501 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3503 // If we expanded the SETCC into an AND/OR, return the new node
3504 if (Tmp2.getNode() == 0) {
3505 Results.push_back(Tmp1);
3509 // Otherwise, SETCC for the given comparison type must be completely
3510 // illegal; expand it into a SELECT_CC.
3511 EVT VT = Node->getValueType(0);
3512 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3513 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3514 Results.push_back(Tmp1);
3517 case ISD::SELECT_CC: {
3518 Tmp1 = Node->getOperand(0); // LHS
3519 Tmp2 = Node->getOperand(1); // RHS
3520 Tmp3 = Node->getOperand(2); // True
3521 Tmp4 = Node->getOperand(3); // False
3522 SDValue CC = Node->getOperand(4);
3524 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3525 Tmp1, Tmp2, CC, dl);
3527 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3528 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3529 CC = DAG.getCondCode(ISD::SETNE);
3530 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3532 Results.push_back(Tmp1);
3536 Tmp1 = Node->getOperand(0); // Chain
3537 Tmp2 = Node->getOperand(2); // LHS
3538 Tmp3 = Node->getOperand(3); // RHS
3539 Tmp4 = Node->getOperand(1); // CC
3541 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3542 Tmp2, Tmp3, Tmp4, dl);
3544 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3545 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3546 Tmp4 = DAG.getCondCode(ISD::SETNE);
3547 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3548 Tmp3, Node->getOperand(4));
3549 Results.push_back(Tmp1);
3552 case ISD::BUILD_VECTOR:
3553 Results.push_back(ExpandBUILD_VECTOR(Node));
3558 // Scalarize vector SRA/SRL/SHL.
3559 EVT VT = Node->getValueType(0);
3560 assert(VT.isVector() && "Unable to legalize non-vector shift");
3561 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3562 unsigned NumElem = VT.getVectorNumElements();
3564 SmallVector<SDValue, 8> Scalars;
3565 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3566 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3568 Node->getOperand(0), DAG.getIntPtrConstant(Idx));
3569 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3571 Node->getOperand(1), DAG.getIntPtrConstant(Idx));
3572 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3573 VT.getScalarType(), Ex, Sh));
3576 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
3577 &Scalars[0], Scalars.size());
3578 ReplaceNode(SDValue(Node, 0), Result);
3581 case ISD::GLOBAL_OFFSET_TABLE:
3582 case ISD::GlobalAddress:
3583 case ISD::GlobalTLSAddress:
3584 case ISD::ExternalSymbol:
3585 case ISD::ConstantPool:
3586 case ISD::JumpTable:
3587 case ISD::INTRINSIC_W_CHAIN:
3588 case ISD::INTRINSIC_WO_CHAIN:
3589 case ISD::INTRINSIC_VOID:
3590 // FIXME: Custom lowering for these operations shouldn't return null!
3594 // Replace the original node with the legalized result.
3595 if (!Results.empty())
3596 ReplaceNode(Node, Results.data());
3599 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
3600 SmallVector<SDValue, 8> Results;
3601 MVT OVT = Node->getSimpleValueType(0);
3602 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3603 Node->getOpcode() == ISD::SINT_TO_FP ||
3604 Node->getOpcode() == ISD::SETCC) {
3605 OVT = Node->getOperand(0).getSimpleValueType();
3607 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3608 DebugLoc dl = Node->getDebugLoc();
3609 SDValue Tmp1, Tmp2, Tmp3;
3610 switch (Node->getOpcode()) {
3612 case ISD::CTTZ_ZERO_UNDEF:
3614 case ISD::CTLZ_ZERO_UNDEF:
3616 // Zero extend the argument.
3617 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3618 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
3619 // already the correct result.
3620 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3621 if (Node->getOpcode() == ISD::CTTZ) {
3622 // FIXME: This should set a bit in the zero extended value instead.
3623 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3624 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3626 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3627 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3628 } else if (Node->getOpcode() == ISD::CTLZ ||
3629 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
3630 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3631 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3632 DAG.getConstant(NVT.getSizeInBits() -
3633 OVT.getSizeInBits(), NVT));
3635 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3638 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3639 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3640 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3641 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3642 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3643 Results.push_back(Tmp1);
3646 case ISD::FP_TO_UINT:
3647 case ISD::FP_TO_SINT:
3648 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3649 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3650 Results.push_back(Tmp1);
3652 case ISD::UINT_TO_FP:
3653 case ISD::SINT_TO_FP:
3654 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3655 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3656 Results.push_back(Tmp1);
3659 SDValue Chain = Node->getOperand(0); // Get the chain.
3660 SDValue Ptr = Node->getOperand(1); // Get the pointer.
3663 if (OVT.isVector()) {
3664 TruncOp = ISD::BITCAST;
3666 assert(OVT.isInteger()
3667 && "VAARG promotion is supported only for vectors or integer types");
3668 TruncOp = ISD::TRUNCATE;
3671 // Perform the larger operation, then convert back
3672 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
3673 Node->getConstantOperandVal(3));
3674 Chain = Tmp1.getValue(1);
3676 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
3678 // Modified the chain result - switch anything that used the old chain to
3680 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
3681 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
3688 unsigned ExtOp, TruncOp;
3689 if (OVT.isVector()) {
3690 ExtOp = ISD::BITCAST;
3691 TruncOp = ISD::BITCAST;
3693 assert(OVT.isInteger() && "Cannot promote logic operation");
3694 ExtOp = ISD::ANY_EXTEND;
3695 TruncOp = ISD::TRUNCATE;
3697 // Promote each of the values to the new type.
3698 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3699 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3700 // Perform the larger operation, then convert back
3701 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3702 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3706 unsigned ExtOp, TruncOp;
3707 if (Node->getValueType(0).isVector()) {
3708 ExtOp = ISD::BITCAST;
3709 TruncOp = ISD::BITCAST;
3710 } else if (Node->getValueType(0).isInteger()) {
3711 ExtOp = ISD::ANY_EXTEND;
3712 TruncOp = ISD::TRUNCATE;
3714 ExtOp = ISD::FP_EXTEND;
3715 TruncOp = ISD::FP_ROUND;
3717 Tmp1 = Node->getOperand(0);
3718 // Promote each of the values to the new type.
3719 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3720 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3721 // Perform the larger operation, then round down.
3722 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3723 if (TruncOp != ISD::FP_ROUND)
3724 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3726 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3727 DAG.getIntPtrConstant(0));
3728 Results.push_back(Tmp1);
3731 case ISD::VECTOR_SHUFFLE: {
3732 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3734 // Cast the two input vectors.
3735 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3736 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3738 // Convert the shuffle mask to the right # elements.
3739 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3740 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3741 Results.push_back(Tmp1);
3745 unsigned ExtOp = ISD::FP_EXTEND;
3746 if (NVT.isInteger()) {
3747 ISD::CondCode CCCode =
3748 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3749 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3751 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3752 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3753 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3754 Tmp1, Tmp2, Node->getOperand(2)));
3760 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
3761 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
3762 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3763 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
3764 Tmp3, DAG.getIntPtrConstant(0)));
3771 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
3772 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3773 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
3774 Tmp2, DAG.getIntPtrConstant(0)));
3779 // Replace the original node with the legalized result.
3780 if (!Results.empty())
3781 ReplaceNode(Node, Results.data());
3784 // SelectionDAG::Legalize - This is the entry point for the file.
3786 void SelectionDAG::Legalize() {
3787 /// run - This is the main entry point to this class.
3789 SelectionDAGLegalize(*this).LegalizeDAG();