1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/DwarfWriter.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetSubtarget.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/DerivedTypes.h"
31 #include "llvm/Function.h"
32 #include "llvm/GlobalVariable.h"
33 #include "llvm/LLVMContext.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Compiler.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/ADT/DenseMap.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/ADT/SmallPtrSet.h"
44 //===----------------------------------------------------------------------===//
45 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
46 /// hacks on it until the target machine can handle it. This involves
47 /// eliminating value sizes the machine cannot handle (promoting small sizes to
48 /// large sizes or splitting up large values into small values) as well as
49 /// eliminating operations the machine cannot handle.
51 /// This code also does a small amount of optimization and recognition of idioms
52 /// as part of its processing. For example, if a target does not support a
53 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
54 /// will attempt merge setcc and brc instructions into brcc's.
57 class VISIBILITY_HIDDEN SelectionDAGLegalize {
60 CodeGenOpt::Level OptLevel;
62 // Libcall insertion helpers.
64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
65 /// legalized. We use this to ensure that calls are properly serialized
66 /// against each other, including inserted libcalls.
67 SDValue LastCALLSEQ_END;
69 /// IsLegalizingCall - This member is used *only* for purposes of providing
70 /// helpful assertions that a libcall isn't created while another call is
71 /// being legalized (which could lead to non-serialized call sequences).
72 bool IsLegalizingCall;
75 Legal, // The target natively supports this operation.
76 Promote, // This operation should be executed in a larger type.
77 Expand // Try to expand this to other ops, otherwise use a libcall.
80 /// ValueTypeActions - This is a bitvector that contains two bits for each
81 /// value type, where the two bits correspond to the LegalizeAction enum.
82 /// This can be queried with "getTypeAction(VT)".
83 TargetLowering::ValueTypeActionImpl ValueTypeActions;
85 /// LegalizedNodes - For nodes that are of legal width, and that have more
86 /// than one use, this map indicates what regularized operand to use. This
87 /// allows us to avoid legalizing the same thing more than once.
88 DenseMap<SDValue, SDValue> LegalizedNodes;
90 void AddLegalizedOperand(SDValue From, SDValue To) {
91 LegalizedNodes.insert(std::make_pair(From, To));
92 // If someone requests legalization of the new node, return itself.
94 LegalizedNodes.insert(std::make_pair(To, To));
98 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol);
100 /// getTypeAction - Return how we should legalize values of this type, either
101 /// it is already legal or we need to expand it into multiple registers of
102 /// smaller integer type, or we need to promote it to a larger type.
103 LegalizeAction getTypeAction(EVT VT) const {
105 (LegalizeAction)ValueTypeActions.getTypeAction(*DAG.getContext(), VT);
108 /// isTypeLegal - Return true if this type is legal on this target.
110 bool isTypeLegal(EVT VT) const {
111 return getTypeAction(VT) == Legal;
117 /// LegalizeOp - We know that the specified value has a legal type.
118 /// Recursively ensure that the operands have legal types, then return the
120 SDValue LegalizeOp(SDValue O);
122 SDValue OptimizeFloatStore(StoreSDNode *ST);
124 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
125 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
126 /// is necessary to spill the vector being inserted into to memory, perform
127 /// the insert there, and then read the result back.
128 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
129 SDValue Idx, DebugLoc dl);
130 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
131 SDValue Idx, DebugLoc dl);
133 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
134 /// performs the same shuffe in terms of order or result bytes, but on a type
135 /// whose vector element type is narrower than the original shuffle type.
136 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
137 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
138 SDValue N1, SDValue N2,
139 SmallVectorImpl<int> &Mask) const;
141 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
142 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
144 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
147 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
148 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
149 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
150 RTLIB::Libcall Call_PPCF128);
151 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, RTLIB::Libcall Call_I16,
152 RTLIB::Libcall Call_I32, RTLIB::Libcall Call_I64,
153 RTLIB::Libcall Call_I128);
155 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
156 SDValue ExpandBUILD_VECTOR(SDNode *Node);
157 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
158 SDValue ExpandDBG_STOPPOINT(SDNode *Node);
159 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
160 SmallVectorImpl<SDValue> &Results);
161 SDValue ExpandFCOPYSIGN(SDNode *Node);
162 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
164 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
166 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
169 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
170 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
172 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
173 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
175 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
176 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
180 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
181 /// performs the same shuffe in terms of order or result bytes, but on a type
182 /// whose vector element type is narrower than the original shuffle type.
183 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
185 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
186 SDValue N1, SDValue N2,
187 SmallVectorImpl<int> &Mask) const {
188 EVT EltVT = NVT.getVectorElementType();
189 unsigned NumMaskElts = VT.getVectorNumElements();
190 unsigned NumDestElts = NVT.getVectorNumElements();
191 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
193 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
195 if (NumEltsGrowth == 1)
196 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
198 SmallVector<int, 8> NewMask;
199 for (unsigned i = 0; i != NumMaskElts; ++i) {
201 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
203 NewMask.push_back(-1);
205 NewMask.push_back(Idx * NumEltsGrowth + j);
208 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
209 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
210 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
213 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
214 CodeGenOpt::Level ol)
215 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
216 ValueTypeActions(TLI.getValueTypeActions()) {
217 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
218 "Too many value types for ValueTypeActions to hold!");
221 void SelectionDAGLegalize::LegalizeDAG() {
222 LastCALLSEQ_END = DAG.getEntryNode();
223 IsLegalizingCall = false;
225 // The legalize process is inherently a bottom-up recursive process (users
226 // legalize their uses before themselves). Given infinite stack space, we
227 // could just start legalizing on the root and traverse the whole graph. In
228 // practice however, this causes us to run out of stack space on large basic
229 // blocks. To avoid this problem, compute an ordering of the nodes where each
230 // node is only legalized after all of its operands are legalized.
231 DAG.AssignTopologicalOrder();
232 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
233 E = prior(DAG.allnodes_end()); I != next(E); ++I)
234 LegalizeOp(SDValue(I, 0));
236 // Finally, it's possible the root changed. Get the new root.
237 SDValue OldRoot = DAG.getRoot();
238 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
239 DAG.setRoot(LegalizedNodes[OldRoot]);
241 LegalizedNodes.clear();
243 // Remove dead nodes now.
244 DAG.RemoveDeadNodes();
248 /// FindCallEndFromCallStart - Given a chained node that is part of a call
249 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
250 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
251 if (Node->getOpcode() == ISD::CALLSEQ_END)
253 if (Node->use_empty())
254 return 0; // No CallSeqEnd
256 // The chain is usually at the end.
257 SDValue TheChain(Node, Node->getNumValues()-1);
258 if (TheChain.getValueType() != MVT::Other) {
259 // Sometimes it's at the beginning.
260 TheChain = SDValue(Node, 0);
261 if (TheChain.getValueType() != MVT::Other) {
262 // Otherwise, hunt for it.
263 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
264 if (Node->getValueType(i) == MVT::Other) {
265 TheChain = SDValue(Node, i);
269 // Otherwise, we walked into a node without a chain.
270 if (TheChain.getValueType() != MVT::Other)
275 for (SDNode::use_iterator UI = Node->use_begin(),
276 E = Node->use_end(); UI != E; ++UI) {
278 // Make sure to only follow users of our token chain.
280 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
281 if (User->getOperand(i) == TheChain)
282 if (SDNode *Result = FindCallEndFromCallStart(User))
288 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
289 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
290 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
291 assert(Node && "Didn't find callseq_start for a call??");
292 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
294 assert(Node->getOperand(0).getValueType() == MVT::Other &&
295 "Node doesn't have a token chain argument!");
296 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
299 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
300 /// see if any uses can reach Dest. If no dest operands can get to dest,
301 /// legalize them, legalize ourself, and return false, otherwise, return true.
303 /// Keep track of the nodes we fine that actually do lead to Dest in
304 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
306 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
307 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
308 if (N == Dest) return true; // N certainly leads to Dest :)
310 // If we've already processed this node and it does lead to Dest, there is no
311 // need to reprocess it.
312 if (NodesLeadingTo.count(N)) return true;
314 // If the first result of this node has been already legalized, then it cannot
316 if (LegalizedNodes.count(SDValue(N, 0))) return false;
318 // Okay, this node has not already been legalized. Check and legalize all
319 // operands. If none lead to Dest, then we can legalize this node.
320 bool OperandsLeadToDest = false;
321 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
322 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
323 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
325 if (OperandsLeadToDest) {
326 NodesLeadingTo.insert(N);
330 // Okay, this node looks safe, legalize it and return false.
331 LegalizeOp(SDValue(N, 0));
335 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
336 /// a load from the constant pool.
337 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
338 SelectionDAG &DAG, const TargetLowering &TLI) {
340 DebugLoc dl = CFP->getDebugLoc();
342 // If a FP immediate is precise when represented as a float and if the
343 // target can do an extending load from float to double, we put it into
344 // the constant pool as a float, even if it's is statically typed as a
345 // double. This shrinks FP constants and canonicalizes them for targets where
346 // an FP extending load is the same cost as a normal load (such as on the x87
347 // fp stack or PPC FP unit).
348 EVT VT = CFP->getValueType(0);
349 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
351 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
352 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
353 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
358 while (SVT != MVT::f32) {
359 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
360 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
361 // Only do this if the target has a native EXTLOAD instruction from
363 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
364 TLI.ShouldShrinkFPConstant(OrigVT)) {
365 const Type *SType = SVT.getTypeForEVT(*DAG.getContext());
366 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
372 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
373 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
375 return DAG.getExtLoad(ISD::EXTLOAD, dl,
376 OrigVT, DAG.getEntryNode(),
377 CPIdx, PseudoSourceValue::getConstantPool(),
378 0, VT, false, Alignment);
379 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
380 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
383 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
385 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
386 const TargetLowering &TLI) {
387 SDValue Chain = ST->getChain();
388 SDValue Ptr = ST->getBasePtr();
389 SDValue Val = ST->getValue();
390 EVT VT = Val.getValueType();
391 int Alignment = ST->getAlignment();
392 int SVOffset = ST->getSrcValueOffset();
393 DebugLoc dl = ST->getDebugLoc();
394 if (ST->getMemoryVT().isFloatingPoint() ||
395 ST->getMemoryVT().isVector()) {
396 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
397 if (TLI.isTypeLegal(intVT)) {
398 // Expand to a bitconvert of the value to the integer type of the
399 // same size, then a (misaligned) int store.
400 // FIXME: Does not handle truncating floating point stores!
401 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
402 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
403 SVOffset, ST->isVolatile(), Alignment);
405 // Do a (aligned) store to a stack slot, then copy from the stack slot
406 // to the final destination using (unaligned) integer loads and stores.
407 EVT StoredVT = ST->getMemoryVT();
409 TLI.getRegisterType(*DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(), StoredVT.getSizeInBits()));
410 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
411 unsigned RegBytes = RegVT.getSizeInBits() / 8;
412 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
414 // Make sure the stack slot is also aligned for the register type.
415 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
417 // Perform the original store, only redirected to the stack slot.
418 SDValue Store = DAG.getTruncStore(Chain, dl,
419 Val, StackPtr, NULL, 0, StoredVT);
420 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
421 SmallVector<SDValue, 8> Stores;
424 // Do all but one copies using the full register width.
425 for (unsigned i = 1; i < NumRegs; i++) {
426 // Load one integer register's worth from the stack slot.
427 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0);
428 // Store it to the final location. Remember the store.
429 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
430 ST->getSrcValue(), SVOffset + Offset,
432 MinAlign(ST->getAlignment(), Offset)));
433 // Increment the pointers.
435 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
437 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
440 // The last store may be partial. Do a truncating store. On big-endian
441 // machines this requires an extending load from the stack slot to ensure
442 // that the bits are in the right place.
443 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (StoredBytes - Offset));
445 // Load from the stack slot.
446 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
449 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
450 ST->getSrcValue(), SVOffset + Offset,
451 MemVT, ST->isVolatile(),
452 MinAlign(ST->getAlignment(), Offset)));
453 // The order of the stores doesn't matter - say it with a TokenFactor.
454 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
458 assert(ST->getMemoryVT().isInteger() &&
459 !ST->getMemoryVT().isVector() &&
460 "Unaligned store of unknown type.");
461 // Get the half-size VT
463 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT().SimpleTy - 1);
464 int NumBits = NewStoredVT.getSizeInBits();
465 int IncrementSize = NumBits / 8;
467 // Divide the stored value in two parts.
468 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
470 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
472 // Store the two parts
473 SDValue Store1, Store2;
474 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
475 ST->getSrcValue(), SVOffset, NewStoredVT,
476 ST->isVolatile(), Alignment);
477 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
478 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
479 Alignment = MinAlign(Alignment, IncrementSize);
480 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
481 ST->getSrcValue(), SVOffset + IncrementSize,
482 NewStoredVT, ST->isVolatile(), Alignment);
484 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
487 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
489 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
490 const TargetLowering &TLI) {
491 int SVOffset = LD->getSrcValueOffset();
492 SDValue Chain = LD->getChain();
493 SDValue Ptr = LD->getBasePtr();
494 EVT VT = LD->getValueType(0);
495 EVT LoadedVT = LD->getMemoryVT();
496 DebugLoc dl = LD->getDebugLoc();
497 if (VT.isFloatingPoint() || VT.isVector()) {
498 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
499 if (TLI.isTypeLegal(intVT)) {
500 // Expand to a (misaligned) integer load of the same size,
501 // then bitconvert to floating point or vector.
502 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
503 SVOffset, LD->isVolatile(),
505 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
506 if (VT.isFloatingPoint() && LoadedVT != VT)
507 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
509 SDValue Ops[] = { Result, Chain };
510 return DAG.getMergeValues(Ops, 2, dl);
512 // Copy the value to a (aligned) stack slot using (unaligned) integer
513 // loads and stores, then do a (aligned) load from the stack slot.
514 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
515 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
516 unsigned RegBytes = RegVT.getSizeInBits() / 8;
517 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
519 // Make sure the stack slot is also aligned for the register type.
520 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
522 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
523 SmallVector<SDValue, 8> Stores;
524 SDValue StackPtr = StackBase;
527 // Do all but one copies using the full register width.
528 for (unsigned i = 1; i < NumRegs; i++) {
529 // Load one integer register's worth from the original location.
530 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
531 SVOffset + Offset, LD->isVolatile(),
532 MinAlign(LD->getAlignment(), Offset));
533 // Follow the load with a store to the stack slot. Remember the store.
534 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
536 // Increment the pointers.
538 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
539 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
543 // The last copy may be partial. Do an extending load.
544 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (LoadedBytes - Offset));
545 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
546 LD->getSrcValue(), SVOffset + Offset,
547 MemVT, LD->isVolatile(),
548 MinAlign(LD->getAlignment(), Offset));
549 // Follow the load with a store to the stack slot. Remember the store.
550 // On big-endian machines this requires a truncating store to ensure
551 // that the bits end up in the right place.
552 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
555 // The order of the stores doesn't matter - say it with a TokenFactor.
556 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
559 // Finally, perform the original load only redirected to the stack slot.
560 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
563 // Callers expect a MERGE_VALUES node.
564 SDValue Ops[] = { Load, TF };
565 return DAG.getMergeValues(Ops, 2, dl);
568 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
569 "Unaligned load of unsupported type.");
571 // Compute the new VT that is half the size of the old one. This is an
573 unsigned NumBits = LoadedVT.getSizeInBits();
575 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
578 unsigned Alignment = LD->getAlignment();
579 unsigned IncrementSize = NumBits / 8;
580 ISD::LoadExtType HiExtType = LD->getExtensionType();
582 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
583 if (HiExtType == ISD::NON_EXTLOAD)
584 HiExtType = ISD::ZEXTLOAD;
586 // Load the value in two parts
588 if (TLI.isLittleEndian()) {
589 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
590 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
591 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
592 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
593 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
594 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
595 MinAlign(Alignment, IncrementSize));
597 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
598 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
599 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
600 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
601 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
602 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
603 MinAlign(Alignment, IncrementSize));
606 // aggregate the two parts
607 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
608 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
609 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
611 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
614 SDValue Ops[] = { Result, TF };
615 return DAG.getMergeValues(Ops, 2, dl);
618 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
619 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
620 /// is necessary to spill the vector being inserted into to memory, perform
621 /// the insert there, and then read the result back.
622 SDValue SelectionDAGLegalize::
623 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
629 // If the target doesn't support this, we have to spill the input vector
630 // to a temporary stack slot, update the element, then reload it. This is
631 // badness. We could also load the value into a vector register (either
632 // with a "move to register" or "extload into register" instruction, then
633 // permute it into place, if the idx is a constant and if the idx is
634 // supported by the target.
635 EVT VT = Tmp1.getValueType();
636 EVT EltVT = VT.getVectorElementType();
637 EVT IdxVT = Tmp3.getValueType();
638 EVT PtrVT = TLI.getPointerTy();
639 SDValue StackPtr = DAG.CreateStackTemporary(VT);
641 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
644 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
645 PseudoSourceValue::getFixedStack(SPFI), 0);
647 // Truncate or zero extend offset to target pointer type.
648 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
649 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
650 // Add the offset to the index.
651 unsigned EltSize = EltVT.getSizeInBits()/8;
652 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
653 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
654 // Store the scalar value.
655 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
656 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
657 // Load the updated vector.
658 return DAG.getLoad(VT, dl, Ch, StackPtr,
659 PseudoSourceValue::getFixedStack(SPFI), 0);
663 SDValue SelectionDAGLegalize::
664 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
665 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
666 // SCALAR_TO_VECTOR requires that the type of the value being inserted
667 // match the element type of the vector being created, except for
668 // integers in which case the inserted value can be over width.
669 EVT EltVT = Vec.getValueType().getVectorElementType();
670 if (Val.getValueType() == EltVT ||
671 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
672 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
673 Vec.getValueType(), Val);
675 unsigned NumElts = Vec.getValueType().getVectorNumElements();
676 // We generate a shuffle of InVec and ScVec, so the shuffle mask
677 // should be 0,1,2,3,4,5... with the appropriate element replaced with
679 SmallVector<int, 8> ShufOps;
680 for (unsigned i = 0; i != NumElts; ++i)
681 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
683 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
687 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
690 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
691 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
692 // FIXME: We shouldn't do this for TargetConstantFP's.
693 // FIXME: move this to the DAG Combiner! Note that we can't regress due
694 // to phase ordering between legalized code and the dag combiner. This
695 // probably means that we need to integrate dag combiner and legalizer
697 // We generally can't do this one for long doubles.
698 SDValue Tmp1 = ST->getChain();
699 SDValue Tmp2 = ST->getBasePtr();
701 int SVOffset = ST->getSrcValueOffset();
702 unsigned Alignment = ST->getAlignment();
703 bool isVolatile = ST->isVolatile();
704 DebugLoc dl = ST->getDebugLoc();
705 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
706 if (CFP->getValueType(0) == MVT::f32 &&
707 getTypeAction(MVT::i32) == Legal) {
708 Tmp3 = DAG.getConstant(CFP->getValueAPF().
709 bitcastToAPInt().zextOrTrunc(32),
711 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
712 SVOffset, isVolatile, Alignment);
713 } else if (CFP->getValueType(0) == MVT::f64) {
714 // If this target supports 64-bit registers, do a single 64-bit store.
715 if (getTypeAction(MVT::i64) == Legal) {
716 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
717 zextOrTrunc(64), MVT::i64);
718 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
719 SVOffset, isVolatile, Alignment);
720 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
721 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
722 // stores. If the target supports neither 32- nor 64-bits, this
723 // xform is certainly not worth it.
724 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
725 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
726 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
727 if (TLI.isBigEndian()) std::swap(Lo, Hi);
729 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
730 SVOffset, isVolatile, Alignment);
731 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
732 DAG.getIntPtrConstant(4));
733 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
734 isVolatile, MinAlign(Alignment, 4U));
736 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
743 /// LegalizeOp - We know that the specified value has a legal type, and
744 /// that its operands are legal. Now ensure that the operation itself
745 /// is legal, recursively ensuring that the operands' operations remain
747 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
748 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
751 SDNode *Node = Op.getNode();
752 DebugLoc dl = Node->getDebugLoc();
754 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
755 assert(getTypeAction(Node->getValueType(i)) == Legal &&
756 "Unexpected illegal type!");
758 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
759 assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
760 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
761 "Unexpected illegal type!");
763 // Note that LegalizeOp may be reentered even from single-use nodes, which
764 // means that we always must cache transformed nodes.
765 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
766 if (I != LegalizedNodes.end()) return I->second;
768 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
770 bool isCustom = false;
772 // Figure out the correct action; the way to query this varies by opcode
773 TargetLowering::LegalizeAction Action;
774 bool SimpleFinishLegalizing = true;
775 switch (Node->getOpcode()) {
776 case ISD::INTRINSIC_W_CHAIN:
777 case ISD::INTRINSIC_WO_CHAIN:
778 case ISD::INTRINSIC_VOID:
781 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
783 case ISD::SINT_TO_FP:
784 case ISD::UINT_TO_FP:
785 case ISD::EXTRACT_VECTOR_ELT:
786 Action = TLI.getOperationAction(Node->getOpcode(),
787 Node->getOperand(0).getValueType());
789 case ISD::FP_ROUND_INREG:
790 case ISD::SIGN_EXTEND_INREG: {
791 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
792 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
798 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
799 Node->getOpcode() == ISD::SETCC ? 2 : 1;
800 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
801 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
802 ISD::CondCode CCCode =
803 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
804 Action = TLI.getCondCodeAction(CCCode, OpVT);
805 if (Action == TargetLowering::Legal) {
806 if (Node->getOpcode() == ISD::SELECT_CC)
807 Action = TLI.getOperationAction(Node->getOpcode(),
808 Node->getValueType(0));
810 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
816 // FIXME: Model these properly. LOAD and STORE are complicated, and
817 // STORE expects the unlegalized operand in some cases.
818 SimpleFinishLegalizing = false;
820 case ISD::CALLSEQ_START:
821 case ISD::CALLSEQ_END:
822 // FIXME: This shouldn't be necessary. These nodes have special properties
823 // dealing with the recursive nature of legalization. Removing this
824 // special case should be done as part of making LegalizeDAG non-recursive.
825 SimpleFinishLegalizing = false;
827 case ISD::EXTRACT_ELEMENT:
828 case ISD::FLT_ROUNDS_:
836 case ISD::MERGE_VALUES:
838 case ISD::FRAME_TO_ARGS_OFFSET:
839 // These operations lie about being legal: when they claim to be legal,
840 // they should actually be expanded.
841 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
842 if (Action == TargetLowering::Legal)
843 Action = TargetLowering::Expand;
845 case ISD::TRAMPOLINE:
847 case ISD::RETURNADDR:
848 // These operations lie about being legal: when they claim to be legal,
849 // they should actually be custom-lowered.
850 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
851 if (Action == TargetLowering::Legal)
852 Action = TargetLowering::Custom;
854 case ISD::BUILD_VECTOR:
855 // A weird case: legalization for BUILD_VECTOR never legalizes the
857 // FIXME: This really sucks... changing it isn't semantically incorrect,
858 // but it massively pessimizes the code for floating-point BUILD_VECTORs
859 // because ConstantFP operands get legalized into constant pool loads
860 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
861 // though, because BUILD_VECTORS usually get lowered into other nodes
862 // which get legalized properly.
863 SimpleFinishLegalizing = false;
866 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
867 Action = TargetLowering::Legal;
869 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
874 if (SimpleFinishLegalizing) {
875 SmallVector<SDValue, 8> Ops, ResultVals;
876 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
877 Ops.push_back(LegalizeOp(Node->getOperand(i)));
878 switch (Node->getOpcode()) {
885 // Branches tweak the chain to include LastCALLSEQ_END
886 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
888 Ops[0] = LegalizeOp(Ops[0]);
889 LastCALLSEQ_END = DAG.getEntryNode();
896 // Legalizing shifts/rotates requires adjusting the shift amount
897 // to the appropriate width.
898 if (!Ops[1].getValueType().isVector())
899 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1]));
904 // Legalizing shifts/rotates requires adjusting the shift amount
905 // to the appropriate width.
906 if (!Ops[2].getValueType().isVector())
907 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2]));
911 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(),
914 case TargetLowering::Legal:
915 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
916 ResultVals.push_back(Result.getValue(i));
918 case TargetLowering::Custom:
919 // FIXME: The handling for custom lowering with multiple results is
921 Tmp1 = TLI.LowerOperation(Result, DAG);
922 if (Tmp1.getNode()) {
923 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
925 ResultVals.push_back(Tmp1);
927 ResultVals.push_back(Tmp1.getValue(i));
933 case TargetLowering::Expand:
934 ExpandNode(Result.getNode(), ResultVals);
936 case TargetLowering::Promote:
937 PromoteNode(Result.getNode(), ResultVals);
940 if (!ResultVals.empty()) {
941 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
942 if (ResultVals[i] != SDValue(Node, i))
943 ResultVals[i] = LegalizeOp(ResultVals[i]);
944 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
946 return ResultVals[Op.getResNo()];
950 switch (Node->getOpcode()) {
953 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
955 llvm_unreachable("Do not know how to legalize this operator!");
957 case ISD::BUILD_VECTOR:
958 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
959 default: llvm_unreachable("This action is not supported yet!");
960 case TargetLowering::Custom:
961 Tmp3 = TLI.LowerOperation(Result, DAG);
962 if (Tmp3.getNode()) {
967 case TargetLowering::Expand:
968 Result = ExpandBUILD_VECTOR(Result.getNode());
972 case ISD::CALLSEQ_START: {
973 SDNode *CallEnd = FindCallEndFromCallStart(Node);
975 // Recursively Legalize all of the inputs of the call end that do not lead
976 // to this call start. This ensures that any libcalls that need be inserted
977 // are inserted *before* the CALLSEQ_START.
978 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
979 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
980 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
984 // Now that we legalized all of the inputs (which may have inserted
985 // libcalls) create the new CALLSEQ_START node.
986 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
988 // Merge in the last call, to ensure that this call start after the last
990 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
991 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
992 Tmp1, LastCALLSEQ_END);
993 Tmp1 = LegalizeOp(Tmp1);
996 // Do not try to legalize the target-specific arguments (#1+).
997 if (Tmp1 != Node->getOperand(0)) {
998 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1000 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1003 // Remember that the CALLSEQ_START is legalized.
1004 AddLegalizedOperand(Op.getValue(0), Result);
1005 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1006 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1008 // Now that the callseq_start and all of the non-call nodes above this call
1009 // sequence have been legalized, legalize the call itself. During this
1010 // process, no libcalls can/will be inserted, guaranteeing that no calls
1012 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1013 // Note that we are selecting this call!
1014 LastCALLSEQ_END = SDValue(CallEnd, 0);
1015 IsLegalizingCall = true;
1017 // Legalize the call, starting from the CALLSEQ_END.
1018 LegalizeOp(LastCALLSEQ_END);
1019 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1022 case ISD::CALLSEQ_END:
1023 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1024 // will cause this node to be legalized as well as handling libcalls right.
1025 if (LastCALLSEQ_END.getNode() != Node) {
1026 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1027 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1028 assert(I != LegalizedNodes.end() &&
1029 "Legalizing the call start should have legalized this node!");
1033 // Otherwise, the call start has been legalized and everything is going
1034 // according to plan. Just legalize ourselves normally here.
1035 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1036 // Do not try to legalize the target-specific arguments (#1+), except for
1037 // an optional flag input.
1038 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1039 if (Tmp1 != Node->getOperand(0)) {
1040 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1042 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1045 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1046 if (Tmp1 != Node->getOperand(0) ||
1047 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1048 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1051 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1054 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1055 // This finishes up call legalization.
1056 IsLegalizingCall = false;
1058 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1059 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1060 if (Node->getNumValues() == 2)
1061 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1062 return Result.getValue(Op.getResNo());
1064 LoadSDNode *LD = cast<LoadSDNode>(Node);
1065 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1066 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1068 ISD::LoadExtType ExtType = LD->getExtensionType();
1069 if (ExtType == ISD::NON_EXTLOAD) {
1070 EVT VT = Node->getValueType(0);
1071 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1072 Tmp3 = Result.getValue(0);
1073 Tmp4 = Result.getValue(1);
1075 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1076 default: llvm_unreachable("This action is not supported yet!");
1077 case TargetLowering::Legal:
1078 // If this is an unaligned load and the target doesn't support it,
1080 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1081 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1082 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1083 if (LD->getAlignment() < ABIAlignment){
1084 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1086 Tmp3 = Result.getOperand(0);
1087 Tmp4 = Result.getOperand(1);
1088 Tmp3 = LegalizeOp(Tmp3);
1089 Tmp4 = LegalizeOp(Tmp4);
1093 case TargetLowering::Custom:
1094 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1095 if (Tmp1.getNode()) {
1096 Tmp3 = LegalizeOp(Tmp1);
1097 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1100 case TargetLowering::Promote: {
1101 // Only promote a load of vector type to another.
1102 assert(VT.isVector() && "Cannot promote this load!");
1103 // Change base type to a different vector type.
1104 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1106 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1107 LD->getSrcValueOffset(),
1108 LD->isVolatile(), LD->getAlignment());
1109 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
1110 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1114 // Since loads produce two values, make sure to remember that we
1115 // legalized both of them.
1116 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1117 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1118 return Op.getResNo() ? Tmp4 : Tmp3;
1120 EVT SrcVT = LD->getMemoryVT();
1121 unsigned SrcWidth = SrcVT.getSizeInBits();
1122 int SVOffset = LD->getSrcValueOffset();
1123 unsigned Alignment = LD->getAlignment();
1124 bool isVolatile = LD->isVolatile();
1126 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1127 // Some targets pretend to have an i1 loading operation, and actually
1128 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1129 // bits are guaranteed to be zero; it helps the optimizers understand
1130 // that these bits are zero. It is also useful for EXTLOAD, since it
1131 // tells the optimizers that those bits are undefined. It would be
1132 // nice to have an effective generic way of getting these benefits...
1133 // Until such a way is found, don't insist on promoting i1 here.
1134 (SrcVT != MVT::i1 ||
1135 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1136 // Promote to a byte-sized load if not loading an integral number of
1137 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1138 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1139 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
1142 // The extra bits are guaranteed to be zero, since we stored them that
1143 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1145 ISD::LoadExtType NewExtType =
1146 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1148 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
1149 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1150 NVT, isVolatile, Alignment);
1152 Ch = Result.getValue(1); // The chain.
1154 if (ExtType == ISD::SEXTLOAD)
1155 // Having the top bits zero doesn't help when sign extending.
1156 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1157 Result.getValueType(),
1158 Result, DAG.getValueType(SrcVT));
1159 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1160 // All the top bits are guaranteed to be zero - inform the optimizers.
1161 Result = DAG.getNode(ISD::AssertZext, dl,
1162 Result.getValueType(), Result,
1163 DAG.getValueType(SrcVT));
1165 Tmp1 = LegalizeOp(Result);
1166 Tmp2 = LegalizeOp(Ch);
1167 } else if (SrcWidth & (SrcWidth - 1)) {
1168 // If not loading a power-of-2 number of bits, expand as two loads.
1169 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
1170 "Unsupported extload!");
1171 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1172 assert(RoundWidth < SrcWidth);
1173 unsigned ExtraWidth = SrcWidth - RoundWidth;
1174 assert(ExtraWidth < RoundWidth);
1175 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1176 "Load size not an integral number of bytes!");
1177 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1178 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1180 unsigned IncrementSize;
1182 if (TLI.isLittleEndian()) {
1183 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1184 // Load the bottom RoundWidth bits.
1185 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
1186 Node->getValueType(0), Tmp1, Tmp2,
1187 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1190 // Load the remaining ExtraWidth bits.
1191 IncrementSize = RoundWidth / 8;
1192 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1193 DAG.getIntPtrConstant(IncrementSize));
1194 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1195 LD->getSrcValue(), SVOffset + IncrementSize,
1196 ExtraVT, isVolatile,
1197 MinAlign(Alignment, IncrementSize));
1199 // Build a factor node to remember that this load is independent of the
1201 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1204 // Move the top bits to the right place.
1205 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1206 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1208 // Join the hi and lo parts.
1209 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1211 // Big endian - avoid unaligned loads.
1212 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1213 // Load the top RoundWidth bits.
1214 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1215 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1218 // Load the remaining ExtraWidth bits.
1219 IncrementSize = RoundWidth / 8;
1220 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1221 DAG.getIntPtrConstant(IncrementSize));
1222 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
1223 Node->getValueType(0), Tmp1, Tmp2,
1224 LD->getSrcValue(), SVOffset + IncrementSize,
1225 ExtraVT, isVolatile,
1226 MinAlign(Alignment, IncrementSize));
1228 // Build a factor node to remember that this load is independent of the
1230 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1233 // Move the top bits to the right place.
1234 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1235 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1237 // Join the hi and lo parts.
1238 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1241 Tmp1 = LegalizeOp(Result);
1242 Tmp2 = LegalizeOp(Ch);
1244 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1245 default: llvm_unreachable("This action is not supported yet!");
1246 case TargetLowering::Custom:
1249 case TargetLowering::Legal:
1250 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1251 Tmp1 = Result.getValue(0);
1252 Tmp2 = Result.getValue(1);
1255 Tmp3 = TLI.LowerOperation(Result, DAG);
1256 if (Tmp3.getNode()) {
1257 Tmp1 = LegalizeOp(Tmp3);
1258 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1261 // If this is an unaligned load and the target doesn't support it,
1263 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1264 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1265 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1266 if (LD->getAlignment() < ABIAlignment){
1267 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1269 Tmp1 = Result.getOperand(0);
1270 Tmp2 = Result.getOperand(1);
1271 Tmp1 = LegalizeOp(Tmp1);
1272 Tmp2 = LegalizeOp(Tmp2);
1277 case TargetLowering::Expand:
1278 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1279 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1280 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1281 LD->getSrcValueOffset(),
1282 LD->isVolatile(), LD->getAlignment());
1283 Result = DAG.getNode(ISD::FP_EXTEND, dl,
1284 Node->getValueType(0), Load);
1285 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1286 Tmp2 = LegalizeOp(Load.getValue(1));
1289 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1290 // Turn the unsupported load into an EXTLOAD followed by an explicit
1291 // zero/sign extend inreg.
1292 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1293 Tmp1, Tmp2, LD->getSrcValue(),
1294 LD->getSrcValueOffset(), SrcVT,
1295 LD->isVolatile(), LD->getAlignment());
1297 if (ExtType == ISD::SEXTLOAD)
1298 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1299 Result.getValueType(),
1300 Result, DAG.getValueType(SrcVT));
1302 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
1303 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1304 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1309 // Since loads produce two values, make sure to remember that we legalized
1311 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1312 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1313 return Op.getResNo() ? Tmp2 : Tmp1;
1317 StoreSDNode *ST = cast<StoreSDNode>(Node);
1318 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1319 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1320 int SVOffset = ST->getSrcValueOffset();
1321 unsigned Alignment = ST->getAlignment();
1322 bool isVolatile = ST->isVolatile();
1324 if (!ST->isTruncatingStore()) {
1325 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1326 Result = SDValue(OptStore, 0);
1331 Tmp3 = LegalizeOp(ST->getValue());
1332 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1335 EVT VT = Tmp3.getValueType();
1336 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1337 default: llvm_unreachable("This action is not supported yet!");
1338 case TargetLowering::Legal:
1339 // If this is an unaligned store and the target doesn't support it,
1341 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1342 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1343 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1344 if (ST->getAlignment() < ABIAlignment)
1345 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1349 case TargetLowering::Custom:
1350 Tmp1 = TLI.LowerOperation(Result, DAG);
1351 if (Tmp1.getNode()) Result = Tmp1;
1353 case TargetLowering::Promote:
1354 assert(VT.isVector() && "Unknown legal promote case!");
1355 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
1356 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1357 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1358 ST->getSrcValue(), SVOffset, isVolatile,
1365 Tmp3 = LegalizeOp(ST->getValue());
1367 EVT StVT = ST->getMemoryVT();
1368 unsigned StWidth = StVT.getSizeInBits();
1370 if (StWidth != StVT.getStoreSizeInBits()) {
1371 // Promote to a byte-sized store with upper bits zero if not
1372 // storing an integral number of bytes. For example, promote
1373 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1374 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), StVT.getStoreSizeInBits());
1375 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1376 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1377 SVOffset, NVT, isVolatile, Alignment);
1378 } else if (StWidth & (StWidth - 1)) {
1379 // If not storing a power-of-2 number of bits, expand as two stores.
1380 assert(StVT.isExtended() && !StVT.isVector() &&
1381 "Unsupported truncstore!");
1382 unsigned RoundWidth = 1 << Log2_32(StWidth);
1383 assert(RoundWidth < StWidth);
1384 unsigned ExtraWidth = StWidth - RoundWidth;
1385 assert(ExtraWidth < RoundWidth);
1386 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1387 "Store size not an integral number of bytes!");
1388 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1389 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1391 unsigned IncrementSize;
1393 if (TLI.isLittleEndian()) {
1394 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1395 // Store the bottom RoundWidth bits.
1396 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1398 isVolatile, Alignment);
1400 // Store the remaining ExtraWidth bits.
1401 IncrementSize = RoundWidth / 8;
1402 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1403 DAG.getIntPtrConstant(IncrementSize));
1404 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1405 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1406 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1407 SVOffset + IncrementSize, ExtraVT, isVolatile,
1408 MinAlign(Alignment, IncrementSize));
1410 // Big endian - avoid unaligned stores.
1411 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1412 // Store the top RoundWidth bits.
1413 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1414 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1415 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1416 SVOffset, RoundVT, isVolatile, Alignment);
1418 // Store the remaining ExtraWidth bits.
1419 IncrementSize = RoundWidth / 8;
1420 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1421 DAG.getIntPtrConstant(IncrementSize));
1422 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1423 SVOffset + IncrementSize, ExtraVT, isVolatile,
1424 MinAlign(Alignment, IncrementSize));
1427 // The order of the stores doesn't matter.
1428 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1430 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1431 Tmp2 != ST->getBasePtr())
1432 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1435 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1436 default: llvm_unreachable("This action is not supported yet!");
1437 case TargetLowering::Legal:
1438 // If this is an unaligned store and the target doesn't support it,
1440 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1441 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1442 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1443 if (ST->getAlignment() < ABIAlignment)
1444 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1448 case TargetLowering::Custom:
1449 Result = TLI.LowerOperation(Result, DAG);
1452 // TRUNCSTORE:i16 i32 -> STORE i16
1453 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
1454 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1455 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1456 SVOffset, isVolatile, Alignment);
1464 assert(Result.getValueType() == Op.getValueType() &&
1465 "Bad legalization!");
1467 // Make sure that the generated code is itself legal.
1469 Result = LegalizeOp(Result);
1471 // Note that LegalizeOp may be reentered even from single-use nodes, which
1472 // means that we always must cache transformed nodes.
1473 AddLegalizedOperand(Op, Result);
1477 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1478 SDValue Vec = Op.getOperand(0);
1479 SDValue Idx = Op.getOperand(1);
1480 DebugLoc dl = Op.getDebugLoc();
1481 // Store the value to a temporary stack slot, then LOAD the returned part.
1482 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1483 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
1485 // Add the offset to the index.
1487 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1488 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1489 DAG.getConstant(EltSize, Idx.getValueType()));
1491 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1492 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1494 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1496 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1498 if (Op.getValueType().isVector())
1499 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0);
1501 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1502 NULL, 0, Vec.getValueType().getVectorElementType());
1505 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1506 // We can't handle this case efficiently. Allocate a sufficiently
1507 // aligned object on the stack, store each element into it, then load
1508 // the result as a vector.
1509 // Create the stack frame object.
1510 EVT VT = Node->getValueType(0);
1511 EVT OpVT = Node->getOperand(0).getValueType();
1512 DebugLoc dl = Node->getDebugLoc();
1513 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1514 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1515 const Value *SV = PseudoSourceValue::getFixedStack(FI);
1517 // Emit a store of each element to the stack slot.
1518 SmallVector<SDValue, 8> Stores;
1519 unsigned TypeByteSize = OpVT.getSizeInBits() / 8;
1520 // Store (in the right endianness) the elements to memory.
1521 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1522 // Ignore undef elements.
1523 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1525 unsigned Offset = TypeByteSize*i;
1527 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1528 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1530 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
1535 if (!Stores.empty()) // Not all undef elements?
1536 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1537 &Stores[0], Stores.size());
1539 StoreChain = DAG.getEntryNode();
1541 // Result is a load from the stack slot.
1542 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0);
1545 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1546 DebugLoc dl = Node->getDebugLoc();
1547 SDValue Tmp1 = Node->getOperand(0);
1548 SDValue Tmp2 = Node->getOperand(1);
1549 assert((Tmp2.getValueType() == MVT::f32 ||
1550 Tmp2.getValueType() == MVT::f64) &&
1551 "Ugly special-cased code!");
1552 // Get the sign bit of the RHS.
1554 EVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32;
1555 if (isTypeLegal(IVT)) {
1556 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
1558 assert(isTypeLegal(TLI.getPointerTy()) &&
1559 (TLI.getPointerTy() == MVT::i32 ||
1560 TLI.getPointerTy() == MVT::i64) &&
1561 "Legal type for load?!");
1562 SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType());
1563 SDValue StorePtr = StackPtr, LoadPtr = StackPtr;
1565 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0);
1566 if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian())
1567 LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(),
1568 LoadPtr, DAG.getIntPtrConstant(4));
1569 SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(),
1570 Ch, LoadPtr, NULL, 0, MVT::i32);
1573 DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1574 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1576 // Get the absolute value of the result.
1577 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1578 // Select between the nabs and abs value based on the sign bit of
1580 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1581 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1585 SDValue SelectionDAGLegalize::ExpandDBG_STOPPOINT(SDNode* Node) {
1586 DebugLoc dl = Node->getDebugLoc();
1587 DwarfWriter *DW = DAG.getDwarfWriter();
1588 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
1590 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
1592 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1593 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
1594 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) {
1595 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit()));
1597 unsigned Line = DSP->getLine();
1598 unsigned Col = DSP->getColumn();
1600 if (OptLevel == CodeGenOpt::None) {
1601 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
1602 // won't hurt anything.
1604 return DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Node->getOperand(0),
1605 DAG.getConstant(Line, MVT::i32),
1606 DAG.getConstant(Col, MVT::i32),
1607 DAG.getSrcValue(CU.getGV()));
1609 unsigned ID = DW->RecordSourceLine(Line, Col, CU);
1610 return DAG.getLabel(ISD::DBG_LABEL, dl, Node->getOperand(0), ID);
1614 return Node->getOperand(0);
1617 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1618 SmallVectorImpl<SDValue> &Results) {
1619 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1620 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1621 " not tell us which reg is the stack pointer!");
1622 DebugLoc dl = Node->getDebugLoc();
1623 EVT VT = Node->getValueType(0);
1624 SDValue Tmp1 = SDValue(Node, 0);
1625 SDValue Tmp2 = SDValue(Node, 1);
1626 SDValue Tmp3 = Node->getOperand(2);
1627 SDValue Chain = Tmp1.getOperand(0);
1629 // Chain the dynamic stack allocation so that it doesn't modify the stack
1630 // pointer when other instructions are using the stack.
1631 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1633 SDValue Size = Tmp2.getOperand(1);
1634 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1635 Chain = SP.getValue(1);
1636 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1637 unsigned StackAlign =
1638 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1639 if (Align > StackAlign)
1640 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1641 DAG.getConstant(-(uint64_t)Align, VT));
1642 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1643 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1645 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1646 DAG.getIntPtrConstant(0, true), SDValue());
1648 Results.push_back(Tmp1);
1649 Results.push_back(Tmp2);
1652 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1653 /// condition code CC on the current target. This routine assumes LHS and rHS
1654 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
1655 /// illegal condition code into AND / OR of multiple SETCC values.
1656 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1657 SDValue &LHS, SDValue &RHS,
1660 EVT OpVT = LHS.getValueType();
1661 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1662 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1663 default: llvm_unreachable("Unknown condition code action!");
1664 case TargetLowering::Legal:
1667 case TargetLowering::Expand: {
1668 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1671 default: llvm_unreachable("Don't know how to expand this condition!");
1672 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1673 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1674 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1675 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1676 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1677 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1678 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1679 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1680 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1681 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1682 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1683 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1684 // FIXME: Implement more expansions.
1687 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1688 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1689 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1697 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1698 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1699 /// a load from the stack slot to DestVT, extending it if needed.
1700 /// The resultant code need not be legal.
1701 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1705 // Create the stack frame object.
1707 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1708 getTypeForEVT(*DAG.getContext()));
1709 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1711 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1712 int SPFI = StackPtrFI->getIndex();
1713 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
1715 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1716 unsigned SlotSize = SlotVT.getSizeInBits();
1717 unsigned DestSize = DestVT.getSizeInBits();
1718 unsigned DestAlign =
1719 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForEVT(*DAG.getContext()));
1721 // Emit a store to the stack slot. Use a truncstore if the input value is
1722 // later than DestVT.
1725 if (SrcSize > SlotSize)
1726 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1727 SV, 0, SlotVT, false, SrcAlign);
1729 assert(SrcSize == SlotSize && "Invalid store");
1730 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1731 SV, 0, false, SrcAlign);
1734 // Result is a load from the stack slot.
1735 if (SlotSize == DestSize)
1736 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign);
1738 assert(SlotSize < DestSize && "Unknown extension!");
1739 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
1743 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1744 DebugLoc dl = Node->getDebugLoc();
1745 // Create a vector sized/aligned stack slot, store the value to element #0,
1746 // then load the whole vector back out.
1747 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1749 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1750 int SPFI = StackPtrFI->getIndex();
1752 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1754 PseudoSourceValue::getFixedStack(SPFI), 0,
1755 Node->getValueType(0).getVectorElementType());
1756 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1757 PseudoSourceValue::getFixedStack(SPFI), 0);
1761 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1762 /// support the operation, but do support the resultant vector type.
1763 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1764 unsigned NumElems = Node->getNumOperands();
1765 SDValue Value1, Value2;
1766 DebugLoc dl = Node->getDebugLoc();
1767 EVT VT = Node->getValueType(0);
1768 EVT OpVT = Node->getOperand(0).getValueType();
1769 EVT EltVT = VT.getVectorElementType();
1771 // If the only non-undef value is the low element, turn this into a
1772 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1773 bool isOnlyLowElement = true;
1774 bool MoreThanTwoValues = false;
1775 bool isConstant = true;
1776 for (unsigned i = 0; i < NumElems; ++i) {
1777 SDValue V = Node->getOperand(i);
1778 if (V.getOpcode() == ISD::UNDEF)
1781 isOnlyLowElement = false;
1782 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1785 if (!Value1.getNode()) {
1787 } else if (!Value2.getNode()) {
1790 } else if (V != Value1 && V != Value2) {
1791 MoreThanTwoValues = true;
1795 if (!Value1.getNode())
1796 return DAG.getUNDEF(VT);
1798 if (isOnlyLowElement)
1799 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1801 // If all elements are constants, create a load from the constant pool.
1803 std::vector<Constant*> CV;
1804 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1805 if (ConstantFPSDNode *V =
1806 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1807 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1808 } else if (ConstantSDNode *V =
1809 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1810 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1812 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1813 const Type *OpNTy = OpVT.getTypeForEVT(*DAG.getContext());
1814 CV.push_back(UndefValue::get(OpNTy));
1817 Constant *CP = ConstantVector::get(CV);
1818 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1819 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1820 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1821 PseudoSourceValue::getConstantPool(), 0,
1825 if (!MoreThanTwoValues) {
1826 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1827 for (unsigned i = 0; i < NumElems; ++i) {
1828 SDValue V = Node->getOperand(i);
1829 if (V.getOpcode() == ISD::UNDEF)
1831 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1833 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1834 // Get the splatted value into the low element of a vector register.
1835 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1837 if (Value2.getNode())
1838 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1840 Vec2 = DAG.getUNDEF(VT);
1842 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1843 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1847 // Otherwise, we can't handle this case efficiently.
1848 return ExpandVectorBuildThroughStack(Node);
1851 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1852 // does not fit into a register, return the lo part and set the hi part to the
1853 // by-reg argument. If it does fit into a single register, return the result
1854 // and leave the Hi part unset.
1855 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1857 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
1858 // The input chain to this libcall is the entry node of the function.
1859 // Legalizing the call will automatically add the previous call to the
1861 SDValue InChain = DAG.getEntryNode();
1863 TargetLowering::ArgListTy Args;
1864 TargetLowering::ArgListEntry Entry;
1865 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1866 EVT ArgVT = Node->getOperand(i).getValueType();
1867 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1868 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1869 Entry.isSExt = isSigned;
1870 Entry.isZExt = !isSigned;
1871 Args.push_back(Entry);
1873 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1874 TLI.getPointerTy());
1876 // Splice the libcall in wherever FindInputOutputChains tells us to.
1877 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1878 std::pair<SDValue, SDValue> CallInfo =
1879 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
1880 0, TLI.getLibcallCallingConv(LC), false,
1881 /*isReturnValueUsed=*/true,
1883 Node->getDebugLoc());
1885 // Legalize the call sequence, starting with the chain. This will advance
1886 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
1887 // was added by LowerCallTo (guaranteeing proper serialization of calls).
1888 LegalizeOp(CallInfo.second);
1889 return CallInfo.first;
1892 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1893 RTLIB::Libcall Call_F32,
1894 RTLIB::Libcall Call_F64,
1895 RTLIB::Libcall Call_F80,
1896 RTLIB::Libcall Call_PPCF128) {
1898 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1899 default: llvm_unreachable("Unexpected request for libcall!");
1900 case MVT::f32: LC = Call_F32; break;
1901 case MVT::f64: LC = Call_F64; break;
1902 case MVT::f80: LC = Call_F80; break;
1903 case MVT::ppcf128: LC = Call_PPCF128; break;
1905 return ExpandLibCall(LC, Node, false);
1908 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1909 RTLIB::Libcall Call_I16,
1910 RTLIB::Libcall Call_I32,
1911 RTLIB::Libcall Call_I64,
1912 RTLIB::Libcall Call_I128) {
1914 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1915 default: llvm_unreachable("Unexpected request for libcall!");
1916 case MVT::i16: LC = Call_I16; break;
1917 case MVT::i32: LC = Call_I32; break;
1918 case MVT::i64: LC = Call_I64; break;
1919 case MVT::i128: LC = Call_I128; break;
1921 return ExpandLibCall(LC, Node, isSigned);
1924 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
1925 /// INT_TO_FP operation of the specified operand when the target requests that
1926 /// we expand it. At this point, we know that the result and operand types are
1927 /// legal for the target.
1928 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
1932 if (Op0.getValueType() == MVT::i32) {
1933 // simple 32-bit [signed|unsigned] integer to float/double expansion
1935 // Get the stack frame index of a 8 byte buffer.
1936 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
1938 // word offset constant for Hi/Lo address computation
1939 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
1940 // set up Hi and Lo (into buffer) address based on endian
1941 SDValue Hi = StackSlot;
1942 SDValue Lo = DAG.getNode(ISD::ADD, dl,
1943 TLI.getPointerTy(), StackSlot, WordOff);
1944 if (TLI.isLittleEndian())
1947 // if signed map to unsigned space
1950 // constant used to invert sign bit (signed to unsigned mapping)
1951 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
1952 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
1956 // store the lo of the constructed double - based on integer input
1957 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
1958 Op0Mapped, Lo, NULL, 0);
1959 // initial hi portion of constructed double
1960 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
1961 // store the hi of the constructed double - biased exponent
1962 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
1963 // load the constructed double
1964 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
1965 // FP constant to bias correct the final result
1966 SDValue Bias = DAG.getConstantFP(isSigned ?
1967 BitsToDouble(0x4330000080000000ULL) :
1968 BitsToDouble(0x4330000000000000ULL),
1970 // subtract the bias
1971 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
1974 // handle final rounding
1975 if (DestVT == MVT::f64) {
1978 } else if (DestVT.bitsLT(MVT::f64)) {
1979 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
1980 DAG.getIntPtrConstant(0));
1981 } else if (DestVT.bitsGT(MVT::f64)) {
1982 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
1986 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
1987 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
1989 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
1990 Op0, DAG.getConstant(0, Op0.getValueType()),
1992 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
1993 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
1994 SignSet, Four, Zero);
1996 // If the sign bit of the integer is set, the large number will be treated
1997 // as a negative number. To counteract this, the dynamic code adds an
1998 // offset depending on the data type.
2000 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2001 default: llvm_unreachable("Unsupported integer type!");
2002 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2003 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2004 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2005 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2007 if (TLI.isLittleEndian()) FF <<= 32;
2008 Constant *FudgeFactor = ConstantInt::get(
2009 Type::getInt64Ty(*DAG.getContext()), FF);
2011 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2012 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2013 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2014 Alignment = std::min(Alignment, 4u);
2016 if (DestVT == MVT::f32)
2017 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2018 PseudoSourceValue::getConstantPool(), 0,
2022 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2023 DAG.getEntryNode(), CPIdx,
2024 PseudoSourceValue::getConstantPool(), 0,
2025 MVT::f32, false, Alignment));
2028 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2031 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2032 /// *INT_TO_FP operation of the specified operand when the target requests that
2033 /// we promote it. At this point, we know that the result and operand types are
2034 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2035 /// operation that takes a larger input.
2036 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2040 // First step, figure out the appropriate *INT_TO_FP operation to use.
2041 EVT NewInTy = LegalOp.getValueType();
2043 unsigned OpToUse = 0;
2045 // Scan for the appropriate larger type to use.
2047 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2048 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2050 // If the target supports SINT_TO_FP of this type, use it.
2051 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2052 OpToUse = ISD::SINT_TO_FP;
2055 if (isSigned) continue;
2057 // If the target supports UINT_TO_FP of this type, use it.
2058 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2059 OpToUse = ISD::UINT_TO_FP;
2063 // Otherwise, try a larger type.
2066 // Okay, we found the operation and type to use. Zero extend our input to the
2067 // desired type then run the operation on it.
2068 return DAG.getNode(OpToUse, dl, DestVT,
2069 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2070 dl, NewInTy, LegalOp));
2073 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2074 /// FP_TO_*INT operation of the specified operand when the target requests that
2075 /// we promote it. At this point, we know that the result and operand types are
2076 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2077 /// operation that returns a larger result.
2078 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2082 // First step, figure out the appropriate FP_TO*INT operation to use.
2083 EVT NewOutTy = DestVT;
2085 unsigned OpToUse = 0;
2087 // Scan for the appropriate larger type to use.
2089 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2090 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2092 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2093 OpToUse = ISD::FP_TO_SINT;
2097 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2098 OpToUse = ISD::FP_TO_UINT;
2102 // Otherwise, try a larger type.
2106 // Okay, we found the operation and type to use.
2107 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2109 // Truncate the result of the extended FP_TO_*INT operation to the desired
2111 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2114 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2116 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2117 EVT VT = Op.getValueType();
2118 EVT SHVT = TLI.getShiftAmountTy();
2119 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2120 switch (VT.getSimpleVT().SimpleTy) {
2121 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2123 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2124 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2125 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2127 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2128 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2129 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2130 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2131 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2132 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2133 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2134 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2135 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2137 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2138 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2139 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2140 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2141 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2142 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2143 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2144 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2145 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2146 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2147 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2148 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2149 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2150 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2151 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2152 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2153 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2154 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2155 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2156 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2157 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2161 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2163 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2166 default: llvm_unreachable("Cannot expand this yet!");
2168 static const uint64_t mask[6] = {
2169 0x5555555555555555ULL, 0x3333333333333333ULL,
2170 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
2171 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
2173 EVT VT = Op.getValueType();
2174 EVT ShVT = TLI.getShiftAmountTy();
2175 unsigned len = VT.getSizeInBits();
2176 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2177 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
2178 unsigned EltSize = VT.isVector() ?
2179 VT.getVectorElementType().getSizeInBits() : len;
2180 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
2181 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2182 Op = DAG.getNode(ISD::ADD, dl, VT,
2183 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
2184 DAG.getNode(ISD::AND, dl, VT,
2185 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
2191 // for now, we do this:
2192 // x = x | (x >> 1);
2193 // x = x | (x >> 2);
2195 // x = x | (x >>16);
2196 // x = x | (x >>32); // for 64-bit input
2197 // return popcount(~x);
2199 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2200 EVT VT = Op.getValueType();
2201 EVT ShVT = TLI.getShiftAmountTy();
2202 unsigned len = VT.getSizeInBits();
2203 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2204 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2205 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2206 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2208 Op = DAG.getNOT(dl, Op, VT);
2209 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2212 // for now, we use: { return popcount(~x & (x - 1)); }
2213 // unless the target has ctlz but not ctpop, in which case we use:
2214 // { return 32 - nlz(~x & (x-1)); }
2215 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2216 EVT VT = Op.getValueType();
2217 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2218 DAG.getNOT(dl, Op, VT),
2219 DAG.getNode(ISD::SUB, dl, VT, Op,
2220 DAG.getConstant(1, VT)));
2221 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2222 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2223 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2224 return DAG.getNode(ISD::SUB, dl, VT,
2225 DAG.getConstant(VT.getSizeInBits(), VT),
2226 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2227 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2232 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2233 SmallVectorImpl<SDValue> &Results) {
2234 DebugLoc dl = Node->getDebugLoc();
2235 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2236 switch (Node->getOpcode()) {
2240 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2241 Results.push_back(Tmp1);
2244 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2246 case ISD::FRAMEADDR:
2247 case ISD::RETURNADDR:
2248 case ISD::FRAME_TO_ARGS_OFFSET:
2249 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2251 case ISD::FLT_ROUNDS_:
2252 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2254 case ISD::EH_RETURN:
2255 case ISD::DBG_LABEL:
2258 case ISD::MEMBARRIER:
2260 Results.push_back(Node->getOperand(0));
2262 case ISD::DBG_STOPPOINT:
2263 Results.push_back(ExpandDBG_STOPPOINT(Node));
2265 case ISD::DYNAMIC_STACKALLOC:
2266 ExpandDYNAMIC_STACKALLOC(Node, Results);
2268 case ISD::MERGE_VALUES:
2269 for (unsigned i = 0; i < Node->getNumValues(); i++)
2270 Results.push_back(Node->getOperand(i));
2273 EVT VT = Node->getValueType(0);
2275 Results.push_back(DAG.getConstant(0, VT));
2276 else if (VT.isFloatingPoint())
2277 Results.push_back(DAG.getConstantFP(0, VT));
2279 llvm_unreachable("Unknown value type!");
2283 // If this operation is not supported, lower it to 'abort()' call
2284 TargetLowering::ArgListTy Args;
2285 std::pair<SDValue, SDValue> CallResult =
2286 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2287 false, false, false, false, 0, CallingConv::C, false,
2288 /*isReturnValueUsed=*/true,
2289 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2291 Results.push_back(CallResult.second);
2295 case ISD::BIT_CONVERT:
2296 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2297 Node->getValueType(0), dl);
2298 Results.push_back(Tmp1);
2300 case ISD::FP_EXTEND:
2301 Tmp1 = EmitStackConvert(Node->getOperand(0),
2302 Node->getOperand(0).getValueType(),
2303 Node->getValueType(0), dl);
2304 Results.push_back(Tmp1);
2306 case ISD::SIGN_EXTEND_INREG: {
2307 // NOTE: we could fall back on load/store here too for targets without
2308 // SAR. However, it is doubtful that any exist.
2309 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2310 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
2311 ExtraVT.getSizeInBits();
2312 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2313 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2314 Node->getOperand(0), ShiftCst);
2315 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2316 Results.push_back(Tmp1);
2319 case ISD::FP_ROUND_INREG: {
2320 // The only way we can lower this is to turn it into a TRUNCSTORE,
2321 // EXTLOAD pair, targetting a temporary location (a stack slot).
2323 // NOTE: there is a choice here between constantly creating new stack
2324 // slots and always reusing the same one. We currently always create
2325 // new ones, as reuse may inhibit scheduling.
2326 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2327 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2328 Node->getValueType(0), dl);
2329 Results.push_back(Tmp1);
2332 case ISD::SINT_TO_FP:
2333 case ISD::UINT_TO_FP:
2334 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2335 Node->getOperand(0), Node->getValueType(0), dl);
2336 Results.push_back(Tmp1);
2338 case ISD::FP_TO_UINT: {
2339 SDValue True, False;
2340 EVT VT = Node->getOperand(0).getValueType();
2341 EVT NVT = Node->getValueType(0);
2342 const uint64_t zero[] = {0, 0};
2343 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
2344 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2345 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2346 Tmp1 = DAG.getConstantFP(apf, VT);
2347 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2348 Node->getOperand(0),
2350 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2351 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2352 DAG.getNode(ISD::FSUB, dl, VT,
2353 Node->getOperand(0), Tmp1));
2354 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2355 DAG.getConstant(x, NVT));
2356 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2357 Results.push_back(Tmp1);
2361 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2362 EVT VT = Node->getValueType(0);
2363 Tmp1 = Node->getOperand(0);
2364 Tmp2 = Node->getOperand(1);
2365 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
2366 // Increment the pointer, VAList, to the next vaarg
2367 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2368 DAG.getConstant(TLI.getTargetData()->
2369 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2370 TLI.getPointerTy()));
2371 // Store the incremented VAList to the legalized pointer
2372 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
2373 // Load the actual argument out of the pointer VAList
2374 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0));
2375 Results.push_back(Results[0].getValue(1));
2379 // This defaults to loading a pointer from the input and storing it to the
2380 // output, returning the chain.
2381 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2382 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2383 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2384 Node->getOperand(2), VS, 0);
2385 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0);
2386 Results.push_back(Tmp1);
2389 case ISD::EXTRACT_VECTOR_ELT:
2390 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2391 // This must be an access of the only element. Return it.
2392 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
2393 Node->getOperand(0));
2395 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2396 Results.push_back(Tmp1);
2398 case ISD::EXTRACT_SUBVECTOR:
2399 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2401 case ISD::CONCAT_VECTORS: {
2402 Results.push_back(ExpandVectorBuildThroughStack(Node));
2405 case ISD::SCALAR_TO_VECTOR:
2406 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2408 case ISD::INSERT_VECTOR_ELT:
2409 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2410 Node->getOperand(1),
2411 Node->getOperand(2), dl));
2413 case ISD::VECTOR_SHUFFLE: {
2414 SmallVector<int, 8> Mask;
2415 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
2417 EVT VT = Node->getValueType(0);
2418 EVT EltVT = VT.getVectorElementType();
2419 unsigned NumElems = VT.getVectorNumElements();
2420 SmallVector<SDValue, 8> Ops;
2421 for (unsigned i = 0; i != NumElems; ++i) {
2423 Ops.push_back(DAG.getUNDEF(EltVT));
2426 unsigned Idx = Mask[i];
2428 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2429 Node->getOperand(0),
2430 DAG.getIntPtrConstant(Idx)));
2432 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2433 Node->getOperand(1),
2434 DAG.getIntPtrConstant(Idx - NumElems)));
2436 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2437 Results.push_back(Tmp1);
2440 case ISD::EXTRACT_ELEMENT: {
2441 EVT OpTy = Node->getOperand(0).getValueType();
2442 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2444 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2445 DAG.getConstant(OpTy.getSizeInBits()/2,
2446 TLI.getShiftAmountTy()));
2447 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2450 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2451 Node->getOperand(0));
2453 Results.push_back(Tmp1);
2456 case ISD::STACKSAVE:
2457 // Expand to CopyFromReg if the target set
2458 // StackPointerRegisterToSaveRestore.
2459 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2460 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2461 Node->getValueType(0)));
2462 Results.push_back(Results[0].getValue(1));
2464 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2465 Results.push_back(Node->getOperand(0));
2468 case ISD::STACKRESTORE:
2469 // Expand to CopyToReg if the target set
2470 // StackPointerRegisterToSaveRestore.
2471 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2472 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2473 Node->getOperand(1)));
2475 Results.push_back(Node->getOperand(0));
2478 case ISD::FCOPYSIGN:
2479 Results.push_back(ExpandFCOPYSIGN(Node));
2482 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2483 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2484 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
2485 Node->getOperand(0));
2486 Results.push_back(Tmp1);
2489 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2490 EVT VT = Node->getValueType(0);
2491 Tmp1 = Node->getOperand(0);
2492 Tmp2 = DAG.getConstantFP(0.0, VT);
2493 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2494 Tmp1, Tmp2, ISD::SETUGT);
2495 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
2496 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
2497 Results.push_back(Tmp1);
2501 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
2502 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
2505 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
2506 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
2509 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
2510 RTLIB::COS_F80, RTLIB::COS_PPCF128));
2513 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
2514 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
2517 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
2518 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
2521 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
2522 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
2525 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
2526 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
2529 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
2530 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
2533 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
2534 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
2537 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
2538 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
2541 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
2542 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
2545 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
2546 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
2548 case ISD::FNEARBYINT:
2549 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
2550 RTLIB::NEARBYINT_F64,
2551 RTLIB::NEARBYINT_F80,
2552 RTLIB::NEARBYINT_PPCF128));
2555 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
2556 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
2559 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
2560 RTLIB::POW_F80, RTLIB::POW_PPCF128));
2563 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
2564 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
2567 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
2568 RTLIB::REM_F80, RTLIB::REM_PPCF128));
2570 case ISD::ConstantFP: {
2571 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
2572 // Check to see if this FP immediate is already legal.
2573 bool isLegal = false;
2574 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
2575 E = TLI.legal_fpimm_end(); I != E; ++I) {
2576 if (CFP->isExactlyValue(*I)) {
2581 // If this is a legal constant, turn it into a TargetConstantFP node.
2583 Results.push_back(SDValue(Node, 0));
2585 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
2588 case ISD::EHSELECTION: {
2589 unsigned Reg = TLI.getExceptionSelectorRegister();
2590 assert(Reg && "Can't expand to unknown register!");
2591 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
2592 Node->getValueType(0)));
2593 Results.push_back(Results[0].getValue(1));
2596 case ISD::EXCEPTIONADDR: {
2597 unsigned Reg = TLI.getExceptionAddressRegister();
2598 assert(Reg && "Can't expand to unknown register!");
2599 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
2600 Node->getValueType(0)));
2601 Results.push_back(Results[0].getValue(1));
2605 EVT VT = Node->getValueType(0);
2606 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
2607 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
2608 "Don't know how to expand this subtraction!");
2609 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
2610 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
2611 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
2612 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
2617 EVT VT = Node->getValueType(0);
2618 SDVTList VTs = DAG.getVTList(VT, VT);
2619 bool isSigned = Node->getOpcode() == ISD::SREM;
2620 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
2621 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2622 Tmp2 = Node->getOperand(0);
2623 Tmp3 = Node->getOperand(1);
2624 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
2625 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
2626 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
2628 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
2629 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
2630 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
2631 } else if (isSigned) {
2632 Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SREM_I16, RTLIB::SREM_I32,
2633 RTLIB::SREM_I64, RTLIB::SREM_I128);
2635 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UREM_I16, RTLIB::UREM_I32,
2636 RTLIB::UREM_I64, RTLIB::UREM_I128);
2638 Results.push_back(Tmp1);
2643 bool isSigned = Node->getOpcode() == ISD::SDIV;
2644 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2645 EVT VT = Node->getValueType(0);
2646 SDVTList VTs = DAG.getVTList(VT, VT);
2647 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT))
2648 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
2649 Node->getOperand(1));
2651 Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SDIV_I16, RTLIB::SDIV_I32,
2652 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
2654 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UDIV_I16, RTLIB::UDIV_I32,
2655 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
2656 Results.push_back(Tmp1);
2661 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
2663 EVT VT = Node->getValueType(0);
2664 SDVTList VTs = DAG.getVTList(VT, VT);
2665 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
2666 "If this wasn't legal, it shouldn't have been created!");
2667 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
2668 Node->getOperand(1));
2669 Results.push_back(Tmp1.getValue(1));
2673 EVT VT = Node->getValueType(0);
2674 SDVTList VTs = DAG.getVTList(VT, VT);
2675 // See if multiply or divide can be lowered using two-result operations.
2676 // We just need the low half of the multiply; try both the signed
2677 // and unsigned forms. If the target supports both SMUL_LOHI and
2678 // UMUL_LOHI, form a preference by checking which forms of plain
2679 // MULH it supports.
2680 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
2681 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
2682 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
2683 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
2684 unsigned OpToUse = 0;
2685 if (HasSMUL_LOHI && !HasMULHS) {
2686 OpToUse = ISD::SMUL_LOHI;
2687 } else if (HasUMUL_LOHI && !HasMULHU) {
2688 OpToUse = ISD::UMUL_LOHI;
2689 } else if (HasSMUL_LOHI) {
2690 OpToUse = ISD::SMUL_LOHI;
2691 } else if (HasUMUL_LOHI) {
2692 OpToUse = ISD::UMUL_LOHI;
2695 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
2696 Node->getOperand(1)));
2699 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::MUL_I16, RTLIB::MUL_I32,
2700 RTLIB::MUL_I64, RTLIB::MUL_I128);
2701 Results.push_back(Tmp1);
2706 SDValue LHS = Node->getOperand(0);
2707 SDValue RHS = Node->getOperand(1);
2708 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2709 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2711 Results.push_back(Sum);
2712 EVT OType = Node->getValueType(1);
2714 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2716 // LHSSign -> LHS >= 0
2717 // RHSSign -> RHS >= 0
2718 // SumSign -> Sum >= 0
2721 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2723 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2725 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2726 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2727 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2728 Node->getOpcode() == ISD::SADDO ?
2729 ISD::SETEQ : ISD::SETNE);
2731 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2732 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2734 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2735 Results.push_back(Cmp);
2740 SDValue LHS = Node->getOperand(0);
2741 SDValue RHS = Node->getOperand(1);
2742 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
2743 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2745 Results.push_back(Sum);
2746 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
2747 Node->getOpcode () == ISD::UADDO ?
2748 ISD::SETULT : ISD::SETUGT));
2753 EVT VT = Node->getValueType(0);
2754 SDValue LHS = Node->getOperand(0);
2755 SDValue RHS = Node->getOperand(1);
2758 static unsigned Ops[2][3] =
2759 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
2760 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
2761 bool isSigned = Node->getOpcode() == ISD::SMULO;
2762 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
2763 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
2764 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
2765 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
2766 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
2768 TopHalf = BottomHalf.getValue(1);
2769 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2))) {
2770 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
2771 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
2772 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
2773 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
2774 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
2775 DAG.getIntPtrConstant(0));
2776 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
2777 DAG.getIntPtrConstant(1));
2779 // FIXME: We should be able to fall back to a libcall with an illegal
2780 // type in some cases cases.
2781 // Also, we can fall back to a division in some cases, but that's a big
2782 // performance hit in the general case.
2783 llvm_unreachable("Don't know how to expand this operation yet!");
2786 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy());
2787 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
2788 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
2791 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
2792 DAG.getConstant(0, VT), ISD::SETNE);
2794 Results.push_back(BottomHalf);
2795 Results.push_back(TopHalf);
2798 case ISD::BUILD_PAIR: {
2799 EVT PairTy = Node->getValueType(0);
2800 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
2801 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
2802 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
2803 DAG.getConstant(PairTy.getSizeInBits()/2,
2804 TLI.getShiftAmountTy()));
2805 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
2809 Tmp1 = Node->getOperand(0);
2810 Tmp2 = Node->getOperand(1);
2811 Tmp3 = Node->getOperand(2);
2812 if (Tmp1.getOpcode() == ISD::SETCC) {
2813 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
2815 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2817 Tmp1 = DAG.getSelectCC(dl, Tmp1,
2818 DAG.getConstant(0, Tmp1.getValueType()),
2819 Tmp2, Tmp3, ISD::SETNE);
2821 Results.push_back(Tmp1);
2824 SDValue Chain = Node->getOperand(0);
2825 SDValue Table = Node->getOperand(1);
2826 SDValue Index = Node->getOperand(2);
2828 EVT PTy = TLI.getPointerTy();
2829 MachineFunction &MF = DAG.getMachineFunction();
2830 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
2831 Index= DAG.getNode(ISD::MUL, dl, PTy,
2832 Index, DAG.getConstant(EntrySize, PTy));
2833 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2835 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
2836 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
2837 PseudoSourceValue::getJumpTable(), 0, MemVT);
2839 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2840 // For PIC, the sequence is:
2841 // BRIND(load(Jumptable + index) + RelocBase)
2842 // RelocBase can be JumpTable, GOT or some sort of global base.
2843 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
2844 TLI.getPICJumpTableRelocBase(Table, DAG));
2846 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
2847 Results.push_back(Tmp1);
2851 // Expand brcond's setcc into its constituent parts and create a BR_CC
2853 Tmp1 = Node->getOperand(0);
2854 Tmp2 = Node->getOperand(1);
2855 if (Tmp2.getOpcode() == ISD::SETCC) {
2856 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
2857 Tmp1, Tmp2.getOperand(2),
2858 Tmp2.getOperand(0), Tmp2.getOperand(1),
2859 Node->getOperand(2));
2861 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
2862 DAG.getCondCode(ISD::SETNE), Tmp2,
2863 DAG.getConstant(0, Tmp2.getValueType()),
2864 Node->getOperand(2));
2866 Results.push_back(Tmp1);
2869 Tmp1 = Node->getOperand(0);
2870 Tmp2 = Node->getOperand(1);
2871 Tmp3 = Node->getOperand(2);
2872 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
2874 // If we expanded the SETCC into an AND/OR, return the new node
2875 if (Tmp2.getNode() == 0) {
2876 Results.push_back(Tmp1);
2880 // Otherwise, SETCC for the given comparison type must be completely
2881 // illegal; expand it into a SELECT_CC.
2882 EVT VT = Node->getValueType(0);
2883 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
2884 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
2885 Results.push_back(Tmp1);
2888 case ISD::SELECT_CC: {
2889 Tmp1 = Node->getOperand(0); // LHS
2890 Tmp2 = Node->getOperand(1); // RHS
2891 Tmp3 = Node->getOperand(2); // True
2892 Tmp4 = Node->getOperand(3); // False
2893 SDValue CC = Node->getOperand(4);
2895 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
2896 Tmp1, Tmp2, CC, dl);
2898 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
2899 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2900 CC = DAG.getCondCode(ISD::SETNE);
2901 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
2903 Results.push_back(Tmp1);
2907 Tmp1 = Node->getOperand(0); // Chain
2908 Tmp2 = Node->getOperand(2); // LHS
2909 Tmp3 = Node->getOperand(3); // RHS
2910 Tmp4 = Node->getOperand(1); // CC
2912 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
2913 Tmp2, Tmp3, Tmp4, dl);
2914 LastCALLSEQ_END = DAG.getEntryNode();
2916 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
2917 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2918 Tmp4 = DAG.getCondCode(ISD::SETNE);
2919 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
2920 Tmp3, Node->getOperand(4));
2921 Results.push_back(Tmp1);
2924 case ISD::GLOBAL_OFFSET_TABLE:
2925 case ISD::GlobalAddress:
2926 case ISD::GlobalTLSAddress:
2927 case ISD::ExternalSymbol:
2928 case ISD::ConstantPool:
2929 case ISD::JumpTable:
2930 case ISD::INTRINSIC_W_CHAIN:
2931 case ISD::INTRINSIC_WO_CHAIN:
2932 case ISD::INTRINSIC_VOID:
2933 // FIXME: Custom lowering for these operations shouldn't return null!
2934 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2935 Results.push_back(SDValue(Node, i));
2939 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
2940 SmallVectorImpl<SDValue> &Results) {
2941 EVT OVT = Node->getValueType(0);
2942 if (Node->getOpcode() == ISD::UINT_TO_FP ||
2943 Node->getOpcode() == ISD::SINT_TO_FP ||
2944 Node->getOpcode() == ISD::SETCC) {
2945 OVT = Node->getOperand(0).getValueType();
2947 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2948 DebugLoc dl = Node->getDebugLoc();
2949 SDValue Tmp1, Tmp2, Tmp3;
2950 switch (Node->getOpcode()) {
2954 // Zero extend the argument.
2955 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
2956 // Perform the larger operation.
2957 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
2958 if (Node->getOpcode() == ISD::CTTZ) {
2959 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2960 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
2961 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
2963 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
2964 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
2965 } else if (Node->getOpcode() == ISD::CTLZ) {
2966 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2967 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
2968 DAG.getConstant(NVT.getSizeInBits() -
2969 OVT.getSizeInBits(), NVT));
2971 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
2974 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
2975 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
2976 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
2977 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
2978 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2979 Results.push_back(Tmp1);
2982 case ISD::FP_TO_UINT:
2983 case ISD::FP_TO_SINT:
2984 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
2985 Node->getOpcode() == ISD::FP_TO_SINT, dl);
2986 Results.push_back(Tmp1);
2988 case ISD::UINT_TO_FP:
2989 case ISD::SINT_TO_FP:
2990 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
2991 Node->getOpcode() == ISD::SINT_TO_FP, dl);
2992 Results.push_back(Tmp1);
2997 unsigned ExtOp, TruncOp;
2998 if (OVT.isVector()) {
2999 ExtOp = ISD::BIT_CONVERT;
3000 TruncOp = ISD::BIT_CONVERT;
3001 } else if (OVT.isInteger()) {
3002 ExtOp = ISD::ANY_EXTEND;
3003 TruncOp = ISD::TRUNCATE;
3005 llvm_report_error("Cannot promote logic operation");
3007 // Promote each of the values to the new type.
3008 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3009 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3010 // Perform the larger operation, then convert back
3011 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3012 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3016 unsigned ExtOp, TruncOp;
3017 if (Node->getValueType(0).isVector()) {
3018 ExtOp = ISD::BIT_CONVERT;
3019 TruncOp = ISD::BIT_CONVERT;
3020 } else if (Node->getValueType(0).isInteger()) {
3021 ExtOp = ISD::ANY_EXTEND;
3022 TruncOp = ISD::TRUNCATE;
3024 ExtOp = ISD::FP_EXTEND;
3025 TruncOp = ISD::FP_ROUND;
3027 Tmp1 = Node->getOperand(0);
3028 // Promote each of the values to the new type.
3029 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3030 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3031 // Perform the larger operation, then round down.
3032 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3033 if (TruncOp != ISD::FP_ROUND)
3034 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3036 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3037 DAG.getIntPtrConstant(0));
3038 Results.push_back(Tmp1);
3041 case ISD::VECTOR_SHUFFLE: {
3042 SmallVector<int, 8> Mask;
3043 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3045 // Cast the two input vectors.
3046 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
3047 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1));
3049 // Convert the shuffle mask to the right # elements.
3050 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3051 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1);
3052 Results.push_back(Tmp1);
3056 unsigned ExtOp = ISD::FP_EXTEND;
3057 if (NVT.isInteger()) {
3058 ISD::CondCode CCCode =
3059 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3060 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3062 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3063 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3064 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3065 Tmp1, Tmp2, Node->getOperand(2)));
3071 // SelectionDAG::Legalize - This is the entry point for the file.
3073 void SelectionDAG::Legalize(bool TypesNeedLegalizing,
3074 CodeGenOpt::Level OptLevel) {
3075 /// run - This is the main entry point to this class.
3077 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG();