1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Target/TargetLowering.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Compiler.h"
25 #include "llvm/ADT/SmallVector.h"
32 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
33 cl::desc("Pop up a window to show dags before legalize"));
35 static const bool ViewLegalizeDAGs = 0;
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class VISIBILITY_HIDDEN SelectionDAGLegalize {
55 // Libcall insertion helpers.
57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
58 /// legalized. We use this to ensure that calls are properly serialized
59 /// against each other, including inserted libcalls.
60 SDOperand LastCALLSEQ_END;
62 /// IsLegalizingCall - This member is used *only* for purposes of providing
63 /// helpful assertions that a libcall isn't created while another call is
64 /// being legalized (which could lead to non-serialized call sequences).
65 bool IsLegalizingCall;
68 Legal, // The target natively supports this operation.
69 Promote, // This operation should be executed in a larger type.
70 Expand // Try to expand this to other ops, otherwise use a libcall.
73 /// ValueTypeActions - This is a bitvector that contains two bits for each
74 /// value type, where the two bits correspond to the LegalizeAction enum.
75 /// This can be queried with "getTypeAction(VT)".
76 TargetLowering::ValueTypeActionImpl ValueTypeActions;
78 /// LegalizedNodes - For nodes that are of legal width, and that have more
79 /// than one use, this map indicates what regularized operand to use. This
80 /// allows us to avoid legalizing the same thing more than once.
81 std::map<SDOperand, SDOperand> LegalizedNodes;
83 /// PromotedNodes - For nodes that are below legal width, and that have more
84 /// than one use, this map indicates what promoted value to use. This allows
85 /// us to avoid promoting the same thing more than once.
86 std::map<SDOperand, SDOperand> PromotedNodes;
88 /// ExpandedNodes - For nodes that need to be expanded this map indicates
89 /// which which operands are the expanded version of the input. This allows
90 /// us to avoid expanding the same node more than once.
91 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
93 /// SplitNodes - For vector nodes that need to be split, this map indicates
94 /// which which operands are the split version of the input. This allows us
95 /// to avoid splitting the same node more than once.
96 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
98 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
99 /// concrete packed types, this contains the mapping of ones we have already
100 /// processed to the result.
101 std::map<SDOperand, SDOperand> PackedNodes;
103 void AddLegalizedOperand(SDOperand From, SDOperand To) {
104 LegalizedNodes.insert(std::make_pair(From, To));
105 // If someone requests legalization of the new node, return itself.
107 LegalizedNodes.insert(std::make_pair(To, To));
109 void AddPromotedOperand(SDOperand From, SDOperand To) {
110 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
111 assert(isNew && "Got into the map somehow?");
112 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
118 SelectionDAGLegalize(SelectionDAG &DAG);
120 /// getTypeAction - Return how we should legalize values of this type, either
121 /// it is already legal or we need to expand it into multiple registers of
122 /// smaller integer type, or we need to promote it to a larger type.
123 LegalizeAction getTypeAction(MVT::ValueType VT) const {
124 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
127 /// isTypeLegal - Return true if this type is legal on this target.
129 bool isTypeLegal(MVT::ValueType VT) const {
130 return getTypeAction(VT) == Legal;
136 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
137 /// appropriate for its type.
138 void HandleOp(SDOperand Op);
140 /// LegalizeOp - We know that the specified value has a legal type.
141 /// Recursively ensure that the operands have legal types, then return the
143 SDOperand LegalizeOp(SDOperand O);
145 /// PromoteOp - Given an operation that produces a value in an invalid type,
146 /// promote it to compute the value into a larger type. The produced value
147 /// will have the correct bits for the low portion of the register, but no
148 /// guarantee is made about the top bits: it may be zero, sign-extended, or
150 SDOperand PromoteOp(SDOperand O);
152 /// ExpandOp - Expand the specified SDOperand into its two component pieces
153 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
154 /// the LegalizeNodes map is filled in for any results that are not expanded,
155 /// the ExpandedNodes map is filled in for any results that are expanded, and
156 /// the Lo/Hi values are returned. This applies to integer types and Vector
158 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
160 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
161 /// two smaller values of MVT::Vector type.
162 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
164 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
165 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
166 /// this is called, we know that PackedVT is the right type for the result and
167 /// we know that this type is legal for the target.
168 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
170 /// isShuffleLegal - Return true if a vector shuffle is legal with the
171 /// specified mask and type. Targets can specify exactly which masks they
172 /// support and the code generator is tasked with not creating illegal masks.
174 /// Note that this will also return true for shuffles that are promoted to a
177 /// If this is a legal shuffle, this method returns the (possibly promoted)
178 /// build_vector Mask. If it's not a legal shuffle, it returns null.
179 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
181 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
182 std::set<SDNode*> &NodesLeadingTo);
184 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
186 SDOperand CreateStackTemporary(MVT::ValueType VT);
188 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
190 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
193 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
194 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
195 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
196 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
198 MVT::ValueType DestVT);
199 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
201 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
204 SDOperand ExpandBSWAP(SDOperand Op);
205 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
206 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
207 SDOperand &Lo, SDOperand &Hi);
208 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
209 SDOperand &Lo, SDOperand &Hi);
211 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
212 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
214 SDOperand getIntPtrConstant(uint64_t Val) {
215 return DAG.getConstant(Val, TLI.getPointerTy());
220 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
221 /// specified mask and type. Targets can specify exactly which masks they
222 /// support and the code generator is tasked with not creating illegal masks.
224 /// Note that this will also return true for shuffles that are promoted to a
226 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
227 SDOperand Mask) const {
228 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
230 case TargetLowering::Legal:
231 case TargetLowering::Custom:
233 case TargetLowering::Promote: {
234 // If this is promoted to a different type, convert the shuffle mask and
235 // ask if it is legal in the promoted type!
236 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
238 // If we changed # elements, change the shuffle mask.
239 unsigned NumEltsGrowth =
240 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
241 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
242 if (NumEltsGrowth > 1) {
243 // Renumber the elements.
244 SmallVector<SDOperand, 8> Ops;
245 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
246 SDOperand InOp = Mask.getOperand(i);
247 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
248 if (InOp.getOpcode() == ISD::UNDEF)
249 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
251 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
252 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
256 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
262 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
265 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
266 /// specified vector opcode.
267 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
269 default: assert(0 && "Don't know how to scalarize this opcode!");
270 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
271 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
272 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
273 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
274 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
275 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
276 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
277 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
281 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
282 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
283 ValueTypeActions(TLI.getValueTypeActions()) {
284 assert(MVT::LAST_VALUETYPE <= 32 &&
285 "Too many value types for ValueTypeActions to hold!");
288 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
289 /// not been visited yet and if all of its operands have already been visited.
290 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
291 std::map<SDNode*, unsigned> &Visited) {
292 if (++Visited[N] != N->getNumOperands())
293 return; // Haven't visited all operands yet
297 if (N->hasOneUse()) { // Tail recurse in common case.
298 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
302 // Now that we have N in, add anything that uses it if all of their operands
304 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
305 ComputeTopDownOrdering(*UI, Order, Visited);
309 void SelectionDAGLegalize::LegalizeDAG() {
310 LastCALLSEQ_END = DAG.getEntryNode();
311 IsLegalizingCall = false;
313 // The legalize process is inherently a bottom-up recursive process (users
314 // legalize their uses before themselves). Given infinite stack space, we
315 // could just start legalizing on the root and traverse the whole graph. In
316 // practice however, this causes us to run out of stack space on large basic
317 // blocks. To avoid this problem, compute an ordering of the nodes where each
318 // node is only legalized after all of its operands are legalized.
319 std::map<SDNode*, unsigned> Visited;
320 std::vector<SDNode*> Order;
322 // Compute ordering from all of the leaves in the graphs, those (like the
323 // entry node) that have no operands.
324 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
325 E = DAG.allnodes_end(); I != E; ++I) {
326 if (I->getNumOperands() == 0) {
328 ComputeTopDownOrdering(I, Order, Visited);
332 assert(Order.size() == Visited.size() &&
334 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
335 "Error: DAG is cyclic!");
338 for (unsigned i = 0, e = Order.size(); i != e; ++i)
339 HandleOp(SDOperand(Order[i], 0));
341 // Finally, it's possible the root changed. Get the new root.
342 SDOperand OldRoot = DAG.getRoot();
343 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
344 DAG.setRoot(LegalizedNodes[OldRoot]);
346 ExpandedNodes.clear();
347 LegalizedNodes.clear();
348 PromotedNodes.clear();
352 // Remove dead nodes now.
353 DAG.RemoveDeadNodes();
357 /// FindCallEndFromCallStart - Given a chained node that is part of a call
358 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
359 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
360 if (Node->getOpcode() == ISD::CALLSEQ_END)
362 if (Node->use_empty())
363 return 0; // No CallSeqEnd
365 // The chain is usually at the end.
366 SDOperand TheChain(Node, Node->getNumValues()-1);
367 if (TheChain.getValueType() != MVT::Other) {
368 // Sometimes it's at the beginning.
369 TheChain = SDOperand(Node, 0);
370 if (TheChain.getValueType() != MVT::Other) {
371 // Otherwise, hunt for it.
372 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
373 if (Node->getValueType(i) == MVT::Other) {
374 TheChain = SDOperand(Node, i);
378 // Otherwise, we walked into a node without a chain.
379 if (TheChain.getValueType() != MVT::Other)
384 for (SDNode::use_iterator UI = Node->use_begin(),
385 E = Node->use_end(); UI != E; ++UI) {
387 // Make sure to only follow users of our token chain.
389 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
390 if (User->getOperand(i) == TheChain)
391 if (SDNode *Result = FindCallEndFromCallStart(User))
397 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
398 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
399 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
400 assert(Node && "Didn't find callseq_start for a call??");
401 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
403 assert(Node->getOperand(0).getValueType() == MVT::Other &&
404 "Node doesn't have a token chain argument!");
405 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
408 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
409 /// see if any uses can reach Dest. If no dest operands can get to dest,
410 /// legalize them, legalize ourself, and return false, otherwise, return true.
412 /// Keep track of the nodes we fine that actually do lead to Dest in
413 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
415 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
416 std::set<SDNode*> &NodesLeadingTo) {
417 if (N == Dest) return true; // N certainly leads to Dest :)
419 // If we've already processed this node and it does lead to Dest, there is no
420 // need to reprocess it.
421 if (NodesLeadingTo.count(N)) return true;
423 // If the first result of this node has been already legalized, then it cannot
425 switch (getTypeAction(N->getValueType(0))) {
427 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
430 if (PromotedNodes.count(SDOperand(N, 0))) return false;
433 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
437 // Okay, this node has not already been legalized. Check and legalize all
438 // operands. If none lead to Dest, then we can legalize this node.
439 bool OperandsLeadToDest = false;
440 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
441 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
442 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
444 if (OperandsLeadToDest) {
445 NodesLeadingTo.insert(N);
449 // Okay, this node looks safe, legalize it and return false.
450 HandleOp(SDOperand(N, 0));
454 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
455 /// appropriate for its type.
456 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
457 switch (getTypeAction(Op.getValueType())) {
458 default: assert(0 && "Bad type action!");
459 case Legal: LegalizeOp(Op); break;
460 case Promote: PromoteOp(Op); break;
462 if (Op.getValueType() != MVT::Vector) {
467 unsigned NumOps = N->getNumOperands();
468 unsigned NumElements =
469 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
470 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
471 MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
472 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
473 // In the common case, this is a legal vector type, convert it to the
474 // packed operation and type now.
475 PackVectorOp(Op, PackedVT);
476 } else if (NumElements == 1) {
477 // Otherwise, if this is a single element vector, convert it to a
479 PackVectorOp(Op, EVT);
481 // Otherwise, this is a multiple element vector that isn't supported.
482 // Split it in half and legalize both parts.
484 SplitVectorOp(Op, X, Y);
492 /// LegalizeOp - We know that the specified value has a legal type.
493 /// Recursively ensure that the operands have legal types, then return the
495 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
496 assert(isTypeLegal(Op.getValueType()) &&
497 "Caller should expand or promote operands that are not legal!");
498 SDNode *Node = Op.Val;
500 // If this operation defines any values that cannot be represented in a
501 // register on this target, make sure to expand or promote them.
502 if (Node->getNumValues() > 1) {
503 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
504 if (getTypeAction(Node->getValueType(i)) != Legal) {
505 HandleOp(Op.getValue(i));
506 assert(LegalizedNodes.count(Op) &&
507 "Handling didn't add legal operands!");
508 return LegalizedNodes[Op];
512 // Note that LegalizeOp may be reentered even from single-use nodes, which
513 // means that we always must cache transformed nodes.
514 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
515 if (I != LegalizedNodes.end()) return I->second;
517 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
518 SDOperand Result = Op;
519 bool isCustom = false;
521 switch (Node->getOpcode()) {
522 case ISD::FrameIndex:
523 case ISD::EntryToken:
525 case ISD::BasicBlock:
526 case ISD::TargetFrameIndex:
527 case ISD::TargetJumpTable:
528 case ISD::TargetConstant:
529 case ISD::TargetConstantFP:
530 case ISD::TargetConstantPool:
531 case ISD::TargetGlobalAddress:
532 case ISD::TargetExternalSymbol:
537 // Primitives must all be legal.
538 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
539 "This must be legal!");
542 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
543 // If this is a target node, legalize it by legalizing the operands then
544 // passing it through.
545 SmallVector<SDOperand, 8> Ops;
546 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
547 Ops.push_back(LegalizeOp(Node->getOperand(i)));
549 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
551 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
552 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
553 return Result.getValue(Op.ResNo);
555 // Otherwise this is an unhandled builtin node. splat.
557 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
559 assert(0 && "Do not know how to legalize this operator!");
561 case ISD::JumpTableRelocBase:
562 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
563 case TargetLowering::Custom:
564 Tmp1 = TLI.LowerOperation(Op, DAG);
565 if (Tmp1.Val) Result = Tmp1;
568 Result = LegalizeOp(Node->getOperand(0));
572 case ISD::GlobalAddress:
573 case ISD::ExternalSymbol:
574 case ISD::ConstantPool:
575 case ISD::JumpTable: // Nothing to do.
576 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
577 default: assert(0 && "This action is not supported yet!");
578 case TargetLowering::Custom:
579 Tmp1 = TLI.LowerOperation(Op, DAG);
580 if (Tmp1.Val) Result = Tmp1;
581 // FALLTHROUGH if the target doesn't want to lower this op after all.
582 case TargetLowering::Legal:
586 case ISD::AssertSext:
587 case ISD::AssertZext:
588 Tmp1 = LegalizeOp(Node->getOperand(0));
589 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
591 case ISD::MERGE_VALUES:
592 // Legalize eliminates MERGE_VALUES nodes.
593 Result = Node->getOperand(Op.ResNo);
595 case ISD::CopyFromReg:
596 Tmp1 = LegalizeOp(Node->getOperand(0));
597 Result = Op.getValue(0);
598 if (Node->getNumValues() == 2) {
599 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
601 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
602 if (Node->getNumOperands() == 3) {
603 Tmp2 = LegalizeOp(Node->getOperand(2));
604 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
606 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
608 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
610 // Since CopyFromReg produces two values, make sure to remember that we
611 // legalized both of them.
612 AddLegalizedOperand(Op.getValue(0), Result);
613 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
614 return Result.getValue(Op.ResNo);
616 MVT::ValueType VT = Op.getValueType();
617 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
618 default: assert(0 && "This action is not supported yet!");
619 case TargetLowering::Expand:
620 if (MVT::isInteger(VT))
621 Result = DAG.getConstant(0, VT);
622 else if (MVT::isFloatingPoint(VT))
623 Result = DAG.getConstantFP(0, VT);
625 assert(0 && "Unknown value type!");
627 case TargetLowering::Legal:
633 case ISD::INTRINSIC_W_CHAIN:
634 case ISD::INTRINSIC_WO_CHAIN:
635 case ISD::INTRINSIC_VOID: {
636 SmallVector<SDOperand, 8> Ops;
637 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
638 Ops.push_back(LegalizeOp(Node->getOperand(i)));
639 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
641 // Allow the target to custom lower its intrinsics if it wants to.
642 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
643 TargetLowering::Custom) {
644 Tmp3 = TLI.LowerOperation(Result, DAG);
645 if (Tmp3.Val) Result = Tmp3;
648 if (Result.Val->getNumValues() == 1) break;
650 // Must have return value and chain result.
651 assert(Result.Val->getNumValues() == 2 &&
652 "Cannot return more than two values!");
654 // Since loads produce two values, make sure to remember that we
655 // legalized both of them.
656 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
657 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
658 return Result.getValue(Op.ResNo);
662 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
663 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
665 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
666 case TargetLowering::Promote:
667 default: assert(0 && "This action is not supported yet!");
668 case TargetLowering::Expand: {
669 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
670 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
671 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
673 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
674 const std::string &FName =
675 cast<StringSDNode>(Node->getOperand(3))->getValue();
676 const std::string &DirName =
677 cast<StringSDNode>(Node->getOperand(4))->getValue();
678 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
680 SmallVector<SDOperand, 8> Ops;
681 Ops.push_back(Tmp1); // chain
682 SDOperand LineOp = Node->getOperand(1);
683 SDOperand ColOp = Node->getOperand(2);
686 Ops.push_back(LineOp); // line #
687 Ops.push_back(ColOp); // col #
688 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
689 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
691 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
692 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
693 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
694 Ops.push_back(DAG.getConstant(ID, MVT::i32));
695 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,&Ops[0],Ops.size());
698 Result = Tmp1; // chain
702 case TargetLowering::Legal:
703 if (Tmp1 != Node->getOperand(0) ||
704 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
705 SmallVector<SDOperand, 8> Ops;
707 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
708 Ops.push_back(Node->getOperand(1)); // line # must be legal.
709 Ops.push_back(Node->getOperand(2)); // col # must be legal.
711 // Otherwise promote them.
712 Ops.push_back(PromoteOp(Node->getOperand(1)));
713 Ops.push_back(PromoteOp(Node->getOperand(2)));
715 Ops.push_back(Node->getOperand(3)); // filename must be legal.
716 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
717 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
724 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
725 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
726 default: assert(0 && "This action is not supported yet!");
727 case TargetLowering::Legal:
728 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
729 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
730 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
731 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
732 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
737 case ISD::DEBUG_LABEL:
738 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
739 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
740 default: assert(0 && "This action is not supported yet!");
741 case TargetLowering::Legal:
742 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
743 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
744 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
750 // We know we don't need to expand constants here, constants only have one
751 // value and we check that it is fine above.
753 // FIXME: Maybe we should handle things like targets that don't support full
754 // 32-bit immediates?
756 case ISD::ConstantFP: {
757 // Spill FP immediates to the constant pool if the target cannot directly
758 // codegen them. Targets often have some immediate values that can be
759 // efficiently generated into an FP register without a load. We explicitly
760 // leave these constants as ConstantFP nodes for the target to deal with.
761 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
763 // Check to see if this FP immediate is already legal.
764 bool isLegal = false;
765 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
766 E = TLI.legal_fpimm_end(); I != E; ++I)
767 if (CFP->isExactlyValue(*I)) {
772 // If this is a legal constant, turn it into a TargetConstantFP node.
774 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
778 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
779 default: assert(0 && "This action is not supported yet!");
780 case TargetLowering::Custom:
781 Tmp3 = TLI.LowerOperation(Result, DAG);
787 case TargetLowering::Expand:
788 // Otherwise we need to spill the constant to memory.
791 // If a FP immediate is precise when represented as a float and if the
792 // target can do an extending load from float to double, we put it into
793 // the constant pool as a float, even if it's is statically typed as a
795 MVT::ValueType VT = CFP->getValueType(0);
796 bool isDouble = VT == MVT::f64;
797 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
798 Type::FloatTy, CFP->getValue());
799 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
800 // Only do this if the target has a native EXTLOAD instruction from
802 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
803 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
808 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
810 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
811 CPIdx, NULL, 0, MVT::f32);
813 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
818 case ISD::TokenFactor:
819 if (Node->getNumOperands() == 2) {
820 Tmp1 = LegalizeOp(Node->getOperand(0));
821 Tmp2 = LegalizeOp(Node->getOperand(1));
822 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
823 } else if (Node->getNumOperands() == 3) {
824 Tmp1 = LegalizeOp(Node->getOperand(0));
825 Tmp2 = LegalizeOp(Node->getOperand(1));
826 Tmp3 = LegalizeOp(Node->getOperand(2));
827 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
829 SmallVector<SDOperand, 8> Ops;
830 // Legalize the operands.
831 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
832 Ops.push_back(LegalizeOp(Node->getOperand(i)));
833 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
837 case ISD::FORMAL_ARGUMENTS:
839 // The only option for this is to custom lower it.
840 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
841 assert(Tmp3.Val && "Target didn't custom lower this node!");
842 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
843 "Lowering call/formal_arguments produced unexpected # results!");
845 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
846 // remember that we legalized all of them, so it doesn't get relegalized.
847 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
848 Tmp1 = LegalizeOp(Tmp3.getValue(i));
851 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
855 case ISD::BUILD_VECTOR:
856 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
857 default: assert(0 && "This action is not supported yet!");
858 case TargetLowering::Custom:
859 Tmp3 = TLI.LowerOperation(Result, DAG);
865 case TargetLowering::Expand:
866 Result = ExpandBUILD_VECTOR(Result.Val);
870 case ISD::INSERT_VECTOR_ELT:
871 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
872 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
873 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
874 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
876 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
877 Node->getValueType(0))) {
878 default: assert(0 && "This action is not supported yet!");
879 case TargetLowering::Legal:
881 case TargetLowering::Custom:
882 Tmp3 = TLI.LowerOperation(Result, DAG);
888 case TargetLowering::Expand: {
889 // If the insert index is a constant, codegen this as a scalar_to_vector,
890 // then a shuffle that inserts it into the right position in the vector.
891 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
892 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
893 Tmp1.getValueType(), Tmp2);
895 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
896 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
897 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT);
899 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
900 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
902 SmallVector<SDOperand, 8> ShufOps;
903 for (unsigned i = 0; i != NumElts; ++i) {
904 if (i != InsertPos->getValue())
905 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
907 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
909 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
910 &ShufOps[0], ShufOps.size());
912 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
913 Tmp1, ScVec, ShufMask);
914 Result = LegalizeOp(Result);
918 // If the target doesn't support this, we have to spill the input vector
919 // to a temporary stack slot, update the element, then reload it. This is
920 // badness. We could also load the value into a vector register (either
921 // with a "move to register" or "extload into register" instruction, then
922 // permute it into place, if the idx is a constant and if the idx is
923 // supported by the target.
924 MVT::ValueType VT = Tmp1.getValueType();
925 MVT::ValueType EltVT = Tmp2.getValueType();
926 MVT::ValueType IdxVT = Tmp3.getValueType();
927 MVT::ValueType PtrVT = TLI.getPointerTy();
928 SDOperand StackPtr = CreateStackTemporary(VT);
930 SDOperand Ch = DAG.getStore(DAG.getEntryNode(),
931 Tmp1, StackPtr, DAG.getSrcValue(NULL));
933 // Truncate or zero extend offset to target pointer type.
934 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
935 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
936 // Add the offset to the index.
937 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
938 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
939 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
940 // Store the scalar value.
941 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, DAG.getSrcValue(NULL));
942 // Load the updated vector.
943 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
948 case ISD::SCALAR_TO_VECTOR:
949 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
950 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
954 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
955 Result = DAG.UpdateNodeOperands(Result, Tmp1);
956 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
957 Node->getValueType(0))) {
958 default: assert(0 && "This action is not supported yet!");
959 case TargetLowering::Legal:
961 case TargetLowering::Custom:
962 Tmp3 = TLI.LowerOperation(Result, DAG);
968 case TargetLowering::Expand:
969 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
973 case ISD::VECTOR_SHUFFLE:
974 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
975 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
976 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
978 // Allow targets to custom lower the SHUFFLEs they support.
979 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
980 default: assert(0 && "Unknown operation action!");
981 case TargetLowering::Legal:
982 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
983 "vector shuffle should not be created if not legal!");
985 case TargetLowering::Custom:
986 Tmp3 = TLI.LowerOperation(Result, DAG);
992 case TargetLowering::Expand: {
993 MVT::ValueType VT = Node->getValueType(0);
994 MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
995 MVT::ValueType PtrVT = TLI.getPointerTy();
996 SDOperand Mask = Node->getOperand(2);
997 unsigned NumElems = Mask.getNumOperands();
998 SmallVector<SDOperand,8> Ops;
999 for (unsigned i = 0; i != NumElems; ++i) {
1000 SDOperand Arg = Mask.getOperand(i);
1001 if (Arg.getOpcode() == ISD::UNDEF) {
1002 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1004 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1005 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1007 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1008 DAG.getConstant(Idx, PtrVT)));
1010 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1011 DAG.getConstant(Idx - NumElems, PtrVT)));
1014 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1017 case TargetLowering::Promote: {
1018 // Change base type to a different vector type.
1019 MVT::ValueType OVT = Node->getValueType(0);
1020 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1022 // Cast the two input vectors.
1023 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1024 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1026 // Convert the shuffle mask to the right # elements.
1027 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1028 assert(Tmp3.Val && "Shuffle not legal?");
1029 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1030 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1036 case ISD::EXTRACT_VECTOR_ELT:
1037 Tmp1 = LegalizeOp(Node->getOperand(0));
1038 Tmp2 = LegalizeOp(Node->getOperand(1));
1039 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1041 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
1042 Tmp1.getValueType())) {
1043 default: assert(0 && "This action is not supported yet!");
1044 case TargetLowering::Legal:
1046 case TargetLowering::Custom:
1047 Tmp3 = TLI.LowerOperation(Result, DAG);
1053 case TargetLowering::Expand:
1054 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1059 case ISD::VEXTRACT_VECTOR_ELT:
1060 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
1063 case ISD::CALLSEQ_START: {
1064 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1066 // Recursively Legalize all of the inputs of the call end that do not lead
1067 // to this call start. This ensures that any libcalls that need be inserted
1068 // are inserted *before* the CALLSEQ_START.
1069 {std::set<SDNode*> NodesLeadingTo;
1070 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1071 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1075 // Now that we legalized all of the inputs (which may have inserted
1076 // libcalls) create the new CALLSEQ_START node.
1077 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1079 // Merge in the last call, to ensure that this call start after the last
1081 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1082 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1083 Tmp1 = LegalizeOp(Tmp1);
1086 // Do not try to legalize the target-specific arguments (#1+).
1087 if (Tmp1 != Node->getOperand(0)) {
1088 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1090 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1093 // Remember that the CALLSEQ_START is legalized.
1094 AddLegalizedOperand(Op.getValue(0), Result);
1095 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1096 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1098 // Now that the callseq_start and all of the non-call nodes above this call
1099 // sequence have been legalized, legalize the call itself. During this
1100 // process, no libcalls can/will be inserted, guaranteeing that no calls
1102 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1103 SDOperand InCallSEQ = LastCALLSEQ_END;
1104 // Note that we are selecting this call!
1105 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1106 IsLegalizingCall = true;
1108 // Legalize the call, starting from the CALLSEQ_END.
1109 LegalizeOp(LastCALLSEQ_END);
1110 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1113 case ISD::CALLSEQ_END:
1114 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1115 // will cause this node to be legalized as well as handling libcalls right.
1116 if (LastCALLSEQ_END.Val != Node) {
1117 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1118 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1119 assert(I != LegalizedNodes.end() &&
1120 "Legalizing the call start should have legalized this node!");
1124 // Otherwise, the call start has been legalized and everything is going
1125 // according to plan. Just legalize ourselves normally here.
1126 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1127 // Do not try to legalize the target-specific arguments (#1+), except for
1128 // an optional flag input.
1129 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1130 if (Tmp1 != Node->getOperand(0)) {
1131 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1133 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1136 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1137 if (Tmp1 != Node->getOperand(0) ||
1138 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1139 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1142 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1145 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1146 // This finishes up call legalization.
1147 IsLegalizingCall = false;
1149 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1150 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1151 if (Node->getNumValues() == 2)
1152 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1153 return Result.getValue(Op.ResNo);
1154 case ISD::DYNAMIC_STACKALLOC: {
1155 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1156 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1157 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1158 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1160 Tmp1 = Result.getValue(0);
1161 Tmp2 = Result.getValue(1);
1162 switch (TLI.getOperationAction(Node->getOpcode(),
1163 Node->getValueType(0))) {
1164 default: assert(0 && "This action is not supported yet!");
1165 case TargetLowering::Expand: {
1166 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1167 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1168 " not tell us which reg is the stack pointer!");
1169 SDOperand Chain = Tmp1.getOperand(0);
1170 SDOperand Size = Tmp2.getOperand(1);
1171 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1172 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1173 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1174 Tmp1 = LegalizeOp(Tmp1);
1175 Tmp2 = LegalizeOp(Tmp2);
1178 case TargetLowering::Custom:
1179 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1181 Tmp1 = LegalizeOp(Tmp3);
1182 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1185 case TargetLowering::Legal:
1188 // Since this op produce two values, make sure to remember that we
1189 // legalized both of them.
1190 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1191 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1192 return Op.ResNo ? Tmp2 : Tmp1;
1194 case ISD::INLINEASM: {
1195 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1196 bool Changed = false;
1197 // Legalize all of the operands of the inline asm, in case they are nodes
1198 // that need to be expanded or something. Note we skip the asm string and
1199 // all of the TargetConstant flags.
1200 SDOperand Op = LegalizeOp(Ops[0]);
1201 Changed = Op != Ops[0];
1204 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1205 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1206 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1207 for (++i; NumVals; ++i, --NumVals) {
1208 SDOperand Op = LegalizeOp(Ops[i]);
1217 Op = LegalizeOp(Ops.back());
1218 Changed |= Op != Ops.back();
1223 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1225 // INLINE asm returns a chain and flag, make sure to add both to the map.
1226 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1227 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1228 return Result.getValue(Op.ResNo);
1231 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1232 // Ensure that libcalls are emitted before a branch.
1233 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1234 Tmp1 = LegalizeOp(Tmp1);
1235 LastCALLSEQ_END = DAG.getEntryNode();
1237 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1240 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1241 // Ensure that libcalls are emitted before a branch.
1242 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1243 Tmp1 = LegalizeOp(Tmp1);
1244 LastCALLSEQ_END = DAG.getEntryNode();
1246 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1247 default: assert(0 && "Indirect target must be legal type (pointer)!");
1249 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1252 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1255 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1256 // Ensure that libcalls are emitted before a return.
1257 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1258 Tmp1 = LegalizeOp(Tmp1);
1259 LastCALLSEQ_END = DAG.getEntryNode();
1261 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1262 case Expand: assert(0 && "It's impossible to expand bools");
1264 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1267 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1271 // Basic block destination (Op#2) is always legal.
1272 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1274 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1275 default: assert(0 && "This action is not supported yet!");
1276 case TargetLowering::Legal: break;
1277 case TargetLowering::Custom:
1278 Tmp1 = TLI.LowerOperation(Result, DAG);
1279 if (Tmp1.Val) Result = Tmp1;
1281 case TargetLowering::Expand:
1282 // Expand brcond's setcc into its constituent parts and create a BR_CC
1284 if (Tmp2.getOpcode() == ISD::SETCC) {
1285 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1286 Tmp2.getOperand(0), Tmp2.getOperand(1),
1287 Node->getOperand(2));
1289 // Make sure the condition is either zero or one. It may have been
1290 // promoted from something else.
1291 unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType());
1292 if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1))
1293 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1295 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1296 DAG.getCondCode(ISD::SETNE), Tmp2,
1297 DAG.getConstant(0, Tmp2.getValueType()),
1298 Node->getOperand(2));
1304 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1305 // Ensure that libcalls are emitted before a branch.
1306 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1307 Tmp1 = LegalizeOp(Tmp1);
1308 LastCALLSEQ_END = DAG.getEntryNode();
1310 Tmp2 = Node->getOperand(2); // LHS
1311 Tmp3 = Node->getOperand(3); // RHS
1312 Tmp4 = Node->getOperand(1); // CC
1314 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1316 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1317 // the LHS is a legal SETCC itself. In this case, we need to compare
1318 // the result against zero to select between true and false values.
1319 if (Tmp3.Val == 0) {
1320 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1321 Tmp4 = DAG.getCondCode(ISD::SETNE);
1324 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1325 Node->getOperand(4));
1327 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1328 default: assert(0 && "Unexpected action for BR_CC!");
1329 case TargetLowering::Legal: break;
1330 case TargetLowering::Custom:
1331 Tmp4 = TLI.LowerOperation(Result, DAG);
1332 if (Tmp4.Val) Result = Tmp4;
1337 LoadSDNode *LD = cast<LoadSDNode>(Node);
1338 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1339 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1341 ISD::LoadExtType ExtType = LD->getExtensionType();
1342 if (ExtType == ISD::NON_EXTLOAD) {
1343 MVT::ValueType VT = Node->getValueType(0);
1344 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1345 Tmp3 = Result.getValue(0);
1346 Tmp4 = Result.getValue(1);
1348 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1349 default: assert(0 && "This action is not supported yet!");
1350 case TargetLowering::Legal: break;
1351 case TargetLowering::Custom:
1352 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1354 Tmp3 = LegalizeOp(Tmp1);
1355 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1358 case TargetLowering::Promote: {
1359 // Only promote a load of vector type to another.
1360 assert(MVT::isVector(VT) && "Cannot promote this load!");
1361 // Change base type to a different vector type.
1362 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1364 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1365 LD->getSrcValueOffset());
1366 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1367 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1371 // Since loads produce two values, make sure to remember that we
1372 // legalized both of them.
1373 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1374 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1375 return Op.ResNo ? Tmp4 : Tmp3;
1377 MVT::ValueType SrcVT = LD->getLoadVT();
1378 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1379 default: assert(0 && "This action is not supported yet!");
1380 case TargetLowering::Promote:
1381 assert(SrcVT == MVT::i1 &&
1382 "Can only promote extending LOAD from i1 -> i8!");
1383 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1384 LD->getSrcValue(), LD->getSrcValueOffset(),
1386 Tmp1 = Result.getValue(0);
1387 Tmp2 = Result.getValue(1);
1389 case TargetLowering::Custom:
1392 case TargetLowering::Legal:
1393 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1394 Tmp1 = Result.getValue(0);
1395 Tmp2 = Result.getValue(1);
1398 Tmp3 = TLI.LowerOperation(Result, DAG);
1400 Tmp1 = LegalizeOp(Tmp3);
1401 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1405 case TargetLowering::Expand:
1406 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1407 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1408 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1409 LD->getSrcValueOffset());
1410 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1411 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1412 Tmp2 = LegalizeOp(Load.getValue(1));
1415 assert(ExtType != ISD::EXTLOAD && "EXTLOAD should always be supported!");
1416 // Turn the unsupported load into an EXTLOAD followed by an explicit
1417 // zero/sign extend inreg.
1418 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1419 Tmp1, Tmp2, LD->getSrcValue(),
1420 LD->getSrcValueOffset(), SrcVT);
1422 if (ExtType == ISD::SEXTLOAD)
1423 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1424 Result, DAG.getValueType(SrcVT));
1426 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1427 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1428 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1431 // Since loads produce two values, make sure to remember that we legalized
1433 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1434 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1435 return Op.ResNo ? Tmp2 : Tmp1;
1438 case ISD::EXTRACT_ELEMENT: {
1439 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1440 switch (getTypeAction(OpTy)) {
1441 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1443 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1445 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1446 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1447 TLI.getShiftAmountTy()));
1448 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1451 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1452 Node->getOperand(0));
1456 // Get both the low and high parts.
1457 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1458 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1459 Result = Tmp2; // 1 -> Hi
1461 Result = Tmp1; // 0 -> Lo
1467 case ISD::CopyToReg:
1468 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1470 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1471 "Register type must be legal!");
1472 // Legalize the incoming value (must be a legal type).
1473 Tmp2 = LegalizeOp(Node->getOperand(2));
1474 if (Node->getNumValues() == 1) {
1475 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1477 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1478 if (Node->getNumOperands() == 4) {
1479 Tmp3 = LegalizeOp(Node->getOperand(3));
1480 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1483 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1486 // Since this produces two values, make sure to remember that we legalized
1488 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1489 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1495 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1497 // Ensure that libcalls are emitted before a return.
1498 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1499 Tmp1 = LegalizeOp(Tmp1);
1500 LastCALLSEQ_END = DAG.getEntryNode();
1502 switch (Node->getNumOperands()) {
1504 Tmp2 = Node->getOperand(1);
1505 Tmp3 = Node->getOperand(2); // Signness
1506 switch (getTypeAction(Tmp2.getValueType())) {
1508 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1511 if (Tmp2.getValueType() != MVT::Vector) {
1513 ExpandOp(Tmp2, Lo, Hi);
1514 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1515 Result = LegalizeOp(Result);
1517 SDNode *InVal = Tmp2.Val;
1519 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1520 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1522 // Figure out if there is a Packed type corresponding to this Vector
1523 // type. If so, convert to the packed type.
1524 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1525 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1526 // Turn this into a return of the packed type.
1527 Tmp2 = PackVectorOp(Tmp2, TVT);
1528 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1529 } else if (NumElems == 1) {
1530 // Turn this into a return of the scalar type.
1531 Tmp2 = PackVectorOp(Tmp2, EVT);
1532 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1534 // FIXME: Returns of gcc generic vectors smaller than a legal type
1535 // should be returned in integer registers!
1537 // The scalarized value type may not be legal, e.g. it might require
1538 // promotion or expansion. Relegalize the return.
1539 Result = LegalizeOp(Result);
1541 // FIXME: Returns of gcc generic vectors larger than a legal vector
1542 // type should be returned by reference!
1544 SplitVectorOp(Tmp2, Lo, Hi);
1545 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1546 Result = LegalizeOp(Result);
1551 Tmp2 = PromoteOp(Node->getOperand(1));
1552 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1553 Result = LegalizeOp(Result);
1558 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1560 default: { // ret <values>
1561 SmallVector<SDOperand, 8> NewValues;
1562 NewValues.push_back(Tmp1);
1563 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1564 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1566 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1567 NewValues.push_back(Node->getOperand(i+1));
1571 assert(Node->getOperand(i).getValueType() != MVT::Vector &&
1572 "FIXME: TODO: implement returning non-legal vector types!");
1573 ExpandOp(Node->getOperand(i), Lo, Hi);
1574 NewValues.push_back(Lo);
1575 NewValues.push_back(Node->getOperand(i+1));
1576 NewValues.push_back(Hi);
1577 NewValues.push_back(Node->getOperand(i+1));
1581 assert(0 && "Can't promote multiple return value yet!");
1584 if (NewValues.size() == Node->getNumOperands())
1585 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1587 Result = DAG.getNode(ISD::RET, MVT::Other,
1588 &NewValues[0], NewValues.size());
1593 if (Result.getOpcode() == ISD::RET) {
1594 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1595 default: assert(0 && "This action is not supported yet!");
1596 case TargetLowering::Legal: break;
1597 case TargetLowering::Custom:
1598 Tmp1 = TLI.LowerOperation(Result, DAG);
1599 if (Tmp1.Val) Result = Tmp1;
1605 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1606 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1608 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1609 // FIXME: We shouldn't do this for TargetConstantFP's.
1610 // FIXME: move this to the DAG Combiner!
1611 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1612 if (CFP->getValueType(0) == MVT::f32) {
1613 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1615 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1616 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1618 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, Node->getOperand(3));
1622 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1624 Tmp3 = LegalizeOp(Node->getOperand(1));
1625 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1626 Node->getOperand(3));
1628 MVT::ValueType VT = Tmp3.getValueType();
1629 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1630 default: assert(0 && "This action is not supported yet!");
1631 case TargetLowering::Legal: break;
1632 case TargetLowering::Custom:
1633 Tmp1 = TLI.LowerOperation(Result, DAG);
1634 if (Tmp1.Val) Result = Tmp1;
1636 case TargetLowering::Promote:
1637 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1638 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1639 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1640 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1641 Node->getOperand(3));
1647 // Truncate the value and store the result.
1648 Tmp3 = PromoteOp(Node->getOperand(1));
1649 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1650 Node->getOperand(3),
1651 DAG.getValueType(Node->getOperand(1).getValueType()));
1655 unsigned IncrementSize = 0;
1658 // If this is a vector type, then we have to calculate the increment as
1659 // the product of the element size in bytes, and the number of elements
1660 // in the high half of the vector.
1661 if (Node->getOperand(1).getValueType() == MVT::Vector) {
1662 SDNode *InVal = Node->getOperand(1).Val;
1664 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1665 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1667 // Figure out if there is a Packed type corresponding to this Vector
1668 // type. If so, convert to the packed type.
1669 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1670 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1671 // Turn this into a normal store of the packed type.
1672 Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1673 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1674 Node->getOperand(3));
1675 Result = LegalizeOp(Result);
1677 } else if (NumElems == 1) {
1678 // Turn this into a normal store of the scalar type.
1679 Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1680 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1681 Node->getOperand(3));
1682 // The scalarized value type may not be legal, e.g. it might require
1683 // promotion or expansion. Relegalize the scalar store.
1684 Result = LegalizeOp(Result);
1687 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1688 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1691 ExpandOp(Node->getOperand(1), Lo, Hi);
1692 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1694 if (!TLI.isLittleEndian())
1698 Lo = DAG.getStore(Tmp1, Lo, Tmp2, Node->getOperand(3));
1699 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1700 getIntPtrConstant(IncrementSize));
1701 assert(isTypeLegal(Tmp2.getValueType()) &&
1702 "Pointers must be legal!");
1703 // FIXME: This sets the srcvalue of both halves to be the same, which is
1705 Hi = DAG.getStore(Tmp1, Hi, Tmp2, Node->getOperand(3));
1706 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1712 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1713 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1715 case ISD::STACKSAVE:
1716 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1717 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1718 Tmp1 = Result.getValue(0);
1719 Tmp2 = Result.getValue(1);
1721 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1722 default: assert(0 && "This action is not supported yet!");
1723 case TargetLowering::Legal: break;
1724 case TargetLowering::Custom:
1725 Tmp3 = TLI.LowerOperation(Result, DAG);
1727 Tmp1 = LegalizeOp(Tmp3);
1728 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1731 case TargetLowering::Expand:
1732 // Expand to CopyFromReg if the target set
1733 // StackPointerRegisterToSaveRestore.
1734 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1735 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1736 Node->getValueType(0));
1737 Tmp2 = Tmp1.getValue(1);
1739 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1740 Tmp2 = Node->getOperand(0);
1745 // Since stacksave produce two values, make sure to remember that we
1746 // legalized both of them.
1747 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1748 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1749 return Op.ResNo ? Tmp2 : Tmp1;
1751 case ISD::STACKRESTORE:
1752 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1753 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1754 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1756 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1757 default: assert(0 && "This action is not supported yet!");
1758 case TargetLowering::Legal: break;
1759 case TargetLowering::Custom:
1760 Tmp1 = TLI.LowerOperation(Result, DAG);
1761 if (Tmp1.Val) Result = Tmp1;
1763 case TargetLowering::Expand:
1764 // Expand to CopyToReg if the target set
1765 // StackPointerRegisterToSaveRestore.
1766 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1767 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1775 case ISD::READCYCLECOUNTER:
1776 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1777 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1779 // Since rdcc produce two values, make sure to remember that we legalized
1781 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1782 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1785 case ISD::TRUNCSTORE: {
1786 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1787 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1789 assert(isTypeLegal(Node->getOperand(1).getValueType()) &&
1790 "Cannot handle illegal TRUNCSTORE yet!");
1791 Tmp2 = LegalizeOp(Node->getOperand(1));
1793 // The only promote case we handle is TRUNCSTORE:i1 X into
1794 // -> TRUNCSTORE:i8 (and X, 1)
1795 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1796 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1797 TargetLowering::Promote) {
1798 // Promote the bool to a mask then store.
1799 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1800 DAG.getConstant(1, Tmp2.getValueType()));
1801 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1802 Node->getOperand(3), DAG.getValueType(MVT::i8));
1804 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1805 Tmp3 != Node->getOperand(2)) {
1806 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
1807 Node->getOperand(3), Node->getOperand(4));
1810 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT();
1811 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) {
1812 default: assert(0 && "This action is not supported yet!");
1813 case TargetLowering::Legal: break;
1814 case TargetLowering::Custom:
1815 Tmp1 = TLI.LowerOperation(Result, DAG);
1816 if (Tmp1.Val) Result = Tmp1;
1822 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1823 case Expand: assert(0 && "It's impossible to expand bools");
1825 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1828 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1831 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1832 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1834 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1836 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1837 default: assert(0 && "This action is not supported yet!");
1838 case TargetLowering::Legal: break;
1839 case TargetLowering::Custom: {
1840 Tmp1 = TLI.LowerOperation(Result, DAG);
1841 if (Tmp1.Val) Result = Tmp1;
1844 case TargetLowering::Expand:
1845 if (Tmp1.getOpcode() == ISD::SETCC) {
1846 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1848 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1850 // Make sure the condition is either zero or one. It may have been
1851 // promoted from something else.
1852 unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType());
1853 if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1))
1854 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1855 Result = DAG.getSelectCC(Tmp1,
1856 DAG.getConstant(0, Tmp1.getValueType()),
1857 Tmp2, Tmp3, ISD::SETNE);
1860 case TargetLowering::Promote: {
1861 MVT::ValueType NVT =
1862 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1863 unsigned ExtOp, TruncOp;
1864 if (MVT::isVector(Tmp2.getValueType())) {
1865 ExtOp = ISD::BIT_CONVERT;
1866 TruncOp = ISD::BIT_CONVERT;
1867 } else if (MVT::isInteger(Tmp2.getValueType())) {
1868 ExtOp = ISD::ANY_EXTEND;
1869 TruncOp = ISD::TRUNCATE;
1871 ExtOp = ISD::FP_EXTEND;
1872 TruncOp = ISD::FP_ROUND;
1874 // Promote each of the values to the new type.
1875 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1876 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1877 // Perform the larger operation, then round down.
1878 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1879 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1884 case ISD::SELECT_CC: {
1885 Tmp1 = Node->getOperand(0); // LHS
1886 Tmp2 = Node->getOperand(1); // RHS
1887 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1888 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1889 SDOperand CC = Node->getOperand(4);
1891 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
1893 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1894 // the LHS is a legal SETCC itself. In this case, we need to compare
1895 // the result against zero to select between true and false values.
1896 if (Tmp2.Val == 0) {
1897 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1898 CC = DAG.getCondCode(ISD::SETNE);
1900 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
1902 // Everything is legal, see if we should expand this op or something.
1903 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
1904 default: assert(0 && "This action is not supported yet!");
1905 case TargetLowering::Legal: break;
1906 case TargetLowering::Custom:
1907 Tmp1 = TLI.LowerOperation(Result, DAG);
1908 if (Tmp1.Val) Result = Tmp1;
1914 Tmp1 = Node->getOperand(0);
1915 Tmp2 = Node->getOperand(1);
1916 Tmp3 = Node->getOperand(2);
1917 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
1919 // If we had to Expand the SetCC operands into a SELECT node, then it may
1920 // not always be possible to return a true LHS & RHS. In this case, just
1921 // return the value we legalized, returned in the LHS
1922 if (Tmp2.Val == 0) {
1927 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
1928 default: assert(0 && "Cannot handle this action for SETCC yet!");
1929 case TargetLowering::Custom:
1932 case TargetLowering::Legal:
1933 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1935 Tmp3 = TLI.LowerOperation(Result, DAG);
1936 if (Tmp3.Val) Result = Tmp3;
1939 case TargetLowering::Promote: {
1940 // First step, figure out the appropriate operation to use.
1941 // Allow SETCC to not be supported for all legal data types
1942 // Mostly this targets FP
1943 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1944 MVT::ValueType OldVT = NewInTy;
1946 // Scan for the appropriate larger type to use.
1948 NewInTy = (MVT::ValueType)(NewInTy+1);
1950 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1951 "Fell off of the edge of the integer world");
1952 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1953 "Fell off of the edge of the floating point world");
1955 // If the target supports SETCC of this type, use it.
1956 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
1959 if (MVT::isInteger(NewInTy))
1960 assert(0 && "Cannot promote Legal Integer SETCC yet");
1962 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1963 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
1965 Tmp1 = LegalizeOp(Tmp1);
1966 Tmp2 = LegalizeOp(Tmp2);
1967 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1968 Result = LegalizeOp(Result);
1971 case TargetLowering::Expand:
1972 // Expand a setcc node into a select_cc of the same condition, lhs, and
1973 // rhs that selects between const 1 (true) and const 0 (false).
1974 MVT::ValueType VT = Node->getValueType(0);
1975 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1976 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1977 Node->getOperand(2));
1983 case ISD::MEMMOVE: {
1984 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1985 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1987 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1988 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1989 case Expand: assert(0 && "Cannot expand a byte!");
1991 Tmp3 = LegalizeOp(Node->getOperand(2));
1994 Tmp3 = PromoteOp(Node->getOperand(2));
1998 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2002 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2004 // Length is too big, just take the lo-part of the length.
2006 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
2010 Tmp4 = LegalizeOp(Node->getOperand(3));
2013 Tmp4 = PromoteOp(Node->getOperand(3));
2018 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2019 case Expand: assert(0 && "Cannot expand this yet!");
2021 Tmp5 = LegalizeOp(Node->getOperand(4));
2024 Tmp5 = PromoteOp(Node->getOperand(4));
2028 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2029 default: assert(0 && "This action not implemented for this operation!");
2030 case TargetLowering::Custom:
2033 case TargetLowering::Legal:
2034 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2036 Tmp1 = TLI.LowerOperation(Result, DAG);
2037 if (Tmp1.Val) Result = Tmp1;
2040 case TargetLowering::Expand: {
2041 // Otherwise, the target does not support this operation. Lower the
2042 // operation to an explicit libcall as appropriate.
2043 MVT::ValueType IntPtr = TLI.getPointerTy();
2044 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2045 std::vector<std::pair<SDOperand, const Type*> > Args;
2047 const char *FnName = 0;
2048 if (Node->getOpcode() == ISD::MEMSET) {
2049 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2050 // Extend the (previously legalized) ubyte argument to be an int value
2052 if (Tmp3.getValueType() > MVT::i32)
2053 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2055 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2056 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
2057 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2060 } else if (Node->getOpcode() == ISD::MEMCPY ||
2061 Node->getOpcode() == ISD::MEMMOVE) {
2062 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2063 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
2064 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2065 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2067 assert(0 && "Unknown op!");
2070 std::pair<SDOperand,SDOperand> CallResult =
2071 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
2072 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2073 Result = CallResult.second;
2080 case ISD::SHL_PARTS:
2081 case ISD::SRA_PARTS:
2082 case ISD::SRL_PARTS: {
2083 SmallVector<SDOperand, 8> Ops;
2084 bool Changed = false;
2085 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2086 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2087 Changed |= Ops.back() != Node->getOperand(i);
2090 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2092 switch (TLI.getOperationAction(Node->getOpcode(),
2093 Node->getValueType(0))) {
2094 default: assert(0 && "This action is not supported yet!");
2095 case TargetLowering::Legal: break;
2096 case TargetLowering::Custom:
2097 Tmp1 = TLI.LowerOperation(Result, DAG);
2099 SDOperand Tmp2, RetVal(0, 0);
2100 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2101 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2102 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2106 assert(RetVal.Val && "Illegal result number");
2112 // Since these produce multiple values, make sure to remember that we
2113 // legalized all of them.
2114 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2115 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2116 return Result.getValue(Op.ResNo);
2137 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2138 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2139 case Expand: assert(0 && "Not possible");
2141 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2144 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2148 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2150 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2151 default: assert(0 && "BinOp legalize operation not supported");
2152 case TargetLowering::Legal: break;
2153 case TargetLowering::Custom:
2154 Tmp1 = TLI.LowerOperation(Result, DAG);
2155 if (Tmp1.Val) Result = Tmp1;
2157 case TargetLowering::Expand: {
2158 if (Node->getValueType(0) == MVT::i32) {
2159 switch (Node->getOpcode()) {
2160 default: assert(0 && "Do not know how to expand this integer BinOp!");
2163 const char *FnName = Node->getOpcode() == ISD::UDIV
2164 ? "__udivsi3" : "__divsi3";
2166 Result = ExpandLibCall(FnName, Node, Dummy);
2171 assert(MVT::isVector(Node->getValueType(0)) &&
2172 "Cannot expand this binary operator!");
2173 // Expand the operation into a bunch of nasty scalar code.
2174 SmallVector<SDOperand, 8> Ops;
2175 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
2176 MVT::ValueType PtrVT = TLI.getPointerTy();
2177 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2179 SDOperand Idx = DAG.getConstant(i, PtrVT);
2180 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2181 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2182 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2184 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2185 &Ops[0], Ops.size());
2188 case TargetLowering::Promote: {
2189 switch (Node->getOpcode()) {
2190 default: assert(0 && "Do not know how to promote this BinOp!");
2194 MVT::ValueType OVT = Node->getValueType(0);
2195 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2196 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2197 // Bit convert each of the values to the new type.
2198 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2199 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2200 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2201 // Bit convert the result back the original type.
2202 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2210 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2211 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2212 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2213 case Expand: assert(0 && "Not possible");
2215 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2218 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2222 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2224 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2225 default: assert(0 && "Operation not supported");
2226 case TargetLowering::Custom:
2227 Tmp1 = TLI.LowerOperation(Result, DAG);
2228 if (Tmp1.Val) Result = Tmp1;
2230 case TargetLowering::Legal: break;
2231 case TargetLowering::Expand:
2232 // If this target supports fabs/fneg natively, do this efficiently.
2233 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
2234 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
2235 // Get the sign bit of the RHS.
2236 MVT::ValueType IVT =
2237 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2238 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2239 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2240 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2241 // Get the absolute value of the result.
2242 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2243 // Select between the nabs and abs value based on the sign bit of
2245 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2246 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2249 Result = LegalizeOp(Result);
2253 // Otherwise, do bitwise ops!
2255 // copysign -> copysignf/copysign libcall.
2257 if (Node->getValueType(0) == MVT::f32) {
2258 FnName = "copysignf";
2259 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type.
2260 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2261 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2));
2263 FnName = "copysign";
2264 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type.
2265 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2266 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2));
2269 Result = ExpandLibCall(FnName, Node, Dummy);
2276 Tmp1 = LegalizeOp(Node->getOperand(0));
2277 Tmp2 = LegalizeOp(Node->getOperand(1));
2278 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2279 // Since this produces two values, make sure to remember that we legalized
2281 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2282 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2287 Tmp1 = LegalizeOp(Node->getOperand(0));
2288 Tmp2 = LegalizeOp(Node->getOperand(1));
2289 Tmp3 = LegalizeOp(Node->getOperand(2));
2290 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2291 // Since this produces two values, make sure to remember that we legalized
2293 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2294 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2297 case ISD::BUILD_PAIR: {
2298 MVT::ValueType PairTy = Node->getValueType(0);
2299 // TODO: handle the case where the Lo and Hi operands are not of legal type
2300 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2301 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2302 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2303 case TargetLowering::Promote:
2304 case TargetLowering::Custom:
2305 assert(0 && "Cannot promote/custom this yet!");
2306 case TargetLowering::Legal:
2307 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2308 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2310 case TargetLowering::Expand:
2311 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2312 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2313 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2314 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2315 TLI.getShiftAmountTy()));
2316 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2325 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2326 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2328 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2329 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2330 case TargetLowering::Custom:
2333 case TargetLowering::Legal:
2334 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2336 Tmp1 = TLI.LowerOperation(Result, DAG);
2337 if (Tmp1.Val) Result = Tmp1;
2340 case TargetLowering::Expand:
2341 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2342 if (MVT::isInteger(Node->getValueType(0))) {
2343 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2344 TargetLowering::Legal) {
2346 MVT::ValueType VT = Node->getValueType(0);
2347 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2348 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2349 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2351 assert(Node->getValueType(0) == MVT::i32 &&
2352 "Cannot expand this binary operator!");
2353 const char *FnName = Node->getOpcode() == ISD::UREM
2354 ? "__umodsi3" : "__modsi3";
2356 Result = ExpandLibCall(FnName, Node, Dummy);
2359 // Floating point mod -> fmod libcall.
2360 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
2362 Result = ExpandLibCall(FnName, Node, Dummy);
2368 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2369 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2371 MVT::ValueType VT = Node->getValueType(0);
2372 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2373 default: assert(0 && "This action is not supported yet!");
2374 case TargetLowering::Custom:
2377 case TargetLowering::Legal:
2378 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2379 Result = Result.getValue(0);
2380 Tmp1 = Result.getValue(1);
2383 Tmp2 = TLI.LowerOperation(Result, DAG);
2385 Result = LegalizeOp(Tmp2);
2386 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2390 case TargetLowering::Expand: {
2391 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2392 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2393 SV->getValue(), SV->getOffset());
2394 // Increment the pointer, VAList, to the next vaarg
2395 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2396 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2397 TLI.getPointerTy()));
2398 // Store the incremented VAList to the legalized pointer
2399 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, Node->getOperand(2));
2400 // Load the actual argument out of the pointer VAList
2401 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2402 Tmp1 = LegalizeOp(Result.getValue(1));
2403 Result = LegalizeOp(Result);
2407 // Since VAARG produces two values, make sure to remember that we
2408 // legalized both of them.
2409 AddLegalizedOperand(SDOperand(Node, 0), Result);
2410 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2411 return Op.ResNo ? Tmp1 : Result;
2415 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2416 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2417 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2419 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2420 default: assert(0 && "This action is not supported yet!");
2421 case TargetLowering::Custom:
2424 case TargetLowering::Legal:
2425 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2426 Node->getOperand(3), Node->getOperand(4));
2428 Tmp1 = TLI.LowerOperation(Result, DAG);
2429 if (Tmp1.Val) Result = Tmp1;
2432 case TargetLowering::Expand:
2433 // This defaults to loading a pointer from the input and storing it to the
2434 // output, returning the chain.
2435 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
2436 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
2437 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
2439 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, Node->getOperand(4));
2445 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2446 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2448 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2449 default: assert(0 && "This action is not supported yet!");
2450 case TargetLowering::Custom:
2453 case TargetLowering::Legal:
2454 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2456 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2457 if (Tmp1.Val) Result = Tmp1;
2460 case TargetLowering::Expand:
2461 Result = Tmp1; // Default to a no-op, return the chain
2467 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2468 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2470 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2472 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2473 default: assert(0 && "This action is not supported yet!");
2474 case TargetLowering::Legal: break;
2475 case TargetLowering::Custom:
2476 Tmp1 = TLI.LowerOperation(Result, DAG);
2477 if (Tmp1.Val) Result = Tmp1;
2484 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2485 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2487 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2488 "Cannot handle this yet!");
2489 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2493 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2494 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2495 case TargetLowering::Custom:
2496 assert(0 && "Cannot custom legalize this yet!");
2497 case TargetLowering::Legal:
2498 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2500 case TargetLowering::Promote: {
2501 MVT::ValueType OVT = Tmp1.getValueType();
2502 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2503 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2505 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2506 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2507 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2508 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2511 case TargetLowering::Expand:
2512 Result = ExpandBSWAP(Tmp1);
2520 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2521 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2522 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2523 case TargetLowering::Legal:
2524 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2526 case TargetLowering::Promote: {
2527 MVT::ValueType OVT = Tmp1.getValueType();
2528 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2530 // Zero extend the argument.
2531 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2532 // Perform the larger operation, then subtract if needed.
2533 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2534 switch (Node->getOpcode()) {
2539 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2540 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2541 DAG.getConstant(getSizeInBits(NVT), NVT),
2543 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2544 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2547 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2548 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2549 DAG.getConstant(getSizeInBits(NVT) -
2550 getSizeInBits(OVT), NVT));
2555 case TargetLowering::Expand:
2556 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2567 Tmp1 = LegalizeOp(Node->getOperand(0));
2568 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2569 case TargetLowering::Promote:
2570 case TargetLowering::Custom:
2573 case TargetLowering::Legal:
2574 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2576 Tmp1 = TLI.LowerOperation(Result, DAG);
2577 if (Tmp1.Val) Result = Tmp1;
2580 case TargetLowering::Expand:
2581 switch (Node->getOpcode()) {
2582 default: assert(0 && "Unreachable!");
2584 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2585 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2586 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2589 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2590 MVT::ValueType VT = Node->getValueType(0);
2591 Tmp2 = DAG.getConstantFP(0.0, VT);
2592 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2593 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2594 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2600 MVT::ValueType VT = Node->getValueType(0);
2601 const char *FnName = 0;
2602 switch(Node->getOpcode()) {
2603 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2604 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2605 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2606 default: assert(0 && "Unreachable!");
2609 Result = ExpandLibCall(FnName, Node, Dummy);
2617 // We always lower FPOWI into a libcall. No target support it yet.
2618 const char *FnName = Node->getValueType(0) == MVT::f32
2619 ? "__powisf2" : "__powidf2";
2621 Result = ExpandLibCall(FnName, Node, Dummy);
2624 case ISD::BIT_CONVERT:
2625 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2626 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2628 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2629 Node->getOperand(0).getValueType())) {
2630 default: assert(0 && "Unknown operation action!");
2631 case TargetLowering::Expand:
2632 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2634 case TargetLowering::Legal:
2635 Tmp1 = LegalizeOp(Node->getOperand(0));
2636 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2641 case ISD::VBIT_CONVERT: {
2642 assert(Op.getOperand(0).getValueType() == MVT::Vector &&
2643 "Can only have VBIT_CONVERT where input or output is MVT::Vector!");
2645 // The input has to be a vector type, we have to either scalarize it, pack
2646 // it, or convert it based on whether the input vector type is legal.
2647 SDNode *InVal = Node->getOperand(0).Val;
2649 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
2650 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
2652 // Figure out if there is a Packed type corresponding to this Vector
2653 // type. If so, convert to the packed type.
2654 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2655 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
2656 // Turn this into a bit convert of the packed input.
2657 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2658 PackVectorOp(Node->getOperand(0), TVT));
2660 } else if (NumElems == 1) {
2661 // Turn this into a bit convert of the scalar input.
2662 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2663 PackVectorOp(Node->getOperand(0), EVT));
2666 // FIXME: UNIMP! Store then reload
2667 assert(0 && "Cast from unsupported vector type not implemented yet!");
2671 // Conversion operators. The source and destination have different types.
2672 case ISD::SINT_TO_FP:
2673 case ISD::UINT_TO_FP: {
2674 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2675 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2677 switch (TLI.getOperationAction(Node->getOpcode(),
2678 Node->getOperand(0).getValueType())) {
2679 default: assert(0 && "Unknown operation action!");
2680 case TargetLowering::Custom:
2683 case TargetLowering::Legal:
2684 Tmp1 = LegalizeOp(Node->getOperand(0));
2685 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2687 Tmp1 = TLI.LowerOperation(Result, DAG);
2688 if (Tmp1.Val) Result = Tmp1;
2691 case TargetLowering::Expand:
2692 Result = ExpandLegalINT_TO_FP(isSigned,
2693 LegalizeOp(Node->getOperand(0)),
2694 Node->getValueType(0));
2696 case TargetLowering::Promote:
2697 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2698 Node->getValueType(0),
2704 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2705 Node->getValueType(0), Node->getOperand(0));
2708 Tmp1 = PromoteOp(Node->getOperand(0));
2710 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2711 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2713 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2714 Node->getOperand(0).getValueType());
2716 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2717 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2723 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2725 Tmp1 = LegalizeOp(Node->getOperand(0));
2726 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2729 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2731 // Since the result is legal, we should just be able to truncate the low
2732 // part of the source.
2733 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2736 Result = PromoteOp(Node->getOperand(0));
2737 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2742 case ISD::FP_TO_SINT:
2743 case ISD::FP_TO_UINT:
2744 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2746 Tmp1 = LegalizeOp(Node->getOperand(0));
2748 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2749 default: assert(0 && "Unknown operation action!");
2750 case TargetLowering::Custom:
2753 case TargetLowering::Legal:
2754 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2756 Tmp1 = TLI.LowerOperation(Result, DAG);
2757 if (Tmp1.Val) Result = Tmp1;
2760 case TargetLowering::Promote:
2761 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2762 Node->getOpcode() == ISD::FP_TO_SINT);
2764 case TargetLowering::Expand:
2765 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2766 SDOperand True, False;
2767 MVT::ValueType VT = Node->getOperand(0).getValueType();
2768 MVT::ValueType NVT = Node->getValueType(0);
2769 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2770 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2771 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2772 Node->getOperand(0), Tmp2, ISD::SETLT);
2773 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2774 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2775 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2777 False = DAG.getNode(ISD::XOR, NVT, False,
2778 DAG.getConstant(1ULL << ShiftAmt, NVT));
2779 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2782 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2788 assert(0 && "Shouldn't need to expand other operators here!");
2790 Tmp1 = PromoteOp(Node->getOperand(0));
2791 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
2792 Result = LegalizeOp(Result);
2797 case ISD::ANY_EXTEND:
2798 case ISD::ZERO_EXTEND:
2799 case ISD::SIGN_EXTEND:
2800 case ISD::FP_EXTEND:
2802 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2803 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
2805 Tmp1 = LegalizeOp(Node->getOperand(0));
2806 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2809 switch (Node->getOpcode()) {
2810 case ISD::ANY_EXTEND:
2811 Tmp1 = PromoteOp(Node->getOperand(0));
2812 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
2814 case ISD::ZERO_EXTEND:
2815 Result = PromoteOp(Node->getOperand(0));
2816 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2817 Result = DAG.getZeroExtendInReg(Result,
2818 Node->getOperand(0).getValueType());
2820 case ISD::SIGN_EXTEND:
2821 Result = PromoteOp(Node->getOperand(0));
2822 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2823 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2825 DAG.getValueType(Node->getOperand(0).getValueType()));
2827 case ISD::FP_EXTEND:
2828 Result = PromoteOp(Node->getOperand(0));
2829 if (Result.getValueType() != Op.getValueType())
2830 // Dynamically dead while we have only 2 FP types.
2831 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2834 Result = PromoteOp(Node->getOperand(0));
2835 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2840 case ISD::FP_ROUND_INREG:
2841 case ISD::SIGN_EXTEND_INREG: {
2842 Tmp1 = LegalizeOp(Node->getOperand(0));
2843 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2845 // If this operation is not supported, convert it to a shl/shr or load/store
2847 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2848 default: assert(0 && "This action not supported for this op yet!");
2849 case TargetLowering::Legal:
2850 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2852 case TargetLowering::Expand:
2853 // If this is an integer extend and shifts are supported, do that.
2854 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2855 // NOTE: we could fall back on load/store here too for targets without
2856 // SAR. However, it is doubtful that any exist.
2857 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2858 MVT::getSizeInBits(ExtraVT);
2859 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2860 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2861 Node->getOperand(0), ShiftCst);
2862 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2864 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2865 // The only way we can lower this is to turn it into a STORETRUNC,
2866 // EXTLOAD pair, targetting a temporary location (a stack slot).
2868 // NOTE: there is a choice here between constantly creating new stack
2869 // slots and always reusing the same one. We currently always create
2870 // new ones, as reuse may inhibit scheduling.
2871 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2872 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty);
2873 unsigned Align = TLI.getTargetData()->getTypeAlignment(Ty);
2874 MachineFunction &MF = DAG.getMachineFunction();
2876 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2877 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2878 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2879 Node->getOperand(0), StackSlot,
2880 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2881 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2882 Result, StackSlot, NULL, 0, ExtraVT);
2884 assert(0 && "Unknown op");
2892 assert(Result.getValueType() == Op.getValueType() &&
2893 "Bad legalization!");
2895 // Make sure that the generated code is itself legal.
2897 Result = LegalizeOp(Result);
2899 // Note that LegalizeOp may be reentered even from single-use nodes, which
2900 // means that we always must cache transformed nodes.
2901 AddLegalizedOperand(Op, Result);
2905 /// PromoteOp - Given an operation that produces a value in an invalid type,
2906 /// promote it to compute the value into a larger type. The produced value will
2907 /// have the correct bits for the low portion of the register, but no guarantee
2908 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2909 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2910 MVT::ValueType VT = Op.getValueType();
2911 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2912 assert(getTypeAction(VT) == Promote &&
2913 "Caller should expand or legalize operands that are not promotable!");
2914 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2915 "Cannot promote to smaller type!");
2917 SDOperand Tmp1, Tmp2, Tmp3;
2919 SDNode *Node = Op.Val;
2921 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2922 if (I != PromotedNodes.end()) return I->second;
2924 switch (Node->getOpcode()) {
2925 case ISD::CopyFromReg:
2926 assert(0 && "CopyFromReg must be legal!");
2929 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2931 assert(0 && "Do not know how to promote this operator!");
2934 Result = DAG.getNode(ISD::UNDEF, NVT);
2938 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2940 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2941 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2943 case ISD::ConstantFP:
2944 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2945 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2949 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2950 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2951 Node->getOperand(1), Node->getOperand(2));
2955 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2957 Result = LegalizeOp(Node->getOperand(0));
2958 assert(Result.getValueType() >= NVT &&
2959 "This truncation doesn't make sense!");
2960 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2961 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2964 // The truncation is not required, because we don't guarantee anything
2965 // about high bits anyway.
2966 Result = PromoteOp(Node->getOperand(0));
2969 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2970 // Truncate the low part of the expanded value to the result type
2971 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2974 case ISD::SIGN_EXTEND:
2975 case ISD::ZERO_EXTEND:
2976 case ISD::ANY_EXTEND:
2977 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2978 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2980 // Input is legal? Just do extend all the way to the larger type.
2981 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2984 // Promote the reg if it's smaller.
2985 Result = PromoteOp(Node->getOperand(0));
2986 // The high bits are not guaranteed to be anything. Insert an extend.
2987 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2988 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2989 DAG.getValueType(Node->getOperand(0).getValueType()));
2990 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2991 Result = DAG.getZeroExtendInReg(Result,
2992 Node->getOperand(0).getValueType());
2996 case ISD::BIT_CONVERT:
2997 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2998 Result = PromoteOp(Result);
3001 case ISD::FP_EXTEND:
3002 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3004 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3005 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3006 case Promote: assert(0 && "Unreachable with 2 FP types!");
3008 // Input is legal? Do an FP_ROUND_INREG.
3009 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3010 DAG.getValueType(VT));
3015 case ISD::SINT_TO_FP:
3016 case ISD::UINT_TO_FP:
3017 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3019 // No extra round required here.
3020 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3024 Result = PromoteOp(Node->getOperand(0));
3025 if (Node->getOpcode() == ISD::SINT_TO_FP)
3026 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3028 DAG.getValueType(Node->getOperand(0).getValueType()));
3030 Result = DAG.getZeroExtendInReg(Result,
3031 Node->getOperand(0).getValueType());
3032 // No extra round required here.
3033 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3036 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3037 Node->getOperand(0));
3038 // Round if we cannot tolerate excess precision.
3039 if (NoExcessFPPrecision)
3040 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3041 DAG.getValueType(VT));
3046 case ISD::SIGN_EXTEND_INREG:
3047 Result = PromoteOp(Node->getOperand(0));
3048 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3049 Node->getOperand(1));
3051 case ISD::FP_TO_SINT:
3052 case ISD::FP_TO_UINT:
3053 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3055 Tmp1 = Node->getOperand(0);
3058 // The input result is prerounded, so we don't have to do anything
3060 Tmp1 = PromoteOp(Node->getOperand(0));
3063 assert(0 && "not implemented");
3065 // If we're promoting a UINT to a larger size, check to see if the new node
3066 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3067 // we can use that instead. This allows us to generate better code for
3068 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3069 // legal, such as PowerPC.
3070 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3071 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3072 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3073 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3074 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3076 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3082 Tmp1 = PromoteOp(Node->getOperand(0));
3083 assert(Tmp1.getValueType() == NVT);
3084 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3085 // NOTE: we do not have to do any extra rounding here for
3086 // NoExcessFPPrecision, because we know the input will have the appropriate
3087 // precision, and these operations don't modify precision at all.
3093 Tmp1 = PromoteOp(Node->getOperand(0));
3094 assert(Tmp1.getValueType() == NVT);
3095 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3096 if (NoExcessFPPrecision)
3097 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3098 DAG.getValueType(VT));
3107 // The input may have strange things in the top bits of the registers, but
3108 // these operations don't care. They may have weird bits going out, but
3109 // that too is okay if they are integer operations.
3110 Tmp1 = PromoteOp(Node->getOperand(0));
3111 Tmp2 = PromoteOp(Node->getOperand(1));
3112 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3113 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3118 Tmp1 = PromoteOp(Node->getOperand(0));
3119 Tmp2 = PromoteOp(Node->getOperand(1));
3120 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3121 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3123 // Floating point operations will give excess precision that we may not be
3124 // able to tolerate. If we DO allow excess precision, just leave it,
3125 // otherwise excise it.
3126 // FIXME: Why would we need to round FP ops more than integer ones?
3127 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3128 if (NoExcessFPPrecision)
3129 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3130 DAG.getValueType(VT));
3135 // These operators require that their input be sign extended.
3136 Tmp1 = PromoteOp(Node->getOperand(0));
3137 Tmp2 = PromoteOp(Node->getOperand(1));
3138 if (MVT::isInteger(NVT)) {
3139 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3140 DAG.getValueType(VT));
3141 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3142 DAG.getValueType(VT));
3144 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3146 // Perform FP_ROUND: this is probably overly pessimistic.
3147 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3148 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3149 DAG.getValueType(VT));
3153 case ISD::FCOPYSIGN:
3154 // These operators require that their input be fp extended.
3155 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3157 Tmp1 = LegalizeOp(Node->getOperand(0));
3160 Tmp1 = PromoteOp(Node->getOperand(0));
3163 assert(0 && "not implemented");
3165 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3167 Tmp2 = LegalizeOp(Node->getOperand(1));
3170 Tmp2 = PromoteOp(Node->getOperand(1));
3173 assert(0 && "not implemented");
3175 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3177 // Perform FP_ROUND: this is probably overly pessimistic.
3178 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3179 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3180 DAG.getValueType(VT));
3185 // These operators require that their input be zero extended.
3186 Tmp1 = PromoteOp(Node->getOperand(0));
3187 Tmp2 = PromoteOp(Node->getOperand(1));
3188 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3189 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3190 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3191 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3195 Tmp1 = PromoteOp(Node->getOperand(0));
3196 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3199 // The input value must be properly sign extended.
3200 Tmp1 = PromoteOp(Node->getOperand(0));
3201 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3202 DAG.getValueType(VT));
3203 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3206 // The input value must be properly zero extended.
3207 Tmp1 = PromoteOp(Node->getOperand(0));
3208 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3209 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3213 Tmp1 = Node->getOperand(0); // Get the chain.
3214 Tmp2 = Node->getOperand(1); // Get the pointer.
3215 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3216 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3217 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3219 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3220 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3221 SV->getValue(), SV->getOffset());
3222 // Increment the pointer, VAList, to the next vaarg
3223 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3224 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3225 TLI.getPointerTy()));
3226 // Store the incremented VAList to the legalized pointer
3227 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, Node->getOperand(2));
3228 // Load the actual argument out of the pointer VAList
3229 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
3231 // Remember that we legalized the chain.
3232 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3236 LoadSDNode *LD = cast<LoadSDNode>(Node);
3237 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, LD->getChain(), LD->getBasePtr(),
3238 LD->getSrcValue(), LD->getSrcValueOffset(), VT);
3239 // Remember that we legalized the chain.
3240 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3244 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3245 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3246 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3248 case ISD::SELECT_CC:
3249 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3250 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3251 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3252 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3255 Tmp1 = Node->getOperand(0);
3256 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3257 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3258 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3259 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
3260 TLI.getShiftAmountTy()));
3265 // Zero extend the argument
3266 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3267 // Perform the larger operation, then subtract if needed.
3268 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3269 switch(Node->getOpcode()) {
3274 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3275 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3276 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
3277 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3278 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
3281 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3282 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3283 DAG.getConstant(getSizeInBits(NVT) -
3284 getSizeInBits(VT), NVT));
3288 case ISD::VEXTRACT_VECTOR_ELT:
3289 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
3291 case ISD::EXTRACT_VECTOR_ELT:
3292 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3296 assert(Result.Val && "Didn't set a result!");
3298 // Make sure the result is itself legal.
3299 Result = LegalizeOp(Result);
3301 // Remember that we promoted this!
3302 AddPromotedOperand(Op, Result);
3306 /// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
3307 /// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
3308 /// on the vector type. The return type of this matches the element type of the
3309 /// vector, which may not be legal for the target.
3310 SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
3311 // We know that operand #0 is the Vec vector. If the index is a constant
3312 // or if the invec is a supported hardware type, we can use it. Otherwise,
3313 // lower to a store then an indexed load.
3314 SDOperand Vec = Op.getOperand(0);
3315 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3317 SDNode *InVal = Vec.Val;
3318 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
3319 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
3321 // Figure out if there is a Packed type corresponding to this Vector
3322 // type. If so, convert to the packed type.
3323 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3324 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
3325 // Turn this into a packed extract_vector_elt operation.
3326 Vec = PackVectorOp(Vec, TVT);
3327 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
3328 } else if (NumElems == 1) {
3329 // This must be an access of the only element. Return it.
3330 return PackVectorOp(Vec, EVT);
3331 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
3333 SplitVectorOp(Vec, Lo, Hi);
3334 if (CIdx->getValue() < NumElems/2) {
3338 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3341 // It's now an extract from the appropriate high or low part. Recurse.
3342 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3343 return LowerVEXTRACT_VECTOR_ELT(Op);
3345 // Variable index case for extract element.
3346 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
3347 assert(0 && "unimp!");
3352 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3354 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3355 SDOperand Vector = Op.getOperand(0);
3356 SDOperand Idx = Op.getOperand(1);
3358 // If the target doesn't support this, store the value to a temporary
3359 // stack slot, then LOAD the scalar element back out.
3360 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
3361 SDOperand Ch = DAG.getStore(DAG.getEntryNode(),
3362 Vector, StackPtr, DAG.getSrcValue(NULL));
3364 // Add the offset to the index.
3365 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3366 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3367 DAG.getConstant(EltSize, Idx.getValueType()));
3368 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3370 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
3374 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3375 /// with condition CC on the current target. This usually involves legalizing
3376 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3377 /// there may be no choice but to create a new SetCC node to represent the
3378 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3379 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3380 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3383 SDOperand Tmp1, Tmp2, Result;
3385 switch (getTypeAction(LHS.getValueType())) {
3387 Tmp1 = LegalizeOp(LHS); // LHS
3388 Tmp2 = LegalizeOp(RHS); // RHS
3391 Tmp1 = PromoteOp(LHS); // LHS
3392 Tmp2 = PromoteOp(RHS); // RHS
3394 // If this is an FP compare, the operands have already been extended.
3395 if (MVT::isInteger(LHS.getValueType())) {
3396 MVT::ValueType VT = LHS.getValueType();
3397 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3399 // Otherwise, we have to insert explicit sign or zero extends. Note
3400 // that we could insert sign extends for ALL conditions, but zero extend
3401 // is cheaper on many machines (an AND instead of two shifts), so prefer
3403 switch (cast<CondCodeSDNode>(CC)->get()) {
3404 default: assert(0 && "Unknown integer comparison!");
3411 // ALL of these operations will work if we either sign or zero extend
3412 // the operands (including the unsigned comparisons!). Zero extend is
3413 // usually a simpler/cheaper operation, so prefer it.
3414 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3415 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3421 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3422 DAG.getValueType(VT));
3423 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3424 DAG.getValueType(VT));
3430 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3431 ExpandOp(LHS, LHSLo, LHSHi);
3432 ExpandOp(RHS, RHSLo, RHSHi);
3433 switch (cast<CondCodeSDNode>(CC)->get()) {
3437 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3438 if (RHSCST->isAllOnesValue()) {
3439 // Comparison to -1.
3440 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3445 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3446 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3447 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3448 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3451 // If this is a comparison of the sign bit, just look at the top part.
3453 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3454 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3455 CST->getValue() == 0) || // X < 0
3456 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3457 CST->isAllOnesValue())) { // X > -1
3463 // FIXME: This generated code sucks.
3464 ISD::CondCode LowCC;
3465 switch (cast<CondCodeSDNode>(CC)->get()) {
3466 default: assert(0 && "Unknown integer setcc!");
3468 case ISD::SETULT: LowCC = ISD::SETULT; break;
3470 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3472 case ISD::SETULE: LowCC = ISD::SETULE; break;
3474 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3477 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3478 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3479 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3481 // NOTE: on targets without efficient SELECT of bools, we can always use
3482 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3483 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3484 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3485 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3486 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3487 Result, Tmp1, Tmp2));
3496 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3497 /// The resultant code need not be legal. Note that SrcOp is the input operand
3498 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3499 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3501 // Create the stack frame object.
3502 SDOperand FIPtr = CreateStackTemporary(DestVT);
3504 // Emit a store to the stack slot.
3505 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
3506 SrcOp, FIPtr, DAG.getSrcValue(NULL));
3507 // Result is a load from the stack slot.
3508 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
3511 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3512 // Create a vector sized/aligned stack slot, store the value to element #0,
3513 // then load the whole vector back out.
3514 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3515 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
3516 DAG.getSrcValue(NULL));
3517 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
3521 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3522 /// support the operation, but do support the resultant packed vector type.
3523 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3525 // If the only non-undef value is the low element, turn this into a
3526 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3527 unsigned NumElems = Node->getNumOperands();
3528 bool isOnlyLowElement = true;
3529 SDOperand SplatValue = Node->getOperand(0);
3530 std::map<SDOperand, std::vector<unsigned> > Values;
3531 Values[SplatValue].push_back(0);
3532 bool isConstant = true;
3533 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3534 SplatValue.getOpcode() != ISD::UNDEF)
3537 for (unsigned i = 1; i < NumElems; ++i) {
3538 SDOperand V = Node->getOperand(i);
3539 Values[V].push_back(i);
3540 if (V.getOpcode() != ISD::UNDEF)
3541 isOnlyLowElement = false;
3542 if (SplatValue != V)
3543 SplatValue = SDOperand(0,0);
3545 // If this isn't a constant element or an undef, we can't use a constant
3547 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3548 V.getOpcode() != ISD::UNDEF)
3552 if (isOnlyLowElement) {
3553 // If the low element is an undef too, then this whole things is an undef.
3554 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3555 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3556 // Otherwise, turn this into a scalar_to_vector node.
3557 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3558 Node->getOperand(0));
3561 // If all elements are constants, create a load from the constant pool.
3563 MVT::ValueType VT = Node->getValueType(0);
3565 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3566 std::vector<Constant*> CV;
3567 for (unsigned i = 0, e = NumElems; i != e; ++i) {
3568 if (ConstantFPSDNode *V =
3569 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3570 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3571 } else if (ConstantSDNode *V =
3572 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3573 CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
3575 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3576 CV.push_back(UndefValue::get(OpNTy));
3579 Constant *CP = ConstantPacked::get(CV);
3580 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3581 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
3584 if (SplatValue.Val) { // Splat of one value?
3585 // Build the shuffle constant vector: <0, 0, 0, 0>
3586 MVT::ValueType MaskVT =
3587 MVT::getIntVectorWithNumElements(NumElems);
3588 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
3589 std::vector<SDOperand> ZeroVec(NumElems, Zero);
3590 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3591 &ZeroVec[0], ZeroVec.size());
3593 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3594 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
3595 // Get the splatted value into the low element of a vector register.
3596 SDOperand LowValVec =
3597 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3599 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3600 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3601 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3606 // If there are only two unique elements, we may be able to turn this into a
3608 if (Values.size() == 2) {
3609 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
3610 MVT::ValueType MaskVT =
3611 MVT::getIntVectorWithNumElements(NumElems);
3612 std::vector<SDOperand> MaskVec(NumElems);
3614 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3615 E = Values.end(); I != E; ++I) {
3616 for (std::vector<unsigned>::iterator II = I->second.begin(),
3617 EE = I->second.end(); II != EE; ++II)
3618 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
3621 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3622 &MaskVec[0], MaskVec.size());
3624 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3625 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
3626 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
3627 SmallVector<SDOperand, 8> Ops;
3628 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3629 E = Values.end(); I != E; ++I) {
3630 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3634 Ops.push_back(ShuffleMask);
3636 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
3637 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
3638 &Ops[0], Ops.size());
3642 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
3643 // aligned object on the stack, store each element into it, then load
3644 // the result as a vector.
3645 MVT::ValueType VT = Node->getValueType(0);
3646 // Create the stack frame object.
3647 SDOperand FIPtr = CreateStackTemporary(VT);
3649 // Emit a store of each element to the stack slot.
3650 SmallVector<SDOperand, 8> Stores;
3651 unsigned TypeByteSize =
3652 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
3653 unsigned VectorSize = MVT::getSizeInBits(VT)/8;
3654 // Store (in the right endianness) the elements to memory.
3655 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3656 // Ignore undef elements.
3657 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3659 unsigned Offset = TypeByteSize*i;
3661 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
3662 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
3664 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
3665 DAG.getSrcValue(NULL)));
3668 SDOperand StoreChain;
3669 if (!Stores.empty()) // Not all undef elements?
3670 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3671 &Stores[0], Stores.size());
3673 StoreChain = DAG.getEntryNode();
3675 // Result is a load from the stack slot.
3676 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
3679 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
3680 /// specified value type.
3681 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
3682 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3683 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
3684 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
3685 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
3688 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
3689 SDOperand Op, SDOperand Amt,
3690 SDOperand &Lo, SDOperand &Hi) {
3691 // Expand the subcomponents.
3692 SDOperand LHSL, LHSH;
3693 ExpandOp(Op, LHSL, LHSH);
3695 SDOperand Ops[] = { LHSL, LHSH, Amt };
3696 MVT::ValueType VT = LHSL.getValueType();
3697 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
3698 Hi = Lo.getValue(1);
3702 /// ExpandShift - Try to find a clever way to expand this shift operation out to
3703 /// smaller elements. If we can't find a way that is more efficient than a
3704 /// libcall on this target, return false. Otherwise, return true with the
3705 /// low-parts expanded into Lo and Hi.
3706 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3707 SDOperand &Lo, SDOperand &Hi) {
3708 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3709 "This is not a shift!");
3711 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3712 SDOperand ShAmt = LegalizeOp(Amt);
3713 MVT::ValueType ShTy = ShAmt.getValueType();
3714 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3715 unsigned NVTBits = MVT::getSizeInBits(NVT);
3717 // Handle the case when Amt is an immediate. Other cases are currently broken
3718 // and are disabled.
3719 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3720 unsigned Cst = CN->getValue();
3721 // Expand the incoming operand to be shifted, so that we have its parts
3723 ExpandOp(Op, InL, InH);
3727 Lo = DAG.getConstant(0, NVT);
3728 Hi = DAG.getConstant(0, NVT);
3729 } else if (Cst > NVTBits) {
3730 Lo = DAG.getConstant(0, NVT);
3731 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
3732 } else if (Cst == NVTBits) {
3733 Lo = DAG.getConstant(0, NVT);
3736 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
3737 Hi = DAG.getNode(ISD::OR, NVT,
3738 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
3739 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
3744 Lo = DAG.getConstant(0, NVT);
3745 Hi = DAG.getConstant(0, NVT);
3746 } else if (Cst > NVTBits) {
3747 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
3748 Hi = DAG.getConstant(0, NVT);
3749 } else if (Cst == NVTBits) {
3751 Hi = DAG.getConstant(0, NVT);
3753 Lo = DAG.getNode(ISD::OR, NVT,
3754 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3755 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3756 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
3761 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
3762 DAG.getConstant(NVTBits-1, ShTy));
3763 } else if (Cst > NVTBits) {
3764 Lo = DAG.getNode(ISD::SRA, NVT, InH,
3765 DAG.getConstant(Cst-NVTBits, ShTy));
3766 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3767 DAG.getConstant(NVTBits-1, ShTy));
3768 } else if (Cst == NVTBits) {
3770 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3771 DAG.getConstant(NVTBits-1, ShTy));
3773 Lo = DAG.getNode(ISD::OR, NVT,
3774 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3775 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3776 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
3782 // Okay, the shift amount isn't constant. However, if we can tell that it is
3783 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
3784 uint64_t Mask = NVTBits, KnownZero, KnownOne;
3785 TLI.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
3787 // If we know that the high bit of the shift amount is one, then we can do
3788 // this as a couple of simple shifts.
3789 if (KnownOne & Mask) {
3790 // Mask out the high bit, which we know is set.
3791 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
3792 DAG.getConstant(NVTBits-1, Amt.getValueType()));
3794 // Expand the incoming operand to be shifted, so that we have its parts
3796 ExpandOp(Op, InL, InH);
3799 Lo = DAG.getConstant(0, NVT); // Low part is zero.
3800 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
3803 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
3804 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
3807 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
3808 DAG.getConstant(NVTBits-1, Amt.getValueType()));
3809 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
3814 // If we know that the high bit of the shift amount is zero, then we can do
3815 // this as a couple of simple shifts.
3816 if (KnownZero & Mask) {
3818 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
3819 DAG.getConstant(NVTBits, Amt.getValueType()),
3822 // Expand the incoming operand to be shifted, so that we have its parts
3824 ExpandOp(Op, InL, InH);
3827 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
3828 Hi = DAG.getNode(ISD::OR, NVT,
3829 DAG.getNode(ISD::SHL, NVT, InH, Amt),
3830 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
3833 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
3834 Lo = DAG.getNode(ISD::OR, NVT,
3835 DAG.getNode(ISD::SRL, NVT, InL, Amt),
3836 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
3839 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
3840 Lo = DAG.getNode(ISD::OR, NVT,
3841 DAG.getNode(ISD::SRL, NVT, InL, Amt),
3842 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
3851 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
3852 // does not fit into a register, return the lo part and set the hi part to the
3853 // by-reg argument. If it does fit into a single register, return the result
3854 // and leave the Hi part unset.
3855 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3857 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
3858 // The input chain to this libcall is the entry node of the function.
3859 // Legalizing the call will automatically add the previous call to the
3861 SDOperand InChain = DAG.getEntryNode();
3863 TargetLowering::ArgListTy Args;
3864 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3865 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3866 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3867 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3869 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3871 // Splice the libcall in wherever FindInputOutputChains tells us to.
3872 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3873 std::pair<SDOperand,SDOperand> CallInfo =
3874 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3877 // Legalize the call sequence, starting with the chain. This will advance
3878 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
3879 // was added by LowerCallTo (guaranteeing proper serialization of calls).
3880 LegalizeOp(CallInfo.second);
3882 switch (getTypeAction(CallInfo.first.getValueType())) {
3883 default: assert(0 && "Unknown thing");
3885 Result = CallInfo.first;
3888 ExpandOp(CallInfo.first, Result, Hi);
3895 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3896 /// destination type is legal.
3897 SDOperand SelectionDAGLegalize::
3898 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3899 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3900 assert(getTypeAction(Source.getValueType()) == Expand &&
3901 "This is not an expansion!");
3902 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3905 assert(Source.getValueType() == MVT::i64 &&
3906 "This only works for 64-bit -> FP");
3907 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3908 // incoming integer is set. To handle this, we dynamically test to see if
3909 // it is set, and, if so, add a fudge factor.
3911 ExpandOp(Source, Lo, Hi);
3913 // If this is unsigned, and not supported, first perform the conversion to
3914 // signed, then adjust the result if the sign bit is set.
3915 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3916 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3918 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3919 DAG.getConstant(0, Hi.getValueType()),
3921 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3922 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3923 SignSet, Four, Zero);
3924 uint64_t FF = 0x5f800000ULL;
3925 if (TLI.isLittleEndian()) FF <<= 32;
3926 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3928 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3929 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3930 SDOperand FudgeInReg;
3931 if (DestTy == MVT::f32)
3932 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
3934 assert(DestTy == MVT::f64 && "Unexpected conversion");
3935 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3936 CPIdx, NULL, 0, MVT::f32);
3938 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3941 // Check to see if the target has a custom way to lower this. If so, use it.
3942 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3943 default: assert(0 && "This action not implemented for this operation!");
3944 case TargetLowering::Legal:
3945 case TargetLowering::Expand:
3946 break; // This case is handled below.
3947 case TargetLowering::Custom: {
3948 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3951 return LegalizeOp(NV);
3952 break; // The target decided this was legal after all
3956 // Expand the source, then glue it back together for the call. We must expand
3957 // the source in case it is shared (this pass of legalize must traverse it).
3958 SDOperand SrcLo, SrcHi;
3959 ExpandOp(Source, SrcLo, SrcHi);
3960 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
3962 const char *FnName = 0;
3963 if (DestTy == MVT::f32)
3964 FnName = "__floatdisf";
3966 assert(DestTy == MVT::f64 && "Unknown fp value type!");
3967 FnName = "__floatdidf";
3970 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
3971 SDOperand UnusedHiPart;
3972 return ExpandLibCall(FnName, Source.Val, UnusedHiPart);
3975 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
3976 /// INT_TO_FP operation of the specified operand when the target requests that
3977 /// we expand it. At this point, we know that the result and operand types are
3978 /// legal for the target.
3979 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
3981 MVT::ValueType DestVT) {
3982 if (Op0.getValueType() == MVT::i32) {
3983 // simple 32-bit [signed|unsigned] integer to float/double expansion
3985 // get the stack frame index of a 8 byte buffer
3986 MachineFunction &MF = DAG.getMachineFunction();
3987 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3988 // get address of 8 byte buffer
3989 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3990 // word offset constant for Hi/Lo address computation
3991 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
3992 // set up Hi and Lo (into buffer) address based on endian
3993 SDOperand Hi = StackSlot;
3994 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
3995 if (TLI.isLittleEndian())
3998 // if signed map to unsigned space
3999 SDOperand Op0Mapped;
4001 // constant used to invert sign bit (signed to unsigned mapping)
4002 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4003 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4007 // store the lo of the constructed double - based on integer input
4008 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4009 Op0Mapped, Lo, DAG.getSrcValue(NULL));
4010 // initial hi portion of constructed double
4011 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4012 // store the hi of the constructed double - biased exponent
4013 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, DAG.getSrcValue(NULL));
4014 // load the constructed double
4015 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4016 // FP constant to bias correct the final result
4017 SDOperand Bias = DAG.getConstantFP(isSigned ?
4018 BitsToDouble(0x4330000080000000ULL)
4019 : BitsToDouble(0x4330000000000000ULL),
4021 // subtract the bias
4022 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4025 // handle final rounding
4026 if (DestVT == MVT::f64) {
4030 // if f32 then cast to f32
4031 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
4035 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4036 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4038 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4039 DAG.getConstant(0, Op0.getValueType()),
4041 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4042 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4043 SignSet, Four, Zero);
4045 // If the sign bit of the integer is set, the large number will be treated
4046 // as a negative number. To counteract this, the dynamic code adds an
4047 // offset depending on the data type.
4049 switch (Op0.getValueType()) {
4050 default: assert(0 && "Unsupported integer type!");
4051 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4052 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4053 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4054 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4056 if (TLI.isLittleEndian()) FF <<= 32;
4057 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
4059 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4060 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4061 SDOperand FudgeInReg;
4062 if (DestVT == MVT::f32)
4063 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4065 assert(DestVT == MVT::f64 && "Unexpected conversion");
4066 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
4067 DAG.getEntryNode(), CPIdx,
4068 NULL, 0, MVT::f32));
4071 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4074 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4075 /// *INT_TO_FP operation of the specified operand when the target requests that
4076 /// we promote it. At this point, we know that the result and operand types are
4077 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4078 /// operation that takes a larger input.
4079 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4080 MVT::ValueType DestVT,
4082 // First step, figure out the appropriate *INT_TO_FP operation to use.
4083 MVT::ValueType NewInTy = LegalOp.getValueType();
4085 unsigned OpToUse = 0;
4087 // Scan for the appropriate larger type to use.
4089 NewInTy = (MVT::ValueType)(NewInTy+1);
4090 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4092 // If the target supports SINT_TO_FP of this type, use it.
4093 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4095 case TargetLowering::Legal:
4096 if (!TLI.isTypeLegal(NewInTy))
4097 break; // Can't use this datatype.
4099 case TargetLowering::Custom:
4100 OpToUse = ISD::SINT_TO_FP;
4104 if (isSigned) continue;
4106 // If the target supports UINT_TO_FP of this type, use it.
4107 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4109 case TargetLowering::Legal:
4110 if (!TLI.isTypeLegal(NewInTy))
4111 break; // Can't use this datatype.
4113 case TargetLowering::Custom:
4114 OpToUse = ISD::UINT_TO_FP;
4119 // Otherwise, try a larger type.
4122 // Okay, we found the operation and type to use. Zero extend our input to the
4123 // desired type then run the operation on it.
4124 return DAG.getNode(OpToUse, DestVT,
4125 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4129 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4130 /// FP_TO_*INT operation of the specified operand when the target requests that
4131 /// we promote it. At this point, we know that the result and operand types are
4132 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4133 /// operation that returns a larger result.
4134 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4135 MVT::ValueType DestVT,
4137 // First step, figure out the appropriate FP_TO*INT operation to use.
4138 MVT::ValueType NewOutTy = DestVT;
4140 unsigned OpToUse = 0;
4142 // Scan for the appropriate larger type to use.
4144 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4145 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4147 // If the target supports FP_TO_SINT returning this type, use it.
4148 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4150 case TargetLowering::Legal:
4151 if (!TLI.isTypeLegal(NewOutTy))
4152 break; // Can't use this datatype.
4154 case TargetLowering::Custom:
4155 OpToUse = ISD::FP_TO_SINT;
4160 // If the target supports FP_TO_UINT of this type, use it.
4161 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4163 case TargetLowering::Legal:
4164 if (!TLI.isTypeLegal(NewOutTy))
4165 break; // Can't use this datatype.
4167 case TargetLowering::Custom:
4168 OpToUse = ISD::FP_TO_UINT;
4173 // Otherwise, try a larger type.
4176 // Okay, we found the operation and type to use. Truncate the result of the
4177 // extended FP_TO_*INT operation to the desired size.
4178 return DAG.getNode(ISD::TRUNCATE, DestVT,
4179 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4182 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4184 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4185 MVT::ValueType VT = Op.getValueType();
4186 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4187 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4189 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4191 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4192 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4193 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4195 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4196 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4197 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4198 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4199 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4200 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4201 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4202 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4203 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4205 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4206 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4207 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4208 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4209 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4210 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4211 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4212 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4213 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4214 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4215 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4216 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4217 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4218 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4219 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4220 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4221 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4222 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4223 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4224 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4225 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4229 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4231 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4233 default: assert(0 && "Cannot expand this yet!");
4235 static const uint64_t mask[6] = {
4236 0x5555555555555555ULL, 0x3333333333333333ULL,
4237 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4238 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4240 MVT::ValueType VT = Op.getValueType();
4241 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4242 unsigned len = getSizeInBits(VT);
4243 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4244 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4245 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4246 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4247 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4248 DAG.getNode(ISD::AND, VT,
4249 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4254 // for now, we do this:
4255 // x = x | (x >> 1);
4256 // x = x | (x >> 2);
4258 // x = x | (x >>16);
4259 // x = x | (x >>32); // for 64-bit input
4260 // return popcount(~x);
4262 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4263 MVT::ValueType VT = Op.getValueType();
4264 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4265 unsigned len = getSizeInBits(VT);
4266 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4267 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4268 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4270 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4271 return DAG.getNode(ISD::CTPOP, VT, Op);
4274 // for now, we use: { return popcount(~x & (x - 1)); }
4275 // unless the target has ctlz but not ctpop, in which case we use:
4276 // { return 32 - nlz(~x & (x-1)); }
4277 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4278 MVT::ValueType VT = Op.getValueType();
4279 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4280 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4281 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4282 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4283 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4284 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4285 TLI.isOperationLegal(ISD::CTLZ, VT))
4286 return DAG.getNode(ISD::SUB, VT,
4287 DAG.getConstant(getSizeInBits(VT), VT),
4288 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4289 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4294 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4295 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4296 /// LegalizeNodes map is filled in for any results that are not expanded, the
4297 /// ExpandedNodes map is filled in for any results that are expanded, and the
4298 /// Lo/Hi values are returned.
4299 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4300 MVT::ValueType VT = Op.getValueType();
4301 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4302 SDNode *Node = Op.Val;
4303 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4304 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
4305 "Cannot expand FP values!");
4306 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
4307 "Cannot expand to FP value or to larger int value!");
4309 // See if we already expanded it.
4310 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4311 = ExpandedNodes.find(Op);
4312 if (I != ExpandedNodes.end()) {
4313 Lo = I->second.first;
4314 Hi = I->second.second;
4318 switch (Node->getOpcode()) {
4319 case ISD::CopyFromReg:
4320 assert(0 && "CopyFromReg must be legal!");
4323 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
4325 assert(0 && "Do not know how to expand this operator!");
4328 Lo = DAG.getNode(ISD::UNDEF, NVT);
4329 Hi = DAG.getNode(ISD::UNDEF, NVT);
4331 case ISD::Constant: {
4332 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4333 Lo = DAG.getConstant(Cst, NVT);
4334 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4337 case ISD::BUILD_PAIR:
4338 // Return the operands.
4339 Lo = Node->getOperand(0);
4340 Hi = Node->getOperand(1);
4343 case ISD::SIGN_EXTEND_INREG:
4344 ExpandOp(Node->getOperand(0), Lo, Hi);
4345 // sext_inreg the low part if needed.
4346 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4348 // The high part gets the sign extension from the lo-part. This handles
4349 // things like sextinreg V:i64 from i8.
4350 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4351 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4352 TLI.getShiftAmountTy()));
4356 ExpandOp(Node->getOperand(0), Lo, Hi);
4357 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4358 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4364 ExpandOp(Node->getOperand(0), Lo, Hi);
4365 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4366 DAG.getNode(ISD::CTPOP, NVT, Lo),
4367 DAG.getNode(ISD::CTPOP, NVT, Hi));
4368 Hi = DAG.getConstant(0, NVT);
4372 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4373 ExpandOp(Node->getOperand(0), Lo, Hi);
4374 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4375 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4376 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4378 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4379 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4381 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4382 Hi = DAG.getConstant(0, NVT);
4387 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4388 ExpandOp(Node->getOperand(0), Lo, Hi);
4389 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4390 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4391 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4393 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4394 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4396 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4397 Hi = DAG.getConstant(0, NVT);
4402 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4403 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4404 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4405 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4407 // Remember that we legalized the chain.
4408 Hi = LegalizeOp(Hi);
4409 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4410 if (!TLI.isLittleEndian())
4416 LoadSDNode *LD = cast<LoadSDNode>(Node);
4417 SDOperand Ch = LD->getChain(); // Legalize the chain.
4418 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
4419 ISD::LoadExtType ExtType = LD->getExtensionType();
4421 if (ExtType == ISD::NON_EXTLOAD) {
4422 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset());
4424 // Increment the pointer to the other half.
4425 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4426 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4427 getIntPtrConstant(IncrementSize));
4428 // FIXME: This creates a bogus srcvalue!
4429 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset());
4431 // Build a factor node to remember that this load is independent of the
4433 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4436 // Remember that we legalized the chain.
4437 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4438 if (!TLI.isLittleEndian())
4441 MVT::ValueType EVT = LD->getLoadVT();
4444 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
4445 LD->getSrcValueOffset());
4447 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
4448 LD->getSrcValueOffset(), EVT);
4450 // Remember that we legalized the chain.
4451 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4453 if (ExtType == ISD::SEXTLOAD) {
4454 // The high part is obtained by SRA'ing all but one of the bits of the
4456 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4457 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4458 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4459 } else if (ExtType == ISD::ZEXTLOAD) {
4460 // The high part is just a zero.
4461 Hi = DAG.getConstant(0, NVT);
4462 } else /* if (ExtType == ISD::EXTLOAD) */ {
4463 // The high part is undefined.
4464 Hi = DAG.getNode(ISD::UNDEF, NVT);
4471 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
4472 SDOperand LL, LH, RL, RH;
4473 ExpandOp(Node->getOperand(0), LL, LH);
4474 ExpandOp(Node->getOperand(1), RL, RH);
4475 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4476 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4480 SDOperand LL, LH, RL, RH;
4481 ExpandOp(Node->getOperand(1), LL, LH);
4482 ExpandOp(Node->getOperand(2), RL, RH);
4483 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4484 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4487 case ISD::SELECT_CC: {
4488 SDOperand TL, TH, FL, FH;
4489 ExpandOp(Node->getOperand(2), TL, TH);
4490 ExpandOp(Node->getOperand(3), FL, FH);
4491 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4492 Node->getOperand(1), TL, FL, Node->getOperand(4));
4493 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4494 Node->getOperand(1), TH, FH, Node->getOperand(4));
4497 case ISD::ANY_EXTEND:
4498 // The low part is any extension of the input (which degenerates to a copy).
4499 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4500 // The high part is undefined.
4501 Hi = DAG.getNode(ISD::UNDEF, NVT);
4503 case ISD::SIGN_EXTEND: {
4504 // The low part is just a sign extension of the input (which degenerates to
4506 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4508 // The high part is obtained by SRA'ing all but one of the bits of the lo
4510 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4511 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4512 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4515 case ISD::ZERO_EXTEND:
4516 // The low part is just a zero extension of the input (which degenerates to
4518 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4520 // The high part is just a zero.
4521 Hi = DAG.getConstant(0, NVT);
4524 case ISD::BIT_CONVERT: {
4526 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
4527 // If the target wants to, allow it to lower this itself.
4528 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4529 case Expand: assert(0 && "cannot expand FP!");
4530 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
4531 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
4533 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
4536 // Turn this into a load/store pair by default.
4538 Tmp = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
4540 ExpandOp(Tmp, Lo, Hi);
4544 case ISD::READCYCLECOUNTER:
4545 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
4546 TargetLowering::Custom &&
4547 "Must custom expand ReadCycleCounter");
4548 Lo = TLI.LowerOperation(Op, DAG);
4549 assert(Lo.Val && "Node must be custom expanded!");
4550 Hi = Lo.getValue(1);
4551 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
4552 LegalizeOp(Lo.getValue(2)));
4555 // These operators cannot be expanded directly, emit them as calls to
4556 // library functions.
4557 case ISD::FP_TO_SINT:
4558 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
4560 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4561 case Expand: assert(0 && "cannot expand FP!");
4562 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4563 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4566 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
4568 // Now that the custom expander is done, expand the result, which is still
4571 ExpandOp(Op, Lo, Hi);
4576 if (Node->getOperand(0).getValueType() == MVT::f32)
4577 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
4579 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
4582 case ISD::FP_TO_UINT:
4583 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
4585 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4586 case Expand: assert(0 && "cannot expand FP!");
4587 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4588 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4591 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
4593 // Now that the custom expander is done, expand the result.
4595 ExpandOp(Op, Lo, Hi);
4600 if (Node->getOperand(0).getValueType() == MVT::f32)
4601 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
4603 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
4607 // If the target wants custom lowering, do so.
4608 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4609 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
4610 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
4611 Op = TLI.LowerOperation(Op, DAG);
4613 // Now that the custom expander is done, expand the result, which is
4615 ExpandOp(Op, Lo, Hi);
4620 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
4621 // this X << 1 as X+X.
4622 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
4623 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
4624 TLI.isOperationLegal(ISD::ADDE, NVT)) {
4625 SDOperand LoOps[2], HiOps[3];
4626 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
4627 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
4628 LoOps[1] = LoOps[0];
4629 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
4631 HiOps[1] = HiOps[0];
4632 HiOps[2] = Lo.getValue(1);
4633 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
4638 // If we can emit an efficient shift operation, do so now.
4639 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4642 // If this target supports SHL_PARTS, use it.
4643 TargetLowering::LegalizeAction Action =
4644 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
4645 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4646 Action == TargetLowering::Custom) {
4647 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4651 // Otherwise, emit a libcall.
4652 Lo = ExpandLibCall("__ashldi3", Node, Hi);
4657 // If the target wants custom lowering, do so.
4658 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4659 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
4660 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
4661 Op = TLI.LowerOperation(Op, DAG);
4663 // Now that the custom expander is done, expand the result, which is
4665 ExpandOp(Op, Lo, Hi);
4670 // If we can emit an efficient shift operation, do so now.
4671 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
4674 // If this target supports SRA_PARTS, use it.
4675 TargetLowering::LegalizeAction Action =
4676 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
4677 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4678 Action == TargetLowering::Custom) {
4679 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4683 // Otherwise, emit a libcall.
4684 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
4689 // If the target wants custom lowering, do so.
4690 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4691 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
4692 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
4693 Op = TLI.LowerOperation(Op, DAG);
4695 // Now that the custom expander is done, expand the result, which is
4697 ExpandOp(Op, Lo, Hi);
4702 // If we can emit an efficient shift operation, do so now.
4703 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4706 // If this target supports SRL_PARTS, use it.
4707 TargetLowering::LegalizeAction Action =
4708 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
4709 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4710 Action == TargetLowering::Custom) {
4711 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4715 // Otherwise, emit a libcall.
4716 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
4722 // If the target wants to custom expand this, let them.
4723 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
4724 TargetLowering::Custom) {
4725 Op = TLI.LowerOperation(Op, DAG);
4727 ExpandOp(Op, Lo, Hi);
4732 // Expand the subcomponents.
4733 SDOperand LHSL, LHSH, RHSL, RHSH;
4734 ExpandOp(Node->getOperand(0), LHSL, LHSH);
4735 ExpandOp(Node->getOperand(1), RHSL, RHSH);
4736 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
4737 SDOperand LoOps[2], HiOps[3];
4742 if (Node->getOpcode() == ISD::ADD) {
4743 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
4744 HiOps[2] = Lo.getValue(1);
4745 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
4747 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
4748 HiOps[2] = Lo.getValue(1);
4749 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
4754 // If the target wants to custom expand this, let them.
4755 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
4756 SDOperand New = TLI.LowerOperation(Op, DAG);
4758 ExpandOp(New, Lo, Hi);
4763 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
4764 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
4765 bool UseLibCall = true;
4766 if (HasMULHS || HasMULHU) {
4767 SDOperand LL, LH, RL, RH;
4768 ExpandOp(Node->getOperand(0), LL, LH);
4769 ExpandOp(Node->getOperand(1), RL, RH);
4770 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
4771 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
4772 // extended the sign bit of the low half through the upper half, and if so
4773 // emit a MULHS instead of the alternate sequence that is valid for any
4774 // i64 x i64 multiply.
4776 // is RH an extension of the sign bit of RL?
4777 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
4778 RH.getOperand(1).getOpcode() == ISD::Constant &&
4779 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
4780 // is LH an extension of the sign bit of LL?
4781 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
4782 LH.getOperand(1).getOpcode() == ISD::Constant &&
4783 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
4784 // FIXME: Move this to the dag combiner.
4787 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4789 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
4791 } else if (HasMULHU) {
4793 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4796 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
4797 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
4798 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
4799 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
4800 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
4805 Lo = ExpandLibCall("__muldi3" , Node, Hi);
4808 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
4809 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
4810 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
4811 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
4814 // Make sure the resultant values have been legalized themselves, unless this
4815 // is a type that requires multi-step expansion.
4816 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
4817 Lo = LegalizeOp(Lo);
4818 Hi = LegalizeOp(Hi);
4821 // Remember in a map if the values will be reused later.
4823 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4824 assert(isNew && "Value already expanded?!?");
4827 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
4828 /// two smaller values of MVT::Vector type.
4829 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
4831 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
4832 SDNode *Node = Op.Val;
4833 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
4834 assert(NumElements > 1 && "Cannot split a single element vector!");
4835 unsigned NewNumElts = NumElements/2;
4836 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
4837 SDOperand TypeNode = *(Node->op_end()-1);
4839 // See if we already split it.
4840 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4841 = SplitNodes.find(Op);
4842 if (I != SplitNodes.end()) {
4843 Lo = I->second.first;
4844 Hi = I->second.second;
4848 switch (Node->getOpcode()) {
4853 assert(0 && "Unhandled operation in SplitVectorOp!");
4854 case ISD::VBUILD_VECTOR: {
4855 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
4856 Node->op_begin()+NewNumElts);
4857 LoOps.push_back(NewNumEltsNode);
4858 LoOps.push_back(TypeNode);
4859 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size());
4861 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
4863 HiOps.push_back(NewNumEltsNode);
4864 HiOps.push_back(TypeNode);
4865 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size());
4876 SDOperand LL, LH, RL, RH;
4877 SplitVectorOp(Node->getOperand(0), LL, LH);
4878 SplitVectorOp(Node->getOperand(1), RL, RH);
4880 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
4881 NewNumEltsNode, TypeNode);
4882 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
4883 NewNumEltsNode, TypeNode);
4887 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4888 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4889 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4891 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4892 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
4893 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4894 getIntPtrConstant(IncrementSize));
4895 // FIXME: This creates a bogus srcvalue!
4896 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4898 // Build a factor node to remember that this load is independent of the
4900 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4903 // Remember that we legalized the chain.
4904 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4907 case ISD::VBIT_CONVERT: {
4908 // We know the result is a vector. The input may be either a vector or a
4910 if (Op.getOperand(0).getValueType() != MVT::Vector) {
4911 // Lower to a store/load. FIXME: this could be improved probably.
4912 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
4914 SDOperand St = DAG.getStore(DAG.getEntryNode(),
4915 Op.getOperand(0), Ptr, DAG.getSrcValue(0));
4916 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4917 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0));
4918 SplitVectorOp(St, Lo, Hi);
4920 // If the input is a vector type, we have to either scalarize it, pack it
4921 // or convert it based on whether the input vector type is legal.
4922 SDNode *InVal = Node->getOperand(0).Val;
4924 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
4925 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
4927 // If the input is from a single element vector, scalarize the vector,
4928 // then treat like a scalar.
4929 if (NumElems == 1) {
4930 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT);
4931 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar,
4932 Op.getOperand(1), Op.getOperand(2));
4933 SplitVectorOp(Scalar, Lo, Hi);
4935 // Split the input vector.
4936 SplitVectorOp(Op.getOperand(0), Lo, Hi);
4938 // Convert each of the pieces now.
4939 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo,
4940 NewNumEltsNode, TypeNode);
4941 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi,
4942 NewNumEltsNode, TypeNode);
4949 // Remember in a map if the values will be reused later.
4951 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4952 assert(isNew && "Value already expanded?!?");
4956 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
4957 /// equivalent operation that returns a scalar (e.g. F32) or packed value
4958 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
4959 /// type for the result.
4960 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
4961 MVT::ValueType NewVT) {
4962 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
4963 SDNode *Node = Op.Val;
4965 // See if we already packed it.
4966 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
4967 if (I != PackedNodes.end()) return I->second;
4970 switch (Node->getOpcode()) {
4973 Node->dump(); std::cerr << "\n";
4975 assert(0 && "Unknown vector operation in PackVectorOp!");
4984 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
4986 PackVectorOp(Node->getOperand(0), NewVT),
4987 PackVectorOp(Node->getOperand(1), NewVT));
4990 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
4991 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
4993 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
4994 Result = DAG.getLoad(NewVT, Ch, Ptr, SV->getValue(), SV->getOffset());
4996 // Remember that we legalized the chain.
4997 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
5000 case ISD::VBUILD_VECTOR:
5001 if (Node->getOperand(0).getValueType() == NewVT) {
5002 // Returning a scalar?
5003 Result = Node->getOperand(0);
5005 // Returning a BUILD_VECTOR?
5007 // If all elements of the build_vector are undefs, return an undef.
5008 bool AllUndef = true;
5009 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i)
5010 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) {
5015 Result = DAG.getNode(ISD::UNDEF, NewVT);
5017 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(),
5018 Node->getNumOperands()-2);
5022 case ISD::VINSERT_VECTOR_ELT:
5023 if (!MVT::isVector(NewVT)) {
5024 // Returning a scalar? Must be the inserted element.
5025 Result = Node->getOperand(1);
5027 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
5028 PackVectorOp(Node->getOperand(0), NewVT),
5029 Node->getOperand(1), Node->getOperand(2));
5032 case ISD::VVECTOR_SHUFFLE:
5033 if (!MVT::isVector(NewVT)) {
5034 // Returning a scalar? Figure out if it is the LHS or RHS and return it.
5035 SDOperand EltNum = Node->getOperand(2).getOperand(0);
5036 if (cast<ConstantSDNode>(EltNum)->getValue())
5037 Result = PackVectorOp(Node->getOperand(1), NewVT);
5039 Result = PackVectorOp(Node->getOperand(0), NewVT);
5041 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index
5042 // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
5043 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
5044 Node->getOperand(2).Val->op_end()-2);
5045 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
5046 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT,
5047 Node->getOperand(2).Val->op_begin(),
5048 Node->getOperand(2).Val->getNumOperands()-2);
5050 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
5051 PackVectorOp(Node->getOperand(0), NewVT),
5052 PackVectorOp(Node->getOperand(1), NewVT), BV);
5055 case ISD::VBIT_CONVERT:
5056 if (Op.getOperand(0).getValueType() != MVT::Vector)
5057 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
5059 // If the input is a vector type, we have to either scalarize it, pack it
5060 // or convert it based on whether the input vector type is legal.
5061 SDNode *InVal = Node->getOperand(0).Val;
5063 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
5064 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
5066 // Figure out if there is a Packed type corresponding to this Vector
5067 // type. If so, convert to the packed type.
5068 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
5069 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
5070 // Turn this into a bit convert of the packed input.
5071 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5072 PackVectorOp(Node->getOperand(0), TVT));
5074 } else if (NumElems == 1) {
5075 // Turn this into a bit convert of the scalar input.
5076 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5077 PackVectorOp(Node->getOperand(0), EVT));
5081 assert(0 && "Cast from unsupported vector type not implemented yet!");
5086 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
5087 PackVectorOp(Op.getOperand(1), NewVT),
5088 PackVectorOp(Op.getOperand(2), NewVT));
5092 if (TLI.isTypeLegal(NewVT))
5093 Result = LegalizeOp(Result);
5094 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
5095 assert(isNew && "Value already packed?");
5100 // SelectionDAG::Legalize - This is the entry point for the file.
5102 void SelectionDAG::Legalize() {
5103 if (ViewLegalizeDAGs) viewGraph();
5105 /// run - This is the main entry point to this class.
5107 SelectionDAGLegalize(*this).LegalizeDAG();