1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/Support/MathExtras.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Compiler.h"
27 #include "llvm/ADT/SmallVector.h"
33 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
34 cl::desc("Pop up a window to show dags before legalize"));
36 static const bool ViewLegalizeDAGs = 0;
39 //===----------------------------------------------------------------------===//
40 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
41 /// hacks on it until the target machine can handle it. This involves
42 /// eliminating value sizes the machine cannot handle (promoting small sizes to
43 /// large sizes or splitting up large values into small values) as well as
44 /// eliminating operations the machine cannot handle.
46 /// This code also does a small amount of optimization and recognition of idioms
47 /// as part of its processing. For example, if a target does not support a
48 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
49 /// will attempt merge setcc and brc instructions into brcc's.
52 class VISIBILITY_HIDDEN SelectionDAGLegalize {
56 // Libcall insertion helpers.
58 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
59 /// legalized. We use this to ensure that calls are properly serialized
60 /// against each other, including inserted libcalls.
61 SDOperand LastCALLSEQ_END;
63 /// IsLegalizingCall - This member is used *only* for purposes of providing
64 /// helpful assertions that a libcall isn't created while another call is
65 /// being legalized (which could lead to non-serialized call sequences).
66 bool IsLegalizingCall;
69 Legal, // The target natively supports this operation.
70 Promote, // This operation should be executed in a larger type.
71 Expand // Try to expand this to other ops, otherwise use a libcall.
74 /// ValueTypeActions - This is a bitvector that contains two bits for each
75 /// value type, where the two bits correspond to the LegalizeAction enum.
76 /// This can be queried with "getTypeAction(VT)".
77 TargetLowering::ValueTypeActionImpl ValueTypeActions;
79 /// LegalizedNodes - For nodes that are of legal width, and that have more
80 /// than one use, this map indicates what regularized operand to use. This
81 /// allows us to avoid legalizing the same thing more than once.
82 std::map<SDOperand, SDOperand> LegalizedNodes;
84 /// PromotedNodes - For nodes that are below legal width, and that have more
85 /// than one use, this map indicates what promoted value to use. This allows
86 /// us to avoid promoting the same thing more than once.
87 std::map<SDOperand, SDOperand> PromotedNodes;
89 /// ExpandedNodes - For nodes that need to be expanded this map indicates
90 /// which which operands are the expanded version of the input. This allows
91 /// us to avoid expanding the same node more than once.
92 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
94 /// SplitNodes - For vector nodes that need to be split, this map indicates
95 /// which which operands are the split version of the input. This allows us
96 /// to avoid splitting the same node more than once.
97 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
99 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
100 /// concrete packed types, this contains the mapping of ones we have already
101 /// processed to the result.
102 std::map<SDOperand, SDOperand> PackedNodes;
104 void AddLegalizedOperand(SDOperand From, SDOperand To) {
105 LegalizedNodes.insert(std::make_pair(From, To));
106 // If someone requests legalization of the new node, return itself.
108 LegalizedNodes.insert(std::make_pair(To, To));
110 void AddPromotedOperand(SDOperand From, SDOperand To) {
111 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
112 assert(isNew && "Got into the map somehow?");
113 // If someone requests legalization of the new node, return itself.
114 LegalizedNodes.insert(std::make_pair(To, To));
119 SelectionDAGLegalize(SelectionDAG &DAG);
121 /// getTypeAction - Return how we should legalize values of this type, either
122 /// it is already legal or we need to expand it into multiple registers of
123 /// smaller integer type, or we need to promote it to a larger type.
124 LegalizeAction getTypeAction(MVT::ValueType VT) const {
125 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
128 /// isTypeLegal - Return true if this type is legal on this target.
130 bool isTypeLegal(MVT::ValueType VT) const {
131 return getTypeAction(VT) == Legal;
137 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
138 /// appropriate for its type.
139 void HandleOp(SDOperand Op);
141 /// LegalizeOp - We know that the specified value has a legal type.
142 /// Recursively ensure that the operands have legal types, then return the
144 SDOperand LegalizeOp(SDOperand O);
146 /// PromoteOp - Given an operation that produces a value in an invalid type,
147 /// promote it to compute the value into a larger type. The produced value
148 /// will have the correct bits for the low portion of the register, but no
149 /// guarantee is made about the top bits: it may be zero, sign-extended, or
151 SDOperand PromoteOp(SDOperand O);
153 /// ExpandOp - Expand the specified SDOperand into its two component pieces
154 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
155 /// the LegalizeNodes map is filled in for any results that are not expanded,
156 /// the ExpandedNodes map is filled in for any results that are expanded, and
157 /// the Lo/Hi values are returned. This applies to integer types and Vector
159 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
161 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
162 /// two smaller values of MVT::Vector type.
163 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
165 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
166 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
167 /// this is called, we know that PackedVT is the right type for the result and
168 /// we know that this type is legal for the target.
169 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
171 /// isShuffleLegal - Return true if a vector shuffle is legal with the
172 /// specified mask and type. Targets can specify exactly which masks they
173 /// support and the code generator is tasked with not creating illegal masks.
175 /// Note that this will also return true for shuffles that are promoted to a
178 /// If this is a legal shuffle, this method returns the (possibly promoted)
179 /// build_vector Mask. If it's not a legal shuffle, it returns null.
180 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
182 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
183 std::set<SDNode*> &NodesLeadingTo);
185 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
187 SDOperand CreateStackTemporary(MVT::ValueType VT);
189 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
191 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
194 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
195 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
196 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
197 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
199 MVT::ValueType DestVT);
200 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
202 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
205 SDOperand ExpandBSWAP(SDOperand Op);
206 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
207 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
208 SDOperand &Lo, SDOperand &Hi);
209 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
210 SDOperand &Lo, SDOperand &Hi);
212 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
213 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
215 SDOperand getIntPtrConstant(uint64_t Val) {
216 return DAG.getConstant(Val, TLI.getPointerTy());
221 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
222 /// specified mask and type. Targets can specify exactly which masks they
223 /// support and the code generator is tasked with not creating illegal masks.
225 /// Note that this will also return true for shuffles that are promoted to a
227 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
228 SDOperand Mask) const {
229 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
231 case TargetLowering::Legal:
232 case TargetLowering::Custom:
234 case TargetLowering::Promote: {
235 // If this is promoted to a different type, convert the shuffle mask and
236 // ask if it is legal in the promoted type!
237 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
239 // If we changed # elements, change the shuffle mask.
240 unsigned NumEltsGrowth =
241 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
242 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
243 if (NumEltsGrowth > 1) {
244 // Renumber the elements.
245 SmallVector<SDOperand, 8> Ops;
246 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
247 SDOperand InOp = Mask.getOperand(i);
248 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
249 if (InOp.getOpcode() == ISD::UNDEF)
250 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
252 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
253 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
257 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
263 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
266 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
267 /// specified vector opcode.
268 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
270 default: assert(0 && "Don't know how to scalarize this opcode!");
271 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
272 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
273 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
274 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
275 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
276 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
277 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
278 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
282 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
283 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
284 ValueTypeActions(TLI.getValueTypeActions()) {
285 assert(MVT::LAST_VALUETYPE <= 32 &&
286 "Too many value types for ValueTypeActions to hold!");
289 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
290 /// not been visited yet and if all of its operands have already been visited.
291 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
292 std::map<SDNode*, unsigned> &Visited) {
293 if (++Visited[N] != N->getNumOperands())
294 return; // Haven't visited all operands yet
298 if (N->hasOneUse()) { // Tail recurse in common case.
299 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
303 // Now that we have N in, add anything that uses it if all of their operands
305 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
306 ComputeTopDownOrdering(*UI, Order, Visited);
310 void SelectionDAGLegalize::LegalizeDAG() {
311 LastCALLSEQ_END = DAG.getEntryNode();
312 IsLegalizingCall = false;
314 // The legalize process is inherently a bottom-up recursive process (users
315 // legalize their uses before themselves). Given infinite stack space, we
316 // could just start legalizing on the root and traverse the whole graph. In
317 // practice however, this causes us to run out of stack space on large basic
318 // blocks. To avoid this problem, compute an ordering of the nodes where each
319 // node is only legalized after all of its operands are legalized.
320 std::map<SDNode*, unsigned> Visited;
321 std::vector<SDNode*> Order;
323 // Compute ordering from all of the leaves in the graphs, those (like the
324 // entry node) that have no operands.
325 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
326 E = DAG.allnodes_end(); I != E; ++I) {
327 if (I->getNumOperands() == 0) {
329 ComputeTopDownOrdering(I, Order, Visited);
333 assert(Order.size() == Visited.size() &&
335 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
336 "Error: DAG is cyclic!");
339 for (unsigned i = 0, e = Order.size(); i != e; ++i)
340 HandleOp(SDOperand(Order[i], 0));
342 // Finally, it's possible the root changed. Get the new root.
343 SDOperand OldRoot = DAG.getRoot();
344 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
345 DAG.setRoot(LegalizedNodes[OldRoot]);
347 ExpandedNodes.clear();
348 LegalizedNodes.clear();
349 PromotedNodes.clear();
353 // Remove dead nodes now.
354 DAG.RemoveDeadNodes();
358 /// FindCallEndFromCallStart - Given a chained node that is part of a call
359 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
360 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
361 if (Node->getOpcode() == ISD::CALLSEQ_END)
363 if (Node->use_empty())
364 return 0; // No CallSeqEnd
366 // The chain is usually at the end.
367 SDOperand TheChain(Node, Node->getNumValues()-1);
368 if (TheChain.getValueType() != MVT::Other) {
369 // Sometimes it's at the beginning.
370 TheChain = SDOperand(Node, 0);
371 if (TheChain.getValueType() != MVT::Other) {
372 // Otherwise, hunt for it.
373 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
374 if (Node->getValueType(i) == MVT::Other) {
375 TheChain = SDOperand(Node, i);
379 // Otherwise, we walked into a node without a chain.
380 if (TheChain.getValueType() != MVT::Other)
385 for (SDNode::use_iterator UI = Node->use_begin(),
386 E = Node->use_end(); UI != E; ++UI) {
388 // Make sure to only follow users of our token chain.
390 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
391 if (User->getOperand(i) == TheChain)
392 if (SDNode *Result = FindCallEndFromCallStart(User))
398 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
399 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
400 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
401 assert(Node && "Didn't find callseq_start for a call??");
402 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
404 assert(Node->getOperand(0).getValueType() == MVT::Other &&
405 "Node doesn't have a token chain argument!");
406 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
409 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
410 /// see if any uses can reach Dest. If no dest operands can get to dest,
411 /// legalize them, legalize ourself, and return false, otherwise, return true.
413 /// Keep track of the nodes we fine that actually do lead to Dest in
414 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
416 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
417 std::set<SDNode*> &NodesLeadingTo) {
418 if (N == Dest) return true; // N certainly leads to Dest :)
420 // If we've already processed this node and it does lead to Dest, there is no
421 // need to reprocess it.
422 if (NodesLeadingTo.count(N)) return true;
424 // If the first result of this node has been already legalized, then it cannot
426 switch (getTypeAction(N->getValueType(0))) {
428 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
431 if (PromotedNodes.count(SDOperand(N, 0))) return false;
434 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
438 // Okay, this node has not already been legalized. Check and legalize all
439 // operands. If none lead to Dest, then we can legalize this node.
440 bool OperandsLeadToDest = false;
441 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
442 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
443 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
445 if (OperandsLeadToDest) {
446 NodesLeadingTo.insert(N);
450 // Okay, this node looks safe, legalize it and return false.
451 HandleOp(SDOperand(N, 0));
455 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
456 /// appropriate for its type.
457 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
458 switch (getTypeAction(Op.getValueType())) {
459 default: assert(0 && "Bad type action!");
460 case Legal: LegalizeOp(Op); break;
461 case Promote: PromoteOp(Op); break;
463 if (Op.getValueType() != MVT::Vector) {
468 unsigned NumOps = N->getNumOperands();
469 unsigned NumElements =
470 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
471 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
472 MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
473 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
474 // In the common case, this is a legal vector type, convert it to the
475 // packed operation and type now.
476 PackVectorOp(Op, PackedVT);
477 } else if (NumElements == 1) {
478 // Otherwise, if this is a single element vector, convert it to a
480 PackVectorOp(Op, EVT);
482 // Otherwise, this is a multiple element vector that isn't supported.
483 // Split it in half and legalize both parts.
485 SplitVectorOp(Op, X, Y);
492 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
493 /// a load from the constant pool.
494 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
495 SelectionDAG &DAG, TargetLowering &TLI) {
498 // If a FP immediate is precise when represented as a float and if the
499 // target can do an extending load from float to double, we put it into
500 // the constant pool as a float, even if it's is statically typed as a
502 MVT::ValueType VT = CFP->getValueType(0);
503 bool isDouble = VT == MVT::f64;
504 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
505 Type::FloatTy, CFP->getValue());
507 double Val = LLVMC->getValue();
509 ? DAG.getConstant(DoubleToBits(Val), MVT::i64)
510 : DAG.getConstant(FloatToBits(Val), MVT::i32);
513 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
514 // Only do this if the target has a native EXTLOAD instruction from f32.
515 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
516 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
521 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
523 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
524 CPIdx, NULL, 0, MVT::f32);
526 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
531 /// LegalizeOp - We know that the specified value has a legal type.
532 /// Recursively ensure that the operands have legal types, then return the
534 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
535 assert(isTypeLegal(Op.getValueType()) &&
536 "Caller should expand or promote operands that are not legal!");
537 SDNode *Node = Op.Val;
539 // If this operation defines any values that cannot be represented in a
540 // register on this target, make sure to expand or promote them.
541 if (Node->getNumValues() > 1) {
542 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
543 if (getTypeAction(Node->getValueType(i)) != Legal) {
544 HandleOp(Op.getValue(i));
545 assert(LegalizedNodes.count(Op) &&
546 "Handling didn't add legal operands!");
547 return LegalizedNodes[Op];
551 // Note that LegalizeOp may be reentered even from single-use nodes, which
552 // means that we always must cache transformed nodes.
553 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
554 if (I != LegalizedNodes.end()) return I->second;
556 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
557 SDOperand Result = Op;
558 bool isCustom = false;
560 switch (Node->getOpcode()) {
561 case ISD::FrameIndex:
562 case ISD::EntryToken:
564 case ISD::BasicBlock:
565 case ISD::TargetFrameIndex:
566 case ISD::TargetJumpTable:
567 case ISD::TargetConstant:
568 case ISD::TargetConstantFP:
569 case ISD::TargetConstantPool:
570 case ISD::TargetGlobalAddress:
571 case ISD::TargetExternalSymbol:
576 case ISD::GLOBAL_OFFSET_TABLE:
577 // Primitives must all be legal.
578 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
579 "This must be legal!");
582 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
583 // If this is a target node, legalize it by legalizing the operands then
584 // passing it through.
585 SmallVector<SDOperand, 8> Ops;
586 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
587 Ops.push_back(LegalizeOp(Node->getOperand(i)));
589 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
591 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
592 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
593 return Result.getValue(Op.ResNo);
595 // Otherwise this is an unhandled builtin node. splat.
597 cerr << "NODE: "; Node->dump(); cerr << "\n";
599 assert(0 && "Do not know how to legalize this operator!");
601 case ISD::GlobalAddress:
602 case ISD::ExternalSymbol:
603 case ISD::ConstantPool:
604 case ISD::JumpTable: // Nothing to do.
605 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
606 default: assert(0 && "This action is not supported yet!");
607 case TargetLowering::Custom:
608 Tmp1 = TLI.LowerOperation(Op, DAG);
609 if (Tmp1.Val) Result = Tmp1;
610 // FALLTHROUGH if the target doesn't want to lower this op after all.
611 case TargetLowering::Legal:
615 case ISD::AssertSext:
616 case ISD::AssertZext:
617 Tmp1 = LegalizeOp(Node->getOperand(0));
618 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
620 case ISD::MERGE_VALUES:
621 // Legalize eliminates MERGE_VALUES nodes.
622 Result = Node->getOperand(Op.ResNo);
624 case ISD::CopyFromReg:
625 Tmp1 = LegalizeOp(Node->getOperand(0));
626 Result = Op.getValue(0);
627 if (Node->getNumValues() == 2) {
628 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
630 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
631 if (Node->getNumOperands() == 3) {
632 Tmp2 = LegalizeOp(Node->getOperand(2));
633 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
635 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
637 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
639 // Since CopyFromReg produces two values, make sure to remember that we
640 // legalized both of them.
641 AddLegalizedOperand(Op.getValue(0), Result);
642 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
643 return Result.getValue(Op.ResNo);
645 MVT::ValueType VT = Op.getValueType();
646 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
647 default: assert(0 && "This action is not supported yet!");
648 case TargetLowering::Expand:
649 if (MVT::isInteger(VT))
650 Result = DAG.getConstant(0, VT);
651 else if (MVT::isFloatingPoint(VT))
652 Result = DAG.getConstantFP(0, VT);
654 assert(0 && "Unknown value type!");
656 case TargetLowering::Legal:
662 case ISD::INTRINSIC_W_CHAIN:
663 case ISD::INTRINSIC_WO_CHAIN:
664 case ISD::INTRINSIC_VOID: {
665 SmallVector<SDOperand, 8> Ops;
666 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
667 Ops.push_back(LegalizeOp(Node->getOperand(i)));
668 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
670 // Allow the target to custom lower its intrinsics if it wants to.
671 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
672 TargetLowering::Custom) {
673 Tmp3 = TLI.LowerOperation(Result, DAG);
674 if (Tmp3.Val) Result = Tmp3;
677 if (Result.Val->getNumValues() == 1) break;
679 // Must have return value and chain result.
680 assert(Result.Val->getNumValues() == 2 &&
681 "Cannot return more than two values!");
683 // Since loads produce two values, make sure to remember that we
684 // legalized both of them.
685 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
686 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
687 return Result.getValue(Op.ResNo);
691 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
692 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
694 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
695 case TargetLowering::Promote:
696 default: assert(0 && "This action is not supported yet!");
697 case TargetLowering::Expand: {
698 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
699 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
700 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
702 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
703 const std::string &FName =
704 cast<StringSDNode>(Node->getOperand(3))->getValue();
705 const std::string &DirName =
706 cast<StringSDNode>(Node->getOperand(4))->getValue();
707 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
709 SmallVector<SDOperand, 8> Ops;
710 Ops.push_back(Tmp1); // chain
711 SDOperand LineOp = Node->getOperand(1);
712 SDOperand ColOp = Node->getOperand(2);
715 Ops.push_back(LineOp); // line #
716 Ops.push_back(ColOp); // col #
717 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
718 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
720 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
721 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
722 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
723 Ops.push_back(DAG.getConstant(ID, MVT::i32));
724 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,&Ops[0],Ops.size());
727 Result = Tmp1; // chain
731 case TargetLowering::Legal:
732 if (Tmp1 != Node->getOperand(0) ||
733 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
734 SmallVector<SDOperand, 8> Ops;
736 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
737 Ops.push_back(Node->getOperand(1)); // line # must be legal.
738 Ops.push_back(Node->getOperand(2)); // col # must be legal.
740 // Otherwise promote them.
741 Ops.push_back(PromoteOp(Node->getOperand(1)));
742 Ops.push_back(PromoteOp(Node->getOperand(2)));
744 Ops.push_back(Node->getOperand(3)); // filename must be legal.
745 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
746 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
753 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
754 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
755 default: assert(0 && "This action is not supported yet!");
756 case TargetLowering::Legal:
757 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
758 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
759 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
760 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
761 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
766 case ISD::DEBUG_LABEL:
767 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
768 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
769 default: assert(0 && "This action is not supported yet!");
770 case TargetLowering::Legal:
771 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
772 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
773 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
779 // We know we don't need to expand constants here, constants only have one
780 // value and we check that it is fine above.
782 // FIXME: Maybe we should handle things like targets that don't support full
783 // 32-bit immediates?
785 case ISD::ConstantFP: {
786 // Spill FP immediates to the constant pool if the target cannot directly
787 // codegen them. Targets often have some immediate values that can be
788 // efficiently generated into an FP register without a load. We explicitly
789 // leave these constants as ConstantFP nodes for the target to deal with.
790 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
792 // Check to see if this FP immediate is already legal.
793 bool isLegal = false;
794 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
795 E = TLI.legal_fpimm_end(); I != E; ++I)
796 if (CFP->isExactlyValue(*I)) {
801 // If this is a legal constant, turn it into a TargetConstantFP node.
803 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
807 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
808 default: assert(0 && "This action is not supported yet!");
809 case TargetLowering::Custom:
810 Tmp3 = TLI.LowerOperation(Result, DAG);
816 case TargetLowering::Expand:
817 Result = ExpandConstantFP(CFP, true, DAG, TLI);
821 case ISD::TokenFactor:
822 if (Node->getNumOperands() == 2) {
823 Tmp1 = LegalizeOp(Node->getOperand(0));
824 Tmp2 = LegalizeOp(Node->getOperand(1));
825 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
826 } else if (Node->getNumOperands() == 3) {
827 Tmp1 = LegalizeOp(Node->getOperand(0));
828 Tmp2 = LegalizeOp(Node->getOperand(1));
829 Tmp3 = LegalizeOp(Node->getOperand(2));
830 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
832 SmallVector<SDOperand, 8> Ops;
833 // Legalize the operands.
834 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
835 Ops.push_back(LegalizeOp(Node->getOperand(i)));
836 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
840 case ISD::FORMAL_ARGUMENTS:
842 // The only option for this is to custom lower it.
843 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
844 assert(Tmp3.Val && "Target didn't custom lower this node!");
845 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
846 "Lowering call/formal_arguments produced unexpected # results!");
848 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
849 // remember that we legalized all of them, so it doesn't get relegalized.
850 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
851 Tmp1 = LegalizeOp(Tmp3.getValue(i));
854 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
858 case ISD::BUILD_VECTOR:
859 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
860 default: assert(0 && "This action is not supported yet!");
861 case TargetLowering::Custom:
862 Tmp3 = TLI.LowerOperation(Result, DAG);
868 case TargetLowering::Expand:
869 Result = ExpandBUILD_VECTOR(Result.Val);
873 case ISD::INSERT_VECTOR_ELT:
874 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
875 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
876 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
877 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
879 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
880 Node->getValueType(0))) {
881 default: assert(0 && "This action is not supported yet!");
882 case TargetLowering::Legal:
884 case TargetLowering::Custom:
885 Tmp3 = TLI.LowerOperation(Result, DAG);
891 case TargetLowering::Expand: {
892 // If the insert index is a constant, codegen this as a scalar_to_vector,
893 // then a shuffle that inserts it into the right position in the vector.
894 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
895 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
896 Tmp1.getValueType(), Tmp2);
898 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
899 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
900 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT);
902 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
903 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
905 SmallVector<SDOperand, 8> ShufOps;
906 for (unsigned i = 0; i != NumElts; ++i) {
907 if (i != InsertPos->getValue())
908 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
910 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
912 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
913 &ShufOps[0], ShufOps.size());
915 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
916 Tmp1, ScVec, ShufMask);
917 Result = LegalizeOp(Result);
921 // If the target doesn't support this, we have to spill the input vector
922 // to a temporary stack slot, update the element, then reload it. This is
923 // badness. We could also load the value into a vector register (either
924 // with a "move to register" or "extload into register" instruction, then
925 // permute it into place, if the idx is a constant and if the idx is
926 // supported by the target.
927 MVT::ValueType VT = Tmp1.getValueType();
928 MVT::ValueType EltVT = Tmp2.getValueType();
929 MVT::ValueType IdxVT = Tmp3.getValueType();
930 MVT::ValueType PtrVT = TLI.getPointerTy();
931 SDOperand StackPtr = CreateStackTemporary(VT);
933 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
935 // Truncate or zero extend offset to target pointer type.
936 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
937 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
938 // Add the offset to the index.
939 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
940 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
941 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
942 // Store the scalar value.
943 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
944 // Load the updated vector.
945 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
950 case ISD::SCALAR_TO_VECTOR:
951 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
952 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
956 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
957 Result = DAG.UpdateNodeOperands(Result, Tmp1);
958 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
959 Node->getValueType(0))) {
960 default: assert(0 && "This action is not supported yet!");
961 case TargetLowering::Legal:
963 case TargetLowering::Custom:
964 Tmp3 = TLI.LowerOperation(Result, DAG);
970 case TargetLowering::Expand:
971 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
975 case ISD::VECTOR_SHUFFLE:
976 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
977 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
978 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
980 // Allow targets to custom lower the SHUFFLEs they support.
981 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
982 default: assert(0 && "Unknown operation action!");
983 case TargetLowering::Legal:
984 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
985 "vector shuffle should not be created if not legal!");
987 case TargetLowering::Custom:
988 Tmp3 = TLI.LowerOperation(Result, DAG);
994 case TargetLowering::Expand: {
995 MVT::ValueType VT = Node->getValueType(0);
996 MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
997 MVT::ValueType PtrVT = TLI.getPointerTy();
998 SDOperand Mask = Node->getOperand(2);
999 unsigned NumElems = Mask.getNumOperands();
1000 SmallVector<SDOperand,8> Ops;
1001 for (unsigned i = 0; i != NumElems; ++i) {
1002 SDOperand Arg = Mask.getOperand(i);
1003 if (Arg.getOpcode() == ISD::UNDEF) {
1004 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1006 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1007 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1009 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1010 DAG.getConstant(Idx, PtrVT)));
1012 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1013 DAG.getConstant(Idx - NumElems, PtrVT)));
1016 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1019 case TargetLowering::Promote: {
1020 // Change base type to a different vector type.
1021 MVT::ValueType OVT = Node->getValueType(0);
1022 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1024 // Cast the two input vectors.
1025 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1026 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1028 // Convert the shuffle mask to the right # elements.
1029 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1030 assert(Tmp3.Val && "Shuffle not legal?");
1031 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1032 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1038 case ISD::EXTRACT_VECTOR_ELT:
1039 Tmp1 = LegalizeOp(Node->getOperand(0));
1040 Tmp2 = LegalizeOp(Node->getOperand(1));
1041 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1043 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
1044 Tmp1.getValueType())) {
1045 default: assert(0 && "This action is not supported yet!");
1046 case TargetLowering::Legal:
1048 case TargetLowering::Custom:
1049 Tmp3 = TLI.LowerOperation(Result, DAG);
1055 case TargetLowering::Expand:
1056 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1061 case ISD::VEXTRACT_VECTOR_ELT:
1062 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
1065 case ISD::CALLSEQ_START: {
1066 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1068 // Recursively Legalize all of the inputs of the call end that do not lead
1069 // to this call start. This ensures that any libcalls that need be inserted
1070 // are inserted *before* the CALLSEQ_START.
1071 {std::set<SDNode*> NodesLeadingTo;
1072 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1073 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1077 // Now that we legalized all of the inputs (which may have inserted
1078 // libcalls) create the new CALLSEQ_START node.
1079 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1081 // Merge in the last call, to ensure that this call start after the last
1083 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1084 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1085 Tmp1 = LegalizeOp(Tmp1);
1088 // Do not try to legalize the target-specific arguments (#1+).
1089 if (Tmp1 != Node->getOperand(0)) {
1090 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1092 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1095 // Remember that the CALLSEQ_START is legalized.
1096 AddLegalizedOperand(Op.getValue(0), Result);
1097 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1098 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1100 // Now that the callseq_start and all of the non-call nodes above this call
1101 // sequence have been legalized, legalize the call itself. During this
1102 // process, no libcalls can/will be inserted, guaranteeing that no calls
1104 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1105 SDOperand InCallSEQ = LastCALLSEQ_END;
1106 // Note that we are selecting this call!
1107 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1108 IsLegalizingCall = true;
1110 // Legalize the call, starting from the CALLSEQ_END.
1111 LegalizeOp(LastCALLSEQ_END);
1112 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1115 case ISD::CALLSEQ_END:
1116 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1117 // will cause this node to be legalized as well as handling libcalls right.
1118 if (LastCALLSEQ_END.Val != Node) {
1119 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1120 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1121 assert(I != LegalizedNodes.end() &&
1122 "Legalizing the call start should have legalized this node!");
1126 // Otherwise, the call start has been legalized and everything is going
1127 // according to plan. Just legalize ourselves normally here.
1128 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1129 // Do not try to legalize the target-specific arguments (#1+), except for
1130 // an optional flag input.
1131 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1132 if (Tmp1 != Node->getOperand(0)) {
1133 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1135 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1138 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1139 if (Tmp1 != Node->getOperand(0) ||
1140 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1141 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1144 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1147 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1148 // This finishes up call legalization.
1149 IsLegalizingCall = false;
1151 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1152 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1153 if (Node->getNumValues() == 2)
1154 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1155 return Result.getValue(Op.ResNo);
1156 case ISD::DYNAMIC_STACKALLOC: {
1157 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1158 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1159 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1160 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1162 Tmp1 = Result.getValue(0);
1163 Tmp2 = Result.getValue(1);
1164 switch (TLI.getOperationAction(Node->getOpcode(),
1165 Node->getValueType(0))) {
1166 default: assert(0 && "This action is not supported yet!");
1167 case TargetLowering::Expand: {
1168 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1169 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1170 " not tell us which reg is the stack pointer!");
1171 SDOperand Chain = Tmp1.getOperand(0);
1172 SDOperand Size = Tmp2.getOperand(1);
1173 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1174 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1175 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1176 Tmp1 = LegalizeOp(Tmp1);
1177 Tmp2 = LegalizeOp(Tmp2);
1180 case TargetLowering::Custom:
1181 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1183 Tmp1 = LegalizeOp(Tmp3);
1184 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1187 case TargetLowering::Legal:
1190 // Since this op produce two values, make sure to remember that we
1191 // legalized both of them.
1192 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1193 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1194 return Op.ResNo ? Tmp2 : Tmp1;
1196 case ISD::INLINEASM: {
1197 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1198 bool Changed = false;
1199 // Legalize all of the operands of the inline asm, in case they are nodes
1200 // that need to be expanded or something. Note we skip the asm string and
1201 // all of the TargetConstant flags.
1202 SDOperand Op = LegalizeOp(Ops[0]);
1203 Changed = Op != Ops[0];
1206 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1207 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1208 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1209 for (++i; NumVals; ++i, --NumVals) {
1210 SDOperand Op = LegalizeOp(Ops[i]);
1219 Op = LegalizeOp(Ops.back());
1220 Changed |= Op != Ops.back();
1225 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1227 // INLINE asm returns a chain and flag, make sure to add both to the map.
1228 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1229 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1230 return Result.getValue(Op.ResNo);
1233 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1234 // Ensure that libcalls are emitted before a branch.
1235 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1236 Tmp1 = LegalizeOp(Tmp1);
1237 LastCALLSEQ_END = DAG.getEntryNode();
1239 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1242 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1243 // Ensure that libcalls are emitted before a branch.
1244 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1245 Tmp1 = LegalizeOp(Tmp1);
1246 LastCALLSEQ_END = DAG.getEntryNode();
1248 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1249 default: assert(0 && "Indirect target must be legal type (pointer)!");
1251 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1254 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1257 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1258 // Ensure that libcalls are emitted before a branch.
1259 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1260 Tmp1 = LegalizeOp(Tmp1);
1261 LastCALLSEQ_END = DAG.getEntryNode();
1263 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1264 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1266 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1267 default: assert(0 && "This action is not supported yet!");
1268 case TargetLowering::Legal: break;
1269 case TargetLowering::Custom:
1270 Tmp1 = TLI.LowerOperation(Result, DAG);
1271 if (Tmp1.Val) Result = Tmp1;
1273 case TargetLowering::Expand: {
1274 SDOperand Chain = Result.getOperand(0);
1275 SDOperand Table = Result.getOperand(1);
1276 SDOperand Index = Result.getOperand(2);
1278 MVT::ValueType PTy = TLI.getPointerTy();
1279 MachineFunction &MF = DAG.getMachineFunction();
1280 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1281 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1282 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1285 switch (EntrySize) {
1286 default: assert(0 && "Size of jump table not supported yet."); break;
1287 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1288 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1291 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1292 // For PIC, the sequence is:
1293 // BRIND(load(Jumptable + index) + RelocBase)
1294 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
1296 if (TLI.usesGlobalOffsetTable())
1297 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
1300 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
1301 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
1302 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1304 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD);
1310 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1311 // Ensure that libcalls are emitted before a return.
1312 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1313 Tmp1 = LegalizeOp(Tmp1);
1314 LastCALLSEQ_END = DAG.getEntryNode();
1316 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1317 case Expand: assert(0 && "It's impossible to expand bools");
1319 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1322 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1324 // The top bits of the promoted condition are not necessarily zero, ensure
1325 // that the value is properly zero extended.
1326 if (!TLI.MaskedValueIsZero(Tmp2,
1327 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1328 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1332 // Basic block destination (Op#2) is always legal.
1333 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1335 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1336 default: assert(0 && "This action is not supported yet!");
1337 case TargetLowering::Legal: break;
1338 case TargetLowering::Custom:
1339 Tmp1 = TLI.LowerOperation(Result, DAG);
1340 if (Tmp1.Val) Result = Tmp1;
1342 case TargetLowering::Expand:
1343 // Expand brcond's setcc into its constituent parts and create a BR_CC
1345 if (Tmp2.getOpcode() == ISD::SETCC) {
1346 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1347 Tmp2.getOperand(0), Tmp2.getOperand(1),
1348 Node->getOperand(2));
1350 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1351 DAG.getCondCode(ISD::SETNE), Tmp2,
1352 DAG.getConstant(0, Tmp2.getValueType()),
1353 Node->getOperand(2));
1359 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1360 // Ensure that libcalls are emitted before a branch.
1361 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1362 Tmp1 = LegalizeOp(Tmp1);
1363 Tmp2 = Node->getOperand(2); // LHS
1364 Tmp3 = Node->getOperand(3); // RHS
1365 Tmp4 = Node->getOperand(1); // CC
1367 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1368 LastCALLSEQ_END = DAG.getEntryNode();
1370 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1371 // the LHS is a legal SETCC itself. In this case, we need to compare
1372 // the result against zero to select between true and false values.
1373 if (Tmp3.Val == 0) {
1374 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1375 Tmp4 = DAG.getCondCode(ISD::SETNE);
1378 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1379 Node->getOperand(4));
1381 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1382 default: assert(0 && "Unexpected action for BR_CC!");
1383 case TargetLowering::Legal: break;
1384 case TargetLowering::Custom:
1385 Tmp4 = TLI.LowerOperation(Result, DAG);
1386 if (Tmp4.Val) Result = Tmp4;
1391 LoadSDNode *LD = cast<LoadSDNode>(Node);
1392 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1393 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1395 ISD::LoadExtType ExtType = LD->getExtensionType();
1396 if (ExtType == ISD::NON_EXTLOAD) {
1397 MVT::ValueType VT = Node->getValueType(0);
1398 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1399 Tmp3 = Result.getValue(0);
1400 Tmp4 = Result.getValue(1);
1402 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1403 default: assert(0 && "This action is not supported yet!");
1404 case TargetLowering::Legal: break;
1405 case TargetLowering::Custom:
1406 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1408 Tmp3 = LegalizeOp(Tmp1);
1409 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1412 case TargetLowering::Promote: {
1413 // Only promote a load of vector type to another.
1414 assert(MVT::isVector(VT) && "Cannot promote this load!");
1415 // Change base type to a different vector type.
1416 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1418 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1419 LD->getSrcValueOffset());
1420 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1421 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1425 // Since loads produce two values, make sure to remember that we
1426 // legalized both of them.
1427 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1428 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1429 return Op.ResNo ? Tmp4 : Tmp3;
1431 MVT::ValueType SrcVT = LD->getLoadedVT();
1432 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1433 default: assert(0 && "This action is not supported yet!");
1434 case TargetLowering::Promote:
1435 assert(SrcVT == MVT::i1 &&
1436 "Can only promote extending LOAD from i1 -> i8!");
1437 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1438 LD->getSrcValue(), LD->getSrcValueOffset(),
1440 Tmp1 = Result.getValue(0);
1441 Tmp2 = Result.getValue(1);
1443 case TargetLowering::Custom:
1446 case TargetLowering::Legal:
1447 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1448 Tmp1 = Result.getValue(0);
1449 Tmp2 = Result.getValue(1);
1452 Tmp3 = TLI.LowerOperation(Result, DAG);
1454 Tmp1 = LegalizeOp(Tmp3);
1455 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1459 case TargetLowering::Expand:
1460 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1461 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1462 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1463 LD->getSrcValueOffset());
1464 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1465 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1466 Tmp2 = LegalizeOp(Load.getValue(1));
1469 assert(ExtType != ISD::EXTLOAD && "EXTLOAD should always be supported!");
1470 // Turn the unsupported load into an EXTLOAD followed by an explicit
1471 // zero/sign extend inreg.
1472 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1473 Tmp1, Tmp2, LD->getSrcValue(),
1474 LD->getSrcValueOffset(), SrcVT);
1476 if (ExtType == ISD::SEXTLOAD)
1477 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1478 Result, DAG.getValueType(SrcVT));
1480 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1481 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1482 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1485 // Since loads produce two values, make sure to remember that we legalized
1487 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1488 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1489 return Op.ResNo ? Tmp2 : Tmp1;
1492 case ISD::EXTRACT_ELEMENT: {
1493 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1494 switch (getTypeAction(OpTy)) {
1495 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1497 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1499 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1500 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1501 TLI.getShiftAmountTy()));
1502 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1505 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1506 Node->getOperand(0));
1510 // Get both the low and high parts.
1511 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1512 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1513 Result = Tmp2; // 1 -> Hi
1515 Result = Tmp1; // 0 -> Lo
1521 case ISD::CopyToReg:
1522 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1524 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1525 "Register type must be legal!");
1526 // Legalize the incoming value (must be a legal type).
1527 Tmp2 = LegalizeOp(Node->getOperand(2));
1528 if (Node->getNumValues() == 1) {
1529 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1531 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1532 if (Node->getNumOperands() == 4) {
1533 Tmp3 = LegalizeOp(Node->getOperand(3));
1534 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1537 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1540 // Since this produces two values, make sure to remember that we legalized
1542 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1543 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1549 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1551 // Ensure that libcalls are emitted before a return.
1552 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1553 Tmp1 = LegalizeOp(Tmp1);
1554 LastCALLSEQ_END = DAG.getEntryNode();
1556 switch (Node->getNumOperands()) {
1558 Tmp2 = Node->getOperand(1);
1559 Tmp3 = Node->getOperand(2); // Signness
1560 switch (getTypeAction(Tmp2.getValueType())) {
1562 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1565 if (Tmp2.getValueType() != MVT::Vector) {
1567 ExpandOp(Tmp2, Lo, Hi);
1569 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1571 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1572 Result = LegalizeOp(Result);
1574 SDNode *InVal = Tmp2.Val;
1576 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1577 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1579 // Figure out if there is a Packed type corresponding to this Vector
1580 // type. If so, convert to the packed type.
1581 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1582 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1583 // Turn this into a return of the packed type.
1584 Tmp2 = PackVectorOp(Tmp2, TVT);
1585 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1586 } else if (NumElems == 1) {
1587 // Turn this into a return of the scalar type.
1588 Tmp2 = PackVectorOp(Tmp2, EVT);
1589 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1591 // FIXME: Returns of gcc generic vectors smaller than a legal type
1592 // should be returned in integer registers!
1594 // The scalarized value type may not be legal, e.g. it might require
1595 // promotion or expansion. Relegalize the return.
1596 Result = LegalizeOp(Result);
1598 // FIXME: Returns of gcc generic vectors larger than a legal vector
1599 // type should be returned by reference!
1601 SplitVectorOp(Tmp2, Lo, Hi);
1602 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1603 Result = LegalizeOp(Result);
1608 Tmp2 = PromoteOp(Node->getOperand(1));
1609 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1610 Result = LegalizeOp(Result);
1615 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1617 default: { // ret <values>
1618 SmallVector<SDOperand, 8> NewValues;
1619 NewValues.push_back(Tmp1);
1620 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1621 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1623 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1624 NewValues.push_back(Node->getOperand(i+1));
1628 assert(Node->getOperand(i).getValueType() != MVT::Vector &&
1629 "FIXME: TODO: implement returning non-legal vector types!");
1630 ExpandOp(Node->getOperand(i), Lo, Hi);
1631 NewValues.push_back(Lo);
1632 NewValues.push_back(Node->getOperand(i+1));
1634 NewValues.push_back(Hi);
1635 NewValues.push_back(Node->getOperand(i+1));
1640 assert(0 && "Can't promote multiple return value yet!");
1643 if (NewValues.size() == Node->getNumOperands())
1644 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1646 Result = DAG.getNode(ISD::RET, MVT::Other,
1647 &NewValues[0], NewValues.size());
1652 if (Result.getOpcode() == ISD::RET) {
1653 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1654 default: assert(0 && "This action is not supported yet!");
1655 case TargetLowering::Legal: break;
1656 case TargetLowering::Custom:
1657 Tmp1 = TLI.LowerOperation(Result, DAG);
1658 if (Tmp1.Val) Result = Tmp1;
1664 StoreSDNode *ST = cast<StoreSDNode>(Node);
1665 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1666 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1668 if (!ST->isTruncatingStore()) {
1669 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1670 // FIXME: We shouldn't do this for TargetConstantFP's.
1671 // FIXME: move this to the DAG Combiner! Note that we can't regress due
1672 // to phase ordering between legalized code and the dag combiner. This
1673 // probably means that we need to integrate dag combiner and legalizer
1675 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
1676 if (CFP->getValueType(0) == MVT::f32) {
1677 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1679 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1680 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1682 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1683 ST->getSrcValueOffset());
1687 switch (getTypeAction(ST->getStoredVT())) {
1689 Tmp3 = LegalizeOp(ST->getValue());
1690 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1693 MVT::ValueType VT = Tmp3.getValueType();
1694 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1695 default: assert(0 && "This action is not supported yet!");
1696 case TargetLowering::Legal: break;
1697 case TargetLowering::Custom:
1698 Tmp1 = TLI.LowerOperation(Result, DAG);
1699 if (Tmp1.Val) Result = Tmp1;
1701 case TargetLowering::Promote:
1702 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1703 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1704 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1705 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
1706 ST->getSrcValue(), ST->getSrcValueOffset());
1712 // Truncate the value and store the result.
1713 Tmp3 = PromoteOp(ST->getValue());
1714 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1715 ST->getSrcValueOffset(), ST->getStoredVT());
1719 unsigned IncrementSize = 0;
1722 // If this is a vector type, then we have to calculate the increment as
1723 // the product of the element size in bytes, and the number of elements
1724 // in the high half of the vector.
1725 if (ST->getValue().getValueType() == MVT::Vector) {
1726 SDNode *InVal = ST->getValue().Val;
1728 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1729 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1731 // Figure out if there is a Packed type corresponding to this Vector
1732 // type. If so, convert to the packed type.
1733 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1734 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1735 // Turn this into a normal store of the packed type.
1736 Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1737 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1738 ST->getSrcValueOffset());
1739 Result = LegalizeOp(Result);
1741 } else if (NumElems == 1) {
1742 // Turn this into a normal store of the scalar type.
1743 Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1744 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1745 ST->getSrcValueOffset());
1746 // The scalarized value type may not be legal, e.g. it might require
1747 // promotion or expansion. Relegalize the scalar store.
1748 Result = LegalizeOp(Result);
1751 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1752 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1755 ExpandOp(Node->getOperand(1), Lo, Hi);
1756 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
1758 if (!TLI.isLittleEndian())
1762 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
1763 ST->getSrcValueOffset());
1765 if (Hi.Val == NULL) {
1766 // Must be int <-> float one-to-one expansion.
1771 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1772 getIntPtrConstant(IncrementSize));
1773 assert(isTypeLegal(Tmp2.getValueType()) &&
1774 "Pointers must be legal!");
1775 // FIXME: This sets the srcvalue of both halves to be the same, which is
1777 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
1778 ST->getSrcValueOffset());
1779 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1784 assert(isTypeLegal(ST->getValue().getValueType()) &&
1785 "Cannot handle illegal TRUNCSTORE yet!");
1786 Tmp3 = LegalizeOp(ST->getValue());
1788 // The only promote case we handle is TRUNCSTORE:i1 X into
1789 // -> TRUNCSTORE:i8 (and X, 1)
1790 if (ST->getStoredVT() == MVT::i1 &&
1791 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
1792 // Promote the bool to a mask then store.
1793 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
1794 DAG.getConstant(1, Tmp3.getValueType()));
1795 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1796 ST->getSrcValueOffset(), MVT::i8);
1797 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1798 Tmp2 != ST->getBasePtr()) {
1799 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1803 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
1804 switch (TLI.getStoreXAction(StVT)) {
1805 default: assert(0 && "This action is not supported yet!");
1806 case TargetLowering::Legal: break;
1807 case TargetLowering::Custom:
1808 Tmp1 = TLI.LowerOperation(Result, DAG);
1809 if (Tmp1.Val) Result = Tmp1;
1816 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1817 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1819 case ISD::STACKSAVE:
1820 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1821 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1822 Tmp1 = Result.getValue(0);
1823 Tmp2 = Result.getValue(1);
1825 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1826 default: assert(0 && "This action is not supported yet!");
1827 case TargetLowering::Legal: break;
1828 case TargetLowering::Custom:
1829 Tmp3 = TLI.LowerOperation(Result, DAG);
1831 Tmp1 = LegalizeOp(Tmp3);
1832 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1835 case TargetLowering::Expand:
1836 // Expand to CopyFromReg if the target set
1837 // StackPointerRegisterToSaveRestore.
1838 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1839 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1840 Node->getValueType(0));
1841 Tmp2 = Tmp1.getValue(1);
1843 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1844 Tmp2 = Node->getOperand(0);
1849 // Since stacksave produce two values, make sure to remember that we
1850 // legalized both of them.
1851 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1852 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1853 return Op.ResNo ? Tmp2 : Tmp1;
1855 case ISD::STACKRESTORE:
1856 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1857 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1858 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1860 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1861 default: assert(0 && "This action is not supported yet!");
1862 case TargetLowering::Legal: break;
1863 case TargetLowering::Custom:
1864 Tmp1 = TLI.LowerOperation(Result, DAG);
1865 if (Tmp1.Val) Result = Tmp1;
1867 case TargetLowering::Expand:
1868 // Expand to CopyToReg if the target set
1869 // StackPointerRegisterToSaveRestore.
1870 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1871 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1879 case ISD::READCYCLECOUNTER:
1880 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1881 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1882 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
1883 Node->getValueType(0))) {
1884 default: assert(0 && "This action is not supported yet!");
1885 case TargetLowering::Legal:
1886 Tmp1 = Result.getValue(0);
1887 Tmp2 = Result.getValue(1);
1889 case TargetLowering::Custom:
1890 Result = TLI.LowerOperation(Result, DAG);
1891 Tmp1 = LegalizeOp(Result.getValue(0));
1892 Tmp2 = LegalizeOp(Result.getValue(1));
1896 // Since rdcc produce two values, make sure to remember that we legalized
1898 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1899 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1903 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1904 case Expand: assert(0 && "It's impossible to expand bools");
1906 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1909 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1910 // Make sure the condition is either zero or one.
1911 if (!TLI.MaskedValueIsZero(Tmp1,
1912 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
1913 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1916 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1917 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1919 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1921 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1922 default: assert(0 && "This action is not supported yet!");
1923 case TargetLowering::Legal: break;
1924 case TargetLowering::Custom: {
1925 Tmp1 = TLI.LowerOperation(Result, DAG);
1926 if (Tmp1.Val) Result = Tmp1;
1929 case TargetLowering::Expand:
1930 if (Tmp1.getOpcode() == ISD::SETCC) {
1931 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1933 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1935 Result = DAG.getSelectCC(Tmp1,
1936 DAG.getConstant(0, Tmp1.getValueType()),
1937 Tmp2, Tmp3, ISD::SETNE);
1940 case TargetLowering::Promote: {
1941 MVT::ValueType NVT =
1942 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1943 unsigned ExtOp, TruncOp;
1944 if (MVT::isVector(Tmp2.getValueType())) {
1945 ExtOp = ISD::BIT_CONVERT;
1946 TruncOp = ISD::BIT_CONVERT;
1947 } else if (MVT::isInteger(Tmp2.getValueType())) {
1948 ExtOp = ISD::ANY_EXTEND;
1949 TruncOp = ISD::TRUNCATE;
1951 ExtOp = ISD::FP_EXTEND;
1952 TruncOp = ISD::FP_ROUND;
1954 // Promote each of the values to the new type.
1955 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1956 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1957 // Perform the larger operation, then round down.
1958 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1959 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1964 case ISD::SELECT_CC: {
1965 Tmp1 = Node->getOperand(0); // LHS
1966 Tmp2 = Node->getOperand(1); // RHS
1967 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1968 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1969 SDOperand CC = Node->getOperand(4);
1971 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
1973 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1974 // the LHS is a legal SETCC itself. In this case, we need to compare
1975 // the result against zero to select between true and false values.
1976 if (Tmp2.Val == 0) {
1977 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1978 CC = DAG.getCondCode(ISD::SETNE);
1980 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
1982 // Everything is legal, see if we should expand this op or something.
1983 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
1984 default: assert(0 && "This action is not supported yet!");
1985 case TargetLowering::Legal: break;
1986 case TargetLowering::Custom:
1987 Tmp1 = TLI.LowerOperation(Result, DAG);
1988 if (Tmp1.Val) Result = Tmp1;
1994 Tmp1 = Node->getOperand(0);
1995 Tmp2 = Node->getOperand(1);
1996 Tmp3 = Node->getOperand(2);
1997 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
1999 // If we had to Expand the SetCC operands into a SELECT node, then it may
2000 // not always be possible to return a true LHS & RHS. In this case, just
2001 // return the value we legalized, returned in the LHS
2002 if (Tmp2.Val == 0) {
2007 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2008 default: assert(0 && "Cannot handle this action for SETCC yet!");
2009 case TargetLowering::Custom:
2012 case TargetLowering::Legal:
2013 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2015 Tmp4 = TLI.LowerOperation(Result, DAG);
2016 if (Tmp4.Val) Result = Tmp4;
2019 case TargetLowering::Promote: {
2020 // First step, figure out the appropriate operation to use.
2021 // Allow SETCC to not be supported for all legal data types
2022 // Mostly this targets FP
2023 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2024 MVT::ValueType OldVT = NewInTy;
2026 // Scan for the appropriate larger type to use.
2028 NewInTy = (MVT::ValueType)(NewInTy+1);
2030 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2031 "Fell off of the edge of the integer world");
2032 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2033 "Fell off of the edge of the floating point world");
2035 // If the target supports SETCC of this type, use it.
2036 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2039 if (MVT::isInteger(NewInTy))
2040 assert(0 && "Cannot promote Legal Integer SETCC yet");
2042 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2043 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2045 Tmp1 = LegalizeOp(Tmp1);
2046 Tmp2 = LegalizeOp(Tmp2);
2047 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2048 Result = LegalizeOp(Result);
2051 case TargetLowering::Expand:
2052 // Expand a setcc node into a select_cc of the same condition, lhs, and
2053 // rhs that selects between const 1 (true) and const 0 (false).
2054 MVT::ValueType VT = Node->getValueType(0);
2055 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2056 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2063 case ISD::MEMMOVE: {
2064 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2065 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2067 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2068 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2069 case Expand: assert(0 && "Cannot expand a byte!");
2071 Tmp3 = LegalizeOp(Node->getOperand(2));
2074 Tmp3 = PromoteOp(Node->getOperand(2));
2078 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2082 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2084 // Length is too big, just take the lo-part of the length.
2086 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2090 Tmp4 = LegalizeOp(Node->getOperand(3));
2093 Tmp4 = PromoteOp(Node->getOperand(3));
2098 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2099 case Expand: assert(0 && "Cannot expand this yet!");
2101 Tmp5 = LegalizeOp(Node->getOperand(4));
2104 Tmp5 = PromoteOp(Node->getOperand(4));
2108 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2109 default: assert(0 && "This action not implemented for this operation!");
2110 case TargetLowering::Custom:
2113 case TargetLowering::Legal:
2114 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2116 Tmp1 = TLI.LowerOperation(Result, DAG);
2117 if (Tmp1.Val) Result = Tmp1;
2120 case TargetLowering::Expand: {
2121 // Otherwise, the target does not support this operation. Lower the
2122 // operation to an explicit libcall as appropriate.
2123 MVT::ValueType IntPtr = TLI.getPointerTy();
2124 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2125 TargetLowering::ArgListTy Args;
2126 TargetLowering::ArgListEntry Entry;
2128 const char *FnName = 0;
2129 if (Node->getOpcode() == ISD::MEMSET) {
2131 Entry.Ty = IntPtrTy;
2132 Entry.isSigned = false;
2133 Args.push_back(Entry);
2134 // Extend the (previously legalized) ubyte argument to be an int value
2136 if (Tmp3.getValueType() > MVT::i32)
2137 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2139 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2140 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSigned = true;
2141 Args.push_back(Entry);
2142 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSigned = false;
2143 Args.push_back(Entry);
2146 } else if (Node->getOpcode() == ISD::MEMCPY ||
2147 Node->getOpcode() == ISD::MEMMOVE) {
2148 Entry.Node = Tmp2; Entry.Ty = IntPtrTy; Entry.isSigned = false;
2149 Args.push_back(Entry);
2150 Entry.Node = Tmp3; Entry.Ty = IntPtrTy; Entry.isSigned = false;
2151 Args.push_back(Entry);
2152 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSigned = false;
2153 Args.push_back(Entry);
2154 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2156 assert(0 && "Unknown op!");
2159 std::pair<SDOperand,SDOperand> CallResult =
2160 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2161 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2162 Result = CallResult.second;
2169 case ISD::SHL_PARTS:
2170 case ISD::SRA_PARTS:
2171 case ISD::SRL_PARTS: {
2172 SmallVector<SDOperand, 8> Ops;
2173 bool Changed = false;
2174 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2175 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2176 Changed |= Ops.back() != Node->getOperand(i);
2179 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2181 switch (TLI.getOperationAction(Node->getOpcode(),
2182 Node->getValueType(0))) {
2183 default: assert(0 && "This action is not supported yet!");
2184 case TargetLowering::Legal: break;
2185 case TargetLowering::Custom:
2186 Tmp1 = TLI.LowerOperation(Result, DAG);
2188 SDOperand Tmp2, RetVal(0, 0);
2189 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2190 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2191 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2195 assert(RetVal.Val && "Illegal result number");
2201 // Since these produce multiple values, make sure to remember that we
2202 // legalized all of them.
2203 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2204 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2205 return Result.getValue(Op.ResNo);
2226 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2227 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2228 case Expand: assert(0 && "Not possible");
2230 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2233 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2237 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2239 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2240 default: assert(0 && "BinOp legalize operation not supported");
2241 case TargetLowering::Legal: break;
2242 case TargetLowering::Custom:
2243 Tmp1 = TLI.LowerOperation(Result, DAG);
2244 if (Tmp1.Val) Result = Tmp1;
2246 case TargetLowering::Expand: {
2247 if (Node->getValueType(0) == MVT::i32) {
2248 switch (Node->getOpcode()) {
2249 default: assert(0 && "Do not know how to expand this integer BinOp!");
2252 const char *FnName = Node->getOpcode() == ISD::UDIV
2253 ? "__udivsi3" : "__divsi3";
2255 bool isSigned = Node->getOpcode() == ISD::SDIV;
2256 Result = ExpandLibCall(FnName, Node, isSigned, Dummy);
2261 assert(MVT::isVector(Node->getValueType(0)) &&
2262 "Cannot expand this binary operator!");
2263 // Expand the operation into a bunch of nasty scalar code.
2264 SmallVector<SDOperand, 8> Ops;
2265 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
2266 MVT::ValueType PtrVT = TLI.getPointerTy();
2267 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2269 SDOperand Idx = DAG.getConstant(i, PtrVT);
2270 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2271 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2272 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2274 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2275 &Ops[0], Ops.size());
2278 case TargetLowering::Promote: {
2279 switch (Node->getOpcode()) {
2280 default: assert(0 && "Do not know how to promote this BinOp!");
2284 MVT::ValueType OVT = Node->getValueType(0);
2285 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2286 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2287 // Bit convert each of the values to the new type.
2288 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2289 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2290 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2291 // Bit convert the result back the original type.
2292 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2300 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2301 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2302 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2303 case Expand: assert(0 && "Not possible");
2305 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2308 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2312 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2314 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2315 default: assert(0 && "Operation not supported");
2316 case TargetLowering::Custom:
2317 Tmp1 = TLI.LowerOperation(Result, DAG);
2318 if (Tmp1.Val) Result = Tmp1;
2320 case TargetLowering::Legal: break;
2321 case TargetLowering::Expand:
2322 // If this target supports fabs/fneg natively, do this efficiently.
2323 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
2324 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
2325 // Get the sign bit of the RHS.
2326 MVT::ValueType IVT =
2327 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2328 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2329 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2330 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2331 // Get the absolute value of the result.
2332 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2333 // Select between the nabs and abs value based on the sign bit of
2335 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2336 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2339 Result = LegalizeOp(Result);
2343 // Otherwise, do bitwise ops!
2345 // copysign -> copysignf/copysign libcall.
2347 if (Node->getValueType(0) == MVT::f32) {
2348 FnName = "copysignf";
2349 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type.
2350 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2351 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2));
2353 FnName = "copysign";
2354 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type.
2355 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2356 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2));
2359 Result = ExpandLibCall(FnName, Node, false, Dummy);
2366 Tmp1 = LegalizeOp(Node->getOperand(0));
2367 Tmp2 = LegalizeOp(Node->getOperand(1));
2368 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2369 // Since this produces two values, make sure to remember that we legalized
2371 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2372 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2377 Tmp1 = LegalizeOp(Node->getOperand(0));
2378 Tmp2 = LegalizeOp(Node->getOperand(1));
2379 Tmp3 = LegalizeOp(Node->getOperand(2));
2380 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2381 // Since this produces two values, make sure to remember that we legalized
2383 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2384 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2387 case ISD::BUILD_PAIR: {
2388 MVT::ValueType PairTy = Node->getValueType(0);
2389 // TODO: handle the case where the Lo and Hi operands are not of legal type
2390 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2391 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2392 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2393 case TargetLowering::Promote:
2394 case TargetLowering::Custom:
2395 assert(0 && "Cannot promote/custom this yet!");
2396 case TargetLowering::Legal:
2397 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2398 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2400 case TargetLowering::Expand:
2401 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2402 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2403 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2404 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2405 TLI.getShiftAmountTy()));
2406 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2415 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2416 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2418 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2419 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2420 case TargetLowering::Custom:
2423 case TargetLowering::Legal:
2424 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2426 Tmp1 = TLI.LowerOperation(Result, DAG);
2427 if (Tmp1.Val) Result = Tmp1;
2430 case TargetLowering::Expand:
2431 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2432 bool isSigned = DivOpc == ISD::SDIV;
2433 if (MVT::isInteger(Node->getValueType(0))) {
2434 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2435 TargetLowering::Legal) {
2437 MVT::ValueType VT = Node->getValueType(0);
2438 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2439 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2440 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2442 assert(Node->getValueType(0) == MVT::i32 &&
2443 "Cannot expand this binary operator!");
2444 const char *FnName = Node->getOpcode() == ISD::UREM
2445 ? "__umodsi3" : "__modsi3";
2447 Result = ExpandLibCall(FnName, Node, isSigned, Dummy);
2450 // Floating point mod -> fmod libcall.
2451 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
2453 Result = ExpandLibCall(FnName, Node, false, Dummy);
2459 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2460 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2462 MVT::ValueType VT = Node->getValueType(0);
2463 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2464 default: assert(0 && "This action is not supported yet!");
2465 case TargetLowering::Custom:
2468 case TargetLowering::Legal:
2469 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2470 Result = Result.getValue(0);
2471 Tmp1 = Result.getValue(1);
2474 Tmp2 = TLI.LowerOperation(Result, DAG);
2476 Result = LegalizeOp(Tmp2);
2477 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2481 case TargetLowering::Expand: {
2482 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2483 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2484 SV->getValue(), SV->getOffset());
2485 // Increment the pointer, VAList, to the next vaarg
2486 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2487 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2488 TLI.getPointerTy()));
2489 // Store the incremented VAList to the legalized pointer
2490 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
2492 // Load the actual argument out of the pointer VAList
2493 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2494 Tmp1 = LegalizeOp(Result.getValue(1));
2495 Result = LegalizeOp(Result);
2499 // Since VAARG produces two values, make sure to remember that we
2500 // legalized both of them.
2501 AddLegalizedOperand(SDOperand(Node, 0), Result);
2502 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2503 return Op.ResNo ? Tmp1 : Result;
2507 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2508 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2509 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2511 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2512 default: assert(0 && "This action is not supported yet!");
2513 case TargetLowering::Custom:
2516 case TargetLowering::Legal:
2517 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2518 Node->getOperand(3), Node->getOperand(4));
2520 Tmp1 = TLI.LowerOperation(Result, DAG);
2521 if (Tmp1.Val) Result = Tmp1;
2524 case TargetLowering::Expand:
2525 // This defaults to loading a pointer from the input and storing it to the
2526 // output, returning the chain.
2527 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
2528 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
2529 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
2531 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
2538 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2539 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2541 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2542 default: assert(0 && "This action is not supported yet!");
2543 case TargetLowering::Custom:
2546 case TargetLowering::Legal:
2547 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2549 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2550 if (Tmp1.Val) Result = Tmp1;
2553 case TargetLowering::Expand:
2554 Result = Tmp1; // Default to a no-op, return the chain
2560 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2561 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2563 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2565 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2566 default: assert(0 && "This action is not supported yet!");
2567 case TargetLowering::Legal: break;
2568 case TargetLowering::Custom:
2569 Tmp1 = TLI.LowerOperation(Result, DAG);
2570 if (Tmp1.Val) Result = Tmp1;
2577 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2578 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2580 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2581 "Cannot handle this yet!");
2582 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2586 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2587 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2588 case TargetLowering::Custom:
2589 assert(0 && "Cannot custom legalize this yet!");
2590 case TargetLowering::Legal:
2591 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2593 case TargetLowering::Promote: {
2594 MVT::ValueType OVT = Tmp1.getValueType();
2595 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2596 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2598 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2599 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2600 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2601 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2604 case TargetLowering::Expand:
2605 Result = ExpandBSWAP(Tmp1);
2613 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2614 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2615 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2616 case TargetLowering::Legal:
2617 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2619 case TargetLowering::Promote: {
2620 MVT::ValueType OVT = Tmp1.getValueType();
2621 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2623 // Zero extend the argument.
2624 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2625 // Perform the larger operation, then subtract if needed.
2626 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2627 switch (Node->getOpcode()) {
2632 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2633 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2634 DAG.getConstant(getSizeInBits(NVT), NVT),
2636 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2637 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2640 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2641 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2642 DAG.getConstant(getSizeInBits(NVT) -
2643 getSizeInBits(OVT), NVT));
2648 case TargetLowering::Expand:
2649 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2660 Tmp1 = LegalizeOp(Node->getOperand(0));
2661 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2662 case TargetLowering::Promote:
2663 case TargetLowering::Custom:
2666 case TargetLowering::Legal:
2667 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2669 Tmp1 = TLI.LowerOperation(Result, DAG);
2670 if (Tmp1.Val) Result = Tmp1;
2673 case TargetLowering::Expand:
2674 switch (Node->getOpcode()) {
2675 default: assert(0 && "Unreachable!");
2677 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2678 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2679 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2682 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2683 MVT::ValueType VT = Node->getValueType(0);
2684 Tmp2 = DAG.getConstantFP(0.0, VT);
2685 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2686 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2687 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2693 MVT::ValueType VT = Node->getValueType(0);
2694 const char *FnName = 0;
2695 switch(Node->getOpcode()) {
2696 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2697 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2698 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2699 default: assert(0 && "Unreachable!");
2702 Result = ExpandLibCall(FnName, Node, false, Dummy);
2710 // We always lower FPOWI into a libcall. No target support it yet.
2711 const char *FnName = Node->getValueType(0) == MVT::f32
2712 ? "__powisf2" : "__powidf2";
2714 Result = ExpandLibCall(FnName, Node, false, Dummy);
2717 case ISD::BIT_CONVERT:
2718 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2719 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2721 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2722 Node->getOperand(0).getValueType())) {
2723 default: assert(0 && "Unknown operation action!");
2724 case TargetLowering::Expand:
2725 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2727 case TargetLowering::Legal:
2728 Tmp1 = LegalizeOp(Node->getOperand(0));
2729 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2734 case ISD::VBIT_CONVERT: {
2735 assert(Op.getOperand(0).getValueType() == MVT::Vector &&
2736 "Can only have VBIT_CONVERT where input or output is MVT::Vector!");
2738 // The input has to be a vector type, we have to either scalarize it, pack
2739 // it, or convert it based on whether the input vector type is legal.
2740 SDNode *InVal = Node->getOperand(0).Val;
2742 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
2743 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
2745 // Figure out if there is a Packed type corresponding to this Vector
2746 // type. If so, convert to the packed type.
2747 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2748 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
2749 // Turn this into a bit convert of the packed input.
2750 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2751 PackVectorOp(Node->getOperand(0), TVT));
2753 } else if (NumElems == 1) {
2754 // Turn this into a bit convert of the scalar input.
2755 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2756 PackVectorOp(Node->getOperand(0), EVT));
2759 // FIXME: UNIMP! Store then reload
2760 assert(0 && "Cast from unsupported vector type not implemented yet!");
2764 // Conversion operators. The source and destination have different types.
2765 case ISD::SINT_TO_FP:
2766 case ISD::UINT_TO_FP: {
2767 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2768 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2770 switch (TLI.getOperationAction(Node->getOpcode(),
2771 Node->getOperand(0).getValueType())) {
2772 default: assert(0 && "Unknown operation action!");
2773 case TargetLowering::Custom:
2776 case TargetLowering::Legal:
2777 Tmp1 = LegalizeOp(Node->getOperand(0));
2778 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2780 Tmp1 = TLI.LowerOperation(Result, DAG);
2781 if (Tmp1.Val) Result = Tmp1;
2784 case TargetLowering::Expand:
2785 Result = ExpandLegalINT_TO_FP(isSigned,
2786 LegalizeOp(Node->getOperand(0)),
2787 Node->getValueType(0));
2789 case TargetLowering::Promote:
2790 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2791 Node->getValueType(0),
2797 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2798 Node->getValueType(0), Node->getOperand(0));
2801 Tmp1 = PromoteOp(Node->getOperand(0));
2803 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2804 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2806 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2807 Node->getOperand(0).getValueType());
2809 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2810 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2816 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2818 Tmp1 = LegalizeOp(Node->getOperand(0));
2819 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2822 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2824 // Since the result is legal, we should just be able to truncate the low
2825 // part of the source.
2826 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2829 Result = PromoteOp(Node->getOperand(0));
2830 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2835 case ISD::FP_TO_SINT:
2836 case ISD::FP_TO_UINT:
2837 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2839 Tmp1 = LegalizeOp(Node->getOperand(0));
2841 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2842 default: assert(0 && "Unknown operation action!");
2843 case TargetLowering::Custom:
2846 case TargetLowering::Legal:
2847 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2849 Tmp1 = TLI.LowerOperation(Result, DAG);
2850 if (Tmp1.Val) Result = Tmp1;
2853 case TargetLowering::Promote:
2854 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2855 Node->getOpcode() == ISD::FP_TO_SINT);
2857 case TargetLowering::Expand:
2858 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2859 SDOperand True, False;
2860 MVT::ValueType VT = Node->getOperand(0).getValueType();
2861 MVT::ValueType NVT = Node->getValueType(0);
2862 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2863 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2864 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2865 Node->getOperand(0), Tmp2, ISD::SETLT);
2866 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2867 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2868 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2870 False = DAG.getNode(ISD::XOR, NVT, False,
2871 DAG.getConstant(1ULL << ShiftAmt, NVT));
2872 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2875 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2881 // Convert f32 / f64 to i32 / i64.
2882 MVT::ValueType VT = Op.getValueType();
2883 const char *FnName = 0;
2884 switch (Node->getOpcode()) {
2885 case ISD::FP_TO_SINT:
2886 if (Node->getOperand(0).getValueType() == MVT::f32)
2887 FnName = (VT == MVT::i32) ? "__fixsfsi" : "__fixsfdi";
2889 FnName = (VT == MVT::i32) ? "__fixdfsi" : "__fixdfdi";
2891 case ISD::FP_TO_UINT:
2892 if (Node->getOperand(0).getValueType() == MVT::f32)
2893 FnName = (VT == MVT::i32) ? "__fixunssfsi" : "__fixunssfdi";
2895 FnName = (VT == MVT::i32) ? "__fixunsdfsi" : "__fixunsdfdi";
2897 default: assert(0 && "Unreachable!");
2900 Result = ExpandLibCall(FnName, Node, false, Dummy);
2904 Tmp1 = PromoteOp(Node->getOperand(0));
2905 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
2906 Result = LegalizeOp(Result);
2911 case ISD::ANY_EXTEND:
2912 case ISD::ZERO_EXTEND:
2913 case ISD::SIGN_EXTEND:
2914 case ISD::FP_EXTEND:
2916 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2917 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
2919 Tmp1 = LegalizeOp(Node->getOperand(0));
2920 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2923 switch (Node->getOpcode()) {
2924 case ISD::ANY_EXTEND:
2925 Tmp1 = PromoteOp(Node->getOperand(0));
2926 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
2928 case ISD::ZERO_EXTEND:
2929 Result = PromoteOp(Node->getOperand(0));
2930 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2931 Result = DAG.getZeroExtendInReg(Result,
2932 Node->getOperand(0).getValueType());
2934 case ISD::SIGN_EXTEND:
2935 Result = PromoteOp(Node->getOperand(0));
2936 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2937 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2939 DAG.getValueType(Node->getOperand(0).getValueType()));
2941 case ISD::FP_EXTEND:
2942 Result = PromoteOp(Node->getOperand(0));
2943 if (Result.getValueType() != Op.getValueType())
2944 // Dynamically dead while we have only 2 FP types.
2945 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2948 Result = PromoteOp(Node->getOperand(0));
2949 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2954 case ISD::FP_ROUND_INREG:
2955 case ISD::SIGN_EXTEND_INREG: {
2956 Tmp1 = LegalizeOp(Node->getOperand(0));
2957 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2959 // If this operation is not supported, convert it to a shl/shr or load/store
2961 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2962 default: assert(0 && "This action not supported for this op yet!");
2963 case TargetLowering::Legal:
2964 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2966 case TargetLowering::Expand:
2967 // If this is an integer extend and shifts are supported, do that.
2968 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2969 // NOTE: we could fall back on load/store here too for targets without
2970 // SAR. However, it is doubtful that any exist.
2971 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2972 MVT::getSizeInBits(ExtraVT);
2973 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2974 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2975 Node->getOperand(0), ShiftCst);
2976 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2978 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2979 // The only way we can lower this is to turn it into a TRUNCSTORE,
2980 // EXTLOAD pair, targetting a temporary location (a stack slot).
2982 // NOTE: there is a choice here between constantly creating new stack
2983 // slots and always reusing the same one. We currently always create
2984 // new ones, as reuse may inhibit scheduling.
2985 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2986 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty);
2987 unsigned Align = TLI.getTargetData()->getTypeAlignment(Ty);
2988 MachineFunction &MF = DAG.getMachineFunction();
2990 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2991 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2992 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
2993 StackSlot, NULL, 0, ExtraVT);
2994 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2995 Result, StackSlot, NULL, 0, ExtraVT);
2997 assert(0 && "Unknown op");
3005 assert(Result.getValueType() == Op.getValueType() &&
3006 "Bad legalization!");
3008 // Make sure that the generated code is itself legal.
3010 Result = LegalizeOp(Result);
3012 // Note that LegalizeOp may be reentered even from single-use nodes, which
3013 // means that we always must cache transformed nodes.
3014 AddLegalizedOperand(Op, Result);
3018 /// PromoteOp - Given an operation that produces a value in an invalid type,
3019 /// promote it to compute the value into a larger type. The produced value will
3020 /// have the correct bits for the low portion of the register, but no guarantee
3021 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3022 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3023 MVT::ValueType VT = Op.getValueType();
3024 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3025 assert(getTypeAction(VT) == Promote &&
3026 "Caller should expand or legalize operands that are not promotable!");
3027 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3028 "Cannot promote to smaller type!");
3030 SDOperand Tmp1, Tmp2, Tmp3;
3032 SDNode *Node = Op.Val;
3034 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3035 if (I != PromotedNodes.end()) return I->second;
3037 switch (Node->getOpcode()) {
3038 case ISD::CopyFromReg:
3039 assert(0 && "CopyFromReg must be legal!");
3042 cerr << "NODE: "; Node->dump(); cerr << "\n";
3044 assert(0 && "Do not know how to promote this operator!");
3047 Result = DAG.getNode(ISD::UNDEF, NVT);
3051 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3053 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3054 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3056 case ISD::ConstantFP:
3057 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3058 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3062 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3063 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3064 Node->getOperand(1), Node->getOperand(2));
3068 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3070 Result = LegalizeOp(Node->getOperand(0));
3071 assert(Result.getValueType() >= NVT &&
3072 "This truncation doesn't make sense!");
3073 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3074 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3077 // The truncation is not required, because we don't guarantee anything
3078 // about high bits anyway.
3079 Result = PromoteOp(Node->getOperand(0));
3082 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3083 // Truncate the low part of the expanded value to the result type
3084 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3087 case ISD::SIGN_EXTEND:
3088 case ISD::ZERO_EXTEND:
3089 case ISD::ANY_EXTEND:
3090 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3091 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3093 // Input is legal? Just do extend all the way to the larger type.
3094 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3097 // Promote the reg if it's smaller.
3098 Result = PromoteOp(Node->getOperand(0));
3099 // The high bits are not guaranteed to be anything. Insert an extend.
3100 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3101 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3102 DAG.getValueType(Node->getOperand(0).getValueType()));
3103 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3104 Result = DAG.getZeroExtendInReg(Result,
3105 Node->getOperand(0).getValueType());
3109 case ISD::BIT_CONVERT:
3110 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3111 Result = PromoteOp(Result);
3114 case ISD::FP_EXTEND:
3115 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3117 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3118 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3119 case Promote: assert(0 && "Unreachable with 2 FP types!");
3121 // Input is legal? Do an FP_ROUND_INREG.
3122 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3123 DAG.getValueType(VT));
3128 case ISD::SINT_TO_FP:
3129 case ISD::UINT_TO_FP:
3130 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3132 // No extra round required here.
3133 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3137 Result = PromoteOp(Node->getOperand(0));
3138 if (Node->getOpcode() == ISD::SINT_TO_FP)
3139 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3141 DAG.getValueType(Node->getOperand(0).getValueType()));
3143 Result = DAG.getZeroExtendInReg(Result,
3144 Node->getOperand(0).getValueType());
3145 // No extra round required here.
3146 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3149 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3150 Node->getOperand(0));
3151 // Round if we cannot tolerate excess precision.
3152 if (NoExcessFPPrecision)
3153 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3154 DAG.getValueType(VT));
3159 case ISD::SIGN_EXTEND_INREG:
3160 Result = PromoteOp(Node->getOperand(0));
3161 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3162 Node->getOperand(1));
3164 case ISD::FP_TO_SINT:
3165 case ISD::FP_TO_UINT:
3166 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3169 Tmp1 = Node->getOperand(0);
3172 // The input result is prerounded, so we don't have to do anything
3174 Tmp1 = PromoteOp(Node->getOperand(0));
3177 // If we're promoting a UINT to a larger size, check to see if the new node
3178 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3179 // we can use that instead. This allows us to generate better code for
3180 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3181 // legal, such as PowerPC.
3182 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3183 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3184 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3185 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3186 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3188 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3194 Tmp1 = PromoteOp(Node->getOperand(0));
3195 assert(Tmp1.getValueType() == NVT);
3196 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3197 // NOTE: we do not have to do any extra rounding here for
3198 // NoExcessFPPrecision, because we know the input will have the appropriate
3199 // precision, and these operations don't modify precision at all.
3205 Tmp1 = PromoteOp(Node->getOperand(0));
3206 assert(Tmp1.getValueType() == NVT);
3207 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3208 if (NoExcessFPPrecision)
3209 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3210 DAG.getValueType(VT));
3219 // The input may have strange things in the top bits of the registers, but
3220 // these operations don't care. They may have weird bits going out, but
3221 // that too is okay if they are integer operations.
3222 Tmp1 = PromoteOp(Node->getOperand(0));
3223 Tmp2 = PromoteOp(Node->getOperand(1));
3224 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3225 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3230 Tmp1 = PromoteOp(Node->getOperand(0));
3231 Tmp2 = PromoteOp(Node->getOperand(1));
3232 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3233 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3235 // Floating point operations will give excess precision that we may not be
3236 // able to tolerate. If we DO allow excess precision, just leave it,
3237 // otherwise excise it.
3238 // FIXME: Why would we need to round FP ops more than integer ones?
3239 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3240 if (NoExcessFPPrecision)
3241 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3242 DAG.getValueType(VT));
3247 // These operators require that their input be sign extended.
3248 Tmp1 = PromoteOp(Node->getOperand(0));
3249 Tmp2 = PromoteOp(Node->getOperand(1));
3250 if (MVT::isInteger(NVT)) {
3251 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3252 DAG.getValueType(VT));
3253 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3254 DAG.getValueType(VT));
3256 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3258 // Perform FP_ROUND: this is probably overly pessimistic.
3259 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3260 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3261 DAG.getValueType(VT));
3265 case ISD::FCOPYSIGN:
3266 // These operators require that their input be fp extended.
3267 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3269 Tmp1 = LegalizeOp(Node->getOperand(0));
3272 Tmp1 = PromoteOp(Node->getOperand(0));
3275 assert(0 && "not implemented");
3277 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3279 Tmp2 = LegalizeOp(Node->getOperand(1));
3282 Tmp2 = PromoteOp(Node->getOperand(1));
3285 assert(0 && "not implemented");
3287 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3289 // Perform FP_ROUND: this is probably overly pessimistic.
3290 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3291 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3292 DAG.getValueType(VT));
3297 // These operators require that their input be zero extended.
3298 Tmp1 = PromoteOp(Node->getOperand(0));
3299 Tmp2 = PromoteOp(Node->getOperand(1));
3300 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3301 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3302 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3303 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3307 Tmp1 = PromoteOp(Node->getOperand(0));
3308 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3311 // The input value must be properly sign extended.
3312 Tmp1 = PromoteOp(Node->getOperand(0));
3313 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3314 DAG.getValueType(VT));
3315 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3318 // The input value must be properly zero extended.
3319 Tmp1 = PromoteOp(Node->getOperand(0));
3320 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3321 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3325 Tmp1 = Node->getOperand(0); // Get the chain.
3326 Tmp2 = Node->getOperand(1); // Get the pointer.
3327 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3328 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3329 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3331 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3332 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3333 SV->getValue(), SV->getOffset());
3334 // Increment the pointer, VAList, to the next vaarg
3335 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3336 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3337 TLI.getPointerTy()));
3338 // Store the incremented VAList to the legalized pointer
3339 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3341 // Load the actual argument out of the pointer VAList
3342 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
3344 // Remember that we legalized the chain.
3345 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3349 LoadSDNode *LD = cast<LoadSDNode>(Node);
3350 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
3351 ? ISD::EXTLOAD : LD->getExtensionType();
3352 Result = DAG.getExtLoad(ExtType, NVT,
3353 LD->getChain(), LD->getBasePtr(),
3354 LD->getSrcValue(), LD->getSrcValueOffset(),
3356 // Remember that we legalized the chain.
3357 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3361 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3362 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3363 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3365 case ISD::SELECT_CC:
3366 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3367 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3368 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3369 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3372 Tmp1 = Node->getOperand(0);
3373 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3374 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3375 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3376 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
3377 TLI.getShiftAmountTy()));
3382 // Zero extend the argument
3383 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3384 // Perform the larger operation, then subtract if needed.
3385 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3386 switch(Node->getOpcode()) {
3391 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3392 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3393 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
3394 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3395 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
3398 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3399 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3400 DAG.getConstant(getSizeInBits(NVT) -
3401 getSizeInBits(VT), NVT));
3405 case ISD::VEXTRACT_VECTOR_ELT:
3406 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
3408 case ISD::EXTRACT_VECTOR_ELT:
3409 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3413 assert(Result.Val && "Didn't set a result!");
3415 // Make sure the result is itself legal.
3416 Result = LegalizeOp(Result);
3418 // Remember that we promoted this!
3419 AddPromotedOperand(Op, Result);
3423 /// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
3424 /// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
3425 /// on the vector type. The return type of this matches the element type of the
3426 /// vector, which may not be legal for the target.
3427 SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
3428 // We know that operand #0 is the Vec vector. If the index is a constant
3429 // or if the invec is a supported hardware type, we can use it. Otherwise,
3430 // lower to a store then an indexed load.
3431 SDOperand Vec = Op.getOperand(0);
3432 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3434 SDNode *InVal = Vec.Val;
3435 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
3436 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
3438 // Figure out if there is a Packed type corresponding to this Vector
3439 // type. If so, convert to the packed type.
3440 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3441 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
3442 // Turn this into a packed extract_vector_elt operation.
3443 Vec = PackVectorOp(Vec, TVT);
3444 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
3445 } else if (NumElems == 1) {
3446 // This must be an access of the only element. Return it.
3447 return PackVectorOp(Vec, EVT);
3448 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
3450 SplitVectorOp(Vec, Lo, Hi);
3451 if (CIdx->getValue() < NumElems/2) {
3455 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3458 // It's now an extract from the appropriate high or low part. Recurse.
3459 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3460 return LowerVEXTRACT_VECTOR_ELT(Op);
3462 // Variable index case for extract element.
3463 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
3464 assert(0 && "unimp!");
3469 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3471 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3472 SDOperand Vector = Op.getOperand(0);
3473 SDOperand Idx = Op.getOperand(1);
3475 // If the target doesn't support this, store the value to a temporary
3476 // stack slot, then LOAD the scalar element back out.
3477 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
3478 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vector, StackPtr, NULL, 0);
3480 // Add the offset to the index.
3481 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3482 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3483 DAG.getConstant(EltSize, Idx.getValueType()));
3484 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3486 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
3490 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3491 /// with condition CC on the current target. This usually involves legalizing
3492 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3493 /// there may be no choice but to create a new SetCC node to represent the
3494 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3495 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3496 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3499 SDOperand Tmp1, Tmp2, Result;
3501 switch (getTypeAction(LHS.getValueType())) {
3503 Tmp1 = LegalizeOp(LHS); // LHS
3504 Tmp2 = LegalizeOp(RHS); // RHS
3507 Tmp1 = PromoteOp(LHS); // LHS
3508 Tmp2 = PromoteOp(RHS); // RHS
3510 // If this is an FP compare, the operands have already been extended.
3511 if (MVT::isInteger(LHS.getValueType())) {
3512 MVT::ValueType VT = LHS.getValueType();
3513 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3515 // Otherwise, we have to insert explicit sign or zero extends. Note
3516 // that we could insert sign extends for ALL conditions, but zero extend
3517 // is cheaper on many machines (an AND instead of two shifts), so prefer
3519 switch (cast<CondCodeSDNode>(CC)->get()) {
3520 default: assert(0 && "Unknown integer comparison!");
3527 // ALL of these operations will work if we either sign or zero extend
3528 // the operands (including the unsigned comparisons!). Zero extend is
3529 // usually a simpler/cheaper operation, so prefer it.
3530 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3531 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3537 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3538 DAG.getValueType(VT));
3539 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3540 DAG.getValueType(VT));
3546 MVT::ValueType VT = LHS.getValueType();
3547 if (VT == MVT::f32 || VT == MVT::f64) {
3548 // Expand into one or more soft-fp libcall(s).
3549 const char *FnName1 = NULL, *FnName2 = NULL;
3550 ISD::CondCode CC1, CC2 = ISD::SETCC_INVALID;
3551 switch (cast<CondCodeSDNode>(CC)->get()) {
3554 FnName1 = (VT == MVT::f32) ? "__eqsf2" : "__eqdf2";
3559 FnName1 = (VT == MVT::f32) ? "__nesf2" : "__nedf2";
3564 FnName1 = (VT == MVT::f32) ? "__gesf2" : "__gedf2";
3569 FnName1 = (VT == MVT::f32) ? "__ltsf2" : "__ltdf2";
3574 FnName1 = (VT == MVT::f32) ? "__lesf2" : "__ledf2";
3579 FnName1 = (VT == MVT::f32) ? "__gtsf2" : "__gtdf2";
3584 FnName1 = (VT == MVT::f32) ? "__unordsf2" : "__unorddf2";
3585 CC1 = cast<CondCodeSDNode>(CC)->get() == ISD::SETO
3586 ? ISD::SETEQ : ISD::SETNE;
3589 FnName1 = (VT == MVT::f32) ? "__unordsf2" : "__unorddf2";
3591 switch (cast<CondCodeSDNode>(CC)->get()) {
3593 // SETONE = SETOLT | SETOGT
3594 FnName1 = (VT == MVT::f32) ? "__ltsf2" : "__ltdf2";
3598 FnName2 = (VT == MVT::f32) ? "__gtsf2" : "__gtdf2";
3602 FnName2 = (VT == MVT::f32) ? "__gesf2" : "__gedf2";
3606 FnName2 = (VT == MVT::f32) ? "__ltsf2" : "__ltdf2";
3610 FnName2 = (VT == MVT::f32) ? "__lesf2" : "__ledf2";
3614 FnName2 = (VT == MVT::f32) ? "__eqsf2" : "__eqdf2";
3617 default: assert(0 && "Unsupported FP setcc!");
3622 Tmp1 = ExpandLibCall(FnName1,
3623 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
3625 Tmp2 = DAG.getConstant(0, MVT::i32);
3626 CC = DAG.getCondCode(CC1);
3628 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
3629 LHS = ExpandLibCall(FnName2,
3630 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
3632 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
3633 DAG.getCondCode(CC2));
3634 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3642 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3643 ExpandOp(LHS, LHSLo, LHSHi);
3644 ExpandOp(RHS, RHSLo, RHSHi);
3645 switch (cast<CondCodeSDNode>(CC)->get()) {
3649 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3650 if (RHSCST->isAllOnesValue()) {
3651 // Comparison to -1.
3652 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3657 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3658 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3659 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3660 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3663 // If this is a comparison of the sign bit, just look at the top part.
3665 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3666 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3667 CST->getValue() == 0) || // X < 0
3668 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3669 CST->isAllOnesValue())) { // X > -1
3675 // FIXME: This generated code sucks.
3676 ISD::CondCode LowCC;
3677 switch (cast<CondCodeSDNode>(CC)->get()) {
3678 default: assert(0 && "Unknown integer setcc!");
3680 case ISD::SETULT: LowCC = ISD::SETULT; break;
3682 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3684 case ISD::SETULE: LowCC = ISD::SETULE; break;
3686 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3689 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3690 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3691 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3693 // NOTE: on targets without efficient SELECT of bools, we can always use
3694 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3695 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3696 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3697 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3698 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3699 Result, Tmp1, Tmp2));
3709 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3710 /// The resultant code need not be legal. Note that SrcOp is the input operand
3711 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3712 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3714 // Create the stack frame object.
3715 SDOperand FIPtr = CreateStackTemporary(DestVT);
3717 // Emit a store to the stack slot.
3718 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
3719 // Result is a load from the stack slot.
3720 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
3723 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3724 // Create a vector sized/aligned stack slot, store the value to element #0,
3725 // then load the whole vector back out.
3726 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3727 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
3729 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
3733 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3734 /// support the operation, but do support the resultant packed vector type.
3735 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3737 // If the only non-undef value is the low element, turn this into a
3738 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3739 unsigned NumElems = Node->getNumOperands();
3740 bool isOnlyLowElement = true;
3741 SDOperand SplatValue = Node->getOperand(0);
3742 std::map<SDOperand, std::vector<unsigned> > Values;
3743 Values[SplatValue].push_back(0);
3744 bool isConstant = true;
3745 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3746 SplatValue.getOpcode() != ISD::UNDEF)
3749 for (unsigned i = 1; i < NumElems; ++i) {
3750 SDOperand V = Node->getOperand(i);
3751 Values[V].push_back(i);
3752 if (V.getOpcode() != ISD::UNDEF)
3753 isOnlyLowElement = false;
3754 if (SplatValue != V)
3755 SplatValue = SDOperand(0,0);
3757 // If this isn't a constant element or an undef, we can't use a constant
3759 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3760 V.getOpcode() != ISD::UNDEF)
3764 if (isOnlyLowElement) {
3765 // If the low element is an undef too, then this whole things is an undef.
3766 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3767 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3768 // Otherwise, turn this into a scalar_to_vector node.
3769 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3770 Node->getOperand(0));
3773 // If all elements are constants, create a load from the constant pool.
3775 MVT::ValueType VT = Node->getValueType(0);
3777 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3778 std::vector<Constant*> CV;
3779 for (unsigned i = 0, e = NumElems; i != e; ++i) {
3780 if (ConstantFPSDNode *V =
3781 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3782 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3783 } else if (ConstantSDNode *V =
3784 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3785 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
3787 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3788 CV.push_back(UndefValue::get(OpNTy));
3791 Constant *CP = ConstantPacked::get(CV);
3792 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3793 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
3796 if (SplatValue.Val) { // Splat of one value?
3797 // Build the shuffle constant vector: <0, 0, 0, 0>
3798 MVT::ValueType MaskVT =
3799 MVT::getIntVectorWithNumElements(NumElems);
3800 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
3801 std::vector<SDOperand> ZeroVec(NumElems, Zero);
3802 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3803 &ZeroVec[0], ZeroVec.size());
3805 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3806 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
3807 // Get the splatted value into the low element of a vector register.
3808 SDOperand LowValVec =
3809 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3811 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3812 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3813 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3818 // If there are only two unique elements, we may be able to turn this into a
3820 if (Values.size() == 2) {
3821 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
3822 MVT::ValueType MaskVT =
3823 MVT::getIntVectorWithNumElements(NumElems);
3824 std::vector<SDOperand> MaskVec(NumElems);
3826 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3827 E = Values.end(); I != E; ++I) {
3828 for (std::vector<unsigned>::iterator II = I->second.begin(),
3829 EE = I->second.end(); II != EE; ++II)
3830 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
3833 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3834 &MaskVec[0], MaskVec.size());
3836 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3837 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
3838 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
3839 SmallVector<SDOperand, 8> Ops;
3840 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3841 E = Values.end(); I != E; ++I) {
3842 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3846 Ops.push_back(ShuffleMask);
3848 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
3849 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
3850 &Ops[0], Ops.size());
3854 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
3855 // aligned object on the stack, store each element into it, then load
3856 // the result as a vector.
3857 MVT::ValueType VT = Node->getValueType(0);
3858 // Create the stack frame object.
3859 SDOperand FIPtr = CreateStackTemporary(VT);
3861 // Emit a store of each element to the stack slot.
3862 SmallVector<SDOperand, 8> Stores;
3863 unsigned TypeByteSize =
3864 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
3865 // Store (in the right endianness) the elements to memory.
3866 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3867 // Ignore undef elements.
3868 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3870 unsigned Offset = TypeByteSize*i;
3872 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
3873 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
3875 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
3879 SDOperand StoreChain;
3880 if (!Stores.empty()) // Not all undef elements?
3881 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3882 &Stores[0], Stores.size());
3884 StoreChain = DAG.getEntryNode();
3886 // Result is a load from the stack slot.
3887 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
3890 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
3891 /// specified value type.
3892 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
3893 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3894 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
3895 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
3896 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
3899 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
3900 SDOperand Op, SDOperand Amt,
3901 SDOperand &Lo, SDOperand &Hi) {
3902 // Expand the subcomponents.
3903 SDOperand LHSL, LHSH;
3904 ExpandOp(Op, LHSL, LHSH);
3906 SDOperand Ops[] = { LHSL, LHSH, Amt };
3907 MVT::ValueType VT = LHSL.getValueType();
3908 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
3909 Hi = Lo.getValue(1);
3913 /// ExpandShift - Try to find a clever way to expand this shift operation out to
3914 /// smaller elements. If we can't find a way that is more efficient than a
3915 /// libcall on this target, return false. Otherwise, return true with the
3916 /// low-parts expanded into Lo and Hi.
3917 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3918 SDOperand &Lo, SDOperand &Hi) {
3919 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3920 "This is not a shift!");
3922 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3923 SDOperand ShAmt = LegalizeOp(Amt);
3924 MVT::ValueType ShTy = ShAmt.getValueType();
3925 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3926 unsigned NVTBits = MVT::getSizeInBits(NVT);
3928 // Handle the case when Amt is an immediate. Other cases are currently broken
3929 // and are disabled.
3930 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3931 unsigned Cst = CN->getValue();
3932 // Expand the incoming operand to be shifted, so that we have its parts
3934 ExpandOp(Op, InL, InH);
3938 Lo = DAG.getConstant(0, NVT);
3939 Hi = DAG.getConstant(0, NVT);
3940 } else if (Cst > NVTBits) {
3941 Lo = DAG.getConstant(0, NVT);
3942 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
3943 } else if (Cst == NVTBits) {
3944 Lo = DAG.getConstant(0, NVT);
3947 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
3948 Hi = DAG.getNode(ISD::OR, NVT,
3949 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
3950 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
3955 Lo = DAG.getConstant(0, NVT);
3956 Hi = DAG.getConstant(0, NVT);
3957 } else if (Cst > NVTBits) {
3958 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
3959 Hi = DAG.getConstant(0, NVT);
3960 } else if (Cst == NVTBits) {
3962 Hi = DAG.getConstant(0, NVT);
3964 Lo = DAG.getNode(ISD::OR, NVT,
3965 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3966 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3967 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
3972 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
3973 DAG.getConstant(NVTBits-1, ShTy));
3974 } else if (Cst > NVTBits) {
3975 Lo = DAG.getNode(ISD::SRA, NVT, InH,
3976 DAG.getConstant(Cst-NVTBits, ShTy));
3977 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3978 DAG.getConstant(NVTBits-1, ShTy));
3979 } else if (Cst == NVTBits) {
3981 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3982 DAG.getConstant(NVTBits-1, ShTy));
3984 Lo = DAG.getNode(ISD::OR, NVT,
3985 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3986 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3987 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
3993 // Okay, the shift amount isn't constant. However, if we can tell that it is
3994 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
3995 uint64_t Mask = NVTBits, KnownZero, KnownOne;
3996 TLI.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
3998 // If we know that the high bit of the shift amount is one, then we can do
3999 // this as a couple of simple shifts.
4000 if (KnownOne & Mask) {
4001 // Mask out the high bit, which we know is set.
4002 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
4003 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4005 // Expand the incoming operand to be shifted, so that we have its parts
4007 ExpandOp(Op, InL, InH);
4010 Lo = DAG.getConstant(0, NVT); // Low part is zero.
4011 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
4014 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
4015 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
4018 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
4019 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4020 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
4025 // If we know that the high bit of the shift amount is zero, then we can do
4026 // this as a couple of simple shifts.
4027 if (KnownZero & Mask) {
4029 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
4030 DAG.getConstant(NVTBits, Amt.getValueType()),
4033 // Expand the incoming operand to be shifted, so that we have its parts
4035 ExpandOp(Op, InL, InH);
4038 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
4039 Hi = DAG.getNode(ISD::OR, NVT,
4040 DAG.getNode(ISD::SHL, NVT, InH, Amt),
4041 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
4044 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
4045 Lo = DAG.getNode(ISD::OR, NVT,
4046 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4047 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4050 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
4051 Lo = DAG.getNode(ISD::OR, NVT,
4052 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4053 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4062 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
4063 // does not fit into a register, return the lo part and set the hi part to the
4064 // by-reg argument. If it does fit into a single register, return the result
4065 // and leave the Hi part unset.
4066 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
4067 bool isSigned, SDOperand &Hi) {
4068 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
4069 // The input chain to this libcall is the entry node of the function.
4070 // Legalizing the call will automatically add the previous call to the
4072 SDOperand InChain = DAG.getEntryNode();
4074 TargetLowering::ArgListTy Args;
4075 TargetLowering::ArgListEntry Entry;
4076 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4077 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
4078 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
4079 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
4080 Entry.isSigned = isSigned;
4081 Args.push_back(Entry);
4083 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
4085 // Splice the libcall in wherever FindInputOutputChains tells us to.
4086 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
4087 std::pair<SDOperand,SDOperand> CallInfo =
4088 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
4091 // Legalize the call sequence, starting with the chain. This will advance
4092 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
4093 // was added by LowerCallTo (guaranteeing proper serialization of calls).
4094 LegalizeOp(CallInfo.second);
4096 switch (getTypeAction(CallInfo.first.getValueType())) {
4097 default: assert(0 && "Unknown thing");
4099 Result = CallInfo.first;
4102 ExpandOp(CallInfo.first, Result, Hi);
4109 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
4110 /// destination type is legal.
4111 SDOperand SelectionDAGLegalize::
4112 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
4113 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
4114 assert(getTypeAction(Source.getValueType()) == Expand &&
4115 "This is not an expansion!");
4116 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
4119 assert(Source.getValueType() == MVT::i64 &&
4120 "This only works for 64-bit -> FP");
4121 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
4122 // incoming integer is set. To handle this, we dynamically test to see if
4123 // it is set, and, if so, add a fudge factor.
4125 ExpandOp(Source, Lo, Hi);
4127 // If this is unsigned, and not supported, first perform the conversion to
4128 // signed, then adjust the result if the sign bit is set.
4129 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
4130 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
4132 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
4133 DAG.getConstant(0, Hi.getValueType()),
4135 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4136 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4137 SignSet, Four, Zero);
4138 uint64_t FF = 0x5f800000ULL;
4139 if (TLI.isLittleEndian()) FF <<= 32;
4140 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4142 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4143 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4144 SDOperand FudgeInReg;
4145 if (DestTy == MVT::f32)
4146 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4148 assert(DestTy == MVT::f64 && "Unexpected conversion");
4149 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
4150 CPIdx, NULL, 0, MVT::f32);
4152 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
4155 // Check to see if the target has a custom way to lower this. If so, use it.
4156 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
4157 default: assert(0 && "This action not implemented for this operation!");
4158 case TargetLowering::Legal:
4159 case TargetLowering::Expand:
4160 break; // This case is handled below.
4161 case TargetLowering::Custom: {
4162 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
4165 return LegalizeOp(NV);
4166 break; // The target decided this was legal after all
4170 // Expand the source, then glue it back together for the call. We must expand
4171 // the source in case it is shared (this pass of legalize must traverse it).
4172 SDOperand SrcLo, SrcHi;
4173 ExpandOp(Source, SrcLo, SrcHi);
4174 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
4176 const char *FnName = 0;
4177 if (DestTy == MVT::f32)
4178 FnName = "__floatdisf";
4180 assert(DestTy == MVT::f64 && "Unknown fp value type!");
4181 FnName = "__floatdidf";
4184 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
4185 SDOperand UnusedHiPart;
4186 return ExpandLibCall(FnName, Source.Val, isSigned, UnusedHiPart);
4189 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
4190 /// INT_TO_FP operation of the specified operand when the target requests that
4191 /// we expand it. At this point, we know that the result and operand types are
4192 /// legal for the target.
4193 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
4195 MVT::ValueType DestVT) {
4196 if (Op0.getValueType() == MVT::i32) {
4197 // simple 32-bit [signed|unsigned] integer to float/double expansion
4199 // get the stack frame index of a 8 byte buffer
4200 MachineFunction &MF = DAG.getMachineFunction();
4201 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4202 // get address of 8 byte buffer
4203 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4204 // word offset constant for Hi/Lo address computation
4205 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
4206 // set up Hi and Lo (into buffer) address based on endian
4207 SDOperand Hi = StackSlot;
4208 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4209 if (TLI.isLittleEndian())
4212 // if signed map to unsigned space
4213 SDOperand Op0Mapped;
4215 // constant used to invert sign bit (signed to unsigned mapping)
4216 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4217 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4221 // store the lo of the constructed double - based on integer input
4222 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4223 Op0Mapped, Lo, NULL, 0);
4224 // initial hi portion of constructed double
4225 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4226 // store the hi of the constructed double - biased exponent
4227 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
4228 // load the constructed double
4229 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4230 // FP constant to bias correct the final result
4231 SDOperand Bias = DAG.getConstantFP(isSigned ?
4232 BitsToDouble(0x4330000080000000ULL)
4233 : BitsToDouble(0x4330000000000000ULL),
4235 // subtract the bias
4236 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4239 // handle final rounding
4240 if (DestVT == MVT::f64) {
4244 // if f32 then cast to f32
4245 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
4249 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4250 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4252 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4253 DAG.getConstant(0, Op0.getValueType()),
4255 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4256 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4257 SignSet, Four, Zero);
4259 // If the sign bit of the integer is set, the large number will be treated
4260 // as a negative number. To counteract this, the dynamic code adds an
4261 // offset depending on the data type.
4263 switch (Op0.getValueType()) {
4264 default: assert(0 && "Unsupported integer type!");
4265 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4266 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4267 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4268 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4270 if (TLI.isLittleEndian()) FF <<= 32;
4271 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4273 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4274 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4275 SDOperand FudgeInReg;
4276 if (DestVT == MVT::f32)
4277 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4279 assert(DestVT == MVT::f64 && "Unexpected conversion");
4280 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
4281 DAG.getEntryNode(), CPIdx,
4282 NULL, 0, MVT::f32));
4285 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4288 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4289 /// *INT_TO_FP operation of the specified operand when the target requests that
4290 /// we promote it. At this point, we know that the result and operand types are
4291 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4292 /// operation that takes a larger input.
4293 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4294 MVT::ValueType DestVT,
4296 // First step, figure out the appropriate *INT_TO_FP operation to use.
4297 MVT::ValueType NewInTy = LegalOp.getValueType();
4299 unsigned OpToUse = 0;
4301 // Scan for the appropriate larger type to use.
4303 NewInTy = (MVT::ValueType)(NewInTy+1);
4304 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4306 // If the target supports SINT_TO_FP of this type, use it.
4307 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4309 case TargetLowering::Legal:
4310 if (!TLI.isTypeLegal(NewInTy))
4311 break; // Can't use this datatype.
4313 case TargetLowering::Custom:
4314 OpToUse = ISD::SINT_TO_FP;
4318 if (isSigned) continue;
4320 // If the target supports UINT_TO_FP of this type, use it.
4321 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4323 case TargetLowering::Legal:
4324 if (!TLI.isTypeLegal(NewInTy))
4325 break; // Can't use this datatype.
4327 case TargetLowering::Custom:
4328 OpToUse = ISD::UINT_TO_FP;
4333 // Otherwise, try a larger type.
4336 // Okay, we found the operation and type to use. Zero extend our input to the
4337 // desired type then run the operation on it.
4338 return DAG.getNode(OpToUse, DestVT,
4339 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4343 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4344 /// FP_TO_*INT operation of the specified operand when the target requests that
4345 /// we promote it. At this point, we know that the result and operand types are
4346 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4347 /// operation that returns a larger result.
4348 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4349 MVT::ValueType DestVT,
4351 // First step, figure out the appropriate FP_TO*INT operation to use.
4352 MVT::ValueType NewOutTy = DestVT;
4354 unsigned OpToUse = 0;
4356 // Scan for the appropriate larger type to use.
4358 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4359 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4361 // If the target supports FP_TO_SINT returning this type, use it.
4362 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4364 case TargetLowering::Legal:
4365 if (!TLI.isTypeLegal(NewOutTy))
4366 break; // Can't use this datatype.
4368 case TargetLowering::Custom:
4369 OpToUse = ISD::FP_TO_SINT;
4374 // If the target supports FP_TO_UINT of this type, use it.
4375 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4377 case TargetLowering::Legal:
4378 if (!TLI.isTypeLegal(NewOutTy))
4379 break; // Can't use this datatype.
4381 case TargetLowering::Custom:
4382 OpToUse = ISD::FP_TO_UINT;
4387 // Otherwise, try a larger type.
4390 // Okay, we found the operation and type to use. Truncate the result of the
4391 // extended FP_TO_*INT operation to the desired size.
4392 return DAG.getNode(ISD::TRUNCATE, DestVT,
4393 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4396 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4398 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4399 MVT::ValueType VT = Op.getValueType();
4400 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4401 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4403 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4405 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4406 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4407 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4409 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4410 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4411 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4412 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4413 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4414 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4415 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4416 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4417 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4419 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4420 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4421 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4422 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4423 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4424 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4425 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4426 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4427 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4428 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4429 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4430 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4431 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4432 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4433 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4434 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4435 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4436 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4437 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4438 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4439 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4443 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4445 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4447 default: assert(0 && "Cannot expand this yet!");
4449 static const uint64_t mask[6] = {
4450 0x5555555555555555ULL, 0x3333333333333333ULL,
4451 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4452 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4454 MVT::ValueType VT = Op.getValueType();
4455 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4456 unsigned len = getSizeInBits(VT);
4457 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4458 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4459 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4460 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4461 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4462 DAG.getNode(ISD::AND, VT,
4463 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4468 // for now, we do this:
4469 // x = x | (x >> 1);
4470 // x = x | (x >> 2);
4472 // x = x | (x >>16);
4473 // x = x | (x >>32); // for 64-bit input
4474 // return popcount(~x);
4476 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4477 MVT::ValueType VT = Op.getValueType();
4478 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4479 unsigned len = getSizeInBits(VT);
4480 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4481 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4482 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4484 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4485 return DAG.getNode(ISD::CTPOP, VT, Op);
4488 // for now, we use: { return popcount(~x & (x - 1)); }
4489 // unless the target has ctlz but not ctpop, in which case we use:
4490 // { return 32 - nlz(~x & (x-1)); }
4491 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4492 MVT::ValueType VT = Op.getValueType();
4493 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4494 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4495 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4496 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4497 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4498 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4499 TLI.isOperationLegal(ISD::CTLZ, VT))
4500 return DAG.getNode(ISD::SUB, VT,
4501 DAG.getConstant(getSizeInBits(VT), VT),
4502 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4503 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4508 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4509 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4510 /// LegalizeNodes map is filled in for any results that are not expanded, the
4511 /// ExpandedNodes map is filled in for any results that are expanded, and the
4512 /// Lo/Hi values are returned.
4513 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4514 MVT::ValueType VT = Op.getValueType();
4515 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4516 SDNode *Node = Op.Val;
4517 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4518 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
4519 VT == MVT::Vector) &&
4520 "Cannot expand to FP value or to larger int value!");
4522 // See if we already expanded it.
4523 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4524 = ExpandedNodes.find(Op);
4525 if (I != ExpandedNodes.end()) {
4526 Lo = I->second.first;
4527 Hi = I->second.second;
4531 switch (Node->getOpcode()) {
4532 case ISD::CopyFromReg:
4533 assert(0 && "CopyFromReg must be legal!");
4536 cerr << "NODE: "; Node->dump(); cerr << "\n";
4538 assert(0 && "Do not know how to expand this operator!");
4541 NVT = TLI.getTypeToExpandTo(VT);
4542 Lo = DAG.getNode(ISD::UNDEF, NVT);
4543 Hi = DAG.getNode(ISD::UNDEF, NVT);
4545 case ISD::Constant: {
4546 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4547 Lo = DAG.getConstant(Cst, NVT);
4548 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4551 case ISD::ConstantFP: {
4552 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
4553 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
4554 if (getTypeAction(Lo.getValueType()) == Expand)
4555 ExpandOp(Lo, Lo, Hi);
4558 case ISD::BUILD_PAIR:
4559 // Return the operands.
4560 Lo = Node->getOperand(0);
4561 Hi = Node->getOperand(1);
4564 case ISD::SIGN_EXTEND_INREG:
4565 ExpandOp(Node->getOperand(0), Lo, Hi);
4566 // sext_inreg the low part if needed.
4567 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4569 // The high part gets the sign extension from the lo-part. This handles
4570 // things like sextinreg V:i64 from i8.
4571 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4572 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4573 TLI.getShiftAmountTy()));
4577 ExpandOp(Node->getOperand(0), Lo, Hi);
4578 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4579 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4585 ExpandOp(Node->getOperand(0), Lo, Hi);
4586 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4587 DAG.getNode(ISD::CTPOP, NVT, Lo),
4588 DAG.getNode(ISD::CTPOP, NVT, Hi));
4589 Hi = DAG.getConstant(0, NVT);
4593 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4594 ExpandOp(Node->getOperand(0), Lo, Hi);
4595 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4596 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4597 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4599 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4600 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4602 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4603 Hi = DAG.getConstant(0, NVT);
4608 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4609 ExpandOp(Node->getOperand(0), Lo, Hi);
4610 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4611 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4612 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4614 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4615 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4617 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4618 Hi = DAG.getConstant(0, NVT);
4623 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4624 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4625 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4626 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4628 // Remember that we legalized the chain.
4629 Hi = LegalizeOp(Hi);
4630 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4631 if (!TLI.isLittleEndian())
4637 LoadSDNode *LD = cast<LoadSDNode>(Node);
4638 SDOperand Ch = LD->getChain(); // Legalize the chain.
4639 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
4640 ISD::LoadExtType ExtType = LD->getExtensionType();
4642 if (ExtType == ISD::NON_EXTLOAD) {
4643 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset());
4644 if (VT == MVT::f32 || VT == MVT::f64) {
4645 // f32->i32 or f64->i64 one to one expansion.
4646 // Remember that we legalized the chain.
4647 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4648 // Recursively expand the new load.
4649 if (getTypeAction(NVT) == Expand)
4650 ExpandOp(Lo, Lo, Hi);
4654 // Increment the pointer to the other half.
4655 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4656 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4657 getIntPtrConstant(IncrementSize));
4658 // FIXME: This creates a bogus srcvalue!
4659 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset());
4661 // Build a factor node to remember that this load is independent of the
4663 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4666 // Remember that we legalized the chain.
4667 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4668 if (!TLI.isLittleEndian())
4671 MVT::ValueType EVT = LD->getLoadedVT();
4673 if (VT == MVT::f64 && EVT == MVT::f32) {
4674 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
4675 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
4676 LD->getSrcValueOffset());
4677 // Remember that we legalized the chain.
4678 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
4679 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
4684 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
4685 LD->getSrcValueOffset());
4687 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
4688 LD->getSrcValueOffset(), EVT);
4690 // Remember that we legalized the chain.
4691 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4693 if (ExtType == ISD::SEXTLOAD) {
4694 // The high part is obtained by SRA'ing all but one of the bits of the
4696 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4697 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4698 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4699 } else if (ExtType == ISD::ZEXTLOAD) {
4700 // The high part is just a zero.
4701 Hi = DAG.getConstant(0, NVT);
4702 } else /* if (ExtType == ISD::EXTLOAD) */ {
4703 // The high part is undefined.
4704 Hi = DAG.getNode(ISD::UNDEF, NVT);
4711 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
4712 SDOperand LL, LH, RL, RH;
4713 ExpandOp(Node->getOperand(0), LL, LH);
4714 ExpandOp(Node->getOperand(1), RL, RH);
4715 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4716 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4720 SDOperand LL, LH, RL, RH;
4721 ExpandOp(Node->getOperand(1), LL, LH);
4722 ExpandOp(Node->getOperand(2), RL, RH);
4723 if (getTypeAction(NVT) == Expand)
4724 NVT = TLI.getTypeToExpandTo(NVT);
4725 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4727 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4730 case ISD::SELECT_CC: {
4731 SDOperand TL, TH, FL, FH;
4732 ExpandOp(Node->getOperand(2), TL, TH);
4733 ExpandOp(Node->getOperand(3), FL, FH);
4734 if (getTypeAction(NVT) == Expand)
4735 NVT = TLI.getTypeToExpandTo(NVT);
4736 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4737 Node->getOperand(1), TL, FL, Node->getOperand(4));
4739 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4740 Node->getOperand(1), TH, FH, Node->getOperand(4));
4743 case ISD::ANY_EXTEND:
4744 // The low part is any extension of the input (which degenerates to a copy).
4745 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4746 // The high part is undefined.
4747 Hi = DAG.getNode(ISD::UNDEF, NVT);
4749 case ISD::SIGN_EXTEND: {
4750 // The low part is just a sign extension of the input (which degenerates to
4752 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4754 // The high part is obtained by SRA'ing all but one of the bits of the lo
4756 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4757 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4758 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4761 case ISD::ZERO_EXTEND:
4762 // The low part is just a zero extension of the input (which degenerates to
4764 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4766 // The high part is just a zero.
4767 Hi = DAG.getConstant(0, NVT);
4770 case ISD::BIT_CONVERT: {
4772 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
4773 // If the target wants to, allow it to lower this itself.
4774 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4775 case Expand: assert(0 && "cannot expand FP!");
4776 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
4777 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
4779 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
4782 // f32 / f64 must be expanded to i32 / i64.
4783 if (VT == MVT::f32 || VT == MVT::f64) {
4784 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
4785 if (getTypeAction(NVT) == Expand)
4786 ExpandOp(Lo, Lo, Hi);
4790 // If source operand will be expanded to the same type as VT, i.e.
4791 // i64 <- f64, i32 <- f32, expand the source operand instead.
4792 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
4793 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
4794 ExpandOp(Node->getOperand(0), Lo, Hi);
4798 // Turn this into a load/store pair by default.
4800 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0));
4802 ExpandOp(Tmp, Lo, Hi);
4806 case ISD::READCYCLECOUNTER:
4807 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
4808 TargetLowering::Custom &&
4809 "Must custom expand ReadCycleCounter");
4810 Lo = TLI.LowerOperation(Op, DAG);
4811 assert(Lo.Val && "Node must be custom expanded!");
4812 Hi = Lo.getValue(1);
4813 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
4814 LegalizeOp(Lo.getValue(2)));
4817 // These operators cannot be expanded directly, emit them as calls to
4818 // library functions.
4819 case ISD::FP_TO_SINT:
4820 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
4822 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4823 case Expand: assert(0 && "cannot expand FP!");
4824 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4825 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4828 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
4830 // Now that the custom expander is done, expand the result, which is still
4833 ExpandOp(Op, Lo, Hi);
4838 if (Node->getOperand(0).getValueType() == MVT::f32)
4839 Lo = ExpandLibCall("__fixsfdi", Node, false, Hi);
4841 Lo = ExpandLibCall("__fixdfdi", Node, false, Hi);
4844 case ISD::FP_TO_UINT:
4845 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
4847 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4848 case Expand: assert(0 && "cannot expand FP!");
4849 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4850 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4853 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
4855 // Now that the custom expander is done, expand the result.
4857 ExpandOp(Op, Lo, Hi);
4862 if (Node->getOperand(0).getValueType() == MVT::f32)
4863 Lo = ExpandLibCall("__fixunssfdi", Node, false, Hi);
4865 Lo = ExpandLibCall("__fixunsdfdi", Node, false, Hi);
4869 // If the target wants custom lowering, do so.
4870 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4871 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
4872 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
4873 Op = TLI.LowerOperation(Op, DAG);
4875 // Now that the custom expander is done, expand the result, which is
4877 ExpandOp(Op, Lo, Hi);
4882 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
4883 // this X << 1 as X+X.
4884 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
4885 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
4886 TLI.isOperationLegal(ISD::ADDE, NVT)) {
4887 SDOperand LoOps[2], HiOps[3];
4888 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
4889 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
4890 LoOps[1] = LoOps[0];
4891 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
4893 HiOps[1] = HiOps[0];
4894 HiOps[2] = Lo.getValue(1);
4895 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
4900 // If we can emit an efficient shift operation, do so now.
4901 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4904 // If this target supports SHL_PARTS, use it.
4905 TargetLowering::LegalizeAction Action =
4906 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
4907 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4908 Action == TargetLowering::Custom) {
4909 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4913 // Otherwise, emit a libcall.
4914 Lo = ExpandLibCall("__ashldi3", Node, false, Hi);
4919 // If the target wants custom lowering, do so.
4920 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4921 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
4922 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
4923 Op = TLI.LowerOperation(Op, DAG);
4925 // Now that the custom expander is done, expand the result, which is
4927 ExpandOp(Op, Lo, Hi);
4932 // If we can emit an efficient shift operation, do so now.
4933 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
4936 // If this target supports SRA_PARTS, use it.
4937 TargetLowering::LegalizeAction Action =
4938 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
4939 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4940 Action == TargetLowering::Custom) {
4941 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4945 // Otherwise, emit a libcall.
4946 Lo = ExpandLibCall("__ashrdi3", Node, true, Hi);
4951 // If the target wants custom lowering, do so.
4952 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4953 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
4954 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
4955 Op = TLI.LowerOperation(Op, DAG);
4957 // Now that the custom expander is done, expand the result, which is
4959 ExpandOp(Op, Lo, Hi);
4964 // If we can emit an efficient shift operation, do so now.
4965 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4968 // If this target supports SRL_PARTS, use it.
4969 TargetLowering::LegalizeAction Action =
4970 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
4971 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4972 Action == TargetLowering::Custom) {
4973 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4977 // Otherwise, emit a libcall.
4978 Lo = ExpandLibCall("__lshrdi3", Node, false, Hi);
4984 // If the target wants to custom expand this, let them.
4985 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
4986 TargetLowering::Custom) {
4987 Op = TLI.LowerOperation(Op, DAG);
4989 ExpandOp(Op, Lo, Hi);
4994 // Expand the subcomponents.
4995 SDOperand LHSL, LHSH, RHSL, RHSH;
4996 ExpandOp(Node->getOperand(0), LHSL, LHSH);
4997 ExpandOp(Node->getOperand(1), RHSL, RHSH);
4998 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
4999 SDOperand LoOps[2], HiOps[3];
5004 if (Node->getOpcode() == ISD::ADD) {
5005 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5006 HiOps[2] = Lo.getValue(1);
5007 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5009 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5010 HiOps[2] = Lo.getValue(1);
5011 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5016 // If the target wants to custom expand this, let them.
5017 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
5018 SDOperand New = TLI.LowerOperation(Op, DAG);
5020 ExpandOp(New, Lo, Hi);
5025 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
5026 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
5027 if (HasMULHS || HasMULHU) {
5028 SDOperand LL, LH, RL, RH;
5029 ExpandOp(Node->getOperand(0), LL, LH);
5030 ExpandOp(Node->getOperand(1), RL, RH);
5031 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
5032 // FIXME: Move this to the dag combiner.
5033 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
5034 // extended the sign bit of the low half through the upper half, and if so
5035 // emit a MULHS instead of the alternate sequence that is valid for any
5036 // i64 x i64 multiply.
5038 // is RH an extension of the sign bit of RL?
5039 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
5040 RH.getOperand(1).getOpcode() == ISD::Constant &&
5041 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
5042 // is LH an extension of the sign bit of LL?
5043 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
5044 LH.getOperand(1).getOpcode() == ISD::Constant &&
5045 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
5047 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5049 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
5051 } else if (HasMULHU) {
5053 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5056 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
5057 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
5058 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
5059 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
5060 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
5065 Lo = ExpandLibCall("__muldi3" , Node, false, Hi);
5068 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, true, Hi); break;
5069 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, false, Hi); break;
5070 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, true, Hi); break;
5071 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, false, Hi); break;
5074 Lo = ExpandLibCall(((VT == MVT::f32) ? "__addsf3" : "__adddf3"), Node,
5078 Lo = ExpandLibCall(((VT == MVT::f32) ? "__subsf3" : "__subdf3"), Node,
5082 Lo = ExpandLibCall(((VT == MVT::f32) ? "__mulsf3" : "__muldf3"), Node,
5086 Lo = ExpandLibCall(((VT == MVT::f32) ? "__divsf3" : "__divdf3"), Node,
5089 case ISD::FP_EXTEND:
5090 Lo = ExpandLibCall("__extendsfdf2", Node, false, Hi);
5093 Lo = ExpandLibCall("__truncdfsf2", Node, false, Hi);
5098 const char *FnName = 0;
5099 switch(Node->getOpcode()) {
5100 case ISD::FSQRT: FnName = (VT == MVT::f32) ? "sqrtf" : "sqrt"; break;
5101 case ISD::FSIN: FnName = (VT == MVT::f32) ? "sinf" : "sin"; break;
5102 case ISD::FCOS: FnName = (VT == MVT::f32) ? "cosf" : "cos"; break;
5103 default: assert(0 && "Unreachable!");
5105 Lo = ExpandLibCall(FnName, Node, false, Hi);
5109 SDOperand Mask = (VT == MVT::f64)
5110 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
5111 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
5112 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5113 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5114 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
5115 if (getTypeAction(NVT) == Expand)
5116 ExpandOp(Lo, Lo, Hi);
5120 SDOperand Mask = (VT == MVT::f64)
5121 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
5122 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
5123 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5124 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5125 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
5126 if (getTypeAction(NVT) == Expand)
5127 ExpandOp(Lo, Lo, Hi);
5130 case ISD::SINT_TO_FP:
5131 case ISD::UINT_TO_FP: {
5132 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
5133 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
5134 const char *FnName = 0;
5135 if (Node->getOperand(0).getValueType() == MVT::i64) {
5137 FnName = isSigned ? "__floatdisf" : "__floatundisf";
5139 FnName = isSigned ? "__floatdidf" : "__floatundidf";
5142 FnName = isSigned ? "__floatsisf" : "__floatunsisf";
5144 FnName = isSigned ? "__floatsidf" : "__floatunsidf";
5147 // Promote the operand if needed.
5148 if (getTypeAction(SrcVT) == Promote) {
5149 SDOperand Tmp = PromoteOp(Node->getOperand(0));
5151 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
5152 DAG.getValueType(SrcVT))
5153 : DAG.getZeroExtendInReg(Tmp, SrcVT);
5154 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
5156 Lo = ExpandLibCall(FnName, Node, isSigned, Hi);
5161 // Make sure the resultant values have been legalized themselves, unless this
5162 // is a type that requires multi-step expansion.
5163 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
5164 Lo = LegalizeOp(Lo);
5166 // Don't legalize the high part if it is expanded to a single node.
5167 Hi = LegalizeOp(Hi);
5170 // Remember in a map if the values will be reused later.
5172 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
5173 assert(isNew && "Value already expanded?!?");
5176 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
5177 /// two smaller values of MVT::Vector type.
5178 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
5180 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
5181 SDNode *Node = Op.Val;
5182 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
5183 assert(NumElements > 1 && "Cannot split a single element vector!");
5184 unsigned NewNumElts = NumElements/2;
5185 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
5186 SDOperand TypeNode = *(Node->op_end()-1);
5188 // See if we already split it.
5189 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5190 = SplitNodes.find(Op);
5191 if (I != SplitNodes.end()) {
5192 Lo = I->second.first;
5193 Hi = I->second.second;
5197 switch (Node->getOpcode()) {
5202 assert(0 && "Unhandled operation in SplitVectorOp!");
5203 case ISD::VBUILD_VECTOR: {
5204 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5205 Node->op_begin()+NewNumElts);
5206 LoOps.push_back(NewNumEltsNode);
5207 LoOps.push_back(TypeNode);
5208 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size());
5210 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
5212 HiOps.push_back(NewNumEltsNode);
5213 HiOps.push_back(TypeNode);
5214 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size());
5225 SDOperand LL, LH, RL, RH;
5226 SplitVectorOp(Node->getOperand(0), LL, LH);
5227 SplitVectorOp(Node->getOperand(1), RL, RH);
5229 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
5230 NewNumEltsNode, TypeNode);
5231 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
5232 NewNumEltsNode, TypeNode);
5236 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5237 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5238 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
5240 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
5241 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
5242 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5243 getIntPtrConstant(IncrementSize));
5244 // FIXME: This creates a bogus srcvalue!
5245 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
5247 // Build a factor node to remember that this load is independent of the
5249 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5252 // Remember that we legalized the chain.
5253 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5256 case ISD::VBIT_CONVERT: {
5257 // We know the result is a vector. The input may be either a vector or a
5259 if (Op.getOperand(0).getValueType() != MVT::Vector) {
5260 // Lower to a store/load. FIXME: this could be improved probably.
5261 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
5263 SDOperand St = DAG.getStore(DAG.getEntryNode(),
5264 Op.getOperand(0), Ptr, NULL, 0);
5265 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
5266 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0));
5267 SplitVectorOp(St, Lo, Hi);
5269 // If the input is a vector type, we have to either scalarize it, pack it
5270 // or convert it based on whether the input vector type is legal.
5271 SDNode *InVal = Node->getOperand(0).Val;
5273 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
5274 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
5276 // If the input is from a single element vector, scalarize the vector,
5277 // then treat like a scalar.
5278 if (NumElems == 1) {
5279 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT);
5280 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar,
5281 Op.getOperand(1), Op.getOperand(2));
5282 SplitVectorOp(Scalar, Lo, Hi);
5284 // Split the input vector.
5285 SplitVectorOp(Op.getOperand(0), Lo, Hi);
5287 // Convert each of the pieces now.
5288 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo,
5289 NewNumEltsNode, TypeNode);
5290 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi,
5291 NewNumEltsNode, TypeNode);
5298 // Remember in a map if the values will be reused later.
5300 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
5301 assert(isNew && "Value already expanded?!?");
5305 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
5306 /// equivalent operation that returns a scalar (e.g. F32) or packed value
5307 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
5308 /// type for the result.
5309 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
5310 MVT::ValueType NewVT) {
5311 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
5312 SDNode *Node = Op.Val;
5314 // See if we already packed it.
5315 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
5316 if (I != PackedNodes.end()) return I->second;
5319 switch (Node->getOpcode()) {
5322 Node->dump(); cerr << "\n";
5324 assert(0 && "Unknown vector operation in PackVectorOp!");
5333 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
5335 PackVectorOp(Node->getOperand(0), NewVT),
5336 PackVectorOp(Node->getOperand(1), NewVT));
5339 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
5340 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
5342 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
5343 Result = DAG.getLoad(NewVT, Ch, Ptr, SV->getValue(), SV->getOffset());
5345 // Remember that we legalized the chain.
5346 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
5349 case ISD::VBUILD_VECTOR:
5350 if (Node->getOperand(0).getValueType() == NewVT) {
5351 // Returning a scalar?
5352 Result = Node->getOperand(0);
5354 // Returning a BUILD_VECTOR?
5356 // If all elements of the build_vector are undefs, return an undef.
5357 bool AllUndef = true;
5358 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i)
5359 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) {
5364 Result = DAG.getNode(ISD::UNDEF, NewVT);
5366 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(),
5367 Node->getNumOperands()-2);
5371 case ISD::VINSERT_VECTOR_ELT:
5372 if (!MVT::isVector(NewVT)) {
5373 // Returning a scalar? Must be the inserted element.
5374 Result = Node->getOperand(1);
5376 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
5377 PackVectorOp(Node->getOperand(0), NewVT),
5378 Node->getOperand(1), Node->getOperand(2));
5381 case ISD::VVECTOR_SHUFFLE:
5382 if (!MVT::isVector(NewVT)) {
5383 // Returning a scalar? Figure out if it is the LHS or RHS and return it.
5384 SDOperand EltNum = Node->getOperand(2).getOperand(0);
5385 if (cast<ConstantSDNode>(EltNum)->getValue())
5386 Result = PackVectorOp(Node->getOperand(1), NewVT);
5388 Result = PackVectorOp(Node->getOperand(0), NewVT);
5390 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index
5391 // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
5392 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
5393 Node->getOperand(2).Val->op_end()-2);
5394 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
5395 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT,
5396 Node->getOperand(2).Val->op_begin(),
5397 Node->getOperand(2).Val->getNumOperands()-2);
5399 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
5400 PackVectorOp(Node->getOperand(0), NewVT),
5401 PackVectorOp(Node->getOperand(1), NewVT), BV);
5404 case ISD::VBIT_CONVERT:
5405 if (Op.getOperand(0).getValueType() != MVT::Vector)
5406 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
5408 // If the input is a vector type, we have to either scalarize it, pack it
5409 // or convert it based on whether the input vector type is legal.
5410 SDNode *InVal = Node->getOperand(0).Val;
5412 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
5413 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
5415 // Figure out if there is a Packed type corresponding to this Vector
5416 // type. If so, convert to the packed type.
5417 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
5418 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
5419 // Turn this into a bit convert of the packed input.
5420 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5421 PackVectorOp(Node->getOperand(0), TVT));
5423 } else if (NumElems == 1) {
5424 // Turn this into a bit convert of the scalar input.
5425 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5426 PackVectorOp(Node->getOperand(0), EVT));
5430 assert(0 && "Cast from unsupported vector type not implemented yet!");
5435 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
5436 PackVectorOp(Op.getOperand(1), NewVT),
5437 PackVectorOp(Op.getOperand(2), NewVT));
5441 if (TLI.isTypeLegal(NewVT))
5442 Result = LegalizeOp(Result);
5443 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
5444 assert(isNew && "Value already packed?");
5449 // SelectionDAG::Legalize - This is the entry point for the file.
5451 void SelectionDAG::Legalize() {
5452 if (ViewLegalizeDAGs) viewGraph();
5454 /// run - This is the main entry point to this class.
5456 SelectionDAGLegalize(*this).LegalizeDAG();