1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Triple.h"
18 #include "llvm/CodeGen/Analysis.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/DebugInfo.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/IR/DerivedTypes.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/LLVMContext.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetFrameLowering.h"
33 #include "llvm/Target/TargetLowering.h"
34 #include "llvm/Target/TargetMachine.h"
37 //===----------------------------------------------------------------------===//
38 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
39 /// hacks on it until the target machine can handle it. This involves
40 /// eliminating value sizes the machine cannot handle (promoting small sizes to
41 /// large sizes or splitting up large values into small values) as well as
42 /// eliminating operations the machine cannot handle.
44 /// This code also does a small amount of optimization and recognition of idioms
45 /// as part of its processing. For example, if a target does not support a
46 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
47 /// will attempt merge setcc and brc instructions into brcc's.
50 class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
51 const TargetMachine &TM;
52 const TargetLowering &TLI;
55 /// LegalizePosition - The iterator for walking through the node list.
56 SelectionDAG::allnodes_iterator LegalizePosition;
58 /// LegalizedNodes - The set of nodes which have already been legalized.
59 SmallPtrSet<SDNode *, 16> LegalizedNodes;
61 EVT getSetCCResultType(EVT VT) const {
62 return TLI.getSetCCResultType(*DAG.getContext(), VT);
65 // Libcall insertion helpers.
68 explicit SelectionDAGLegalize(SelectionDAG &DAG);
73 /// LegalizeOp - Legalizes the given operation.
74 void LegalizeOp(SDNode *Node);
76 SDValue OptimizeFloatStore(StoreSDNode *ST);
78 void LegalizeLoadOps(SDNode *Node);
79 void LegalizeStoreOps(SDNode *Node);
81 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
82 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
83 /// is necessary to spill the vector being inserted into to memory, perform
84 /// the insert there, and then read the result back.
85 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
86 SDValue Idx, SDLoc dl);
87 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
88 SDValue Idx, SDLoc dl);
90 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
91 /// performs the same shuffe in terms of order or result bytes, but on a type
92 /// whose vector element type is narrower than the original shuffle type.
93 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
94 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
95 SDValue N1, SDValue N2,
96 ArrayRef<int> Mask) const;
98 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
101 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
102 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
103 unsigned NumOps, bool isSigned, SDLoc dl);
105 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
106 SDNode *Node, bool isSigned);
107 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
108 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
109 RTLIB::Libcall Call_F128,
110 RTLIB::Libcall Call_PPCF128);
111 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
112 RTLIB::Libcall Call_I8,
113 RTLIB::Libcall Call_I16,
114 RTLIB::Libcall Call_I32,
115 RTLIB::Libcall Call_I64,
116 RTLIB::Libcall Call_I128);
117 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
118 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
120 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
121 SDValue ExpandBUILD_VECTOR(SDNode *Node);
122 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
123 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
124 SmallVectorImpl<SDValue> &Results);
125 SDValue ExpandFCOPYSIGN(SDNode *Node);
126 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
128 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
130 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
133 SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
134 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
136 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
137 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
138 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
140 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
142 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
144 void ExpandNode(SDNode *Node);
145 void PromoteNode(SDNode *Node);
147 void ForgetNode(SDNode *N) {
148 LegalizedNodes.erase(N);
149 if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
154 // DAGUpdateListener implementation.
155 virtual void NodeDeleted(SDNode *N, SDNode *E) {
158 virtual void NodeUpdated(SDNode *N) {}
160 // Node replacement helpers
161 void ReplacedNode(SDNode *N) {
162 if (N->use_empty()) {
163 DAG.RemoveDeadNode(N);
168 void ReplaceNode(SDNode *Old, SDNode *New) {
169 DAG.ReplaceAllUsesWith(Old, New);
172 void ReplaceNode(SDValue Old, SDValue New) {
173 DAG.ReplaceAllUsesWith(Old, New);
174 ReplacedNode(Old.getNode());
176 void ReplaceNode(SDNode *Old, const SDValue *New) {
177 DAG.ReplaceAllUsesWith(Old, New);
183 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
184 /// performs the same shuffe in terms of order or result bytes, but on a type
185 /// whose vector element type is narrower than the original shuffle type.
186 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
188 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
189 SDValue N1, SDValue N2,
190 ArrayRef<int> Mask) const {
191 unsigned NumMaskElts = VT.getVectorNumElements();
192 unsigned NumDestElts = NVT.getVectorNumElements();
193 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
195 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
197 if (NumEltsGrowth == 1)
198 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
200 SmallVector<int, 8> NewMask;
201 for (unsigned i = 0; i != NumMaskElts; ++i) {
203 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
205 NewMask.push_back(-1);
207 NewMask.push_back(Idx * NumEltsGrowth + j);
210 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
211 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
212 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
215 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
216 : SelectionDAG::DAGUpdateListener(dag),
217 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
221 void SelectionDAGLegalize::LegalizeDAG() {
222 DAG.AssignTopologicalOrder();
224 // Visit all the nodes. We start in topological order, so that we see
225 // nodes with their original operands intact. Legalization can produce
226 // new nodes which may themselves need to be legalized. Iterate until all
227 // nodes have been legalized.
229 bool AnyLegalized = false;
230 for (LegalizePosition = DAG.allnodes_end();
231 LegalizePosition != DAG.allnodes_begin(); ) {
234 SDNode *N = LegalizePosition;
235 if (LegalizedNodes.insert(N)) {
245 // Remove dead nodes now.
246 DAG.RemoveDeadNodes();
249 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
250 /// a load from the constant pool.
252 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
256 // If a FP immediate is precise when represented as a float and if the
257 // target can do an extending load from float to double, we put it into
258 // the constant pool as a float, even if it's is statically typed as a
259 // double. This shrinks FP constants and canonicalizes them for targets where
260 // an FP extending load is the same cost as a normal load (such as on the x87
261 // fp stack or PPC FP unit).
262 EVT VT = CFP->getValueType(0);
263 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
265 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
266 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
267 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
272 while (SVT != MVT::f32) {
273 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
274 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
275 // Only do this if the target has a native EXTLOAD instruction from
277 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
278 TLI.ShouldShrinkFPConstant(OrigVT)) {
279 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
280 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
286 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
287 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
290 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
292 CPIdx, MachinePointerInfo::getConstantPool(),
293 VT, false, false, Alignment);
297 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
298 MachinePointerInfo::getConstantPool(), false, false, false,
303 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
304 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
305 const TargetLowering &TLI,
306 SelectionDAGLegalize *DAGLegalize) {
307 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
308 "unaligned indexed stores not implemented!");
309 SDValue Chain = ST->getChain();
310 SDValue Ptr = ST->getBasePtr();
311 SDValue Val = ST->getValue();
312 EVT VT = Val.getValueType();
313 int Alignment = ST->getAlignment();
315 if (ST->getMemoryVT().isFloatingPoint() ||
316 ST->getMemoryVT().isVector()) {
317 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
318 if (TLI.isTypeLegal(intVT)) {
319 // Expand to a bitconvert of the value to the integer type of the
320 // same size, then a (misaligned) int store.
321 // FIXME: Does not handle truncating floating point stores!
322 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
323 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
324 ST->isVolatile(), ST->isNonTemporal(), Alignment);
325 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
328 // Do a (aligned) store to a stack slot, then copy from the stack slot
329 // to the final destination using (unaligned) integer loads and stores.
330 EVT StoredVT = ST->getMemoryVT();
332 TLI.getRegisterType(*DAG.getContext(),
333 EVT::getIntegerVT(*DAG.getContext(),
334 StoredVT.getSizeInBits()));
335 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
336 unsigned RegBytes = RegVT.getSizeInBits() / 8;
337 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
339 // Make sure the stack slot is also aligned for the register type.
340 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
342 // Perform the original store, only redirected to the stack slot.
343 SDValue Store = DAG.getTruncStore(Chain, dl,
344 Val, StackPtr, MachinePointerInfo(),
345 StoredVT, false, false, 0);
346 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
347 SmallVector<SDValue, 8> Stores;
350 // Do all but one copies using the full register width.
351 for (unsigned i = 1; i < NumRegs; i++) {
352 // Load one integer register's worth from the stack slot.
353 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
354 MachinePointerInfo(),
355 false, false, false, 0);
356 // Store it to the final location. Remember the store.
357 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
358 ST->getPointerInfo().getWithOffset(Offset),
359 ST->isVolatile(), ST->isNonTemporal(),
360 MinAlign(ST->getAlignment(), Offset)));
361 // Increment the pointers.
363 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
365 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
368 // The last store may be partial. Do a truncating store. On big-endian
369 // machines this requires an extending load from the stack slot to ensure
370 // that the bits are in the right place.
371 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
372 8 * (StoredBytes - Offset));
374 // Load from the stack slot.
375 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
376 MachinePointerInfo(),
377 MemVT, false, false, 0);
379 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
381 .getWithOffset(Offset),
382 MemVT, ST->isVolatile(),
384 MinAlign(ST->getAlignment(), Offset)));
385 // The order of the stores doesn't matter - say it with a TokenFactor.
387 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
389 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
392 assert(ST->getMemoryVT().isInteger() &&
393 !ST->getMemoryVT().isVector() &&
394 "Unaligned store of unknown type.");
395 // Get the half-size VT
396 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
397 int NumBits = NewStoredVT.getSizeInBits();
398 int IncrementSize = NumBits / 8;
400 // Divide the stored value in two parts.
401 SDValue ShiftAmount = DAG.getConstant(NumBits,
402 TLI.getShiftAmountTy(Val.getValueType()));
404 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
406 // Store the two parts
407 SDValue Store1, Store2;
408 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
409 ST->getPointerInfo(), NewStoredVT,
410 ST->isVolatile(), ST->isNonTemporal(), Alignment);
411 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
412 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
413 Alignment = MinAlign(Alignment, IncrementSize);
414 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
415 ST->getPointerInfo().getWithOffset(IncrementSize),
416 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
420 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
421 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
424 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
426 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
427 const TargetLowering &TLI,
428 SDValue &ValResult, SDValue &ChainResult) {
429 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
430 "unaligned indexed loads not implemented!");
431 SDValue Chain = LD->getChain();
432 SDValue Ptr = LD->getBasePtr();
433 EVT VT = LD->getValueType(0);
434 EVT LoadedVT = LD->getMemoryVT();
436 if (VT.isFloatingPoint() || VT.isVector()) {
437 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
438 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
439 // Expand to a (misaligned) integer load of the same size,
440 // then bitconvert to floating point or vector.
441 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
444 LD->isInvariant(), LD->getAlignment());
445 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
447 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
448 ISD::ANY_EXTEND, dl, VT, Result);
455 // Copy the value to a (aligned) stack slot using (unaligned) integer
456 // loads and stores, then do a (aligned) load from the stack slot.
457 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
458 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
459 unsigned RegBytes = RegVT.getSizeInBits() / 8;
460 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
462 // Make sure the stack slot is also aligned for the register type.
463 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
465 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
466 SmallVector<SDValue, 8> Stores;
467 SDValue StackPtr = StackBase;
470 // Do all but one copies using the full register width.
471 for (unsigned i = 1; i < NumRegs; i++) {
472 // Load one integer register's worth from the original location.
473 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
474 LD->getPointerInfo().getWithOffset(Offset),
475 LD->isVolatile(), LD->isNonTemporal(),
477 MinAlign(LD->getAlignment(), Offset));
478 // Follow the load with a store to the stack slot. Remember the store.
479 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
480 MachinePointerInfo(), false, false, 0));
481 // Increment the pointers.
483 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
484 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
488 // The last copy may be partial. Do an extending load.
489 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
490 8 * (LoadedBytes - Offset));
491 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
492 LD->getPointerInfo().getWithOffset(Offset),
493 MemVT, LD->isVolatile(),
495 MinAlign(LD->getAlignment(), Offset));
496 // Follow the load with a store to the stack slot. Remember the store.
497 // On big-endian machines this requires a truncating store to ensure
498 // that the bits end up in the right place.
499 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
500 MachinePointerInfo(), MemVT,
503 // The order of the stores doesn't matter - say it with a TokenFactor.
504 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
507 // Finally, perform the original load only redirected to the stack slot.
508 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
509 MachinePointerInfo(), LoadedVT, false, false, 0);
511 // Callers expect a MERGE_VALUES node.
516 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
517 "Unaligned load of unsupported type.");
519 // Compute the new VT that is half the size of the old one. This is an
521 unsigned NumBits = LoadedVT.getSizeInBits();
523 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
526 unsigned Alignment = LD->getAlignment();
527 unsigned IncrementSize = NumBits / 8;
528 ISD::LoadExtType HiExtType = LD->getExtensionType();
530 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
531 if (HiExtType == ISD::NON_EXTLOAD)
532 HiExtType = ISD::ZEXTLOAD;
534 // Load the value in two parts
536 if (TLI.isLittleEndian()) {
537 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
538 NewLoadedVT, LD->isVolatile(),
539 LD->isNonTemporal(), Alignment);
540 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
541 DAG.getConstant(IncrementSize, Ptr.getValueType()));
542 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
543 LD->getPointerInfo().getWithOffset(IncrementSize),
544 NewLoadedVT, LD->isVolatile(),
545 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
547 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
548 NewLoadedVT, LD->isVolatile(),
549 LD->isNonTemporal(), Alignment);
550 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
551 DAG.getConstant(IncrementSize, Ptr.getValueType()));
552 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
553 LD->getPointerInfo().getWithOffset(IncrementSize),
554 NewLoadedVT, LD->isVolatile(),
555 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
558 // aggregate the two parts
559 SDValue ShiftAmount = DAG.getConstant(NumBits,
560 TLI.getShiftAmountTy(Hi.getValueType()));
561 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
562 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
564 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
571 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
572 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
573 /// is necessary to spill the vector being inserted into to memory, perform
574 /// the insert there, and then read the result back.
575 SDValue SelectionDAGLegalize::
576 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
582 // If the target doesn't support this, we have to spill the input vector
583 // to a temporary stack slot, update the element, then reload it. This is
584 // badness. We could also load the value into a vector register (either
585 // with a "move to register" or "extload into register" instruction, then
586 // permute it into place, if the idx is a constant and if the idx is
587 // supported by the target.
588 EVT VT = Tmp1.getValueType();
589 EVT EltVT = VT.getVectorElementType();
590 EVT IdxVT = Tmp3.getValueType();
591 EVT PtrVT = TLI.getPointerTy();
592 SDValue StackPtr = DAG.CreateStackTemporary(VT);
594 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
597 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
598 MachinePointerInfo::getFixedStack(SPFI),
601 // Truncate or zero extend offset to target pointer type.
602 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
603 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
604 // Add the offset to the index.
605 unsigned EltSize = EltVT.getSizeInBits()/8;
606 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
607 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
608 // Store the scalar value.
609 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
611 // Load the updated vector.
612 return DAG.getLoad(VT, dl, Ch, StackPtr,
613 MachinePointerInfo::getFixedStack(SPFI), false, false,
618 SDValue SelectionDAGLegalize::
619 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
620 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
621 // SCALAR_TO_VECTOR requires that the type of the value being inserted
622 // match the element type of the vector being created, except for
623 // integers in which case the inserted value can be over width.
624 EVT EltVT = Vec.getValueType().getVectorElementType();
625 if (Val.getValueType() == EltVT ||
626 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
627 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
628 Vec.getValueType(), Val);
630 unsigned NumElts = Vec.getValueType().getVectorNumElements();
631 // We generate a shuffle of InVec and ScVec, so the shuffle mask
632 // should be 0,1,2,3,4,5... with the appropriate element replaced with
634 SmallVector<int, 8> ShufOps;
635 for (unsigned i = 0; i != NumElts; ++i)
636 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
638 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
642 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
645 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
646 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
647 // FIXME: We shouldn't do this for TargetConstantFP's.
648 // FIXME: move this to the DAG Combiner! Note that we can't regress due
649 // to phase ordering between legalized code and the dag combiner. This
650 // probably means that we need to integrate dag combiner and legalizer
652 // We generally can't do this one for long doubles.
653 SDValue Chain = ST->getChain();
654 SDValue Ptr = ST->getBasePtr();
655 unsigned Alignment = ST->getAlignment();
656 bool isVolatile = ST->isVolatile();
657 bool isNonTemporal = ST->isNonTemporal();
659 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
660 if (CFP->getValueType(0) == MVT::f32 &&
661 TLI.isTypeLegal(MVT::i32)) {
662 SDValue Con = DAG.getConstant(CFP->getValueAPF().
663 bitcastToAPInt().zextOrTrunc(32),
665 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
666 isVolatile, isNonTemporal, Alignment);
669 if (CFP->getValueType(0) == MVT::f64) {
670 // If this target supports 64-bit registers, do a single 64-bit store.
671 if (TLI.isTypeLegal(MVT::i64)) {
672 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
673 zextOrTrunc(64), MVT::i64);
674 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
675 isVolatile, isNonTemporal, Alignment);
678 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
679 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
680 // stores. If the target supports neither 32- nor 64-bits, this
681 // xform is certainly not worth it.
682 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
683 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
684 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
685 if (TLI.isBigEndian()) std::swap(Lo, Hi);
687 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
688 isNonTemporal, Alignment);
689 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
690 DAG.getConstant(4, Ptr.getValueType()));
691 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
692 ST->getPointerInfo().getWithOffset(4),
693 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
695 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
699 return SDValue(0, 0);
702 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
703 StoreSDNode *ST = cast<StoreSDNode>(Node);
704 SDValue Chain = ST->getChain();
705 SDValue Ptr = ST->getBasePtr();
708 unsigned Alignment = ST->getAlignment();
709 bool isVolatile = ST->isVolatile();
710 bool isNonTemporal = ST->isNonTemporal();
712 if (!ST->isTruncatingStore()) {
713 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
714 ReplaceNode(ST, OptStore);
719 SDValue Value = ST->getValue();
720 MVT VT = Value.getSimpleValueType();
721 switch (TLI.getOperationAction(ISD::STORE, VT)) {
722 default: llvm_unreachable("This action is not supported yet!");
723 case TargetLowering::Legal:
724 // If this is an unaligned store and the target doesn't support it,
726 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
727 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
728 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
729 if (ST->getAlignment() < ABIAlignment)
730 ExpandUnalignedStore(cast<StoreSDNode>(Node),
734 case TargetLowering::Custom: {
735 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
737 ReplaceNode(SDValue(Node, 0), Res);
740 case TargetLowering::Promote: {
741 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
742 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
743 "Can only promote stores to same size type");
744 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
746 DAG.getStore(Chain, dl, Value, Ptr,
747 ST->getPointerInfo(), isVolatile,
748 isNonTemporal, Alignment);
749 ReplaceNode(SDValue(Node, 0), Result);
756 SDValue Value = ST->getValue();
758 EVT StVT = ST->getMemoryVT();
759 unsigned StWidth = StVT.getSizeInBits();
761 if (StWidth != StVT.getStoreSizeInBits()) {
762 // Promote to a byte-sized store with upper bits zero if not
763 // storing an integral number of bytes. For example, promote
764 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
765 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
766 StVT.getStoreSizeInBits());
767 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
769 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
770 NVT, isVolatile, isNonTemporal, Alignment);
771 ReplaceNode(SDValue(Node, 0), Result);
772 } else if (StWidth & (StWidth - 1)) {
773 // If not storing a power-of-2 number of bits, expand as two stores.
774 assert(!StVT.isVector() && "Unsupported truncstore!");
775 unsigned RoundWidth = 1 << Log2_32(StWidth);
776 assert(RoundWidth < StWidth);
777 unsigned ExtraWidth = StWidth - RoundWidth;
778 assert(ExtraWidth < RoundWidth);
779 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
780 "Store size not an integral number of bytes!");
781 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
782 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
784 unsigned IncrementSize;
786 if (TLI.isLittleEndian()) {
787 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
788 // Store the bottom RoundWidth bits.
789 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
791 isVolatile, isNonTemporal, Alignment);
793 // Store the remaining ExtraWidth bits.
794 IncrementSize = RoundWidth / 8;
795 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
796 DAG.getConstant(IncrementSize, Ptr.getValueType()));
797 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
798 DAG.getConstant(RoundWidth,
799 TLI.getShiftAmountTy(Value.getValueType())));
800 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
801 ST->getPointerInfo().getWithOffset(IncrementSize),
802 ExtraVT, isVolatile, isNonTemporal,
803 MinAlign(Alignment, IncrementSize));
805 // Big endian - avoid unaligned stores.
806 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
807 // Store the top RoundWidth bits.
808 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
809 DAG.getConstant(ExtraWidth,
810 TLI.getShiftAmountTy(Value.getValueType())));
811 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
812 RoundVT, isVolatile, isNonTemporal, Alignment);
814 // Store the remaining ExtraWidth bits.
815 IncrementSize = RoundWidth / 8;
816 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
817 DAG.getConstant(IncrementSize, Ptr.getValueType()));
818 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
819 ST->getPointerInfo().getWithOffset(IncrementSize),
820 ExtraVT, isVolatile, isNonTemporal,
821 MinAlign(Alignment, IncrementSize));
824 // The order of the stores doesn't matter.
825 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
826 ReplaceNode(SDValue(Node, 0), Result);
828 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(),
829 StVT.getSimpleVT())) {
830 default: llvm_unreachable("This action is not supported yet!");
831 case TargetLowering::Legal:
832 // If this is an unaligned store and the target doesn't support it,
834 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
835 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
836 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
837 if (ST->getAlignment() < ABIAlignment)
838 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
841 case TargetLowering::Custom: {
842 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
844 ReplaceNode(SDValue(Node, 0), Res);
847 case TargetLowering::Expand:
848 assert(!StVT.isVector() &&
849 "Vector Stores are handled in LegalizeVectorOps");
851 // TRUNCSTORE:i16 i32 -> STORE i16
852 assert(TLI.isTypeLegal(StVT) &&
853 "Do not know how to expand this store!");
854 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
856 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
857 isVolatile, isNonTemporal, Alignment);
858 ReplaceNode(SDValue(Node, 0), Result);
865 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
866 LoadSDNode *LD = cast<LoadSDNode>(Node);
867 SDValue Chain = LD->getChain(); // The chain.
868 SDValue Ptr = LD->getBasePtr(); // The base pointer.
869 SDValue Value; // The value returned by the load op.
872 ISD::LoadExtType ExtType = LD->getExtensionType();
873 if (ExtType == ISD::NON_EXTLOAD) {
874 MVT VT = Node->getSimpleValueType(0);
875 SDValue RVal = SDValue(Node, 0);
876 SDValue RChain = SDValue(Node, 1);
878 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
879 default: llvm_unreachable("This action is not supported yet!");
880 case TargetLowering::Legal:
881 // If this is an unaligned load and the target doesn't support it,
883 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
884 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
885 unsigned ABIAlignment =
886 TLI.getDataLayout()->getABITypeAlignment(Ty);
887 if (LD->getAlignment() < ABIAlignment){
888 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
892 case TargetLowering::Custom: {
893 SDValue Res = TLI.LowerOperation(RVal, DAG);
896 RChain = Res.getValue(1);
900 case TargetLowering::Promote: {
901 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
902 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
903 "Can only promote loads to same size type");
905 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getPointerInfo(),
906 LD->isVolatile(), LD->isNonTemporal(),
907 LD->isInvariant(), LD->getAlignment());
908 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
909 RChain = Res.getValue(1);
913 if (RChain.getNode() != Node) {
914 assert(RVal.getNode() != Node && "Load must be completely replaced");
915 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
916 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
922 EVT SrcVT = LD->getMemoryVT();
923 unsigned SrcWidth = SrcVT.getSizeInBits();
924 unsigned Alignment = LD->getAlignment();
925 bool isVolatile = LD->isVolatile();
926 bool isNonTemporal = LD->isNonTemporal();
928 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
929 // Some targets pretend to have an i1 loading operation, and actually
930 // load an i8. This trick is correct for ZEXTLOAD because the top 7
931 // bits are guaranteed to be zero; it helps the optimizers understand
932 // that these bits are zero. It is also useful for EXTLOAD, since it
933 // tells the optimizers that those bits are undefined. It would be
934 // nice to have an effective generic way of getting these benefits...
935 // Until such a way is found, don't insist on promoting i1 here.
937 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
938 // Promote to a byte-sized load if not loading an integral number of
939 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
940 unsigned NewWidth = SrcVT.getStoreSizeInBits();
941 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
944 // The extra bits are guaranteed to be zero, since we stored them that
945 // way. A zext load from NVT thus automatically gives zext from SrcVT.
947 ISD::LoadExtType NewExtType =
948 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
951 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
952 Chain, Ptr, LD->getPointerInfo(),
953 NVT, isVolatile, isNonTemporal, Alignment);
955 Ch = Result.getValue(1); // The chain.
957 if (ExtType == ISD::SEXTLOAD)
958 // Having the top bits zero doesn't help when sign extending.
959 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
960 Result.getValueType(),
961 Result, DAG.getValueType(SrcVT));
962 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
963 // All the top bits are guaranteed to be zero - inform the optimizers.
964 Result = DAG.getNode(ISD::AssertZext, dl,
965 Result.getValueType(), Result,
966 DAG.getValueType(SrcVT));
970 } else if (SrcWidth & (SrcWidth - 1)) {
971 // If not loading a power-of-2 number of bits, expand as two loads.
972 assert(!SrcVT.isVector() && "Unsupported extload!");
973 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
974 assert(RoundWidth < SrcWidth);
975 unsigned ExtraWidth = SrcWidth - RoundWidth;
976 assert(ExtraWidth < RoundWidth);
977 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
978 "Load size not an integral number of bytes!");
979 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
980 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
982 unsigned IncrementSize;
984 if (TLI.isLittleEndian()) {
985 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
986 // Load the bottom RoundWidth bits.
987 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
989 LD->getPointerInfo(), RoundVT, isVolatile,
990 isNonTemporal, Alignment);
992 // Load the remaining ExtraWidth bits.
993 IncrementSize = RoundWidth / 8;
994 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
995 DAG.getConstant(IncrementSize, Ptr.getValueType()));
996 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
997 LD->getPointerInfo().getWithOffset(IncrementSize),
998 ExtraVT, isVolatile, isNonTemporal,
999 MinAlign(Alignment, IncrementSize));
1001 // Build a factor node to remember that this load is independent of
1003 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1006 // Move the top bits to the right place.
1007 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1008 DAG.getConstant(RoundWidth,
1009 TLI.getShiftAmountTy(Hi.getValueType())));
1011 // Join the hi and lo parts.
1012 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1014 // Big endian - avoid unaligned loads.
1015 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1016 // Load the top RoundWidth bits.
1017 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1018 LD->getPointerInfo(), RoundVT, isVolatile,
1019 isNonTemporal, Alignment);
1021 // Load the remaining ExtraWidth bits.
1022 IncrementSize = RoundWidth / 8;
1023 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1024 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1025 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1026 dl, Node->getValueType(0), Chain, Ptr,
1027 LD->getPointerInfo().getWithOffset(IncrementSize),
1028 ExtraVT, isVolatile, isNonTemporal,
1029 MinAlign(Alignment, IncrementSize));
1031 // Build a factor node to remember that this load is independent of
1033 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1036 // Move the top bits to the right place.
1037 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1038 DAG.getConstant(ExtraWidth,
1039 TLI.getShiftAmountTy(Hi.getValueType())));
1041 // Join the hi and lo parts.
1042 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1047 bool isCustom = false;
1048 switch (TLI.getLoadExtAction(ExtType, SrcVT.getSimpleVT())) {
1049 default: llvm_unreachable("This action is not supported yet!");
1050 case TargetLowering::Custom:
1053 case TargetLowering::Legal: {
1054 Value = SDValue(Node, 0);
1055 Chain = SDValue(Node, 1);
1058 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1059 if (Res.getNode()) {
1061 Chain = Res.getValue(1);
1064 // If this is an unaligned load and the target doesn't support it,
1066 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1068 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1069 unsigned ABIAlignment =
1070 TLI.getDataLayout()->getABITypeAlignment(Ty);
1071 if (LD->getAlignment() < ABIAlignment){
1072 ExpandUnalignedLoad(cast<LoadSDNode>(Node),
1073 DAG, TLI, Value, Chain);
1079 case TargetLowering::Expand:
1080 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
1081 SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr,
1082 LD->getPointerInfo(),
1083 LD->isVolatile(), LD->isNonTemporal(),
1084 LD->isInvariant(), LD->getAlignment());
1088 ExtendOp = (SrcVT.isFloatingPoint() ?
1089 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1091 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1092 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1093 default: llvm_unreachable("Unexpected extend load type!");
1095 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1096 Chain = Load.getValue(1);
1100 assert(!SrcVT.isVector() &&
1101 "Vector Loads are handled in LegalizeVectorOps");
1103 // FIXME: This does not work for vectors on most targets. Sign- and
1104 // zero-extend operations are currently folded into extending loads,
1105 // whether they are legal or not, and then we end up here without any
1106 // support for legalizing them.
1107 assert(ExtType != ISD::EXTLOAD &&
1108 "EXTLOAD should always be supported!");
1109 // Turn the unsupported load into an EXTLOAD followed by an explicit
1110 // zero/sign extend inreg.
1111 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1112 Chain, Ptr, LD->getPointerInfo(), SrcVT,
1113 LD->isVolatile(), LD->isNonTemporal(),
1114 LD->getAlignment());
1116 if (ExtType == ISD::SEXTLOAD)
1117 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1118 Result.getValueType(),
1119 Result, DAG.getValueType(SrcVT));
1121 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1123 Chain = Result.getValue(1);
1128 // Since loads produce two values, make sure to remember that we legalized
1130 if (Chain.getNode() != Node) {
1131 assert(Value.getNode() != Node && "Load must be completely replaced");
1132 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1133 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1138 /// LegalizeOp - Return a legal replacement for the given operation, with
1139 /// all legal operands.
1140 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1141 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1144 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1145 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1146 TargetLowering::TypeLegal &&
1147 "Unexpected illegal type!");
1149 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1150 assert((TLI.getTypeAction(*DAG.getContext(),
1151 Node->getOperand(i).getValueType()) ==
1152 TargetLowering::TypeLegal ||
1153 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1154 "Unexpected illegal type!");
1156 // Figure out the correct action; the way to query this varies by opcode
1157 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1158 bool SimpleFinishLegalizing = true;
1159 switch (Node->getOpcode()) {
1160 case ISD::INTRINSIC_W_CHAIN:
1161 case ISD::INTRINSIC_WO_CHAIN:
1162 case ISD::INTRINSIC_VOID:
1163 case ISD::STACKSAVE:
1164 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1167 Action = TLI.getOperationAction(Node->getOpcode(),
1168 Node->getValueType(0));
1169 if (Action != TargetLowering::Promote)
1170 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1172 case ISD::SINT_TO_FP:
1173 case ISD::UINT_TO_FP:
1174 case ISD::EXTRACT_VECTOR_ELT:
1175 Action = TLI.getOperationAction(Node->getOpcode(),
1176 Node->getOperand(0).getValueType());
1178 case ISD::FP_ROUND_INREG:
1179 case ISD::SIGN_EXTEND_INREG: {
1180 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1181 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1184 case ISD::ATOMIC_STORE: {
1185 Action = TLI.getOperationAction(Node->getOpcode(),
1186 Node->getOperand(2).getValueType());
1189 case ISD::SELECT_CC:
1192 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1193 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1194 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1195 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1196 ISD::CondCode CCCode =
1197 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1198 Action = TLI.getCondCodeAction(CCCode, OpVT);
1199 if (Action == TargetLowering::Legal) {
1200 if (Node->getOpcode() == ISD::SELECT_CC)
1201 Action = TLI.getOperationAction(Node->getOpcode(),
1202 Node->getValueType(0));
1204 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1210 // FIXME: Model these properly. LOAD and STORE are complicated, and
1211 // STORE expects the unlegalized operand in some cases.
1212 SimpleFinishLegalizing = false;
1214 case ISD::CALLSEQ_START:
1215 case ISD::CALLSEQ_END:
1216 // FIXME: This shouldn't be necessary. These nodes have special properties
1217 // dealing with the recursive nature of legalization. Removing this
1218 // special case should be done as part of making LegalizeDAG non-recursive.
1219 SimpleFinishLegalizing = false;
1221 case ISD::EXTRACT_ELEMENT:
1222 case ISD::FLT_ROUNDS_:
1230 case ISD::MERGE_VALUES:
1231 case ISD::EH_RETURN:
1232 case ISD::FRAME_TO_ARGS_OFFSET:
1233 case ISD::EH_SJLJ_SETJMP:
1234 case ISD::EH_SJLJ_LONGJMP:
1235 // These operations lie about being legal: when they claim to be legal,
1236 // they should actually be expanded.
1237 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1238 if (Action == TargetLowering::Legal)
1239 Action = TargetLowering::Expand;
1241 case ISD::INIT_TRAMPOLINE:
1242 case ISD::ADJUST_TRAMPOLINE:
1243 case ISD::FRAMEADDR:
1244 case ISD::RETURNADDR:
1245 // These operations lie about being legal: when they claim to be legal,
1246 // they should actually be custom-lowered.
1247 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1248 if (Action == TargetLowering::Legal)
1249 Action = TargetLowering::Custom;
1251 case ISD::DEBUGTRAP:
1252 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1253 if (Action == TargetLowering::Expand) {
1254 // replace ISD::DEBUGTRAP with ISD::TRAP
1256 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1257 Node->getOperand(0));
1258 ReplaceNode(Node, NewVal.getNode());
1259 LegalizeOp(NewVal.getNode());
1265 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1266 Action = TargetLowering::Legal;
1268 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1273 if (SimpleFinishLegalizing) {
1274 SDNode *NewNode = Node;
1275 switch (Node->getOpcode()) {
1282 // Legalizing shifts/rotates requires adjusting the shift amount
1283 // to the appropriate width.
1284 if (!Node->getOperand(1).getValueType().isVector()) {
1286 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1287 Node->getOperand(1));
1288 HandleSDNode Handle(SAO);
1289 LegalizeOp(SAO.getNode());
1290 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1294 case ISD::SRL_PARTS:
1295 case ISD::SRA_PARTS:
1296 case ISD::SHL_PARTS:
1297 // Legalizing shifts/rotates requires adjusting the shift amount
1298 // to the appropriate width.
1299 if (!Node->getOperand(2).getValueType().isVector()) {
1301 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1302 Node->getOperand(2));
1303 HandleSDNode Handle(SAO);
1304 LegalizeOp(SAO.getNode());
1305 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1306 Node->getOperand(1),
1312 if (NewNode != Node) {
1313 DAG.ReplaceAllUsesWith(Node, NewNode);
1314 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1315 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
1320 case TargetLowering::Legal:
1322 case TargetLowering::Custom: {
1323 // FIXME: The handling for custom lowering with multiple results is
1325 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1326 if (Res.getNode()) {
1327 SmallVector<SDValue, 8> ResultVals;
1328 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1330 ResultVals.push_back(Res);
1332 ResultVals.push_back(Res.getValue(i));
1334 if (Res.getNode() != Node || Res.getResNo() != 0) {
1335 DAG.ReplaceAllUsesWith(Node, ResultVals.data());
1336 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1337 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
1344 case TargetLowering::Expand:
1347 case TargetLowering::Promote:
1353 switch (Node->getOpcode()) {
1360 llvm_unreachable("Do not know how to legalize this operator!");
1362 case ISD::CALLSEQ_START:
1363 case ISD::CALLSEQ_END:
1366 return LegalizeLoadOps(Node);
1369 return LegalizeStoreOps(Node);
1374 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1375 SDValue Vec = Op.getOperand(0);
1376 SDValue Idx = Op.getOperand(1);
1378 // Store the value to a temporary stack slot, then LOAD the returned part.
1379 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1380 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1381 MachinePointerInfo(), false, false, 0);
1383 // Add the offset to the index.
1385 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1386 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1387 DAG.getConstant(EltSize, Idx.getValueType()));
1389 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1390 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1392 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1394 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1396 if (Op.getValueType().isVector())
1397 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1398 false, false, false, 0);
1399 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1400 MachinePointerInfo(),
1401 Vec.getValueType().getVectorElementType(),
1405 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1406 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1408 SDValue Vec = Op.getOperand(0);
1409 SDValue Part = Op.getOperand(1);
1410 SDValue Idx = Op.getOperand(2);
1413 // Store the value to a temporary stack slot, then LOAD the returned part.
1415 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1416 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1417 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1419 // First store the whole vector.
1420 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1423 // Then store the inserted part.
1425 // Add the offset to the index.
1427 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1429 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1430 DAG.getConstant(EltSize, Idx.getValueType()));
1432 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1433 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1435 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1437 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1440 // Store the subvector.
1441 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1442 MachinePointerInfo(), false, false, 0);
1444 // Finally, load the updated vector.
1445 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1446 false, false, false, 0);
1449 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1450 // We can't handle this case efficiently. Allocate a sufficiently
1451 // aligned object on the stack, store each element into it, then load
1452 // the result as a vector.
1453 // Create the stack frame object.
1454 EVT VT = Node->getValueType(0);
1455 EVT EltVT = VT.getVectorElementType();
1457 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1458 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1459 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1461 // Emit a store of each element to the stack slot.
1462 SmallVector<SDValue, 8> Stores;
1463 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1464 // Store (in the right endianness) the elements to memory.
1465 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1466 // Ignore undef elements.
1467 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1469 unsigned Offset = TypeByteSize*i;
1471 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1472 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1474 // If the destination vector element type is narrower than the source
1475 // element type, only store the bits necessary.
1476 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1477 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1478 Node->getOperand(i), Idx,
1479 PtrInfo.getWithOffset(Offset),
1480 EltVT, false, false, 0));
1482 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1483 Node->getOperand(i), Idx,
1484 PtrInfo.getWithOffset(Offset),
1489 if (!Stores.empty()) // Not all undef elements?
1490 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1491 &Stores[0], Stores.size());
1493 StoreChain = DAG.getEntryNode();
1495 // Result is a load from the stack slot.
1496 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1497 false, false, false, 0);
1500 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1502 SDValue Tmp1 = Node->getOperand(0);
1503 SDValue Tmp2 = Node->getOperand(1);
1505 // Get the sign bit of the RHS. First obtain a value that has the same
1506 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1508 EVT FloatVT = Tmp2.getValueType();
1509 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1510 if (TLI.isTypeLegal(IVT)) {
1511 // Convert to an integer with the same sign bit.
1512 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1514 // Store the float to memory, then load the sign part out as an integer.
1515 MVT LoadTy = TLI.getPointerTy();
1516 // First create a temporary that is aligned for both the load and store.
1517 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1518 // Then store the float to it.
1520 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1522 if (TLI.isBigEndian()) {
1523 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1524 // Load out a legal integer with the same sign bit as the float.
1525 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1526 false, false, false, 0);
1527 } else { // Little endian
1528 SDValue LoadPtr = StackPtr;
1529 // The float may be wider than the integer we are going to load. Advance
1530 // the pointer so that the loaded integer will contain the sign bit.
1531 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1532 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1533 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1535 DAG.getConstant(ByteOffset, LoadPtr.getValueType()));
1536 // Load a legal integer containing the sign bit.
1537 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1538 false, false, false, 0);
1539 // Move the sign bit to the top bit of the loaded integer.
1540 unsigned BitShift = LoadTy.getSizeInBits() -
1541 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1542 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1544 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1545 DAG.getConstant(BitShift,
1546 TLI.getShiftAmountTy(SignBit.getValueType())));
1549 // Now get the sign bit proper, by seeing whether the value is negative.
1550 SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
1551 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1553 // Get the absolute value of the result.
1554 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1555 // Select between the nabs and abs value based on the sign bit of
1557 return DAG.getSelect(dl, AbsVal.getValueType(), SignBit,
1558 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1562 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1563 SmallVectorImpl<SDValue> &Results) {
1564 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1565 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1566 " not tell us which reg is the stack pointer!");
1568 EVT VT = Node->getValueType(0);
1569 SDValue Tmp1 = SDValue(Node, 0);
1570 SDValue Tmp2 = SDValue(Node, 1);
1571 SDValue Tmp3 = Node->getOperand(2);
1572 SDValue Chain = Tmp1.getOperand(0);
1574 // Chain the dynamic stack allocation so that it doesn't modify the stack
1575 // pointer when other instructions are using the stack.
1576 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
1579 SDValue Size = Tmp2.getOperand(1);
1580 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1581 Chain = SP.getValue(1);
1582 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1583 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1584 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1585 if (Align > StackAlign)
1586 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1587 DAG.getConstant(-(uint64_t)Align, VT));
1588 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1590 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1591 DAG.getIntPtrConstant(0, true), SDValue(),
1594 Results.push_back(Tmp1);
1595 Results.push_back(Tmp2);
1598 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1599 /// condition code CC on the current target.
1600 /// If the SETCC has been legalized using AND / OR, then the legalized node
1601 /// will be stored in LHS. RHS and CC will be set to SDValue().
1602 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1603 /// then the values of LHS and RHS will be swapped and CC will be set to the
1605 /// \returns true if the SetCC has been legalized, false if it hasn't.
1606 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1607 SDValue &LHS, SDValue &RHS,
1610 MVT OpVT = LHS.getSimpleValueType();
1611 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1612 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1613 default: llvm_unreachable("Unknown condition code action!");
1614 case TargetLowering::Legal:
1617 case TargetLowering::Expand: {
1618 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1619 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1620 std::swap(LHS, RHS);
1621 CC = DAG.getCondCode(InvCC);
1624 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1627 default: llvm_unreachable("Don't know how to expand this condition!");
1629 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1630 == TargetLowering::Legal
1631 && "If SETO is expanded, SETOEQ must be legal!");
1632 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1634 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1635 == TargetLowering::Legal
1636 && "If SETUO is expanded, SETUNE must be legal!");
1637 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1650 // If we are floating point, assign and break, otherwise fall through.
1651 if (!OpVT.isInteger()) {
1652 // We can use the 4th bit to tell if we are the unordered
1653 // or ordered version of the opcode.
1654 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1655 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1656 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1659 // Fallthrough if we are unsigned integer.
1666 // We only support using the inverted operation, which is computed above
1667 // and not a different manner of supporting expanding these cases.
1668 llvm_unreachable("Don't know how to expand this condition!");
1671 SDValue SetCC1, SetCC2;
1672 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1673 // If we aren't the ordered or unorder operation,
1674 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1675 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1676 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1678 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1679 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1680 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1682 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1691 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1692 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1693 /// a load from the stack slot to DestVT, extending it if needed.
1694 /// The resultant code need not be legal.
1695 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1699 // Create the stack frame object.
1701 TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType().
1702 getTypeForEVT(*DAG.getContext()));
1703 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1705 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1706 int SPFI = StackPtrFI->getIndex();
1707 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1709 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1710 unsigned SlotSize = SlotVT.getSizeInBits();
1711 unsigned DestSize = DestVT.getSizeInBits();
1712 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1713 unsigned DestAlign = TLI.getDataLayout()->getPrefTypeAlignment(DestType);
1715 // Emit a store to the stack slot. Use a truncstore if the input value is
1716 // later than DestVT.
1719 if (SrcSize > SlotSize)
1720 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1721 PtrInfo, SlotVT, false, false, SrcAlign);
1723 assert(SrcSize == SlotSize && "Invalid store");
1724 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1725 PtrInfo, false, false, SrcAlign);
1728 // Result is a load from the stack slot.
1729 if (SlotSize == DestSize)
1730 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1731 false, false, false, DestAlign);
1733 assert(SlotSize < DestSize && "Unknown extension!");
1734 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1735 PtrInfo, SlotVT, false, false, DestAlign);
1738 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1740 // Create a vector sized/aligned stack slot, store the value to element #0,
1741 // then load the whole vector back out.
1742 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1744 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1745 int SPFI = StackPtrFI->getIndex();
1747 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1749 MachinePointerInfo::getFixedStack(SPFI),
1750 Node->getValueType(0).getVectorElementType(),
1752 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1753 MachinePointerInfo::getFixedStack(SPFI),
1754 false, false, false, 0);
1758 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1759 /// support the operation, but do support the resultant vector type.
1760 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1761 unsigned NumElems = Node->getNumOperands();
1762 SDValue Value1, Value2;
1764 EVT VT = Node->getValueType(0);
1765 EVT OpVT = Node->getOperand(0).getValueType();
1766 EVT EltVT = VT.getVectorElementType();
1768 // If the only non-undef value is the low element, turn this into a
1769 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1770 bool isOnlyLowElement = true;
1771 bool MoreThanTwoValues = false;
1772 bool isConstant = true;
1773 for (unsigned i = 0; i < NumElems; ++i) {
1774 SDValue V = Node->getOperand(i);
1775 if (V.getOpcode() == ISD::UNDEF)
1778 isOnlyLowElement = false;
1779 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1782 if (!Value1.getNode()) {
1784 } else if (!Value2.getNode()) {
1787 } else if (V != Value1 && V != Value2) {
1788 MoreThanTwoValues = true;
1792 if (!Value1.getNode())
1793 return DAG.getUNDEF(VT);
1795 if (isOnlyLowElement)
1796 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1798 // If all elements are constants, create a load from the constant pool.
1800 SmallVector<Constant*, 16> CV;
1801 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1802 if (ConstantFPSDNode *V =
1803 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1804 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1805 } else if (ConstantSDNode *V =
1806 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1808 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1810 // If OpVT and EltVT don't match, EltVT is not legal and the
1811 // element values have been promoted/truncated earlier. Undo this;
1812 // we don't want a v16i8 to become a v16i32 for example.
1813 const ConstantInt *CI = V->getConstantIntValue();
1814 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1815 CI->getZExtValue()));
1818 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1819 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1820 CV.push_back(UndefValue::get(OpNTy));
1823 Constant *CP = ConstantVector::get(CV);
1824 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1825 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1826 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1827 MachinePointerInfo::getConstantPool(),
1828 false, false, false, Alignment);
1831 if (!MoreThanTwoValues) {
1832 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1833 for (unsigned i = 0; i < NumElems; ++i) {
1834 SDValue V = Node->getOperand(i);
1835 if (V.getOpcode() == ISD::UNDEF)
1837 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1839 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1840 // Get the splatted value into the low element of a vector register.
1841 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1843 if (Value2.getNode())
1844 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1846 Vec2 = DAG.getUNDEF(VT);
1848 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1849 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1853 // Otherwise, we can't handle this case efficiently.
1854 return ExpandVectorBuildThroughStack(Node);
1857 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1858 // does not fit into a register, return the lo part and set the hi part to the
1859 // by-reg argument. If it does fit into a single register, return the result
1860 // and leave the Hi part unset.
1861 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1863 TargetLowering::ArgListTy Args;
1864 TargetLowering::ArgListEntry Entry;
1865 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1866 EVT ArgVT = Node->getOperand(i).getValueType();
1867 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1868 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1869 Entry.isSExt = isSigned;
1870 Entry.isZExt = !isSigned;
1871 Args.push_back(Entry);
1873 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1874 TLI.getPointerTy());
1876 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1878 // By default, the input chain to this libcall is the entry node of the
1879 // function. If the libcall is going to be emitted as a tail call then
1880 // TLI.isUsedByReturnOnly will change it to the right chain if the return
1881 // node which is being folded has a non-entry input chain.
1882 SDValue InChain = DAG.getEntryNode();
1884 // isTailCall may be true since the callee does not reference caller stack
1885 // frame. Check if it's in the right position.
1886 SDValue TCChain = InChain;
1887 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
1892 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1893 0, TLI.getLibcallCallingConv(LC), isTailCall,
1894 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1895 Callee, Args, DAG, SDLoc(Node));
1896 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1899 if (!CallInfo.second.getNode())
1900 // It's a tailcall, return the chain (which is the DAG root).
1901 return DAG.getRoot();
1903 return CallInfo.first;
1906 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
1907 /// and returning a result of type RetVT.
1908 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
1909 const SDValue *Ops, unsigned NumOps,
1910 bool isSigned, SDLoc dl) {
1911 TargetLowering::ArgListTy Args;
1912 Args.reserve(NumOps);
1914 TargetLowering::ArgListEntry Entry;
1915 for (unsigned i = 0; i != NumOps; ++i) {
1916 Entry.Node = Ops[i];
1917 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
1918 Entry.isSExt = isSigned;
1919 Entry.isZExt = !isSigned;
1920 Args.push_back(Entry);
1922 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1923 TLI.getPointerTy());
1925 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
1927 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
1928 false, 0, TLI.getLibcallCallingConv(LC),
1929 /*isTailCall=*/false,
1930 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1931 Callee, Args, DAG, dl);
1932 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
1934 return CallInfo.first;
1937 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
1938 // ExpandLibCall except that the first operand is the in-chain.
1939 std::pair<SDValue, SDValue>
1940 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
1943 SDValue InChain = Node->getOperand(0);
1945 TargetLowering::ArgListTy Args;
1946 TargetLowering::ArgListEntry Entry;
1947 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
1948 EVT ArgVT = Node->getOperand(i).getValueType();
1949 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1950 Entry.Node = Node->getOperand(i);
1952 Entry.isSExt = isSigned;
1953 Entry.isZExt = !isSigned;
1954 Args.push_back(Entry);
1956 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1957 TLI.getPointerTy());
1959 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1961 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1962 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
1963 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1964 Callee, Args, DAG, SDLoc(Node));
1965 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1970 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1971 RTLIB::Libcall Call_F32,
1972 RTLIB::Libcall Call_F64,
1973 RTLIB::Libcall Call_F80,
1974 RTLIB::Libcall Call_F128,
1975 RTLIB::Libcall Call_PPCF128) {
1977 switch (Node->getSimpleValueType(0).SimpleTy) {
1978 default: llvm_unreachable("Unexpected request for libcall!");
1979 case MVT::f32: LC = Call_F32; break;
1980 case MVT::f64: LC = Call_F64; break;
1981 case MVT::f80: LC = Call_F80; break;
1982 case MVT::f128: LC = Call_F128; break;
1983 case MVT::ppcf128: LC = Call_PPCF128; break;
1985 return ExpandLibCall(LC, Node, false);
1988 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1989 RTLIB::Libcall Call_I8,
1990 RTLIB::Libcall Call_I16,
1991 RTLIB::Libcall Call_I32,
1992 RTLIB::Libcall Call_I64,
1993 RTLIB::Libcall Call_I128) {
1995 switch (Node->getSimpleValueType(0).SimpleTy) {
1996 default: llvm_unreachable("Unexpected request for libcall!");
1997 case MVT::i8: LC = Call_I8; break;
1998 case MVT::i16: LC = Call_I16; break;
1999 case MVT::i32: LC = Call_I32; break;
2000 case MVT::i64: LC = Call_I64; break;
2001 case MVT::i128: LC = Call_I128; break;
2003 return ExpandLibCall(LC, Node, isSigned);
2006 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
2007 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2008 const TargetLowering &TLI) {
2010 switch (Node->getSimpleValueType(0).SimpleTy) {
2011 default: llvm_unreachable("Unexpected request for libcall!");
2012 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2013 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2014 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2015 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2016 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2019 return TLI.getLibcallName(LC) != 0;
2022 /// useDivRem - Only issue divrem libcall if both quotient and remainder are
2024 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2025 // The other use might have been replaced with a divrem already.
2026 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2027 unsigned OtherOpcode = 0;
2029 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2031 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2033 SDValue Op0 = Node->getOperand(0);
2034 SDValue Op1 = Node->getOperand(1);
2035 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2036 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2040 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2041 User->getOperand(0) == Op0 &&
2042 User->getOperand(1) == Op1)
2048 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2051 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2052 SmallVectorImpl<SDValue> &Results) {
2053 unsigned Opcode = Node->getOpcode();
2054 bool isSigned = Opcode == ISD::SDIVREM;
2057 switch (Node->getSimpleValueType(0).SimpleTy) {
2058 default: llvm_unreachable("Unexpected request for libcall!");
2059 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2060 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2061 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2062 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2063 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2066 // The input chain to this libcall is the entry node of the function.
2067 // Legalizing the call will automatically add the previous call to the
2069 SDValue InChain = DAG.getEntryNode();
2071 EVT RetVT = Node->getValueType(0);
2072 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2074 TargetLowering::ArgListTy Args;
2075 TargetLowering::ArgListEntry Entry;
2076 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2077 EVT ArgVT = Node->getOperand(i).getValueType();
2078 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2079 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2080 Entry.isSExt = isSigned;
2081 Entry.isZExt = !isSigned;
2082 Args.push_back(Entry);
2085 // Also pass the return address of the remainder.
2086 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2088 Entry.Ty = RetTy->getPointerTo();
2089 Entry.isSExt = isSigned;
2090 Entry.isZExt = !isSigned;
2091 Args.push_back(Entry);
2093 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2094 TLI.getPointerTy());
2098 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2099 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2100 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2101 Callee, Args, DAG, dl);
2102 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2104 // Remainder is loaded back from the stack frame.
2105 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2106 MachinePointerInfo(), false, false, false, 0);
2107 Results.push_back(CallInfo.first);
2108 Results.push_back(Rem);
2111 /// isSinCosLibcallAvailable - Return true if sincos libcall is available.
2112 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2114 switch (Node->getSimpleValueType(0).SimpleTy) {
2115 default: llvm_unreachable("Unexpected request for libcall!");
2116 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2117 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2118 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2119 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2120 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2122 return TLI.getLibcallName(LC) != 0;
2125 /// canCombineSinCosLibcall - Return true if sincos libcall is available and
2126 /// can be used to combine sin and cos.
2127 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2128 const TargetMachine &TM) {
2129 if (!isSinCosLibcallAvailable(Node, TLI))
2131 // GNU sin/cos functions set errno while sincos does not. Therefore
2132 // combining sin and cos is only safe if unsafe-fpmath is enabled.
2133 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2134 if (isGNU && !TM.Options.UnsafeFPMath)
2139 /// useSinCos - Only issue sincos libcall if both sin and cos are
2141 static bool useSinCos(SDNode *Node) {
2142 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2143 ? ISD::FCOS : ISD::FSIN;
2145 SDValue Op0 = Node->getOperand(0);
2146 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2147 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2151 // The other user might have been turned into sincos already.
2152 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2158 /// ExpandSinCosLibCall - Issue libcalls to sincos to compute sin / cos
2161 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2162 SmallVectorImpl<SDValue> &Results) {
2164 switch (Node->getSimpleValueType(0).SimpleTy) {
2165 default: llvm_unreachable("Unexpected request for libcall!");
2166 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2167 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2168 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2169 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2170 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2173 // The input chain to this libcall is the entry node of the function.
2174 // Legalizing the call will automatically add the previous call to the
2176 SDValue InChain = DAG.getEntryNode();
2178 EVT RetVT = Node->getValueType(0);
2179 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2181 TargetLowering::ArgListTy Args;
2182 TargetLowering::ArgListEntry Entry;
2184 // Pass the argument.
2185 Entry.Node = Node->getOperand(0);
2187 Entry.isSExt = false;
2188 Entry.isZExt = false;
2189 Args.push_back(Entry);
2191 // Pass the return address of sin.
2192 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2193 Entry.Node = SinPtr;
2194 Entry.Ty = RetTy->getPointerTo();
2195 Entry.isSExt = false;
2196 Entry.isZExt = false;
2197 Args.push_back(Entry);
2199 // Also pass the return address of the cos.
2200 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2201 Entry.Node = CosPtr;
2202 Entry.Ty = RetTy->getPointerTo();
2203 Entry.isSExt = false;
2204 Entry.isZExt = false;
2205 Args.push_back(Entry);
2207 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2208 TLI.getPointerTy());
2212 CallLoweringInfo CLI(InChain, Type::getVoidTy(*DAG.getContext()),
2213 false, false, false, false,
2214 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2215 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2216 Callee, Args, DAG, dl);
2217 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2219 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2220 MachinePointerInfo(), false, false, false, 0));
2221 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2222 MachinePointerInfo(), false, false, false, 0));
2225 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2226 /// INT_TO_FP operation of the specified operand when the target requests that
2227 /// we expand it. At this point, we know that the result and operand types are
2228 /// legal for the target.
2229 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2233 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2234 // simple 32-bit [signed|unsigned] integer to float/double expansion
2236 // Get the stack frame index of a 8 byte buffer.
2237 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2239 // word offset constant for Hi/Lo address computation
2240 SDValue WordOff = DAG.getConstant(sizeof(int), StackSlot.getValueType());
2241 // set up Hi and Lo (into buffer) address based on endian
2242 SDValue Hi = StackSlot;
2243 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2244 StackSlot, WordOff);
2245 if (TLI.isLittleEndian())
2248 // if signed map to unsigned space
2251 // constant used to invert sign bit (signed to unsigned mapping)
2252 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2253 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2257 // store the lo of the constructed double - based on integer input
2258 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2259 Op0Mapped, Lo, MachinePointerInfo(),
2261 // initial hi portion of constructed double
2262 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2263 // store the hi of the constructed double - biased exponent
2264 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2265 MachinePointerInfo(),
2267 // load the constructed double
2268 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2269 MachinePointerInfo(), false, false, false, 0);
2270 // FP constant to bias correct the final result
2271 SDValue Bias = DAG.getConstantFP(isSigned ?
2272 BitsToDouble(0x4330000080000000ULL) :
2273 BitsToDouble(0x4330000000000000ULL),
2275 // subtract the bias
2276 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2279 // handle final rounding
2280 if (DestVT == MVT::f64) {
2283 } else if (DestVT.bitsLT(MVT::f64)) {
2284 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2285 DAG.getIntPtrConstant(0));
2286 } else if (DestVT.bitsGT(MVT::f64)) {
2287 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2291 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2292 // Code below here assumes !isSigned without checking again.
2294 // Implementation of unsigned i64 to f64 following the algorithm in
2295 // __floatundidf in compiler_rt. This implementation has the advantage
2296 // of performing rounding correctly, both in the default rounding mode
2297 // and in all alternate rounding modes.
2298 // TODO: Generalize this for use with other types.
2299 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2301 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2302 SDValue TwoP84PlusTwoP52 =
2303 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2305 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2307 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2308 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2309 DAG.getConstant(32, MVT::i64));
2310 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2311 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2312 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2313 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2314 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2316 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2319 // Implementation of unsigned i64 to f32.
2320 // TODO: Generalize this for use with other types.
2321 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2322 // For unsigned conversions, convert them to signed conversions using the
2323 // algorithm from the x86_64 __floatundidf in compiler_rt.
2325 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2327 SDValue ShiftConst =
2328 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2329 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2330 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2331 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2332 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2334 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2335 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2337 // TODO: This really should be implemented using a branch rather than a
2338 // select. We happen to get lucky and machinesink does the right
2339 // thing most of the time. This would be a good candidate for a
2340 //pseudo-op, or, even better, for whole-function isel.
2341 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2342 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2343 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2346 // Otherwise, implement the fully general conversion.
2348 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2349 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2350 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2351 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2352 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2353 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2354 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2355 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2356 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2357 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2358 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2360 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2361 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2363 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2364 DAG.getConstant(32, SHVT));
2365 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2366 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2368 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2369 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2370 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2371 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2372 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2373 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2374 DAG.getIntPtrConstant(0));
2377 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2379 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2380 Op0, DAG.getConstant(0, Op0.getValueType()),
2382 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2383 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2384 SignSet, Four, Zero);
2386 // If the sign bit of the integer is set, the large number will be treated
2387 // as a negative number. To counteract this, the dynamic code adds an
2388 // offset depending on the data type.
2390 switch (Op0.getSimpleValueType().SimpleTy) {
2391 default: llvm_unreachable("Unsupported integer type!");
2392 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2393 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2394 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2395 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2397 if (TLI.isLittleEndian()) FF <<= 32;
2398 Constant *FudgeFactor = ConstantInt::get(
2399 Type::getInt64Ty(*DAG.getContext()), FF);
2401 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2402 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2403 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2404 Alignment = std::min(Alignment, 4u);
2406 if (DestVT == MVT::f32)
2407 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2408 MachinePointerInfo::getConstantPool(),
2409 false, false, false, Alignment);
2411 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2412 DAG.getEntryNode(), CPIdx,
2413 MachinePointerInfo::getConstantPool(),
2414 MVT::f32, false, false, Alignment);
2415 HandleSDNode Handle(Load);
2416 LegalizeOp(Load.getNode());
2417 FudgeInReg = Handle.getValue();
2420 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2423 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2424 /// *INT_TO_FP operation of the specified operand when the target requests that
2425 /// we promote it. At this point, we know that the result and operand types are
2426 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2427 /// operation that takes a larger input.
2428 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2432 // First step, figure out the appropriate *INT_TO_FP operation to use.
2433 EVT NewInTy = LegalOp.getValueType();
2435 unsigned OpToUse = 0;
2437 // Scan for the appropriate larger type to use.
2439 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2440 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2442 // If the target supports SINT_TO_FP of this type, use it.
2443 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2444 OpToUse = ISD::SINT_TO_FP;
2447 if (isSigned) continue;
2449 // If the target supports UINT_TO_FP of this type, use it.
2450 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2451 OpToUse = ISD::UINT_TO_FP;
2455 // Otherwise, try a larger type.
2458 // Okay, we found the operation and type to use. Zero extend our input to the
2459 // desired type then run the operation on it.
2460 return DAG.getNode(OpToUse, dl, DestVT,
2461 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2462 dl, NewInTy, LegalOp));
2465 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2466 /// FP_TO_*INT operation of the specified operand when the target requests that
2467 /// we promote it. At this point, we know that the result and operand types are
2468 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2469 /// operation that returns a larger result.
2470 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2474 // First step, figure out the appropriate FP_TO*INT operation to use.
2475 EVT NewOutTy = DestVT;
2477 unsigned OpToUse = 0;
2479 // Scan for the appropriate larger type to use.
2481 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2482 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2484 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2485 OpToUse = ISD::FP_TO_SINT;
2489 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2490 OpToUse = ISD::FP_TO_UINT;
2494 // Otherwise, try a larger type.
2498 // Okay, we found the operation and type to use.
2499 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2501 // Truncate the result of the extended FP_TO_*INT operation to the desired
2503 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2506 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2508 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2509 EVT VT = Op.getValueType();
2510 EVT SHVT = TLI.getShiftAmountTy(VT);
2511 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2512 switch (VT.getSimpleVT().SimpleTy) {
2513 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2515 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2516 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2517 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2519 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2520 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2521 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2522 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2523 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2524 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2525 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2526 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2527 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2529 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2530 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2531 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2532 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2533 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2534 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2535 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2536 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2537 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2538 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2539 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2540 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2541 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2542 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2543 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2544 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2545 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2546 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2547 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2548 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2549 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2553 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2555 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2558 default: llvm_unreachable("Cannot expand this yet!");
2560 EVT VT = Op.getValueType();
2561 EVT ShVT = TLI.getShiftAmountTy(VT);
2562 unsigned Len = VT.getSizeInBits();
2564 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2565 "CTPOP not implemented for this type.");
2567 // This is the "best" algorithm from
2568 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2570 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), VT);
2571 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), VT);
2572 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), VT);
2573 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), VT);
2575 // v = v - ((v >> 1) & 0x55555555...)
2576 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2577 DAG.getNode(ISD::AND, dl, VT,
2578 DAG.getNode(ISD::SRL, dl, VT, Op,
2579 DAG.getConstant(1, ShVT)),
2581 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2582 Op = DAG.getNode(ISD::ADD, dl, VT,
2583 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2584 DAG.getNode(ISD::AND, dl, VT,
2585 DAG.getNode(ISD::SRL, dl, VT, Op,
2586 DAG.getConstant(2, ShVT)),
2588 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2589 Op = DAG.getNode(ISD::AND, dl, VT,
2590 DAG.getNode(ISD::ADD, dl, VT, Op,
2591 DAG.getNode(ISD::SRL, dl, VT, Op,
2592 DAG.getConstant(4, ShVT))),
2594 // v = (v * 0x01010101...) >> (Len - 8)
2595 Op = DAG.getNode(ISD::SRL, dl, VT,
2596 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2597 DAG.getConstant(Len - 8, ShVT));
2601 case ISD::CTLZ_ZERO_UNDEF:
2602 // This trivially expands to CTLZ.
2603 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2605 // for now, we do this:
2606 // x = x | (x >> 1);
2607 // x = x | (x >> 2);
2609 // x = x | (x >>16);
2610 // x = x | (x >>32); // for 64-bit input
2611 // return popcount(~x);
2613 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2614 EVT VT = Op.getValueType();
2615 EVT ShVT = TLI.getShiftAmountTy(VT);
2616 unsigned len = VT.getSizeInBits();
2617 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2618 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2619 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2620 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2622 Op = DAG.getNOT(dl, Op, VT);
2623 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2625 case ISD::CTTZ_ZERO_UNDEF:
2626 // This trivially expands to CTTZ.
2627 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2629 // for now, we use: { return popcount(~x & (x - 1)); }
2630 // unless the target has ctlz but not ctpop, in which case we use:
2631 // { return 32 - nlz(~x & (x-1)); }
2632 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2633 EVT VT = Op.getValueType();
2634 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2635 DAG.getNOT(dl, Op, VT),
2636 DAG.getNode(ISD::SUB, dl, VT, Op,
2637 DAG.getConstant(1, VT)));
2638 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2639 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2640 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2641 return DAG.getNode(ISD::SUB, dl, VT,
2642 DAG.getConstant(VT.getSizeInBits(), VT),
2643 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2644 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2649 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2650 unsigned Opc = Node->getOpcode();
2651 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2656 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2657 case ISD::ATOMIC_SWAP:
2658 switch (VT.SimpleTy) {
2659 default: llvm_unreachable("Unexpected value type for atomic!");
2660 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2661 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2662 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2663 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2664 case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;
2667 case ISD::ATOMIC_CMP_SWAP:
2668 switch (VT.SimpleTy) {
2669 default: llvm_unreachable("Unexpected value type for atomic!");
2670 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2671 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2672 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2673 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2674 case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;
2677 case ISD::ATOMIC_LOAD_ADD:
2678 switch (VT.SimpleTy) {
2679 default: llvm_unreachable("Unexpected value type for atomic!");
2680 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2681 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2682 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2683 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2684 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;
2687 case ISD::ATOMIC_LOAD_SUB:
2688 switch (VT.SimpleTy) {
2689 default: llvm_unreachable("Unexpected value type for atomic!");
2690 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2691 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2692 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2693 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2694 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;
2697 case ISD::ATOMIC_LOAD_AND:
2698 switch (VT.SimpleTy) {
2699 default: llvm_unreachable("Unexpected value type for atomic!");
2700 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2701 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2702 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2703 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2704 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;
2707 case ISD::ATOMIC_LOAD_OR:
2708 switch (VT.SimpleTy) {
2709 default: llvm_unreachable("Unexpected value type for atomic!");
2710 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2711 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2712 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2713 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2714 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;
2717 case ISD::ATOMIC_LOAD_XOR:
2718 switch (VT.SimpleTy) {
2719 default: llvm_unreachable("Unexpected value type for atomic!");
2720 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2721 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2722 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2723 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2724 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;
2727 case ISD::ATOMIC_LOAD_NAND:
2728 switch (VT.SimpleTy) {
2729 default: llvm_unreachable("Unexpected value type for atomic!");
2730 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2731 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2732 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2733 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2734 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;
2737 case ISD::ATOMIC_LOAD_MAX:
2738 switch (VT.SimpleTy) {
2739 default: llvm_unreachable("Unexpected value type for atomic!");
2740 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MAX_1; break;
2741 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MAX_2; break;
2742 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MAX_4; break;
2743 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MAX_8; break;
2744 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MAX_16;break;
2747 case ISD::ATOMIC_LOAD_UMAX:
2748 switch (VT.SimpleTy) {
2749 default: llvm_unreachable("Unexpected value type for atomic!");
2750 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMAX_1; break;
2751 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMAX_2; break;
2752 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMAX_4; break;
2753 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMAX_8; break;
2754 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMAX_16;break;
2757 case ISD::ATOMIC_LOAD_MIN:
2758 switch (VT.SimpleTy) {
2759 default: llvm_unreachable("Unexpected value type for atomic!");
2760 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MIN_1; break;
2761 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MIN_2; break;
2762 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MIN_4; break;
2763 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MIN_8; break;
2764 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MIN_16;break;
2767 case ISD::ATOMIC_LOAD_UMIN:
2768 switch (VT.SimpleTy) {
2769 default: llvm_unreachable("Unexpected value type for atomic!");
2770 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMIN_1; break;
2771 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMIN_2; break;
2772 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMIN_4; break;
2773 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMIN_8; break;
2774 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMIN_16;break;
2779 return ExpandChainLibCall(LC, Node, false);
2782 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2783 SmallVector<SDValue, 8> Results;
2785 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2786 switch (Node->getOpcode()) {
2789 case ISD::CTLZ_ZERO_UNDEF:
2791 case ISD::CTTZ_ZERO_UNDEF:
2792 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2793 Results.push_back(Tmp1);
2796 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2798 case ISD::FRAMEADDR:
2799 case ISD::RETURNADDR:
2800 case ISD::FRAME_TO_ARGS_OFFSET:
2801 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2803 case ISD::FLT_ROUNDS_:
2804 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2806 case ISD::EH_RETURN:
2810 case ISD::EH_SJLJ_LONGJMP:
2811 // If the target didn't expand these, there's nothing to do, so just
2812 // preserve the chain and be done.
2813 Results.push_back(Node->getOperand(0));
2815 case ISD::EH_SJLJ_SETJMP:
2816 // If the target didn't expand this, just return 'zero' and preserve the
2818 Results.push_back(DAG.getConstant(0, MVT::i32));
2819 Results.push_back(Node->getOperand(0));
2821 case ISD::ATOMIC_FENCE: {
2822 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2823 // FIXME: handle "fence singlethread" more efficiently.
2824 TargetLowering::ArgListTy Args;
2826 CallLoweringInfo CLI(Node->getOperand(0),
2827 Type::getVoidTy(*DAG.getContext()),
2828 false, false, false, false, 0, CallingConv::C,
2829 /*isTailCall=*/false,
2830 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2831 DAG.getExternalSymbol("__sync_synchronize",
2832 TLI.getPointerTy()),
2834 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2836 Results.push_back(CallResult.second);
2839 case ISD::ATOMIC_LOAD: {
2840 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2841 SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
2842 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
2843 cast<AtomicSDNode>(Node)->getMemoryVT(),
2844 Node->getOperand(0),
2845 Node->getOperand(1), Zero, Zero,
2846 cast<AtomicSDNode>(Node)->getMemOperand(),
2847 cast<AtomicSDNode>(Node)->getOrdering(),
2848 cast<AtomicSDNode>(Node)->getSynchScope());
2849 Results.push_back(Swap.getValue(0));
2850 Results.push_back(Swap.getValue(1));
2853 case ISD::ATOMIC_STORE: {
2854 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2855 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2856 cast<AtomicSDNode>(Node)->getMemoryVT(),
2857 Node->getOperand(0),
2858 Node->getOperand(1), Node->getOperand(2),
2859 cast<AtomicSDNode>(Node)->getMemOperand(),
2860 cast<AtomicSDNode>(Node)->getOrdering(),
2861 cast<AtomicSDNode>(Node)->getSynchScope());
2862 Results.push_back(Swap.getValue(1));
2865 // By default, atomic intrinsics are marked Legal and lowered. Targets
2866 // which don't support them directly, however, may want libcalls, in which
2867 // case they mark them Expand, and we get here.
2868 case ISD::ATOMIC_SWAP:
2869 case ISD::ATOMIC_LOAD_ADD:
2870 case ISD::ATOMIC_LOAD_SUB:
2871 case ISD::ATOMIC_LOAD_AND:
2872 case ISD::ATOMIC_LOAD_OR:
2873 case ISD::ATOMIC_LOAD_XOR:
2874 case ISD::ATOMIC_LOAD_NAND:
2875 case ISD::ATOMIC_LOAD_MIN:
2876 case ISD::ATOMIC_LOAD_MAX:
2877 case ISD::ATOMIC_LOAD_UMIN:
2878 case ISD::ATOMIC_LOAD_UMAX:
2879 case ISD::ATOMIC_CMP_SWAP: {
2880 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2881 Results.push_back(Tmp.first);
2882 Results.push_back(Tmp.second);
2885 case ISD::DYNAMIC_STACKALLOC:
2886 ExpandDYNAMIC_STACKALLOC(Node, Results);
2888 case ISD::MERGE_VALUES:
2889 for (unsigned i = 0; i < Node->getNumValues(); i++)
2890 Results.push_back(Node->getOperand(i));
2893 EVT VT = Node->getValueType(0);
2895 Results.push_back(DAG.getConstant(0, VT));
2897 assert(VT.isFloatingPoint() && "Unknown value type!");
2898 Results.push_back(DAG.getConstantFP(0, VT));
2903 // If this operation is not supported, lower it to 'abort()' call
2904 TargetLowering::ArgListTy Args;
2906 CallLoweringInfo CLI(Node->getOperand(0),
2907 Type::getVoidTy(*DAG.getContext()),
2908 false, false, false, false, 0, CallingConv::C,
2909 /*isTailCall=*/false,
2910 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2911 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2913 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2915 Results.push_back(CallResult.second);
2920 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2921 Node->getValueType(0), dl);
2922 Results.push_back(Tmp1);
2924 case ISD::FP_EXTEND:
2925 Tmp1 = EmitStackConvert(Node->getOperand(0),
2926 Node->getOperand(0).getValueType(),
2927 Node->getValueType(0), dl);
2928 Results.push_back(Tmp1);
2930 case ISD::SIGN_EXTEND_INREG: {
2931 // NOTE: we could fall back on load/store here too for targets without
2932 // SAR. However, it is doubtful that any exist.
2933 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2934 EVT VT = Node->getValueType(0);
2935 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
2938 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2939 ExtraVT.getScalarType().getSizeInBits();
2940 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2941 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2942 Node->getOperand(0), ShiftCst);
2943 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2944 Results.push_back(Tmp1);
2947 case ISD::FP_ROUND_INREG: {
2948 // The only way we can lower this is to turn it into a TRUNCSTORE,
2949 // EXTLOAD pair, targeting a temporary location (a stack slot).
2951 // NOTE: there is a choice here between constantly creating new stack
2952 // slots and always reusing the same one. We currently always create
2953 // new ones, as reuse may inhibit scheduling.
2954 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2955 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2956 Node->getValueType(0), dl);
2957 Results.push_back(Tmp1);
2960 case ISD::SINT_TO_FP:
2961 case ISD::UINT_TO_FP:
2962 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2963 Node->getOperand(0), Node->getValueType(0), dl);
2964 Results.push_back(Tmp1);
2966 case ISD::FP_TO_UINT: {
2967 SDValue True, False;
2968 EVT VT = Node->getOperand(0).getValueType();
2969 EVT NVT = Node->getValueType(0);
2970 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
2971 APInt::getNullValue(VT.getSizeInBits()));
2972 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2973 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2974 Tmp1 = DAG.getConstantFP(apf, VT);
2975 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
2976 Node->getOperand(0),
2978 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2979 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2980 DAG.getNode(ISD::FSUB, dl, VT,
2981 Node->getOperand(0), Tmp1));
2982 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2983 DAG.getConstant(x, NVT));
2984 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
2985 Results.push_back(Tmp1);
2989 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2990 EVT VT = Node->getValueType(0);
2991 Tmp1 = Node->getOperand(0);
2992 Tmp2 = Node->getOperand(1);
2993 unsigned Align = Node->getConstantOperandVal(3);
2995 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
2996 MachinePointerInfo(V),
2997 false, false, false, 0);
2998 SDValue VAList = VAListLoad;
3000 if (Align > TLI.getMinStackArgumentAlignment()) {
3001 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
3003 VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3004 DAG.getConstant(Align - 1,
3005 VAList.getValueType()));
3007 VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList,
3008 DAG.getConstant(-(int64_t)Align,
3009 VAList.getValueType()));
3012 // Increment the pointer, VAList, to the next vaarg
3013 Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3014 DAG.getConstant(TLI.getDataLayout()->
3015 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
3016 VAList.getValueType()));
3017 // Store the incremented VAList to the legalized pointer
3018 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
3019 MachinePointerInfo(V), false, false, 0);
3020 // Load the actual argument out of the pointer VAList
3021 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
3022 false, false, false, 0));
3023 Results.push_back(Results[0].getValue(1));
3027 // This defaults to loading a pointer from the input and storing it to the
3028 // output, returning the chain.
3029 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3030 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3031 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
3032 Node->getOperand(2), MachinePointerInfo(VS),
3033 false, false, false, 0);
3034 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3035 MachinePointerInfo(VD), false, false, 0);
3036 Results.push_back(Tmp1);
3039 case ISD::EXTRACT_VECTOR_ELT:
3040 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3041 // This must be an access of the only element. Return it.
3042 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3043 Node->getOperand(0));
3045 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3046 Results.push_back(Tmp1);
3048 case ISD::EXTRACT_SUBVECTOR:
3049 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3051 case ISD::INSERT_SUBVECTOR:
3052 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3054 case ISD::CONCAT_VECTORS: {
3055 Results.push_back(ExpandVectorBuildThroughStack(Node));
3058 case ISD::SCALAR_TO_VECTOR:
3059 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3061 case ISD::INSERT_VECTOR_ELT:
3062 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3063 Node->getOperand(1),
3064 Node->getOperand(2), dl));
3066 case ISD::VECTOR_SHUFFLE: {
3067 SmallVector<int, 32> NewMask;
3068 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3070 EVT VT = Node->getValueType(0);
3071 EVT EltVT = VT.getVectorElementType();
3072 SDValue Op0 = Node->getOperand(0);
3073 SDValue Op1 = Node->getOperand(1);
3074 if (!TLI.isTypeLegal(EltVT)) {
3076 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3078 // BUILD_VECTOR operands are allowed to be wider than the element type.
3079 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept it
3080 if (NewEltVT.bitsLT(EltVT)) {
3082 // Convert shuffle node.
3083 // If original node was v4i64 and the new EltVT is i32,
3084 // cast operands to v8i32 and re-build the mask.
3086 // Calculate new VT, the size of the new VT should be equal to original.
3087 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3088 VT.getSizeInBits()/NewEltVT.getSizeInBits());
3089 assert(NewVT.bitsEq(VT));
3091 // cast operands to new VT
3092 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3093 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3095 // Convert the shuffle mask
3096 unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements();
3098 // EltVT gets smaller
3101 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3103 for (unsigned fi = 0; fi < factor; ++fi)
3104 NewMask.push_back(Mask[i]);
3107 for (unsigned fi = 0; fi < factor; ++fi)
3108 NewMask.push_back(Mask[i]*factor+fi);
3116 unsigned NumElems = VT.getVectorNumElements();
3117 SmallVector<SDValue, 16> Ops;
3118 for (unsigned i = 0; i != NumElems; ++i) {
3120 Ops.push_back(DAG.getUNDEF(EltVT));
3123 unsigned Idx = Mask[i];
3125 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3127 DAG.getConstant(Idx, TLI.getVectorIdxTy())));
3129 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3131 DAG.getConstant(Idx - NumElems,
3132 TLI.getVectorIdxTy())));
3135 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
3136 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3137 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3138 Results.push_back(Tmp1);
3141 case ISD::EXTRACT_ELEMENT: {
3142 EVT OpTy = Node->getOperand(0).getValueType();
3143 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3145 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3146 DAG.getConstant(OpTy.getSizeInBits()/2,
3147 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3148 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3151 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3152 Node->getOperand(0));
3154 Results.push_back(Tmp1);
3157 case ISD::STACKSAVE:
3158 // Expand to CopyFromReg if the target set
3159 // StackPointerRegisterToSaveRestore.
3160 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3161 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3162 Node->getValueType(0)));
3163 Results.push_back(Results[0].getValue(1));
3165 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3166 Results.push_back(Node->getOperand(0));
3169 case ISD::STACKRESTORE:
3170 // Expand to CopyToReg if the target set
3171 // StackPointerRegisterToSaveRestore.
3172 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3173 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3174 Node->getOperand(1)));
3176 Results.push_back(Node->getOperand(0));
3179 case ISD::FCOPYSIGN:
3180 Results.push_back(ExpandFCOPYSIGN(Node));
3183 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3184 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3185 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3186 Node->getOperand(0));
3187 Results.push_back(Tmp1);
3190 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3191 EVT VT = Node->getValueType(0);
3192 Tmp1 = Node->getOperand(0);
3193 Tmp2 = DAG.getConstantFP(0.0, VT);
3194 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
3195 Tmp1, Tmp2, ISD::SETUGT);
3196 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3197 Tmp1 = DAG.getSelect(dl, VT, Tmp2, Tmp1, Tmp3);
3198 Results.push_back(Tmp1);
3202 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3203 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3204 RTLIB::SQRT_PPCF128));
3208 EVT VT = Node->getValueType(0);
3209 bool isSIN = Node->getOpcode() == ISD::FSIN;
3210 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3211 // fcos which share the same operand and both are used.
3212 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3213 canCombineSinCosLibcall(Node, TLI, TM))
3214 && useSinCos(Node)) {
3215 SDVTList VTs = DAG.getVTList(VT, VT);
3216 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3218 Tmp1 = Tmp1.getValue(1);
3219 Results.push_back(Tmp1);
3221 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3222 RTLIB::SIN_F80, RTLIB::SIN_F128,
3223 RTLIB::SIN_PPCF128));
3225 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3226 RTLIB::COS_F80, RTLIB::COS_F128,
3227 RTLIB::COS_PPCF128));
3232 // Expand into sincos libcall.
3233 ExpandSinCosLibCall(Node, Results);
3236 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3237 RTLIB::LOG_F80, RTLIB::LOG_F128,
3238 RTLIB::LOG_PPCF128));
3241 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3242 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3243 RTLIB::LOG2_PPCF128));
3246 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3247 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3248 RTLIB::LOG10_PPCF128));
3251 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3252 RTLIB::EXP_F80, RTLIB::EXP_F128,
3253 RTLIB::EXP_PPCF128));
3256 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3257 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3258 RTLIB::EXP2_PPCF128));
3261 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3262 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3263 RTLIB::TRUNC_PPCF128));
3266 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3267 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3268 RTLIB::FLOOR_PPCF128));
3271 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3272 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3273 RTLIB::CEIL_PPCF128));
3276 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3277 RTLIB::RINT_F80, RTLIB::RINT_F128,
3278 RTLIB::RINT_PPCF128));
3280 case ISD::FNEARBYINT:
3281 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3282 RTLIB::NEARBYINT_F64,
3283 RTLIB::NEARBYINT_F80,
3284 RTLIB::NEARBYINT_F128,
3285 RTLIB::NEARBYINT_PPCF128));
3288 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3292 RTLIB::ROUND_PPCF128));
3295 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3296 RTLIB::POWI_F80, RTLIB::POWI_F128,
3297 RTLIB::POWI_PPCF128));
3300 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3301 RTLIB::POW_F80, RTLIB::POW_F128,
3302 RTLIB::POW_PPCF128));
3305 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3306 RTLIB::DIV_F80, RTLIB::DIV_F128,
3307 RTLIB::DIV_PPCF128));
3310 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3311 RTLIB::REM_F80, RTLIB::REM_F128,
3312 RTLIB::REM_PPCF128));
3315 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3316 RTLIB::FMA_F80, RTLIB::FMA_F128,
3317 RTLIB::FMA_PPCF128));
3319 case ISD::FP16_TO_FP32:
3320 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3322 case ISD::FP32_TO_FP16:
3323 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3325 case ISD::ConstantFP: {
3326 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3327 // Check to see if this FP immediate is already legal.
3328 // If this is a legal constant, turn it into a TargetConstantFP node.
3329 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3330 Results.push_back(ExpandConstantFP(CFP, true));
3334 EVT VT = Node->getValueType(0);
3335 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3336 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3337 "Don't know how to expand this FP subtraction!");
3338 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3339 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3340 Results.push_back(Tmp1);
3344 EVT VT = Node->getValueType(0);
3345 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3346 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3347 "Don't know how to expand this subtraction!");
3348 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3349 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3350 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3351 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3356 EVT VT = Node->getValueType(0);
3357 bool isSigned = Node->getOpcode() == ISD::SREM;
3358 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3359 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3360 Tmp2 = Node->getOperand(0);
3361 Tmp3 = Node->getOperand(1);
3362 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3363 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3364 // If div is legal, it's better to do the normal expansion
3365 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
3366 useDivRem(Node, isSigned, false))) {
3367 SDVTList VTs = DAG.getVTList(VT, VT);
3368 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3369 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3371 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3372 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3373 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3374 } else if (isSigned)
3375 Tmp1 = ExpandIntLibCall(Node, true,
3377 RTLIB::SREM_I16, RTLIB::SREM_I32,
3378 RTLIB::SREM_I64, RTLIB::SREM_I128);
3380 Tmp1 = ExpandIntLibCall(Node, false,
3382 RTLIB::UREM_I16, RTLIB::UREM_I32,
3383 RTLIB::UREM_I64, RTLIB::UREM_I128);
3384 Results.push_back(Tmp1);
3389 bool isSigned = Node->getOpcode() == ISD::SDIV;
3390 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3391 EVT VT = Node->getValueType(0);
3392 SDVTList VTs = DAG.getVTList(VT, VT);
3393 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3394 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3395 useDivRem(Node, isSigned, true)))
3396 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3397 Node->getOperand(1));
3399 Tmp1 = ExpandIntLibCall(Node, true,
3401 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3402 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3404 Tmp1 = ExpandIntLibCall(Node, false,
3406 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3407 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3408 Results.push_back(Tmp1);
3413 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3415 EVT VT = Node->getValueType(0);
3416 SDVTList VTs = DAG.getVTList(VT, VT);
3417 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3418 "If this wasn't legal, it shouldn't have been created!");
3419 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3420 Node->getOperand(1));
3421 Results.push_back(Tmp1.getValue(1));
3426 // Expand into divrem libcall
3427 ExpandDivRemLibCall(Node, Results);
3430 EVT VT = Node->getValueType(0);
3431 SDVTList VTs = DAG.getVTList(VT, VT);
3432 // See if multiply or divide can be lowered using two-result operations.
3433 // We just need the low half of the multiply; try both the signed
3434 // and unsigned forms. If the target supports both SMUL_LOHI and
3435 // UMUL_LOHI, form a preference by checking which forms of plain
3436 // MULH it supports.
3437 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3438 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3439 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3440 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3441 unsigned OpToUse = 0;
3442 if (HasSMUL_LOHI && !HasMULHS) {
3443 OpToUse = ISD::SMUL_LOHI;
3444 } else if (HasUMUL_LOHI && !HasMULHU) {
3445 OpToUse = ISD::UMUL_LOHI;
3446 } else if (HasSMUL_LOHI) {
3447 OpToUse = ISD::SMUL_LOHI;
3448 } else if (HasUMUL_LOHI) {
3449 OpToUse = ISD::UMUL_LOHI;
3452 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3453 Node->getOperand(1)));
3456 Tmp1 = ExpandIntLibCall(Node, false,
3458 RTLIB::MUL_I16, RTLIB::MUL_I32,
3459 RTLIB::MUL_I64, RTLIB::MUL_I128);
3460 Results.push_back(Tmp1);
3465 SDValue LHS = Node->getOperand(0);
3466 SDValue RHS = Node->getOperand(1);
3467 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3468 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3470 Results.push_back(Sum);
3471 EVT OType = Node->getValueType(1);
3473 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3475 // LHSSign -> LHS >= 0
3476 // RHSSign -> RHS >= 0
3477 // SumSign -> Sum >= 0
3480 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3482 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3484 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3485 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3486 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3487 Node->getOpcode() == ISD::SADDO ?
3488 ISD::SETEQ : ISD::SETNE);
3490 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3491 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3493 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3494 Results.push_back(Cmp);
3499 SDValue LHS = Node->getOperand(0);
3500 SDValue RHS = Node->getOperand(1);
3501 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3502 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3504 Results.push_back(Sum);
3505 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3506 Node->getOpcode () == ISD::UADDO ?
3507 ISD::SETULT : ISD::SETUGT));
3512 EVT VT = Node->getValueType(0);
3513 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3514 SDValue LHS = Node->getOperand(0);
3515 SDValue RHS = Node->getOperand(1);
3518 static const unsigned Ops[2][3] =
3519 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3520 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3521 bool isSigned = Node->getOpcode() == ISD::SMULO;
3522 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3523 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3524 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3525 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3526 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3528 TopHalf = BottomHalf.getValue(1);
3529 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3530 VT.getSizeInBits() * 2))) {
3531 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3532 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3533 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3534 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3535 DAG.getIntPtrConstant(0));
3536 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3537 DAG.getIntPtrConstant(1));
3539 // We can fall back to a libcall with an illegal type for the MUL if we
3540 // have a libcall big enough.
3541 // Also, we can fall back to a division in some cases, but that's a big
3542 // performance hit in the general case.
3543 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3544 if (WideVT == MVT::i16)
3545 LC = RTLIB::MUL_I16;
3546 else if (WideVT == MVT::i32)
3547 LC = RTLIB::MUL_I32;
3548 else if (WideVT == MVT::i64)
3549 LC = RTLIB::MUL_I64;
3550 else if (WideVT == MVT::i128)
3551 LC = RTLIB::MUL_I128;
3552 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3554 // The high part is obtained by SRA'ing all but one of the bits of low
3556 unsigned LoSize = VT.getSizeInBits();
3557 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3558 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3559 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3560 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3562 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3563 // pre-lowered to the correct types. This all depends upon WideVT not
3564 // being a legal type for the architecture and thus has to be split to
3566 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3567 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3568 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3569 DAG.getIntPtrConstant(0));
3570 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3571 DAG.getIntPtrConstant(1));
3572 // Ret is a node with an illegal type. Because such things are not
3573 // generally permitted during this phase of legalization, delete the
3574 // node. The above EXTRACT_ELEMENT nodes should have been folded.
3575 DAG.DeleteNode(Ret.getNode());
3579 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3580 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3581 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3582 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3585 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3586 DAG.getConstant(0, VT), ISD::SETNE);
3588 Results.push_back(BottomHalf);
3589 Results.push_back(TopHalf);
3592 case ISD::BUILD_PAIR: {
3593 EVT PairTy = Node->getValueType(0);
3594 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3595 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3596 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3597 DAG.getConstant(PairTy.getSizeInBits()/2,
3598 TLI.getShiftAmountTy(PairTy)));
3599 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3603 Tmp1 = Node->getOperand(0);
3604 Tmp2 = Node->getOperand(1);
3605 Tmp3 = Node->getOperand(2);
3606 if (Tmp1.getOpcode() == ISD::SETCC) {
3607 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3609 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3611 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3612 DAG.getConstant(0, Tmp1.getValueType()),
3613 Tmp2, Tmp3, ISD::SETNE);
3615 Results.push_back(Tmp1);
3618 SDValue Chain = Node->getOperand(0);
3619 SDValue Table = Node->getOperand(1);
3620 SDValue Index = Node->getOperand(2);
3622 EVT PTy = TLI.getPointerTy();
3624 const DataLayout &TD = *TLI.getDataLayout();
3625 unsigned EntrySize =
3626 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3628 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(),
3629 Index, DAG.getConstant(EntrySize, Index.getValueType()));
3630 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3633 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3634 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3635 MachinePointerInfo::getJumpTable(), MemVT,
3638 if (TM.getRelocationModel() == Reloc::PIC_) {
3639 // For PIC, the sequence is:
3640 // BRIND(load(Jumptable + index) + RelocBase)
3641 // RelocBase can be JumpTable, GOT or some sort of global base.
3642 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3643 TLI.getPICJumpTableRelocBase(Table, DAG));
3645 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3646 Results.push_back(Tmp1);
3650 // Expand brcond's setcc into its constituent parts and create a BR_CC
3652 Tmp1 = Node->getOperand(0);
3653 Tmp2 = Node->getOperand(1);
3654 if (Tmp2.getOpcode() == ISD::SETCC) {
3655 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3656 Tmp1, Tmp2.getOperand(2),
3657 Tmp2.getOperand(0), Tmp2.getOperand(1),
3658 Node->getOperand(2));
3660 // We test only the i1 bit. Skip the AND if UNDEF.
3661 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3662 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3663 DAG.getConstant(1, Tmp2.getValueType()));
3664 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3665 DAG.getCondCode(ISD::SETNE), Tmp3,
3666 DAG.getConstant(0, Tmp3.getValueType()),
3667 Node->getOperand(2));
3669 Results.push_back(Tmp1);
3672 Tmp1 = Node->getOperand(0);
3673 Tmp2 = Node->getOperand(1);
3674 Tmp3 = Node->getOperand(2);
3675 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3679 // If we exapanded the SETCC by swapping LHS and RHS, create a new SETCC
3682 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3685 Results.push_back(Tmp1);
3689 // Otherwise, SETCC for the given comparison type must be completely
3690 // illegal; expand it into a SELECT_CC.
3691 EVT VT = Node->getValueType(0);
3693 switch (TLI.getBooleanContents(VT.isVector())) {
3694 case TargetLowering::ZeroOrOneBooleanContent:
3695 case TargetLowering::UndefinedBooleanContent:
3698 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3702 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3703 DAG.getConstant(TrueValue, VT), DAG.getConstant(0, VT),
3705 Results.push_back(Tmp1);
3708 case ISD::SELECT_CC: {
3709 Tmp1 = Node->getOperand(0); // LHS
3710 Tmp2 = Node->getOperand(1); // RHS
3711 Tmp3 = Node->getOperand(2); // True
3712 Tmp4 = Node->getOperand(3); // False
3713 SDValue CC = Node->getOperand(4);
3715 bool Legalized = false;
3716 // Try to legalize by inverting the condition. This is for targets that
3717 // might support an ordered version of a condition, but not the unordered
3718 // version (or vice versa).
3719 ISD::CondCode InvCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3720 Tmp1.getValueType().isInteger());
3721 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
3722 // Use the new condition code and swap true and false
3724 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3726 // If The inverse is not legal, then try to swap the arguments using
3727 // the inverse condition code.
3728 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3729 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
3730 // The swapped inverse condition is legal, so swap true and false,
3733 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3738 Legalized = LegalizeSetCCCondCode(
3739 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, dl);
3741 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3742 // If we exapanded the SETCC by swapping LHS and RHS, create a new
3745 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3746 Tmp1, Tmp2, Tmp3, Tmp4, CC);
3748 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3749 CC = DAG.getCondCode(ISD::SETNE);
3750 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3754 Results.push_back(Tmp1);
3758 Tmp1 = Node->getOperand(0); // Chain
3759 Tmp2 = Node->getOperand(2); // LHS
3760 Tmp3 = Node->getOperand(3); // RHS
3761 Tmp4 = Node->getOperand(1); // CC
3763 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3764 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, dl);
3766 assert(Legalized && "Can't legalize BR_CC with legal condition!");
3768 // If we exapanded the SETCC by swapping LHS and RHS, create a new BR_CC
3770 if (Tmp4.getNode()) {
3771 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3772 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3774 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3775 Tmp4 = DAG.getCondCode(ISD::SETNE);
3776 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3777 Tmp3, Node->getOperand(4));
3779 Results.push_back(Tmp1);
3782 case ISD::BUILD_VECTOR:
3783 Results.push_back(ExpandBUILD_VECTOR(Node));
3788 // Scalarize vector SRA/SRL/SHL.
3789 EVT VT = Node->getValueType(0);
3790 assert(VT.isVector() && "Unable to legalize non-vector shift");
3791 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3792 unsigned NumElem = VT.getVectorNumElements();
3794 SmallVector<SDValue, 8> Scalars;
3795 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3796 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3798 Node->getOperand(0), DAG.getConstant(Idx,
3799 TLI.getVectorIdxTy()));
3800 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3802 Node->getOperand(1), DAG.getConstant(Idx,
3803 TLI.getVectorIdxTy()));
3804 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3805 VT.getScalarType(), Ex, Sh));
3808 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
3809 &Scalars[0], Scalars.size());
3810 ReplaceNode(SDValue(Node, 0), Result);
3813 case ISD::GLOBAL_OFFSET_TABLE:
3814 case ISD::GlobalAddress:
3815 case ISD::GlobalTLSAddress:
3816 case ISD::ExternalSymbol:
3817 case ISD::ConstantPool:
3818 case ISD::JumpTable:
3819 case ISD::INTRINSIC_W_CHAIN:
3820 case ISD::INTRINSIC_WO_CHAIN:
3821 case ISD::INTRINSIC_VOID:
3822 // FIXME: Custom lowering for these operations shouldn't return null!
3826 // Replace the original node with the legalized result.
3827 if (!Results.empty())
3828 ReplaceNode(Node, Results.data());
3831 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
3832 SmallVector<SDValue, 8> Results;
3833 MVT OVT = Node->getSimpleValueType(0);
3834 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3835 Node->getOpcode() == ISD::SINT_TO_FP ||
3836 Node->getOpcode() == ISD::SETCC) {
3837 OVT = Node->getOperand(0).getSimpleValueType();
3839 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3841 SDValue Tmp1, Tmp2, Tmp3;
3842 switch (Node->getOpcode()) {
3844 case ISD::CTTZ_ZERO_UNDEF:
3846 case ISD::CTLZ_ZERO_UNDEF:
3848 // Zero extend the argument.
3849 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3850 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
3851 // already the correct result.
3852 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3853 if (Node->getOpcode() == ISD::CTTZ) {
3854 // FIXME: This should set a bit in the zero extended value instead.
3855 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
3856 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3858 Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
3859 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3860 } else if (Node->getOpcode() == ISD::CTLZ ||
3861 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
3862 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3863 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3864 DAG.getConstant(NVT.getSizeInBits() -
3865 OVT.getSizeInBits(), NVT));
3867 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3870 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3871 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3872 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3873 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3874 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3875 Results.push_back(Tmp1);
3878 case ISD::FP_TO_UINT:
3879 case ISD::FP_TO_SINT:
3880 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3881 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3882 Results.push_back(Tmp1);
3884 case ISD::UINT_TO_FP:
3885 case ISD::SINT_TO_FP:
3886 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3887 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3888 Results.push_back(Tmp1);
3891 SDValue Chain = Node->getOperand(0); // Get the chain.
3892 SDValue Ptr = Node->getOperand(1); // Get the pointer.
3895 if (OVT.isVector()) {
3896 TruncOp = ISD::BITCAST;
3898 assert(OVT.isInteger()
3899 && "VAARG promotion is supported only for vectors or integer types");
3900 TruncOp = ISD::TRUNCATE;
3903 // Perform the larger operation, then convert back
3904 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
3905 Node->getConstantOperandVal(3));
3906 Chain = Tmp1.getValue(1);
3908 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
3910 // Modified the chain result - switch anything that used the old chain to
3912 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
3913 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
3920 unsigned ExtOp, TruncOp;
3921 if (OVT.isVector()) {
3922 ExtOp = ISD::BITCAST;
3923 TruncOp = ISD::BITCAST;
3925 assert(OVT.isInteger() && "Cannot promote logic operation");
3926 ExtOp = ISD::ANY_EXTEND;
3927 TruncOp = ISD::TRUNCATE;
3929 // Promote each of the values to the new type.
3930 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3931 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3932 // Perform the larger operation, then convert back
3933 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3934 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3938 unsigned ExtOp, TruncOp;
3939 if (Node->getValueType(0).isVector()) {
3940 ExtOp = ISD::BITCAST;
3941 TruncOp = ISD::BITCAST;
3942 } else if (Node->getValueType(0).isInteger()) {
3943 ExtOp = ISD::ANY_EXTEND;
3944 TruncOp = ISD::TRUNCATE;
3946 ExtOp = ISD::FP_EXTEND;
3947 TruncOp = ISD::FP_ROUND;
3949 Tmp1 = Node->getOperand(0);
3950 // Promote each of the values to the new type.
3951 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3952 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3953 // Perform the larger operation, then round down.
3954 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
3955 if (TruncOp != ISD::FP_ROUND)
3956 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3958 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3959 DAG.getIntPtrConstant(0));
3960 Results.push_back(Tmp1);
3963 case ISD::VECTOR_SHUFFLE: {
3964 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3966 // Cast the two input vectors.
3967 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3968 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3970 // Convert the shuffle mask to the right # elements.
3971 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3972 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3973 Results.push_back(Tmp1);
3977 unsigned ExtOp = ISD::FP_EXTEND;
3978 if (NVT.isInteger()) {
3979 ISD::CondCode CCCode =
3980 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3981 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3983 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3984 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3985 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3986 Tmp1, Tmp2, Node->getOperand(2)));
3992 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
3993 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
3994 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3995 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
3996 Tmp3, DAG.getIntPtrConstant(0)));
4003 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4004 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4005 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4006 Tmp2, DAG.getIntPtrConstant(0)));
4011 // Replace the original node with the legalized result.
4012 if (!Results.empty())
4013 ReplaceNode(Node, Results.data());
4016 // SelectionDAG::Legalize - This is the entry point for the file.
4018 void SelectionDAG::Legalize() {
4019 /// run - This is the main entry point to this class.
4021 SelectionDAGLegalize(*this).LegalizeDAG();