1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Target/TargetLowering.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Compiler.h"
25 #include "llvm/ADT/SmallVector.h"
32 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
33 cl::desc("Pop up a window to show dags before legalize"));
35 static const bool ViewLegalizeDAGs = 0;
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class VISIBILITY_HIDDEN SelectionDAGLegalize {
55 // Libcall insertion helpers.
57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
58 /// legalized. We use this to ensure that calls are properly serialized
59 /// against each other, including inserted libcalls.
60 SDOperand LastCALLSEQ_END;
62 /// IsLegalizingCall - This member is used *only* for purposes of providing
63 /// helpful assertions that a libcall isn't created while another call is
64 /// being legalized (which could lead to non-serialized call sequences).
65 bool IsLegalizingCall;
68 Legal, // The target natively supports this operation.
69 Promote, // This operation should be executed in a larger type.
70 Expand // Try to expand this to other ops, otherwise use a libcall.
73 /// ValueTypeActions - This is a bitvector that contains two bits for each
74 /// value type, where the two bits correspond to the LegalizeAction enum.
75 /// This can be queried with "getTypeAction(VT)".
76 TargetLowering::ValueTypeActionImpl ValueTypeActions;
78 /// LegalizedNodes - For nodes that are of legal width, and that have more
79 /// than one use, this map indicates what regularized operand to use. This
80 /// allows us to avoid legalizing the same thing more than once.
81 std::map<SDOperand, SDOperand> LegalizedNodes;
83 /// PromotedNodes - For nodes that are below legal width, and that have more
84 /// than one use, this map indicates what promoted value to use. This allows
85 /// us to avoid promoting the same thing more than once.
86 std::map<SDOperand, SDOperand> PromotedNodes;
88 /// ExpandedNodes - For nodes that need to be expanded this map indicates
89 /// which which operands are the expanded version of the input. This allows
90 /// us to avoid expanding the same node more than once.
91 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
93 /// SplitNodes - For vector nodes that need to be split, this map indicates
94 /// which which operands are the split version of the input. This allows us
95 /// to avoid splitting the same node more than once.
96 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
98 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
99 /// concrete packed types, this contains the mapping of ones we have already
100 /// processed to the result.
101 std::map<SDOperand, SDOperand> PackedNodes;
103 void AddLegalizedOperand(SDOperand From, SDOperand To) {
104 LegalizedNodes.insert(std::make_pair(From, To));
105 // If someone requests legalization of the new node, return itself.
107 LegalizedNodes.insert(std::make_pair(To, To));
109 void AddPromotedOperand(SDOperand From, SDOperand To) {
110 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
111 assert(isNew && "Got into the map somehow?");
112 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
118 SelectionDAGLegalize(SelectionDAG &DAG);
120 /// getTypeAction - Return how we should legalize values of this type, either
121 /// it is already legal or we need to expand it into multiple registers of
122 /// smaller integer type, or we need to promote it to a larger type.
123 LegalizeAction getTypeAction(MVT::ValueType VT) const {
124 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
127 /// isTypeLegal - Return true if this type is legal on this target.
129 bool isTypeLegal(MVT::ValueType VT) const {
130 return getTypeAction(VT) == Legal;
136 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
137 /// appropriate for its type.
138 void HandleOp(SDOperand Op);
140 /// LegalizeOp - We know that the specified value has a legal type.
141 /// Recursively ensure that the operands have legal types, then return the
143 SDOperand LegalizeOp(SDOperand O);
145 /// PromoteOp - Given an operation that produces a value in an invalid type,
146 /// promote it to compute the value into a larger type. The produced value
147 /// will have the correct bits for the low portion of the register, but no
148 /// guarantee is made about the top bits: it may be zero, sign-extended, or
150 SDOperand PromoteOp(SDOperand O);
152 /// ExpandOp - Expand the specified SDOperand into its two component pieces
153 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
154 /// the LegalizeNodes map is filled in for any results that are not expanded,
155 /// the ExpandedNodes map is filled in for any results that are expanded, and
156 /// the Lo/Hi values are returned. This applies to integer types and Vector
158 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
160 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
161 /// two smaller values of MVT::Vector type.
162 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
164 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
165 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
166 /// this is called, we know that PackedVT is the right type for the result and
167 /// we know that this type is legal for the target.
168 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
170 /// isShuffleLegal - Return true if a vector shuffle is legal with the
171 /// specified mask and type. Targets can specify exactly which masks they
172 /// support and the code generator is tasked with not creating illegal masks.
174 /// Note that this will also return true for shuffles that are promoted to a
177 /// If this is a legal shuffle, this method returns the (possibly promoted)
178 /// build_vector Mask. If it's not a legal shuffle, it returns null.
179 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
181 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
182 std::set<SDNode*> &NodesLeadingTo);
184 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
186 SDOperand CreateStackTemporary(MVT::ValueType VT);
188 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
190 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
193 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
194 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
195 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
196 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
198 MVT::ValueType DestVT);
199 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
201 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
204 SDOperand ExpandBSWAP(SDOperand Op);
205 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
206 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
207 SDOperand &Lo, SDOperand &Hi);
208 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
209 SDOperand &Lo, SDOperand &Hi);
211 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
212 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
214 SDOperand getIntPtrConstant(uint64_t Val) {
215 return DAG.getConstant(Val, TLI.getPointerTy());
220 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
221 /// specified mask and type. Targets can specify exactly which masks they
222 /// support and the code generator is tasked with not creating illegal masks.
224 /// Note that this will also return true for shuffles that are promoted to a
226 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
227 SDOperand Mask) const {
228 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
230 case TargetLowering::Legal:
231 case TargetLowering::Custom:
233 case TargetLowering::Promote: {
234 // If this is promoted to a different type, convert the shuffle mask and
235 // ask if it is legal in the promoted type!
236 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
238 // If we changed # elements, change the shuffle mask.
239 unsigned NumEltsGrowth =
240 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
241 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
242 if (NumEltsGrowth > 1) {
243 // Renumber the elements.
244 SmallVector<SDOperand, 8> Ops;
245 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
246 SDOperand InOp = Mask.getOperand(i);
247 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
248 if (InOp.getOpcode() == ISD::UNDEF)
249 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
251 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
252 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
256 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
262 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
265 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
266 /// specified vector opcode.
267 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
269 default: assert(0 && "Don't know how to scalarize this opcode!");
270 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
271 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
272 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
273 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
274 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
275 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
276 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
277 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
281 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
282 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
283 ValueTypeActions(TLI.getValueTypeActions()) {
284 assert(MVT::LAST_VALUETYPE <= 32 &&
285 "Too many value types for ValueTypeActions to hold!");
288 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
289 /// not been visited yet and if all of its operands have already been visited.
290 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
291 std::map<SDNode*, unsigned> &Visited) {
292 if (++Visited[N] != N->getNumOperands())
293 return; // Haven't visited all operands yet
297 if (N->hasOneUse()) { // Tail recurse in common case.
298 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
302 // Now that we have N in, add anything that uses it if all of their operands
304 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
305 ComputeTopDownOrdering(*UI, Order, Visited);
309 void SelectionDAGLegalize::LegalizeDAG() {
310 LastCALLSEQ_END = DAG.getEntryNode();
311 IsLegalizingCall = false;
313 // The legalize process is inherently a bottom-up recursive process (users
314 // legalize their uses before themselves). Given infinite stack space, we
315 // could just start legalizing on the root and traverse the whole graph. In
316 // practice however, this causes us to run out of stack space on large basic
317 // blocks. To avoid this problem, compute an ordering of the nodes where each
318 // node is only legalized after all of its operands are legalized.
319 std::map<SDNode*, unsigned> Visited;
320 std::vector<SDNode*> Order;
322 // Compute ordering from all of the leaves in the graphs, those (like the
323 // entry node) that have no operands.
324 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
325 E = DAG.allnodes_end(); I != E; ++I) {
326 if (I->getNumOperands() == 0) {
328 ComputeTopDownOrdering(I, Order, Visited);
332 assert(Order.size() == Visited.size() &&
334 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
335 "Error: DAG is cyclic!");
338 for (unsigned i = 0, e = Order.size(); i != e; ++i)
339 HandleOp(SDOperand(Order[i], 0));
341 // Finally, it's possible the root changed. Get the new root.
342 SDOperand OldRoot = DAG.getRoot();
343 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
344 DAG.setRoot(LegalizedNodes[OldRoot]);
346 ExpandedNodes.clear();
347 LegalizedNodes.clear();
348 PromotedNodes.clear();
352 // Remove dead nodes now.
353 DAG.RemoveDeadNodes();
357 /// FindCallEndFromCallStart - Given a chained node that is part of a call
358 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
359 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
360 if (Node->getOpcode() == ISD::CALLSEQ_END)
362 if (Node->use_empty())
363 return 0; // No CallSeqEnd
365 // The chain is usually at the end.
366 SDOperand TheChain(Node, Node->getNumValues()-1);
367 if (TheChain.getValueType() != MVT::Other) {
368 // Sometimes it's at the beginning.
369 TheChain = SDOperand(Node, 0);
370 if (TheChain.getValueType() != MVT::Other) {
371 // Otherwise, hunt for it.
372 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
373 if (Node->getValueType(i) == MVT::Other) {
374 TheChain = SDOperand(Node, i);
378 // Otherwise, we walked into a node without a chain.
379 if (TheChain.getValueType() != MVT::Other)
384 for (SDNode::use_iterator UI = Node->use_begin(),
385 E = Node->use_end(); UI != E; ++UI) {
387 // Make sure to only follow users of our token chain.
389 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
390 if (User->getOperand(i) == TheChain)
391 if (SDNode *Result = FindCallEndFromCallStart(User))
397 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
398 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
399 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
400 assert(Node && "Didn't find callseq_start for a call??");
401 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
403 assert(Node->getOperand(0).getValueType() == MVT::Other &&
404 "Node doesn't have a token chain argument!");
405 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
408 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
409 /// see if any uses can reach Dest. If no dest operands can get to dest,
410 /// legalize them, legalize ourself, and return false, otherwise, return true.
412 /// Keep track of the nodes we fine that actually do lead to Dest in
413 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
415 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
416 std::set<SDNode*> &NodesLeadingTo) {
417 if (N == Dest) return true; // N certainly leads to Dest :)
419 // If we've already processed this node and it does lead to Dest, there is no
420 // need to reprocess it.
421 if (NodesLeadingTo.count(N)) return true;
423 // If the first result of this node has been already legalized, then it cannot
425 switch (getTypeAction(N->getValueType(0))) {
427 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
430 if (PromotedNodes.count(SDOperand(N, 0))) return false;
433 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
437 // Okay, this node has not already been legalized. Check and legalize all
438 // operands. If none lead to Dest, then we can legalize this node.
439 bool OperandsLeadToDest = false;
440 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
441 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
442 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
444 if (OperandsLeadToDest) {
445 NodesLeadingTo.insert(N);
449 // Okay, this node looks safe, legalize it and return false.
450 HandleOp(SDOperand(N, 0));
454 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
455 /// appropriate for its type.
456 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
457 switch (getTypeAction(Op.getValueType())) {
458 default: assert(0 && "Bad type action!");
459 case Legal: LegalizeOp(Op); break;
460 case Promote: PromoteOp(Op); break;
462 if (Op.getValueType() != MVT::Vector) {
467 unsigned NumOps = N->getNumOperands();
468 unsigned NumElements =
469 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
470 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
471 MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
472 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
473 // In the common case, this is a legal vector type, convert it to the
474 // packed operation and type now.
475 PackVectorOp(Op, PackedVT);
476 } else if (NumElements == 1) {
477 // Otherwise, if this is a single element vector, convert it to a
479 PackVectorOp(Op, EVT);
481 // Otherwise, this is a multiple element vector that isn't supported.
482 // Split it in half and legalize both parts.
484 SplitVectorOp(Op, X, Y);
492 /// LegalizeOp - We know that the specified value has a legal type.
493 /// Recursively ensure that the operands have legal types, then return the
495 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
496 assert(isTypeLegal(Op.getValueType()) &&
497 "Caller should expand or promote operands that are not legal!");
498 SDNode *Node = Op.Val;
500 // If this operation defines any values that cannot be represented in a
501 // register on this target, make sure to expand or promote them.
502 if (Node->getNumValues() > 1) {
503 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
504 if (getTypeAction(Node->getValueType(i)) != Legal) {
505 HandleOp(Op.getValue(i));
506 assert(LegalizedNodes.count(Op) &&
507 "Handling didn't add legal operands!");
508 return LegalizedNodes[Op];
512 // Note that LegalizeOp may be reentered even from single-use nodes, which
513 // means that we always must cache transformed nodes.
514 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
515 if (I != LegalizedNodes.end()) return I->second;
517 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
518 SDOperand Result = Op;
519 bool isCustom = false;
521 switch (Node->getOpcode()) {
522 case ISD::FrameIndex:
523 case ISD::EntryToken:
525 case ISD::BasicBlock:
526 case ISD::TargetFrameIndex:
527 case ISD::TargetJumpTable:
528 case ISD::TargetConstant:
529 case ISD::TargetConstantFP:
530 case ISD::TargetConstantPool:
531 case ISD::TargetGlobalAddress:
532 case ISD::TargetExternalSymbol:
537 // Primitives must all be legal.
538 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
539 "This must be legal!");
542 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
543 // If this is a target node, legalize it by legalizing the operands then
544 // passing it through.
545 SmallVector<SDOperand, 8> Ops;
546 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
547 Ops.push_back(LegalizeOp(Node->getOperand(i)));
549 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
551 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
552 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
553 return Result.getValue(Op.ResNo);
555 // Otherwise this is an unhandled builtin node. splat.
557 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
559 assert(0 && "Do not know how to legalize this operator!");
561 case ISD::GlobalAddress:
562 case ISD::ExternalSymbol:
563 case ISD::ConstantPool:
564 case ISD::JumpTable: // Nothing to do.
565 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
566 default: assert(0 && "This action is not supported yet!");
567 case TargetLowering::Custom:
568 Tmp1 = TLI.LowerOperation(Op, DAG);
569 if (Tmp1.Val) Result = Tmp1;
570 // FALLTHROUGH if the target doesn't want to lower this op after all.
571 case TargetLowering::Legal:
575 case ISD::AssertSext:
576 case ISD::AssertZext:
577 Tmp1 = LegalizeOp(Node->getOperand(0));
578 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
580 case ISD::MERGE_VALUES:
581 // Legalize eliminates MERGE_VALUES nodes.
582 Result = Node->getOperand(Op.ResNo);
584 case ISD::CopyFromReg:
585 Tmp1 = LegalizeOp(Node->getOperand(0));
586 Result = Op.getValue(0);
587 if (Node->getNumValues() == 2) {
588 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
590 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
591 if (Node->getNumOperands() == 3) {
592 Tmp2 = LegalizeOp(Node->getOperand(2));
593 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
595 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
597 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
599 // Since CopyFromReg produces two values, make sure to remember that we
600 // legalized both of them.
601 AddLegalizedOperand(Op.getValue(0), Result);
602 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
603 return Result.getValue(Op.ResNo);
605 MVT::ValueType VT = Op.getValueType();
606 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
607 default: assert(0 && "This action is not supported yet!");
608 case TargetLowering::Expand:
609 if (MVT::isInteger(VT))
610 Result = DAG.getConstant(0, VT);
611 else if (MVT::isFloatingPoint(VT))
612 Result = DAG.getConstantFP(0, VT);
614 assert(0 && "Unknown value type!");
616 case TargetLowering::Legal:
622 case ISD::INTRINSIC_W_CHAIN:
623 case ISD::INTRINSIC_WO_CHAIN:
624 case ISD::INTRINSIC_VOID: {
625 SmallVector<SDOperand, 8> Ops;
626 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
627 Ops.push_back(LegalizeOp(Node->getOperand(i)));
628 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
630 // Allow the target to custom lower its intrinsics if it wants to.
631 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
632 TargetLowering::Custom) {
633 Tmp3 = TLI.LowerOperation(Result, DAG);
634 if (Tmp3.Val) Result = Tmp3;
637 if (Result.Val->getNumValues() == 1) break;
639 // Must have return value and chain result.
640 assert(Result.Val->getNumValues() == 2 &&
641 "Cannot return more than two values!");
643 // Since loads produce two values, make sure to remember that we
644 // legalized both of them.
645 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
646 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
647 return Result.getValue(Op.ResNo);
651 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
652 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
654 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
655 case TargetLowering::Promote:
656 default: assert(0 && "This action is not supported yet!");
657 case TargetLowering::Expand: {
658 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
659 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
660 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
662 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
663 const std::string &FName =
664 cast<StringSDNode>(Node->getOperand(3))->getValue();
665 const std::string &DirName =
666 cast<StringSDNode>(Node->getOperand(4))->getValue();
667 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
669 SmallVector<SDOperand, 8> Ops;
670 Ops.push_back(Tmp1); // chain
671 SDOperand LineOp = Node->getOperand(1);
672 SDOperand ColOp = Node->getOperand(2);
675 Ops.push_back(LineOp); // line #
676 Ops.push_back(ColOp); // col #
677 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
678 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
680 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
681 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
682 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
683 Ops.push_back(DAG.getConstant(ID, MVT::i32));
684 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,&Ops[0],Ops.size());
687 Result = Tmp1; // chain
691 case TargetLowering::Legal:
692 if (Tmp1 != Node->getOperand(0) ||
693 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
694 SmallVector<SDOperand, 8> Ops;
696 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
697 Ops.push_back(Node->getOperand(1)); // line # must be legal.
698 Ops.push_back(Node->getOperand(2)); // col # must be legal.
700 // Otherwise promote them.
701 Ops.push_back(PromoteOp(Node->getOperand(1)));
702 Ops.push_back(PromoteOp(Node->getOperand(2)));
704 Ops.push_back(Node->getOperand(3)); // filename must be legal.
705 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
706 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
713 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
714 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
715 default: assert(0 && "This action is not supported yet!");
716 case TargetLowering::Legal:
717 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
718 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
719 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
720 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
721 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
726 case ISD::DEBUG_LABEL:
727 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
728 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
729 default: assert(0 && "This action is not supported yet!");
730 case TargetLowering::Legal:
731 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
732 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
733 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
739 // We know we don't need to expand constants here, constants only have one
740 // value and we check that it is fine above.
742 // FIXME: Maybe we should handle things like targets that don't support full
743 // 32-bit immediates?
745 case ISD::ConstantFP: {
746 // Spill FP immediates to the constant pool if the target cannot directly
747 // codegen them. Targets often have some immediate values that can be
748 // efficiently generated into an FP register without a load. We explicitly
749 // leave these constants as ConstantFP nodes for the target to deal with.
750 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
752 // Check to see if this FP immediate is already legal.
753 bool isLegal = false;
754 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
755 E = TLI.legal_fpimm_end(); I != E; ++I)
756 if (CFP->isExactlyValue(*I)) {
761 // If this is a legal constant, turn it into a TargetConstantFP node.
763 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
767 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
768 default: assert(0 && "This action is not supported yet!");
769 case TargetLowering::Custom:
770 Tmp3 = TLI.LowerOperation(Result, DAG);
776 case TargetLowering::Expand:
777 // Otherwise we need to spill the constant to memory.
780 // If a FP immediate is precise when represented as a float and if the
781 // target can do an extending load from float to double, we put it into
782 // the constant pool as a float, even if it's is statically typed as a
784 MVT::ValueType VT = CFP->getValueType(0);
785 bool isDouble = VT == MVT::f64;
786 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
787 Type::FloatTy, CFP->getValue());
788 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
789 // Only do this if the target has a native EXTLOAD instruction from
791 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
792 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
797 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
799 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
800 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
802 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
803 DAG.getSrcValue(NULL));
808 case ISD::TokenFactor:
809 if (Node->getNumOperands() == 2) {
810 Tmp1 = LegalizeOp(Node->getOperand(0));
811 Tmp2 = LegalizeOp(Node->getOperand(1));
812 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
813 } else if (Node->getNumOperands() == 3) {
814 Tmp1 = LegalizeOp(Node->getOperand(0));
815 Tmp2 = LegalizeOp(Node->getOperand(1));
816 Tmp3 = LegalizeOp(Node->getOperand(2));
817 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
819 SmallVector<SDOperand, 8> Ops;
820 // Legalize the operands.
821 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
822 Ops.push_back(LegalizeOp(Node->getOperand(i)));
823 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
827 case ISD::FORMAL_ARGUMENTS:
829 // The only option for this is to custom lower it.
830 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
831 assert(Tmp3.Val && "Target didn't custom lower this node!");
832 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
833 "Lowering call/formal_arguments produced unexpected # results!");
835 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
836 // remember that we legalized all of them, so it doesn't get relegalized.
837 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
838 Tmp1 = LegalizeOp(Tmp3.getValue(i));
841 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
845 case ISD::BUILD_VECTOR:
846 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
847 default: assert(0 && "This action is not supported yet!");
848 case TargetLowering::Custom:
849 Tmp3 = TLI.LowerOperation(Result, DAG);
855 case TargetLowering::Expand:
856 Result = ExpandBUILD_VECTOR(Result.Val);
860 case ISD::INSERT_VECTOR_ELT:
861 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
862 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
863 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
864 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
866 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
867 Node->getValueType(0))) {
868 default: assert(0 && "This action is not supported yet!");
869 case TargetLowering::Legal:
871 case TargetLowering::Custom:
872 Tmp3 = TLI.LowerOperation(Result, DAG);
878 case TargetLowering::Expand: {
879 // If the insert index is a constant, codegen this as a scalar_to_vector,
880 // then a shuffle that inserts it into the right position in the vector.
881 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
882 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
883 Tmp1.getValueType(), Tmp2);
885 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
886 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
887 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT);
889 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
890 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
892 SmallVector<SDOperand, 8> ShufOps;
893 for (unsigned i = 0; i != NumElts; ++i) {
894 if (i != InsertPos->getValue())
895 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
897 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
899 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
900 &ShufOps[0], ShufOps.size());
902 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
903 Tmp1, ScVec, ShufMask);
904 Result = LegalizeOp(Result);
908 // If the target doesn't support this, we have to spill the input vector
909 // to a temporary stack slot, update the element, then reload it. This is
910 // badness. We could also load the value into a vector register (either
911 // with a "move to register" or "extload into register" instruction, then
912 // permute it into place, if the idx is a constant and if the idx is
913 // supported by the target.
914 MVT::ValueType VT = Tmp1.getValueType();
915 MVT::ValueType EltVT = Tmp2.getValueType();
916 MVT::ValueType IdxVT = Tmp3.getValueType();
917 MVT::ValueType PtrVT = TLI.getPointerTy();
918 SDOperand StackPtr = CreateStackTemporary(VT);
920 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
921 Tmp1, StackPtr, DAG.getSrcValue(NULL));
923 // Truncate or zero extend offset to target pointer type.
924 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
925 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
926 // Add the offset to the index.
927 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
928 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
929 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
930 // Store the scalar value.
931 Ch = DAG.getNode(ISD::STORE, MVT::Other, Ch,
932 Tmp2, StackPtr2, DAG.getSrcValue(NULL));
933 // Load the updated vector.
934 Result = DAG.getLoad(VT, Ch, StackPtr, DAG.getSrcValue(NULL));
939 case ISD::SCALAR_TO_VECTOR:
940 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
941 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
945 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
946 Result = DAG.UpdateNodeOperands(Result, Tmp1);
947 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
948 Node->getValueType(0))) {
949 default: assert(0 && "This action is not supported yet!");
950 case TargetLowering::Legal:
952 case TargetLowering::Custom:
953 Tmp3 = TLI.LowerOperation(Result, DAG);
959 case TargetLowering::Expand:
960 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
964 case ISD::VECTOR_SHUFFLE:
965 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
966 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
967 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
969 // Allow targets to custom lower the SHUFFLEs they support.
970 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
971 default: assert(0 && "Unknown operation action!");
972 case TargetLowering::Legal:
973 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
974 "vector shuffle should not be created if not legal!");
976 case TargetLowering::Custom:
977 Tmp3 = TLI.LowerOperation(Result, DAG);
983 case TargetLowering::Expand: {
984 MVT::ValueType VT = Node->getValueType(0);
985 MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
986 MVT::ValueType PtrVT = TLI.getPointerTy();
987 SDOperand Mask = Node->getOperand(2);
988 unsigned NumElems = Mask.getNumOperands();
989 SmallVector<SDOperand,8> Ops;
990 for (unsigned i = 0; i != NumElems; ++i) {
991 SDOperand Arg = Mask.getOperand(i);
992 if (Arg.getOpcode() == ISD::UNDEF) {
993 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
995 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
996 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
998 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
999 DAG.getConstant(Idx, PtrVT)));
1001 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1002 DAG.getConstant(Idx - NumElems, PtrVT)));
1005 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1008 case TargetLowering::Promote: {
1009 // Change base type to a different vector type.
1010 MVT::ValueType OVT = Node->getValueType(0);
1011 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1013 // Cast the two input vectors.
1014 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1015 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1017 // Convert the shuffle mask to the right # elements.
1018 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1019 assert(Tmp3.Val && "Shuffle not legal?");
1020 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1021 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1027 case ISD::EXTRACT_VECTOR_ELT:
1028 Tmp1 = LegalizeOp(Node->getOperand(0));
1029 Tmp2 = LegalizeOp(Node->getOperand(1));
1030 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1032 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
1033 Tmp1.getValueType())) {
1034 default: assert(0 && "This action is not supported yet!");
1035 case TargetLowering::Legal:
1037 case TargetLowering::Custom:
1038 Tmp3 = TLI.LowerOperation(Result, DAG);
1044 case TargetLowering::Expand:
1045 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1050 case ISD::VEXTRACT_VECTOR_ELT:
1051 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
1054 case ISD::CALLSEQ_START: {
1055 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1057 // Recursively Legalize all of the inputs of the call end that do not lead
1058 // to this call start. This ensures that any libcalls that need be inserted
1059 // are inserted *before* the CALLSEQ_START.
1060 {std::set<SDNode*> NodesLeadingTo;
1061 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1062 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1066 // Now that we legalized all of the inputs (which may have inserted
1067 // libcalls) create the new CALLSEQ_START node.
1068 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1070 // Merge in the last call, to ensure that this call start after the last
1072 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1073 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1074 Tmp1 = LegalizeOp(Tmp1);
1077 // Do not try to legalize the target-specific arguments (#1+).
1078 if (Tmp1 != Node->getOperand(0)) {
1079 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1081 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1084 // Remember that the CALLSEQ_START is legalized.
1085 AddLegalizedOperand(Op.getValue(0), Result);
1086 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1087 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1089 // Now that the callseq_start and all of the non-call nodes above this call
1090 // sequence have been legalized, legalize the call itself. During this
1091 // process, no libcalls can/will be inserted, guaranteeing that no calls
1093 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1094 SDOperand InCallSEQ = LastCALLSEQ_END;
1095 // Note that we are selecting this call!
1096 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1097 IsLegalizingCall = true;
1099 // Legalize the call, starting from the CALLSEQ_END.
1100 LegalizeOp(LastCALLSEQ_END);
1101 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1104 case ISD::CALLSEQ_END:
1105 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1106 // will cause this node to be legalized as well as handling libcalls right.
1107 if (LastCALLSEQ_END.Val != Node) {
1108 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1109 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1110 assert(I != LegalizedNodes.end() &&
1111 "Legalizing the call start should have legalized this node!");
1115 // Otherwise, the call start has been legalized and everything is going
1116 // according to plan. Just legalize ourselves normally here.
1117 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1118 // Do not try to legalize the target-specific arguments (#1+), except for
1119 // an optional flag input.
1120 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1121 if (Tmp1 != Node->getOperand(0)) {
1122 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1124 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1127 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1128 if (Tmp1 != Node->getOperand(0) ||
1129 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1130 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1133 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1136 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1137 // This finishes up call legalization.
1138 IsLegalizingCall = false;
1140 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1141 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1142 if (Node->getNumValues() == 2)
1143 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1144 return Result.getValue(Op.ResNo);
1145 case ISD::DYNAMIC_STACKALLOC: {
1146 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1147 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1148 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1149 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1151 Tmp1 = Result.getValue(0);
1152 Tmp2 = Result.getValue(1);
1153 switch (TLI.getOperationAction(Node->getOpcode(),
1154 Node->getValueType(0))) {
1155 default: assert(0 && "This action is not supported yet!");
1156 case TargetLowering::Expand: {
1157 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1158 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1159 " not tell us which reg is the stack pointer!");
1160 SDOperand Chain = Tmp1.getOperand(0);
1161 SDOperand Size = Tmp2.getOperand(1);
1162 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1163 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1164 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1165 Tmp1 = LegalizeOp(Tmp1);
1166 Tmp2 = LegalizeOp(Tmp2);
1169 case TargetLowering::Custom:
1170 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1172 Tmp1 = LegalizeOp(Tmp3);
1173 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1176 case TargetLowering::Legal:
1179 // Since this op produce two values, make sure to remember that we
1180 // legalized both of them.
1181 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1182 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1183 return Op.ResNo ? Tmp2 : Tmp1;
1185 case ISD::INLINEASM: {
1186 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1187 bool Changed = false;
1188 // Legalize all of the operands of the inline asm, in case they are nodes
1189 // that need to be expanded or something. Note we skip the asm string and
1190 // all of the TargetConstant flags.
1191 SDOperand Op = LegalizeOp(Ops[0]);
1192 Changed = Op != Ops[0];
1195 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1196 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1197 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1198 for (++i; NumVals; ++i, --NumVals) {
1199 SDOperand Op = LegalizeOp(Ops[i]);
1208 Op = LegalizeOp(Ops.back());
1209 Changed |= Op != Ops.back();
1214 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1216 // INLINE asm returns a chain and flag, make sure to add both to the map.
1217 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1218 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1219 return Result.getValue(Op.ResNo);
1222 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1223 // Ensure that libcalls are emitted before a branch.
1224 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1225 Tmp1 = LegalizeOp(Tmp1);
1226 LastCALLSEQ_END = DAG.getEntryNode();
1228 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1231 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1232 // Ensure that libcalls are emitted before a branch.
1233 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1234 Tmp1 = LegalizeOp(Tmp1);
1235 LastCALLSEQ_END = DAG.getEntryNode();
1237 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1238 default: assert(0 && "Indirect target must be legal type (pointer)!");
1240 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1243 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1246 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1247 // Ensure that libcalls are emitted before a return.
1248 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1249 Tmp1 = LegalizeOp(Tmp1);
1250 LastCALLSEQ_END = DAG.getEntryNode();
1252 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1253 case Expand: assert(0 && "It's impossible to expand bools");
1255 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1258 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1262 // Basic block destination (Op#2) is always legal.
1263 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1265 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1266 default: assert(0 && "This action is not supported yet!");
1267 case TargetLowering::Legal: break;
1268 case TargetLowering::Custom:
1269 Tmp1 = TLI.LowerOperation(Result, DAG);
1270 if (Tmp1.Val) Result = Tmp1;
1272 case TargetLowering::Expand:
1273 // Expand brcond's setcc into its constituent parts and create a BR_CC
1275 if (Tmp2.getOpcode() == ISD::SETCC) {
1276 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1277 Tmp2.getOperand(0), Tmp2.getOperand(1),
1278 Node->getOperand(2));
1280 // Make sure the condition is either zero or one. It may have been
1281 // promoted from something else.
1282 unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType());
1283 if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1))
1284 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1286 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1287 DAG.getCondCode(ISD::SETNE), Tmp2,
1288 DAG.getConstant(0, Tmp2.getValueType()),
1289 Node->getOperand(2));
1295 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1296 // Ensure that libcalls are emitted before a branch.
1297 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1298 Tmp1 = LegalizeOp(Tmp1);
1299 LastCALLSEQ_END = DAG.getEntryNode();
1301 Tmp2 = Node->getOperand(2); // LHS
1302 Tmp3 = Node->getOperand(3); // RHS
1303 Tmp4 = Node->getOperand(1); // CC
1305 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1307 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1308 // the LHS is a legal SETCC itself. In this case, we need to compare
1309 // the result against zero to select between true and false values.
1310 if (Tmp3.Val == 0) {
1311 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1312 Tmp4 = DAG.getCondCode(ISD::SETNE);
1315 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1316 Node->getOperand(4));
1318 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1319 default: assert(0 && "Unexpected action for BR_CC!");
1320 case TargetLowering::Legal: break;
1321 case TargetLowering::Custom:
1322 Tmp4 = TLI.LowerOperation(Result, DAG);
1323 if (Tmp4.Val) Result = Tmp4;
1328 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1329 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1331 MVT::ValueType VT = Node->getValueType(0);
1332 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1333 Tmp3 = Result.getValue(0);
1334 Tmp4 = Result.getValue(1);
1336 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1337 default: assert(0 && "This action is not supported yet!");
1338 case TargetLowering::Legal: break;
1339 case TargetLowering::Custom:
1340 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1342 Tmp3 = LegalizeOp(Tmp1);
1343 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1346 case TargetLowering::Promote: {
1347 // Only promote a load of vector type to another.
1348 assert(MVT::isVector(VT) && "Cannot promote this load!");
1349 // Change base type to a different vector type.
1350 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1352 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, Node->getOperand(2));
1353 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1354 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1358 // Since loads produce two values, make sure to remember that we
1359 // legalized both of them.
1360 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1361 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1362 return Op.ResNo ? Tmp4 : Tmp3;
1366 case ISD::ZEXTLOAD: {
1367 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1368 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1370 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
1371 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
1372 default: assert(0 && "This action is not supported yet!");
1373 case TargetLowering::Promote:
1374 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
1375 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1376 DAG.getValueType(MVT::i8));
1377 Tmp1 = Result.getValue(0);
1378 Tmp2 = Result.getValue(1);
1380 case TargetLowering::Custom:
1383 case TargetLowering::Legal:
1384 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1385 Node->getOperand(3));
1386 Tmp1 = Result.getValue(0);
1387 Tmp2 = Result.getValue(1);
1390 Tmp3 = TLI.LowerOperation(Tmp3, DAG);
1392 Tmp1 = LegalizeOp(Tmp3);
1393 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1397 case TargetLowering::Expand:
1398 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1399 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1400 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
1401 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1402 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1403 Tmp2 = LegalizeOp(Load.getValue(1));
1406 assert(Node->getOpcode() != ISD::EXTLOAD &&
1407 "EXTLOAD should always be supported!");
1408 // Turn the unsupported load into an EXTLOAD followed by an explicit
1409 // zero/sign extend inreg.
1410 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1411 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1413 if (Node->getOpcode() == ISD::SEXTLOAD)
1414 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1415 Result, DAG.getValueType(SrcVT));
1417 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1418 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1419 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1422 // Since loads produce two values, make sure to remember that we legalized
1424 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1425 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1426 return Op.ResNo ? Tmp2 : Tmp1;
1428 case ISD::EXTRACT_ELEMENT: {
1429 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1430 switch (getTypeAction(OpTy)) {
1431 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1433 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1435 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1436 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1437 TLI.getShiftAmountTy()));
1438 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1441 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1442 Node->getOperand(0));
1446 // Get both the low and high parts.
1447 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1448 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1449 Result = Tmp2; // 1 -> Hi
1451 Result = Tmp1; // 0 -> Lo
1457 case ISD::CopyToReg:
1458 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1460 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1461 "Register type must be legal!");
1462 // Legalize the incoming value (must be a legal type).
1463 Tmp2 = LegalizeOp(Node->getOperand(2));
1464 if (Node->getNumValues() == 1) {
1465 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1467 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1468 if (Node->getNumOperands() == 4) {
1469 Tmp3 = LegalizeOp(Node->getOperand(3));
1470 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1473 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1476 // Since this produces two values, make sure to remember that we legalized
1478 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1479 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1485 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1487 // Ensure that libcalls are emitted before a return.
1488 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1489 Tmp1 = LegalizeOp(Tmp1);
1490 LastCALLSEQ_END = DAG.getEntryNode();
1492 switch (Node->getNumOperands()) {
1494 Tmp2 = Node->getOperand(1);
1495 Tmp3 = Node->getOperand(2); // Signness
1496 switch (getTypeAction(Tmp2.getValueType())) {
1498 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1501 if (Tmp2.getValueType() != MVT::Vector) {
1503 ExpandOp(Tmp2, Lo, Hi);
1504 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1505 Result = LegalizeOp(Result);
1507 SDNode *InVal = Tmp2.Val;
1509 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1510 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1512 // Figure out if there is a Packed type corresponding to this Vector
1513 // type. If so, convert to the packed type.
1514 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1515 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1516 // Turn this into a return of the packed type.
1517 Tmp2 = PackVectorOp(Tmp2, TVT);
1518 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1519 } else if (NumElems == 1) {
1520 // Turn this into a return of the scalar type.
1521 Tmp2 = PackVectorOp(Tmp2, EVT);
1522 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1524 // FIXME: Returns of gcc generic vectors smaller than a legal type
1525 // should be returned in integer registers!
1527 // The scalarized value type may not be legal, e.g. it might require
1528 // promotion or expansion. Relegalize the return.
1529 Result = LegalizeOp(Result);
1531 // FIXME: Returns of gcc generic vectors larger than a legal vector
1532 // type should be returned by reference!
1534 SplitVectorOp(Tmp2, Lo, Hi);
1535 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1536 Result = LegalizeOp(Result);
1541 Tmp2 = PromoteOp(Node->getOperand(1));
1542 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1543 Result = LegalizeOp(Result);
1548 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1550 default: { // ret <values>
1551 SmallVector<SDOperand, 8> NewValues;
1552 NewValues.push_back(Tmp1);
1553 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1554 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1556 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1557 NewValues.push_back(Node->getOperand(i+1));
1561 assert(Node->getOperand(i).getValueType() != MVT::Vector &&
1562 "FIXME: TODO: implement returning non-legal vector types!");
1563 ExpandOp(Node->getOperand(i), Lo, Hi);
1564 NewValues.push_back(Lo);
1565 NewValues.push_back(Node->getOperand(i+1));
1566 NewValues.push_back(Hi);
1567 NewValues.push_back(Node->getOperand(i+1));
1571 assert(0 && "Can't promote multiple return value yet!");
1574 if (NewValues.size() == Node->getNumOperands())
1575 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1577 Result = DAG.getNode(ISD::RET, MVT::Other,
1578 &NewValues[0], NewValues.size());
1583 if (Result.getOpcode() == ISD::RET) {
1584 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1585 default: assert(0 && "This action is not supported yet!");
1586 case TargetLowering::Legal: break;
1587 case TargetLowering::Custom:
1588 Tmp1 = TLI.LowerOperation(Result, DAG);
1589 if (Tmp1.Val) Result = Tmp1;
1595 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1596 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1598 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1599 // FIXME: We shouldn't do this for TargetConstantFP's.
1600 // FIXME: move this to the DAG Combiner!
1601 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1602 if (CFP->getValueType(0) == MVT::f32) {
1603 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1605 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1606 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1608 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1609 Node->getOperand(3));
1613 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1615 Tmp3 = LegalizeOp(Node->getOperand(1));
1616 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1617 Node->getOperand(3));
1619 MVT::ValueType VT = Tmp3.getValueType();
1620 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1621 default: assert(0 && "This action is not supported yet!");
1622 case TargetLowering::Legal: break;
1623 case TargetLowering::Custom:
1624 Tmp1 = TLI.LowerOperation(Result, DAG);
1625 if (Tmp1.Val) Result = Tmp1;
1627 case TargetLowering::Promote:
1628 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1629 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1630 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1631 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1632 Node->getOperand(3));
1638 // Truncate the value and store the result.
1639 Tmp3 = PromoteOp(Node->getOperand(1));
1640 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1641 Node->getOperand(3),
1642 DAG.getValueType(Node->getOperand(1).getValueType()));
1646 unsigned IncrementSize = 0;
1649 // If this is a vector type, then we have to calculate the increment as
1650 // the product of the element size in bytes, and the number of elements
1651 // in the high half of the vector.
1652 if (Node->getOperand(1).getValueType() == MVT::Vector) {
1653 SDNode *InVal = Node->getOperand(1).Val;
1655 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1656 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1658 // Figure out if there is a Packed type corresponding to this Vector
1659 // type. If so, convert to the packed type.
1660 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1661 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1662 // Turn this into a normal store of the packed type.
1663 Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1664 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1665 Node->getOperand(3));
1666 Result = LegalizeOp(Result);
1668 } else if (NumElems == 1) {
1669 // Turn this into a normal store of the scalar type.
1670 Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1671 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1672 Node->getOperand(3));
1673 // The scalarized value type may not be legal, e.g. it might require
1674 // promotion or expansion. Relegalize the scalar store.
1675 Result = LegalizeOp(Result);
1678 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1679 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1682 ExpandOp(Node->getOperand(1), Lo, Hi);
1683 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1685 if (!TLI.isLittleEndian())
1689 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1690 Node->getOperand(3));
1691 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1692 getIntPtrConstant(IncrementSize));
1693 assert(isTypeLegal(Tmp2.getValueType()) &&
1694 "Pointers must be legal!");
1695 // FIXME: This sets the srcvalue of both halves to be the same, which is
1697 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1698 Node->getOperand(3));
1699 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1705 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1706 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1708 case ISD::STACKSAVE:
1709 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1710 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1711 Tmp1 = Result.getValue(0);
1712 Tmp2 = Result.getValue(1);
1714 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1715 default: assert(0 && "This action is not supported yet!");
1716 case TargetLowering::Legal: break;
1717 case TargetLowering::Custom:
1718 Tmp3 = TLI.LowerOperation(Result, DAG);
1720 Tmp1 = LegalizeOp(Tmp3);
1721 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1724 case TargetLowering::Expand:
1725 // Expand to CopyFromReg if the target set
1726 // StackPointerRegisterToSaveRestore.
1727 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1728 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1729 Node->getValueType(0));
1730 Tmp2 = Tmp1.getValue(1);
1732 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1733 Tmp2 = Node->getOperand(0);
1738 // Since stacksave produce two values, make sure to remember that we
1739 // legalized both of them.
1740 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1741 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1742 return Op.ResNo ? Tmp2 : Tmp1;
1744 case ISD::STACKRESTORE:
1745 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1746 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1747 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1749 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1750 default: assert(0 && "This action is not supported yet!");
1751 case TargetLowering::Legal: break;
1752 case TargetLowering::Custom:
1753 Tmp1 = TLI.LowerOperation(Result, DAG);
1754 if (Tmp1.Val) Result = Tmp1;
1756 case TargetLowering::Expand:
1757 // Expand to CopyToReg if the target set
1758 // StackPointerRegisterToSaveRestore.
1759 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1760 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1768 case ISD::READCYCLECOUNTER:
1769 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1770 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1772 // Since rdcc produce two values, make sure to remember that we legalized
1774 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1775 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1778 case ISD::TRUNCSTORE: {
1779 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1780 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1782 assert(isTypeLegal(Node->getOperand(1).getValueType()) &&
1783 "Cannot handle illegal TRUNCSTORE yet!");
1784 Tmp2 = LegalizeOp(Node->getOperand(1));
1786 // The only promote case we handle is TRUNCSTORE:i1 X into
1787 // -> TRUNCSTORE:i8 (and X, 1)
1788 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1789 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1790 TargetLowering::Promote) {
1791 // Promote the bool to a mask then store.
1792 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1793 DAG.getConstant(1, Tmp2.getValueType()));
1794 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1795 Node->getOperand(3), DAG.getValueType(MVT::i8));
1797 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1798 Tmp3 != Node->getOperand(2)) {
1799 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
1800 Node->getOperand(3), Node->getOperand(4));
1803 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT();
1804 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) {
1805 default: assert(0 && "This action is not supported yet!");
1806 case TargetLowering::Legal: break;
1807 case TargetLowering::Custom:
1808 Tmp1 = TLI.LowerOperation(Result, DAG);
1809 if (Tmp1.Val) Result = Tmp1;
1815 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1816 case Expand: assert(0 && "It's impossible to expand bools");
1818 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1821 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1824 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1825 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1827 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1829 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1830 default: assert(0 && "This action is not supported yet!");
1831 case TargetLowering::Legal: break;
1832 case TargetLowering::Custom: {
1833 Tmp1 = TLI.LowerOperation(Result, DAG);
1834 if (Tmp1.Val) Result = Tmp1;
1837 case TargetLowering::Expand:
1838 if (Tmp1.getOpcode() == ISD::SETCC) {
1839 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1841 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1843 // Make sure the condition is either zero or one. It may have been
1844 // promoted from something else.
1845 unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType());
1846 if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1))
1847 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1848 Result = DAG.getSelectCC(Tmp1,
1849 DAG.getConstant(0, Tmp1.getValueType()),
1850 Tmp2, Tmp3, ISD::SETNE);
1853 case TargetLowering::Promote: {
1854 MVT::ValueType NVT =
1855 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1856 unsigned ExtOp, TruncOp;
1857 if (MVT::isVector(Tmp2.getValueType())) {
1858 ExtOp = ISD::BIT_CONVERT;
1859 TruncOp = ISD::BIT_CONVERT;
1860 } else if (MVT::isInteger(Tmp2.getValueType())) {
1861 ExtOp = ISD::ANY_EXTEND;
1862 TruncOp = ISD::TRUNCATE;
1864 ExtOp = ISD::FP_EXTEND;
1865 TruncOp = ISD::FP_ROUND;
1867 // Promote each of the values to the new type.
1868 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1869 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1870 // Perform the larger operation, then round down.
1871 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1872 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1877 case ISD::SELECT_CC: {
1878 Tmp1 = Node->getOperand(0); // LHS
1879 Tmp2 = Node->getOperand(1); // RHS
1880 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1881 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1882 SDOperand CC = Node->getOperand(4);
1884 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
1886 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1887 // the LHS is a legal SETCC itself. In this case, we need to compare
1888 // the result against zero to select between true and false values.
1889 if (Tmp2.Val == 0) {
1890 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1891 CC = DAG.getCondCode(ISD::SETNE);
1893 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
1895 // Everything is legal, see if we should expand this op or something.
1896 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
1897 default: assert(0 && "This action is not supported yet!");
1898 case TargetLowering::Legal: break;
1899 case TargetLowering::Custom:
1900 Tmp1 = TLI.LowerOperation(Result, DAG);
1901 if (Tmp1.Val) Result = Tmp1;
1907 Tmp1 = Node->getOperand(0);
1908 Tmp2 = Node->getOperand(1);
1909 Tmp3 = Node->getOperand(2);
1910 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
1912 // If we had to Expand the SetCC operands into a SELECT node, then it may
1913 // not always be possible to return a true LHS & RHS. In this case, just
1914 // return the value we legalized, returned in the LHS
1915 if (Tmp2.Val == 0) {
1920 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
1921 default: assert(0 && "Cannot handle this action for SETCC yet!");
1922 case TargetLowering::Custom:
1925 case TargetLowering::Legal:
1926 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1928 Tmp3 = TLI.LowerOperation(Result, DAG);
1929 if (Tmp3.Val) Result = Tmp3;
1932 case TargetLowering::Promote: {
1933 // First step, figure out the appropriate operation to use.
1934 // Allow SETCC to not be supported for all legal data types
1935 // Mostly this targets FP
1936 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1937 MVT::ValueType OldVT = NewInTy;
1939 // Scan for the appropriate larger type to use.
1941 NewInTy = (MVT::ValueType)(NewInTy+1);
1943 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1944 "Fell off of the edge of the integer world");
1945 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1946 "Fell off of the edge of the floating point world");
1948 // If the target supports SETCC of this type, use it.
1949 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
1952 if (MVT::isInteger(NewInTy))
1953 assert(0 && "Cannot promote Legal Integer SETCC yet");
1955 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1956 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
1958 Tmp1 = LegalizeOp(Tmp1);
1959 Tmp2 = LegalizeOp(Tmp2);
1960 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1961 Result = LegalizeOp(Result);
1964 case TargetLowering::Expand:
1965 // Expand a setcc node into a select_cc of the same condition, lhs, and
1966 // rhs that selects between const 1 (true) and const 0 (false).
1967 MVT::ValueType VT = Node->getValueType(0);
1968 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1969 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1970 Node->getOperand(2));
1976 case ISD::MEMMOVE: {
1977 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1978 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1980 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1981 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1982 case Expand: assert(0 && "Cannot expand a byte!");
1984 Tmp3 = LegalizeOp(Node->getOperand(2));
1987 Tmp3 = PromoteOp(Node->getOperand(2));
1991 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1995 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1997 // Length is too big, just take the lo-part of the length.
1999 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
2003 Tmp4 = LegalizeOp(Node->getOperand(3));
2006 Tmp4 = PromoteOp(Node->getOperand(3));
2011 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2012 case Expand: assert(0 && "Cannot expand this yet!");
2014 Tmp5 = LegalizeOp(Node->getOperand(4));
2017 Tmp5 = PromoteOp(Node->getOperand(4));
2021 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2022 default: assert(0 && "This action not implemented for this operation!");
2023 case TargetLowering::Custom:
2026 case TargetLowering::Legal:
2027 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2029 Tmp1 = TLI.LowerOperation(Result, DAG);
2030 if (Tmp1.Val) Result = Tmp1;
2033 case TargetLowering::Expand: {
2034 // Otherwise, the target does not support this operation. Lower the
2035 // operation to an explicit libcall as appropriate.
2036 MVT::ValueType IntPtr = TLI.getPointerTy();
2037 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2038 std::vector<std::pair<SDOperand, const Type*> > Args;
2040 const char *FnName = 0;
2041 if (Node->getOpcode() == ISD::MEMSET) {
2042 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2043 // Extend the (previously legalized) ubyte argument to be an int value
2045 if (Tmp3.getValueType() > MVT::i32)
2046 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2048 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2049 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
2050 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2053 } else if (Node->getOpcode() == ISD::MEMCPY ||
2054 Node->getOpcode() == ISD::MEMMOVE) {
2055 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2056 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
2057 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2058 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2060 assert(0 && "Unknown op!");
2063 std::pair<SDOperand,SDOperand> CallResult =
2064 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
2065 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2066 Result = CallResult.second;
2073 case ISD::SHL_PARTS:
2074 case ISD::SRA_PARTS:
2075 case ISD::SRL_PARTS: {
2076 SmallVector<SDOperand, 8> Ops;
2077 bool Changed = false;
2078 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2079 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2080 Changed |= Ops.back() != Node->getOperand(i);
2083 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2085 switch (TLI.getOperationAction(Node->getOpcode(),
2086 Node->getValueType(0))) {
2087 default: assert(0 && "This action is not supported yet!");
2088 case TargetLowering::Legal: break;
2089 case TargetLowering::Custom:
2090 Tmp1 = TLI.LowerOperation(Result, DAG);
2092 SDOperand Tmp2, RetVal(0, 0);
2093 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2094 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2095 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2099 assert(RetVal.Val && "Illegal result number");
2105 // Since these produce multiple values, make sure to remember that we
2106 // legalized all of them.
2107 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2108 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2109 return Result.getValue(Op.ResNo);
2130 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2131 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2132 case Expand: assert(0 && "Not possible");
2134 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2137 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2141 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2143 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2144 default: assert(0 && "BinOp legalize operation not supported");
2145 case TargetLowering::Legal: break;
2146 case TargetLowering::Custom:
2147 Tmp1 = TLI.LowerOperation(Result, DAG);
2148 if (Tmp1.Val) Result = Tmp1;
2150 case TargetLowering::Expand: {
2151 assert(MVT::isVector(Node->getValueType(0)) &&
2152 "Cannot expand this binary operator!");
2153 // Expand the operation into a bunch of nasty scalar code.
2154 SmallVector<SDOperand, 8> Ops;
2155 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
2156 MVT::ValueType PtrVT = TLI.getPointerTy();
2157 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2159 SDOperand Idx = DAG.getConstant(i, PtrVT);
2160 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2161 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2162 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2164 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2165 &Ops[0], Ops.size());
2168 case TargetLowering::Promote: {
2169 switch (Node->getOpcode()) {
2170 default: assert(0 && "Do not know how to promote this BinOp!");
2174 MVT::ValueType OVT = Node->getValueType(0);
2175 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2176 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2177 // Bit convert each of the values to the new type.
2178 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2179 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2180 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2181 // Bit convert the result back the original type.
2182 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2190 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2191 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2192 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2193 case Expand: assert(0 && "Not possible");
2195 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2198 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2202 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2204 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2205 default: assert(0 && "Operation not supported");
2206 case TargetLowering::Custom:
2207 Tmp1 = TLI.LowerOperation(Result, DAG);
2208 if (Tmp1.Val) Result = Tmp1;
2210 case TargetLowering::Legal: break;
2211 case TargetLowering::Expand:
2212 // If this target supports fabs/fneg natively, do this efficiently.
2213 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
2214 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
2215 // Get the sign bit of the RHS.
2216 MVT::ValueType IVT =
2217 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2218 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2219 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2220 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2221 // Get the absolute value of the result.
2222 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2223 // Select between the nabs and abs value based on the sign bit of
2225 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2226 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2229 Result = LegalizeOp(Result);
2233 // Otherwise, do bitwise ops!
2235 // copysign -> copysignf/copysign libcall.
2237 if (Node->getValueType(0) == MVT::f32) {
2238 FnName = "copysignf";
2239 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type.
2240 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2241 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2));
2243 FnName = "copysign";
2244 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type.
2245 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2246 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2));
2249 Result = ExpandLibCall(FnName, Node, Dummy);
2256 Tmp1 = LegalizeOp(Node->getOperand(0));
2257 Tmp2 = LegalizeOp(Node->getOperand(1));
2258 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2259 // Since this produces two values, make sure to remember that we legalized
2261 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2262 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2267 Tmp1 = LegalizeOp(Node->getOperand(0));
2268 Tmp2 = LegalizeOp(Node->getOperand(1));
2269 Tmp3 = LegalizeOp(Node->getOperand(2));
2270 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2271 // Since this produces two values, make sure to remember that we legalized
2273 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2274 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2277 case ISD::BUILD_PAIR: {
2278 MVT::ValueType PairTy = Node->getValueType(0);
2279 // TODO: handle the case where the Lo and Hi operands are not of legal type
2280 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2281 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2282 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2283 case TargetLowering::Promote:
2284 case TargetLowering::Custom:
2285 assert(0 && "Cannot promote/custom this yet!");
2286 case TargetLowering::Legal:
2287 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2288 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2290 case TargetLowering::Expand:
2291 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2292 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2293 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2294 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2295 TLI.getShiftAmountTy()));
2296 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2305 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2306 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2308 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2309 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2310 case TargetLowering::Custom:
2313 case TargetLowering::Legal:
2314 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2316 Tmp1 = TLI.LowerOperation(Result, DAG);
2317 if (Tmp1.Val) Result = Tmp1;
2320 case TargetLowering::Expand:
2321 if (MVT::isInteger(Node->getValueType(0))) {
2323 MVT::ValueType VT = Node->getValueType(0);
2324 unsigned Opc = Node->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
2325 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
2326 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2327 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2329 // Floating point mod -> fmod libcall.
2330 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
2332 Result = ExpandLibCall(FnName, Node, Dummy);
2338 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2339 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2341 MVT::ValueType VT = Node->getValueType(0);
2342 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2343 default: assert(0 && "This action is not supported yet!");
2344 case TargetLowering::Custom:
2347 case TargetLowering::Legal:
2348 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2349 Result = Result.getValue(0);
2350 Tmp1 = Result.getValue(1);
2353 Tmp2 = TLI.LowerOperation(Result, DAG);
2355 Result = LegalizeOp(Tmp2);
2356 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2360 case TargetLowering::Expand: {
2361 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2362 Node->getOperand(2));
2363 // Increment the pointer, VAList, to the next vaarg
2364 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2365 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2366 TLI.getPointerTy()));
2367 // Store the incremented VAList to the legalized pointer
2368 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2,
2369 Node->getOperand(2));
2370 // Load the actual argument out of the pointer VAList
2371 Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0));
2372 Tmp1 = LegalizeOp(Result.getValue(1));
2373 Result = LegalizeOp(Result);
2377 // Since VAARG produces two values, make sure to remember that we
2378 // legalized both of them.
2379 AddLegalizedOperand(SDOperand(Node, 0), Result);
2380 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2381 return Op.ResNo ? Tmp1 : Result;
2385 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2386 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2387 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2389 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2390 default: assert(0 && "This action is not supported yet!");
2391 case TargetLowering::Custom:
2394 case TargetLowering::Legal:
2395 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2396 Node->getOperand(3), Node->getOperand(4));
2398 Tmp1 = TLI.LowerOperation(Result, DAG);
2399 if (Tmp1.Val) Result = Tmp1;
2402 case TargetLowering::Expand:
2403 // This defaults to loading a pointer from the input and storing it to the
2404 // output, returning the chain.
2405 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, Node->getOperand(3));
2406 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp4.getValue(1), Tmp4, Tmp2,
2407 Node->getOperand(4));
2413 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2414 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2416 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2417 default: assert(0 && "This action is not supported yet!");
2418 case TargetLowering::Custom:
2421 case TargetLowering::Legal:
2422 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2424 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2425 if (Tmp1.Val) Result = Tmp1;
2428 case TargetLowering::Expand:
2429 Result = Tmp1; // Default to a no-op, return the chain
2435 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2436 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2438 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2440 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2441 default: assert(0 && "This action is not supported yet!");
2442 case TargetLowering::Legal: break;
2443 case TargetLowering::Custom:
2444 Tmp1 = TLI.LowerOperation(Result, DAG);
2445 if (Tmp1.Val) Result = Tmp1;
2452 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2453 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2455 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2456 "Cannot handle this yet!");
2457 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2461 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2462 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2463 case TargetLowering::Custom:
2464 assert(0 && "Cannot custom legalize this yet!");
2465 case TargetLowering::Legal:
2466 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2468 case TargetLowering::Promote: {
2469 MVT::ValueType OVT = Tmp1.getValueType();
2470 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2471 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2473 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2474 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2475 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2476 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2479 case TargetLowering::Expand:
2480 Result = ExpandBSWAP(Tmp1);
2488 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2489 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2490 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2491 case TargetLowering::Legal:
2492 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2494 case TargetLowering::Promote: {
2495 MVT::ValueType OVT = Tmp1.getValueType();
2496 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2498 // Zero extend the argument.
2499 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2500 // Perform the larger operation, then subtract if needed.
2501 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2502 switch (Node->getOpcode()) {
2507 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2508 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2509 DAG.getConstant(getSizeInBits(NVT), NVT),
2511 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2512 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2515 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2516 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2517 DAG.getConstant(getSizeInBits(NVT) -
2518 getSizeInBits(OVT), NVT));
2523 case TargetLowering::Expand:
2524 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2535 Tmp1 = LegalizeOp(Node->getOperand(0));
2536 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2537 case TargetLowering::Promote:
2538 case TargetLowering::Custom:
2541 case TargetLowering::Legal:
2542 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2544 Tmp1 = TLI.LowerOperation(Result, DAG);
2545 if (Tmp1.Val) Result = Tmp1;
2548 case TargetLowering::Expand:
2549 switch (Node->getOpcode()) {
2550 default: assert(0 && "Unreachable!");
2552 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2553 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2554 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2557 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2558 MVT::ValueType VT = Node->getValueType(0);
2559 Tmp2 = DAG.getConstantFP(0.0, VT);
2560 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2561 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2562 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2568 MVT::ValueType VT = Node->getValueType(0);
2569 const char *FnName = 0;
2570 switch(Node->getOpcode()) {
2571 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2572 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2573 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2574 default: assert(0 && "Unreachable!");
2577 Result = ExpandLibCall(FnName, Node, Dummy);
2585 // We always lower FPOWI into a libcall. No target support it yet.
2586 const char *FnName = Node->getValueType(0) == MVT::f32
2587 ? "__powisf2" : "__powidf2";
2589 Result = ExpandLibCall(FnName, Node, Dummy);
2592 case ISD::BIT_CONVERT:
2593 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2594 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2596 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2597 Node->getOperand(0).getValueType())) {
2598 default: assert(0 && "Unknown operation action!");
2599 case TargetLowering::Expand:
2600 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2602 case TargetLowering::Legal:
2603 Tmp1 = LegalizeOp(Node->getOperand(0));
2604 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2609 case ISD::VBIT_CONVERT: {
2610 assert(Op.getOperand(0).getValueType() == MVT::Vector &&
2611 "Can only have VBIT_CONVERT where input or output is MVT::Vector!");
2613 // The input has to be a vector type, we have to either scalarize it, pack
2614 // it, or convert it based on whether the input vector type is legal.
2615 SDNode *InVal = Node->getOperand(0).Val;
2617 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
2618 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
2620 // Figure out if there is a Packed type corresponding to this Vector
2621 // type. If so, convert to the packed type.
2622 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2623 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
2624 // Turn this into a bit convert of the packed input.
2625 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2626 PackVectorOp(Node->getOperand(0), TVT));
2628 } else if (NumElems == 1) {
2629 // Turn this into a bit convert of the scalar input.
2630 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2631 PackVectorOp(Node->getOperand(0), EVT));
2634 // FIXME: UNIMP! Store then reload
2635 assert(0 && "Cast from unsupported vector type not implemented yet!");
2639 // Conversion operators. The source and destination have different types.
2640 case ISD::SINT_TO_FP:
2641 case ISD::UINT_TO_FP: {
2642 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2643 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2645 switch (TLI.getOperationAction(Node->getOpcode(),
2646 Node->getOperand(0).getValueType())) {
2647 default: assert(0 && "Unknown operation action!");
2648 case TargetLowering::Custom:
2651 case TargetLowering::Legal:
2652 Tmp1 = LegalizeOp(Node->getOperand(0));
2653 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2655 Tmp1 = TLI.LowerOperation(Result, DAG);
2656 if (Tmp1.Val) Result = Tmp1;
2659 case TargetLowering::Expand:
2660 Result = ExpandLegalINT_TO_FP(isSigned,
2661 LegalizeOp(Node->getOperand(0)),
2662 Node->getValueType(0));
2664 case TargetLowering::Promote:
2665 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2666 Node->getValueType(0),
2672 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2673 Node->getValueType(0), Node->getOperand(0));
2676 Tmp1 = PromoteOp(Node->getOperand(0));
2678 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2679 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2681 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2682 Node->getOperand(0).getValueType());
2684 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2685 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2691 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2693 Tmp1 = LegalizeOp(Node->getOperand(0));
2694 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2697 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2699 // Since the result is legal, we should just be able to truncate the low
2700 // part of the source.
2701 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2704 Result = PromoteOp(Node->getOperand(0));
2705 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2710 case ISD::FP_TO_SINT:
2711 case ISD::FP_TO_UINT:
2712 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2714 Tmp1 = LegalizeOp(Node->getOperand(0));
2716 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2717 default: assert(0 && "Unknown operation action!");
2718 case TargetLowering::Custom:
2721 case TargetLowering::Legal:
2722 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2724 Tmp1 = TLI.LowerOperation(Result, DAG);
2725 if (Tmp1.Val) Result = Tmp1;
2728 case TargetLowering::Promote:
2729 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2730 Node->getOpcode() == ISD::FP_TO_SINT);
2732 case TargetLowering::Expand:
2733 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2734 SDOperand True, False;
2735 MVT::ValueType VT = Node->getOperand(0).getValueType();
2736 MVT::ValueType NVT = Node->getValueType(0);
2737 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2738 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2739 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2740 Node->getOperand(0), Tmp2, ISD::SETLT);
2741 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2742 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2743 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2745 False = DAG.getNode(ISD::XOR, NVT, False,
2746 DAG.getConstant(1ULL << ShiftAmt, NVT));
2747 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2750 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2756 assert(0 && "Shouldn't need to expand other operators here!");
2758 Tmp1 = PromoteOp(Node->getOperand(0));
2759 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
2760 Result = LegalizeOp(Result);
2765 case ISD::ANY_EXTEND:
2766 case ISD::ZERO_EXTEND:
2767 case ISD::SIGN_EXTEND:
2768 case ISD::FP_EXTEND:
2770 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2771 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
2773 Tmp1 = LegalizeOp(Node->getOperand(0));
2774 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2777 switch (Node->getOpcode()) {
2778 case ISD::ANY_EXTEND:
2779 Tmp1 = PromoteOp(Node->getOperand(0));
2780 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
2782 case ISD::ZERO_EXTEND:
2783 Result = PromoteOp(Node->getOperand(0));
2784 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2785 Result = DAG.getZeroExtendInReg(Result,
2786 Node->getOperand(0).getValueType());
2788 case ISD::SIGN_EXTEND:
2789 Result = PromoteOp(Node->getOperand(0));
2790 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2791 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2793 DAG.getValueType(Node->getOperand(0).getValueType()));
2795 case ISD::FP_EXTEND:
2796 Result = PromoteOp(Node->getOperand(0));
2797 if (Result.getValueType() != Op.getValueType())
2798 // Dynamically dead while we have only 2 FP types.
2799 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2802 Result = PromoteOp(Node->getOperand(0));
2803 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2808 case ISD::FP_ROUND_INREG:
2809 case ISD::SIGN_EXTEND_INREG: {
2810 Tmp1 = LegalizeOp(Node->getOperand(0));
2811 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2813 // If this operation is not supported, convert it to a shl/shr or load/store
2815 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2816 default: assert(0 && "This action not supported for this op yet!");
2817 case TargetLowering::Legal:
2818 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2820 case TargetLowering::Expand:
2821 // If this is an integer extend and shifts are supported, do that.
2822 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2823 // NOTE: we could fall back on load/store here too for targets without
2824 // SAR. However, it is doubtful that any exist.
2825 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2826 MVT::getSizeInBits(ExtraVT);
2827 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2828 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2829 Node->getOperand(0), ShiftCst);
2830 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2832 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2833 // The only way we can lower this is to turn it into a STORETRUNC,
2834 // EXTLOAD pair, targetting a temporary location (a stack slot).
2836 // NOTE: there is a choice here between constantly creating new stack
2837 // slots and always reusing the same one. We currently always create
2838 // new ones, as reuse may inhibit scheduling.
2839 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2840 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty);
2841 unsigned Align = TLI.getTargetData()->getTypeAlignment(Ty);
2842 MachineFunction &MF = DAG.getMachineFunction();
2844 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2845 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2846 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2847 Node->getOperand(0), StackSlot,
2848 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2849 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2850 Result, StackSlot, DAG.getSrcValue(NULL),
2853 assert(0 && "Unknown op");
2861 assert(Result.getValueType() == Op.getValueType() &&
2862 "Bad legalization!");
2864 // Make sure that the generated code is itself legal.
2866 Result = LegalizeOp(Result);
2868 // Note that LegalizeOp may be reentered even from single-use nodes, which
2869 // means that we always must cache transformed nodes.
2870 AddLegalizedOperand(Op, Result);
2874 /// PromoteOp - Given an operation that produces a value in an invalid type,
2875 /// promote it to compute the value into a larger type. The produced value will
2876 /// have the correct bits for the low portion of the register, but no guarantee
2877 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2878 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2879 MVT::ValueType VT = Op.getValueType();
2880 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2881 assert(getTypeAction(VT) == Promote &&
2882 "Caller should expand or legalize operands that are not promotable!");
2883 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2884 "Cannot promote to smaller type!");
2886 SDOperand Tmp1, Tmp2, Tmp3;
2888 SDNode *Node = Op.Val;
2890 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2891 if (I != PromotedNodes.end()) return I->second;
2893 switch (Node->getOpcode()) {
2894 case ISD::CopyFromReg:
2895 assert(0 && "CopyFromReg must be legal!");
2898 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2900 assert(0 && "Do not know how to promote this operator!");
2903 Result = DAG.getNode(ISD::UNDEF, NVT);
2907 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2909 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2910 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2912 case ISD::ConstantFP:
2913 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2914 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2918 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2919 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2920 Node->getOperand(1), Node->getOperand(2));
2924 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2926 Result = LegalizeOp(Node->getOperand(0));
2927 assert(Result.getValueType() >= NVT &&
2928 "This truncation doesn't make sense!");
2929 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2930 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2933 // The truncation is not required, because we don't guarantee anything
2934 // about high bits anyway.
2935 Result = PromoteOp(Node->getOperand(0));
2938 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2939 // Truncate the low part of the expanded value to the result type
2940 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2943 case ISD::SIGN_EXTEND:
2944 case ISD::ZERO_EXTEND:
2945 case ISD::ANY_EXTEND:
2946 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2947 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2949 // Input is legal? Just do extend all the way to the larger type.
2950 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2953 // Promote the reg if it's smaller.
2954 Result = PromoteOp(Node->getOperand(0));
2955 // The high bits are not guaranteed to be anything. Insert an extend.
2956 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2957 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2958 DAG.getValueType(Node->getOperand(0).getValueType()));
2959 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2960 Result = DAG.getZeroExtendInReg(Result,
2961 Node->getOperand(0).getValueType());
2965 case ISD::BIT_CONVERT:
2966 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2967 Result = PromoteOp(Result);
2970 case ISD::FP_EXTEND:
2971 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2973 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2974 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2975 case Promote: assert(0 && "Unreachable with 2 FP types!");
2977 // Input is legal? Do an FP_ROUND_INREG.
2978 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
2979 DAG.getValueType(VT));
2984 case ISD::SINT_TO_FP:
2985 case ISD::UINT_TO_FP:
2986 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2988 // No extra round required here.
2989 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2993 Result = PromoteOp(Node->getOperand(0));
2994 if (Node->getOpcode() == ISD::SINT_TO_FP)
2995 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2997 DAG.getValueType(Node->getOperand(0).getValueType()));
2999 Result = DAG.getZeroExtendInReg(Result,
3000 Node->getOperand(0).getValueType());
3001 // No extra round required here.
3002 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3005 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3006 Node->getOperand(0));
3007 // Round if we cannot tolerate excess precision.
3008 if (NoExcessFPPrecision)
3009 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3010 DAG.getValueType(VT));
3015 case ISD::SIGN_EXTEND_INREG:
3016 Result = PromoteOp(Node->getOperand(0));
3017 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3018 Node->getOperand(1));
3020 case ISD::FP_TO_SINT:
3021 case ISD::FP_TO_UINT:
3022 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3024 Tmp1 = Node->getOperand(0);
3027 // The input result is prerounded, so we don't have to do anything
3029 Tmp1 = PromoteOp(Node->getOperand(0));
3032 assert(0 && "not implemented");
3034 // If we're promoting a UINT to a larger size, check to see if the new node
3035 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3036 // we can use that instead. This allows us to generate better code for
3037 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3038 // legal, such as PowerPC.
3039 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3040 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3041 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3042 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3043 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3045 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3051 Tmp1 = PromoteOp(Node->getOperand(0));
3052 assert(Tmp1.getValueType() == NVT);
3053 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3054 // NOTE: we do not have to do any extra rounding here for
3055 // NoExcessFPPrecision, because we know the input will have the appropriate
3056 // precision, and these operations don't modify precision at all.
3062 Tmp1 = PromoteOp(Node->getOperand(0));
3063 assert(Tmp1.getValueType() == NVT);
3064 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3065 if (NoExcessFPPrecision)
3066 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3067 DAG.getValueType(VT));
3076 // The input may have strange things in the top bits of the registers, but
3077 // these operations don't care. They may have weird bits going out, but
3078 // that too is okay if they are integer operations.
3079 Tmp1 = PromoteOp(Node->getOperand(0));
3080 Tmp2 = PromoteOp(Node->getOperand(1));
3081 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3082 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3087 Tmp1 = PromoteOp(Node->getOperand(0));
3088 Tmp2 = PromoteOp(Node->getOperand(1));
3089 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3090 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3092 // Floating point operations will give excess precision that we may not be
3093 // able to tolerate. If we DO allow excess precision, just leave it,
3094 // otherwise excise it.
3095 // FIXME: Why would we need to round FP ops more than integer ones?
3096 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3097 if (NoExcessFPPrecision)
3098 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3099 DAG.getValueType(VT));
3104 // These operators require that their input be sign extended.
3105 Tmp1 = PromoteOp(Node->getOperand(0));
3106 Tmp2 = PromoteOp(Node->getOperand(1));
3107 if (MVT::isInteger(NVT)) {
3108 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3109 DAG.getValueType(VT));
3110 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3111 DAG.getValueType(VT));
3113 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3115 // Perform FP_ROUND: this is probably overly pessimistic.
3116 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3117 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3118 DAG.getValueType(VT));
3122 case ISD::FCOPYSIGN:
3123 // These operators require that their input be fp extended.
3124 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3126 Tmp1 = LegalizeOp(Node->getOperand(0));
3129 Tmp1 = PromoteOp(Node->getOperand(0));
3132 assert(0 && "not implemented");
3134 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3136 Tmp2 = LegalizeOp(Node->getOperand(1));
3139 Tmp2 = PromoteOp(Node->getOperand(1));
3142 assert(0 && "not implemented");
3144 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3146 // Perform FP_ROUND: this is probably overly pessimistic.
3147 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3148 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3149 DAG.getValueType(VT));
3154 // These operators require that their input be zero extended.
3155 Tmp1 = PromoteOp(Node->getOperand(0));
3156 Tmp2 = PromoteOp(Node->getOperand(1));
3157 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3158 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3159 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3160 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3164 Tmp1 = PromoteOp(Node->getOperand(0));
3165 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3168 // The input value must be properly sign extended.
3169 Tmp1 = PromoteOp(Node->getOperand(0));
3170 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3171 DAG.getValueType(VT));
3172 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3175 // The input value must be properly zero extended.
3176 Tmp1 = PromoteOp(Node->getOperand(0));
3177 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3178 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3182 Tmp1 = Node->getOperand(0); // Get the chain.
3183 Tmp2 = Node->getOperand(1); // Get the pointer.
3184 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3185 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3186 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3188 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3189 Node->getOperand(2));
3190 // Increment the pointer, VAList, to the next vaarg
3191 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3192 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3193 TLI.getPointerTy()));
3194 // Store the incremented VAList to the legalized pointer
3195 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2,
3196 Node->getOperand(2));
3197 // Load the actual argument out of the pointer VAList
3198 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList,
3199 DAG.getSrcValue(0), VT);
3201 // Remember that we legalized the chain.
3202 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3206 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Node->getOperand(0),
3207 Node->getOperand(1), Node->getOperand(2), VT);
3208 // Remember that we legalized the chain.
3209 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3214 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Node->getOperand(0),
3215 Node->getOperand(1), Node->getOperand(2),
3216 cast<VTSDNode>(Node->getOperand(3))->getVT());
3217 // Remember that we legalized the chain.
3218 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3221 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3222 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3223 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3225 case ISD::SELECT_CC:
3226 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3227 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3228 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3229 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3232 Tmp1 = Node->getOperand(0);
3233 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3234 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3235 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3236 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
3237 TLI.getShiftAmountTy()));
3242 // Zero extend the argument
3243 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3244 // Perform the larger operation, then subtract if needed.
3245 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3246 switch(Node->getOpcode()) {
3251 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3252 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3253 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
3254 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3255 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
3258 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3259 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3260 DAG.getConstant(getSizeInBits(NVT) -
3261 getSizeInBits(VT), NVT));
3265 case ISD::VEXTRACT_VECTOR_ELT:
3266 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
3268 case ISD::EXTRACT_VECTOR_ELT:
3269 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3273 assert(Result.Val && "Didn't set a result!");
3275 // Make sure the result is itself legal.
3276 Result = LegalizeOp(Result);
3278 // Remember that we promoted this!
3279 AddPromotedOperand(Op, Result);
3283 /// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
3284 /// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
3285 /// on the vector type. The return type of this matches the element type of the
3286 /// vector, which may not be legal for the target.
3287 SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
3288 // We know that operand #0 is the Vec vector. If the index is a constant
3289 // or if the invec is a supported hardware type, we can use it. Otherwise,
3290 // lower to a store then an indexed load.
3291 SDOperand Vec = Op.getOperand(0);
3292 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3294 SDNode *InVal = Vec.Val;
3295 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
3296 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
3298 // Figure out if there is a Packed type corresponding to this Vector
3299 // type. If so, convert to the packed type.
3300 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3301 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
3302 // Turn this into a packed extract_vector_elt operation.
3303 Vec = PackVectorOp(Vec, TVT);
3304 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
3305 } else if (NumElems == 1) {
3306 // This must be an access of the only element. Return it.
3307 return PackVectorOp(Vec, EVT);
3308 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
3310 SplitVectorOp(Vec, Lo, Hi);
3311 if (CIdx->getValue() < NumElems/2) {
3315 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3318 // It's now an extract from the appropriate high or low part. Recurse.
3319 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3320 return LowerVEXTRACT_VECTOR_ELT(Op);
3322 // Variable index case for extract element.
3323 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
3324 assert(0 && "unimp!");
3329 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3331 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3332 SDOperand Vector = Op.getOperand(0);
3333 SDOperand Idx = Op.getOperand(1);
3335 // If the target doesn't support this, store the value to a temporary
3336 // stack slot, then LOAD the scalar element back out.
3337 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
3338 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3339 Vector, StackPtr, DAG.getSrcValue(NULL));
3341 // Add the offset to the index.
3342 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3343 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3344 DAG.getConstant(EltSize, Idx.getValueType()));
3345 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3347 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, DAG.getSrcValue(NULL));
3351 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3352 /// with condition CC on the current target. This usually involves legalizing
3353 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3354 /// there may be no choice but to create a new SetCC node to represent the
3355 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3356 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3357 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3360 SDOperand Tmp1, Tmp2, Result;
3362 switch (getTypeAction(LHS.getValueType())) {
3364 Tmp1 = LegalizeOp(LHS); // LHS
3365 Tmp2 = LegalizeOp(RHS); // RHS
3368 Tmp1 = PromoteOp(LHS); // LHS
3369 Tmp2 = PromoteOp(RHS); // RHS
3371 // If this is an FP compare, the operands have already been extended.
3372 if (MVT::isInteger(LHS.getValueType())) {
3373 MVT::ValueType VT = LHS.getValueType();
3374 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3376 // Otherwise, we have to insert explicit sign or zero extends. Note
3377 // that we could insert sign extends for ALL conditions, but zero extend
3378 // is cheaper on many machines (an AND instead of two shifts), so prefer
3380 switch (cast<CondCodeSDNode>(CC)->get()) {
3381 default: assert(0 && "Unknown integer comparison!");
3388 // ALL of these operations will work if we either sign or zero extend
3389 // the operands (including the unsigned comparisons!). Zero extend is
3390 // usually a simpler/cheaper operation, so prefer it.
3391 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3392 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3398 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3399 DAG.getValueType(VT));
3400 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3401 DAG.getValueType(VT));
3407 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3408 ExpandOp(LHS, LHSLo, LHSHi);
3409 ExpandOp(RHS, RHSLo, RHSHi);
3410 switch (cast<CondCodeSDNode>(CC)->get()) {
3414 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3415 if (RHSCST->isAllOnesValue()) {
3416 // Comparison to -1.
3417 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3422 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3423 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3424 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3425 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3428 // If this is a comparison of the sign bit, just look at the top part.
3430 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3431 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3432 CST->getValue() == 0) || // X < 0
3433 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3434 CST->isAllOnesValue())) { // X > -1
3440 // FIXME: This generated code sucks.
3441 ISD::CondCode LowCC;
3442 switch (cast<CondCodeSDNode>(CC)->get()) {
3443 default: assert(0 && "Unknown integer setcc!");
3445 case ISD::SETULT: LowCC = ISD::SETULT; break;
3447 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3449 case ISD::SETULE: LowCC = ISD::SETULE; break;
3451 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3454 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3455 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3456 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3458 // NOTE: on targets without efficient SELECT of bools, we can always use
3459 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3460 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3461 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3462 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3463 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3464 Result, Tmp1, Tmp2));
3473 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3474 /// The resultant code need not be legal. Note that SrcOp is the input operand
3475 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3476 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3478 // Create the stack frame object.
3479 SDOperand FIPtr = CreateStackTemporary(DestVT);
3481 // Emit a store to the stack slot.
3482 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3483 SrcOp, FIPtr, DAG.getSrcValue(NULL));
3484 // Result is a load from the stack slot.
3485 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0));
3488 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3489 // Create a vector sized/aligned stack slot, store the value to element #0,
3490 // then load the whole vector back out.
3491 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3492 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3493 Node->getOperand(0), StackPtr,
3494 DAG.getSrcValue(NULL));
3495 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,DAG.getSrcValue(NULL));
3499 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3500 /// support the operation, but do support the resultant packed vector type.
3501 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3503 // If the only non-undef value is the low element, turn this into a
3504 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3505 unsigned NumElems = Node->getNumOperands();
3506 bool isOnlyLowElement = true;
3507 SDOperand SplatValue = Node->getOperand(0);
3508 std::map<SDOperand, std::vector<unsigned> > Values;
3509 Values[SplatValue].push_back(0);
3510 bool isConstant = true;
3511 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3512 SplatValue.getOpcode() != ISD::UNDEF)
3515 for (unsigned i = 1; i < NumElems; ++i) {
3516 SDOperand V = Node->getOperand(i);
3517 Values[V].push_back(i);
3518 if (V.getOpcode() != ISD::UNDEF)
3519 isOnlyLowElement = false;
3520 if (SplatValue != V)
3521 SplatValue = SDOperand(0,0);
3523 // If this isn't a constant element or an undef, we can't use a constant
3525 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3526 V.getOpcode() != ISD::UNDEF)
3530 if (isOnlyLowElement) {
3531 // If the low element is an undef too, then this whole things is an undef.
3532 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3533 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3534 // Otherwise, turn this into a scalar_to_vector node.
3535 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3536 Node->getOperand(0));
3539 // If all elements are constants, create a load from the constant pool.
3541 MVT::ValueType VT = Node->getValueType(0);
3543 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3544 std::vector<Constant*> CV;
3545 for (unsigned i = 0, e = NumElems; i != e; ++i) {
3546 if (ConstantFPSDNode *V =
3547 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3548 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3549 } else if (ConstantSDNode *V =
3550 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3551 CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
3553 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3554 CV.push_back(UndefValue::get(OpNTy));
3557 Constant *CP = ConstantPacked::get(CV);
3558 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3559 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
3560 DAG.getSrcValue(NULL));
3563 if (SplatValue.Val) { // Splat of one value?
3564 // Build the shuffle constant vector: <0, 0, 0, 0>
3565 MVT::ValueType MaskVT =
3566 MVT::getIntVectorWithNumElements(NumElems);
3567 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
3568 std::vector<SDOperand> ZeroVec(NumElems, Zero);
3569 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3570 &ZeroVec[0], ZeroVec.size());
3572 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3573 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
3574 // Get the splatted value into the low element of a vector register.
3575 SDOperand LowValVec =
3576 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3578 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3579 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3580 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3585 // If there are only two unique elements, we may be able to turn this into a
3587 if (Values.size() == 2) {
3588 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
3589 MVT::ValueType MaskVT =
3590 MVT::getIntVectorWithNumElements(NumElems);
3591 std::vector<SDOperand> MaskVec(NumElems);
3593 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3594 E = Values.end(); I != E; ++I) {
3595 for (std::vector<unsigned>::iterator II = I->second.begin(),
3596 EE = I->second.end(); II != EE; ++II)
3597 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
3600 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3601 &MaskVec[0], MaskVec.size());
3603 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3604 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
3605 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
3606 SmallVector<SDOperand, 8> Ops;
3607 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3608 E = Values.end(); I != E; ++I) {
3609 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3613 Ops.push_back(ShuffleMask);
3615 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
3616 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
3617 &Ops[0], Ops.size());
3621 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
3622 // aligned object on the stack, store each element into it, then load
3623 // the result as a vector.
3624 MVT::ValueType VT = Node->getValueType(0);
3625 // Create the stack frame object.
3626 SDOperand FIPtr = CreateStackTemporary(VT);
3628 // Emit a store of each element to the stack slot.
3629 SmallVector<SDOperand, 8> Stores;
3630 unsigned TypeByteSize =
3631 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
3632 unsigned VectorSize = MVT::getSizeInBits(VT)/8;
3633 // Store (in the right endianness) the elements to memory.
3634 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3635 // Ignore undef elements.
3636 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3638 unsigned Offset = TypeByteSize*i;
3640 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
3641 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
3643 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3644 Node->getOperand(i), Idx,
3645 DAG.getSrcValue(NULL)));
3648 SDOperand StoreChain;
3649 if (!Stores.empty()) // Not all undef elements?
3650 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3651 &Stores[0], Stores.size());
3653 StoreChain = DAG.getEntryNode();
3655 // Result is a load from the stack slot.
3656 return DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0));
3659 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
3660 /// specified value type.
3661 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
3662 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3663 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
3664 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
3665 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
3668 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
3669 SDOperand Op, SDOperand Amt,
3670 SDOperand &Lo, SDOperand &Hi) {
3671 // Expand the subcomponents.
3672 SDOperand LHSL, LHSH;
3673 ExpandOp(Op, LHSL, LHSH);
3675 SDOperand Ops[] = { LHSL, LHSH, Amt };
3676 MVT::ValueType VT = LHSL.getValueType();
3677 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
3678 Hi = Lo.getValue(1);
3682 /// ExpandShift - Try to find a clever way to expand this shift operation out to
3683 /// smaller elements. If we can't find a way that is more efficient than a
3684 /// libcall on this target, return false. Otherwise, return true with the
3685 /// low-parts expanded into Lo and Hi.
3686 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3687 SDOperand &Lo, SDOperand &Hi) {
3688 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3689 "This is not a shift!");
3691 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3692 SDOperand ShAmt = LegalizeOp(Amt);
3693 MVT::ValueType ShTy = ShAmt.getValueType();
3694 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3695 unsigned NVTBits = MVT::getSizeInBits(NVT);
3697 // Handle the case when Amt is an immediate. Other cases are currently broken
3698 // and are disabled.
3699 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3700 unsigned Cst = CN->getValue();
3701 // Expand the incoming operand to be shifted, so that we have its parts
3703 ExpandOp(Op, InL, InH);
3707 Lo = DAG.getConstant(0, NVT);
3708 Hi = DAG.getConstant(0, NVT);
3709 } else if (Cst > NVTBits) {
3710 Lo = DAG.getConstant(0, NVT);
3711 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
3712 } else if (Cst == NVTBits) {
3713 Lo = DAG.getConstant(0, NVT);
3716 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
3717 Hi = DAG.getNode(ISD::OR, NVT,
3718 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
3719 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
3724 Lo = DAG.getConstant(0, NVT);
3725 Hi = DAG.getConstant(0, NVT);
3726 } else if (Cst > NVTBits) {
3727 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
3728 Hi = DAG.getConstant(0, NVT);
3729 } else if (Cst == NVTBits) {
3731 Hi = DAG.getConstant(0, NVT);
3733 Lo = DAG.getNode(ISD::OR, NVT,
3734 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3735 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3736 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
3741 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
3742 DAG.getConstant(NVTBits-1, ShTy));
3743 } else if (Cst > NVTBits) {
3744 Lo = DAG.getNode(ISD::SRA, NVT, InH,
3745 DAG.getConstant(Cst-NVTBits, ShTy));
3746 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3747 DAG.getConstant(NVTBits-1, ShTy));
3748 } else if (Cst == NVTBits) {
3750 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3751 DAG.getConstant(NVTBits-1, ShTy));
3753 Lo = DAG.getNode(ISD::OR, NVT,
3754 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3755 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3756 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
3765 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
3766 // does not fit into a register, return the lo part and set the hi part to the
3767 // by-reg argument. If it does fit into a single register, return the result
3768 // and leave the Hi part unset.
3769 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3771 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
3772 // The input chain to this libcall is the entry node of the function.
3773 // Legalizing the call will automatically add the previous call to the
3775 SDOperand InChain = DAG.getEntryNode();
3777 TargetLowering::ArgListTy Args;
3778 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3779 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3780 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3781 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3783 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3785 // Splice the libcall in wherever FindInputOutputChains tells us to.
3786 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3787 std::pair<SDOperand,SDOperand> CallInfo =
3788 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3791 // Legalize the call sequence, starting with the chain. This will advance
3792 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
3793 // was added by LowerCallTo (guaranteeing proper serialization of calls).
3794 LegalizeOp(CallInfo.second);
3796 switch (getTypeAction(CallInfo.first.getValueType())) {
3797 default: assert(0 && "Unknown thing");
3799 Result = CallInfo.first;
3802 ExpandOp(CallInfo.first, Result, Hi);
3809 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3810 /// destination type is legal.
3811 SDOperand SelectionDAGLegalize::
3812 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3813 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3814 assert(getTypeAction(Source.getValueType()) == Expand &&
3815 "This is not an expansion!");
3816 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3819 assert(Source.getValueType() == MVT::i64 &&
3820 "This only works for 64-bit -> FP");
3821 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3822 // incoming integer is set. To handle this, we dynamically test to see if
3823 // it is set, and, if so, add a fudge factor.
3825 ExpandOp(Source, Lo, Hi);
3827 // If this is unsigned, and not supported, first perform the conversion to
3828 // signed, then adjust the result if the sign bit is set.
3829 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3830 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3832 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3833 DAG.getConstant(0, Hi.getValueType()),
3835 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3836 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3837 SignSet, Four, Zero);
3838 uint64_t FF = 0x5f800000ULL;
3839 if (TLI.isLittleEndian()) FF <<= 32;
3840 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3842 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3843 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3844 SDOperand FudgeInReg;
3845 if (DestTy == MVT::f32)
3846 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3847 DAG.getSrcValue(NULL));
3849 assert(DestTy == MVT::f64 && "Unexpected conversion");
3850 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3851 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
3853 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3856 // Check to see if the target has a custom way to lower this. If so, use it.
3857 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3858 default: assert(0 && "This action not implemented for this operation!");
3859 case TargetLowering::Legal:
3860 case TargetLowering::Expand:
3861 break; // This case is handled below.
3862 case TargetLowering::Custom: {
3863 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3866 return LegalizeOp(NV);
3867 break; // The target decided this was legal after all
3871 // Expand the source, then glue it back together for the call. We must expand
3872 // the source in case it is shared (this pass of legalize must traverse it).
3873 SDOperand SrcLo, SrcHi;
3874 ExpandOp(Source, SrcLo, SrcHi);
3875 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
3877 const char *FnName = 0;
3878 if (DestTy == MVT::f32)
3879 FnName = "__floatdisf";
3881 assert(DestTy == MVT::f64 && "Unknown fp value type!");
3882 FnName = "__floatdidf";
3885 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
3886 SDOperand UnusedHiPart;
3887 return ExpandLibCall(FnName, Source.Val, UnusedHiPart);
3890 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
3891 /// INT_TO_FP operation of the specified operand when the target requests that
3892 /// we expand it. At this point, we know that the result and operand types are
3893 /// legal for the target.
3894 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
3896 MVT::ValueType DestVT) {
3897 if (Op0.getValueType() == MVT::i32) {
3898 // simple 32-bit [signed|unsigned] integer to float/double expansion
3900 // get the stack frame index of a 8 byte buffer
3901 MachineFunction &MF = DAG.getMachineFunction();
3902 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3903 // get address of 8 byte buffer
3904 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3905 // word offset constant for Hi/Lo address computation
3906 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
3907 // set up Hi and Lo (into buffer) address based on endian
3908 SDOperand Hi = StackSlot;
3909 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
3910 if (TLI.isLittleEndian())
3913 // if signed map to unsigned space
3914 SDOperand Op0Mapped;
3916 // constant used to invert sign bit (signed to unsigned mapping)
3917 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
3918 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
3922 // store the lo of the constructed double - based on integer input
3923 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3924 Op0Mapped, Lo, DAG.getSrcValue(NULL));
3925 // initial hi portion of constructed double
3926 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
3927 // store the hi of the constructed double - biased exponent
3928 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
3929 InitialHi, Hi, DAG.getSrcValue(NULL));
3930 // load the constructed double
3931 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
3932 DAG.getSrcValue(NULL));
3933 // FP constant to bias correct the final result
3934 SDOperand Bias = DAG.getConstantFP(isSigned ?
3935 BitsToDouble(0x4330000080000000ULL)
3936 : BitsToDouble(0x4330000000000000ULL),
3938 // subtract the bias
3939 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
3942 // handle final rounding
3943 if (DestVT == MVT::f64) {
3947 // if f32 then cast to f32
3948 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
3952 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
3953 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
3955 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
3956 DAG.getConstant(0, Op0.getValueType()),
3958 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3959 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3960 SignSet, Four, Zero);
3962 // If the sign bit of the integer is set, the large number will be treated
3963 // as a negative number. To counteract this, the dynamic code adds an
3964 // offset depending on the data type.
3966 switch (Op0.getValueType()) {
3967 default: assert(0 && "Unsupported integer type!");
3968 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
3969 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
3970 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
3971 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
3973 if (TLI.isLittleEndian()) FF <<= 32;
3974 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3976 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3977 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3978 SDOperand FudgeInReg;
3979 if (DestVT == MVT::f32)
3980 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3981 DAG.getSrcValue(NULL));
3983 assert(DestVT == MVT::f64 && "Unexpected conversion");
3984 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
3985 DAG.getEntryNode(), CPIdx,
3986 DAG.getSrcValue(NULL), MVT::f32));
3989 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
3992 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
3993 /// *INT_TO_FP operation of the specified operand when the target requests that
3994 /// we promote it. At this point, we know that the result and operand types are
3995 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
3996 /// operation that takes a larger input.
3997 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
3998 MVT::ValueType DestVT,
4000 // First step, figure out the appropriate *INT_TO_FP operation to use.
4001 MVT::ValueType NewInTy = LegalOp.getValueType();
4003 unsigned OpToUse = 0;
4005 // Scan for the appropriate larger type to use.
4007 NewInTy = (MVT::ValueType)(NewInTy+1);
4008 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4010 // If the target supports SINT_TO_FP of this type, use it.
4011 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4013 case TargetLowering::Legal:
4014 if (!TLI.isTypeLegal(NewInTy))
4015 break; // Can't use this datatype.
4017 case TargetLowering::Custom:
4018 OpToUse = ISD::SINT_TO_FP;
4022 if (isSigned) continue;
4024 // If the target supports UINT_TO_FP of this type, use it.
4025 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4027 case TargetLowering::Legal:
4028 if (!TLI.isTypeLegal(NewInTy))
4029 break; // Can't use this datatype.
4031 case TargetLowering::Custom:
4032 OpToUse = ISD::UINT_TO_FP;
4037 // Otherwise, try a larger type.
4040 // Okay, we found the operation and type to use. Zero extend our input to the
4041 // desired type then run the operation on it.
4042 return DAG.getNode(OpToUse, DestVT,
4043 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4047 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4048 /// FP_TO_*INT operation of the specified operand when the target requests that
4049 /// we promote it. At this point, we know that the result and operand types are
4050 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4051 /// operation that returns a larger result.
4052 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4053 MVT::ValueType DestVT,
4055 // First step, figure out the appropriate FP_TO*INT operation to use.
4056 MVT::ValueType NewOutTy = DestVT;
4058 unsigned OpToUse = 0;
4060 // Scan for the appropriate larger type to use.
4062 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4063 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4065 // If the target supports FP_TO_SINT returning this type, use it.
4066 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4068 case TargetLowering::Legal:
4069 if (!TLI.isTypeLegal(NewOutTy))
4070 break; // Can't use this datatype.
4072 case TargetLowering::Custom:
4073 OpToUse = ISD::FP_TO_SINT;
4078 // If the target supports FP_TO_UINT of this type, use it.
4079 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4081 case TargetLowering::Legal:
4082 if (!TLI.isTypeLegal(NewOutTy))
4083 break; // Can't use this datatype.
4085 case TargetLowering::Custom:
4086 OpToUse = ISD::FP_TO_UINT;
4091 // Otherwise, try a larger type.
4094 // Okay, we found the operation and type to use. Truncate the result of the
4095 // extended FP_TO_*INT operation to the desired size.
4096 return DAG.getNode(ISD::TRUNCATE, DestVT,
4097 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4100 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4102 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4103 MVT::ValueType VT = Op.getValueType();
4104 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4105 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4107 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4109 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4110 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4111 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4113 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4114 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4115 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4116 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4117 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4118 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4119 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4120 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4121 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4123 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4124 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4125 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4126 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4127 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4128 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4129 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4130 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4131 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4132 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4133 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4134 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4135 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4136 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4137 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4138 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4139 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4140 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4141 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4142 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4143 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4147 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4149 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4151 default: assert(0 && "Cannot expand this yet!");
4153 static const uint64_t mask[6] = {
4154 0x5555555555555555ULL, 0x3333333333333333ULL,
4155 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4156 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4158 MVT::ValueType VT = Op.getValueType();
4159 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4160 unsigned len = getSizeInBits(VT);
4161 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4162 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4163 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4164 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4165 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4166 DAG.getNode(ISD::AND, VT,
4167 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4172 // for now, we do this:
4173 // x = x | (x >> 1);
4174 // x = x | (x >> 2);
4176 // x = x | (x >>16);
4177 // x = x | (x >>32); // for 64-bit input
4178 // return popcount(~x);
4180 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4181 MVT::ValueType VT = Op.getValueType();
4182 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4183 unsigned len = getSizeInBits(VT);
4184 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4185 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4186 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4188 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4189 return DAG.getNode(ISD::CTPOP, VT, Op);
4192 // for now, we use: { return popcount(~x & (x - 1)); }
4193 // unless the target has ctlz but not ctpop, in which case we use:
4194 // { return 32 - nlz(~x & (x-1)); }
4195 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4196 MVT::ValueType VT = Op.getValueType();
4197 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4198 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4199 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4200 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4201 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4202 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4203 TLI.isOperationLegal(ISD::CTLZ, VT))
4204 return DAG.getNode(ISD::SUB, VT,
4205 DAG.getConstant(getSizeInBits(VT), VT),
4206 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4207 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4212 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4213 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4214 /// LegalizeNodes map is filled in for any results that are not expanded, the
4215 /// ExpandedNodes map is filled in for any results that are expanded, and the
4216 /// Lo/Hi values are returned.
4217 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4218 MVT::ValueType VT = Op.getValueType();
4219 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4220 SDNode *Node = Op.Val;
4221 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4222 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
4223 "Cannot expand FP values!");
4224 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
4225 "Cannot expand to FP value or to larger int value!");
4227 // See if we already expanded it.
4228 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4229 = ExpandedNodes.find(Op);
4230 if (I != ExpandedNodes.end()) {
4231 Lo = I->second.first;
4232 Hi = I->second.second;
4236 switch (Node->getOpcode()) {
4237 case ISD::CopyFromReg:
4238 assert(0 && "CopyFromReg must be legal!");
4241 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
4243 assert(0 && "Do not know how to expand this operator!");
4246 Lo = DAG.getNode(ISD::UNDEF, NVT);
4247 Hi = DAG.getNode(ISD::UNDEF, NVT);
4249 case ISD::Constant: {
4250 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4251 Lo = DAG.getConstant(Cst, NVT);
4252 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4255 case ISD::BUILD_PAIR:
4256 // Return the operands.
4257 Lo = Node->getOperand(0);
4258 Hi = Node->getOperand(1);
4261 case ISD::SIGN_EXTEND_INREG:
4262 ExpandOp(Node->getOperand(0), Lo, Hi);
4263 // Sign extend the lo-part.
4264 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4265 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4266 TLI.getShiftAmountTy()));
4267 // sext_inreg the low part if needed.
4268 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4272 ExpandOp(Node->getOperand(0), Lo, Hi);
4273 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4274 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4280 ExpandOp(Node->getOperand(0), Lo, Hi);
4281 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4282 DAG.getNode(ISD::CTPOP, NVT, Lo),
4283 DAG.getNode(ISD::CTPOP, NVT, Hi));
4284 Hi = DAG.getConstant(0, NVT);
4288 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4289 ExpandOp(Node->getOperand(0), Lo, Hi);
4290 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4291 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4292 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4294 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4295 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4297 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4298 Hi = DAG.getConstant(0, NVT);
4303 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4304 ExpandOp(Node->getOperand(0), Lo, Hi);
4305 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4306 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4307 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4309 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4310 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4312 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4313 Hi = DAG.getConstant(0, NVT);
4318 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4319 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4320 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4321 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4323 // Remember that we legalized the chain.
4324 Hi = LegalizeOp(Hi);
4325 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4326 if (!TLI.isLittleEndian())
4332 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4333 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4334 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
4336 // Increment the pointer to the other half.
4337 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4338 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4339 getIntPtrConstant(IncrementSize));
4340 // FIXME: This creates a bogus srcvalue!
4341 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
4343 // Build a factor node to remember that this load is independent of the
4345 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4348 // Remember that we legalized the chain.
4349 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4350 if (!TLI.isLittleEndian())
4356 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
4357 SDOperand LL, LH, RL, RH;
4358 ExpandOp(Node->getOperand(0), LL, LH);
4359 ExpandOp(Node->getOperand(1), RL, RH);
4360 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4361 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4365 SDOperand LL, LH, RL, RH;
4366 ExpandOp(Node->getOperand(1), LL, LH);
4367 ExpandOp(Node->getOperand(2), RL, RH);
4368 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4369 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4372 case ISD::SELECT_CC: {
4373 SDOperand TL, TH, FL, FH;
4374 ExpandOp(Node->getOperand(2), TL, TH);
4375 ExpandOp(Node->getOperand(3), FL, FH);
4376 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4377 Node->getOperand(1), TL, FL, Node->getOperand(4));
4378 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4379 Node->getOperand(1), TH, FH, Node->getOperand(4));
4382 case ISD::SEXTLOAD: {
4383 SDOperand Chain = Node->getOperand(0);
4384 SDOperand Ptr = Node->getOperand(1);
4385 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4388 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4390 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4393 // Remember that we legalized the chain.
4394 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4396 // The high part is obtained by SRA'ing all but one of the bits of the lo
4398 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4399 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
4400 TLI.getShiftAmountTy()));
4403 case ISD::ZEXTLOAD: {
4404 SDOperand Chain = Node->getOperand(0);
4405 SDOperand Ptr = Node->getOperand(1);
4406 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4409 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4411 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4414 // Remember that we legalized the chain.
4415 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4417 // The high part is just a zero.
4418 Hi = DAG.getConstant(0, NVT);
4421 case ISD::EXTLOAD: {
4422 SDOperand Chain = Node->getOperand(0);
4423 SDOperand Ptr = Node->getOperand(1);
4424 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4427 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4429 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4432 // Remember that we legalized the chain.
4433 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4435 // The high part is undefined.
4436 Hi = DAG.getNode(ISD::UNDEF, NVT);
4439 case ISD::ANY_EXTEND:
4440 // The low part is any extension of the input (which degenerates to a copy).
4441 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4442 // The high part is undefined.
4443 Hi = DAG.getNode(ISD::UNDEF, NVT);
4445 case ISD::SIGN_EXTEND: {
4446 // The low part is just a sign extension of the input (which degenerates to
4448 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4450 // The high part is obtained by SRA'ing all but one of the bits of the lo
4452 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4453 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4454 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4457 case ISD::ZERO_EXTEND:
4458 // The low part is just a zero extension of the input (which degenerates to
4460 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4462 // The high part is just a zero.
4463 Hi = DAG.getConstant(0, NVT);
4466 case ISD::BIT_CONVERT: {
4468 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
4469 // If the target wants to, allow it to lower this itself.
4470 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4471 case Expand: assert(0 && "cannot expand FP!");
4472 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
4473 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
4475 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
4478 // Turn this into a load/store pair by default.
4480 Tmp = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
4482 ExpandOp(Tmp, Lo, Hi);
4486 case ISD::READCYCLECOUNTER:
4487 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
4488 TargetLowering::Custom &&
4489 "Must custom expand ReadCycleCounter");
4490 Lo = TLI.LowerOperation(Op, DAG);
4491 assert(Lo.Val && "Node must be custom expanded!");
4492 Hi = Lo.getValue(1);
4493 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
4494 LegalizeOp(Lo.getValue(2)));
4497 // These operators cannot be expanded directly, emit them as calls to
4498 // library functions.
4499 case ISD::FP_TO_SINT:
4500 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
4502 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4503 case Expand: assert(0 && "cannot expand FP!");
4504 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4505 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4508 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
4510 // Now that the custom expander is done, expand the result, which is still
4513 ExpandOp(Op, Lo, Hi);
4518 if (Node->getOperand(0).getValueType() == MVT::f32)
4519 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
4521 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
4524 case ISD::FP_TO_UINT:
4525 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
4527 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4528 case Expand: assert(0 && "cannot expand FP!");
4529 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4530 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4533 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
4535 // Now that the custom expander is done, expand the result.
4537 ExpandOp(Op, Lo, Hi);
4542 if (Node->getOperand(0).getValueType() == MVT::f32)
4543 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
4545 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
4549 // If the target wants custom lowering, do so.
4550 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4551 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
4552 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
4553 Op = TLI.LowerOperation(Op, DAG);
4555 // Now that the custom expander is done, expand the result, which is
4557 ExpandOp(Op, Lo, Hi);
4562 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
4563 // this X << 1 as X+X.
4564 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
4565 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
4566 TLI.isOperationLegal(ISD::ADDE, NVT)) {
4567 SDOperand LoOps[2], HiOps[3];
4568 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
4569 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
4570 LoOps[1] = LoOps[0];
4571 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
4573 HiOps[1] = HiOps[0];
4574 HiOps[2] = Lo.getValue(1);
4575 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
4580 // If we can emit an efficient shift operation, do so now.
4581 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4584 // If this target supports SHL_PARTS, use it.
4585 TargetLowering::LegalizeAction Action =
4586 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
4587 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4588 Action == TargetLowering::Custom) {
4589 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4593 // Otherwise, emit a libcall.
4594 Lo = ExpandLibCall("__ashldi3", Node, Hi);
4599 // If the target wants custom lowering, do so.
4600 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4601 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
4602 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
4603 Op = TLI.LowerOperation(Op, DAG);
4605 // Now that the custom expander is done, expand the result, which is
4607 ExpandOp(Op, Lo, Hi);
4612 // If we can emit an efficient shift operation, do so now.
4613 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
4616 // If this target supports SRA_PARTS, use it.
4617 TargetLowering::LegalizeAction Action =
4618 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
4619 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4620 Action == TargetLowering::Custom) {
4621 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4625 // Otherwise, emit a libcall.
4626 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
4631 // If the target wants custom lowering, do so.
4632 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4633 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
4634 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
4635 Op = TLI.LowerOperation(Op, DAG);
4637 // Now that the custom expander is done, expand the result, which is
4639 ExpandOp(Op, Lo, Hi);
4644 // If we can emit an efficient shift operation, do so now.
4645 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4648 // If this target supports SRL_PARTS, use it.
4649 TargetLowering::LegalizeAction Action =
4650 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
4651 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4652 Action == TargetLowering::Custom) {
4653 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4657 // Otherwise, emit a libcall.
4658 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
4664 // If the target wants to custom expand this, let them.
4665 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
4666 TargetLowering::Custom) {
4667 Op = TLI.LowerOperation(Op, DAG);
4669 ExpandOp(Op, Lo, Hi);
4674 // Expand the subcomponents.
4675 SDOperand LHSL, LHSH, RHSL, RHSH;
4676 ExpandOp(Node->getOperand(0), LHSL, LHSH);
4677 ExpandOp(Node->getOperand(1), RHSL, RHSH);
4678 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
4679 SDOperand LoOps[2], HiOps[3];
4684 if (Node->getOpcode() == ISD::ADD) {
4685 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
4686 HiOps[2] = Lo.getValue(1);
4687 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
4689 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
4690 HiOps[2] = Lo.getValue(1);
4691 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
4696 // If the target wants to custom expand this, let them.
4697 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
4698 Op = TLI.LowerOperation(Op, DAG);
4700 ExpandOp(Op, Lo, Hi);
4705 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
4706 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
4707 bool UseLibCall = true;
4708 if (HasMULHS || HasMULHU) {
4709 SDOperand LL, LH, RL, RH;
4710 ExpandOp(Node->getOperand(0), LL, LH);
4711 ExpandOp(Node->getOperand(1), RL, RH);
4712 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
4713 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
4714 // extended the sign bit of the low half through the upper half, and if so
4715 // emit a MULHS instead of the alternate sequence that is valid for any
4716 // i64 x i64 multiply.
4718 // is RH an extension of the sign bit of RL?
4719 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
4720 RH.getOperand(1).getOpcode() == ISD::Constant &&
4721 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
4722 // is LH an extension of the sign bit of LL?
4723 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
4724 LH.getOperand(1).getOpcode() == ISD::Constant &&
4725 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
4726 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
4728 } else if (HasMULHU) {
4729 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
4730 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
4731 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
4732 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
4733 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
4737 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4741 Lo = ExpandLibCall("__muldi3" , Node, Hi);
4744 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
4745 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
4746 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
4747 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
4750 // Make sure the resultant values have been legalized themselves, unless this
4751 // is a type that requires multi-step expansion.
4752 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
4753 Lo = LegalizeOp(Lo);
4754 Hi = LegalizeOp(Hi);
4757 // Remember in a map if the values will be reused later.
4759 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4760 assert(isNew && "Value already expanded?!?");
4763 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
4764 /// two smaller values of MVT::Vector type.
4765 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
4767 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
4768 SDNode *Node = Op.Val;
4769 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
4770 assert(NumElements > 1 && "Cannot split a single element vector!");
4771 unsigned NewNumElts = NumElements/2;
4772 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
4773 SDOperand TypeNode = *(Node->op_end()-1);
4775 // See if we already split it.
4776 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4777 = SplitNodes.find(Op);
4778 if (I != SplitNodes.end()) {
4779 Lo = I->second.first;
4780 Hi = I->second.second;
4784 switch (Node->getOpcode()) {
4789 assert(0 && "Unhandled operation in SplitVectorOp!");
4790 case ISD::VBUILD_VECTOR: {
4791 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
4792 Node->op_begin()+NewNumElts);
4793 LoOps.push_back(NewNumEltsNode);
4794 LoOps.push_back(TypeNode);
4795 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size());
4797 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
4799 HiOps.push_back(NewNumEltsNode);
4800 HiOps.push_back(TypeNode);
4801 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size());
4812 SDOperand LL, LH, RL, RH;
4813 SplitVectorOp(Node->getOperand(0), LL, LH);
4814 SplitVectorOp(Node->getOperand(1), RL, RH);
4816 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
4817 NewNumEltsNode, TypeNode);
4818 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
4819 NewNumEltsNode, TypeNode);
4823 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4824 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4825 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4827 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4828 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
4829 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4830 getIntPtrConstant(IncrementSize));
4831 // FIXME: This creates a bogus srcvalue!
4832 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4834 // Build a factor node to remember that this load is independent of the
4836 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4839 // Remember that we legalized the chain.
4840 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4843 case ISD::VBIT_CONVERT: {
4844 // We know the result is a vector. The input may be either a vector or a
4846 if (Op.getOperand(0).getValueType() != MVT::Vector) {
4847 // Lower to a store/load. FIXME: this could be improved probably.
4848 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
4850 SDOperand St = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
4851 Op.getOperand(0), Ptr, DAG.getSrcValue(0));
4852 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4853 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0));
4854 SplitVectorOp(St, Lo, Hi);
4856 // If the input is a vector type, we have to either scalarize it, pack it
4857 // or convert it based on whether the input vector type is legal.
4858 SDNode *InVal = Node->getOperand(0).Val;
4860 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
4861 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
4863 // If the input is from a single element vector, scalarize the vector,
4864 // then treat like a scalar.
4865 if (NumElems == 1) {
4866 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT);
4867 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar,
4868 Op.getOperand(1), Op.getOperand(2));
4869 SplitVectorOp(Scalar, Lo, Hi);
4871 // Split the input vector.
4872 SplitVectorOp(Op.getOperand(0), Lo, Hi);
4874 // Convert each of the pieces now.
4875 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo,
4876 NewNumEltsNode, TypeNode);
4877 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi,
4878 NewNumEltsNode, TypeNode);
4885 // Remember in a map if the values will be reused later.
4887 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4888 assert(isNew && "Value already expanded?!?");
4892 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
4893 /// equivalent operation that returns a scalar (e.g. F32) or packed value
4894 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
4895 /// type for the result.
4896 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
4897 MVT::ValueType NewVT) {
4898 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
4899 SDNode *Node = Op.Val;
4901 // See if we already packed it.
4902 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
4903 if (I != PackedNodes.end()) return I->second;
4906 switch (Node->getOpcode()) {
4909 Node->dump(); std::cerr << "\n";
4911 assert(0 && "Unknown vector operation in PackVectorOp!");
4920 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
4922 PackVectorOp(Node->getOperand(0), NewVT),
4923 PackVectorOp(Node->getOperand(1), NewVT));
4926 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
4927 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
4929 Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(2));
4931 // Remember that we legalized the chain.
4932 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4935 case ISD::VBUILD_VECTOR:
4936 if (Node->getOperand(0).getValueType() == NewVT) {
4937 // Returning a scalar?
4938 Result = Node->getOperand(0);
4940 // Returning a BUILD_VECTOR?
4942 // If all elements of the build_vector are undefs, return an undef.
4943 bool AllUndef = true;
4944 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i)
4945 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) {
4950 Result = DAG.getNode(ISD::UNDEF, NewVT);
4952 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(),
4953 Node->getNumOperands()-2);
4957 case ISD::VINSERT_VECTOR_ELT:
4958 if (!MVT::isVector(NewVT)) {
4959 // Returning a scalar? Must be the inserted element.
4960 Result = Node->getOperand(1);
4962 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
4963 PackVectorOp(Node->getOperand(0), NewVT),
4964 Node->getOperand(1), Node->getOperand(2));
4967 case ISD::VVECTOR_SHUFFLE:
4968 if (!MVT::isVector(NewVT)) {
4969 // Returning a scalar? Figure out if it is the LHS or RHS and return it.
4970 SDOperand EltNum = Node->getOperand(2).getOperand(0);
4971 if (cast<ConstantSDNode>(EltNum)->getValue())
4972 Result = PackVectorOp(Node->getOperand(1), NewVT);
4974 Result = PackVectorOp(Node->getOperand(0), NewVT);
4976 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index
4977 // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
4978 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
4979 Node->getOperand(2).Val->op_end()-2);
4980 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
4981 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT,
4982 Node->getOperand(2).Val->op_begin(),
4983 Node->getOperand(2).Val->getNumOperands()-2);
4985 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
4986 PackVectorOp(Node->getOperand(0), NewVT),
4987 PackVectorOp(Node->getOperand(1), NewVT), BV);
4990 case ISD::VBIT_CONVERT:
4991 if (Op.getOperand(0).getValueType() != MVT::Vector)
4992 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
4994 // If the input is a vector type, we have to either scalarize it, pack it
4995 // or convert it based on whether the input vector type is legal.
4996 SDNode *InVal = Node->getOperand(0).Val;
4998 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
4999 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
5001 // Figure out if there is a Packed type corresponding to this Vector
5002 // type. If so, convert to the packed type.
5003 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
5004 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
5005 // Turn this into a bit convert of the packed input.
5006 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5007 PackVectorOp(Node->getOperand(0), TVT));
5009 } else if (NumElems == 1) {
5010 // Turn this into a bit convert of the scalar input.
5011 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5012 PackVectorOp(Node->getOperand(0), EVT));
5016 assert(0 && "Cast from unsupported vector type not implemented yet!");
5021 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
5022 PackVectorOp(Op.getOperand(1), NewVT),
5023 PackVectorOp(Op.getOperand(2), NewVT));
5027 if (TLI.isTypeLegal(NewVT))
5028 Result = LegalizeOp(Result);
5029 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
5030 assert(isNew && "Value already packed?");
5035 // SelectionDAG::Legalize - This is the entry point for the file.
5037 void SelectionDAG::Legalize() {
5038 if (ViewLegalizeDAGs) viewGraph();
5040 /// run - This is the main entry point to this class.
5042 SelectionDAGLegalize(*this).LegalizeDAG();