1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Support/MathExtras.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
27 //===----------------------------------------------------------------------===//
28 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
29 /// hacks on it until the target machine can handle it. This involves
30 /// eliminating value sizes the machine cannot handle (promoting small sizes to
31 /// large sizes or splitting up large values into small values) as well as
32 /// eliminating operations the machine cannot handle.
34 /// This code also does a small amount of optimization and recognition of idioms
35 /// as part of its processing. For example, if a target does not support a
36 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
37 /// will attempt merge setcc and brc instructions into brcc's.
40 class SelectionDAGLegalize {
44 // Libcall insertion helpers.
46 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
47 /// legalized. We use this to ensure that calls are properly serialized
48 /// against each other, including inserted libcalls.
49 SDOperand LastCALLSEQ_END;
51 /// IsLegalizingCall - This member is used *only* for purposes of providing
52 /// helpful assertions that a libcall isn't created while another call is
53 /// being legalized (which could lead to non-serialized call sequences).
54 bool IsLegalizingCall;
57 Legal, // The target natively supports this operation.
58 Promote, // This operation should be executed in a larger type.
59 Expand, // Try to expand this to other ops, otherwise use a libcall.
62 /// ValueTypeActions - This is a bitvector that contains two bits for each
63 /// value type, where the two bits correspond to the LegalizeAction enum.
64 /// This can be queried with "getTypeAction(VT)".
65 TargetLowering::ValueTypeActionImpl ValueTypeActions;
67 /// LegalizedNodes - For nodes that are of legal width, and that have more
68 /// than one use, this map indicates what regularized operand to use. This
69 /// allows us to avoid legalizing the same thing more than once.
70 std::map<SDOperand, SDOperand> LegalizedNodes;
72 /// PromotedNodes - For nodes that are below legal width, and that have more
73 /// than one use, this map indicates what promoted value to use. This allows
74 /// us to avoid promoting the same thing more than once.
75 std::map<SDOperand, SDOperand> PromotedNodes;
77 /// ExpandedNodes - For nodes that need to be expanded this map indicates
78 /// which which operands are the expanded version of the input. This allows
79 /// us to avoid expanding the same node more than once.
80 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
82 /// SplitNodes - For vector nodes that need to be split, this map indicates
83 /// which which operands are the split version of the input. This allows us
84 /// to avoid splitting the same node more than once.
85 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
87 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
88 /// concrete packed types, this contains the mapping of ones we have already
89 /// processed to the result.
90 std::map<SDOperand, SDOperand> PackedNodes;
92 void AddLegalizedOperand(SDOperand From, SDOperand To) {
93 LegalizedNodes.insert(std::make_pair(From, To));
94 // If someone requests legalization of the new node, return itself.
96 LegalizedNodes.insert(std::make_pair(To, To));
98 void AddPromotedOperand(SDOperand From, SDOperand To) {
99 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
100 assert(isNew && "Got into the map somehow?");
101 // If someone requests legalization of the new node, return itself.
102 LegalizedNodes.insert(std::make_pair(To, To));
107 SelectionDAGLegalize(SelectionDAG &DAG);
109 /// getTypeAction - Return how we should legalize values of this type, either
110 /// it is already legal or we need to expand it into multiple registers of
111 /// smaller integer type, or we need to promote it to a larger type.
112 LegalizeAction getTypeAction(MVT::ValueType VT) const {
113 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
116 /// isTypeLegal - Return true if this type is legal on this target.
118 bool isTypeLegal(MVT::ValueType VT) const {
119 return getTypeAction(VT) == Legal;
125 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
126 /// appropriate for its type.
127 void HandleOp(SDOperand Op);
129 /// LegalizeOp - We know that the specified value has a legal type.
130 /// Recursively ensure that the operands have legal types, then return the
132 SDOperand LegalizeOp(SDOperand O);
134 /// PromoteOp - Given an operation that produces a value in an invalid type,
135 /// promote it to compute the value into a larger type. The produced value
136 /// will have the correct bits for the low portion of the register, but no
137 /// guarantee is made about the top bits: it may be zero, sign-extended, or
139 SDOperand PromoteOp(SDOperand O);
141 /// ExpandOp - Expand the specified SDOperand into its two component pieces
142 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
143 /// the LegalizeNodes map is filled in for any results that are not expanded,
144 /// the ExpandedNodes map is filled in for any results that are expanded, and
145 /// the Lo/Hi values are returned. This applies to integer types and Vector
147 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
149 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
150 /// two smaller values of MVT::Vector type.
151 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
153 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
154 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
155 /// this is called, we know that PackedVT is the right type for the result and
156 /// we know that this type is legal for the target.
157 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
159 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest);
161 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
163 SDOperand CreateStackTemporary(MVT::ValueType VT);
165 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
167 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
170 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
171 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
172 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
174 MVT::ValueType DestVT);
175 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
177 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
180 SDOperand ExpandBSWAP(SDOperand Op);
181 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
182 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
183 SDOperand &Lo, SDOperand &Hi);
184 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
185 SDOperand &Lo, SDOperand &Hi);
187 SDOperand getIntPtrConstant(uint64_t Val) {
188 return DAG.getConstant(Val, TLI.getPointerTy());
193 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
194 /// specified vector opcode.
195 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
197 default: assert(0 && "Don't know how to scalarize this opcode!");
198 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
199 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
200 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
201 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
202 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
203 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
204 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
205 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
209 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
210 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
211 ValueTypeActions(TLI.getValueTypeActions()) {
212 assert(MVT::LAST_VALUETYPE <= 32 &&
213 "Too many value types for ValueTypeActions to hold!");
216 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
217 /// not been visited yet and if all of its operands have already been visited.
218 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
219 std::map<SDNode*, unsigned> &Visited) {
220 if (++Visited[N] != N->getNumOperands())
221 return; // Haven't visited all operands yet
225 if (N->hasOneUse()) { // Tail recurse in common case.
226 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
230 // Now that we have N in, add anything that uses it if all of their operands
232 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
233 ComputeTopDownOrdering(*UI, Order, Visited);
237 void SelectionDAGLegalize::LegalizeDAG() {
238 LastCALLSEQ_END = DAG.getEntryNode();
239 IsLegalizingCall = false;
241 // The legalize process is inherently a bottom-up recursive process (users
242 // legalize their uses before themselves). Given infinite stack space, we
243 // could just start legalizing on the root and traverse the whole graph. In
244 // practice however, this causes us to run out of stack space on large basic
245 // blocks. To avoid this problem, compute an ordering of the nodes where each
246 // node is only legalized after all of its operands are legalized.
247 std::map<SDNode*, unsigned> Visited;
248 std::vector<SDNode*> Order;
250 // Compute ordering from all of the leaves in the graphs, those (like the
251 // entry node) that have no operands.
252 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
253 E = DAG.allnodes_end(); I != E; ++I) {
254 if (I->getNumOperands() == 0) {
256 ComputeTopDownOrdering(I, Order, Visited);
260 assert(Order.size() == Visited.size() &&
262 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
263 "Error: DAG is cyclic!");
266 for (unsigned i = 0, e = Order.size(); i != e; ++i)
267 HandleOp(SDOperand(Order[i], 0));
269 // Finally, it's possible the root changed. Get the new root.
270 SDOperand OldRoot = DAG.getRoot();
271 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
272 DAG.setRoot(LegalizedNodes[OldRoot]);
274 ExpandedNodes.clear();
275 LegalizedNodes.clear();
276 PromotedNodes.clear();
280 // Remove dead nodes now.
281 DAG.RemoveDeadNodes(OldRoot.Val);
285 /// FindCallEndFromCallStart - Given a chained node that is part of a call
286 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
287 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
288 if (Node->getOpcode() == ISD::CALLSEQ_END)
290 if (Node->use_empty())
291 return 0; // No CallSeqEnd
293 // The chain is usually at the end.
294 SDOperand TheChain(Node, Node->getNumValues()-1);
295 if (TheChain.getValueType() != MVT::Other) {
296 // Sometimes it's at the beginning.
297 TheChain = SDOperand(Node, 0);
298 if (TheChain.getValueType() != MVT::Other) {
299 // Otherwise, hunt for it.
300 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
301 if (Node->getValueType(i) == MVT::Other) {
302 TheChain = SDOperand(Node, i);
306 // Otherwise, we walked into a node without a chain.
307 if (TheChain.getValueType() != MVT::Other)
312 for (SDNode::use_iterator UI = Node->use_begin(),
313 E = Node->use_end(); UI != E; ++UI) {
315 // Make sure to only follow users of our token chain.
317 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
318 if (User->getOperand(i) == TheChain)
319 if (SDNode *Result = FindCallEndFromCallStart(User))
325 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
326 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
327 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
328 assert(Node && "Didn't find callseq_start for a call??");
329 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
331 assert(Node->getOperand(0).getValueType() == MVT::Other &&
332 "Node doesn't have a token chain argument!");
333 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
336 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
337 /// see if any uses can reach Dest. If no dest operands can get to dest,
338 /// legalize them, legalize ourself, and return false, otherwise, return true.
339 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N,
341 if (N == Dest) return true; // N certainly leads to Dest :)
343 // If the first result of this node has been already legalized, then it cannot
345 switch (getTypeAction(N->getValueType(0))) {
347 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
350 if (PromotedNodes.count(SDOperand(N, 0))) return false;
353 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
357 // Okay, this node has not already been legalized. Check and legalize all
358 // operands. If none lead to Dest, then we can legalize this node.
359 bool OperandsLeadToDest = false;
360 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
361 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
362 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest);
364 if (OperandsLeadToDest) return true;
366 // Okay, this node looks safe, legalize it and return false.
367 switch (getTypeAction(N->getValueType(0))) {
369 LegalizeOp(SDOperand(N, 0));
372 PromoteOp(SDOperand(N, 0));
376 ExpandOp(SDOperand(N, 0), X, Y);
383 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
384 /// appropriate for its type.
385 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
386 switch (getTypeAction(Op.getValueType())) {
387 default: assert(0 && "Bad type action!");
388 case Legal: LegalizeOp(Op); break;
389 case Promote: PromoteOp(Op); break;
391 if (Op.getValueType() != MVT::Vector) {
396 unsigned NumOps = N->getNumOperands();
397 unsigned NumElements =
398 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
399 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
400 MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
401 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
402 // In the common case, this is a legal vector type, convert it to the
403 // packed operation and type now.
404 PackVectorOp(Op, PackedVT);
405 } else if (NumElements == 1) {
406 // Otherwise, if this is a single element vector, convert it to a
408 PackVectorOp(Op, EVT);
410 // Otherwise, this is a multiple element vector that isn't supported.
411 // Split it in half and legalize both parts.
413 SplitVectorOp(Op, X, Y);
421 /// LegalizeOp - We know that the specified value has a legal type.
422 /// Recursively ensure that the operands have legal types, then return the
424 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
425 assert(isTypeLegal(Op.getValueType()) &&
426 "Caller should expand or promote operands that are not legal!");
427 SDNode *Node = Op.Val;
429 // If this operation defines any values that cannot be represented in a
430 // register on this target, make sure to expand or promote them.
431 if (Node->getNumValues() > 1) {
432 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
433 if (getTypeAction(Node->getValueType(i)) != Legal) {
434 HandleOp(Op.getValue(i));
435 assert(LegalizedNodes.count(Op) &&
436 "Handling didn't add legal operands!");
437 return LegalizedNodes[Op];
441 // Note that LegalizeOp may be reentered even from single-use nodes, which
442 // means that we always must cache transformed nodes.
443 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
444 if (I != LegalizedNodes.end()) return I->second;
446 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
447 SDOperand Result = Op;
448 bool isCustom = false;
450 switch (Node->getOpcode()) {
451 case ISD::FrameIndex:
452 case ISD::EntryToken:
454 case ISD::BasicBlock:
455 case ISD::TargetFrameIndex:
456 case ISD::TargetConstant:
457 case ISD::TargetConstantFP:
458 case ISD::TargetConstantPool:
459 case ISD::TargetGlobalAddress:
460 case ISD::TargetExternalSymbol:
465 // Primitives must all be legal.
466 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
467 "This must be legal!");
470 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
471 // If this is a target node, legalize it by legalizing the operands then
472 // passing it through.
473 std::vector<SDOperand> Ops;
474 bool Changed = false;
475 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
476 Ops.push_back(LegalizeOp(Node->getOperand(i)));
477 Changed = Changed || Node->getOperand(i) != Ops.back();
480 if (Node->getNumValues() == 1)
481 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops);
483 std::vector<MVT::ValueType> VTs(Node->value_begin(),
485 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
488 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
489 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
490 return Result.getValue(Op.ResNo);
492 // Otherwise this is an unhandled builtin node. splat.
493 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
494 assert(0 && "Do not know how to legalize this operator!");
496 case ISD::GlobalAddress:
497 case ISD::ExternalSymbol:
498 case ISD::ConstantPool: // Nothing to do.
499 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
500 default: assert(0 && "This action is not supported yet!");
501 case TargetLowering::Custom:
502 Tmp1 = TLI.LowerOperation(Op, DAG);
503 if (Tmp1.Val) Result = Tmp1;
504 // FALLTHROUGH if the target doesn't want to lower this op after all.
505 case TargetLowering::Legal:
509 case ISD::AssertSext:
510 case ISD::AssertZext:
511 Tmp1 = LegalizeOp(Node->getOperand(0));
512 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
514 case ISD::MERGE_VALUES:
515 // Legalize eliminates MERGE_VALUES nodes.
516 Result = Node->getOperand(Op.ResNo);
518 case ISD::CopyFromReg:
519 Tmp1 = LegalizeOp(Node->getOperand(0));
520 Result = Op.getValue(0);
521 if (Node->getNumValues() == 2) {
522 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
524 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
525 if (Node->getNumOperands() == 3) {
526 Tmp2 = LegalizeOp(Node->getOperand(2));
527 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
529 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
531 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
533 // Since CopyFromReg produces two values, make sure to remember that we
534 // legalized both of them.
535 AddLegalizedOperand(Op.getValue(0), Result);
536 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
537 return Result.getValue(Op.ResNo);
539 MVT::ValueType VT = Op.getValueType();
540 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
541 default: assert(0 && "This action is not supported yet!");
542 case TargetLowering::Expand:
543 if (MVT::isInteger(VT))
544 Result = DAG.getConstant(0, VT);
545 else if (MVT::isFloatingPoint(VT))
546 Result = DAG.getConstantFP(0, VT);
548 assert(0 && "Unknown value type!");
550 case TargetLowering::Legal:
557 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
558 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
560 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
561 case TargetLowering::Promote:
562 default: assert(0 && "This action is not supported yet!");
563 case TargetLowering::Expand: {
564 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
565 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
566 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
568 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
569 const std::string &FName =
570 cast<StringSDNode>(Node->getOperand(3))->getValue();
571 const std::string &DirName =
572 cast<StringSDNode>(Node->getOperand(4))->getValue();
573 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
575 std::vector<SDOperand> Ops;
576 Ops.push_back(Tmp1); // chain
577 SDOperand LineOp = Node->getOperand(1);
578 SDOperand ColOp = Node->getOperand(2);
581 Ops.push_back(LineOp); // line #
582 Ops.push_back(ColOp); // col #
583 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
584 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
586 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
587 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
588 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
589 Ops.push_back(DAG.getConstant(ID, MVT::i32));
590 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops);
593 Result = Tmp1; // chain
597 case TargetLowering::Legal:
598 if (Tmp1 != Node->getOperand(0) ||
599 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
600 std::vector<SDOperand> Ops;
602 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
603 Ops.push_back(Node->getOperand(1)); // line # must be legal.
604 Ops.push_back(Node->getOperand(2)); // col # must be legal.
606 // Otherwise promote them.
607 Ops.push_back(PromoteOp(Node->getOperand(1)));
608 Ops.push_back(PromoteOp(Node->getOperand(2)));
610 Ops.push_back(Node->getOperand(3)); // filename must be legal.
611 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
612 Result = DAG.UpdateNodeOperands(Result, Ops);
619 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
620 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
621 default: assert(0 && "This action is not supported yet!");
622 case TargetLowering::Legal:
623 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
624 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
625 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
626 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
627 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
632 case ISD::DEBUG_LABEL:
633 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
634 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
635 default: assert(0 && "This action is not supported yet!");
636 case TargetLowering::Legal:
637 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
638 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
639 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
645 // We know we don't need to expand constants here, constants only have one
646 // value and we check that it is fine above.
648 // FIXME: Maybe we should handle things like targets that don't support full
649 // 32-bit immediates?
651 case ISD::ConstantFP: {
652 // Spill FP immediates to the constant pool if the target cannot directly
653 // codegen them. Targets often have some immediate values that can be
654 // efficiently generated into an FP register without a load. We explicitly
655 // leave these constants as ConstantFP nodes for the target to deal with.
656 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
658 // Check to see if this FP immediate is already legal.
659 bool isLegal = false;
660 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
661 E = TLI.legal_fpimm_end(); I != E; ++I)
662 if (CFP->isExactlyValue(*I)) {
667 // If this is a legal constant, turn it into a TargetConstantFP node.
669 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
673 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
674 default: assert(0 && "This action is not supported yet!");
675 case TargetLowering::Custom:
676 Tmp3 = TLI.LowerOperation(Result, DAG);
682 case TargetLowering::Expand:
683 // Otherwise we need to spill the constant to memory.
686 // If a FP immediate is precise when represented as a float and if the
687 // target can do an extending load from float to double, we put it into
688 // the constant pool as a float, even if it's is statically typed as a
690 MVT::ValueType VT = CFP->getValueType(0);
691 bool isDouble = VT == MVT::f64;
692 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
693 Type::FloatTy, CFP->getValue());
694 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
695 // Only do this if the target has a native EXTLOAD instruction from
697 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
698 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
703 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
705 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
706 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
708 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
709 DAG.getSrcValue(NULL));
714 case ISD::TokenFactor:
715 if (Node->getNumOperands() == 2) {
716 Tmp1 = LegalizeOp(Node->getOperand(0));
717 Tmp2 = LegalizeOp(Node->getOperand(1));
718 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
719 } else if (Node->getNumOperands() == 3) {
720 Tmp1 = LegalizeOp(Node->getOperand(0));
721 Tmp2 = LegalizeOp(Node->getOperand(1));
722 Tmp3 = LegalizeOp(Node->getOperand(2));
723 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
725 std::vector<SDOperand> Ops;
726 // Legalize the operands.
727 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
728 Ops.push_back(LegalizeOp(Node->getOperand(i)));
729 Result = DAG.UpdateNodeOperands(Result, Ops);
733 case ISD::BUILD_VECTOR:
734 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
735 default: assert(0 && "This action is not supported yet!");
736 case TargetLowering::Custom:
737 Tmp3 = TLI.LowerOperation(Result, DAG);
743 case TargetLowering::Expand:
744 Result = ExpandBUILD_VECTOR(Result.Val);
748 case ISD::INSERT_VECTOR_ELT:
749 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
750 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
751 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
752 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
754 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
755 Node->getValueType(0))) {
756 default: assert(0 && "This action is not supported yet!");
757 case TargetLowering::Legal:
759 case TargetLowering::Custom:
760 Tmp3 = TLI.LowerOperation(Result, DAG);
766 case TargetLowering::Expand: {
767 // If the target doesn't support this, we have to spill the input vector
768 // to a temporary stack slot, update the element, then reload it. This is
769 // badness. We could also load the value into a vector register (either
770 // with a "move to register" or "extload into register" instruction, then
771 // permute it into place, if the idx is a constant and if the idx is
772 // supported by the target.
773 assert(0 && "INSERT_VECTOR_ELT expand not supported yet!");
778 case ISD::SCALAR_TO_VECTOR:
779 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
780 Result = DAG.UpdateNodeOperands(Result, Tmp1);
781 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
782 Node->getValueType(0))) {
783 default: assert(0 && "This action is not supported yet!");
784 case TargetLowering::Legal:
786 case TargetLowering::Custom:
787 Tmp3 = TLI.LowerOperation(Result, DAG);
793 case TargetLowering::Expand: {
794 // If the target doesn't support this, store the value to a temporary
795 // stack slot, then EXTLOAD the vector back out.
796 // TODO: If a target doesn't support this, create a stack slot for the
797 // whole vector, then store into it, then load the whole vector.
799 CreateStackTemporary(Node->getOperand(0).getValueType());
800 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
801 Node->getOperand(0), StackPtr,
802 DAG.getSrcValue(NULL));
803 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), Ch, StackPtr,
804 DAG.getSrcValue(NULL),
805 Node->getOperand(0).getValueType());
810 case ISD::VECTOR_SHUFFLE:
811 assert(TLI.isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
812 "vector shuffle should not be created if not legal!");
813 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
814 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
815 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
817 // Allow targets to custom lower the SHUFFLEs they support.
818 if (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, Result.getValueType())
819 == TargetLowering::Custom) {
820 Tmp1 = TLI.LowerOperation(Result, DAG);
821 if (Tmp1.Val) Result = Tmp1;
825 case ISD::EXTRACT_VECTOR_ELT:
826 Tmp1 = LegalizeOp(Node->getOperand(0));
827 Tmp2 = LegalizeOp(Node->getOperand(1));
828 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
830 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
831 Tmp1.getValueType())) {
832 default: assert(0 && "This action is not supported yet!");
833 case TargetLowering::Legal:
835 case TargetLowering::Custom:
836 Tmp3 = TLI.LowerOperation(Result, DAG);
842 case TargetLowering::Expand: {
843 // If the target doesn't support this, store the value to a temporary
844 // stack slot, then LOAD the scalar element back out.
845 SDOperand StackPtr = CreateStackTemporary(Tmp1.getValueType());
846 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
847 Tmp1, StackPtr, DAG.getSrcValue(NULL));
849 // Add the offset to the index.
850 unsigned EltSize = MVT::getSizeInBits(Result.getValueType())/8;
851 Tmp2 = DAG.getNode(ISD::MUL, Tmp2.getValueType(), Tmp2,
852 DAG.getConstant(EltSize, Tmp2.getValueType()));
853 StackPtr = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, StackPtr);
855 Result = DAG.getLoad(Result.getValueType(), Ch, StackPtr,
856 DAG.getSrcValue(NULL));
862 case ISD::VEXTRACT_VECTOR_ELT: {
863 // We know that operand #0 is the Vec vector. If the index is a constant
864 // or if the invec is a supported hardware type, we can use it. Otherwise,
865 // lower to a store then an indexed load.
866 Tmp1 = Node->getOperand(0);
867 Tmp2 = LegalizeOp(Node->getOperand(1));
869 SDNode *InVal = Tmp1.Val;
870 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
871 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
873 // Figure out if there is a Packed type corresponding to this Vector
874 // type. If so, convert to the packed type.
875 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
876 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
877 // Turn this into a packed extract_vector_elt operation.
878 Tmp1 = PackVectorOp(Tmp1, TVT);
879 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Node->getValueType(0),
882 } else if (NumElems == 1) {
883 // This must be an access of the only element.
884 Result = PackVectorOp(Tmp1, EVT);
886 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Tmp2)) {
888 SplitVectorOp(Tmp1, Lo, Hi);
889 if (CIdx->getValue() < NumElems/2) {
893 Tmp2 = DAG.getConstant(CIdx->getValue() - NumElems/2,
894 Tmp2.getValueType());
897 // It's now an extract from the appropriate high or low part.
898 Result = LegalizeOp(DAG.UpdateNodeOperands(Result, Tmp1, Tmp2));
900 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
901 assert(0 && "unimp!");
906 case ISD::CALLSEQ_START: {
907 SDNode *CallEnd = FindCallEndFromCallStart(Node);
909 // Recursively Legalize all of the inputs of the call end that do not lead
910 // to this call start. This ensures that any libcalls that need be inserted
911 // are inserted *before* the CALLSEQ_START.
912 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
913 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node);
915 // Now that we legalized all of the inputs (which may have inserted
916 // libcalls) create the new CALLSEQ_START node.
917 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
919 // Merge in the last call, to ensure that this call start after the last
921 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
922 Tmp1 = LegalizeOp(Tmp1);
924 // Do not try to legalize the target-specific arguments (#1+).
925 if (Tmp1 != Node->getOperand(0)) {
926 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
928 Result = DAG.UpdateNodeOperands(Result, Ops);
931 // Remember that the CALLSEQ_START is legalized.
932 AddLegalizedOperand(Op.getValue(0), Result);
933 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
934 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
936 // Now that the callseq_start and all of the non-call nodes above this call
937 // sequence have been legalized, legalize the call itself. During this
938 // process, no libcalls can/will be inserted, guaranteeing that no calls
940 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
941 SDOperand InCallSEQ = LastCALLSEQ_END;
942 // Note that we are selecting this call!
943 LastCALLSEQ_END = SDOperand(CallEnd, 0);
944 IsLegalizingCall = true;
946 // Legalize the call, starting from the CALLSEQ_END.
947 LegalizeOp(LastCALLSEQ_END);
948 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
951 case ISD::CALLSEQ_END:
952 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
953 // will cause this node to be legalized as well as handling libcalls right.
954 if (LastCALLSEQ_END.Val != Node) {
955 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
956 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
957 assert(I != LegalizedNodes.end() &&
958 "Legalizing the call start should have legalized this node!");
962 // Otherwise, the call start has been legalized and everything is going
963 // according to plan. Just legalize ourselves normally here.
964 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
965 // Do not try to legalize the target-specific arguments (#1+), except for
966 // an optional flag input.
967 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
968 if (Tmp1 != Node->getOperand(0)) {
969 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
971 Result = DAG.UpdateNodeOperands(Result, Ops);
974 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
975 if (Tmp1 != Node->getOperand(0) ||
976 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
977 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
980 Result = DAG.UpdateNodeOperands(Result, Ops);
983 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
984 // This finishes up call legalization.
985 IsLegalizingCall = false;
987 // If the CALLSEQ_END node has a flag, remember that we legalized it.
988 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
989 if (Node->getNumValues() == 2)
990 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
991 return Result.getValue(Op.ResNo);
992 case ISD::DYNAMIC_STACKALLOC: {
993 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
994 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
995 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
996 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
998 Tmp1 = Result.getValue(0);
999 Tmp2 = Result.getValue(1);
1000 switch (TLI.getOperationAction(Node->getOpcode(),
1001 Node->getValueType(0))) {
1002 default: assert(0 && "This action is not supported yet!");
1003 case TargetLowering::Expand: {
1004 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1005 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1006 " not tell us which reg is the stack pointer!");
1007 SDOperand Chain = Tmp1.getOperand(0);
1008 SDOperand Size = Tmp2.getOperand(1);
1009 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1010 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1011 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1012 Tmp1 = LegalizeOp(Tmp1);
1013 Tmp2 = LegalizeOp(Tmp2);
1016 case TargetLowering::Custom:
1017 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1019 Tmp1 = LegalizeOp(Tmp3);
1020 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1023 case TargetLowering::Legal:
1026 // Since this op produce two values, make sure to remember that we
1027 // legalized both of them.
1028 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1029 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1030 return Op.ResNo ? Tmp2 : Tmp1;
1032 case ISD::INLINEASM:
1033 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize Chain.
1034 Tmp2 = Node->getOperand(Node->getNumOperands()-1);
1035 if (Tmp2.getValueType() == MVT::Flag) // Legalize Flag if it exists.
1036 Tmp2 = Tmp3 = SDOperand(0, 0);
1038 Tmp3 = LegalizeOp(Tmp2);
1040 if (Tmp1 != Node->getOperand(0) || Tmp2 != Tmp3) {
1041 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
1043 if (Tmp3.Val) Ops.back() = Tmp3;
1044 Result = DAG.UpdateNodeOperands(Result, Ops);
1047 // INLINE asm returns a chain and flag, make sure to add both to the map.
1048 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1049 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1050 return Result.getValue(Op.ResNo);
1052 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1053 // Ensure that libcalls are emitted before a branch.
1054 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1055 Tmp1 = LegalizeOp(Tmp1);
1056 LastCALLSEQ_END = DAG.getEntryNode();
1058 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1062 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1063 // Ensure that libcalls are emitted before a return.
1064 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1065 Tmp1 = LegalizeOp(Tmp1);
1066 LastCALLSEQ_END = DAG.getEntryNode();
1068 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1069 case Expand: assert(0 && "It's impossible to expand bools");
1071 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1074 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1078 // Basic block destination (Op#2) is always legal.
1079 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1081 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1082 default: assert(0 && "This action is not supported yet!");
1083 case TargetLowering::Legal: break;
1084 case TargetLowering::Custom:
1085 Tmp1 = TLI.LowerOperation(Result, DAG);
1086 if (Tmp1.Val) Result = Tmp1;
1088 case TargetLowering::Expand:
1089 // Expand brcond's setcc into its constituent parts and create a BR_CC
1091 if (Tmp2.getOpcode() == ISD::SETCC) {
1092 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1093 Tmp2.getOperand(0), Tmp2.getOperand(1),
1094 Node->getOperand(2));
1096 // Make sure the condition is either zero or one. It may have been
1097 // promoted from something else.
1098 unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType());
1099 if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1))
1100 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1102 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1103 DAG.getCondCode(ISD::SETNE), Tmp2,
1104 DAG.getConstant(0, Tmp2.getValueType()),
1105 Node->getOperand(2));
1111 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1112 // Ensure that libcalls are emitted before a branch.
1113 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1114 Tmp1 = LegalizeOp(Tmp1);
1115 LastCALLSEQ_END = DAG.getEntryNode();
1117 Tmp2 = Node->getOperand(2); // LHS
1118 Tmp3 = Node->getOperand(3); // RHS
1119 Tmp4 = Node->getOperand(1); // CC
1121 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1123 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1124 // the LHS is a legal SETCC itself. In this case, we need to compare
1125 // the result against zero to select between true and false values.
1126 if (Tmp3.Val == 0) {
1127 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1128 Tmp4 = DAG.getCondCode(ISD::SETNE);
1131 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1132 Node->getOperand(4));
1134 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1135 default: assert(0 && "Unexpected action for BR_CC!");
1136 case TargetLowering::Legal: break;
1137 case TargetLowering::Custom:
1138 Tmp4 = TLI.LowerOperation(Result, DAG);
1139 if (Tmp4.Val) Result = Tmp4;
1144 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1145 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1147 MVT::ValueType VT = Node->getValueType(0);
1148 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1149 Tmp2 = Result.getValue(0);
1150 Tmp3 = Result.getValue(1);
1152 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1153 default: assert(0 && "This action is not supported yet!");
1154 case TargetLowering::Legal: break;
1155 case TargetLowering::Custom:
1156 Tmp1 = TLI.LowerOperation(Tmp2, DAG);
1158 Tmp2 = LegalizeOp(Tmp1);
1159 Tmp3 = LegalizeOp(Tmp1.getValue(1));
1163 // Since loads produce two values, make sure to remember that we
1164 // legalized both of them.
1165 AddLegalizedOperand(SDOperand(Node, 0), Tmp2);
1166 AddLegalizedOperand(SDOperand(Node, 1), Tmp3);
1167 return Op.ResNo ? Tmp3 : Tmp2;
1171 case ISD::ZEXTLOAD: {
1172 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1173 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1175 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
1176 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
1177 default: assert(0 && "This action is not supported yet!");
1178 case TargetLowering::Promote:
1179 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
1180 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1181 DAG.getValueType(MVT::i8));
1182 Tmp1 = Result.getValue(0);
1183 Tmp2 = Result.getValue(1);
1185 case TargetLowering::Custom:
1188 case TargetLowering::Legal:
1189 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1190 Node->getOperand(3));
1191 Tmp1 = Result.getValue(0);
1192 Tmp2 = Result.getValue(1);
1195 Tmp3 = TLI.LowerOperation(Tmp3, DAG);
1197 Tmp1 = LegalizeOp(Tmp3);
1198 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1202 case TargetLowering::Expand:
1203 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1204 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1205 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
1206 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1207 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1208 Tmp2 = LegalizeOp(Load.getValue(1));
1211 assert(Node->getOpcode() != ISD::EXTLOAD &&
1212 "EXTLOAD should always be supported!");
1213 // Turn the unsupported load into an EXTLOAD followed by an explicit
1214 // zero/sign extend inreg.
1215 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1216 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1218 if (Node->getOpcode() == ISD::SEXTLOAD)
1219 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1220 Result, DAG.getValueType(SrcVT));
1222 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1223 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1224 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1227 // Since loads produce two values, make sure to remember that we legalized
1229 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1230 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1231 return Op.ResNo ? Tmp2 : Tmp1;
1233 case ISD::EXTRACT_ELEMENT: {
1234 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1235 switch (getTypeAction(OpTy)) {
1236 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1238 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1240 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1241 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1242 TLI.getShiftAmountTy()));
1243 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1246 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1247 Node->getOperand(0));
1251 // Get both the low and high parts.
1252 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1253 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1254 Result = Tmp2; // 1 -> Hi
1256 Result = Tmp1; // 0 -> Lo
1262 case ISD::CopyToReg:
1263 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1265 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1266 "Register type must be legal!");
1267 // Legalize the incoming value (must be a legal type).
1268 Tmp2 = LegalizeOp(Node->getOperand(2));
1269 if (Node->getNumValues() == 1) {
1270 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1272 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1273 if (Node->getNumOperands() == 4) {
1274 Tmp3 = LegalizeOp(Node->getOperand(3));
1275 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1278 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1281 // Since this produces two values, make sure to remember that we legalized
1283 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1284 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1290 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1292 // Ensure that libcalls are emitted before a return.
1293 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1294 Tmp1 = LegalizeOp(Tmp1);
1295 LastCALLSEQ_END = DAG.getEntryNode();
1297 switch (Node->getNumOperands()) {
1299 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1301 Tmp2 = LegalizeOp(Node->getOperand(1));
1302 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1306 ExpandOp(Node->getOperand(1), Lo, Hi);
1307 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
1311 Tmp2 = PromoteOp(Node->getOperand(1));
1312 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1313 Result = LegalizeOp(Result);
1318 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1320 default: { // ret <values>
1321 std::vector<SDOperand> NewValues;
1322 NewValues.push_back(Tmp1);
1323 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1324 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1326 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1330 ExpandOp(Node->getOperand(i), Lo, Hi);
1331 NewValues.push_back(Lo);
1332 NewValues.push_back(Hi);
1336 assert(0 && "Can't promote multiple return value yet!");
1339 if (NewValues.size() == Node->getNumOperands())
1340 Result = DAG.UpdateNodeOperands(Result, NewValues);
1342 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
1347 if (Result.getOpcode() == ISD::RET) {
1348 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1349 default: assert(0 && "This action is not supported yet!");
1350 case TargetLowering::Legal: break;
1351 case TargetLowering::Custom:
1352 Tmp1 = TLI.LowerOperation(Result, DAG);
1353 if (Tmp1.Val) Result = Tmp1;
1359 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1360 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1362 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1363 // FIXME: We shouldn't do this for TargetConstantFP's.
1364 // FIXME: move this to the DAG Combiner!
1365 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1366 if (CFP->getValueType(0) == MVT::f32) {
1367 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1369 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1370 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1372 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1373 Node->getOperand(3));
1377 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1379 Tmp3 = LegalizeOp(Node->getOperand(1));
1380 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1381 Node->getOperand(3));
1383 MVT::ValueType VT = Tmp3.getValueType();
1384 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1385 default: assert(0 && "This action is not supported yet!");
1386 case TargetLowering::Legal: break;
1387 case TargetLowering::Custom:
1388 Tmp1 = TLI.LowerOperation(Result, DAG);
1389 if (Tmp1.Val) Result = Tmp1;
1395 // Truncate the value and store the result.
1396 Tmp3 = PromoteOp(Node->getOperand(1));
1397 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1398 Node->getOperand(3),
1399 DAG.getValueType(Node->getOperand(1).getValueType()));
1403 unsigned IncrementSize = 0;
1406 // If this is a vector type, then we have to calculate the increment as
1407 // the product of the element size in bytes, and the number of elements
1408 // in the high half of the vector.
1409 if (Node->getOperand(1).getValueType() == MVT::Vector) {
1410 SDNode *InVal = Node->getOperand(1).Val;
1412 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1413 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1415 // Figure out if there is a Packed type corresponding to this Vector
1416 // type. If so, convert to the packed type.
1417 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1418 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1419 // Turn this into a normal store of the packed type.
1420 Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1421 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1422 Node->getOperand(3));
1424 } else if (NumElems == 1) {
1425 // Turn this into a normal store of the scalar type.
1426 Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1427 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1428 Node->getOperand(3));
1431 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1432 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1435 ExpandOp(Node->getOperand(1), Lo, Hi);
1436 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1439 if (!TLI.isLittleEndian())
1442 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1443 Node->getOperand(3));
1444 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1445 getIntPtrConstant(IncrementSize));
1446 assert(isTypeLegal(Tmp2.getValueType()) &&
1447 "Pointers must be legal!");
1448 // FIXME: This sets the srcvalue of both halves to be the same, which is
1450 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1451 Node->getOperand(3));
1452 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1458 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1459 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1461 case ISD::STACKSAVE:
1462 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1463 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1464 Tmp1 = Result.getValue(0);
1465 Tmp2 = Result.getValue(1);
1467 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1468 default: assert(0 && "This action is not supported yet!");
1469 case TargetLowering::Legal: break;
1470 case TargetLowering::Custom:
1471 Tmp3 = TLI.LowerOperation(Result, DAG);
1473 Tmp1 = LegalizeOp(Tmp3);
1474 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1477 case TargetLowering::Expand:
1478 // Expand to CopyFromReg if the target set
1479 // StackPointerRegisterToSaveRestore.
1480 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1481 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1482 Node->getValueType(0));
1483 Tmp2 = Tmp1.getValue(1);
1485 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1486 Tmp2 = Node->getOperand(0);
1491 // Since stacksave produce two values, make sure to remember that we
1492 // legalized both of them.
1493 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1494 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1495 return Op.ResNo ? Tmp2 : Tmp1;
1497 case ISD::STACKRESTORE:
1498 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1499 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1500 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1502 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1503 default: assert(0 && "This action is not supported yet!");
1504 case TargetLowering::Legal: break;
1505 case TargetLowering::Custom:
1506 Tmp1 = TLI.LowerOperation(Result, DAG);
1507 if (Tmp1.Val) Result = Tmp1;
1509 case TargetLowering::Expand:
1510 // Expand to CopyToReg if the target set
1511 // StackPointerRegisterToSaveRestore.
1512 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1513 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1521 case ISD::READCYCLECOUNTER:
1522 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1523 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1525 // Since rdcc produce two values, make sure to remember that we legalized
1527 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1528 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1531 case ISD::TRUNCSTORE: {
1532 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1533 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1535 assert(isTypeLegal(Node->getOperand(1).getValueType()) &&
1536 "Cannot handle illegal TRUNCSTORE yet!");
1537 Tmp2 = LegalizeOp(Node->getOperand(1));
1539 // The only promote case we handle is TRUNCSTORE:i1 X into
1540 // -> TRUNCSTORE:i8 (and X, 1)
1541 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1542 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1543 TargetLowering::Promote) {
1544 // Promote the bool to a mask then store.
1545 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1546 DAG.getConstant(1, Tmp2.getValueType()));
1547 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1548 Node->getOperand(3), DAG.getValueType(MVT::i8));
1550 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1551 Tmp3 != Node->getOperand(2)) {
1552 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
1553 Node->getOperand(3), Node->getOperand(4));
1556 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT();
1557 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) {
1558 default: assert(0 && "This action is not supported yet!");
1559 case TargetLowering::Legal: break;
1560 case TargetLowering::Custom:
1561 Tmp1 = TLI.LowerOperation(Result, DAG);
1562 if (Tmp1.Val) Result = Tmp1;
1568 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1569 case Expand: assert(0 && "It's impossible to expand bools");
1571 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1574 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1577 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1578 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1580 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1582 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1583 default: assert(0 && "This action is not supported yet!");
1584 case TargetLowering::Legal: break;
1585 case TargetLowering::Custom: {
1586 Tmp1 = TLI.LowerOperation(Result, DAG);
1587 if (Tmp1.Val) Result = Tmp1;
1590 case TargetLowering::Expand:
1591 if (Tmp1.getOpcode() == ISD::SETCC) {
1592 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1594 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1596 // Make sure the condition is either zero or one. It may have been
1597 // promoted from something else.
1598 unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType());
1599 if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1))
1600 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1601 Result = DAG.getSelectCC(Tmp1,
1602 DAG.getConstant(0, Tmp1.getValueType()),
1603 Tmp2, Tmp3, ISD::SETNE);
1606 case TargetLowering::Promote: {
1607 MVT::ValueType NVT =
1608 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1609 unsigned ExtOp, TruncOp;
1610 if (MVT::isInteger(Tmp2.getValueType())) {
1611 ExtOp = ISD::ANY_EXTEND;
1612 TruncOp = ISD::TRUNCATE;
1614 ExtOp = ISD::FP_EXTEND;
1615 TruncOp = ISD::FP_ROUND;
1617 // Promote each of the values to the new type.
1618 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1619 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1620 // Perform the larger operation, then round down.
1621 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1622 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1627 case ISD::SELECT_CC: {
1628 Tmp1 = Node->getOperand(0); // LHS
1629 Tmp2 = Node->getOperand(1); // RHS
1630 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1631 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1632 SDOperand CC = Node->getOperand(4);
1634 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
1636 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1637 // the LHS is a legal SETCC itself. In this case, we need to compare
1638 // the result against zero to select between true and false values.
1639 if (Tmp2.Val == 0) {
1640 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1641 CC = DAG.getCondCode(ISD::SETNE);
1643 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
1645 // Everything is legal, see if we should expand this op or something.
1646 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
1647 default: assert(0 && "This action is not supported yet!");
1648 case TargetLowering::Legal: break;
1649 case TargetLowering::Custom:
1650 Tmp1 = TLI.LowerOperation(Result, DAG);
1651 if (Tmp1.Val) Result = Tmp1;
1657 Tmp1 = Node->getOperand(0);
1658 Tmp2 = Node->getOperand(1);
1659 Tmp3 = Node->getOperand(2);
1660 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
1662 // If we had to Expand the SetCC operands into a SELECT node, then it may
1663 // not always be possible to return a true LHS & RHS. In this case, just
1664 // return the value we legalized, returned in the LHS
1665 if (Tmp2.Val == 0) {
1670 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
1671 default: assert(0 && "Cannot handle this action for SETCC yet!");
1672 case TargetLowering::Custom:
1675 case TargetLowering::Legal:
1676 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1678 Tmp3 = TLI.LowerOperation(Result, DAG);
1679 if (Tmp3.Val) Result = Tmp3;
1682 case TargetLowering::Promote: {
1683 // First step, figure out the appropriate operation to use.
1684 // Allow SETCC to not be supported for all legal data types
1685 // Mostly this targets FP
1686 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1687 MVT::ValueType OldVT = NewInTy;
1689 // Scan for the appropriate larger type to use.
1691 NewInTy = (MVT::ValueType)(NewInTy+1);
1693 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1694 "Fell off of the edge of the integer world");
1695 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1696 "Fell off of the edge of the floating point world");
1698 // If the target supports SETCC of this type, use it.
1699 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
1702 if (MVT::isInteger(NewInTy))
1703 assert(0 && "Cannot promote Legal Integer SETCC yet");
1705 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1706 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
1708 Tmp1 = LegalizeOp(Tmp1);
1709 Tmp2 = LegalizeOp(Tmp2);
1710 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1711 Result = LegalizeOp(Result);
1714 case TargetLowering::Expand:
1715 // Expand a setcc node into a select_cc of the same condition, lhs, and
1716 // rhs that selects between const 1 (true) and const 0 (false).
1717 MVT::ValueType VT = Node->getValueType(0);
1718 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1719 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1720 Node->getOperand(2));
1726 case ISD::MEMMOVE: {
1727 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1728 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1730 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1731 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1732 case Expand: assert(0 && "Cannot expand a byte!");
1734 Tmp3 = LegalizeOp(Node->getOperand(2));
1737 Tmp3 = PromoteOp(Node->getOperand(2));
1741 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1745 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1747 // Length is too big, just take the lo-part of the length.
1749 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
1753 Tmp4 = LegalizeOp(Node->getOperand(3));
1756 Tmp4 = PromoteOp(Node->getOperand(3));
1761 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
1762 case Expand: assert(0 && "Cannot expand this yet!");
1764 Tmp5 = LegalizeOp(Node->getOperand(4));
1767 Tmp5 = PromoteOp(Node->getOperand(4));
1771 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1772 default: assert(0 && "This action not implemented for this operation!");
1773 case TargetLowering::Custom:
1776 case TargetLowering::Legal:
1777 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
1779 Tmp1 = TLI.LowerOperation(Result, DAG);
1780 if (Tmp1.Val) Result = Tmp1;
1783 case TargetLowering::Expand: {
1784 // Otherwise, the target does not support this operation. Lower the
1785 // operation to an explicit libcall as appropriate.
1786 MVT::ValueType IntPtr = TLI.getPointerTy();
1787 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType();
1788 std::vector<std::pair<SDOperand, const Type*> > Args;
1790 const char *FnName = 0;
1791 if (Node->getOpcode() == ISD::MEMSET) {
1792 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1793 // Extend the (previously legalized) ubyte argument to be an int value
1795 if (Tmp3.getValueType() > MVT::i32)
1796 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
1798 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
1799 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
1800 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1803 } else if (Node->getOpcode() == ISD::MEMCPY ||
1804 Node->getOpcode() == ISD::MEMMOVE) {
1805 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1806 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
1807 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1808 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
1810 assert(0 && "Unknown op!");
1813 std::pair<SDOperand,SDOperand> CallResult =
1814 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
1815 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
1816 Result = CallResult.second;
1823 case ISD::SHL_PARTS:
1824 case ISD::SRA_PARTS:
1825 case ISD::SRL_PARTS: {
1826 std::vector<SDOperand> Ops;
1827 bool Changed = false;
1828 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1829 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1830 Changed |= Ops.back() != Node->getOperand(i);
1833 Result = DAG.UpdateNodeOperands(Result, Ops);
1835 switch (TLI.getOperationAction(Node->getOpcode(),
1836 Node->getValueType(0))) {
1837 default: assert(0 && "This action is not supported yet!");
1838 case TargetLowering::Legal: break;
1839 case TargetLowering::Custom:
1840 Tmp1 = TLI.LowerOperation(Result, DAG);
1842 SDOperand Tmp2, RetVal(0, 0);
1843 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1844 Tmp2 = LegalizeOp(Tmp1.getValue(i));
1845 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
1849 assert(RetVal.Val && "Illegal result number");
1855 // Since these produce multiple values, make sure to remember that we
1856 // legalized all of them.
1857 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1858 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
1859 return Result.getValue(Op.ResNo);
1880 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1881 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1882 case Expand: assert(0 && "Not possible");
1884 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
1887 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
1891 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1893 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1894 default: assert(0 && "Operation not supported");
1895 case TargetLowering::Legal: break;
1896 case TargetLowering::Custom:
1897 Tmp1 = TLI.LowerOperation(Result, DAG);
1898 if (Tmp1.Val) Result = Tmp1;
1903 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
1904 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1905 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1906 case Expand: assert(0 && "Not possible");
1908 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
1911 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
1915 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1917 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1918 default: assert(0 && "Operation not supported");
1919 case TargetLowering::Custom:
1920 Tmp1 = TLI.LowerOperation(Result, DAG);
1921 if (Tmp1.Val) Result = Tmp1;
1923 case TargetLowering::Legal: break;
1924 case TargetLowering::Expand:
1925 // If this target supports fabs/fneg natively, do this efficiently.
1926 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
1927 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
1928 // Get the sign bit of the RHS.
1929 MVT::ValueType IVT =
1930 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
1931 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
1932 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
1933 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
1934 // Get the absolute value of the result.
1935 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
1936 // Select between the nabs and abs value based on the sign bit of
1938 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
1939 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
1942 Result = LegalizeOp(Result);
1946 // Otherwise, do bitwise ops!
1948 // copysign -> copysignf/copysign libcall.
1950 if (Node->getValueType(0) == MVT::f32) {
1951 FnName = "copysignf";
1952 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type.
1953 Result = DAG.UpdateNodeOperands(Result, Tmp1,
1954 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2));
1956 FnName = "copysign";
1957 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type.
1958 Result = DAG.UpdateNodeOperands(Result, Tmp1,
1959 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2));
1962 Result = ExpandLibCall(FnName, Node, Dummy);
1969 Tmp1 = LegalizeOp(Node->getOperand(0));
1970 Tmp2 = LegalizeOp(Node->getOperand(1));
1971 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1972 // Since this produces two values, make sure to remember that we legalized
1974 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1975 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1980 Tmp1 = LegalizeOp(Node->getOperand(0));
1981 Tmp2 = LegalizeOp(Node->getOperand(1));
1982 Tmp3 = LegalizeOp(Node->getOperand(2));
1983 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1984 // Since this produces two values, make sure to remember that we legalized
1986 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1987 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1990 case ISD::BUILD_PAIR: {
1991 MVT::ValueType PairTy = Node->getValueType(0);
1992 // TODO: handle the case where the Lo and Hi operands are not of legal type
1993 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
1994 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
1995 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
1996 case TargetLowering::Promote:
1997 case TargetLowering::Custom:
1998 assert(0 && "Cannot promote/custom this yet!");
1999 case TargetLowering::Legal:
2000 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2001 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2003 case TargetLowering::Expand:
2004 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2005 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2006 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2007 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2008 TLI.getShiftAmountTy()));
2009 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2018 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2019 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2021 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2022 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2023 case TargetLowering::Custom:
2026 case TargetLowering::Legal:
2027 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2029 Tmp1 = TLI.LowerOperation(Result, DAG);
2030 if (Tmp1.Val) Result = Tmp1;
2033 case TargetLowering::Expand:
2034 if (MVT::isInteger(Node->getValueType(0))) {
2036 MVT::ValueType VT = Node->getValueType(0);
2037 unsigned Opc = Node->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
2038 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
2039 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2040 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2042 // Floating point mod -> fmod libcall.
2043 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
2045 Result = ExpandLibCall(FnName, Node, Dummy);
2051 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2052 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2054 MVT::ValueType VT = Node->getValueType(0);
2055 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2056 default: assert(0 && "This action is not supported yet!");
2057 case TargetLowering::Custom:
2060 case TargetLowering::Legal:
2061 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2062 Result = Result.getValue(0);
2063 Tmp1 = Result.getValue(1);
2066 Tmp2 = TLI.LowerOperation(Result, DAG);
2068 Result = LegalizeOp(Tmp2);
2069 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2073 case TargetLowering::Expand: {
2074 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2075 Node->getOperand(2));
2076 // Increment the pointer, VAList, to the next vaarg
2077 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2078 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2079 TLI.getPointerTy()));
2080 // Store the incremented VAList to the legalized pointer
2081 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2,
2082 Node->getOperand(2));
2083 // Load the actual argument out of the pointer VAList
2084 Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0));
2085 Tmp1 = LegalizeOp(Result.getValue(1));
2086 Result = LegalizeOp(Result);
2090 // Since VAARG produces two values, make sure to remember that we
2091 // legalized both of them.
2092 AddLegalizedOperand(SDOperand(Node, 0), Result);
2093 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2094 return Op.ResNo ? Tmp1 : Result;
2098 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2099 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2100 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2102 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2103 default: assert(0 && "This action is not supported yet!");
2104 case TargetLowering::Custom:
2107 case TargetLowering::Legal:
2108 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2109 Node->getOperand(3), Node->getOperand(4));
2111 Tmp1 = TLI.LowerOperation(Result, DAG);
2112 if (Tmp1.Val) Result = Tmp1;
2115 case TargetLowering::Expand:
2116 // This defaults to loading a pointer from the input and storing it to the
2117 // output, returning the chain.
2118 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, Node->getOperand(3));
2119 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp4.getValue(1), Tmp4, Tmp2,
2120 Node->getOperand(4));
2126 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2127 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2129 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2130 default: assert(0 && "This action is not supported yet!");
2131 case TargetLowering::Custom:
2134 case TargetLowering::Legal:
2135 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2137 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2138 if (Tmp1.Val) Result = Tmp1;
2141 case TargetLowering::Expand:
2142 Result = Tmp1; // Default to a no-op, return the chain
2148 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2149 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2151 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2153 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2154 default: assert(0 && "This action is not supported yet!");
2155 case TargetLowering::Legal: break;
2156 case TargetLowering::Custom:
2157 Tmp1 = TLI.LowerOperation(Result, DAG);
2158 if (Tmp1.Val) Result = Tmp1;
2165 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2166 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2168 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2169 "Cannot handle this yet!");
2170 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2174 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2175 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2176 case TargetLowering::Custom:
2177 assert(0 && "Cannot custom legalize this yet!");
2178 case TargetLowering::Legal:
2179 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2181 case TargetLowering::Promote: {
2182 MVT::ValueType OVT = Tmp1.getValueType();
2183 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2184 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2186 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2187 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2188 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2189 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2192 case TargetLowering::Expand:
2193 Result = ExpandBSWAP(Tmp1);
2201 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2202 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2203 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2204 case TargetLowering::Legal:
2205 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2207 case TargetLowering::Promote: {
2208 MVT::ValueType OVT = Tmp1.getValueType();
2209 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2211 // Zero extend the argument.
2212 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2213 // Perform the larger operation, then subtract if needed.
2214 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2215 switch (Node->getOpcode()) {
2220 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2221 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2222 DAG.getConstant(getSizeInBits(NVT), NVT),
2224 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2225 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2228 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2229 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2230 DAG.getConstant(getSizeInBits(NVT) -
2231 getSizeInBits(OVT), NVT));
2236 case TargetLowering::Expand:
2237 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2248 Tmp1 = LegalizeOp(Node->getOperand(0));
2249 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2250 case TargetLowering::Promote:
2251 case TargetLowering::Custom:
2254 case TargetLowering::Legal:
2255 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2257 Tmp1 = TLI.LowerOperation(Result, DAG);
2258 if (Tmp1.Val) Result = Tmp1;
2261 case TargetLowering::Expand:
2262 switch (Node->getOpcode()) {
2263 default: assert(0 && "Unreachable!");
2265 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2266 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2267 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2270 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2271 MVT::ValueType VT = Node->getValueType(0);
2272 Tmp2 = DAG.getConstantFP(0.0, VT);
2273 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2274 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2275 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2281 MVT::ValueType VT = Node->getValueType(0);
2282 const char *FnName = 0;
2283 switch(Node->getOpcode()) {
2284 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2285 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2286 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2287 default: assert(0 && "Unreachable!");
2290 Result = ExpandLibCall(FnName, Node, Dummy);
2298 case ISD::BIT_CONVERT:
2299 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2300 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2302 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2303 Node->getOperand(0).getValueType())) {
2304 default: assert(0 && "Unknown operation action!");
2305 case TargetLowering::Expand:
2306 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2308 case TargetLowering::Legal:
2309 Tmp1 = LegalizeOp(Node->getOperand(0));
2310 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2315 // Conversion operators. The source and destination have different types.
2316 case ISD::SINT_TO_FP:
2317 case ISD::UINT_TO_FP: {
2318 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2319 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2321 switch (TLI.getOperationAction(Node->getOpcode(),
2322 Node->getOperand(0).getValueType())) {
2323 default: assert(0 && "Unknown operation action!");
2324 case TargetLowering::Custom:
2327 case TargetLowering::Legal:
2328 Tmp1 = LegalizeOp(Node->getOperand(0));
2329 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2331 Tmp1 = TLI.LowerOperation(Result, DAG);
2332 if (Tmp1.Val) Result = Tmp1;
2335 case TargetLowering::Expand:
2336 Result = ExpandLegalINT_TO_FP(isSigned,
2337 LegalizeOp(Node->getOperand(0)),
2338 Node->getValueType(0));
2340 case TargetLowering::Promote:
2341 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2342 Node->getValueType(0),
2348 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2349 Node->getValueType(0), Node->getOperand(0));
2352 Tmp1 = PromoteOp(Node->getOperand(0));
2354 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2355 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2357 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2358 Node->getOperand(0).getValueType());
2360 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2361 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2367 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2369 Tmp1 = LegalizeOp(Node->getOperand(0));
2370 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2373 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2375 // Since the result is legal, we should just be able to truncate the low
2376 // part of the source.
2377 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2380 Result = PromoteOp(Node->getOperand(0));
2381 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2386 case ISD::FP_TO_SINT:
2387 case ISD::FP_TO_UINT:
2388 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2390 Tmp1 = LegalizeOp(Node->getOperand(0));
2392 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2393 default: assert(0 && "Unknown operation action!");
2394 case TargetLowering::Custom:
2397 case TargetLowering::Legal:
2398 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2400 Tmp1 = TLI.LowerOperation(Result, DAG);
2401 if (Tmp1.Val) Result = Tmp1;
2404 case TargetLowering::Promote:
2405 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2406 Node->getOpcode() == ISD::FP_TO_SINT);
2408 case TargetLowering::Expand:
2409 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2410 SDOperand True, False;
2411 MVT::ValueType VT = Node->getOperand(0).getValueType();
2412 MVT::ValueType NVT = Node->getValueType(0);
2413 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2414 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2415 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2416 Node->getOperand(0), Tmp2, ISD::SETLT);
2417 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2418 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2419 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2421 False = DAG.getNode(ISD::XOR, NVT, False,
2422 DAG.getConstant(1ULL << ShiftAmt, NVT));
2423 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2426 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2432 assert(0 && "Shouldn't need to expand other operators here!");
2434 Tmp1 = PromoteOp(Node->getOperand(0));
2435 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
2436 Result = LegalizeOp(Result);
2441 case ISD::ANY_EXTEND:
2442 case ISD::ZERO_EXTEND:
2443 case ISD::SIGN_EXTEND:
2444 case ISD::FP_EXTEND:
2446 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2447 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
2449 Tmp1 = LegalizeOp(Node->getOperand(0));
2450 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2453 switch (Node->getOpcode()) {
2454 case ISD::ANY_EXTEND:
2455 Tmp1 = PromoteOp(Node->getOperand(0));
2456 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
2458 case ISD::ZERO_EXTEND:
2459 Result = PromoteOp(Node->getOperand(0));
2460 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2461 Result = DAG.getZeroExtendInReg(Result,
2462 Node->getOperand(0).getValueType());
2464 case ISD::SIGN_EXTEND:
2465 Result = PromoteOp(Node->getOperand(0));
2466 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2467 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2469 DAG.getValueType(Node->getOperand(0).getValueType()));
2471 case ISD::FP_EXTEND:
2472 Result = PromoteOp(Node->getOperand(0));
2473 if (Result.getValueType() != Op.getValueType())
2474 // Dynamically dead while we have only 2 FP types.
2475 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2478 Result = PromoteOp(Node->getOperand(0));
2479 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2484 case ISD::FP_ROUND_INREG:
2485 case ISD::SIGN_EXTEND_INREG: {
2486 Tmp1 = LegalizeOp(Node->getOperand(0));
2487 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2489 // If this operation is not supported, convert it to a shl/shr or load/store
2491 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2492 default: assert(0 && "This action not supported for this op yet!");
2493 case TargetLowering::Legal:
2494 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2496 case TargetLowering::Expand:
2497 // If this is an integer extend and shifts are supported, do that.
2498 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2499 // NOTE: we could fall back on load/store here too for targets without
2500 // SAR. However, it is doubtful that any exist.
2501 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2502 MVT::getSizeInBits(ExtraVT);
2503 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2504 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2505 Node->getOperand(0), ShiftCst);
2506 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2508 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2509 // The only way we can lower this is to turn it into a STORETRUNC,
2510 // EXTLOAD pair, targetting a temporary location (a stack slot).
2512 // NOTE: there is a choice here between constantly creating new stack
2513 // slots and always reusing the same one. We currently always create
2514 // new ones, as reuse may inhibit scheduling.
2515 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2516 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
2517 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
2518 MachineFunction &MF = DAG.getMachineFunction();
2520 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2521 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2522 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2523 Node->getOperand(0), StackSlot,
2524 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2525 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2526 Result, StackSlot, DAG.getSrcValue(NULL),
2529 assert(0 && "Unknown op");
2537 // Make sure that the generated code is itself legal.
2539 Result = LegalizeOp(Result);
2541 // Note that LegalizeOp may be reentered even from single-use nodes, which
2542 // means that we always must cache transformed nodes.
2543 AddLegalizedOperand(Op, Result);
2547 /// PromoteOp - Given an operation that produces a value in an invalid type,
2548 /// promote it to compute the value into a larger type. The produced value will
2549 /// have the correct bits for the low portion of the register, but no guarantee
2550 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2551 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2552 MVT::ValueType VT = Op.getValueType();
2553 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2554 assert(getTypeAction(VT) == Promote &&
2555 "Caller should expand or legalize operands that are not promotable!");
2556 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2557 "Cannot promote to smaller type!");
2559 SDOperand Tmp1, Tmp2, Tmp3;
2561 SDNode *Node = Op.Val;
2563 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2564 if (I != PromotedNodes.end()) return I->second;
2566 switch (Node->getOpcode()) {
2567 case ISD::CopyFromReg:
2568 assert(0 && "CopyFromReg must be legal!");
2570 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2571 assert(0 && "Do not know how to promote this operator!");
2574 Result = DAG.getNode(ISD::UNDEF, NVT);
2578 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2580 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2581 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2583 case ISD::ConstantFP:
2584 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2585 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2589 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2590 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2591 Node->getOperand(1), Node->getOperand(2));
2595 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2597 Result = LegalizeOp(Node->getOperand(0));
2598 assert(Result.getValueType() >= NVT &&
2599 "This truncation doesn't make sense!");
2600 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2601 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2604 // The truncation is not required, because we don't guarantee anything
2605 // about high bits anyway.
2606 Result = PromoteOp(Node->getOperand(0));
2609 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2610 // Truncate the low part of the expanded value to the result type
2611 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2614 case ISD::SIGN_EXTEND:
2615 case ISD::ZERO_EXTEND:
2616 case ISD::ANY_EXTEND:
2617 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2618 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2620 // Input is legal? Just do extend all the way to the larger type.
2621 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2624 // Promote the reg if it's smaller.
2625 Result = PromoteOp(Node->getOperand(0));
2626 // The high bits are not guaranteed to be anything. Insert an extend.
2627 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2628 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2629 DAG.getValueType(Node->getOperand(0).getValueType()));
2630 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2631 Result = DAG.getZeroExtendInReg(Result,
2632 Node->getOperand(0).getValueType());
2636 case ISD::BIT_CONVERT:
2637 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2638 Result = PromoteOp(Result);
2641 case ISD::FP_EXTEND:
2642 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2644 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2645 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2646 case Promote: assert(0 && "Unreachable with 2 FP types!");
2648 // Input is legal? Do an FP_ROUND_INREG.
2649 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
2650 DAG.getValueType(VT));
2655 case ISD::SINT_TO_FP:
2656 case ISD::UINT_TO_FP:
2657 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2659 // No extra round required here.
2660 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2664 Result = PromoteOp(Node->getOperand(0));
2665 if (Node->getOpcode() == ISD::SINT_TO_FP)
2666 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2668 DAG.getValueType(Node->getOperand(0).getValueType()));
2670 Result = DAG.getZeroExtendInReg(Result,
2671 Node->getOperand(0).getValueType());
2672 // No extra round required here.
2673 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2676 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
2677 Node->getOperand(0));
2678 // Round if we cannot tolerate excess precision.
2679 if (NoExcessFPPrecision)
2680 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2681 DAG.getValueType(VT));
2686 case ISD::SIGN_EXTEND_INREG:
2687 Result = PromoteOp(Node->getOperand(0));
2688 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2689 Node->getOperand(1));
2691 case ISD::FP_TO_SINT:
2692 case ISD::FP_TO_UINT:
2693 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2695 Tmp1 = Node->getOperand(0);
2698 // The input result is prerounded, so we don't have to do anything
2700 Tmp1 = PromoteOp(Node->getOperand(0));
2703 assert(0 && "not implemented");
2705 // If we're promoting a UINT to a larger size, check to see if the new node
2706 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
2707 // we can use that instead. This allows us to generate better code for
2708 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
2709 // legal, such as PowerPC.
2710 if (Node->getOpcode() == ISD::FP_TO_UINT &&
2711 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
2712 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
2713 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
2714 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
2716 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2722 Tmp1 = PromoteOp(Node->getOperand(0));
2723 assert(Tmp1.getValueType() == NVT);
2724 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2725 // NOTE: we do not have to do any extra rounding here for
2726 // NoExcessFPPrecision, because we know the input will have the appropriate
2727 // precision, and these operations don't modify precision at all.
2733 Tmp1 = PromoteOp(Node->getOperand(0));
2734 assert(Tmp1.getValueType() == NVT);
2735 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2736 if (NoExcessFPPrecision)
2737 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2738 DAG.getValueType(VT));
2747 // The input may have strange things in the top bits of the registers, but
2748 // these operations don't care. They may have weird bits going out, but
2749 // that too is okay if they are integer operations.
2750 Tmp1 = PromoteOp(Node->getOperand(0));
2751 Tmp2 = PromoteOp(Node->getOperand(1));
2752 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2753 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2758 Tmp1 = PromoteOp(Node->getOperand(0));
2759 Tmp2 = PromoteOp(Node->getOperand(1));
2760 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2761 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2763 // Floating point operations will give excess precision that we may not be
2764 // able to tolerate. If we DO allow excess precision, just leave it,
2765 // otherwise excise it.
2766 // FIXME: Why would we need to round FP ops more than integer ones?
2767 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
2768 if (NoExcessFPPrecision)
2769 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2770 DAG.getValueType(VT));
2775 // These operators require that their input be sign extended.
2776 Tmp1 = PromoteOp(Node->getOperand(0));
2777 Tmp2 = PromoteOp(Node->getOperand(1));
2778 if (MVT::isInteger(NVT)) {
2779 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2780 DAG.getValueType(VT));
2781 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
2782 DAG.getValueType(VT));
2784 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2786 // Perform FP_ROUND: this is probably overly pessimistic.
2787 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
2788 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2789 DAG.getValueType(VT));
2793 case ISD::FCOPYSIGN:
2794 // These operators require that their input be fp extended.
2795 Tmp1 = PromoteOp(Node->getOperand(0));
2796 Tmp2 = PromoteOp(Node->getOperand(1));
2797 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2799 // Perform FP_ROUND: this is probably overly pessimistic.
2800 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
2801 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2802 DAG.getValueType(VT));
2807 // These operators require that their input be zero extended.
2808 Tmp1 = PromoteOp(Node->getOperand(0));
2809 Tmp2 = PromoteOp(Node->getOperand(1));
2810 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
2811 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2812 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
2813 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2817 Tmp1 = PromoteOp(Node->getOperand(0));
2818 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
2821 // The input value must be properly sign extended.
2822 Tmp1 = PromoteOp(Node->getOperand(0));
2823 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2824 DAG.getValueType(VT));
2825 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
2828 // The input value must be properly zero extended.
2829 Tmp1 = PromoteOp(Node->getOperand(0));
2830 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2831 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
2835 Tmp1 = Node->getOperand(0); // Get the chain.
2836 Tmp2 = Node->getOperand(1); // Get the pointer.
2837 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
2838 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
2839 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
2841 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2842 Node->getOperand(2));
2843 // Increment the pointer, VAList, to the next vaarg
2844 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2845 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2846 TLI.getPointerTy()));
2847 // Store the incremented VAList to the legalized pointer
2848 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2,
2849 Node->getOperand(2));
2850 // Load the actual argument out of the pointer VAList
2851 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList,
2852 DAG.getSrcValue(0), VT);
2854 // Remember that we legalized the chain.
2855 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
2859 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Node->getOperand(0),
2860 Node->getOperand(1), Node->getOperand(2), VT);
2861 // Remember that we legalized the chain.
2862 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
2867 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Node->getOperand(0),
2868 Node->getOperand(1), Node->getOperand(2),
2869 cast<VTSDNode>(Node->getOperand(3))->getVT());
2870 // Remember that we legalized the chain.
2871 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
2874 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
2875 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
2876 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
2878 case ISD::SELECT_CC:
2879 Tmp2 = PromoteOp(Node->getOperand(2)); // True
2880 Tmp3 = PromoteOp(Node->getOperand(3)); // False
2881 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
2882 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
2885 Tmp1 = Node->getOperand(0);
2886 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2887 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2888 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2889 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
2890 TLI.getShiftAmountTy()));
2895 // Zero extend the argument
2896 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
2897 // Perform the larger operation, then subtract if needed.
2898 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2899 switch(Node->getOpcode()) {
2904 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2905 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2906 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
2907 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2908 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
2911 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2912 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2913 DAG.getConstant(getSizeInBits(NVT) -
2914 getSizeInBits(VT), NVT));
2920 assert(Result.Val && "Didn't set a result!");
2922 // Make sure the result is itself legal.
2923 Result = LegalizeOp(Result);
2925 // Remember that we promoted this!
2926 AddPromotedOperand(Op, Result);
2930 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
2931 /// with condition CC on the current target. This usually involves legalizing
2932 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
2933 /// there may be no choice but to create a new SetCC node to represent the
2934 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
2935 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
2936 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
2939 SDOperand Tmp1, Tmp2, Result;
2941 switch (getTypeAction(LHS.getValueType())) {
2943 Tmp1 = LegalizeOp(LHS); // LHS
2944 Tmp2 = LegalizeOp(RHS); // RHS
2947 Tmp1 = PromoteOp(LHS); // LHS
2948 Tmp2 = PromoteOp(RHS); // RHS
2950 // If this is an FP compare, the operands have already been extended.
2951 if (MVT::isInteger(LHS.getValueType())) {
2952 MVT::ValueType VT = LHS.getValueType();
2953 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2955 // Otherwise, we have to insert explicit sign or zero extends. Note
2956 // that we could insert sign extends for ALL conditions, but zero extend
2957 // is cheaper on many machines (an AND instead of two shifts), so prefer
2959 switch (cast<CondCodeSDNode>(CC)->get()) {
2960 default: assert(0 && "Unknown integer comparison!");
2967 // ALL of these operations will work if we either sign or zero extend
2968 // the operands (including the unsigned comparisons!). Zero extend is
2969 // usually a simpler/cheaper operation, so prefer it.
2970 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2971 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
2977 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2978 DAG.getValueType(VT));
2979 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
2980 DAG.getValueType(VT));
2986 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
2987 ExpandOp(LHS, LHSLo, LHSHi);
2988 ExpandOp(RHS, RHSLo, RHSHi);
2989 switch (cast<CondCodeSDNode>(CC)->get()) {
2993 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
2994 if (RHSCST->isAllOnesValue()) {
2995 // Comparison to -1.
2996 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3001 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3002 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3003 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3004 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3007 // If this is a comparison of the sign bit, just look at the top part.
3009 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3010 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3011 CST->getValue() == 0) || // X < 0
3012 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3013 CST->isAllOnesValue())) { // X > -1
3019 // FIXME: This generated code sucks.
3020 ISD::CondCode LowCC;
3021 switch (cast<CondCodeSDNode>(CC)->get()) {
3022 default: assert(0 && "Unknown integer setcc!");
3024 case ISD::SETULT: LowCC = ISD::SETULT; break;
3026 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3028 case ISD::SETULE: LowCC = ISD::SETULE; break;
3030 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3033 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3034 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3035 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3037 // NOTE: on targets without efficient SELECT of bools, we can always use
3038 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3039 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3040 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3041 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3042 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3043 Result, Tmp1, Tmp2));
3052 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3053 /// The resultant code need not be legal. Note that SrcOp is the input operand
3054 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3055 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3057 // Create the stack frame object.
3058 SDOperand FIPtr = CreateStackTemporary(DestVT);
3060 // Emit a store to the stack slot.
3061 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3062 SrcOp, FIPtr, DAG.getSrcValue(NULL));
3063 // Result is a load from the stack slot.
3064 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0));
3067 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3068 /// support the operation, but do support the resultant packed vector type.
3069 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3071 // If the only non-undef value is the low element, turn this into a
3072 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3073 bool isOnlyLowElement = true;
3074 SDOperand SplatValue = Node->getOperand(0);
3075 for (SDNode::op_iterator I = Node->op_begin()+1, E = Node->op_end();
3077 if (I->getOpcode() != ISD::UNDEF)
3078 isOnlyLowElement = false;
3079 if (SplatValue != *I)
3080 SplatValue = SDOperand(0,0);
3083 if (isOnlyLowElement) {
3084 // If the low element is an undef too, then this whole things is an undef.
3085 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3086 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3087 // Otherwise, turn this into a scalar_to_vector node.
3088 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3089 Node->getOperand(0));
3092 if (SplatValue.Val) { // Splat of one value?
3093 // Build the shuffle constant vector: <0, 0, 0, 0>
3094 MVT::ValueType MaskVT =
3095 MVT::getIntVectorWithNumElements(Node->getNumOperands());
3096 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
3097 std::vector<SDOperand> ZeroVec(Node->getNumOperands(), Zero);
3098 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, ZeroVec);
3100 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3101 if (TLI.isShuffleLegal(Node->getValueType(0), SplatMask)) {
3102 // Get the splatted value into the low element of a vector register.
3103 SDOperand LowValVec =
3104 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3106 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3107 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3108 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3113 // If the elements are all constants, turn this into a load from the constant
3115 bool isConstant = true;
3116 for (SDNode::op_iterator I = Node->op_begin(), E = Node->op_end();
3118 if (!isa<ConstantFPSDNode>(I) && !isa<ConstantSDNode>(I) &&
3119 I->getOpcode() != ISD::UNDEF) {
3125 // Create a ConstantPacked, and put it in the constant pool.
3127 MVT::ValueType VT = Node->getValueType(0);
3129 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3130 std::vector<Constant*> CV;
3131 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3132 if (ConstantFPSDNode *V =
3133 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3134 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3135 } else if (ConstantSDNode *V =
3136 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3137 CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
3139 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3140 CV.push_back(UndefValue::get(OpNTy));
3143 Constant *CP = ConstantPacked::get(CV);
3144 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3145 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
3146 DAG.getSrcValue(NULL));
3149 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
3150 // aligned object on the stack, store each element into it, then load
3151 // the result as a vector.
3152 MVT::ValueType VT = Node->getValueType(0);
3153 // Create the stack frame object.
3154 SDOperand FIPtr = CreateStackTemporary(VT);
3156 // Emit a store of each element to the stack slot.
3157 std::vector<SDOperand> Stores;
3158 unsigned TypeByteSize =
3159 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
3160 unsigned VectorSize = MVT::getSizeInBits(VT)/8;
3161 // Store (in the right endianness) the elements to memory.
3162 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3163 // Ignore undef elements.
3164 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3166 unsigned Offset = TypeByteSize*i;
3168 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
3169 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
3171 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3172 Node->getOperand(i), Idx,
3173 DAG.getSrcValue(NULL)));
3176 SDOperand StoreChain;
3177 if (!Stores.empty()) // Not all undef elements?
3178 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
3180 StoreChain = DAG.getEntryNode();
3182 // Result is a load from the stack slot.
3183 return DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0));
3186 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
3187 /// specified value type.
3188 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
3189 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3190 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
3191 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
3192 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
3195 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
3196 SDOperand Op, SDOperand Amt,
3197 SDOperand &Lo, SDOperand &Hi) {
3198 // Expand the subcomponents.
3199 SDOperand LHSL, LHSH;
3200 ExpandOp(Op, LHSL, LHSH);
3202 std::vector<SDOperand> Ops;
3203 Ops.push_back(LHSL);
3204 Ops.push_back(LHSH);
3206 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
3207 Lo = DAG.getNode(NodeOp, VTs, Ops);
3208 Hi = Lo.getValue(1);
3212 /// ExpandShift - Try to find a clever way to expand this shift operation out to
3213 /// smaller elements. If we can't find a way that is more efficient than a
3214 /// libcall on this target, return false. Otherwise, return true with the
3215 /// low-parts expanded into Lo and Hi.
3216 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3217 SDOperand &Lo, SDOperand &Hi) {
3218 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3219 "This is not a shift!");
3221 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3222 SDOperand ShAmt = LegalizeOp(Amt);
3223 MVT::ValueType ShTy = ShAmt.getValueType();
3224 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3225 unsigned NVTBits = MVT::getSizeInBits(NVT);
3227 // Handle the case when Amt is an immediate. Other cases are currently broken
3228 // and are disabled.
3229 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3230 unsigned Cst = CN->getValue();
3231 // Expand the incoming operand to be shifted, so that we have its parts
3233 ExpandOp(Op, InL, InH);
3237 Lo = DAG.getConstant(0, NVT);
3238 Hi = DAG.getConstant(0, NVT);
3239 } else if (Cst > NVTBits) {
3240 Lo = DAG.getConstant(0, NVT);
3241 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
3242 } else if (Cst == NVTBits) {
3243 Lo = DAG.getConstant(0, NVT);
3246 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
3247 Hi = DAG.getNode(ISD::OR, NVT,
3248 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
3249 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
3254 Lo = DAG.getConstant(0, NVT);
3255 Hi = DAG.getConstant(0, NVT);
3256 } else if (Cst > NVTBits) {
3257 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
3258 Hi = DAG.getConstant(0, NVT);
3259 } else if (Cst == NVTBits) {
3261 Hi = DAG.getConstant(0, NVT);
3263 Lo = DAG.getNode(ISD::OR, NVT,
3264 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3265 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3266 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
3271 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
3272 DAG.getConstant(NVTBits-1, ShTy));
3273 } else if (Cst > NVTBits) {
3274 Lo = DAG.getNode(ISD::SRA, NVT, InH,
3275 DAG.getConstant(Cst-NVTBits, ShTy));
3276 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3277 DAG.getConstant(NVTBits-1, ShTy));
3278 } else if (Cst == NVTBits) {
3280 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3281 DAG.getConstant(NVTBits-1, ShTy));
3283 Lo = DAG.getNode(ISD::OR, NVT,
3284 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3285 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3286 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
3295 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
3296 // does not fit into a register, return the lo part and set the hi part to the
3297 // by-reg argument. If it does fit into a single register, return the result
3298 // and leave the Hi part unset.
3299 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3301 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
3302 // The input chain to this libcall is the entry node of the function.
3303 // Legalizing the call will automatically add the previous call to the
3305 SDOperand InChain = DAG.getEntryNode();
3307 TargetLowering::ArgListTy Args;
3308 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3309 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3310 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3311 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3313 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3315 // Splice the libcall in wherever FindInputOutputChains tells us to.
3316 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3317 std::pair<SDOperand,SDOperand> CallInfo =
3318 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3321 // Legalize the call sequence, starting with the chain. This will advance
3322 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
3323 // was added by LowerCallTo (guaranteeing proper serialization of calls).
3324 LegalizeOp(CallInfo.second);
3326 switch (getTypeAction(CallInfo.first.getValueType())) {
3327 default: assert(0 && "Unknown thing");
3329 Result = CallInfo.first;
3332 ExpandOp(CallInfo.first, Result, Hi);
3339 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3340 /// destination type is legal.
3341 SDOperand SelectionDAGLegalize::
3342 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3343 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3344 assert(getTypeAction(Source.getValueType()) == Expand &&
3345 "This is not an expansion!");
3346 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3349 assert(Source.getValueType() == MVT::i64 &&
3350 "This only works for 64-bit -> FP");
3351 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3352 // incoming integer is set. To handle this, we dynamically test to see if
3353 // it is set, and, if so, add a fudge factor.
3355 ExpandOp(Source, Lo, Hi);
3357 // If this is unsigned, and not supported, first perform the conversion to
3358 // signed, then adjust the result if the sign bit is set.
3359 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3360 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3362 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3363 DAG.getConstant(0, Hi.getValueType()),
3365 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3366 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3367 SignSet, Four, Zero);
3368 uint64_t FF = 0x5f800000ULL;
3369 if (TLI.isLittleEndian()) FF <<= 32;
3370 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3372 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3373 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3374 SDOperand FudgeInReg;
3375 if (DestTy == MVT::f32)
3376 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3377 DAG.getSrcValue(NULL));
3379 assert(DestTy == MVT::f64 && "Unexpected conversion");
3380 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3381 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
3383 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3386 // Check to see if the target has a custom way to lower this. If so, use it.
3387 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3388 default: assert(0 && "This action not implemented for this operation!");
3389 case TargetLowering::Legal:
3390 case TargetLowering::Expand:
3391 break; // This case is handled below.
3392 case TargetLowering::Custom: {
3393 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3396 return LegalizeOp(NV);
3397 break; // The target decided this was legal after all
3401 // Expand the source, then glue it back together for the call. We must expand
3402 // the source in case it is shared (this pass of legalize must traverse it).
3403 SDOperand SrcLo, SrcHi;
3404 ExpandOp(Source, SrcLo, SrcHi);
3405 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
3407 const char *FnName = 0;
3408 if (DestTy == MVT::f32)
3409 FnName = "__floatdisf";
3411 assert(DestTy == MVT::f64 && "Unknown fp value type!");
3412 FnName = "__floatdidf";
3415 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
3416 SDOperand UnusedHiPart;
3417 return ExpandLibCall(FnName, Source.Val, UnusedHiPart);
3420 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
3421 /// INT_TO_FP operation of the specified operand when the target requests that
3422 /// we expand it. At this point, we know that the result and operand types are
3423 /// legal for the target.
3424 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
3426 MVT::ValueType DestVT) {
3427 if (Op0.getValueType() == MVT::i32) {
3428 // simple 32-bit [signed|unsigned] integer to float/double expansion
3430 // get the stack frame index of a 8 byte buffer
3431 MachineFunction &MF = DAG.getMachineFunction();
3432 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3433 // get address of 8 byte buffer
3434 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3435 // word offset constant for Hi/Lo address computation
3436 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
3437 // set up Hi and Lo (into buffer) address based on endian
3439 if (TLI.isLittleEndian()) {
3440 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
3444 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
3446 // if signed map to unsigned space
3447 SDOperand Op0Mapped;
3449 // constant used to invert sign bit (signed to unsigned mapping)
3450 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
3451 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
3455 // store the lo of the constructed double - based on integer input
3456 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3457 Op0Mapped, Lo, DAG.getSrcValue(NULL));
3458 // initial hi portion of constructed double
3459 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
3460 // store the hi of the constructed double - biased exponent
3461 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
3462 InitialHi, Hi, DAG.getSrcValue(NULL));
3463 // load the constructed double
3464 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
3465 DAG.getSrcValue(NULL));
3466 // FP constant to bias correct the final result
3467 SDOperand Bias = DAG.getConstantFP(isSigned ?
3468 BitsToDouble(0x4330000080000000ULL)
3469 : BitsToDouble(0x4330000000000000ULL),
3471 // subtract the bias
3472 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
3475 // handle final rounding
3476 if (DestVT == MVT::f64) {
3480 // if f32 then cast to f32
3481 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
3485 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
3486 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
3488 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
3489 DAG.getConstant(0, Op0.getValueType()),
3491 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3492 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3493 SignSet, Four, Zero);
3495 // If the sign bit of the integer is set, the large number will be treated
3496 // as a negative number. To counteract this, the dynamic code adds an
3497 // offset depending on the data type.
3499 switch (Op0.getValueType()) {
3500 default: assert(0 && "Unsupported integer type!");
3501 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
3502 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
3503 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
3504 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
3506 if (TLI.isLittleEndian()) FF <<= 32;
3507 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3509 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3510 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3511 SDOperand FudgeInReg;
3512 if (DestVT == MVT::f32)
3513 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3514 DAG.getSrcValue(NULL));
3516 assert(DestVT == MVT::f64 && "Unexpected conversion");
3517 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
3518 DAG.getEntryNode(), CPIdx,
3519 DAG.getSrcValue(NULL), MVT::f32));
3522 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
3525 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
3526 /// *INT_TO_FP operation of the specified operand when the target requests that
3527 /// we promote it. At this point, we know that the result and operand types are
3528 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
3529 /// operation that takes a larger input.
3530 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
3531 MVT::ValueType DestVT,
3533 // First step, figure out the appropriate *INT_TO_FP operation to use.
3534 MVT::ValueType NewInTy = LegalOp.getValueType();
3536 unsigned OpToUse = 0;
3538 // Scan for the appropriate larger type to use.
3540 NewInTy = (MVT::ValueType)(NewInTy+1);
3541 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
3543 // If the target supports SINT_TO_FP of this type, use it.
3544 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
3546 case TargetLowering::Legal:
3547 if (!TLI.isTypeLegal(NewInTy))
3548 break; // Can't use this datatype.
3550 case TargetLowering::Custom:
3551 OpToUse = ISD::SINT_TO_FP;
3555 if (isSigned) continue;
3557 // If the target supports UINT_TO_FP of this type, use it.
3558 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
3560 case TargetLowering::Legal:
3561 if (!TLI.isTypeLegal(NewInTy))
3562 break; // Can't use this datatype.
3564 case TargetLowering::Custom:
3565 OpToUse = ISD::UINT_TO_FP;
3570 // Otherwise, try a larger type.
3573 // Okay, we found the operation and type to use. Zero extend our input to the
3574 // desired type then run the operation on it.
3575 return DAG.getNode(OpToUse, DestVT,
3576 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
3580 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
3581 /// FP_TO_*INT operation of the specified operand when the target requests that
3582 /// we promote it. At this point, we know that the result and operand types are
3583 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
3584 /// operation that returns a larger result.
3585 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
3586 MVT::ValueType DestVT,
3588 // First step, figure out the appropriate FP_TO*INT operation to use.
3589 MVT::ValueType NewOutTy = DestVT;
3591 unsigned OpToUse = 0;
3593 // Scan for the appropriate larger type to use.
3595 NewOutTy = (MVT::ValueType)(NewOutTy+1);
3596 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
3598 // If the target supports FP_TO_SINT returning this type, use it.
3599 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
3601 case TargetLowering::Legal:
3602 if (!TLI.isTypeLegal(NewOutTy))
3603 break; // Can't use this datatype.
3605 case TargetLowering::Custom:
3606 OpToUse = ISD::FP_TO_SINT;
3611 // If the target supports FP_TO_UINT of this type, use it.
3612 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
3614 case TargetLowering::Legal:
3615 if (!TLI.isTypeLegal(NewOutTy))
3616 break; // Can't use this datatype.
3618 case TargetLowering::Custom:
3619 OpToUse = ISD::FP_TO_UINT;
3624 // Otherwise, try a larger type.
3627 // Okay, we found the operation and type to use. Truncate the result of the
3628 // extended FP_TO_*INT operation to the desired size.
3629 return DAG.getNode(ISD::TRUNCATE, DestVT,
3630 DAG.getNode(OpToUse, NewOutTy, LegalOp));
3633 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
3635 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
3636 MVT::ValueType VT = Op.getValueType();
3637 MVT::ValueType SHVT = TLI.getShiftAmountTy();
3638 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
3640 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
3642 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
3643 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
3644 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
3646 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
3647 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
3648 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
3649 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
3650 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
3651 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
3652 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
3653 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
3654 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
3656 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
3657 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
3658 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
3659 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
3660 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
3661 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
3662 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
3663 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
3664 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
3665 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
3666 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
3667 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
3668 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
3669 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
3670 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
3671 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
3672 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
3673 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
3674 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
3675 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
3676 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
3680 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
3682 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
3684 default: assert(0 && "Cannot expand this yet!");
3686 static const uint64_t mask[6] = {
3687 0x5555555555555555ULL, 0x3333333333333333ULL,
3688 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
3689 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
3691 MVT::ValueType VT = Op.getValueType();
3692 MVT::ValueType ShVT = TLI.getShiftAmountTy();
3693 unsigned len = getSizeInBits(VT);
3694 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
3695 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
3696 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
3697 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
3698 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
3699 DAG.getNode(ISD::AND, VT,
3700 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
3705 // for now, we do this:
3706 // x = x | (x >> 1);
3707 // x = x | (x >> 2);
3709 // x = x | (x >>16);
3710 // x = x | (x >>32); // for 64-bit input
3711 // return popcount(~x);
3713 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
3714 MVT::ValueType VT = Op.getValueType();
3715 MVT::ValueType ShVT = TLI.getShiftAmountTy();
3716 unsigned len = getSizeInBits(VT);
3717 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
3718 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
3719 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
3721 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
3722 return DAG.getNode(ISD::CTPOP, VT, Op);
3725 // for now, we use: { return popcount(~x & (x - 1)); }
3726 // unless the target has ctlz but not ctpop, in which case we use:
3727 // { return 32 - nlz(~x & (x-1)); }
3728 // see also http://www.hackersdelight.org/HDcode/ntz.cc
3729 MVT::ValueType VT = Op.getValueType();
3730 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
3731 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
3732 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
3733 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
3734 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
3735 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
3736 TLI.isOperationLegal(ISD::CTLZ, VT))
3737 return DAG.getNode(ISD::SUB, VT,
3738 DAG.getConstant(getSizeInBits(VT), VT),
3739 DAG.getNode(ISD::CTLZ, VT, Tmp3));
3740 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
3746 /// ExpandOp - Expand the specified SDOperand into its two component pieces
3747 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
3748 /// LegalizeNodes map is filled in for any results that are not expanded, the
3749 /// ExpandedNodes map is filled in for any results that are expanded, and the
3750 /// Lo/Hi values are returned.
3751 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
3752 MVT::ValueType VT = Op.getValueType();
3753 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3754 SDNode *Node = Op.Val;
3755 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
3756 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
3757 "Cannot expand FP values!");
3758 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
3759 "Cannot expand to FP value or to larger int value!");
3761 // See if we already expanded it.
3762 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
3763 = ExpandedNodes.find(Op);
3764 if (I != ExpandedNodes.end()) {
3765 Lo = I->second.first;
3766 Hi = I->second.second;
3770 switch (Node->getOpcode()) {
3771 case ISD::CopyFromReg:
3772 assert(0 && "CopyFromReg must be legal!");
3774 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
3775 assert(0 && "Do not know how to expand this operator!");
3778 Lo = DAG.getNode(ISD::UNDEF, NVT);
3779 Hi = DAG.getNode(ISD::UNDEF, NVT);
3781 case ISD::Constant: {
3782 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
3783 Lo = DAG.getConstant(Cst, NVT);
3784 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
3787 case ISD::BUILD_PAIR:
3788 // Return the operands.
3789 Lo = Node->getOperand(0);
3790 Hi = Node->getOperand(1);
3793 case ISD::SIGN_EXTEND_INREG:
3794 ExpandOp(Node->getOperand(0), Lo, Hi);
3795 // Sign extend the lo-part.
3796 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
3797 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
3798 TLI.getShiftAmountTy()));
3799 // sext_inreg the low part if needed.
3800 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
3804 ExpandOp(Node->getOperand(0), Lo, Hi);
3805 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
3806 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
3812 ExpandOp(Node->getOperand(0), Lo, Hi);
3813 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
3814 DAG.getNode(ISD::CTPOP, NVT, Lo),
3815 DAG.getNode(ISD::CTPOP, NVT, Hi));
3816 Hi = DAG.getConstant(0, NVT);
3820 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
3821 ExpandOp(Node->getOperand(0), Lo, Hi);
3822 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3823 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
3824 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
3826 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
3827 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
3829 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
3830 Hi = DAG.getConstant(0, NVT);
3835 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
3836 ExpandOp(Node->getOperand(0), Lo, Hi);
3837 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3838 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
3839 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
3841 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
3842 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
3844 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
3845 Hi = DAG.getConstant(0, NVT);
3850 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
3851 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
3852 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
3853 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
3855 // Remember that we legalized the chain.
3856 Hi = LegalizeOp(Hi);
3857 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
3858 if (!TLI.isLittleEndian())
3864 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
3865 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
3866 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3868 // Increment the pointer to the other half.
3869 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
3870 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3871 getIntPtrConstant(IncrementSize));
3872 // FIXME: This creates a bogus srcvalue!
3873 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3875 // Build a factor node to remember that this load is independent of the
3877 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3880 // Remember that we legalized the chain.
3881 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
3882 if (!TLI.isLittleEndian())
3888 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
3889 SDOperand LL, LH, RL, RH;
3890 ExpandOp(Node->getOperand(0), LL, LH);
3891 ExpandOp(Node->getOperand(1), RL, RH);
3892 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
3893 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
3897 SDOperand LL, LH, RL, RH;
3898 ExpandOp(Node->getOperand(1), LL, LH);
3899 ExpandOp(Node->getOperand(2), RL, RH);
3900 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
3901 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
3904 case ISD::SELECT_CC: {
3905 SDOperand TL, TH, FL, FH;
3906 ExpandOp(Node->getOperand(2), TL, TH);
3907 ExpandOp(Node->getOperand(3), FL, FH);
3908 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3909 Node->getOperand(1), TL, FL, Node->getOperand(4));
3910 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3911 Node->getOperand(1), TH, FH, Node->getOperand(4));
3914 case ISD::SEXTLOAD: {
3915 SDOperand Chain = Node->getOperand(0);
3916 SDOperand Ptr = Node->getOperand(1);
3917 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3920 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3922 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3925 // Remember that we legalized the chain.
3926 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
3928 // The high part is obtained by SRA'ing all but one of the bits of the lo
3930 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3931 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3932 TLI.getShiftAmountTy()));
3935 case ISD::ZEXTLOAD: {
3936 SDOperand Chain = Node->getOperand(0);
3937 SDOperand Ptr = Node->getOperand(1);
3938 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3941 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3943 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3946 // Remember that we legalized the chain.
3947 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
3949 // The high part is just a zero.
3950 Hi = DAG.getConstant(0, NVT);
3953 case ISD::EXTLOAD: {
3954 SDOperand Chain = Node->getOperand(0);
3955 SDOperand Ptr = Node->getOperand(1);
3956 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3959 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3961 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3964 // Remember that we legalized the chain.
3965 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
3967 // The high part is undefined.
3968 Hi = DAG.getNode(ISD::UNDEF, NVT);
3971 case ISD::ANY_EXTEND:
3972 // The low part is any extension of the input (which degenerates to a copy).
3973 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
3974 // The high part is undefined.
3975 Hi = DAG.getNode(ISD::UNDEF, NVT);
3977 case ISD::SIGN_EXTEND: {
3978 // The low part is just a sign extension of the input (which degenerates to
3980 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
3982 // The high part is obtained by SRA'ing all but one of the bits of the lo
3984 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3985 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
3986 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
3989 case ISD::ZERO_EXTEND:
3990 // The low part is just a zero extension of the input (which degenerates to
3992 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3994 // The high part is just a zero.
3995 Hi = DAG.getConstant(0, NVT);
3998 case ISD::BIT_CONVERT: {
3999 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0),
4000 Node->getOperand(0));
4001 ExpandOp(Tmp, Lo, Hi);
4005 case ISD::READCYCLECOUNTER:
4006 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
4007 TargetLowering::Custom &&
4008 "Must custom expand ReadCycleCounter");
4009 Lo = TLI.LowerOperation(Op, DAG);
4010 assert(Lo.Val && "Node must be custom expanded!");
4011 Hi = Lo.getValue(1);
4012 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
4013 LegalizeOp(Lo.getValue(2)));
4016 // These operators cannot be expanded directly, emit them as calls to
4017 // library functions.
4018 case ISD::FP_TO_SINT:
4019 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
4021 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4022 case Expand: assert(0 && "cannot expand FP!");
4023 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4024 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4027 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
4029 // Now that the custom expander is done, expand the result, which is still
4032 ExpandOp(Op, Lo, Hi);
4037 if (Node->getOperand(0).getValueType() == MVT::f32)
4038 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
4040 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
4043 case ISD::FP_TO_UINT:
4044 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
4046 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4047 case Expand: assert(0 && "cannot expand FP!");
4048 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4049 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4052 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
4054 // Now that the custom expander is done, expand the result.
4056 ExpandOp(Op, Lo, Hi);
4061 if (Node->getOperand(0).getValueType() == MVT::f32)
4062 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
4064 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
4068 // If the target wants custom lowering, do so.
4069 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4070 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
4071 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
4072 Op = TLI.LowerOperation(Op, DAG);
4074 // Now that the custom expander is done, expand the result, which is
4076 ExpandOp(Op, Lo, Hi);
4081 // If we can emit an efficient shift operation, do so now.
4082 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4085 // If this target supports SHL_PARTS, use it.
4086 TargetLowering::LegalizeAction Action =
4087 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
4088 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4089 Action == TargetLowering::Custom) {
4090 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4094 // Otherwise, emit a libcall.
4095 Lo = ExpandLibCall("__ashldi3", Node, Hi);
4100 // If the target wants custom lowering, do so.
4101 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4102 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
4103 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
4104 Op = TLI.LowerOperation(Op, DAG);
4106 // Now that the custom expander is done, expand the result, which is
4108 ExpandOp(Op, Lo, Hi);
4113 // If we can emit an efficient shift operation, do so now.
4114 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
4117 // If this target supports SRA_PARTS, use it.
4118 TargetLowering::LegalizeAction Action =
4119 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
4120 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4121 Action == TargetLowering::Custom) {
4122 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4126 // Otherwise, emit a libcall.
4127 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
4132 // If the target wants custom lowering, do so.
4133 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4134 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
4135 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
4136 Op = TLI.LowerOperation(Op, DAG);
4138 // Now that the custom expander is done, expand the result, which is
4140 ExpandOp(Op, Lo, Hi);
4145 // If we can emit an efficient shift operation, do so now.
4146 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4149 // If this target supports SRL_PARTS, use it.
4150 TargetLowering::LegalizeAction Action =
4151 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
4152 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4153 Action == TargetLowering::Custom) {
4154 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4158 // Otherwise, emit a libcall.
4159 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
4165 // If the target wants to custom expand this, let them.
4166 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
4167 TargetLowering::Custom) {
4168 Op = TLI.LowerOperation(Op, DAG);
4170 ExpandOp(Op, Lo, Hi);
4175 // Expand the subcomponents.
4176 SDOperand LHSL, LHSH, RHSL, RHSH;
4177 ExpandOp(Node->getOperand(0), LHSL, LHSH);
4178 ExpandOp(Node->getOperand(1), RHSL, RHSH);
4179 std::vector<MVT::ValueType> VTs;
4180 std::vector<SDOperand> LoOps, HiOps;
4181 VTs.push_back(LHSL.getValueType());
4182 VTs.push_back(MVT::Flag);
4183 LoOps.push_back(LHSL);
4184 LoOps.push_back(RHSL);
4185 HiOps.push_back(LHSH);
4186 HiOps.push_back(RHSH);
4187 if (Node->getOpcode() == ISD::ADD) {
4188 Lo = DAG.getNode(ISD::ADDC, VTs, LoOps);
4189 HiOps.push_back(Lo.getValue(1));
4190 Hi = DAG.getNode(ISD::ADDE, VTs, HiOps);
4192 Lo = DAG.getNode(ISD::SUBC, VTs, LoOps);
4193 HiOps.push_back(Lo.getValue(1));
4194 Hi = DAG.getNode(ISD::SUBE, VTs, HiOps);
4199 if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
4200 SDOperand LL, LH, RL, RH;
4201 ExpandOp(Node->getOperand(0), LL, LH);
4202 ExpandOp(Node->getOperand(1), RL, RH);
4203 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
4204 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
4205 // extended the sign bit of the low half through the upper half, and if so
4206 // emit a MULHS instead of the alternate sequence that is valid for any
4207 // i64 x i64 multiply.
4208 if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
4209 // is RH an extension of the sign bit of RL?
4210 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
4211 RH.getOperand(1).getOpcode() == ISD::Constant &&
4212 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
4213 // is LH an extension of the sign bit of LL?
4214 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
4215 LH.getOperand(1).getOpcode() == ISD::Constant &&
4216 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
4217 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
4219 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
4220 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
4221 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
4222 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
4223 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
4225 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4227 Lo = ExpandLibCall("__muldi3" , Node, Hi);
4231 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
4232 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
4233 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
4234 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
4237 // Make sure the resultant values have been legalized themselves, unless this
4238 // is a type that requires multi-step expansion.
4239 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
4240 Lo = LegalizeOp(Lo);
4241 Hi = LegalizeOp(Hi);
4244 // Remember in a map if the values will be reused later.
4246 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4247 assert(isNew && "Value already expanded?!?");
4250 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
4251 /// two smaller values of MVT::Vector type.
4252 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
4254 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
4255 SDNode *Node = Op.Val;
4256 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
4257 assert(NumElements > 1 && "Cannot split a single element vector!");
4258 unsigned NewNumElts = NumElements/2;
4259 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
4260 SDOperand TypeNode = *(Node->op_end()-1);
4262 // See if we already split it.
4263 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4264 = SplitNodes.find(Op);
4265 if (I != SplitNodes.end()) {
4266 Lo = I->second.first;
4267 Hi = I->second.second;
4271 switch (Node->getOpcode()) {
4272 default: assert(0 && "Unknown vector operation!");
4273 case ISD::VBUILD_VECTOR: {
4274 std::vector<SDOperand> LoOps(Node->op_begin(), Node->op_begin()+NewNumElts);
4275 LoOps.push_back(NewNumEltsNode);
4276 LoOps.push_back(TypeNode);
4277 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, LoOps);
4279 std::vector<SDOperand> HiOps(Node->op_begin()+NewNumElts, Node->op_end()-2);
4280 HiOps.push_back(NewNumEltsNode);
4281 HiOps.push_back(TypeNode);
4282 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, HiOps);
4293 SDOperand LL, LH, RL, RH;
4294 SplitVectorOp(Node->getOperand(0), LL, LH);
4295 SplitVectorOp(Node->getOperand(1), RL, RH);
4297 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
4298 NewNumEltsNode, TypeNode);
4299 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
4300 NewNumEltsNode, TypeNode);
4304 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4305 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4306 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4308 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4309 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
4310 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4311 getIntPtrConstant(IncrementSize));
4312 // FIXME: This creates a bogus srcvalue!
4313 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4315 // Build a factor node to remember that this load is independent of the
4317 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4320 // Remember that we legalized the chain.
4321 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4322 if (!TLI.isLittleEndian())
4328 // Remember in a map if the values will be reused later.
4330 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4331 assert(isNew && "Value already expanded?!?");
4335 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
4336 /// equivalent operation that returns a scalar (e.g. F32) or packed value
4337 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
4338 /// type for the result.
4339 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
4340 MVT::ValueType NewVT) {
4341 // FIXME: THIS IS A TEMPORARY HACK
4342 if (Op.getValueType() == NewVT) return Op;
4344 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
4345 SDNode *Node = Op.Val;
4347 // See if we already packed it.
4348 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
4349 if (I != PackedNodes.end()) return I->second;
4352 switch (Node->getOpcode()) {
4354 Node->dump(); std::cerr << "\n";
4355 assert(0 && "Unknown vector operation in PackVectorOp!");
4364 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
4366 PackVectorOp(Node->getOperand(0), NewVT),
4367 PackVectorOp(Node->getOperand(1), NewVT));
4370 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
4371 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
4373 Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(2));
4375 // Remember that we legalized the chain.
4376 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4379 case ISD::VBUILD_VECTOR:
4380 if (!MVT::isVector(NewVT)) {
4381 // Returning a scalar?
4382 Result = Node->getOperand(0);
4384 // Returning a BUILD_VECTOR?
4385 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()-2);
4386 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops);
4389 case ISD::VINSERT_VECTOR_ELT:
4390 if (!MVT::isVector(NewVT)) {
4391 // Returning a scalar? Must be the inserted element.
4392 Result = Node->getOperand(1);
4394 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
4395 PackVectorOp(Node->getOperand(0), NewVT),
4396 Node->getOperand(1), Node->getOperand(2));
4401 if (TLI.isTypeLegal(NewVT))
4402 Result = LegalizeOp(Result);
4403 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
4404 assert(isNew && "Value already packed?");
4409 // SelectionDAG::Legalize - This is the entry point for the file.
4411 void SelectionDAG::Legalize() {
4412 /// run - This is the main entry point to this class.
4414 SelectionDAGLegalize(*this).LegalizeDAG();