1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Target/TargetLowering.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/CommandLine.h"
30 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
31 cl::desc("Pop up a window to show dags before legalize"));
33 static const bool ViewLegalizeDAGs = 0;
36 //===----------------------------------------------------------------------===//
37 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
38 /// hacks on it until the target machine can handle it. This involves
39 /// eliminating value sizes the machine cannot handle (promoting small sizes to
40 /// large sizes or splitting up large values into small values) as well as
41 /// eliminating operations the machine cannot handle.
43 /// This code also does a small amount of optimization and recognition of idioms
44 /// as part of its processing. For example, if a target does not support a
45 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
46 /// will attempt merge setcc and brc instructions into brcc's.
49 class SelectionDAGLegalize {
53 // Libcall insertion helpers.
55 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
56 /// legalized. We use this to ensure that calls are properly serialized
57 /// against each other, including inserted libcalls.
58 SDOperand LastCALLSEQ_END;
60 /// IsLegalizingCall - This member is used *only* for purposes of providing
61 /// helpful assertions that a libcall isn't created while another call is
62 /// being legalized (which could lead to non-serialized call sequences).
63 bool IsLegalizingCall;
66 Legal, // The target natively supports this operation.
67 Promote, // This operation should be executed in a larger type.
68 Expand, // Try to expand this to other ops, otherwise use a libcall.
71 /// ValueTypeActions - This is a bitvector that contains two bits for each
72 /// value type, where the two bits correspond to the LegalizeAction enum.
73 /// This can be queried with "getTypeAction(VT)".
74 TargetLowering::ValueTypeActionImpl ValueTypeActions;
76 /// LegalizedNodes - For nodes that are of legal width, and that have more
77 /// than one use, this map indicates what regularized operand to use. This
78 /// allows us to avoid legalizing the same thing more than once.
79 std::map<SDOperand, SDOperand> LegalizedNodes;
81 /// PromotedNodes - For nodes that are below legal width, and that have more
82 /// than one use, this map indicates what promoted value to use. This allows
83 /// us to avoid promoting the same thing more than once.
84 std::map<SDOperand, SDOperand> PromotedNodes;
86 /// ExpandedNodes - For nodes that need to be expanded this map indicates
87 /// which which operands are the expanded version of the input. This allows
88 /// us to avoid expanding the same node more than once.
89 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
91 /// SplitNodes - For vector nodes that need to be split, this map indicates
92 /// which which operands are the split version of the input. This allows us
93 /// to avoid splitting the same node more than once.
94 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
96 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
97 /// concrete packed types, this contains the mapping of ones we have already
98 /// processed to the result.
99 std::map<SDOperand, SDOperand> PackedNodes;
101 void AddLegalizedOperand(SDOperand From, SDOperand To) {
102 LegalizedNodes.insert(std::make_pair(From, To));
103 // If someone requests legalization of the new node, return itself.
105 LegalizedNodes.insert(std::make_pair(To, To));
107 void AddPromotedOperand(SDOperand From, SDOperand To) {
108 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
109 assert(isNew && "Got into the map somehow?");
110 // If someone requests legalization of the new node, return itself.
111 LegalizedNodes.insert(std::make_pair(To, To));
116 SelectionDAGLegalize(SelectionDAG &DAG);
118 /// getTypeAction - Return how we should legalize values of this type, either
119 /// it is already legal or we need to expand it into multiple registers of
120 /// smaller integer type, or we need to promote it to a larger type.
121 LegalizeAction getTypeAction(MVT::ValueType VT) const {
122 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
125 /// isTypeLegal - Return true if this type is legal on this target.
127 bool isTypeLegal(MVT::ValueType VT) const {
128 return getTypeAction(VT) == Legal;
134 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
135 /// appropriate for its type.
136 void HandleOp(SDOperand Op);
138 /// LegalizeOp - We know that the specified value has a legal type.
139 /// Recursively ensure that the operands have legal types, then return the
141 SDOperand LegalizeOp(SDOperand O);
143 /// PromoteOp - Given an operation that produces a value in an invalid type,
144 /// promote it to compute the value into a larger type. The produced value
145 /// will have the correct bits for the low portion of the register, but no
146 /// guarantee is made about the top bits: it may be zero, sign-extended, or
148 SDOperand PromoteOp(SDOperand O);
150 /// ExpandOp - Expand the specified SDOperand into its two component pieces
151 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
152 /// the LegalizeNodes map is filled in for any results that are not expanded,
153 /// the ExpandedNodes map is filled in for any results that are expanded, and
154 /// the Lo/Hi values are returned. This applies to integer types and Vector
156 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
158 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
159 /// two smaller values of MVT::Vector type.
160 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
162 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
163 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
164 /// this is called, we know that PackedVT is the right type for the result and
165 /// we know that this type is legal for the target.
166 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
168 /// isShuffleLegal - Return true if a vector shuffle is legal with the
169 /// specified mask and type. Targets can specify exactly which masks they
170 /// support and the code generator is tasked with not creating illegal masks.
172 /// Note that this will also return true for shuffles that are promoted to a
175 /// If this is a legal shuffle, this method returns the (possibly promoted)
176 /// build_vector Mask. If it's not a legal shuffle, it returns null.
177 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
179 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest);
181 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
183 SDOperand CreateStackTemporary(MVT::ValueType VT);
185 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
187 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
190 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
191 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
192 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
193 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
195 MVT::ValueType DestVT);
196 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
198 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
201 SDOperand ExpandBSWAP(SDOperand Op);
202 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
203 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
204 SDOperand &Lo, SDOperand &Hi);
205 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
206 SDOperand &Lo, SDOperand &Hi);
208 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
209 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
211 SDOperand getIntPtrConstant(uint64_t Val) {
212 return DAG.getConstant(Val, TLI.getPointerTy());
217 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
218 /// specified mask and type. Targets can specify exactly which masks they
219 /// support and the code generator is tasked with not creating illegal masks.
221 /// Note that this will also return true for shuffles that are promoted to a
223 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
224 SDOperand Mask) const {
225 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
227 case TargetLowering::Legal:
228 case TargetLowering::Custom:
230 case TargetLowering::Promote: {
231 // If this is promoted to a different type, convert the shuffle mask and
232 // ask if it is legal in the promoted type!
233 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
235 // If we changed # elements, change the shuffle mask.
236 unsigned NumEltsGrowth =
237 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
238 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
239 if (NumEltsGrowth > 1) {
240 // Renumber the elements.
241 std::vector<SDOperand> Ops;
242 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
243 SDOperand InOp = Mask.getOperand(i);
244 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
245 if (InOp.getOpcode() == ISD::UNDEF)
246 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
248 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
249 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
253 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, Ops);
259 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
262 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
263 /// specified vector opcode.
264 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
266 default: assert(0 && "Don't know how to scalarize this opcode!");
267 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
268 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
269 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
270 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
271 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
272 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
273 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
274 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
278 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
279 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
280 ValueTypeActions(TLI.getValueTypeActions()) {
281 assert(MVT::LAST_VALUETYPE <= 32 &&
282 "Too many value types for ValueTypeActions to hold!");
285 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
286 /// not been visited yet and if all of its operands have already been visited.
287 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
288 std::map<SDNode*, unsigned> &Visited) {
289 if (++Visited[N] != N->getNumOperands())
290 return; // Haven't visited all operands yet
294 if (N->hasOneUse()) { // Tail recurse in common case.
295 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
299 // Now that we have N in, add anything that uses it if all of their operands
301 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
302 ComputeTopDownOrdering(*UI, Order, Visited);
306 void SelectionDAGLegalize::LegalizeDAG() {
307 LastCALLSEQ_END = DAG.getEntryNode();
308 IsLegalizingCall = false;
310 // The legalize process is inherently a bottom-up recursive process (users
311 // legalize their uses before themselves). Given infinite stack space, we
312 // could just start legalizing on the root and traverse the whole graph. In
313 // practice however, this causes us to run out of stack space on large basic
314 // blocks. To avoid this problem, compute an ordering of the nodes where each
315 // node is only legalized after all of its operands are legalized.
316 std::map<SDNode*, unsigned> Visited;
317 std::vector<SDNode*> Order;
319 // Compute ordering from all of the leaves in the graphs, those (like the
320 // entry node) that have no operands.
321 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
322 E = DAG.allnodes_end(); I != E; ++I) {
323 if (I->getNumOperands() == 0) {
325 ComputeTopDownOrdering(I, Order, Visited);
329 assert(Order.size() == Visited.size() &&
331 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
332 "Error: DAG is cyclic!");
335 for (unsigned i = 0, e = Order.size(); i != e; ++i)
336 HandleOp(SDOperand(Order[i], 0));
338 // Finally, it's possible the root changed. Get the new root.
339 SDOperand OldRoot = DAG.getRoot();
340 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
341 DAG.setRoot(LegalizedNodes[OldRoot]);
343 ExpandedNodes.clear();
344 LegalizedNodes.clear();
345 PromotedNodes.clear();
349 // Remove dead nodes now.
350 DAG.RemoveDeadNodes(OldRoot.Val);
354 /// FindCallEndFromCallStart - Given a chained node that is part of a call
355 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
356 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
357 if (Node->getOpcode() == ISD::CALLSEQ_END)
359 if (Node->use_empty())
360 return 0; // No CallSeqEnd
362 // The chain is usually at the end.
363 SDOperand TheChain(Node, Node->getNumValues()-1);
364 if (TheChain.getValueType() != MVT::Other) {
365 // Sometimes it's at the beginning.
366 TheChain = SDOperand(Node, 0);
367 if (TheChain.getValueType() != MVT::Other) {
368 // Otherwise, hunt for it.
369 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
370 if (Node->getValueType(i) == MVT::Other) {
371 TheChain = SDOperand(Node, i);
375 // Otherwise, we walked into a node without a chain.
376 if (TheChain.getValueType() != MVT::Other)
381 for (SDNode::use_iterator UI = Node->use_begin(),
382 E = Node->use_end(); UI != E; ++UI) {
384 // Make sure to only follow users of our token chain.
386 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
387 if (User->getOperand(i) == TheChain)
388 if (SDNode *Result = FindCallEndFromCallStart(User))
394 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
395 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
396 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
397 assert(Node && "Didn't find callseq_start for a call??");
398 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
400 assert(Node->getOperand(0).getValueType() == MVT::Other &&
401 "Node doesn't have a token chain argument!");
402 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
405 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
406 /// see if any uses can reach Dest. If no dest operands can get to dest,
407 /// legalize them, legalize ourself, and return false, otherwise, return true.
408 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N,
410 if (N == Dest) return true; // N certainly leads to Dest :)
412 // If the first result of this node has been already legalized, then it cannot
414 switch (getTypeAction(N->getValueType(0))) {
416 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
419 if (PromotedNodes.count(SDOperand(N, 0))) return false;
422 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
426 // Okay, this node has not already been legalized. Check and legalize all
427 // operands. If none lead to Dest, then we can legalize this node.
428 bool OperandsLeadToDest = false;
429 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
430 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
431 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest);
433 if (OperandsLeadToDest) return true;
435 // Okay, this node looks safe, legalize it and return false.
436 switch (getTypeAction(N->getValueType(0))) {
438 LegalizeOp(SDOperand(N, 0));
441 PromoteOp(SDOperand(N, 0));
445 ExpandOp(SDOperand(N, 0), X, Y);
452 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
453 /// appropriate for its type.
454 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
455 switch (getTypeAction(Op.getValueType())) {
456 default: assert(0 && "Bad type action!");
457 case Legal: LegalizeOp(Op); break;
458 case Promote: PromoteOp(Op); break;
460 if (Op.getValueType() != MVT::Vector) {
465 unsigned NumOps = N->getNumOperands();
466 unsigned NumElements =
467 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
468 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
469 MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
470 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
471 // In the common case, this is a legal vector type, convert it to the
472 // packed operation and type now.
473 PackVectorOp(Op, PackedVT);
474 } else if (NumElements == 1) {
475 // Otherwise, if this is a single element vector, convert it to a
477 PackVectorOp(Op, EVT);
479 // Otherwise, this is a multiple element vector that isn't supported.
480 // Split it in half and legalize both parts.
482 SplitVectorOp(Op, X, Y);
490 /// LegalizeOp - We know that the specified value has a legal type.
491 /// Recursively ensure that the operands have legal types, then return the
493 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
494 assert(isTypeLegal(Op.getValueType()) &&
495 "Caller should expand or promote operands that are not legal!");
496 SDNode *Node = Op.Val;
498 // If this operation defines any values that cannot be represented in a
499 // register on this target, make sure to expand or promote them.
500 if (Node->getNumValues() > 1) {
501 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
502 if (getTypeAction(Node->getValueType(i)) != Legal) {
503 HandleOp(Op.getValue(i));
504 assert(LegalizedNodes.count(Op) &&
505 "Handling didn't add legal operands!");
506 return LegalizedNodes[Op];
510 // Note that LegalizeOp may be reentered even from single-use nodes, which
511 // means that we always must cache transformed nodes.
512 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
513 if (I != LegalizedNodes.end()) return I->second;
515 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
516 SDOperand Result = Op;
517 bool isCustom = false;
519 switch (Node->getOpcode()) {
520 case ISD::FrameIndex:
521 case ISD::EntryToken:
523 case ISD::BasicBlock:
524 case ISD::TargetFrameIndex:
525 case ISD::TargetConstant:
526 case ISD::TargetConstantFP:
527 case ISD::TargetConstantPool:
528 case ISD::TargetGlobalAddress:
529 case ISD::TargetExternalSymbol:
534 // Primitives must all be legal.
535 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
536 "This must be legal!");
539 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
540 // If this is a target node, legalize it by legalizing the operands then
541 // passing it through.
542 std::vector<SDOperand> Ops;
543 bool Changed = false;
544 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
545 Ops.push_back(LegalizeOp(Node->getOperand(i)));
546 Changed = Changed || Node->getOperand(i) != Ops.back();
549 if (Node->getNumValues() == 1)
550 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops);
552 std::vector<MVT::ValueType> VTs(Node->value_begin(),
554 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
557 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
558 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
559 return Result.getValue(Op.ResNo);
561 // Otherwise this is an unhandled builtin node. splat.
562 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
563 assert(0 && "Do not know how to legalize this operator!");
565 case ISD::GlobalAddress:
566 case ISD::ExternalSymbol:
567 case ISD::ConstantPool: // Nothing to do.
568 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
569 default: assert(0 && "This action is not supported yet!");
570 case TargetLowering::Custom:
571 Tmp1 = TLI.LowerOperation(Op, DAG);
572 if (Tmp1.Val) Result = Tmp1;
573 // FALLTHROUGH if the target doesn't want to lower this op after all.
574 case TargetLowering::Legal:
578 case ISD::AssertSext:
579 case ISD::AssertZext:
580 Tmp1 = LegalizeOp(Node->getOperand(0));
581 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
583 case ISD::MERGE_VALUES:
584 // Legalize eliminates MERGE_VALUES nodes.
585 Result = Node->getOperand(Op.ResNo);
587 case ISD::CopyFromReg:
588 Tmp1 = LegalizeOp(Node->getOperand(0));
589 Result = Op.getValue(0);
590 if (Node->getNumValues() == 2) {
591 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
593 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
594 if (Node->getNumOperands() == 3) {
595 Tmp2 = LegalizeOp(Node->getOperand(2));
596 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
598 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
600 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
602 // Since CopyFromReg produces two values, make sure to remember that we
603 // legalized both of them.
604 AddLegalizedOperand(Op.getValue(0), Result);
605 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
606 return Result.getValue(Op.ResNo);
608 MVT::ValueType VT = Op.getValueType();
609 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
610 default: assert(0 && "This action is not supported yet!");
611 case TargetLowering::Expand:
612 if (MVT::isInteger(VT))
613 Result = DAG.getConstant(0, VT);
614 else if (MVT::isFloatingPoint(VT))
615 Result = DAG.getConstantFP(0, VT);
617 assert(0 && "Unknown value type!");
619 case TargetLowering::Legal:
625 case ISD::INTRINSIC_W_CHAIN:
626 case ISD::INTRINSIC_WO_CHAIN:
627 case ISD::INTRINSIC_VOID: {
628 std::vector<SDOperand> Ops;
629 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
630 Ops.push_back(LegalizeOp(Node->getOperand(i)));
631 Result = DAG.UpdateNodeOperands(Result, Ops);
633 // Allow the target to custom lower its intrinsics if it wants to.
634 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
635 TargetLowering::Custom) {
636 Tmp3 = TLI.LowerOperation(Result, DAG);
637 if (Tmp3.Val) Result = Tmp3;
640 if (Result.Val->getNumValues() == 1) break;
642 // Must have return value and chain result.
643 assert(Result.Val->getNumValues() == 2 &&
644 "Cannot return more than two values!");
646 // Since loads produce two values, make sure to remember that we
647 // legalized both of them.
648 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
649 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
650 return Result.getValue(Op.ResNo);
654 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
655 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
657 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
658 case TargetLowering::Promote:
659 default: assert(0 && "This action is not supported yet!");
660 case TargetLowering::Expand: {
661 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
662 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
663 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
665 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
666 const std::string &FName =
667 cast<StringSDNode>(Node->getOperand(3))->getValue();
668 const std::string &DirName =
669 cast<StringSDNode>(Node->getOperand(4))->getValue();
670 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
672 std::vector<SDOperand> Ops;
673 Ops.push_back(Tmp1); // chain
674 SDOperand LineOp = Node->getOperand(1);
675 SDOperand ColOp = Node->getOperand(2);
678 Ops.push_back(LineOp); // line #
679 Ops.push_back(ColOp); // col #
680 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
681 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
683 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
684 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
685 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
686 Ops.push_back(DAG.getConstant(ID, MVT::i32));
687 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops);
690 Result = Tmp1; // chain
694 case TargetLowering::Legal:
695 if (Tmp1 != Node->getOperand(0) ||
696 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
697 std::vector<SDOperand> Ops;
699 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
700 Ops.push_back(Node->getOperand(1)); // line # must be legal.
701 Ops.push_back(Node->getOperand(2)); // col # must be legal.
703 // Otherwise promote them.
704 Ops.push_back(PromoteOp(Node->getOperand(1)));
705 Ops.push_back(PromoteOp(Node->getOperand(2)));
707 Ops.push_back(Node->getOperand(3)); // filename must be legal.
708 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
709 Result = DAG.UpdateNodeOperands(Result, Ops);
716 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
717 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
718 default: assert(0 && "This action is not supported yet!");
719 case TargetLowering::Legal:
720 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
721 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
722 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
723 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
724 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
729 case ISD::DEBUG_LABEL:
730 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
731 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
732 default: assert(0 && "This action is not supported yet!");
733 case TargetLowering::Legal:
734 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
735 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
736 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
742 // We know we don't need to expand constants here, constants only have one
743 // value and we check that it is fine above.
745 // FIXME: Maybe we should handle things like targets that don't support full
746 // 32-bit immediates?
748 case ISD::ConstantFP: {
749 // Spill FP immediates to the constant pool if the target cannot directly
750 // codegen them. Targets often have some immediate values that can be
751 // efficiently generated into an FP register without a load. We explicitly
752 // leave these constants as ConstantFP nodes for the target to deal with.
753 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
755 // Check to see if this FP immediate is already legal.
756 bool isLegal = false;
757 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
758 E = TLI.legal_fpimm_end(); I != E; ++I)
759 if (CFP->isExactlyValue(*I)) {
764 // If this is a legal constant, turn it into a TargetConstantFP node.
766 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
770 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
771 default: assert(0 && "This action is not supported yet!");
772 case TargetLowering::Custom:
773 Tmp3 = TLI.LowerOperation(Result, DAG);
779 case TargetLowering::Expand:
780 // Otherwise we need to spill the constant to memory.
783 // If a FP immediate is precise when represented as a float and if the
784 // target can do an extending load from float to double, we put it into
785 // the constant pool as a float, even if it's is statically typed as a
787 MVT::ValueType VT = CFP->getValueType(0);
788 bool isDouble = VT == MVT::f64;
789 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
790 Type::FloatTy, CFP->getValue());
791 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
792 // Only do this if the target has a native EXTLOAD instruction from
794 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
795 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
800 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
802 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
803 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
805 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
806 DAG.getSrcValue(NULL));
811 case ISD::TokenFactor:
812 if (Node->getNumOperands() == 2) {
813 Tmp1 = LegalizeOp(Node->getOperand(0));
814 Tmp2 = LegalizeOp(Node->getOperand(1));
815 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
816 } else if (Node->getNumOperands() == 3) {
817 Tmp1 = LegalizeOp(Node->getOperand(0));
818 Tmp2 = LegalizeOp(Node->getOperand(1));
819 Tmp3 = LegalizeOp(Node->getOperand(2));
820 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
822 std::vector<SDOperand> Ops;
823 // Legalize the operands.
824 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
825 Ops.push_back(LegalizeOp(Node->getOperand(i)));
826 Result = DAG.UpdateNodeOperands(Result, Ops);
830 case ISD::FORMAL_ARGUMENTS:
831 // The only option for this is to custom lower it.
832 Result = TLI.LowerOperation(Result, DAG);
833 assert(Result.Val && "Target didn't custom lower ISD::FORMAL_ARGUMENTS!");
836 case ISD::BUILD_VECTOR:
837 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
838 default: assert(0 && "This action is not supported yet!");
839 case TargetLowering::Custom:
840 Tmp3 = TLI.LowerOperation(Result, DAG);
846 case TargetLowering::Expand:
847 Result = ExpandBUILD_VECTOR(Result.Val);
851 case ISD::INSERT_VECTOR_ELT:
852 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
853 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
854 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
855 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
857 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
858 Node->getValueType(0))) {
859 default: assert(0 && "This action is not supported yet!");
860 case TargetLowering::Legal:
862 case TargetLowering::Custom:
863 Tmp3 = TLI.LowerOperation(Result, DAG);
869 case TargetLowering::Expand: {
870 // If the insert index is a constant, codegen this as a scalar_to_vector,
871 // then a shuffle that inserts it into the right position in the vector.
872 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
873 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
874 Tmp1.getValueType(), Tmp2);
876 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
877 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
878 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT);
880 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
881 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
883 std::vector<SDOperand> ShufOps;
884 for (unsigned i = 0; i != NumElts; ++i) {
885 if (i != InsertPos->getValue())
886 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
888 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
890 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,ShufOps);
892 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
893 Tmp1, ScVec, ShufMask);
894 Result = LegalizeOp(Result);
898 // If the target doesn't support this, we have to spill the input vector
899 // to a temporary stack slot, update the element, then reload it. This is
900 // badness. We could also load the value into a vector register (either
901 // with a "move to register" or "extload into register" instruction, then
902 // permute it into place, if the idx is a constant and if the idx is
903 // supported by the target.
904 MVT::ValueType VT = Tmp1.getValueType();
905 MVT::ValueType EltVT = Tmp2.getValueType();
906 MVT::ValueType IdxVT = Tmp3.getValueType();
907 MVT::ValueType PtrVT = TLI.getPointerTy();
908 SDOperand StackPtr = CreateStackTemporary(VT);
910 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
911 Tmp1, StackPtr, DAG.getSrcValue(NULL));
913 // Truncate or zero extend offset to target pointer type.
914 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
915 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
916 // Add the offset to the index.
917 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
918 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
919 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
920 // Store the scalar value.
921 Ch = DAG.getNode(ISD::STORE, MVT::Other, Ch,
922 Tmp2, StackPtr2, DAG.getSrcValue(NULL));
923 // Load the updated vector.
924 Result = DAG.getLoad(VT, Ch, StackPtr, DAG.getSrcValue(NULL));
929 case ISD::SCALAR_TO_VECTOR:
930 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
931 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
935 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
936 Result = DAG.UpdateNodeOperands(Result, Tmp1);
937 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
938 Node->getValueType(0))) {
939 default: assert(0 && "This action is not supported yet!");
940 case TargetLowering::Legal:
942 case TargetLowering::Custom:
943 Tmp3 = TLI.LowerOperation(Result, DAG);
949 case TargetLowering::Expand:
950 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
954 case ISD::VECTOR_SHUFFLE:
955 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
956 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
957 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
959 // Allow targets to custom lower the SHUFFLEs they support.
960 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
961 default: assert(0 && "Unknown operation action!");
962 case TargetLowering::Legal:
963 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
964 "vector shuffle should not be created if not legal!");
966 case TargetLowering::Custom:
967 Tmp3 = TLI.LowerOperation(Result, DAG);
973 case TargetLowering::Expand: {
974 MVT::ValueType VT = Node->getValueType(0);
975 MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
976 MVT::ValueType PtrVT = TLI.getPointerTy();
977 SDOperand Mask = Node->getOperand(2);
978 unsigned NumElems = Mask.getNumOperands();
979 std::vector<SDOperand> Ops;
980 for (unsigned i = 0; i != NumElems; ++i) {
981 SDOperand Arg = Mask.getOperand(i);
982 if (Arg.getOpcode() == ISD::UNDEF) {
983 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
985 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
986 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
988 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
989 DAG.getConstant(Idx, PtrVT)));
991 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
992 DAG.getConstant(Idx - NumElems, PtrVT)));
995 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, Ops);
998 case TargetLowering::Promote: {
999 // Change base type to a different vector type.
1000 MVT::ValueType OVT = Node->getValueType(0);
1001 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1003 // Cast the two input vectors.
1004 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1005 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1007 // Convert the shuffle mask to the right # elements.
1008 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1009 assert(Tmp3.Val && "Shuffle not legal?");
1010 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1011 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1017 case ISD::EXTRACT_VECTOR_ELT:
1018 Tmp1 = LegalizeOp(Node->getOperand(0));
1019 Tmp2 = LegalizeOp(Node->getOperand(1));
1020 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1022 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
1023 Tmp1.getValueType())) {
1024 default: assert(0 && "This action is not supported yet!");
1025 case TargetLowering::Legal:
1027 case TargetLowering::Custom:
1028 Tmp3 = TLI.LowerOperation(Result, DAG);
1034 case TargetLowering::Expand:
1035 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1040 case ISD::VEXTRACT_VECTOR_ELT:
1041 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
1044 case ISD::CALLSEQ_START: {
1045 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1047 // Recursively Legalize all of the inputs of the call end that do not lead
1048 // to this call start. This ensures that any libcalls that need be inserted
1049 // are inserted *before* the CALLSEQ_START.
1050 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1051 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node);
1053 // Now that we legalized all of the inputs (which may have inserted
1054 // libcalls) create the new CALLSEQ_START node.
1055 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1057 // Merge in the last call, to ensure that this call start after the last
1059 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1060 Tmp1 = LegalizeOp(Tmp1);
1062 // Do not try to legalize the target-specific arguments (#1+).
1063 if (Tmp1 != Node->getOperand(0)) {
1064 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
1066 Result = DAG.UpdateNodeOperands(Result, Ops);
1069 // Remember that the CALLSEQ_START is legalized.
1070 AddLegalizedOperand(Op.getValue(0), Result);
1071 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1072 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1074 // Now that the callseq_start and all of the non-call nodes above this call
1075 // sequence have been legalized, legalize the call itself. During this
1076 // process, no libcalls can/will be inserted, guaranteeing that no calls
1078 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1079 SDOperand InCallSEQ = LastCALLSEQ_END;
1080 // Note that we are selecting this call!
1081 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1082 IsLegalizingCall = true;
1084 // Legalize the call, starting from the CALLSEQ_END.
1085 LegalizeOp(LastCALLSEQ_END);
1086 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1089 case ISD::CALLSEQ_END:
1090 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1091 // will cause this node to be legalized as well as handling libcalls right.
1092 if (LastCALLSEQ_END.Val != Node) {
1093 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1094 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1095 assert(I != LegalizedNodes.end() &&
1096 "Legalizing the call start should have legalized this node!");
1100 // Otherwise, the call start has been legalized and everything is going
1101 // according to plan. Just legalize ourselves normally here.
1102 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1103 // Do not try to legalize the target-specific arguments (#1+), except for
1104 // an optional flag input.
1105 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1106 if (Tmp1 != Node->getOperand(0)) {
1107 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
1109 Result = DAG.UpdateNodeOperands(Result, Ops);
1112 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1113 if (Tmp1 != Node->getOperand(0) ||
1114 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1115 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
1118 Result = DAG.UpdateNodeOperands(Result, Ops);
1121 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1122 // This finishes up call legalization.
1123 IsLegalizingCall = false;
1125 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1126 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1127 if (Node->getNumValues() == 2)
1128 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1129 return Result.getValue(Op.ResNo);
1130 case ISD::DYNAMIC_STACKALLOC: {
1131 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1132 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1133 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1134 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1136 Tmp1 = Result.getValue(0);
1137 Tmp2 = Result.getValue(1);
1138 switch (TLI.getOperationAction(Node->getOpcode(),
1139 Node->getValueType(0))) {
1140 default: assert(0 && "This action is not supported yet!");
1141 case TargetLowering::Expand: {
1142 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1143 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1144 " not tell us which reg is the stack pointer!");
1145 SDOperand Chain = Tmp1.getOperand(0);
1146 SDOperand Size = Tmp2.getOperand(1);
1147 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1148 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1149 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1150 Tmp1 = LegalizeOp(Tmp1);
1151 Tmp2 = LegalizeOp(Tmp2);
1154 case TargetLowering::Custom:
1155 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1157 Tmp1 = LegalizeOp(Tmp3);
1158 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1161 case TargetLowering::Legal:
1164 // Since this op produce two values, make sure to remember that we
1165 // legalized both of them.
1166 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1167 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1168 return Op.ResNo ? Tmp2 : Tmp1;
1170 case ISD::INLINEASM:
1171 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize Chain.
1172 Tmp2 = Node->getOperand(Node->getNumOperands()-1);
1173 if (Tmp2.getValueType() == MVT::Flag) // Legalize Flag if it exists.
1174 Tmp2 = Tmp3 = SDOperand(0, 0);
1176 Tmp3 = LegalizeOp(Tmp2);
1178 if (Tmp1 != Node->getOperand(0) || Tmp2 != Tmp3) {
1179 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
1181 if (Tmp3.Val) Ops.back() = Tmp3;
1182 Result = DAG.UpdateNodeOperands(Result, Ops);
1185 // INLINE asm returns a chain and flag, make sure to add both to the map.
1186 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1187 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1188 return Result.getValue(Op.ResNo);
1190 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1191 // Ensure that libcalls are emitted before a branch.
1192 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1193 Tmp1 = LegalizeOp(Tmp1);
1194 LastCALLSEQ_END = DAG.getEntryNode();
1196 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1200 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1201 // Ensure that libcalls are emitted before a return.
1202 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1203 Tmp1 = LegalizeOp(Tmp1);
1204 LastCALLSEQ_END = DAG.getEntryNode();
1206 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1207 case Expand: assert(0 && "It's impossible to expand bools");
1209 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1212 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1216 // Basic block destination (Op#2) is always legal.
1217 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1219 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1220 default: assert(0 && "This action is not supported yet!");
1221 case TargetLowering::Legal: break;
1222 case TargetLowering::Custom:
1223 Tmp1 = TLI.LowerOperation(Result, DAG);
1224 if (Tmp1.Val) Result = Tmp1;
1226 case TargetLowering::Expand:
1227 // Expand brcond's setcc into its constituent parts and create a BR_CC
1229 if (Tmp2.getOpcode() == ISD::SETCC) {
1230 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1231 Tmp2.getOperand(0), Tmp2.getOperand(1),
1232 Node->getOperand(2));
1234 // Make sure the condition is either zero or one. It may have been
1235 // promoted from something else.
1236 unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType());
1237 if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1))
1238 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1240 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1241 DAG.getCondCode(ISD::SETNE), Tmp2,
1242 DAG.getConstant(0, Tmp2.getValueType()),
1243 Node->getOperand(2));
1249 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1250 // Ensure that libcalls are emitted before a branch.
1251 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1252 Tmp1 = LegalizeOp(Tmp1);
1253 LastCALLSEQ_END = DAG.getEntryNode();
1255 Tmp2 = Node->getOperand(2); // LHS
1256 Tmp3 = Node->getOperand(3); // RHS
1257 Tmp4 = Node->getOperand(1); // CC
1259 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1261 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1262 // the LHS is a legal SETCC itself. In this case, we need to compare
1263 // the result against zero to select between true and false values.
1264 if (Tmp3.Val == 0) {
1265 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1266 Tmp4 = DAG.getCondCode(ISD::SETNE);
1269 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1270 Node->getOperand(4));
1272 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1273 default: assert(0 && "Unexpected action for BR_CC!");
1274 case TargetLowering::Legal: break;
1275 case TargetLowering::Custom:
1276 Tmp4 = TLI.LowerOperation(Result, DAG);
1277 if (Tmp4.Val) Result = Tmp4;
1282 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1283 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1285 MVT::ValueType VT = Node->getValueType(0);
1286 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1287 Tmp3 = Result.getValue(0);
1288 Tmp4 = Result.getValue(1);
1290 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1291 default: assert(0 && "This action is not supported yet!");
1292 case TargetLowering::Legal: break;
1293 case TargetLowering::Custom:
1294 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1296 Tmp3 = LegalizeOp(Tmp1);
1297 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1300 case TargetLowering::Promote: {
1301 // Only promote a load of vector type to another.
1302 assert(MVT::isVector(VT) && "Cannot promote this load!");
1303 // Change base type to a different vector type.
1304 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1306 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, Node->getOperand(2));
1307 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1308 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1312 // Since loads produce two values, make sure to remember that we
1313 // legalized both of them.
1314 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1315 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1316 return Op.ResNo ? Tmp4 : Tmp3;
1320 case ISD::ZEXTLOAD: {
1321 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1322 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1324 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
1325 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
1326 default: assert(0 && "This action is not supported yet!");
1327 case TargetLowering::Promote:
1328 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
1329 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1330 DAG.getValueType(MVT::i8));
1331 Tmp1 = Result.getValue(0);
1332 Tmp2 = Result.getValue(1);
1334 case TargetLowering::Custom:
1337 case TargetLowering::Legal:
1338 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1339 Node->getOperand(3));
1340 Tmp1 = Result.getValue(0);
1341 Tmp2 = Result.getValue(1);
1344 Tmp3 = TLI.LowerOperation(Tmp3, DAG);
1346 Tmp1 = LegalizeOp(Tmp3);
1347 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1351 case TargetLowering::Expand:
1352 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1353 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1354 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
1355 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1356 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1357 Tmp2 = LegalizeOp(Load.getValue(1));
1360 assert(Node->getOpcode() != ISD::EXTLOAD &&
1361 "EXTLOAD should always be supported!");
1362 // Turn the unsupported load into an EXTLOAD followed by an explicit
1363 // zero/sign extend inreg.
1364 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1365 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1367 if (Node->getOpcode() == ISD::SEXTLOAD)
1368 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1369 Result, DAG.getValueType(SrcVT));
1371 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1372 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1373 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1376 // Since loads produce two values, make sure to remember that we legalized
1378 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1379 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1380 return Op.ResNo ? Tmp2 : Tmp1;
1382 case ISD::EXTRACT_ELEMENT: {
1383 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1384 switch (getTypeAction(OpTy)) {
1385 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1387 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1389 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1390 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1391 TLI.getShiftAmountTy()));
1392 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1395 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1396 Node->getOperand(0));
1400 // Get both the low and high parts.
1401 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1402 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1403 Result = Tmp2; // 1 -> Hi
1405 Result = Tmp1; // 0 -> Lo
1411 case ISD::CopyToReg:
1412 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1414 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1415 "Register type must be legal!");
1416 // Legalize the incoming value (must be a legal type).
1417 Tmp2 = LegalizeOp(Node->getOperand(2));
1418 if (Node->getNumValues() == 1) {
1419 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1421 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1422 if (Node->getNumOperands() == 4) {
1423 Tmp3 = LegalizeOp(Node->getOperand(3));
1424 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1427 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1430 // Since this produces two values, make sure to remember that we legalized
1432 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1433 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1439 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1441 // Ensure that libcalls are emitted before a return.
1442 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1443 Tmp1 = LegalizeOp(Tmp1);
1444 LastCALLSEQ_END = DAG.getEntryNode();
1446 switch (Node->getNumOperands()) {
1448 Tmp2 = Node->getOperand(1);
1449 switch (getTypeAction(Tmp2.getValueType())) {
1451 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2));
1454 if (Tmp2.getValueType() != MVT::Vector) {
1456 ExpandOp(Tmp2, Lo, Hi);
1457 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
1459 SDNode *InVal = Tmp2.Val;
1461 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1462 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1464 // Figure out if there is a Packed type corresponding to this Vector
1465 // type. If so, convert to the packed type.
1466 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1467 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1468 // Turn this into a return of the packed type.
1469 Tmp2 = PackVectorOp(Tmp2, TVT);
1470 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1471 } else if (NumElems == 1) {
1472 // Turn this into a return of the scalar type.
1473 Tmp2 = PackVectorOp(Tmp2, EVT);
1474 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1476 // FIXME: Returns of gcc generic vectors smaller than a legal type
1477 // should be returned in integer registers!
1479 // The scalarized value type may not be legal, e.g. it might require
1480 // promotion or expansion. Relegalize the return.
1481 Result = LegalizeOp(Result);
1483 // FIXME: Returns of gcc generic vectors larger than a legal vector
1484 // type should be returned by reference!
1486 SplitVectorOp(Tmp2, Lo, Hi);
1487 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
1488 Result = LegalizeOp(Result);
1493 Tmp2 = PromoteOp(Node->getOperand(1));
1494 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1495 Result = LegalizeOp(Result);
1500 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1502 default: { // ret <values>
1503 std::vector<SDOperand> NewValues;
1504 NewValues.push_back(Tmp1);
1505 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1506 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1508 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1512 assert(Node->getOperand(i).getValueType() != MVT::Vector &&
1513 "FIXME: TODO: implement returning non-legal vector types!");
1514 ExpandOp(Node->getOperand(i), Lo, Hi);
1515 NewValues.push_back(Lo);
1516 NewValues.push_back(Hi);
1520 assert(0 && "Can't promote multiple return value yet!");
1523 if (NewValues.size() == Node->getNumOperands())
1524 Result = DAG.UpdateNodeOperands(Result, NewValues);
1526 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
1531 if (Result.getOpcode() == ISD::RET) {
1532 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1533 default: assert(0 && "This action is not supported yet!");
1534 case TargetLowering::Legal: break;
1535 case TargetLowering::Custom:
1536 Tmp1 = TLI.LowerOperation(Result, DAG);
1537 if (Tmp1.Val) Result = Tmp1;
1543 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1544 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1546 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1547 // FIXME: We shouldn't do this for TargetConstantFP's.
1548 // FIXME: move this to the DAG Combiner!
1549 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1550 if (CFP->getValueType(0) == MVT::f32) {
1551 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1553 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1554 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1556 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1557 Node->getOperand(3));
1561 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1563 Tmp3 = LegalizeOp(Node->getOperand(1));
1564 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1565 Node->getOperand(3));
1567 MVT::ValueType VT = Tmp3.getValueType();
1568 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1569 default: assert(0 && "This action is not supported yet!");
1570 case TargetLowering::Legal: break;
1571 case TargetLowering::Custom:
1572 Tmp1 = TLI.LowerOperation(Result, DAG);
1573 if (Tmp1.Val) Result = Tmp1;
1575 case TargetLowering::Promote:
1576 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1577 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1578 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1579 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1580 Node->getOperand(3));
1586 // Truncate the value and store the result.
1587 Tmp3 = PromoteOp(Node->getOperand(1));
1588 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1589 Node->getOperand(3),
1590 DAG.getValueType(Node->getOperand(1).getValueType()));
1594 unsigned IncrementSize = 0;
1597 // If this is a vector type, then we have to calculate the increment as
1598 // the product of the element size in bytes, and the number of elements
1599 // in the high half of the vector.
1600 if (Node->getOperand(1).getValueType() == MVT::Vector) {
1601 SDNode *InVal = Node->getOperand(1).Val;
1603 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1604 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1606 // Figure out if there is a Packed type corresponding to this Vector
1607 // type. If so, convert to the packed type.
1608 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1609 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1610 // Turn this into a normal store of the packed type.
1611 Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1612 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1613 Node->getOperand(3));
1614 Result = LegalizeOp(Result);
1616 } else if (NumElems == 1) {
1617 // Turn this into a normal store of the scalar type.
1618 Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1619 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1620 Node->getOperand(3));
1621 // The scalarized value type may not be legal, e.g. it might require
1622 // promotion or expansion. Relegalize the scalar store.
1623 Result = LegalizeOp(Result);
1626 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1627 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1630 ExpandOp(Node->getOperand(1), Lo, Hi);
1631 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1633 if (!TLI.isLittleEndian())
1637 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1638 Node->getOperand(3));
1639 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1640 getIntPtrConstant(IncrementSize));
1641 assert(isTypeLegal(Tmp2.getValueType()) &&
1642 "Pointers must be legal!");
1643 // FIXME: This sets the srcvalue of both halves to be the same, which is
1645 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1646 Node->getOperand(3));
1647 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1653 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1654 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1656 case ISD::STACKSAVE:
1657 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1658 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1659 Tmp1 = Result.getValue(0);
1660 Tmp2 = Result.getValue(1);
1662 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1663 default: assert(0 && "This action is not supported yet!");
1664 case TargetLowering::Legal: break;
1665 case TargetLowering::Custom:
1666 Tmp3 = TLI.LowerOperation(Result, DAG);
1668 Tmp1 = LegalizeOp(Tmp3);
1669 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1672 case TargetLowering::Expand:
1673 // Expand to CopyFromReg if the target set
1674 // StackPointerRegisterToSaveRestore.
1675 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1676 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1677 Node->getValueType(0));
1678 Tmp2 = Tmp1.getValue(1);
1680 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1681 Tmp2 = Node->getOperand(0);
1686 // Since stacksave produce two values, make sure to remember that we
1687 // legalized both of them.
1688 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1689 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1690 return Op.ResNo ? Tmp2 : Tmp1;
1692 case ISD::STACKRESTORE:
1693 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1694 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1695 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1697 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1698 default: assert(0 && "This action is not supported yet!");
1699 case TargetLowering::Legal: break;
1700 case TargetLowering::Custom:
1701 Tmp1 = TLI.LowerOperation(Result, DAG);
1702 if (Tmp1.Val) Result = Tmp1;
1704 case TargetLowering::Expand:
1705 // Expand to CopyToReg if the target set
1706 // StackPointerRegisterToSaveRestore.
1707 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1708 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1716 case ISD::READCYCLECOUNTER:
1717 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1718 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1720 // Since rdcc produce two values, make sure to remember that we legalized
1722 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1723 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1726 case ISD::TRUNCSTORE: {
1727 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1728 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1730 assert(isTypeLegal(Node->getOperand(1).getValueType()) &&
1731 "Cannot handle illegal TRUNCSTORE yet!");
1732 Tmp2 = LegalizeOp(Node->getOperand(1));
1734 // The only promote case we handle is TRUNCSTORE:i1 X into
1735 // -> TRUNCSTORE:i8 (and X, 1)
1736 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1737 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1738 TargetLowering::Promote) {
1739 // Promote the bool to a mask then store.
1740 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1741 DAG.getConstant(1, Tmp2.getValueType()));
1742 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1743 Node->getOperand(3), DAG.getValueType(MVT::i8));
1745 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1746 Tmp3 != Node->getOperand(2)) {
1747 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
1748 Node->getOperand(3), Node->getOperand(4));
1751 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT();
1752 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) {
1753 default: assert(0 && "This action is not supported yet!");
1754 case TargetLowering::Legal: break;
1755 case TargetLowering::Custom:
1756 Tmp1 = TLI.LowerOperation(Result, DAG);
1757 if (Tmp1.Val) Result = Tmp1;
1763 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1764 case Expand: assert(0 && "It's impossible to expand bools");
1766 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1769 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1772 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1773 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1775 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1777 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1778 default: assert(0 && "This action is not supported yet!");
1779 case TargetLowering::Legal: break;
1780 case TargetLowering::Custom: {
1781 Tmp1 = TLI.LowerOperation(Result, DAG);
1782 if (Tmp1.Val) Result = Tmp1;
1785 case TargetLowering::Expand:
1786 if (Tmp1.getOpcode() == ISD::SETCC) {
1787 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1789 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1791 // Make sure the condition is either zero or one. It may have been
1792 // promoted from something else.
1793 unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType());
1794 if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1))
1795 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1796 Result = DAG.getSelectCC(Tmp1,
1797 DAG.getConstant(0, Tmp1.getValueType()),
1798 Tmp2, Tmp3, ISD::SETNE);
1801 case TargetLowering::Promote: {
1802 MVT::ValueType NVT =
1803 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1804 unsigned ExtOp, TruncOp;
1805 if (MVT::isVector(Tmp2.getValueType())) {
1806 ExtOp = ISD::BIT_CONVERT;
1807 TruncOp = ISD::BIT_CONVERT;
1808 } else if (MVT::isInteger(Tmp2.getValueType())) {
1809 ExtOp = ISD::ANY_EXTEND;
1810 TruncOp = ISD::TRUNCATE;
1812 ExtOp = ISD::FP_EXTEND;
1813 TruncOp = ISD::FP_ROUND;
1815 // Promote each of the values to the new type.
1816 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1817 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1818 // Perform the larger operation, then round down.
1819 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1820 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1825 case ISD::SELECT_CC: {
1826 Tmp1 = Node->getOperand(0); // LHS
1827 Tmp2 = Node->getOperand(1); // RHS
1828 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1829 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1830 SDOperand CC = Node->getOperand(4);
1832 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
1834 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1835 // the LHS is a legal SETCC itself. In this case, we need to compare
1836 // the result against zero to select between true and false values.
1837 if (Tmp2.Val == 0) {
1838 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1839 CC = DAG.getCondCode(ISD::SETNE);
1841 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
1843 // Everything is legal, see if we should expand this op or something.
1844 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
1845 default: assert(0 && "This action is not supported yet!");
1846 case TargetLowering::Legal: break;
1847 case TargetLowering::Custom:
1848 Tmp1 = TLI.LowerOperation(Result, DAG);
1849 if (Tmp1.Val) Result = Tmp1;
1855 Tmp1 = Node->getOperand(0);
1856 Tmp2 = Node->getOperand(1);
1857 Tmp3 = Node->getOperand(2);
1858 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
1860 // If we had to Expand the SetCC operands into a SELECT node, then it may
1861 // not always be possible to return a true LHS & RHS. In this case, just
1862 // return the value we legalized, returned in the LHS
1863 if (Tmp2.Val == 0) {
1868 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
1869 default: assert(0 && "Cannot handle this action for SETCC yet!");
1870 case TargetLowering::Custom:
1873 case TargetLowering::Legal:
1874 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1876 Tmp3 = TLI.LowerOperation(Result, DAG);
1877 if (Tmp3.Val) Result = Tmp3;
1880 case TargetLowering::Promote: {
1881 // First step, figure out the appropriate operation to use.
1882 // Allow SETCC to not be supported for all legal data types
1883 // Mostly this targets FP
1884 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1885 MVT::ValueType OldVT = NewInTy;
1887 // Scan for the appropriate larger type to use.
1889 NewInTy = (MVT::ValueType)(NewInTy+1);
1891 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1892 "Fell off of the edge of the integer world");
1893 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1894 "Fell off of the edge of the floating point world");
1896 // If the target supports SETCC of this type, use it.
1897 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
1900 if (MVT::isInteger(NewInTy))
1901 assert(0 && "Cannot promote Legal Integer SETCC yet");
1903 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1904 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
1906 Tmp1 = LegalizeOp(Tmp1);
1907 Tmp2 = LegalizeOp(Tmp2);
1908 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1909 Result = LegalizeOp(Result);
1912 case TargetLowering::Expand:
1913 // Expand a setcc node into a select_cc of the same condition, lhs, and
1914 // rhs that selects between const 1 (true) and const 0 (false).
1915 MVT::ValueType VT = Node->getValueType(0);
1916 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1917 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1918 Node->getOperand(2));
1924 case ISD::MEMMOVE: {
1925 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1926 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1928 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1929 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1930 case Expand: assert(0 && "Cannot expand a byte!");
1932 Tmp3 = LegalizeOp(Node->getOperand(2));
1935 Tmp3 = PromoteOp(Node->getOperand(2));
1939 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1943 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1945 // Length is too big, just take the lo-part of the length.
1947 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
1951 Tmp4 = LegalizeOp(Node->getOperand(3));
1954 Tmp4 = PromoteOp(Node->getOperand(3));
1959 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
1960 case Expand: assert(0 && "Cannot expand this yet!");
1962 Tmp5 = LegalizeOp(Node->getOperand(4));
1965 Tmp5 = PromoteOp(Node->getOperand(4));
1969 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1970 default: assert(0 && "This action not implemented for this operation!");
1971 case TargetLowering::Custom:
1974 case TargetLowering::Legal:
1975 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
1977 Tmp1 = TLI.LowerOperation(Result, DAG);
1978 if (Tmp1.Val) Result = Tmp1;
1981 case TargetLowering::Expand: {
1982 // Otherwise, the target does not support this operation. Lower the
1983 // operation to an explicit libcall as appropriate.
1984 MVT::ValueType IntPtr = TLI.getPointerTy();
1985 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType();
1986 std::vector<std::pair<SDOperand, const Type*> > Args;
1988 const char *FnName = 0;
1989 if (Node->getOpcode() == ISD::MEMSET) {
1990 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1991 // Extend the (previously legalized) ubyte argument to be an int value
1993 if (Tmp3.getValueType() > MVT::i32)
1994 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
1996 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
1997 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
1998 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2001 } else if (Node->getOpcode() == ISD::MEMCPY ||
2002 Node->getOpcode() == ISD::MEMMOVE) {
2003 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2004 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
2005 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2006 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2008 assert(0 && "Unknown op!");
2011 std::pair<SDOperand,SDOperand> CallResult =
2012 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
2013 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2014 Result = CallResult.second;
2021 case ISD::SHL_PARTS:
2022 case ISD::SRA_PARTS:
2023 case ISD::SRL_PARTS: {
2024 std::vector<SDOperand> Ops;
2025 bool Changed = false;
2026 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2027 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2028 Changed |= Ops.back() != Node->getOperand(i);
2031 Result = DAG.UpdateNodeOperands(Result, Ops);
2033 switch (TLI.getOperationAction(Node->getOpcode(),
2034 Node->getValueType(0))) {
2035 default: assert(0 && "This action is not supported yet!");
2036 case TargetLowering::Legal: break;
2037 case TargetLowering::Custom:
2038 Tmp1 = TLI.LowerOperation(Result, DAG);
2040 SDOperand Tmp2, RetVal(0, 0);
2041 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2042 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2043 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2047 assert(RetVal.Val && "Illegal result number");
2053 // Since these produce multiple values, make sure to remember that we
2054 // legalized all of them.
2055 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2056 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2057 return Result.getValue(Op.ResNo);
2078 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2079 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2080 case Expand: assert(0 && "Not possible");
2082 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2085 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2089 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2091 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2092 default: assert(0 && "BinOp legalize operation not supported");
2093 case TargetLowering::Legal: break;
2094 case TargetLowering::Custom:
2095 Tmp1 = TLI.LowerOperation(Result, DAG);
2096 if (Tmp1.Val) Result = Tmp1;
2098 case TargetLowering::Expand: {
2099 assert(MVT::isVector(Node->getValueType(0)) &&
2100 "Cannot expand this binary operator!");
2101 // Expand the operation into a bunch of nasty scalar code.
2102 std::vector<SDOperand> Ops;
2103 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
2104 MVT::ValueType PtrVT = TLI.getPointerTy();
2105 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2107 SDOperand Idx = DAG.getConstant(i, PtrVT);
2108 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2109 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2110 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2112 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), Ops);
2115 case TargetLowering::Promote: {
2116 switch (Node->getOpcode()) {
2117 default: assert(0 && "Do not know how to promote this BinOp!");
2121 MVT::ValueType OVT = Node->getValueType(0);
2122 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2123 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2124 // Bit convert each of the values to the new type.
2125 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2126 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2127 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2128 // Bit convert the result back the original type.
2129 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2137 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2138 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2139 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2140 case Expand: assert(0 && "Not possible");
2142 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2145 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2149 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2151 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2152 default: assert(0 && "Operation not supported");
2153 case TargetLowering::Custom:
2154 Tmp1 = TLI.LowerOperation(Result, DAG);
2155 if (Tmp1.Val) Result = Tmp1;
2157 case TargetLowering::Legal: break;
2158 case TargetLowering::Expand:
2159 // If this target supports fabs/fneg natively, do this efficiently.
2160 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
2161 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
2162 // Get the sign bit of the RHS.
2163 MVT::ValueType IVT =
2164 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2165 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2166 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2167 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2168 // Get the absolute value of the result.
2169 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2170 // Select between the nabs and abs value based on the sign bit of
2172 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2173 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2176 Result = LegalizeOp(Result);
2180 // Otherwise, do bitwise ops!
2182 // copysign -> copysignf/copysign libcall.
2184 if (Node->getValueType(0) == MVT::f32) {
2185 FnName = "copysignf";
2186 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type.
2187 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2188 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2));
2190 FnName = "copysign";
2191 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type.
2192 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2193 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2));
2196 Result = ExpandLibCall(FnName, Node, Dummy);
2203 Tmp1 = LegalizeOp(Node->getOperand(0));
2204 Tmp2 = LegalizeOp(Node->getOperand(1));
2205 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2206 // Since this produces two values, make sure to remember that we legalized
2208 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2209 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2214 Tmp1 = LegalizeOp(Node->getOperand(0));
2215 Tmp2 = LegalizeOp(Node->getOperand(1));
2216 Tmp3 = LegalizeOp(Node->getOperand(2));
2217 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2218 // Since this produces two values, make sure to remember that we legalized
2220 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2221 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2224 case ISD::BUILD_PAIR: {
2225 MVT::ValueType PairTy = Node->getValueType(0);
2226 // TODO: handle the case where the Lo and Hi operands are not of legal type
2227 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2228 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2229 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2230 case TargetLowering::Promote:
2231 case TargetLowering::Custom:
2232 assert(0 && "Cannot promote/custom this yet!");
2233 case TargetLowering::Legal:
2234 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2235 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2237 case TargetLowering::Expand:
2238 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2239 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2240 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2241 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2242 TLI.getShiftAmountTy()));
2243 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2252 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2253 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2255 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2256 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2257 case TargetLowering::Custom:
2260 case TargetLowering::Legal:
2261 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2263 Tmp1 = TLI.LowerOperation(Result, DAG);
2264 if (Tmp1.Val) Result = Tmp1;
2267 case TargetLowering::Expand:
2268 if (MVT::isInteger(Node->getValueType(0))) {
2270 MVT::ValueType VT = Node->getValueType(0);
2271 unsigned Opc = Node->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
2272 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
2273 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2274 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2276 // Floating point mod -> fmod libcall.
2277 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
2279 Result = ExpandLibCall(FnName, Node, Dummy);
2285 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2286 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2288 MVT::ValueType VT = Node->getValueType(0);
2289 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2290 default: assert(0 && "This action is not supported yet!");
2291 case TargetLowering::Custom:
2294 case TargetLowering::Legal:
2295 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2296 Result = Result.getValue(0);
2297 Tmp1 = Result.getValue(1);
2300 Tmp2 = TLI.LowerOperation(Result, DAG);
2302 Result = LegalizeOp(Tmp2);
2303 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2307 case TargetLowering::Expand: {
2308 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2309 Node->getOperand(2));
2310 // Increment the pointer, VAList, to the next vaarg
2311 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2312 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2313 TLI.getPointerTy()));
2314 // Store the incremented VAList to the legalized pointer
2315 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2,
2316 Node->getOperand(2));
2317 // Load the actual argument out of the pointer VAList
2318 Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0));
2319 Tmp1 = LegalizeOp(Result.getValue(1));
2320 Result = LegalizeOp(Result);
2324 // Since VAARG produces two values, make sure to remember that we
2325 // legalized both of them.
2326 AddLegalizedOperand(SDOperand(Node, 0), Result);
2327 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2328 return Op.ResNo ? Tmp1 : Result;
2332 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2333 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2334 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2336 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2337 default: assert(0 && "This action is not supported yet!");
2338 case TargetLowering::Custom:
2341 case TargetLowering::Legal:
2342 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2343 Node->getOperand(3), Node->getOperand(4));
2345 Tmp1 = TLI.LowerOperation(Result, DAG);
2346 if (Tmp1.Val) Result = Tmp1;
2349 case TargetLowering::Expand:
2350 // This defaults to loading a pointer from the input and storing it to the
2351 // output, returning the chain.
2352 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, Node->getOperand(3));
2353 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp4.getValue(1), Tmp4, Tmp2,
2354 Node->getOperand(4));
2360 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2361 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2363 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2364 default: assert(0 && "This action is not supported yet!");
2365 case TargetLowering::Custom:
2368 case TargetLowering::Legal:
2369 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2371 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2372 if (Tmp1.Val) Result = Tmp1;
2375 case TargetLowering::Expand:
2376 Result = Tmp1; // Default to a no-op, return the chain
2382 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2383 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2385 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2387 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2388 default: assert(0 && "This action is not supported yet!");
2389 case TargetLowering::Legal: break;
2390 case TargetLowering::Custom:
2391 Tmp1 = TLI.LowerOperation(Result, DAG);
2392 if (Tmp1.Val) Result = Tmp1;
2399 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2400 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2402 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2403 "Cannot handle this yet!");
2404 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2408 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2409 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2410 case TargetLowering::Custom:
2411 assert(0 && "Cannot custom legalize this yet!");
2412 case TargetLowering::Legal:
2413 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2415 case TargetLowering::Promote: {
2416 MVT::ValueType OVT = Tmp1.getValueType();
2417 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2418 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2420 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2421 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2422 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2423 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2426 case TargetLowering::Expand:
2427 Result = ExpandBSWAP(Tmp1);
2435 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2436 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2437 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2438 case TargetLowering::Legal:
2439 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2441 case TargetLowering::Promote: {
2442 MVT::ValueType OVT = Tmp1.getValueType();
2443 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2445 // Zero extend the argument.
2446 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2447 // Perform the larger operation, then subtract if needed.
2448 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2449 switch (Node->getOpcode()) {
2454 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2455 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2456 DAG.getConstant(getSizeInBits(NVT), NVT),
2458 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2459 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2462 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2463 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2464 DAG.getConstant(getSizeInBits(NVT) -
2465 getSizeInBits(OVT), NVT));
2470 case TargetLowering::Expand:
2471 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2482 Tmp1 = LegalizeOp(Node->getOperand(0));
2483 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2484 case TargetLowering::Promote:
2485 case TargetLowering::Custom:
2488 case TargetLowering::Legal:
2489 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2491 Tmp1 = TLI.LowerOperation(Result, DAG);
2492 if (Tmp1.Val) Result = Tmp1;
2495 case TargetLowering::Expand:
2496 switch (Node->getOpcode()) {
2497 default: assert(0 && "Unreachable!");
2499 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2500 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2501 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2504 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2505 MVT::ValueType VT = Node->getValueType(0);
2506 Tmp2 = DAG.getConstantFP(0.0, VT);
2507 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2508 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2509 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2515 MVT::ValueType VT = Node->getValueType(0);
2516 const char *FnName = 0;
2517 switch(Node->getOpcode()) {
2518 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2519 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2520 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2521 default: assert(0 && "Unreachable!");
2524 Result = ExpandLibCall(FnName, Node, Dummy);
2532 case ISD::BIT_CONVERT:
2533 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2534 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2536 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2537 Node->getOperand(0).getValueType())) {
2538 default: assert(0 && "Unknown operation action!");
2539 case TargetLowering::Expand:
2540 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2542 case TargetLowering::Legal:
2543 Tmp1 = LegalizeOp(Node->getOperand(0));
2544 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2549 case ISD::VBIT_CONVERT: {
2550 assert(Op.getOperand(0).getValueType() == MVT::Vector &&
2551 "Can only have VBIT_CONVERT where input or output is MVT::Vector!");
2553 // The input has to be a vector type, we have to either scalarize it, pack
2554 // it, or convert it based on whether the input vector type is legal.
2555 SDNode *InVal = Node->getOperand(0).Val;
2557 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
2558 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
2560 // Figure out if there is a Packed type corresponding to this Vector
2561 // type. If so, convert to the packed type.
2562 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2563 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
2564 // Turn this into a bit convert of the packed input.
2565 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2566 PackVectorOp(Node->getOperand(0), TVT));
2568 } else if (NumElems == 1) {
2569 // Turn this into a bit convert of the scalar input.
2570 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2571 PackVectorOp(Node->getOperand(0), EVT));
2574 // FIXME: UNIMP! Store then reload
2575 assert(0 && "Cast from unsupported vector type not implemented yet!");
2579 // Conversion operators. The source and destination have different types.
2580 case ISD::SINT_TO_FP:
2581 case ISD::UINT_TO_FP: {
2582 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2583 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2585 switch (TLI.getOperationAction(Node->getOpcode(),
2586 Node->getOperand(0).getValueType())) {
2587 default: assert(0 && "Unknown operation action!");
2588 case TargetLowering::Custom:
2591 case TargetLowering::Legal:
2592 Tmp1 = LegalizeOp(Node->getOperand(0));
2593 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2595 Tmp1 = TLI.LowerOperation(Result, DAG);
2596 if (Tmp1.Val) Result = Tmp1;
2599 case TargetLowering::Expand:
2600 Result = ExpandLegalINT_TO_FP(isSigned,
2601 LegalizeOp(Node->getOperand(0)),
2602 Node->getValueType(0));
2604 case TargetLowering::Promote:
2605 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2606 Node->getValueType(0),
2612 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2613 Node->getValueType(0), Node->getOperand(0));
2616 Tmp1 = PromoteOp(Node->getOperand(0));
2618 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2619 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2621 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2622 Node->getOperand(0).getValueType());
2624 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2625 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2631 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2633 Tmp1 = LegalizeOp(Node->getOperand(0));
2634 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2637 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2639 // Since the result is legal, we should just be able to truncate the low
2640 // part of the source.
2641 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2644 Result = PromoteOp(Node->getOperand(0));
2645 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2650 case ISD::FP_TO_SINT:
2651 case ISD::FP_TO_UINT:
2652 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2654 Tmp1 = LegalizeOp(Node->getOperand(0));
2656 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2657 default: assert(0 && "Unknown operation action!");
2658 case TargetLowering::Custom:
2661 case TargetLowering::Legal:
2662 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2664 Tmp1 = TLI.LowerOperation(Result, DAG);
2665 if (Tmp1.Val) Result = Tmp1;
2668 case TargetLowering::Promote:
2669 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2670 Node->getOpcode() == ISD::FP_TO_SINT);
2672 case TargetLowering::Expand:
2673 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2674 SDOperand True, False;
2675 MVT::ValueType VT = Node->getOperand(0).getValueType();
2676 MVT::ValueType NVT = Node->getValueType(0);
2677 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2678 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2679 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2680 Node->getOperand(0), Tmp2, ISD::SETLT);
2681 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2682 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2683 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2685 False = DAG.getNode(ISD::XOR, NVT, False,
2686 DAG.getConstant(1ULL << ShiftAmt, NVT));
2687 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2690 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2696 assert(0 && "Shouldn't need to expand other operators here!");
2698 Tmp1 = PromoteOp(Node->getOperand(0));
2699 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
2700 Result = LegalizeOp(Result);
2705 case ISD::ANY_EXTEND:
2706 case ISD::ZERO_EXTEND:
2707 case ISD::SIGN_EXTEND:
2708 case ISD::FP_EXTEND:
2710 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2711 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
2713 Tmp1 = LegalizeOp(Node->getOperand(0));
2714 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2717 switch (Node->getOpcode()) {
2718 case ISD::ANY_EXTEND:
2719 Tmp1 = PromoteOp(Node->getOperand(0));
2720 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
2722 case ISD::ZERO_EXTEND:
2723 Result = PromoteOp(Node->getOperand(0));
2724 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2725 Result = DAG.getZeroExtendInReg(Result,
2726 Node->getOperand(0).getValueType());
2728 case ISD::SIGN_EXTEND:
2729 Result = PromoteOp(Node->getOperand(0));
2730 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2731 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2733 DAG.getValueType(Node->getOperand(0).getValueType()));
2735 case ISD::FP_EXTEND:
2736 Result = PromoteOp(Node->getOperand(0));
2737 if (Result.getValueType() != Op.getValueType())
2738 // Dynamically dead while we have only 2 FP types.
2739 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2742 Result = PromoteOp(Node->getOperand(0));
2743 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2748 case ISD::FP_ROUND_INREG:
2749 case ISD::SIGN_EXTEND_INREG: {
2750 Tmp1 = LegalizeOp(Node->getOperand(0));
2751 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2753 // If this operation is not supported, convert it to a shl/shr or load/store
2755 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2756 default: assert(0 && "This action not supported for this op yet!");
2757 case TargetLowering::Legal:
2758 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2760 case TargetLowering::Expand:
2761 // If this is an integer extend and shifts are supported, do that.
2762 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2763 // NOTE: we could fall back on load/store here too for targets without
2764 // SAR. However, it is doubtful that any exist.
2765 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2766 MVT::getSizeInBits(ExtraVT);
2767 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2768 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2769 Node->getOperand(0), ShiftCst);
2770 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2772 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2773 // The only way we can lower this is to turn it into a STORETRUNC,
2774 // EXTLOAD pair, targetting a temporary location (a stack slot).
2776 // NOTE: there is a choice here between constantly creating new stack
2777 // slots and always reusing the same one. We currently always create
2778 // new ones, as reuse may inhibit scheduling.
2779 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2780 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
2781 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
2782 MachineFunction &MF = DAG.getMachineFunction();
2784 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2785 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2786 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2787 Node->getOperand(0), StackSlot,
2788 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2789 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2790 Result, StackSlot, DAG.getSrcValue(NULL),
2793 assert(0 && "Unknown op");
2801 assert(Result.getValueType() == Op.getValueType() &&
2802 "Bad legalization!");
2804 // Make sure that the generated code is itself legal.
2806 Result = LegalizeOp(Result);
2808 // Note that LegalizeOp may be reentered even from single-use nodes, which
2809 // means that we always must cache transformed nodes.
2810 AddLegalizedOperand(Op, Result);
2814 /// PromoteOp - Given an operation that produces a value in an invalid type,
2815 /// promote it to compute the value into a larger type. The produced value will
2816 /// have the correct bits for the low portion of the register, but no guarantee
2817 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2818 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2819 MVT::ValueType VT = Op.getValueType();
2820 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2821 assert(getTypeAction(VT) == Promote &&
2822 "Caller should expand or legalize operands that are not promotable!");
2823 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2824 "Cannot promote to smaller type!");
2826 SDOperand Tmp1, Tmp2, Tmp3;
2828 SDNode *Node = Op.Val;
2830 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2831 if (I != PromotedNodes.end()) return I->second;
2833 switch (Node->getOpcode()) {
2834 case ISD::CopyFromReg:
2835 assert(0 && "CopyFromReg must be legal!");
2837 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2838 assert(0 && "Do not know how to promote this operator!");
2841 Result = DAG.getNode(ISD::UNDEF, NVT);
2845 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2847 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2848 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2850 case ISD::ConstantFP:
2851 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2852 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2856 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2857 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2858 Node->getOperand(1), Node->getOperand(2));
2862 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2864 Result = LegalizeOp(Node->getOperand(0));
2865 assert(Result.getValueType() >= NVT &&
2866 "This truncation doesn't make sense!");
2867 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2868 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2871 // The truncation is not required, because we don't guarantee anything
2872 // about high bits anyway.
2873 Result = PromoteOp(Node->getOperand(0));
2876 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2877 // Truncate the low part of the expanded value to the result type
2878 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2881 case ISD::SIGN_EXTEND:
2882 case ISD::ZERO_EXTEND:
2883 case ISD::ANY_EXTEND:
2884 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2885 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2887 // Input is legal? Just do extend all the way to the larger type.
2888 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2891 // Promote the reg if it's smaller.
2892 Result = PromoteOp(Node->getOperand(0));
2893 // The high bits are not guaranteed to be anything. Insert an extend.
2894 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2895 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2896 DAG.getValueType(Node->getOperand(0).getValueType()));
2897 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2898 Result = DAG.getZeroExtendInReg(Result,
2899 Node->getOperand(0).getValueType());
2903 case ISD::BIT_CONVERT:
2904 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2905 Result = PromoteOp(Result);
2908 case ISD::FP_EXTEND:
2909 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2911 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2912 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2913 case Promote: assert(0 && "Unreachable with 2 FP types!");
2915 // Input is legal? Do an FP_ROUND_INREG.
2916 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
2917 DAG.getValueType(VT));
2922 case ISD::SINT_TO_FP:
2923 case ISD::UINT_TO_FP:
2924 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2926 // No extra round required here.
2927 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2931 Result = PromoteOp(Node->getOperand(0));
2932 if (Node->getOpcode() == ISD::SINT_TO_FP)
2933 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2935 DAG.getValueType(Node->getOperand(0).getValueType()));
2937 Result = DAG.getZeroExtendInReg(Result,
2938 Node->getOperand(0).getValueType());
2939 // No extra round required here.
2940 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2943 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
2944 Node->getOperand(0));
2945 // Round if we cannot tolerate excess precision.
2946 if (NoExcessFPPrecision)
2947 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2948 DAG.getValueType(VT));
2953 case ISD::SIGN_EXTEND_INREG:
2954 Result = PromoteOp(Node->getOperand(0));
2955 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2956 Node->getOperand(1));
2958 case ISD::FP_TO_SINT:
2959 case ISD::FP_TO_UINT:
2960 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2962 Tmp1 = Node->getOperand(0);
2965 // The input result is prerounded, so we don't have to do anything
2967 Tmp1 = PromoteOp(Node->getOperand(0));
2970 assert(0 && "not implemented");
2972 // If we're promoting a UINT to a larger size, check to see if the new node
2973 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
2974 // we can use that instead. This allows us to generate better code for
2975 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
2976 // legal, such as PowerPC.
2977 if (Node->getOpcode() == ISD::FP_TO_UINT &&
2978 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
2979 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
2980 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
2981 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
2983 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2989 Tmp1 = PromoteOp(Node->getOperand(0));
2990 assert(Tmp1.getValueType() == NVT);
2991 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2992 // NOTE: we do not have to do any extra rounding here for
2993 // NoExcessFPPrecision, because we know the input will have the appropriate
2994 // precision, and these operations don't modify precision at all.
3000 Tmp1 = PromoteOp(Node->getOperand(0));
3001 assert(Tmp1.getValueType() == NVT);
3002 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3003 if (NoExcessFPPrecision)
3004 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3005 DAG.getValueType(VT));
3011 // The input may have strange things in the top bits of the registers, but
3012 // these operations don't care. They may have weird bits going out, but
3013 // that too is okay if they are integer operations.
3014 Tmp1 = PromoteOp(Node->getOperand(0));
3015 Tmp2 = PromoteOp(Node->getOperand(1));
3016 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3017 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3022 // The input may have strange things in the top bits of the registers, but
3023 // these operations don't care. They may have weird bits going out, but
3024 // that too is okay if they are integer operations.
3025 Tmp1 = PromoteOp(Node->getOperand(0));
3026 Tmp2 = PromoteOp(Node->getOperand(1));
3027 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3028 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3033 Tmp1 = PromoteOp(Node->getOperand(0));
3034 Tmp2 = PromoteOp(Node->getOperand(1));
3035 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3036 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3038 // Floating point operations will give excess precision that we may not be
3039 // able to tolerate. If we DO allow excess precision, just leave it,
3040 // otherwise excise it.
3041 // FIXME: Why would we need to round FP ops more than integer ones?
3042 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3043 if (NoExcessFPPrecision)
3044 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3045 DAG.getValueType(VT));
3050 // These operators require that their input be sign extended.
3051 Tmp1 = PromoteOp(Node->getOperand(0));
3052 Tmp2 = PromoteOp(Node->getOperand(1));
3053 if (MVT::isInteger(NVT)) {
3054 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3055 DAG.getValueType(VT));
3056 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3057 DAG.getValueType(VT));
3059 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3061 // Perform FP_ROUND: this is probably overly pessimistic.
3062 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3063 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3064 DAG.getValueType(VT));
3068 case ISD::FCOPYSIGN:
3069 // These operators require that their input be fp extended.
3070 Tmp1 = PromoteOp(Node->getOperand(0));
3071 Tmp2 = PromoteOp(Node->getOperand(1));
3072 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3074 // Perform FP_ROUND: this is probably overly pessimistic.
3075 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3076 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3077 DAG.getValueType(VT));
3082 // These operators require that their input be zero extended.
3083 Tmp1 = PromoteOp(Node->getOperand(0));
3084 Tmp2 = PromoteOp(Node->getOperand(1));
3085 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3086 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3087 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3088 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3092 Tmp1 = PromoteOp(Node->getOperand(0));
3093 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3096 // The input value must be properly sign extended.
3097 Tmp1 = PromoteOp(Node->getOperand(0));
3098 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3099 DAG.getValueType(VT));
3100 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3103 // The input value must be properly zero extended.
3104 Tmp1 = PromoteOp(Node->getOperand(0));
3105 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3106 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3110 Tmp1 = Node->getOperand(0); // Get the chain.
3111 Tmp2 = Node->getOperand(1); // Get the pointer.
3112 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3113 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3114 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3116 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3117 Node->getOperand(2));
3118 // Increment the pointer, VAList, to the next vaarg
3119 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3120 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3121 TLI.getPointerTy()));
3122 // Store the incremented VAList to the legalized pointer
3123 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2,
3124 Node->getOperand(2));
3125 // Load the actual argument out of the pointer VAList
3126 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList,
3127 DAG.getSrcValue(0), VT);
3129 // Remember that we legalized the chain.
3130 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3134 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Node->getOperand(0),
3135 Node->getOperand(1), Node->getOperand(2), VT);
3136 // Remember that we legalized the chain.
3137 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3142 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Node->getOperand(0),
3143 Node->getOperand(1), Node->getOperand(2),
3144 cast<VTSDNode>(Node->getOperand(3))->getVT());
3145 // Remember that we legalized the chain.
3146 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3149 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3150 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3151 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3153 case ISD::SELECT_CC:
3154 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3155 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3156 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3157 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3160 Tmp1 = Node->getOperand(0);
3161 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3162 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3163 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3164 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
3165 TLI.getShiftAmountTy()));
3170 // Zero extend the argument
3171 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3172 // Perform the larger operation, then subtract if needed.
3173 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3174 switch(Node->getOpcode()) {
3179 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3180 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3181 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
3182 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3183 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
3186 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3187 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3188 DAG.getConstant(getSizeInBits(NVT) -
3189 getSizeInBits(VT), NVT));
3193 case ISD::VEXTRACT_VECTOR_ELT:
3194 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
3196 case ISD::EXTRACT_VECTOR_ELT:
3197 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3201 assert(Result.Val && "Didn't set a result!");
3203 // Make sure the result is itself legal.
3204 Result = LegalizeOp(Result);
3206 // Remember that we promoted this!
3207 AddPromotedOperand(Op, Result);
3211 /// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
3212 /// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
3213 /// on the vector type. The return type of this matches the element type of the
3214 /// vector, which may not be legal for the target.
3215 SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
3216 // We know that operand #0 is the Vec vector. If the index is a constant
3217 // or if the invec is a supported hardware type, we can use it. Otherwise,
3218 // lower to a store then an indexed load.
3219 SDOperand Vec = Op.getOperand(0);
3220 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3222 SDNode *InVal = Vec.Val;
3223 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
3224 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
3226 // Figure out if there is a Packed type corresponding to this Vector
3227 // type. If so, convert to the packed type.
3228 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3229 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
3230 // Turn this into a packed extract_vector_elt operation.
3231 Vec = PackVectorOp(Vec, TVT);
3232 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
3233 } else if (NumElems == 1) {
3234 // This must be an access of the only element. Return it.
3235 return PackVectorOp(Vec, EVT);
3236 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
3238 SplitVectorOp(Vec, Lo, Hi);
3239 if (CIdx->getValue() < NumElems/2) {
3243 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3246 // It's now an extract from the appropriate high or low part. Recurse.
3247 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3248 return LowerVEXTRACT_VECTOR_ELT(Op);
3250 // Variable index case for extract element.
3251 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
3252 assert(0 && "unimp!");
3257 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3259 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3260 SDOperand Vector = Op.getOperand(0);
3261 SDOperand Idx = Op.getOperand(1);
3263 // If the target doesn't support this, store the value to a temporary
3264 // stack slot, then LOAD the scalar element back out.
3265 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
3266 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3267 Vector, StackPtr, DAG.getSrcValue(NULL));
3269 // Add the offset to the index.
3270 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3271 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3272 DAG.getConstant(EltSize, Idx.getValueType()));
3273 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3275 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, DAG.getSrcValue(NULL));
3279 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3280 /// with condition CC on the current target. This usually involves legalizing
3281 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3282 /// there may be no choice but to create a new SetCC node to represent the
3283 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3284 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3285 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3288 SDOperand Tmp1, Tmp2, Result;
3290 switch (getTypeAction(LHS.getValueType())) {
3292 Tmp1 = LegalizeOp(LHS); // LHS
3293 Tmp2 = LegalizeOp(RHS); // RHS
3296 Tmp1 = PromoteOp(LHS); // LHS
3297 Tmp2 = PromoteOp(RHS); // RHS
3299 // If this is an FP compare, the operands have already been extended.
3300 if (MVT::isInteger(LHS.getValueType())) {
3301 MVT::ValueType VT = LHS.getValueType();
3302 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3304 // Otherwise, we have to insert explicit sign or zero extends. Note
3305 // that we could insert sign extends for ALL conditions, but zero extend
3306 // is cheaper on many machines (an AND instead of two shifts), so prefer
3308 switch (cast<CondCodeSDNode>(CC)->get()) {
3309 default: assert(0 && "Unknown integer comparison!");
3316 // ALL of these operations will work if we either sign or zero extend
3317 // the operands (including the unsigned comparisons!). Zero extend is
3318 // usually a simpler/cheaper operation, so prefer it.
3319 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3320 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3326 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3327 DAG.getValueType(VT));
3328 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3329 DAG.getValueType(VT));
3335 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3336 ExpandOp(LHS, LHSLo, LHSHi);
3337 ExpandOp(RHS, RHSLo, RHSHi);
3338 switch (cast<CondCodeSDNode>(CC)->get()) {
3342 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3343 if (RHSCST->isAllOnesValue()) {
3344 // Comparison to -1.
3345 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3350 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3351 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3352 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3353 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3356 // If this is a comparison of the sign bit, just look at the top part.
3358 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3359 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3360 CST->getValue() == 0) || // X < 0
3361 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3362 CST->isAllOnesValue())) { // X > -1
3368 // FIXME: This generated code sucks.
3369 ISD::CondCode LowCC;
3370 switch (cast<CondCodeSDNode>(CC)->get()) {
3371 default: assert(0 && "Unknown integer setcc!");
3373 case ISD::SETULT: LowCC = ISD::SETULT; break;
3375 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3377 case ISD::SETULE: LowCC = ISD::SETULE; break;
3379 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3382 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3383 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3384 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3386 // NOTE: on targets without efficient SELECT of bools, we can always use
3387 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3388 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3389 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3390 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3391 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3392 Result, Tmp1, Tmp2));
3401 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3402 /// The resultant code need not be legal. Note that SrcOp is the input operand
3403 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3404 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3406 // Create the stack frame object.
3407 SDOperand FIPtr = CreateStackTemporary(DestVT);
3409 // Emit a store to the stack slot.
3410 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3411 SrcOp, FIPtr, DAG.getSrcValue(NULL));
3412 // Result is a load from the stack slot.
3413 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0));
3416 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3417 // Create a vector sized/aligned stack slot, store the value to element #0,
3418 // then load the whole vector back out.
3419 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3420 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3421 Node->getOperand(0), StackPtr,
3422 DAG.getSrcValue(NULL));
3423 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,DAG.getSrcValue(NULL));
3427 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3428 /// support the operation, but do support the resultant packed vector type.
3429 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3431 // If the only non-undef value is the low element, turn this into a
3432 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3433 unsigned NumElems = Node->getNumOperands();
3434 bool isOnlyLowElement = true;
3435 SDOperand SplatValue = Node->getOperand(0);
3436 std::map<SDOperand, std::vector<unsigned> > Values;
3437 Values[SplatValue].push_back(0);
3438 bool isConstant = true;
3439 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3440 SplatValue.getOpcode() != ISD::UNDEF)
3443 for (unsigned i = 1; i < NumElems; ++i) {
3444 SDOperand V = Node->getOperand(i);
3445 std::map<SDOperand, std::vector<unsigned> >::iterator I = Values.find(V);
3446 if (I != Values.end())
3447 I->second.push_back(i);
3449 Values[V].push_back(i);
3450 if (V.getOpcode() != ISD::UNDEF)
3451 isOnlyLowElement = false;
3452 if (SplatValue != V)
3453 SplatValue = SDOperand(0,0);
3455 // If this isn't a constant element or an undef, we can't use a constant
3457 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3458 V.getOpcode() != ISD::UNDEF)
3462 if (isOnlyLowElement) {
3463 // If the low element is an undef too, then this whole things is an undef.
3464 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3465 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3466 // Otherwise, turn this into a scalar_to_vector node.
3467 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3468 Node->getOperand(0));
3471 // If all elements are constants, create a load from the constant pool.
3473 MVT::ValueType VT = Node->getValueType(0);
3475 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3476 std::vector<Constant*> CV;
3477 for (unsigned i = 0, e = NumElems; i != e; ++i) {
3478 if (ConstantFPSDNode *V =
3479 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3480 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3481 } else if (ConstantSDNode *V =
3482 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3483 CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
3485 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3486 CV.push_back(UndefValue::get(OpNTy));
3489 Constant *CP = ConstantPacked::get(CV);
3490 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3491 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
3492 DAG.getSrcValue(NULL));
3495 if (SplatValue.Val) { // Splat of one value?
3496 // Build the shuffle constant vector: <0, 0, 0, 0>
3497 MVT::ValueType MaskVT =
3498 MVT::getIntVectorWithNumElements(NumElems);
3499 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
3500 std::vector<SDOperand> ZeroVec(NumElems, Zero);
3501 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, ZeroVec);
3503 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3504 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
3505 // Get the splatted value into the low element of a vector register.
3506 SDOperand LowValVec =
3507 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3509 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3510 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3511 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3516 // If there are only two unique elements, we may be able to turn this into a
3518 if (Values.size() == 2) {
3519 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
3520 MVT::ValueType MaskVT =
3521 MVT::getIntVectorWithNumElements(NumElems);
3522 std::vector<SDOperand> MaskVec(NumElems);
3524 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3525 E = Values.end(); I != E; ++I) {
3526 for (std::vector<unsigned>::iterator II = I->second.begin(),
3527 EE = I->second.end(); II != EE; ++II)
3528 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
3531 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
3533 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3534 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
3535 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
3536 std::vector<SDOperand> Ops;
3537 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3538 E = Values.end(); I != E; ++I) {
3539 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3543 Ops.push_back(ShuffleMask);
3545 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
3546 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops);
3550 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
3551 // aligned object on the stack, store each element into it, then load
3552 // the result as a vector.
3553 MVT::ValueType VT = Node->getValueType(0);
3554 // Create the stack frame object.
3555 SDOperand FIPtr = CreateStackTemporary(VT);
3557 // Emit a store of each element to the stack slot.
3558 std::vector<SDOperand> Stores;
3559 unsigned TypeByteSize =
3560 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
3561 unsigned VectorSize = MVT::getSizeInBits(VT)/8;
3562 // Store (in the right endianness) the elements to memory.
3563 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3564 // Ignore undef elements.
3565 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3567 unsigned Offset = TypeByteSize*i;
3569 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
3570 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
3572 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3573 Node->getOperand(i), Idx,
3574 DAG.getSrcValue(NULL)));
3577 SDOperand StoreChain;
3578 if (!Stores.empty()) // Not all undef elements?
3579 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
3581 StoreChain = DAG.getEntryNode();
3583 // Result is a load from the stack slot.
3584 return DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0));
3587 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
3588 /// specified value type.
3589 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
3590 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3591 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
3592 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
3593 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
3596 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
3597 SDOperand Op, SDOperand Amt,
3598 SDOperand &Lo, SDOperand &Hi) {
3599 // Expand the subcomponents.
3600 SDOperand LHSL, LHSH;
3601 ExpandOp(Op, LHSL, LHSH);
3603 std::vector<SDOperand> Ops;
3604 Ops.push_back(LHSL);
3605 Ops.push_back(LHSH);
3607 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
3608 Lo = DAG.getNode(NodeOp, VTs, Ops);
3609 Hi = Lo.getValue(1);
3613 /// ExpandShift - Try to find a clever way to expand this shift operation out to
3614 /// smaller elements. If we can't find a way that is more efficient than a
3615 /// libcall on this target, return false. Otherwise, return true with the
3616 /// low-parts expanded into Lo and Hi.
3617 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3618 SDOperand &Lo, SDOperand &Hi) {
3619 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3620 "This is not a shift!");
3622 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3623 SDOperand ShAmt = LegalizeOp(Amt);
3624 MVT::ValueType ShTy = ShAmt.getValueType();
3625 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3626 unsigned NVTBits = MVT::getSizeInBits(NVT);
3628 // Handle the case when Amt is an immediate. Other cases are currently broken
3629 // and are disabled.
3630 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3631 unsigned Cst = CN->getValue();
3632 // Expand the incoming operand to be shifted, so that we have its parts
3634 ExpandOp(Op, InL, InH);
3638 Lo = DAG.getConstant(0, NVT);
3639 Hi = DAG.getConstant(0, NVT);
3640 } else if (Cst > NVTBits) {
3641 Lo = DAG.getConstant(0, NVT);
3642 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
3643 } else if (Cst == NVTBits) {
3644 Lo = DAG.getConstant(0, NVT);
3647 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
3648 Hi = DAG.getNode(ISD::OR, NVT,
3649 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
3650 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
3655 Lo = DAG.getConstant(0, NVT);
3656 Hi = DAG.getConstant(0, NVT);
3657 } else if (Cst > NVTBits) {
3658 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
3659 Hi = DAG.getConstant(0, NVT);
3660 } else if (Cst == NVTBits) {
3662 Hi = DAG.getConstant(0, NVT);
3664 Lo = DAG.getNode(ISD::OR, NVT,
3665 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3666 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3667 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
3672 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
3673 DAG.getConstant(NVTBits-1, ShTy));
3674 } else if (Cst > NVTBits) {
3675 Lo = DAG.getNode(ISD::SRA, NVT, InH,
3676 DAG.getConstant(Cst-NVTBits, ShTy));
3677 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3678 DAG.getConstant(NVTBits-1, ShTy));
3679 } else if (Cst == NVTBits) {
3681 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3682 DAG.getConstant(NVTBits-1, ShTy));
3684 Lo = DAG.getNode(ISD::OR, NVT,
3685 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3686 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3687 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
3696 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
3697 // does not fit into a register, return the lo part and set the hi part to the
3698 // by-reg argument. If it does fit into a single register, return the result
3699 // and leave the Hi part unset.
3700 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3702 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
3703 // The input chain to this libcall is the entry node of the function.
3704 // Legalizing the call will automatically add the previous call to the
3706 SDOperand InChain = DAG.getEntryNode();
3708 TargetLowering::ArgListTy Args;
3709 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3710 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3711 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3712 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3714 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3716 // Splice the libcall in wherever FindInputOutputChains tells us to.
3717 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3718 std::pair<SDOperand,SDOperand> CallInfo =
3719 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3722 // Legalize the call sequence, starting with the chain. This will advance
3723 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
3724 // was added by LowerCallTo (guaranteeing proper serialization of calls).
3725 LegalizeOp(CallInfo.second);
3727 switch (getTypeAction(CallInfo.first.getValueType())) {
3728 default: assert(0 && "Unknown thing");
3730 Result = CallInfo.first;
3733 ExpandOp(CallInfo.first, Result, Hi);
3740 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3741 /// destination type is legal.
3742 SDOperand SelectionDAGLegalize::
3743 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3744 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3745 assert(getTypeAction(Source.getValueType()) == Expand &&
3746 "This is not an expansion!");
3747 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3750 assert(Source.getValueType() == MVT::i64 &&
3751 "This only works for 64-bit -> FP");
3752 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3753 // incoming integer is set. To handle this, we dynamically test to see if
3754 // it is set, and, if so, add a fudge factor.
3756 ExpandOp(Source, Lo, Hi);
3758 // If this is unsigned, and not supported, first perform the conversion to
3759 // signed, then adjust the result if the sign bit is set.
3760 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3761 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3763 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3764 DAG.getConstant(0, Hi.getValueType()),
3766 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3767 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3768 SignSet, Four, Zero);
3769 uint64_t FF = 0x5f800000ULL;
3770 if (TLI.isLittleEndian()) FF <<= 32;
3771 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3773 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3774 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3775 SDOperand FudgeInReg;
3776 if (DestTy == MVT::f32)
3777 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3778 DAG.getSrcValue(NULL));
3780 assert(DestTy == MVT::f64 && "Unexpected conversion");
3781 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3782 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
3784 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3787 // Check to see if the target has a custom way to lower this. If so, use it.
3788 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3789 default: assert(0 && "This action not implemented for this operation!");
3790 case TargetLowering::Legal:
3791 case TargetLowering::Expand:
3792 break; // This case is handled below.
3793 case TargetLowering::Custom: {
3794 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3797 return LegalizeOp(NV);
3798 break; // The target decided this was legal after all
3802 // Expand the source, then glue it back together for the call. We must expand
3803 // the source in case it is shared (this pass of legalize must traverse it).
3804 SDOperand SrcLo, SrcHi;
3805 ExpandOp(Source, SrcLo, SrcHi);
3806 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
3808 const char *FnName = 0;
3809 if (DestTy == MVT::f32)
3810 FnName = "__floatdisf";
3812 assert(DestTy == MVT::f64 && "Unknown fp value type!");
3813 FnName = "__floatdidf";
3816 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
3817 SDOperand UnusedHiPart;
3818 return ExpandLibCall(FnName, Source.Val, UnusedHiPart);
3821 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
3822 /// INT_TO_FP operation of the specified operand when the target requests that
3823 /// we expand it. At this point, we know that the result and operand types are
3824 /// legal for the target.
3825 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
3827 MVT::ValueType DestVT) {
3828 if (Op0.getValueType() == MVT::i32) {
3829 // simple 32-bit [signed|unsigned] integer to float/double expansion
3831 // get the stack frame index of a 8 byte buffer
3832 MachineFunction &MF = DAG.getMachineFunction();
3833 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3834 // get address of 8 byte buffer
3835 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3836 // word offset constant for Hi/Lo address computation
3837 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
3838 // set up Hi and Lo (into buffer) address based on endian
3839 SDOperand Hi = StackSlot;
3840 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
3841 if (TLI.isLittleEndian())
3844 // if signed map to unsigned space
3845 SDOperand Op0Mapped;
3847 // constant used to invert sign bit (signed to unsigned mapping)
3848 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
3849 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
3853 // store the lo of the constructed double - based on integer input
3854 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3855 Op0Mapped, Lo, DAG.getSrcValue(NULL));
3856 // initial hi portion of constructed double
3857 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
3858 // store the hi of the constructed double - biased exponent
3859 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
3860 InitialHi, Hi, DAG.getSrcValue(NULL));
3861 // load the constructed double
3862 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
3863 DAG.getSrcValue(NULL));
3864 // FP constant to bias correct the final result
3865 SDOperand Bias = DAG.getConstantFP(isSigned ?
3866 BitsToDouble(0x4330000080000000ULL)
3867 : BitsToDouble(0x4330000000000000ULL),
3869 // subtract the bias
3870 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
3873 // handle final rounding
3874 if (DestVT == MVT::f64) {
3878 // if f32 then cast to f32
3879 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
3883 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
3884 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
3886 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
3887 DAG.getConstant(0, Op0.getValueType()),
3889 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3890 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3891 SignSet, Four, Zero);
3893 // If the sign bit of the integer is set, the large number will be treated
3894 // as a negative number. To counteract this, the dynamic code adds an
3895 // offset depending on the data type.
3897 switch (Op0.getValueType()) {
3898 default: assert(0 && "Unsupported integer type!");
3899 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
3900 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
3901 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
3902 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
3904 if (TLI.isLittleEndian()) FF <<= 32;
3905 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3907 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3908 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3909 SDOperand FudgeInReg;
3910 if (DestVT == MVT::f32)
3911 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3912 DAG.getSrcValue(NULL));
3914 assert(DestVT == MVT::f64 && "Unexpected conversion");
3915 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
3916 DAG.getEntryNode(), CPIdx,
3917 DAG.getSrcValue(NULL), MVT::f32));
3920 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
3923 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
3924 /// *INT_TO_FP operation of the specified operand when the target requests that
3925 /// we promote it. At this point, we know that the result and operand types are
3926 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
3927 /// operation that takes a larger input.
3928 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
3929 MVT::ValueType DestVT,
3931 // First step, figure out the appropriate *INT_TO_FP operation to use.
3932 MVT::ValueType NewInTy = LegalOp.getValueType();
3934 unsigned OpToUse = 0;
3936 // Scan for the appropriate larger type to use.
3938 NewInTy = (MVT::ValueType)(NewInTy+1);
3939 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
3941 // If the target supports SINT_TO_FP of this type, use it.
3942 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
3944 case TargetLowering::Legal:
3945 if (!TLI.isTypeLegal(NewInTy))
3946 break; // Can't use this datatype.
3948 case TargetLowering::Custom:
3949 OpToUse = ISD::SINT_TO_FP;
3953 if (isSigned) continue;
3955 // If the target supports UINT_TO_FP of this type, use it.
3956 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
3958 case TargetLowering::Legal:
3959 if (!TLI.isTypeLegal(NewInTy))
3960 break; // Can't use this datatype.
3962 case TargetLowering::Custom:
3963 OpToUse = ISD::UINT_TO_FP;
3968 // Otherwise, try a larger type.
3971 // Okay, we found the operation and type to use. Zero extend our input to the
3972 // desired type then run the operation on it.
3973 return DAG.getNode(OpToUse, DestVT,
3974 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
3978 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
3979 /// FP_TO_*INT operation of the specified operand when the target requests that
3980 /// we promote it. At this point, we know that the result and operand types are
3981 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
3982 /// operation that returns a larger result.
3983 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
3984 MVT::ValueType DestVT,
3986 // First step, figure out the appropriate FP_TO*INT operation to use.
3987 MVT::ValueType NewOutTy = DestVT;
3989 unsigned OpToUse = 0;
3991 // Scan for the appropriate larger type to use.
3993 NewOutTy = (MVT::ValueType)(NewOutTy+1);
3994 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
3996 // If the target supports FP_TO_SINT returning this type, use it.
3997 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
3999 case TargetLowering::Legal:
4000 if (!TLI.isTypeLegal(NewOutTy))
4001 break; // Can't use this datatype.
4003 case TargetLowering::Custom:
4004 OpToUse = ISD::FP_TO_SINT;
4009 // If the target supports FP_TO_UINT of this type, use it.
4010 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4012 case TargetLowering::Legal:
4013 if (!TLI.isTypeLegal(NewOutTy))
4014 break; // Can't use this datatype.
4016 case TargetLowering::Custom:
4017 OpToUse = ISD::FP_TO_UINT;
4022 // Otherwise, try a larger type.
4025 // Okay, we found the operation and type to use. Truncate the result of the
4026 // extended FP_TO_*INT operation to the desired size.
4027 return DAG.getNode(ISD::TRUNCATE, DestVT,
4028 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4031 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4033 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4034 MVT::ValueType VT = Op.getValueType();
4035 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4036 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4038 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4040 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4041 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4042 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4044 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4045 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4046 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4047 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4048 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4049 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4050 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4051 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4052 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4054 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4055 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4056 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4057 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4058 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4059 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4060 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4061 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4062 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4063 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4064 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4065 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4066 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4067 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4068 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4069 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4070 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4071 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4072 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4073 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4074 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4078 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4080 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4082 default: assert(0 && "Cannot expand this yet!");
4084 static const uint64_t mask[6] = {
4085 0x5555555555555555ULL, 0x3333333333333333ULL,
4086 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4087 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4089 MVT::ValueType VT = Op.getValueType();
4090 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4091 unsigned len = getSizeInBits(VT);
4092 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4093 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4094 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4095 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4096 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4097 DAG.getNode(ISD::AND, VT,
4098 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4103 // for now, we do this:
4104 // x = x | (x >> 1);
4105 // x = x | (x >> 2);
4107 // x = x | (x >>16);
4108 // x = x | (x >>32); // for 64-bit input
4109 // return popcount(~x);
4111 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4112 MVT::ValueType VT = Op.getValueType();
4113 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4114 unsigned len = getSizeInBits(VT);
4115 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4116 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4117 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4119 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4120 return DAG.getNode(ISD::CTPOP, VT, Op);
4123 // for now, we use: { return popcount(~x & (x - 1)); }
4124 // unless the target has ctlz but not ctpop, in which case we use:
4125 // { return 32 - nlz(~x & (x-1)); }
4126 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4127 MVT::ValueType VT = Op.getValueType();
4128 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4129 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4130 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4131 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4132 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4133 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4134 TLI.isOperationLegal(ISD::CTLZ, VT))
4135 return DAG.getNode(ISD::SUB, VT,
4136 DAG.getConstant(getSizeInBits(VT), VT),
4137 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4138 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4143 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4144 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4145 /// LegalizeNodes map is filled in for any results that are not expanded, the
4146 /// ExpandedNodes map is filled in for any results that are expanded, and the
4147 /// Lo/Hi values are returned.
4148 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4149 MVT::ValueType VT = Op.getValueType();
4150 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4151 SDNode *Node = Op.Val;
4152 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4153 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
4154 "Cannot expand FP values!");
4155 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
4156 "Cannot expand to FP value or to larger int value!");
4158 // See if we already expanded it.
4159 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4160 = ExpandedNodes.find(Op);
4161 if (I != ExpandedNodes.end()) {
4162 Lo = I->second.first;
4163 Hi = I->second.second;
4167 switch (Node->getOpcode()) {
4168 case ISD::CopyFromReg:
4169 assert(0 && "CopyFromReg must be legal!");
4171 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
4172 assert(0 && "Do not know how to expand this operator!");
4175 Lo = DAG.getNode(ISD::UNDEF, NVT);
4176 Hi = DAG.getNode(ISD::UNDEF, NVT);
4178 case ISD::Constant: {
4179 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4180 Lo = DAG.getConstant(Cst, NVT);
4181 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4184 case ISD::BUILD_PAIR:
4185 // Return the operands.
4186 Lo = Node->getOperand(0);
4187 Hi = Node->getOperand(1);
4190 case ISD::SIGN_EXTEND_INREG:
4191 ExpandOp(Node->getOperand(0), Lo, Hi);
4192 // Sign extend the lo-part.
4193 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4194 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4195 TLI.getShiftAmountTy()));
4196 // sext_inreg the low part if needed.
4197 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4201 ExpandOp(Node->getOperand(0), Lo, Hi);
4202 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4203 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4209 ExpandOp(Node->getOperand(0), Lo, Hi);
4210 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4211 DAG.getNode(ISD::CTPOP, NVT, Lo),
4212 DAG.getNode(ISD::CTPOP, NVT, Hi));
4213 Hi = DAG.getConstant(0, NVT);
4217 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4218 ExpandOp(Node->getOperand(0), Lo, Hi);
4219 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4220 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4221 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4223 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4224 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4226 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4227 Hi = DAG.getConstant(0, NVT);
4232 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4233 ExpandOp(Node->getOperand(0), Lo, Hi);
4234 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4235 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4236 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4238 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4239 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4241 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4242 Hi = DAG.getConstant(0, NVT);
4247 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4248 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4249 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4250 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4252 // Remember that we legalized the chain.
4253 Hi = LegalizeOp(Hi);
4254 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4255 if (!TLI.isLittleEndian())
4261 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4262 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4263 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
4265 // Increment the pointer to the other half.
4266 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4267 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4268 getIntPtrConstant(IncrementSize));
4269 // FIXME: This creates a bogus srcvalue!
4270 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
4272 // Build a factor node to remember that this load is independent of the
4274 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4277 // Remember that we legalized the chain.
4278 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4279 if (!TLI.isLittleEndian())
4285 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
4286 SDOperand LL, LH, RL, RH;
4287 ExpandOp(Node->getOperand(0), LL, LH);
4288 ExpandOp(Node->getOperand(1), RL, RH);
4289 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4290 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4294 SDOperand LL, LH, RL, RH;
4295 ExpandOp(Node->getOperand(1), LL, LH);
4296 ExpandOp(Node->getOperand(2), RL, RH);
4297 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4298 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4301 case ISD::SELECT_CC: {
4302 SDOperand TL, TH, FL, FH;
4303 ExpandOp(Node->getOperand(2), TL, TH);
4304 ExpandOp(Node->getOperand(3), FL, FH);
4305 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4306 Node->getOperand(1), TL, FL, Node->getOperand(4));
4307 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4308 Node->getOperand(1), TH, FH, Node->getOperand(4));
4311 case ISD::SEXTLOAD: {
4312 SDOperand Chain = Node->getOperand(0);
4313 SDOperand Ptr = Node->getOperand(1);
4314 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4317 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4319 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4322 // Remember that we legalized the chain.
4323 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4325 // The high part is obtained by SRA'ing all but one of the bits of the lo
4327 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4328 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
4329 TLI.getShiftAmountTy()));
4332 case ISD::ZEXTLOAD: {
4333 SDOperand Chain = Node->getOperand(0);
4334 SDOperand Ptr = Node->getOperand(1);
4335 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4338 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4340 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4343 // Remember that we legalized the chain.
4344 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4346 // The high part is just a zero.
4347 Hi = DAG.getConstant(0, NVT);
4350 case ISD::EXTLOAD: {
4351 SDOperand Chain = Node->getOperand(0);
4352 SDOperand Ptr = Node->getOperand(1);
4353 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4356 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4358 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4361 // Remember that we legalized the chain.
4362 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4364 // The high part is undefined.
4365 Hi = DAG.getNode(ISD::UNDEF, NVT);
4368 case ISD::ANY_EXTEND:
4369 // The low part is any extension of the input (which degenerates to a copy).
4370 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4371 // The high part is undefined.
4372 Hi = DAG.getNode(ISD::UNDEF, NVT);
4374 case ISD::SIGN_EXTEND: {
4375 // The low part is just a sign extension of the input (which degenerates to
4377 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4379 // The high part is obtained by SRA'ing all but one of the bits of the lo
4381 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4382 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4383 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4386 case ISD::ZERO_EXTEND:
4387 // The low part is just a zero extension of the input (which degenerates to
4389 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4391 // The high part is just a zero.
4392 Hi = DAG.getConstant(0, NVT);
4395 case ISD::BIT_CONVERT: {
4396 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0),
4397 Node->getOperand(0));
4398 ExpandOp(Tmp, Lo, Hi);
4402 case ISD::READCYCLECOUNTER:
4403 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
4404 TargetLowering::Custom &&
4405 "Must custom expand ReadCycleCounter");
4406 Lo = TLI.LowerOperation(Op, DAG);
4407 assert(Lo.Val && "Node must be custom expanded!");
4408 Hi = Lo.getValue(1);
4409 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
4410 LegalizeOp(Lo.getValue(2)));
4413 // These operators cannot be expanded directly, emit them as calls to
4414 // library functions.
4415 case ISD::FP_TO_SINT:
4416 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
4418 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4419 case Expand: assert(0 && "cannot expand FP!");
4420 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4421 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4424 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
4426 // Now that the custom expander is done, expand the result, which is still
4429 ExpandOp(Op, Lo, Hi);
4434 if (Node->getOperand(0).getValueType() == MVT::f32)
4435 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
4437 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
4440 case ISD::FP_TO_UINT:
4441 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
4443 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4444 case Expand: assert(0 && "cannot expand FP!");
4445 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4446 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4449 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
4451 // Now that the custom expander is done, expand the result.
4453 ExpandOp(Op, Lo, Hi);
4458 if (Node->getOperand(0).getValueType() == MVT::f32)
4459 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
4461 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
4465 // If the target wants custom lowering, do so.
4466 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4467 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
4468 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
4469 Op = TLI.LowerOperation(Op, DAG);
4471 // Now that the custom expander is done, expand the result, which is
4473 ExpandOp(Op, Lo, Hi);
4478 // If we can emit an efficient shift operation, do so now.
4479 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4482 // If this target supports SHL_PARTS, use it.
4483 TargetLowering::LegalizeAction Action =
4484 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
4485 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4486 Action == TargetLowering::Custom) {
4487 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4491 // Otherwise, emit a libcall.
4492 Lo = ExpandLibCall("__ashldi3", Node, Hi);
4497 // If the target wants custom lowering, do so.
4498 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4499 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
4500 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
4501 Op = TLI.LowerOperation(Op, DAG);
4503 // Now that the custom expander is done, expand the result, which is
4505 ExpandOp(Op, Lo, Hi);
4510 // If we can emit an efficient shift operation, do so now.
4511 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
4514 // If this target supports SRA_PARTS, use it.
4515 TargetLowering::LegalizeAction Action =
4516 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
4517 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4518 Action == TargetLowering::Custom) {
4519 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4523 // Otherwise, emit a libcall.
4524 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
4529 // If the target wants custom lowering, do so.
4530 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4531 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
4532 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
4533 Op = TLI.LowerOperation(Op, DAG);
4535 // Now that the custom expander is done, expand the result, which is
4537 ExpandOp(Op, Lo, Hi);
4542 // If we can emit an efficient shift operation, do so now.
4543 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4546 // If this target supports SRL_PARTS, use it.
4547 TargetLowering::LegalizeAction Action =
4548 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
4549 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4550 Action == TargetLowering::Custom) {
4551 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4555 // Otherwise, emit a libcall.
4556 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
4562 // If the target wants to custom expand this, let them.
4563 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
4564 TargetLowering::Custom) {
4565 Op = TLI.LowerOperation(Op, DAG);
4567 ExpandOp(Op, Lo, Hi);
4572 // Expand the subcomponents.
4573 SDOperand LHSL, LHSH, RHSL, RHSH;
4574 ExpandOp(Node->getOperand(0), LHSL, LHSH);
4575 ExpandOp(Node->getOperand(1), RHSL, RHSH);
4576 std::vector<MVT::ValueType> VTs;
4577 std::vector<SDOperand> LoOps, HiOps;
4578 VTs.push_back(LHSL.getValueType());
4579 VTs.push_back(MVT::Flag);
4580 LoOps.push_back(LHSL);
4581 LoOps.push_back(RHSL);
4582 HiOps.push_back(LHSH);
4583 HiOps.push_back(RHSH);
4584 if (Node->getOpcode() == ISD::ADD) {
4585 Lo = DAG.getNode(ISD::ADDC, VTs, LoOps);
4586 HiOps.push_back(Lo.getValue(1));
4587 Hi = DAG.getNode(ISD::ADDE, VTs, HiOps);
4589 Lo = DAG.getNode(ISD::SUBC, VTs, LoOps);
4590 HiOps.push_back(Lo.getValue(1));
4591 Hi = DAG.getNode(ISD::SUBE, VTs, HiOps);
4596 if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
4597 SDOperand LL, LH, RL, RH;
4598 ExpandOp(Node->getOperand(0), LL, LH);
4599 ExpandOp(Node->getOperand(1), RL, RH);
4600 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
4601 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
4602 // extended the sign bit of the low half through the upper half, and if so
4603 // emit a MULHS instead of the alternate sequence that is valid for any
4604 // i64 x i64 multiply.
4605 if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
4606 // is RH an extension of the sign bit of RL?
4607 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
4608 RH.getOperand(1).getOpcode() == ISD::Constant &&
4609 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
4610 // is LH an extension of the sign bit of LL?
4611 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
4612 LH.getOperand(1).getOpcode() == ISD::Constant &&
4613 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
4614 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
4616 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
4617 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
4618 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
4619 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
4620 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
4622 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4624 Lo = ExpandLibCall("__muldi3" , Node, Hi);
4628 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
4629 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
4630 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
4631 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
4634 // Make sure the resultant values have been legalized themselves, unless this
4635 // is a type that requires multi-step expansion.
4636 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
4637 Lo = LegalizeOp(Lo);
4638 Hi = LegalizeOp(Hi);
4641 // Remember in a map if the values will be reused later.
4643 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4644 assert(isNew && "Value already expanded?!?");
4647 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
4648 /// two smaller values of MVT::Vector type.
4649 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
4651 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
4652 SDNode *Node = Op.Val;
4653 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
4654 assert(NumElements > 1 && "Cannot split a single element vector!");
4655 unsigned NewNumElts = NumElements/2;
4656 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
4657 SDOperand TypeNode = *(Node->op_end()-1);
4659 // See if we already split it.
4660 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4661 = SplitNodes.find(Op);
4662 if (I != SplitNodes.end()) {
4663 Lo = I->second.first;
4664 Hi = I->second.second;
4668 switch (Node->getOpcode()) {
4669 default: Node->dump(); assert(0 && "Unhandled operation in SplitVectorOp!");
4670 case ISD::VBUILD_VECTOR: {
4671 std::vector<SDOperand> LoOps(Node->op_begin(), Node->op_begin()+NewNumElts);
4672 LoOps.push_back(NewNumEltsNode);
4673 LoOps.push_back(TypeNode);
4674 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, LoOps);
4676 std::vector<SDOperand> HiOps(Node->op_begin()+NewNumElts, Node->op_end()-2);
4677 HiOps.push_back(NewNumEltsNode);
4678 HiOps.push_back(TypeNode);
4679 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, HiOps);
4690 SDOperand LL, LH, RL, RH;
4691 SplitVectorOp(Node->getOperand(0), LL, LH);
4692 SplitVectorOp(Node->getOperand(1), RL, RH);
4694 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
4695 NewNumEltsNode, TypeNode);
4696 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
4697 NewNumEltsNode, TypeNode);
4701 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4702 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4703 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4705 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4706 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
4707 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4708 getIntPtrConstant(IncrementSize));
4709 // FIXME: This creates a bogus srcvalue!
4710 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4712 // Build a factor node to remember that this load is independent of the
4714 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4717 // Remember that we legalized the chain.
4718 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4721 case ISD::VBIT_CONVERT: {
4722 // We know the result is a vector. The input may be either a vector or a
4724 if (Op.getOperand(0).getValueType() != MVT::Vector) {
4725 // Lower to a store/load. FIXME: this could be improved probably.
4726 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
4728 SDOperand St = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
4729 Op.getOperand(0), Ptr, DAG.getSrcValue(0));
4730 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4731 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0));
4732 SplitVectorOp(St, Lo, Hi);
4734 // If the input is a vector type, we have to either scalarize it, pack it
4735 // or convert it based on whether the input vector type is legal.
4736 SDNode *InVal = Node->getOperand(0).Val;
4738 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
4739 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
4741 // If the input is from a single element vector, scalarize the vector,
4742 // then treat like a scalar.
4743 if (NumElems == 1) {
4744 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT);
4745 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar,
4746 Op.getOperand(1), Op.getOperand(2));
4747 SplitVectorOp(Scalar, Lo, Hi);
4749 // Split the input vector.
4750 SplitVectorOp(Op.getOperand(0), Lo, Hi);
4752 // Convert each of the pieces now.
4753 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo,
4754 NewNumEltsNode, TypeNode);
4755 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi,
4756 NewNumEltsNode, TypeNode);
4763 // Remember in a map if the values will be reused later.
4765 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4766 assert(isNew && "Value already expanded?!?");
4770 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
4771 /// equivalent operation that returns a scalar (e.g. F32) or packed value
4772 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
4773 /// type for the result.
4774 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
4775 MVT::ValueType NewVT) {
4776 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
4777 SDNode *Node = Op.Val;
4779 // See if we already packed it.
4780 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
4781 if (I != PackedNodes.end()) return I->second;
4784 switch (Node->getOpcode()) {
4786 Node->dump(); std::cerr << "\n";
4787 assert(0 && "Unknown vector operation in PackVectorOp!");
4796 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
4798 PackVectorOp(Node->getOperand(0), NewVT),
4799 PackVectorOp(Node->getOperand(1), NewVT));
4802 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
4803 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
4805 Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(2));
4807 // Remember that we legalized the chain.
4808 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4811 case ISD::VBUILD_VECTOR:
4812 if (Node->getOperand(0).getValueType() == NewVT) {
4813 // Returning a scalar?
4814 Result = Node->getOperand(0);
4816 // Returning a BUILD_VECTOR?
4818 // If all elements of the build_vector are undefs, return an undef.
4819 bool AllUndef = true;
4820 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i)
4821 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) {
4826 Result = DAG.getNode(ISD::UNDEF, NewVT);
4828 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()-2);
4829 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops);
4833 case ISD::VINSERT_VECTOR_ELT:
4834 if (!MVT::isVector(NewVT)) {
4835 // Returning a scalar? Must be the inserted element.
4836 Result = Node->getOperand(1);
4838 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
4839 PackVectorOp(Node->getOperand(0), NewVT),
4840 Node->getOperand(1), Node->getOperand(2));
4843 case ISD::VVECTOR_SHUFFLE:
4844 if (!MVT::isVector(NewVT)) {
4845 // Returning a scalar? Figure out if it is the LHS or RHS and return it.
4846 SDOperand EltNum = Node->getOperand(2).getOperand(0);
4847 if (cast<ConstantSDNode>(EltNum)->getValue())
4848 Result = PackVectorOp(Node->getOperand(1), NewVT);
4850 Result = PackVectorOp(Node->getOperand(0), NewVT);
4852 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index
4853 // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
4854 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
4855 Node->getOperand(2).Val->op_end()-2);
4856 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
4857 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT, BuildVecIdx);
4859 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
4860 PackVectorOp(Node->getOperand(0), NewVT),
4861 PackVectorOp(Node->getOperand(1), NewVT), BV);
4864 case ISD::VBIT_CONVERT:
4865 if (Op.getOperand(0).getValueType() != MVT::Vector)
4866 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
4868 // If the input is a vector type, we have to either scalarize it, pack it
4869 // or convert it based on whether the input vector type is legal.
4870 SDNode *InVal = Node->getOperand(0).Val;
4872 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
4873 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
4875 // Figure out if there is a Packed type corresponding to this Vector
4876 // type. If so, convert to the packed type.
4877 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
4878 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
4879 // Turn this into a bit convert of the packed input.
4880 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
4881 PackVectorOp(Node->getOperand(0), TVT));
4883 } else if (NumElems == 1) {
4884 // Turn this into a bit convert of the scalar input.
4885 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
4886 PackVectorOp(Node->getOperand(0), EVT));
4890 assert(0 && "Cast from unsupported vector type not implemented yet!");
4895 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
4896 PackVectorOp(Op.getOperand(1), NewVT),
4897 PackVectorOp(Op.getOperand(2), NewVT));
4901 if (TLI.isTypeLegal(NewVT))
4902 Result = LegalizeOp(Result);
4903 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
4904 assert(isNew && "Value already packed?");
4909 // SelectionDAG::Legalize - This is the entry point for the file.
4911 void SelectionDAG::Legalize() {
4912 if (ViewLegalizeDAGs) viewGraph();
4914 /// run - This is the main entry point to this class.
4916 SelectionDAGLegalize(*this).LegalizeDAG();