1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/DwarfWriter.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetSubtarget.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/DerivedTypes.h"
31 #include "llvm/Function.h"
32 #include "llvm/GlobalVariable.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/ADT/DenseMap.h"
37 #include "llvm/ADT/SmallVector.h"
38 #include "llvm/ADT/SmallPtrSet.h"
42 //===----------------------------------------------------------------------===//
43 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class VISIBILITY_HIDDEN SelectionDAGLegalize {
58 bool TypesNeedLegalizing;
61 // Libcall insertion helpers.
63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
64 /// legalized. We use this to ensure that calls are properly serialized
65 /// against each other, including inserted libcalls.
66 SDValue LastCALLSEQ_END;
68 /// IsLegalizingCall - This member is used *only* for purposes of providing
69 /// helpful assertions that a libcall isn't created while another call is
70 /// being legalized (which could lead to non-serialized call sequences).
71 bool IsLegalizingCall;
73 /// IsLegalizingCallArguments - This member is used only for the purpose
74 /// of providing assert to check for LegalizeTypes because legalizing an
75 /// operation might introduce call nodes that might need type legalization.
76 bool IsLegalizingCallArgs;
79 Legal, // The target natively supports this operation.
80 Promote, // This operation should be executed in a larger type.
81 Expand // Try to expand this to other ops, otherwise use a libcall.
84 /// ValueTypeActions - This is a bitvector that contains two bits for each
85 /// value type, where the two bits correspond to the LegalizeAction enum.
86 /// This can be queried with "getTypeAction(VT)".
87 TargetLowering::ValueTypeActionImpl ValueTypeActions;
89 /// LegalizedNodes - For nodes that are of legal width, and that have more
90 /// than one use, this map indicates what regularized operand to use. This
91 /// allows us to avoid legalizing the same thing more than once.
92 DenseMap<SDValue, SDValue> LegalizedNodes;
94 /// PromotedNodes - For nodes that are below legal width, and that have more
95 /// than one use, this map indicates what promoted value to use. This allows
96 /// us to avoid promoting the same thing more than once.
97 DenseMap<SDValue, SDValue> PromotedNodes;
99 /// ExpandedNodes - For nodes that need to be expanded this map indicates
100 /// which operands are the expanded version of the input. This allows
101 /// us to avoid expanding the same node more than once.
102 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
104 /// SplitNodes - For vector nodes that need to be split, this map indicates
105 /// which operands are the split version of the input. This allows us
106 /// to avoid splitting the same node more than once.
107 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
109 /// ScalarizedNodes - For nodes that need to be converted from vector types to
110 /// scalar types, this contains the mapping of ones we have already
111 /// processed to the result.
112 std::map<SDValue, SDValue> ScalarizedNodes;
114 /// WidenNodes - For nodes that need to be widened from one vector type to
115 /// another, this contains the mapping of those that we have already widen.
116 /// This allows us to avoid widening more than once.
117 std::map<SDValue, SDValue> WidenNodes;
119 void AddLegalizedOperand(SDValue From, SDValue To) {
120 LegalizedNodes.insert(std::make_pair(From, To));
121 // If someone requests legalization of the new node, return itself.
123 LegalizedNodes.insert(std::make_pair(To, To));
125 void AddPromotedOperand(SDValue From, SDValue To) {
126 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
127 assert(isNew && "Got into the map somehow?");
129 // If someone requests legalization of the new node, return itself.
130 LegalizedNodes.insert(std::make_pair(To, To));
132 void AddWidenedOperand(SDValue From, SDValue To) {
133 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second;
134 assert(isNew && "Got into the map somehow?");
136 // If someone requests legalization of the new node, return itself.
137 LegalizedNodes.insert(std::make_pair(To, To));
141 explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing,
144 /// getTypeAction - Return how we should legalize values of this type, either
145 /// it is already legal or we need to expand it into multiple registers of
146 /// smaller integer type, or we need to promote it to a larger type.
147 LegalizeAction getTypeAction(MVT VT) const {
148 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
151 /// isTypeLegal - Return true if this type is legal on this target.
153 bool isTypeLegal(MVT VT) const {
154 return getTypeAction(VT) == Legal;
160 /// HandleOp - Legalize, Promote, or Expand the specified operand as
161 /// appropriate for its type.
162 void HandleOp(SDValue Op);
164 /// LegalizeOp - We know that the specified value has a legal type.
165 /// Recursively ensure that the operands have legal types, then return the
167 SDValue LegalizeOp(SDValue O);
169 /// UnrollVectorOp - We know that the given vector has a legal type, however
170 /// the operation it performs is not legal and is an operation that we have
171 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
172 /// operating on each element individually.
173 SDValue UnrollVectorOp(SDValue O);
175 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
176 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
177 /// is necessary to spill the vector being inserted into to memory, perform
178 /// the insert there, and then read the result back.
179 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
180 SDValue Idx, DebugLoc dl);
182 /// PromoteOp - Given an operation that produces a value in an invalid type,
183 /// promote it to compute the value into a larger type. The produced value
184 /// will have the correct bits for the low portion of the register, but no
185 /// guarantee is made about the top bits: it may be zero, sign-extended, or
187 SDValue PromoteOp(SDValue O);
189 /// ExpandOp - Expand the specified SDValue into its two component pieces
190 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
191 /// the LegalizedNodes map is filled in for any results that are not expanded,
192 /// the ExpandedNodes map is filled in for any results that are expanded, and
193 /// the Lo/Hi values are returned. This applies to integer types and Vector
195 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
197 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
198 /// (e.g., v3i32 to v4i32). The produced value will have the correct value
199 /// for the existing elements but no guarantee is made about the new elements
200 /// at the end of the vector: it may be zero, ones, or garbage. This is useful
201 /// when we have an instruction operating on an illegal vector type and we
202 /// want to widen it to do the computation on a legal wider vector type.
203 SDValue WidenVectorOp(SDValue Op, MVT WidenVT);
205 /// SplitVectorOp - Given an operand of vector type, break it down into
206 /// two smaller values.
207 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
209 /// ScalarizeVectorOp - Given an operand of single-element vector type
210 /// (e.g. v1f32), convert it into the equivalent operation that returns a
211 /// scalar (e.g. f32) value.
212 SDValue ScalarizeVectorOp(SDValue O);
214 /// Useful 16 element vector type that is used to pass operands for widening.
215 typedef SmallVector<SDValue, 16> SDValueVector;
217 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if
218 /// the LdChain contains a single load and false if it contains a token
219 /// factor for multiple loads. It takes
220 /// Result: location to return the result
221 /// LdChain: location to return the load chain
222 /// Op: load operation to widen
223 /// NVT: widen vector result type we want for the load
224 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
225 SDValue Op, MVT NVT);
227 /// Helper genWidenVectorLoads - Helper function to generate a set of
228 /// loads to load a vector with a resulting wider type. It takes
229 /// LdChain: list of chains for the load we have generated
230 /// Chain: incoming chain for the ld vector
231 /// BasePtr: base pointer to load from
232 /// SV: memory disambiguation source value
233 /// SVOffset: memory disambiugation offset
234 /// Alignment: alignment of the memory
235 /// isVolatile: volatile load
236 /// LdWidth: width of memory that we want to load
237 /// ResType: the wider result result type for the resulting loaded vector
238 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain,
239 SDValue BasePtr, const Value *SV,
240 int SVOffset, unsigned Alignment,
241 bool isVolatile, unsigned LdWidth,
242 MVT ResType, DebugLoc dl);
244 /// StoreWidenVectorOp - Stores a widen vector into non widen memory
245 /// location. It takes
246 /// ST: store node that we want to replace
247 /// Chain: incoming store chain
248 /// BasePtr: base address of where we want to store into
249 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
252 /// Helper genWidenVectorStores - Helper function to generate a set of
253 /// stores to store a widen vector into non widen memory
255 // StChain: list of chains for the stores we have generated
256 // Chain: incoming chain for the ld vector
257 // BasePtr: base pointer to load from
258 // SV: memory disambiguation source value
259 // SVOffset: memory disambiugation offset
260 // Alignment: alignment of the memory
261 // isVolatile: volatile lod
262 // ValOp: value to store
263 // StWidth: width of memory that we want to store
264 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain,
265 SDValue BasePtr, const Value *SV,
266 int SVOffset, unsigned Alignment,
267 bool isVolatile, SDValue ValOp,
268 unsigned StWidth, DebugLoc dl);
270 /// promoteShuffle - Promote a shuffle mask of a vector VT to perform the
271 /// same shuffle on a vector of NVT. Must not create an illegal shuffle mask.
272 SDValue promoteShuffle(MVT NVT, MVT VT, DebugLoc dl, SDValue N1, SDValue N2,
273 SmallVectorImpl<int> &Mask) const;
275 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
276 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
278 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC,
280 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
282 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
284 LegalizeSetCCOperands(LHS, RHS, CC, dl);
285 LegalizeSetCCCondCode(VT, LHS, RHS, CC, dl);
288 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
290 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl);
292 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl);
293 SDValue ExpandBUILD_VECTOR(SDNode *Node);
294 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
295 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy,
296 SDValue Op, DebugLoc dl);
297 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT,
299 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned,
301 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned,
304 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
305 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
306 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
307 SDValue &Lo, SDValue &Hi, DebugLoc dl);
308 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
309 SDValue &Lo, SDValue &Hi, DebugLoc dl);
311 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
312 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
316 /// promoteShuffle - Promote a shuffle mask of a vector VT to perform the
317 /// same shuffle on a vector of NVT. Must not create an illegal shuffle mask.
318 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
319 SDValue SelectionDAGLegalize::promoteShuffle(MVT NVT, MVT VT, DebugLoc dl,
320 SDValue N1, SDValue N2,
321 SmallVectorImpl<int> &Mask) const {
322 MVT EltVT = NVT.getVectorElementType();
323 int NumMaskElts = VT.getVectorNumElements();
324 int NumDestElts = NVT.getVectorNumElements();
325 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
327 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
329 if (NumEltsGrowth == 1)
330 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
332 SmallVector<int, 8> NewMask;
333 for (int i = 0; i != NumMaskElts; ++i) {
335 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
337 NewMask.push_back(-1);
339 NewMask.push_back(Idx * NumEltsGrowth + j);
342 assert((int)NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
343 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
344 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
347 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
348 bool types, bool fast)
349 : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types),
350 Fast(fast), ValueTypeActions(TLI.getValueTypeActions()) {
351 assert(MVT::LAST_VALUETYPE <= 32 &&
352 "Too many value types for ValueTypeActions to hold!");
355 void SelectionDAGLegalize::LegalizeDAG() {
356 LastCALLSEQ_END = DAG.getEntryNode();
357 IsLegalizingCall = false;
358 IsLegalizingCallArgs = false;
360 // The legalize process is inherently a bottom-up recursive process (users
361 // legalize their uses before themselves). Given infinite stack space, we
362 // could just start legalizing on the root and traverse the whole graph. In
363 // practice however, this causes us to run out of stack space on large basic
364 // blocks. To avoid this problem, compute an ordering of the nodes where each
365 // node is only legalized after all of its operands are legalized.
366 DAG.AssignTopologicalOrder();
367 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
368 E = prior(DAG.allnodes_end()); I != next(E); ++I)
369 HandleOp(SDValue(I, 0));
371 // Finally, it's possible the root changed. Get the new root.
372 SDValue OldRoot = DAG.getRoot();
373 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
374 DAG.setRoot(LegalizedNodes[OldRoot]);
376 ExpandedNodes.clear();
377 LegalizedNodes.clear();
378 PromotedNodes.clear();
380 ScalarizedNodes.clear();
383 // Remove dead nodes now.
384 DAG.RemoveDeadNodes();
388 /// FindCallEndFromCallStart - Given a chained node that is part of a call
389 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
390 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
391 if (Node->getOpcode() == ISD::CALLSEQ_END)
393 if (Node->use_empty())
394 return 0; // No CallSeqEnd
396 // The chain is usually at the end.
397 SDValue TheChain(Node, Node->getNumValues()-1);
398 if (TheChain.getValueType() != MVT::Other) {
399 // Sometimes it's at the beginning.
400 TheChain = SDValue(Node, 0);
401 if (TheChain.getValueType() != MVT::Other) {
402 // Otherwise, hunt for it.
403 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
404 if (Node->getValueType(i) == MVT::Other) {
405 TheChain = SDValue(Node, i);
409 // Otherwise, we walked into a node without a chain.
410 if (TheChain.getValueType() != MVT::Other)
415 for (SDNode::use_iterator UI = Node->use_begin(),
416 E = Node->use_end(); UI != E; ++UI) {
418 // Make sure to only follow users of our token chain.
420 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
421 if (User->getOperand(i) == TheChain)
422 if (SDNode *Result = FindCallEndFromCallStart(User))
428 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
429 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
430 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
431 assert(Node && "Didn't find callseq_start for a call??");
432 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
434 assert(Node->getOperand(0).getValueType() == MVT::Other &&
435 "Node doesn't have a token chain argument!");
436 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
439 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
440 /// see if any uses can reach Dest. If no dest operands can get to dest,
441 /// legalize them, legalize ourself, and return false, otherwise, return true.
443 /// Keep track of the nodes we fine that actually do lead to Dest in
444 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
446 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
447 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
448 if (N == Dest) return true; // N certainly leads to Dest :)
450 // If we've already processed this node and it does lead to Dest, there is no
451 // need to reprocess it.
452 if (NodesLeadingTo.count(N)) return true;
454 // If the first result of this node has been already legalized, then it cannot
456 switch (getTypeAction(N->getValueType(0))) {
458 if (LegalizedNodes.count(SDValue(N, 0))) return false;
461 if (PromotedNodes.count(SDValue(N, 0))) return false;
464 if (ExpandedNodes.count(SDValue(N, 0))) return false;
468 // Okay, this node has not already been legalized. Check and legalize all
469 // operands. If none lead to Dest, then we can legalize this node.
470 bool OperandsLeadToDest = false;
471 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
472 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
473 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
475 if (OperandsLeadToDest) {
476 NodesLeadingTo.insert(N);
480 // Okay, this node looks safe, legalize it and return false.
481 HandleOp(SDValue(N, 0));
485 /// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as
486 /// appropriate for its type.
487 void SelectionDAGLegalize::HandleOp(SDValue Op) {
488 MVT VT = Op.getValueType();
489 // If the type legalizer was run then we should never see any illegal result
490 // types here except for target constants (the type legalizer does not touch
491 // those) or for build vector used as a mask for a vector shuffle.
492 assert((TypesNeedLegalizing || getTypeAction(VT) == Legal ||
493 IsLegalizingCallArgs || Op.getOpcode() == ISD::TargetConstant) &&
494 "Illegal type introduced after type legalization?");
495 switch (getTypeAction(VT)) {
496 default: assert(0 && "Bad type action!");
497 case Legal: (void)LegalizeOp(Op); break;
499 if (!VT.isVector()) {
504 // See if we can widen otherwise use Expand to either scalarize or split
505 MVT WidenVT = TLI.getWidenVectorType(VT);
506 if (WidenVT != MVT::Other) {
507 (void) WidenVectorOp(Op, WidenVT);
510 // else fall thru to expand since we can't widen the vector
513 if (!VT.isVector()) {
514 // If this is an illegal scalar, expand it into its two component
517 if (Op.getOpcode() == ISD::TargetConstant)
518 break; // Allow illegal target nodes.
520 } else if (VT.getVectorNumElements() == 1) {
521 // If this is an illegal single element vector, convert it to a
523 (void)ScalarizeVectorOp(Op);
525 // This is an illegal multiple element vector.
526 // Split it in half and legalize both parts.
528 SplitVectorOp(Op, X, Y);
534 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
535 /// a load from the constant pool.
536 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
537 SelectionDAG &DAG, const TargetLowering &TLI) {
539 DebugLoc dl = CFP->getDebugLoc();
541 // If a FP immediate is precise when represented as a float and if the
542 // target can do an extending load from float to double, we put it into
543 // the constant pool as a float, even if it's is statically typed as a
544 // double. This shrinks FP constants and canonicalizes them for targets where
545 // an FP extending load is the same cost as a normal load (such as on the x87
546 // fp stack or PPC FP unit).
547 MVT VT = CFP->getValueType(0);
548 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
550 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
551 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
552 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
557 while (SVT != MVT::f32) {
558 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
559 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
560 // Only do this if the target has a native EXTLOAD instruction from
562 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
563 TLI.ShouldShrinkFPConstant(OrigVT)) {
564 const Type *SType = SVT.getTypeForMVT();
565 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
571 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
572 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
574 return DAG.getExtLoad(ISD::EXTLOAD, dl,
575 OrigVT, DAG.getEntryNode(),
576 CPIdx, PseudoSourceValue::getConstantPool(),
577 0, VT, false, Alignment);
578 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
579 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
583 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
586 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
588 const TargetLowering &TLI) {
589 DebugLoc dl = Node->getDebugLoc();
590 MVT VT = Node->getValueType(0);
591 MVT SrcVT = Node->getOperand(1).getValueType();
592 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
593 "fcopysign expansion only supported for f32 and f64");
594 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
596 // First get the sign bit of second operand.
597 SDValue Mask1 = (SrcVT == MVT::f64)
598 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
599 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
600 Mask1 = DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT, Mask1);
601 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT,
602 Node->getOperand(1));
603 SignBit = DAG.getNode(ISD::AND, dl, SrcNVT, SignBit, Mask1);
604 // Shift right or sign-extend it if the two operands have different types.
605 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
607 SignBit = DAG.getNode(ISD::SRL, dl, SrcNVT, SignBit,
608 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
609 SignBit = DAG.getNode(ISD::TRUNCATE, dl, NVT, SignBit);
610 } else if (SizeDiff < 0) {
611 SignBit = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, SignBit);
612 SignBit = DAG.getNode(ISD::SHL, dl, NVT, SignBit,
613 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
616 // Clear the sign bit of first operand.
617 SDValue Mask2 = (VT == MVT::f64)
618 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
619 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
620 Mask2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask2);
621 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
622 Result = DAG.getNode(ISD::AND, dl, NVT, Result, Mask2);
624 // Or the value with the sign bit.
625 Result = DAG.getNode(ISD::OR, dl, NVT, Result, SignBit);
629 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
631 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
632 const TargetLowering &TLI) {
633 SDValue Chain = ST->getChain();
634 SDValue Ptr = ST->getBasePtr();
635 SDValue Val = ST->getValue();
636 MVT VT = Val.getValueType();
637 int Alignment = ST->getAlignment();
638 int SVOffset = ST->getSrcValueOffset();
639 DebugLoc dl = ST->getDebugLoc();
640 if (ST->getMemoryVT().isFloatingPoint() ||
641 ST->getMemoryVT().isVector()) {
642 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
643 if (TLI.isTypeLegal(intVT)) {
644 // Expand to a bitconvert of the value to the integer type of the
645 // same size, then a (misaligned) int store.
646 // FIXME: Does not handle truncating floating point stores!
647 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
648 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
649 SVOffset, ST->isVolatile(), Alignment);
651 // Do a (aligned) store to a stack slot, then copy from the stack slot
652 // to the final destination using (unaligned) integer loads and stores.
653 MVT StoredVT = ST->getMemoryVT();
655 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
656 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
657 unsigned RegBytes = RegVT.getSizeInBits() / 8;
658 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
660 // Make sure the stack slot is also aligned for the register type.
661 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
663 // Perform the original store, only redirected to the stack slot.
664 SDValue Store = DAG.getTruncStore(Chain, dl,
665 Val, StackPtr, NULL, 0, StoredVT);
666 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
667 SmallVector<SDValue, 8> Stores;
670 // Do all but one copies using the full register width.
671 for (unsigned i = 1; i < NumRegs; i++) {
672 // Load one integer register's worth from the stack slot.
673 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0);
674 // Store it to the final location. Remember the store.
675 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
676 ST->getSrcValue(), SVOffset + Offset,
678 MinAlign(ST->getAlignment(), Offset)));
679 // Increment the pointers.
681 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
683 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
686 // The last store may be partial. Do a truncating store. On big-endian
687 // machines this requires an extending load from the stack slot to ensure
688 // that the bits are in the right place.
689 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
691 // Load from the stack slot.
692 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
695 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
696 ST->getSrcValue(), SVOffset + Offset,
697 MemVT, ST->isVolatile(),
698 MinAlign(ST->getAlignment(), Offset)));
699 // The order of the stores doesn't matter - say it with a TokenFactor.
700 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
704 assert(ST->getMemoryVT().isInteger() &&
705 !ST->getMemoryVT().isVector() &&
706 "Unaligned store of unknown type.");
707 // Get the half-size VT
709 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
710 int NumBits = NewStoredVT.getSizeInBits();
711 int IncrementSize = NumBits / 8;
713 // Divide the stored value in two parts.
714 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
716 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
718 // Store the two parts
719 SDValue Store1, Store2;
720 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
721 ST->getSrcValue(), SVOffset, NewStoredVT,
722 ST->isVolatile(), Alignment);
723 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
724 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
725 Alignment = MinAlign(Alignment, IncrementSize);
726 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
727 ST->getSrcValue(), SVOffset + IncrementSize,
728 NewStoredVT, ST->isVolatile(), Alignment);
730 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
733 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
735 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
736 const TargetLowering &TLI) {
737 int SVOffset = LD->getSrcValueOffset();
738 SDValue Chain = LD->getChain();
739 SDValue Ptr = LD->getBasePtr();
740 MVT VT = LD->getValueType(0);
741 MVT LoadedVT = LD->getMemoryVT();
742 DebugLoc dl = LD->getDebugLoc();
743 if (VT.isFloatingPoint() || VT.isVector()) {
744 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
745 if (TLI.isTypeLegal(intVT)) {
746 // Expand to a (misaligned) integer load of the same size,
747 // then bitconvert to floating point or vector.
748 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
749 SVOffset, LD->isVolatile(),
751 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
752 if (VT.isFloatingPoint() && LoadedVT != VT)
753 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
755 SDValue Ops[] = { Result, Chain };
756 return DAG.getMergeValues(Ops, 2, dl);
758 // Copy the value to a (aligned) stack slot using (unaligned) integer
759 // loads and stores, then do a (aligned) load from the stack slot.
760 MVT RegVT = TLI.getRegisterType(intVT);
761 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
762 unsigned RegBytes = RegVT.getSizeInBits() / 8;
763 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
765 // Make sure the stack slot is also aligned for the register type.
766 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
768 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
769 SmallVector<SDValue, 8> Stores;
770 SDValue StackPtr = StackBase;
773 // Do all but one copies using the full register width.
774 for (unsigned i = 1; i < NumRegs; i++) {
775 // Load one integer register's worth from the original location.
776 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
777 SVOffset + Offset, LD->isVolatile(),
778 MinAlign(LD->getAlignment(), Offset));
779 // Follow the load with a store to the stack slot. Remember the store.
780 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
782 // Increment the pointers.
784 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
785 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
789 // The last copy may be partial. Do an extending load.
790 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
791 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
792 LD->getSrcValue(), SVOffset + Offset,
793 MemVT, LD->isVolatile(),
794 MinAlign(LD->getAlignment(), Offset));
795 // Follow the load with a store to the stack slot. Remember the store.
796 // On big-endian machines this requires a truncating store to ensure
797 // that the bits end up in the right place.
798 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
801 // The order of the stores doesn't matter - say it with a TokenFactor.
802 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
805 // Finally, perform the original load only redirected to the stack slot.
806 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
809 // Callers expect a MERGE_VALUES node.
810 SDValue Ops[] = { Load, TF };
811 return DAG.getMergeValues(Ops, 2, dl);
814 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
815 "Unaligned load of unsupported type.");
817 // Compute the new VT that is half the size of the old one. This is an
819 unsigned NumBits = LoadedVT.getSizeInBits();
821 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
824 unsigned Alignment = LD->getAlignment();
825 unsigned IncrementSize = NumBits / 8;
826 ISD::LoadExtType HiExtType = LD->getExtensionType();
828 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
829 if (HiExtType == ISD::NON_EXTLOAD)
830 HiExtType = ISD::ZEXTLOAD;
832 // Load the value in two parts
834 if (TLI.isLittleEndian()) {
835 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
836 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
837 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
838 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
839 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
840 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
841 MinAlign(Alignment, IncrementSize));
843 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
844 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
845 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
846 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
847 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
848 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
849 MinAlign(Alignment, IncrementSize));
852 // aggregate the two parts
853 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
854 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
855 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
857 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
860 SDValue Ops[] = { Result, TF };
861 return DAG.getMergeValues(Ops, 2, dl);
864 /// UnrollVectorOp - We know that the given vector has a legal type, however
865 /// the operation it performs is not legal and is an operation that we have
866 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
867 /// operating on each element individually.
868 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
869 MVT VT = Op.getValueType();
870 assert(isTypeLegal(VT) &&
871 "Caller should expand or promote operands that are not legal!");
872 assert(Op.getNode()->getNumValues() == 1 &&
873 "Can't unroll a vector with multiple results!");
874 unsigned NE = VT.getVectorNumElements();
875 MVT EltVT = VT.getVectorElementType();
876 DebugLoc dl = Op.getDebugLoc();
878 SmallVector<SDValue, 8> Scalars;
879 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
880 for (unsigned i = 0; i != NE; ++i) {
881 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
882 SDValue Operand = Op.getOperand(j);
883 MVT OperandVT = Operand.getValueType();
884 if (OperandVT.isVector()) {
885 // A vector operand; extract a single element.
886 MVT OperandEltVT = OperandVT.getVectorElementType();
887 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
890 DAG.getConstant(i, MVT::i32));
892 // A scalar operand; just use it as is.
893 Operands[j] = Operand;
897 switch (Op.getOpcode()) {
899 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT,
900 &Operands[0], Operands.size()));
907 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, Operands[0],
908 DAG.getShiftAmountOperand(Operands[1])));
913 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Scalars[0], Scalars.size());
916 /// GetFPLibCall - Return the right libcall for the given floating point type.
917 static RTLIB::Libcall GetFPLibCall(MVT VT,
918 RTLIB::Libcall Call_F32,
919 RTLIB::Libcall Call_F64,
920 RTLIB::Libcall Call_F80,
921 RTLIB::Libcall Call_PPCF128) {
923 VT == MVT::f32 ? Call_F32 :
924 VT == MVT::f64 ? Call_F64 :
925 VT == MVT::f80 ? Call_F80 :
926 VT == MVT::ppcf128 ? Call_PPCF128 :
927 RTLIB::UNKNOWN_LIBCALL;
930 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
931 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
932 /// is necessary to spill the vector being inserted into to memory, perform
933 /// the insert there, and then read the result back.
934 SDValue SelectionDAGLegalize::
935 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
941 // If the target doesn't support this, we have to spill the input vector
942 // to a temporary stack slot, update the element, then reload it. This is
943 // badness. We could also load the value into a vector register (either
944 // with a "move to register" or "extload into register" instruction, then
945 // permute it into place, if the idx is a constant and if the idx is
946 // supported by the target.
947 MVT VT = Tmp1.getValueType();
948 MVT EltVT = VT.getVectorElementType();
949 MVT IdxVT = Tmp3.getValueType();
950 MVT PtrVT = TLI.getPointerTy();
951 SDValue StackPtr = DAG.CreateStackTemporary(VT);
953 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
956 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
957 PseudoSourceValue::getFixedStack(SPFI), 0);
959 // Truncate or zero extend offset to target pointer type.
960 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
961 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
962 // Add the offset to the index.
963 unsigned EltSize = EltVT.getSizeInBits()/8;
964 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
965 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
966 // Store the scalar value.
967 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
968 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
969 // Load the updated vector.
970 return DAG.getLoad(VT, dl, Ch, StackPtr,
971 PseudoSourceValue::getFixedStack(SPFI), 0);
975 /// LegalizeOp - We know that the specified value has a legal type, and
976 /// that its operands are legal. Now ensure that the operation itself
977 /// is legal, recursively ensuring that the operands' operations remain
979 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
980 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
983 assert(isTypeLegal(Op.getValueType()) &&
984 "Caller should expand or promote operands that are not legal!");
985 SDNode *Node = Op.getNode();
986 DebugLoc dl = Node->getDebugLoc();
988 // If this operation defines any values that cannot be represented in a
989 // register on this target, make sure to expand or promote them.
990 if (Node->getNumValues() > 1) {
991 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
992 if (getTypeAction(Node->getValueType(i)) != Legal) {
993 HandleOp(Op.getValue(i));
994 assert(LegalizedNodes.count(Op) &&
995 "Handling didn't add legal operands!");
996 return LegalizedNodes[Op];
1000 // Note that LegalizeOp may be reentered even from single-use nodes, which
1001 // means that we always must cache transformed nodes.
1002 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1003 if (I != LegalizedNodes.end()) return I->second;
1005 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
1006 SDValue Result = Op;
1007 bool isCustom = false;
1009 switch (Node->getOpcode()) {
1010 case ISD::FrameIndex:
1011 case ISD::EntryToken:
1013 case ISD::BasicBlock:
1014 case ISD::TargetFrameIndex:
1015 case ISD::TargetJumpTable:
1016 case ISD::TargetConstant:
1017 case ISD::TargetConstantFP:
1018 case ISD::TargetConstantPool:
1019 case ISD::TargetGlobalAddress:
1020 case ISD::TargetGlobalTLSAddress:
1021 case ISD::TargetExternalSymbol:
1022 case ISD::VALUETYPE:
1024 case ISD::MEMOPERAND:
1026 case ISD::ARG_FLAGS:
1027 // Primitives must all be legal.
1028 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
1029 "This must be legal!");
1032 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1033 // If this is a target node, legalize it by legalizing the operands then
1034 // passing it through.
1035 SmallVector<SDValue, 8> Ops;
1036 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1037 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1039 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
1041 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1042 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
1043 return Result.getValue(Op.getResNo());
1045 // Otherwise this is an unhandled builtin node. splat.
1047 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
1049 assert(0 && "Do not know how to legalize this operator!");
1051 case ISD::GLOBAL_OFFSET_TABLE:
1052 case ISD::GlobalAddress:
1053 case ISD::GlobalTLSAddress:
1054 case ISD::ExternalSymbol:
1055 case ISD::ConstantPool:
1056 case ISD::JumpTable: // Nothing to do.
1057 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1058 default: assert(0 && "This action is not supported yet!");
1059 case TargetLowering::Custom:
1060 Tmp1 = TLI.LowerOperation(Op, DAG);
1061 if (Tmp1.getNode()) Result = Tmp1;
1062 // FALLTHROUGH if the target doesn't want to lower this op after all.
1063 case TargetLowering::Legal:
1067 case ISD::FRAMEADDR:
1068 case ISD::RETURNADDR:
1069 // The only option for these nodes is to custom lower them. If the target
1070 // does not custom lower them, then return zero.
1071 Tmp1 = TLI.LowerOperation(Op, DAG);
1075 Result = DAG.getConstant(0, TLI.getPointerTy());
1077 case ISD::FRAME_TO_ARGS_OFFSET: {
1078 MVT VT = Node->getValueType(0);
1079 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1080 default: assert(0 && "This action is not supported yet!");
1081 case TargetLowering::Custom:
1082 Result = TLI.LowerOperation(Op, DAG);
1083 if (Result.getNode()) break;
1085 case TargetLowering::Legal:
1086 Result = DAG.getConstant(0, VT);
1091 case ISD::EXCEPTIONADDR: {
1092 Tmp1 = LegalizeOp(Node->getOperand(0));
1093 MVT VT = Node->getValueType(0);
1094 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1095 default: assert(0 && "This action is not supported yet!");
1096 case TargetLowering::Expand: {
1097 unsigned Reg = TLI.getExceptionAddressRegister();
1098 Result = DAG.getCopyFromReg(Tmp1, dl, Reg, VT);
1101 case TargetLowering::Custom:
1102 Result = TLI.LowerOperation(Op, DAG);
1103 if (Result.getNode()) break;
1105 case TargetLowering::Legal: {
1106 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
1107 Result = DAG.getMergeValues(Ops, 2, dl);
1112 if (Result.getNode()->getNumValues() == 1) break;
1114 assert(Result.getNode()->getNumValues() == 2 &&
1115 "Cannot return more than two values!");
1117 // Since we produced two values, make sure to remember that we
1118 // legalized both of them.
1119 Tmp1 = LegalizeOp(Result);
1120 Tmp2 = LegalizeOp(Result.getValue(1));
1121 AddLegalizedOperand(Op.getValue(0), Tmp1);
1122 AddLegalizedOperand(Op.getValue(1), Tmp2);
1123 return Op.getResNo() ? Tmp2 : Tmp1;
1124 case ISD::EHSELECTION: {
1125 Tmp1 = LegalizeOp(Node->getOperand(0));
1126 Tmp2 = LegalizeOp(Node->getOperand(1));
1127 MVT VT = Node->getValueType(0);
1128 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1129 default: assert(0 && "This action is not supported yet!");
1130 case TargetLowering::Expand: {
1131 unsigned Reg = TLI.getExceptionSelectorRegister();
1132 Result = DAG.getCopyFromReg(Tmp2, dl, Reg, VT);
1135 case TargetLowering::Custom:
1136 Result = TLI.LowerOperation(Op, DAG);
1137 if (Result.getNode()) break;
1139 case TargetLowering::Legal: {
1140 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
1141 Result = DAG.getMergeValues(Ops, 2, dl);
1146 if (Result.getNode()->getNumValues() == 1) break;
1148 assert(Result.getNode()->getNumValues() == 2 &&
1149 "Cannot return more than two values!");
1151 // Since we produced two values, make sure to remember that we
1152 // legalized both of them.
1153 Tmp1 = LegalizeOp(Result);
1154 Tmp2 = LegalizeOp(Result.getValue(1));
1155 AddLegalizedOperand(Op.getValue(0), Tmp1);
1156 AddLegalizedOperand(Op.getValue(1), Tmp2);
1157 return Op.getResNo() ? Tmp2 : Tmp1;
1158 case ISD::EH_RETURN: {
1159 MVT VT = Node->getValueType(0);
1160 // The only "good" option for this node is to custom lower it.
1161 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1162 default: assert(0 && "This action is not supported at all!");
1163 case TargetLowering::Custom:
1164 Result = TLI.LowerOperation(Op, DAG);
1165 if (Result.getNode()) break;
1167 case TargetLowering::Legal:
1168 // Target does not know, how to lower this, lower to noop
1169 Result = LegalizeOp(Node->getOperand(0));
1174 case ISD::AssertSext:
1175 case ISD::AssertZext:
1176 Tmp1 = LegalizeOp(Node->getOperand(0));
1177 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1179 case ISD::MERGE_VALUES:
1180 // Legalize eliminates MERGE_VALUES nodes.
1181 Result = Node->getOperand(Op.getResNo());
1183 case ISD::CopyFromReg:
1184 Tmp1 = LegalizeOp(Node->getOperand(0));
1185 Result = Op.getValue(0);
1186 if (Node->getNumValues() == 2) {
1187 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1189 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1190 if (Node->getNumOperands() == 3) {
1191 Tmp2 = LegalizeOp(Node->getOperand(2));
1192 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1194 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1196 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1198 // Since CopyFromReg produces two values, make sure to remember that we
1199 // legalized both of them.
1200 AddLegalizedOperand(Op.getValue(0), Result);
1201 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1202 return Result.getValue(Op.getResNo());
1204 MVT VT = Op.getValueType();
1205 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1206 default: assert(0 && "This action is not supported yet!");
1207 case TargetLowering::Expand:
1209 Result = DAG.getConstant(0, VT);
1210 else if (VT.isFloatingPoint())
1211 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1214 assert(0 && "Unknown value type!");
1216 case TargetLowering::Legal:
1222 case ISD::INTRINSIC_W_CHAIN:
1223 case ISD::INTRINSIC_WO_CHAIN:
1224 case ISD::INTRINSIC_VOID: {
1225 SmallVector<SDValue, 8> Ops;
1226 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1227 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1228 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1230 // Allow the target to custom lower its intrinsics if it wants to.
1231 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1232 TargetLowering::Custom) {
1233 Tmp3 = TLI.LowerOperation(Result, DAG);
1234 if (Tmp3.getNode()) Result = Tmp3;
1237 if (Result.getNode()->getNumValues() == 1) break;
1239 // Must have return value and chain result.
1240 assert(Result.getNode()->getNumValues() == 2 &&
1241 "Cannot return more than two values!");
1243 // Since loads produce two values, make sure to remember that we
1244 // legalized both of them.
1245 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1246 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1247 return Result.getValue(Op.getResNo());
1250 case ISD::DBG_STOPPOINT:
1251 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1252 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1254 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1255 case TargetLowering::Promote:
1256 default: assert(0 && "This action is not supported yet!");
1257 case TargetLowering::Expand: {
1258 DwarfWriter *DW = DAG.getDwarfWriter();
1259 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
1261 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
1263 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1264 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
1265 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) {
1266 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit()));
1267 std::string Dir, FN;
1268 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
1269 CU.getFilename(FN));
1271 unsigned Line = DSP->getLine();
1272 unsigned Col = DSP->getColumn();
1275 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
1276 // won't hurt anything.
1278 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1279 DAG.getConstant(Col, MVT::i32),
1280 DAG.getConstant(SrcFile, MVT::i32) };
1281 Result = DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Ops, 4);
1283 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile);
1284 Result = DAG.getLabel(ISD::DBG_LABEL, dl, Tmp1, ID);
1287 Result = Tmp1; // chain
1290 Result = Tmp1; // chain
1294 case TargetLowering::Custom:
1295 Result = TLI.LowerOperation(Op, DAG);
1296 if (Result.getNode())
1298 case TargetLowering::Legal: {
1299 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1300 if (Action == Legal && Tmp1 == Node->getOperand(0))
1303 SmallVector<SDValue, 8> Ops;
1304 Ops.push_back(Tmp1);
1305 if (Action == Legal) {
1306 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1307 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1309 // Otherwise promote them.
1310 Ops.push_back(PromoteOp(Node->getOperand(1)));
1311 Ops.push_back(PromoteOp(Node->getOperand(2)));
1313 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1314 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1315 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1322 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1323 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1324 default: assert(0 && "This action is not supported yet!");
1325 case TargetLowering::Legal:
1326 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1327 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1328 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1329 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1331 case TargetLowering::Expand:
1332 Result = LegalizeOp(Node->getOperand(0));
1337 case ISD::DEBUG_LOC:
1338 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1339 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1340 default: assert(0 && "This action is not supported yet!");
1341 case TargetLowering::Legal: {
1342 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1343 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1344 if (Action == Legal && Tmp1 == Node->getOperand(0))
1346 if (Action == Legal) {
1347 Tmp2 = Node->getOperand(1);
1348 Tmp3 = Node->getOperand(2);
1349 Tmp4 = Node->getOperand(3);
1351 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1352 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1353 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1355 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1361 case ISD::DBG_LABEL:
1363 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1364 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1365 default: assert(0 && "This action is not supported yet!");
1366 case TargetLowering::Legal:
1367 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1368 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1370 case TargetLowering::Expand:
1371 Result = LegalizeOp(Node->getOperand(0));
1377 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1378 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1379 default: assert(0 && "This action is not supported yet!");
1380 case TargetLowering::Legal:
1381 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1382 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1383 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1384 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1385 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1387 case TargetLowering::Expand:
1389 Result = LegalizeOp(Node->getOperand(0));
1394 case ISD::MEMBARRIER: {
1395 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1396 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1397 default: assert(0 && "This action is not supported yet!");
1398 case TargetLowering::Legal: {
1400 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1401 for (int x = 1; x < 6; ++x) {
1402 Ops[x] = Node->getOperand(x);
1403 if (!isTypeLegal(Ops[x].getValueType()))
1404 Ops[x] = PromoteOp(Ops[x]);
1406 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1409 case TargetLowering::Expand:
1410 //There is no libgcc call for this op
1411 Result = Node->getOperand(0); // Noop
1417 case ISD::ATOMIC_CMP_SWAP: {
1418 unsigned int num_operands = 4;
1419 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1421 for (unsigned int x = 0; x < num_operands; ++x)
1422 Ops[x] = LegalizeOp(Node->getOperand(x));
1423 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1425 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1426 default: assert(0 && "This action is not supported yet!");
1427 case TargetLowering::Custom:
1428 Result = TLI.LowerOperation(Result, DAG);
1430 case TargetLowering::Legal:
1433 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1434 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1435 return Result.getValue(Op.getResNo());
1437 case ISD::ATOMIC_LOAD_ADD:
1438 case ISD::ATOMIC_LOAD_SUB:
1439 case ISD::ATOMIC_LOAD_AND:
1440 case ISD::ATOMIC_LOAD_OR:
1441 case ISD::ATOMIC_LOAD_XOR:
1442 case ISD::ATOMIC_LOAD_NAND:
1443 case ISD::ATOMIC_LOAD_MIN:
1444 case ISD::ATOMIC_LOAD_MAX:
1445 case ISD::ATOMIC_LOAD_UMIN:
1446 case ISD::ATOMIC_LOAD_UMAX:
1447 case ISD::ATOMIC_SWAP: {
1448 unsigned int num_operands = 3;
1449 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1451 for (unsigned int x = 0; x < num_operands; ++x)
1452 Ops[x] = LegalizeOp(Node->getOperand(x));
1453 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1455 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1456 default: assert(0 && "This action is not supported yet!");
1457 case TargetLowering::Custom:
1458 Result = TLI.LowerOperation(Result, DAG);
1460 case TargetLowering::Legal:
1463 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1464 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1465 return Result.getValue(Op.getResNo());
1467 case ISD::Constant: {
1468 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1470 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1472 // We know we don't need to expand constants here, constants only have one
1473 // value and we check that it is fine above.
1475 if (opAction == TargetLowering::Custom) {
1476 Tmp1 = TLI.LowerOperation(Result, DAG);
1482 case ISD::ConstantFP: {
1483 // Spill FP immediates to the constant pool if the target cannot directly
1484 // codegen them. Targets often have some immediate values that can be
1485 // efficiently generated into an FP register without a load. We explicitly
1486 // leave these constants as ConstantFP nodes for the target to deal with.
1487 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1489 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1490 default: assert(0 && "This action is not supported yet!");
1491 case TargetLowering::Legal:
1493 case TargetLowering::Custom:
1494 Tmp3 = TLI.LowerOperation(Result, DAG);
1495 if (Tmp3.getNode()) {
1500 case TargetLowering::Expand: {
1501 // Check to see if this FP immediate is already legal.
1502 bool isLegal = false;
1503 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1504 E = TLI.legal_fpimm_end(); I != E; ++I) {
1505 if (CFP->isExactlyValue(*I)) {
1510 // If this is a legal constant, turn it into a TargetConstantFP node.
1513 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1518 case ISD::TokenFactor:
1519 if (Node->getNumOperands() == 2) {
1520 Tmp1 = LegalizeOp(Node->getOperand(0));
1521 Tmp2 = LegalizeOp(Node->getOperand(1));
1522 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1523 } else if (Node->getNumOperands() == 3) {
1524 Tmp1 = LegalizeOp(Node->getOperand(0));
1525 Tmp2 = LegalizeOp(Node->getOperand(1));
1526 Tmp3 = LegalizeOp(Node->getOperand(2));
1527 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1529 SmallVector<SDValue, 8> Ops;
1530 // Legalize the operands.
1531 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1532 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1533 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1537 case ISD::FORMAL_ARGUMENTS:
1539 // The only option for this is to custom lower it.
1540 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1541 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1542 // A call within a calling sequence must be legalized to something
1543 // other than the normal CALLSEQ_END. Violating this gets Legalize
1544 // into an infinite loop.
1545 assert ((!IsLegalizingCall ||
1546 Node->getOpcode() != ISD::CALL ||
1547 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1548 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1550 // The number of incoming and outgoing values should match; unless the final
1551 // outgoing value is a flag.
1552 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1553 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1554 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1556 "Lowering call/formal_arguments produced unexpected # results!");
1558 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1559 // remember that we legalized all of them, so it doesn't get relegalized.
1560 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1561 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1563 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1564 if (Op.getResNo() == i)
1566 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1569 case ISD::BUILD_VECTOR:
1570 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1571 default: assert(0 && "This action is not supported yet!");
1572 case TargetLowering::Custom:
1573 Tmp3 = TLI.LowerOperation(Result, DAG);
1574 if (Tmp3.getNode()) {
1579 case TargetLowering::Expand:
1580 Result = ExpandBUILD_VECTOR(Result.getNode());
1584 case ISD::INSERT_VECTOR_ELT:
1585 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1586 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1588 // The type of the value to insert may not be legal, even though the vector
1589 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1591 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1592 default: assert(0 && "Cannot expand insert element operand");
1593 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1594 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1596 // FIXME: An alternative would be to check to see if the target is not
1597 // going to custom lower this operation, we could bitcast to half elt
1598 // width and perform two inserts at that width, if that is legal.
1599 Tmp2 = Node->getOperand(1);
1602 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1604 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1605 Node->getValueType(0))) {
1606 default: assert(0 && "This action is not supported yet!");
1607 case TargetLowering::Legal:
1609 case TargetLowering::Custom:
1610 Tmp4 = TLI.LowerOperation(Result, DAG);
1611 if (Tmp4.getNode()) {
1616 case TargetLowering::Promote:
1617 // Fall thru for vector case
1618 case TargetLowering::Expand: {
1619 // If the insert index is a constant, codegen this as a scalar_to_vector,
1620 // then a shuffle that inserts it into the right position in the vector.
1621 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1622 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1623 // match the element type of the vector being created, except for
1624 // integers in which case the inserted value can be over width.
1625 MVT EltVT = Op.getValueType().getVectorElementType();
1626 if (Tmp2.getValueType() == EltVT ||
1627 (EltVT.isInteger() && Tmp2.getValueType().bitsGE(EltVT))) {
1628 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
1629 Tmp1.getValueType(), Tmp2);
1631 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1632 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1633 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1634 // elt 0 of the RHS.
1635 SmallVector<int, 8> ShufOps;
1636 for (unsigned i = 0; i != NumElts; ++i)
1637 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
1639 Result = DAG.getVectorShuffle(Tmp1.getValueType(), dl, Tmp1, ScVec,
1641 Result = LegalizeOp(Result);
1645 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3, dl);
1650 case ISD::SCALAR_TO_VECTOR:
1651 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1652 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1656 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1657 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1658 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1659 Node->getValueType(0))) {
1660 default: assert(0 && "This action is not supported yet!");
1661 case TargetLowering::Legal:
1663 case TargetLowering::Custom:
1664 Tmp3 = TLI.LowerOperation(Result, DAG);
1665 if (Tmp3.getNode()) {
1670 case TargetLowering::Expand:
1671 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1675 case ISD::VECTOR_SHUFFLE: {
1676 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1677 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1678 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1679 MVT VT = Result.getValueType();
1681 // Copy the Mask to a local SmallVector for use wi
1682 SmallVector<int, 8> Mask;
1683 cast<ShuffleVectorSDNode>(Result)->getMask(Mask);
1685 // Allow targets to custom lower the SHUFFLEs they support.
1686 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
1687 default: assert(0 && "Unknown operation action!");
1688 case TargetLowering::Legal:
1689 assert(TLI.isShuffleMaskLegal(Mask, VT) &&
1690 "vector shuffle should not be created if not legal!");
1692 case TargetLowering::Custom:
1693 Tmp3 = TLI.LowerOperation(Result, DAG);
1694 if (Tmp3.getNode()) {
1699 case TargetLowering::Expand: {
1700 MVT EltVT = VT.getVectorElementType();
1701 int NumElems = VT.getVectorNumElements();
1702 SmallVector<SDValue, 8> Ops;
1703 for (int i = 0; i != NumElems; ++i) {
1705 Ops.push_back(DAG.getUNDEF(EltVT));
1710 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp1,
1711 DAG.getIntPtrConstant(Idx)));
1713 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp2,
1714 DAG.getIntPtrConstant(Idx - NumElems)));
1716 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
1719 case TargetLowering::Promote: {
1720 // Change base type to a different vector type.
1721 MVT OVT = Node->getValueType(0);
1722 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1724 // Cast the two input vectors.
1725 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1);
1726 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
1728 // Convert the shuffle mask to the right # elements.
1729 Result = promoteShuffle(NVT, OVT, dl, Tmp1, Tmp2, Mask);
1730 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
1736 case ISD::EXTRACT_VECTOR_ELT:
1737 Tmp1 = Node->getOperand(0);
1738 Tmp2 = LegalizeOp(Node->getOperand(1));
1739 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1740 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1743 case ISD::EXTRACT_SUBVECTOR:
1744 Tmp1 = Node->getOperand(0);
1745 Tmp2 = LegalizeOp(Node->getOperand(1));
1746 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1747 Result = ExpandEXTRACT_SUBVECTOR(Result);
1750 case ISD::CONCAT_VECTORS: {
1751 // Use extract/insert/build vector for now. We might try to be
1752 // more clever later.
1753 MVT PtrVT = TLI.getPointerTy();
1754 SmallVector<SDValue, 8> Ops;
1755 unsigned NumOperands = Node->getNumOperands();
1756 for (unsigned i=0; i < NumOperands; ++i) {
1757 SDValue SubOp = Node->getOperand(i);
1758 MVT VVT = SubOp.getNode()->getValueType(0);
1759 MVT EltVT = VVT.getVectorElementType();
1760 unsigned NumSubElem = VVT.getVectorNumElements();
1761 for (unsigned j=0; j < NumSubElem; ++j) {
1762 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1763 DAG.getConstant(j, PtrVT)));
1766 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
1767 &Ops[0], Ops.size()));
1770 case ISD::CALLSEQ_START: {
1771 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1773 // Recursively Legalize all of the inputs of the call end that do not lead
1774 // to this call start. This ensures that any libcalls that need be inserted
1775 // are inserted *before* the CALLSEQ_START.
1776 IsLegalizingCallArgs = true;
1777 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1778 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1779 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1782 IsLegalizingCallArgs = false;
1784 // Now that we legalized all of the inputs (which may have inserted
1785 // libcalls) create the new CALLSEQ_START node.
1786 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1788 // Merge in the last call, to ensure that this call start after the last
1790 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1791 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1792 Tmp1, LastCALLSEQ_END);
1793 Tmp1 = LegalizeOp(Tmp1);
1796 // Do not try to legalize the target-specific arguments (#1+).
1797 if (Tmp1 != Node->getOperand(0)) {
1798 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1800 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1803 // Remember that the CALLSEQ_START is legalized.
1804 AddLegalizedOperand(Op.getValue(0), Result);
1805 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1806 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1808 // Now that the callseq_start and all of the non-call nodes above this call
1809 // sequence have been legalized, legalize the call itself. During this
1810 // process, no libcalls can/will be inserted, guaranteeing that no calls
1812 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1813 // Note that we are selecting this call!
1814 LastCALLSEQ_END = SDValue(CallEnd, 0);
1815 IsLegalizingCall = true;
1817 // Legalize the call, starting from the CALLSEQ_END.
1818 LegalizeOp(LastCALLSEQ_END);
1819 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1822 case ISD::CALLSEQ_END:
1823 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1824 // will cause this node to be legalized as well as handling libcalls right.
1825 if (LastCALLSEQ_END.getNode() != Node) {
1826 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1827 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1828 assert(I != LegalizedNodes.end() &&
1829 "Legalizing the call start should have legalized this node!");
1833 // Otherwise, the call start has been legalized and everything is going
1834 // according to plan. Just legalize ourselves normally here.
1835 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1836 // Do not try to legalize the target-specific arguments (#1+), except for
1837 // an optional flag input.
1838 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1839 if (Tmp1 != Node->getOperand(0)) {
1840 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1842 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1845 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1846 if (Tmp1 != Node->getOperand(0) ||
1847 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1848 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1851 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1854 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1855 // This finishes up call legalization.
1856 IsLegalizingCall = false;
1858 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1859 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1860 if (Node->getNumValues() == 2)
1861 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1862 return Result.getValue(Op.getResNo());
1863 case ISD::DYNAMIC_STACKALLOC: {
1864 MVT VT = Node->getValueType(0);
1865 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1866 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1867 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1868 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1870 Tmp1 = Result.getValue(0);
1871 Tmp2 = Result.getValue(1);
1872 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1873 default: assert(0 && "This action is not supported yet!");
1874 case TargetLowering::Expand: {
1875 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1876 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1877 " not tell us which reg is the stack pointer!");
1878 SDValue Chain = Tmp1.getOperand(0);
1880 // Chain the dynamic stack allocation so that it doesn't modify the stack
1881 // pointer when other instructions are using the stack.
1882 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1884 SDValue Size = Tmp2.getOperand(1);
1885 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1886 Chain = SP.getValue(1);
1887 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1888 unsigned StackAlign =
1889 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1890 if (Align > StackAlign)
1891 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1892 DAG.getConstant(-(uint64_t)Align, VT));
1893 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1894 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1896 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1897 DAG.getIntPtrConstant(0, true), SDValue());
1899 Tmp1 = LegalizeOp(Tmp1);
1900 Tmp2 = LegalizeOp(Tmp2);
1903 case TargetLowering::Custom:
1904 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1905 if (Tmp3.getNode()) {
1906 Tmp1 = LegalizeOp(Tmp3);
1907 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1910 case TargetLowering::Legal:
1913 // Since this op produce two values, make sure to remember that we
1914 // legalized both of them.
1915 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1916 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1917 return Op.getResNo() ? Tmp2 : Tmp1;
1919 case ISD::INLINEASM: {
1920 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1921 bool Changed = false;
1922 // Legalize all of the operands of the inline asm, in case they are nodes
1923 // that need to be expanded or something. Note we skip the asm string and
1924 // all of the TargetConstant flags.
1925 SDValue Op = LegalizeOp(Ops[0]);
1926 Changed = Op != Ops[0];
1929 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1930 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1931 unsigned NumVals = InlineAsm::
1932 getNumOperandRegisters(cast<ConstantSDNode>(Ops[i])->getZExtValue());
1933 for (++i; NumVals; ++i, --NumVals) {
1934 SDValue Op = LegalizeOp(Ops[i]);
1943 Op = LegalizeOp(Ops.back());
1944 Changed |= Op != Ops.back();
1949 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1951 // INLINE asm returns a chain and flag, make sure to add both to the map.
1952 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1953 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1954 return Result.getValue(Op.getResNo());
1957 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1958 // Ensure that libcalls are emitted before a branch.
1959 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
1960 Tmp1 = LegalizeOp(Tmp1);
1961 LastCALLSEQ_END = DAG.getEntryNode();
1963 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1966 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1967 // Ensure that libcalls are emitted before a branch.
1968 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
1969 Tmp1 = LegalizeOp(Tmp1);
1970 LastCALLSEQ_END = DAG.getEntryNode();
1972 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1973 default: assert(0 && "Indirect target must be legal type (pointer)!");
1975 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1978 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1981 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1982 // Ensure that libcalls are emitted before a branch.
1983 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
1984 Tmp1 = LegalizeOp(Tmp1);
1985 LastCALLSEQ_END = DAG.getEntryNode();
1987 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1988 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1990 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1991 default: assert(0 && "This action is not supported yet!");
1992 case TargetLowering::Legal: break;
1993 case TargetLowering::Custom:
1994 Tmp1 = TLI.LowerOperation(Result, DAG);
1995 if (Tmp1.getNode()) Result = Tmp1;
1997 case TargetLowering::Expand: {
1998 SDValue Chain = Result.getOperand(0);
1999 SDValue Table = Result.getOperand(1);
2000 SDValue Index = Result.getOperand(2);
2002 MVT PTy = TLI.getPointerTy();
2003 MachineFunction &MF = DAG.getMachineFunction();
2004 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
2005 Index= DAG.getNode(ISD::MUL, dl, PTy,
2006 Index, DAG.getConstant(EntrySize, PTy));
2007 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2009 MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
2010 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
2011 PseudoSourceValue::getJumpTable(), 0, MemVT);
2013 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2014 // For PIC, the sequence is:
2015 // BRIND(load(Jumptable + index) + RelocBase)
2016 // RelocBase can be JumpTable, GOT or some sort of global base.
2017 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
2018 TLI.getPICJumpTableRelocBase(Table, DAG));
2020 Result = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
2025 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2026 // Ensure that libcalls are emitted before a return.
2027 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2028 Tmp1 = LegalizeOp(Tmp1);
2029 LastCALLSEQ_END = DAG.getEntryNode();
2031 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2032 case Expand: assert(0 && "It's impossible to expand bools");
2034 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2037 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
2039 // The top bits of the promoted condition are not necessarily zero, ensure
2040 // that the value is properly zero extended.
2041 unsigned BitWidth = Tmp2.getValueSizeInBits();
2042 if (!DAG.MaskedValueIsZero(Tmp2,
2043 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2044 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, MVT::i1);
2049 // Basic block destination (Op#2) is always legal.
2050 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2052 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
2053 default: assert(0 && "This action is not supported yet!");
2054 case TargetLowering::Legal: break;
2055 case TargetLowering::Custom:
2056 Tmp1 = TLI.LowerOperation(Result, DAG);
2057 if (Tmp1.getNode()) Result = Tmp1;
2059 case TargetLowering::Expand:
2060 // Expand brcond's setcc into its constituent parts and create a BR_CC
2062 if (Tmp2.getOpcode() == ISD::SETCC) {
2063 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
2064 Tmp1, Tmp2.getOperand(2),
2065 Tmp2.getOperand(0), Tmp2.getOperand(1),
2066 Node->getOperand(2));
2068 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
2069 DAG.getCondCode(ISD::SETNE), Tmp2,
2070 DAG.getConstant(0, Tmp2.getValueType()),
2071 Node->getOperand(2));
2077 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2078 // Ensure that libcalls are emitted before a branch.
2079 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2080 Tmp1 = LegalizeOp(Tmp1);
2081 Tmp2 = Node->getOperand(2); // LHS
2082 Tmp3 = Node->getOperand(3); // RHS
2083 Tmp4 = Node->getOperand(1); // CC
2085 LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()),
2086 Tmp2, Tmp3, Tmp4, dl);
2087 LastCALLSEQ_END = DAG.getEntryNode();
2089 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2090 // the LHS is a legal SETCC itself. In this case, we need to compare
2091 // the result against zero to select between true and false values.
2092 if (Tmp3.getNode() == 0) {
2093 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2094 Tmp4 = DAG.getCondCode(ISD::SETNE);
2097 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
2098 Node->getOperand(4));
2100 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
2101 default: assert(0 && "Unexpected action for BR_CC!");
2102 case TargetLowering::Legal: break;
2103 case TargetLowering::Custom:
2104 Tmp4 = TLI.LowerOperation(Result, DAG);
2105 if (Tmp4.getNode()) Result = Tmp4;
2110 LoadSDNode *LD = cast<LoadSDNode>(Node);
2111 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
2112 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
2114 ISD::LoadExtType ExtType = LD->getExtensionType();
2115 if (ExtType == ISD::NON_EXTLOAD) {
2116 MVT VT = Node->getValueType(0);
2117 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2118 Tmp3 = Result.getValue(0);
2119 Tmp4 = Result.getValue(1);
2121 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
2122 default: assert(0 && "This action is not supported yet!");
2123 case TargetLowering::Legal:
2124 // If this is an unaligned load and the target doesn't support it,
2126 if (!TLI.allowsUnalignedMemoryAccesses()) {
2127 unsigned ABIAlignment = TLI.getTargetData()->
2128 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2129 if (LD->getAlignment() < ABIAlignment){
2130 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2132 Tmp3 = Result.getOperand(0);
2133 Tmp4 = Result.getOperand(1);
2134 Tmp3 = LegalizeOp(Tmp3);
2135 Tmp4 = LegalizeOp(Tmp4);
2139 case TargetLowering::Custom:
2140 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
2141 if (Tmp1.getNode()) {
2142 Tmp3 = LegalizeOp(Tmp1);
2143 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2146 case TargetLowering::Promote: {
2147 // Only promote a load of vector type to another.
2148 assert(VT.isVector() && "Cannot promote this load!");
2149 // Change base type to a different vector type.
2150 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
2152 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
2153 LD->getSrcValueOffset(),
2154 LD->isVolatile(), LD->getAlignment());
2155 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
2156 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2160 // Since loads produce two values, make sure to remember that we
2161 // legalized both of them.
2162 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
2163 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
2164 return Op.getResNo() ? Tmp4 : Tmp3;
2166 MVT SrcVT = LD->getMemoryVT();
2167 unsigned SrcWidth = SrcVT.getSizeInBits();
2168 int SVOffset = LD->getSrcValueOffset();
2169 unsigned Alignment = LD->getAlignment();
2170 bool isVolatile = LD->isVolatile();
2172 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
2173 // Some targets pretend to have an i1 loading operation, and actually
2174 // load an i8. This trick is correct for ZEXTLOAD because the top 7
2175 // bits are guaranteed to be zero; it helps the optimizers understand
2176 // that these bits are zero. It is also useful for EXTLOAD, since it
2177 // tells the optimizers that those bits are undefined. It would be
2178 // nice to have an effective generic way of getting these benefits...
2179 // Until such a way is found, don't insist on promoting i1 here.
2180 (SrcVT != MVT::i1 ||
2181 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2182 // Promote to a byte-sized load if not loading an integral number of
2183 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2184 unsigned NewWidth = SrcVT.getStoreSizeInBits();
2185 MVT NVT = MVT::getIntegerVT(NewWidth);
2188 // The extra bits are guaranteed to be zero, since we stored them that
2189 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2191 ISD::LoadExtType NewExtType =
2192 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2194 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
2195 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2196 NVT, isVolatile, Alignment);
2198 Ch = Result.getValue(1); // The chain.
2200 if (ExtType == ISD::SEXTLOAD)
2201 // Having the top bits zero doesn't help when sign extending.
2202 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
2203 Result.getValueType(),
2204 Result, DAG.getValueType(SrcVT));
2205 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2206 // All the top bits are guaranteed to be zero - inform the optimizers.
2207 Result = DAG.getNode(ISD::AssertZext, dl,
2208 Result.getValueType(), Result,
2209 DAG.getValueType(SrcVT));
2211 Tmp1 = LegalizeOp(Result);
2212 Tmp2 = LegalizeOp(Ch);
2213 } else if (SrcWidth & (SrcWidth - 1)) {
2214 // If not loading a power-of-2 number of bits, expand as two loads.
2215 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2216 "Unsupported extload!");
2217 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2218 assert(RoundWidth < SrcWidth);
2219 unsigned ExtraWidth = SrcWidth - RoundWidth;
2220 assert(ExtraWidth < RoundWidth);
2221 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2222 "Load size not an integral number of bytes!");
2223 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2224 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2226 unsigned IncrementSize;
2228 if (TLI.isLittleEndian()) {
2229 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2230 // Load the bottom RoundWidth bits.
2231 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
2232 Node->getValueType(0), Tmp1, Tmp2,
2233 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2236 // Load the remaining ExtraWidth bits.
2237 IncrementSize = RoundWidth / 8;
2238 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2239 DAG.getIntPtrConstant(IncrementSize));
2240 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
2241 LD->getSrcValue(), SVOffset + IncrementSize,
2242 ExtraVT, isVolatile,
2243 MinAlign(Alignment, IncrementSize));
2245 // Build a factor node to remember that this load is independent of the
2247 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2250 // Move the top bits to the right place.
2251 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
2252 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2254 // Join the hi and lo parts.
2255 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
2257 // Big endian - avoid unaligned loads.
2258 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2259 // Load the top RoundWidth bits.
2260 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
2261 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2264 // Load the remaining ExtraWidth bits.
2265 IncrementSize = RoundWidth / 8;
2266 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2267 DAG.getIntPtrConstant(IncrementSize));
2268 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
2269 Node->getValueType(0), Tmp1, Tmp2,
2270 LD->getSrcValue(), SVOffset + IncrementSize,
2271 ExtraVT, isVolatile,
2272 MinAlign(Alignment, IncrementSize));
2274 // Build a factor node to remember that this load is independent of the
2276 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2279 // Move the top bits to the right place.
2280 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
2281 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2283 // Join the hi and lo parts.
2284 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
2287 Tmp1 = LegalizeOp(Result);
2288 Tmp2 = LegalizeOp(Ch);
2290 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
2291 default: assert(0 && "This action is not supported yet!");
2292 case TargetLowering::Custom:
2295 case TargetLowering::Legal:
2296 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2297 Tmp1 = Result.getValue(0);
2298 Tmp2 = Result.getValue(1);
2301 Tmp3 = TLI.LowerOperation(Result, DAG);
2302 if (Tmp3.getNode()) {
2303 Tmp1 = LegalizeOp(Tmp3);
2304 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2307 // If this is an unaligned load and the target doesn't support it,
2309 if (!TLI.allowsUnalignedMemoryAccesses()) {
2310 unsigned ABIAlignment = TLI.getTargetData()->
2311 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2312 if (LD->getAlignment() < ABIAlignment){
2313 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2315 Tmp1 = Result.getOperand(0);
2316 Tmp2 = Result.getOperand(1);
2317 Tmp1 = LegalizeOp(Tmp1);
2318 Tmp2 = LegalizeOp(Tmp2);
2323 case TargetLowering::Expand:
2324 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2325 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2326 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
2327 LD->getSrcValueOffset(),
2328 LD->isVolatile(), LD->getAlignment());
2329 Result = DAG.getNode(ISD::FP_EXTEND, dl,
2330 Node->getValueType(0), Load);
2331 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2332 Tmp2 = LegalizeOp(Load.getValue(1));
2335 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2336 // Turn the unsupported load into an EXTLOAD followed by an explicit
2337 // zero/sign extend inreg.
2338 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
2339 Tmp1, Tmp2, LD->getSrcValue(),
2340 LD->getSrcValueOffset(), SrcVT,
2341 LD->isVolatile(), LD->getAlignment());
2343 if (ExtType == ISD::SEXTLOAD)
2344 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
2345 Result.getValueType(),
2346 Result, DAG.getValueType(SrcVT));
2348 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
2349 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2350 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2355 // Since loads produce two values, make sure to remember that we legalized
2357 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2358 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2359 return Op.getResNo() ? Tmp2 : Tmp1;
2362 case ISD::EXTRACT_ELEMENT: {
2363 MVT OpTy = Node->getOperand(0).getValueType();
2364 switch (getTypeAction(OpTy)) {
2365 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2367 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2369 Result = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2370 DAG.getConstant(OpTy.getSizeInBits()/2,
2371 TLI.getShiftAmountTy()));
2372 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Result);
2375 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2376 Node->getOperand(0));
2380 // Get both the low and high parts.
2381 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2382 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2383 Result = Tmp2; // 1 -> Hi
2385 Result = Tmp1; // 0 -> Lo
2391 case ISD::CopyToReg:
2392 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2394 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2395 "Register type must be legal!");
2396 // Legalize the incoming value (must be a legal type).
2397 Tmp2 = LegalizeOp(Node->getOperand(2));
2398 if (Node->getNumValues() == 1) {
2399 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2401 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2402 if (Node->getNumOperands() == 4) {
2403 Tmp3 = LegalizeOp(Node->getOperand(3));
2404 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2407 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2410 // Since this produces two values, make sure to remember that we legalized
2412 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2413 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2419 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2421 // Ensure that libcalls are emitted before a return.
2422 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2423 Tmp1 = LegalizeOp(Tmp1);
2424 LastCALLSEQ_END = DAG.getEntryNode();
2426 switch (Node->getNumOperands()) {
2428 Tmp2 = Node->getOperand(1);
2429 Tmp3 = Node->getOperand(2); // Signness
2430 switch (getTypeAction(Tmp2.getValueType())) {
2432 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2435 if (!Tmp2.getValueType().isVector()) {
2437 ExpandOp(Tmp2, Lo, Hi);
2439 // Big endian systems want the hi reg first.
2440 if (TLI.isBigEndian())
2444 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2445 Tmp1, Lo, Tmp3, Hi, Tmp3);
2447 Result = DAG.getNode(ISD::RET, dl, MVT::Other, Tmp1, Lo, Tmp3);
2448 Result = LegalizeOp(Result);
2450 SDNode *InVal = Tmp2.getNode();
2451 int InIx = Tmp2.getResNo();
2452 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2453 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2455 // Figure out if there is a simple type corresponding to this Vector
2456 // type. If so, convert to the vector type.
2457 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2458 if (TLI.isTypeLegal(TVT)) {
2459 // Turn this into a return of the vector type.
2460 Tmp2 = LegalizeOp(Tmp2);
2461 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2462 } else if (NumElems == 1) {
2463 // Turn this into a return of the scalar type.
2464 Tmp2 = ScalarizeVectorOp(Tmp2);
2465 Tmp2 = LegalizeOp(Tmp2);
2466 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2468 // FIXME: Returns of gcc generic vectors smaller than a legal type
2469 // should be returned in integer registers!
2471 // The scalarized value type may not be legal, e.g. it might require
2472 // promotion or expansion. Relegalize the return.
2473 Result = LegalizeOp(Result);
2475 // FIXME: Returns of gcc generic vectors larger than a legal vector
2476 // type should be returned by reference!
2478 SplitVectorOp(Tmp2, Lo, Hi);
2479 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2480 Tmp1, Lo, Tmp3, Hi, Tmp3);
2481 Result = LegalizeOp(Result);
2486 Tmp2 = PromoteOp(Node->getOperand(1));
2487 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2488 Result = LegalizeOp(Result);
2493 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2495 default: { // ret <values>
2496 SmallVector<SDValue, 8> NewValues;
2497 NewValues.push_back(Tmp1);
2498 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2499 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2501 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2502 NewValues.push_back(Node->getOperand(i+1));
2506 assert(!Node->getOperand(i).getValueType().isExtended() &&
2507 "FIXME: TODO: implement returning non-legal vector types!");
2508 ExpandOp(Node->getOperand(i), Lo, Hi);
2509 NewValues.push_back(Lo);
2510 NewValues.push_back(Node->getOperand(i+1));
2512 NewValues.push_back(Hi);
2513 NewValues.push_back(Node->getOperand(i+1));
2518 assert(0 && "Can't promote multiple return value yet!");
2521 if (NewValues.size() == Node->getNumOperands())
2522 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2524 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2525 &NewValues[0], NewValues.size());
2530 if (Result.getOpcode() == ISD::RET) {
2531 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2532 default: assert(0 && "This action is not supported yet!");
2533 case TargetLowering::Legal: break;
2534 case TargetLowering::Custom:
2535 Tmp1 = TLI.LowerOperation(Result, DAG);
2536 if (Tmp1.getNode()) Result = Tmp1;
2542 StoreSDNode *ST = cast<StoreSDNode>(Node);
2543 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2544 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2545 int SVOffset = ST->getSrcValueOffset();
2546 unsigned Alignment = ST->getAlignment();
2547 bool isVolatile = ST->isVolatile();
2549 if (!ST->isTruncatingStore()) {
2550 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2551 // FIXME: We shouldn't do this for TargetConstantFP's.
2552 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2553 // to phase ordering between legalized code and the dag combiner. This
2554 // probably means that we need to integrate dag combiner and legalizer
2556 // We generally can't do this one for long doubles.
2557 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2558 if (CFP->getValueType(0) == MVT::f32 &&
2559 getTypeAction(MVT::i32) == Legal) {
2560 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2561 bitcastToAPInt().zextOrTrunc(32),
2563 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2564 SVOffset, isVolatile, Alignment);
2566 } else if (CFP->getValueType(0) == MVT::f64) {
2567 // If this target supports 64-bit registers, do a single 64-bit store.
2568 if (getTypeAction(MVT::i64) == Legal) {
2569 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
2570 zextOrTrunc(64), MVT::i64);
2571 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2572 SVOffset, isVolatile, Alignment);
2574 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2575 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2576 // stores. If the target supports neither 32- nor 64-bits, this
2577 // xform is certainly not worth it.
2578 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
2579 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2580 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2581 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2583 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
2584 SVOffset, isVolatile, Alignment);
2585 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2586 DAG.getIntPtrConstant(4));
2587 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2588 isVolatile, MinAlign(Alignment, 4U));
2590 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2596 switch (getTypeAction(ST->getMemoryVT())) {
2598 Tmp3 = LegalizeOp(ST->getValue());
2599 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2602 MVT VT = Tmp3.getValueType();
2603 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2604 default: assert(0 && "This action is not supported yet!");
2605 case TargetLowering::Legal:
2606 // If this is an unaligned store and the target doesn't support it,
2608 if (!TLI.allowsUnalignedMemoryAccesses()) {
2609 unsigned ABIAlignment = TLI.getTargetData()->
2610 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2611 if (ST->getAlignment() < ABIAlignment)
2612 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2616 case TargetLowering::Custom:
2617 Tmp1 = TLI.LowerOperation(Result, DAG);
2618 if (Tmp1.getNode()) Result = Tmp1;
2620 case TargetLowering::Promote:
2621 assert(VT.isVector() && "Unknown legal promote case!");
2622 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
2623 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2624 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
2625 ST->getSrcValue(), SVOffset, isVolatile,
2632 if (!ST->getMemoryVT().isVector()) {
2633 // Truncate the value and store the result.
2634 Tmp3 = PromoteOp(ST->getValue());
2635 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2636 SVOffset, ST->getMemoryVT(),
2637 isVolatile, Alignment);
2640 // Fall thru to expand for vector
2642 unsigned IncrementSize = 0;
2645 // If this is a vector type, then we have to calculate the increment as
2646 // the product of the element size in bytes, and the number of elements
2647 // in the high half of the vector.
2648 if (ST->getValue().getValueType().isVector()) {
2649 SDNode *InVal = ST->getValue().getNode();
2650 int InIx = ST->getValue().getResNo();
2651 MVT InVT = InVal->getValueType(InIx);
2652 unsigned NumElems = InVT.getVectorNumElements();
2653 MVT EVT = InVT.getVectorElementType();
2655 // Figure out if there is a simple type corresponding to this Vector
2656 // type. If so, convert to the vector type.
2657 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2658 if (TLI.isTypeLegal(TVT)) {
2659 // Turn this into a normal store of the vector type.
2660 Tmp3 = LegalizeOp(ST->getValue());
2661 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2662 SVOffset, isVolatile, Alignment);
2663 Result = LegalizeOp(Result);
2665 } else if (NumElems == 1) {
2666 // Turn this into a normal store of the scalar type.
2667 Tmp3 = ScalarizeVectorOp(ST->getValue());
2668 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2669 SVOffset, isVolatile, Alignment);
2670 // The scalarized value type may not be legal, e.g. it might require
2671 // promotion or expansion. Relegalize the scalar store.
2672 Result = LegalizeOp(Result);
2675 // Check if we have widen this node with another value
2676 std::map<SDValue, SDValue>::iterator I =
2677 WidenNodes.find(ST->getValue());
2678 if (I != WidenNodes.end()) {
2679 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2);
2683 SplitVectorOp(ST->getValue(), Lo, Hi);
2684 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2685 EVT.getSizeInBits()/8;
2689 ExpandOp(ST->getValue(), Lo, Hi);
2690 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2692 if (Hi.getNode() && TLI.isBigEndian())
2696 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
2697 SVOffset, isVolatile, Alignment);
2699 if (Hi.getNode() == NULL) {
2700 // Must be int <-> float one-to-one expansion.
2705 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2706 DAG.getIntPtrConstant(IncrementSize));
2707 assert(isTypeLegal(Tmp2.getValueType()) &&
2708 "Pointers must be legal!");
2709 SVOffset += IncrementSize;
2710 Alignment = MinAlign(Alignment, IncrementSize);
2711 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2712 SVOffset, isVolatile, Alignment);
2713 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2718 switch (getTypeAction(ST->getValue().getValueType())) {
2720 Tmp3 = LegalizeOp(ST->getValue());
2723 if (!ST->getValue().getValueType().isVector()) {
2724 // We can promote the value, the truncstore will still take care of it.
2725 Tmp3 = PromoteOp(ST->getValue());
2728 // Vector case falls through to expand
2730 // Just store the low part. This may become a non-trunc store, so make
2731 // sure to use getTruncStore, not UpdateNodeOperands below.
2732 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2733 return DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2734 SVOffset, MVT::i8, isVolatile, Alignment);
2737 MVT StVT = ST->getMemoryVT();
2738 unsigned StWidth = StVT.getSizeInBits();
2740 if (StWidth != StVT.getStoreSizeInBits()) {
2741 // Promote to a byte-sized store with upper bits zero if not
2742 // storing an integral number of bytes. For example, promote
2743 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2744 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2745 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
2746 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2747 SVOffset, NVT, isVolatile, Alignment);
2748 } else if (StWidth & (StWidth - 1)) {
2749 // If not storing a power-of-2 number of bits, expand as two stores.
2750 assert(StVT.isExtended() && !StVT.isVector() &&
2751 "Unsupported truncstore!");
2752 unsigned RoundWidth = 1 << Log2_32(StWidth);
2753 assert(RoundWidth < StWidth);
2754 unsigned ExtraWidth = StWidth - RoundWidth;
2755 assert(ExtraWidth < RoundWidth);
2756 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2757 "Store size not an integral number of bytes!");
2758 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2759 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2761 unsigned IncrementSize;
2763 if (TLI.isLittleEndian()) {
2764 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2765 // Store the bottom RoundWidth bits.
2766 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2768 isVolatile, Alignment);
2770 // Store the remaining ExtraWidth bits.
2771 IncrementSize = RoundWidth / 8;
2772 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2773 DAG.getIntPtrConstant(IncrementSize));
2774 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
2775 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2776 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2777 SVOffset + IncrementSize, ExtraVT, isVolatile,
2778 MinAlign(Alignment, IncrementSize));
2780 // Big endian - avoid unaligned stores.
2781 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2782 // Store the top RoundWidth bits.
2783 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
2784 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2785 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2786 SVOffset, RoundVT, isVolatile, Alignment);
2788 // Store the remaining ExtraWidth bits.
2789 IncrementSize = RoundWidth / 8;
2790 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2791 DAG.getIntPtrConstant(IncrementSize));
2792 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2793 SVOffset + IncrementSize, ExtraVT, isVolatile,
2794 MinAlign(Alignment, IncrementSize));
2797 // The order of the stores doesn't matter.
2798 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2800 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2801 Tmp2 != ST->getBasePtr())
2802 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2805 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2806 default: assert(0 && "This action is not supported yet!");
2807 case TargetLowering::Legal:
2808 // If this is an unaligned store and the target doesn't support it,
2810 if (!TLI.allowsUnalignedMemoryAccesses()) {
2811 unsigned ABIAlignment = TLI.getTargetData()->
2812 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2813 if (ST->getAlignment() < ABIAlignment)
2814 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2818 case TargetLowering::Custom:
2819 Result = TLI.LowerOperation(Result, DAG);
2822 // TRUNCSTORE:i16 i32 -> STORE i16
2823 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2824 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
2825 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2826 SVOffset, isVolatile, Alignment);
2834 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2835 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2837 case ISD::STACKSAVE:
2838 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2839 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2840 Tmp1 = Result.getValue(0);
2841 Tmp2 = Result.getValue(1);
2843 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2844 default: assert(0 && "This action is not supported yet!");
2845 case TargetLowering::Legal: break;
2846 case TargetLowering::Custom:
2847 Tmp3 = TLI.LowerOperation(Result, DAG);
2848 if (Tmp3.getNode()) {
2849 Tmp1 = LegalizeOp(Tmp3);
2850 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2853 case TargetLowering::Expand:
2854 // Expand to CopyFromReg if the target set
2855 // StackPointerRegisterToSaveRestore.
2856 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2857 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), dl, SP,
2858 Node->getValueType(0));
2859 Tmp2 = Tmp1.getValue(1);
2861 Tmp1 = DAG.getUNDEF(Node->getValueType(0));
2862 Tmp2 = Node->getOperand(0);
2867 // Since stacksave produce two values, make sure to remember that we
2868 // legalized both of them.
2869 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2870 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2871 return Op.getResNo() ? Tmp2 : Tmp1;
2873 case ISD::STACKRESTORE:
2874 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2875 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2876 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2878 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2879 default: assert(0 && "This action is not supported yet!");
2880 case TargetLowering::Legal: break;
2881 case TargetLowering::Custom:
2882 Tmp1 = TLI.LowerOperation(Result, DAG);
2883 if (Tmp1.getNode()) Result = Tmp1;
2885 case TargetLowering::Expand:
2886 // Expand to CopyToReg if the target set
2887 // StackPointerRegisterToSaveRestore.
2888 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2889 Result = DAG.getCopyToReg(Tmp1, dl, SP, Tmp2);
2897 case ISD::READCYCLECOUNTER:
2898 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2899 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2900 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2901 Node->getValueType(0))) {
2902 default: assert(0 && "This action is not supported yet!");
2903 case TargetLowering::Legal:
2904 Tmp1 = Result.getValue(0);
2905 Tmp2 = Result.getValue(1);
2907 case TargetLowering::Custom:
2908 Result = TLI.LowerOperation(Result, DAG);
2909 Tmp1 = LegalizeOp(Result.getValue(0));
2910 Tmp2 = LegalizeOp(Result.getValue(1));
2914 // Since rdcc produce two values, make sure to remember that we legalized
2916 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2917 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2921 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2922 case Expand: assert(0 && "It's impossible to expand bools");
2924 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2927 assert(!Node->getOperand(0).getValueType().isVector() && "not possible");
2928 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2929 // Make sure the condition is either zero or one.
2930 unsigned BitWidth = Tmp1.getValueSizeInBits();
2931 if (!DAG.MaskedValueIsZero(Tmp1,
2932 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2933 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, MVT::i1);
2937 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2938 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2940 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2942 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2943 default: assert(0 && "This action is not supported yet!");
2944 case TargetLowering::Legal: break;
2945 case TargetLowering::Custom: {
2946 Tmp1 = TLI.LowerOperation(Result, DAG);
2947 if (Tmp1.getNode()) Result = Tmp1;
2950 case TargetLowering::Expand:
2951 if (Tmp1.getOpcode() == ISD::SETCC) {
2952 Result = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
2954 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2956 Result = DAG.getSelectCC(dl, Tmp1,
2957 DAG.getConstant(0, Tmp1.getValueType()),
2958 Tmp2, Tmp3, ISD::SETNE);
2961 case TargetLowering::Promote: {
2963 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2964 unsigned ExtOp, TruncOp;
2965 if (Tmp2.getValueType().isVector()) {
2966 ExtOp = ISD::BIT_CONVERT;
2967 TruncOp = ISD::BIT_CONVERT;
2968 } else if (Tmp2.getValueType().isInteger()) {
2969 ExtOp = ISD::ANY_EXTEND;
2970 TruncOp = ISD::TRUNCATE;
2972 ExtOp = ISD::FP_EXTEND;
2973 TruncOp = ISD::FP_ROUND;
2975 // Promote each of the values to the new type.
2976 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Tmp2);
2977 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Tmp3);
2978 // Perform the larger operation, then round down.
2979 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
2980 if (TruncOp != ISD::FP_ROUND)
2981 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result);
2983 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result,
2984 DAG.getIntPtrConstant(0));
2989 case ISD::SELECT_CC: {
2990 Tmp1 = Node->getOperand(0); // LHS
2991 Tmp2 = Node->getOperand(1); // RHS
2992 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2993 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2994 SDValue CC = Node->getOperand(4);
2996 LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()),
2997 Tmp1, Tmp2, CC, dl);
2999 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
3000 // the LHS is a legal SETCC itself. In this case, we need to compare
3001 // the result against zero to select between true and false values.
3002 if (Tmp2.getNode() == 0) {
3003 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3004 CC = DAG.getCondCode(ISD::SETNE);
3006 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
3008 // Everything is legal, see if we should expand this op or something.
3009 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
3010 default: assert(0 && "This action is not supported yet!");
3011 case TargetLowering::Legal: break;
3012 case TargetLowering::Custom:
3013 Tmp1 = TLI.LowerOperation(Result, DAG);
3014 if (Tmp1.getNode()) Result = Tmp1;
3020 Tmp1 = Node->getOperand(0);
3021 Tmp2 = Node->getOperand(1);
3022 Tmp3 = Node->getOperand(2);
3023 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3025 // If we had to Expand the SetCC operands into a SELECT node, then it may
3026 // not always be possible to return a true LHS & RHS. In this case, just
3027 // return the value we legalized, returned in the LHS
3028 if (Tmp2.getNode() == 0) {
3033 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
3034 default: assert(0 && "Cannot handle this action for SETCC yet!");
3035 case TargetLowering::Custom:
3038 case TargetLowering::Legal:
3039 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3041 Tmp4 = TLI.LowerOperation(Result, DAG);
3042 if (Tmp4.getNode()) Result = Tmp4;
3045 case TargetLowering::Promote: {
3046 // First step, figure out the appropriate operation to use.
3047 // Allow SETCC to not be supported for all legal data types
3048 // Mostly this targets FP
3049 MVT NewInTy = Node->getOperand(0).getValueType();
3050 MVT OldVT = NewInTy; OldVT = OldVT;
3052 // Scan for the appropriate larger type to use.
3054 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
3056 assert(NewInTy.isInteger() == OldVT.isInteger() &&
3057 "Fell off of the edge of the integer world");
3058 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
3059 "Fell off of the edge of the floating point world");
3061 // If the target supports SETCC of this type, use it.
3062 if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy))
3065 if (NewInTy.isInteger())
3066 assert(0 && "Cannot promote Legal Integer SETCC yet");
3068 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1);
3069 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2);
3071 Tmp1 = LegalizeOp(Tmp1);
3072 Tmp2 = LegalizeOp(Tmp2);
3073 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3074 Result = LegalizeOp(Result);
3077 case TargetLowering::Expand:
3078 // Expand a setcc node into a select_cc of the same condition, lhs, and
3079 // rhs that selects between const 1 (true) and const 0 (false).
3080 MVT VT = Node->getValueType(0);
3081 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3082 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3088 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3089 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3090 SDValue CC = Node->getOperand(2);
3092 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
3094 // Everything is legal, see if we should expand this op or something.
3095 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
3096 default: assert(0 && "This action is not supported yet!");
3097 case TargetLowering::Legal: break;
3098 case TargetLowering::Custom:
3099 Tmp1 = TLI.LowerOperation(Result, DAG);
3100 if (Tmp1.getNode()) Result = Tmp1;
3102 case TargetLowering::Expand: {
3103 // Unroll into a nasty set of scalar code for now.
3104 MVT VT = Node->getValueType(0);
3105 unsigned NumElems = VT.getVectorNumElements();
3106 MVT EltVT = VT.getVectorElementType();
3107 MVT TmpEltVT = Tmp1.getValueType().getVectorElementType();
3108 SmallVector<SDValue, 8> Ops(NumElems);
3109 for (unsigned i = 0; i < NumElems; ++i) {
3110 SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT,
3111 Tmp1, DAG.getIntPtrConstant(i));
3112 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
3113 In1, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3115 DAG.getIntPtrConstant(i)),
3117 Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i],
3118 DAG.getConstant(APInt::getAllOnesValue
3119 (EltVT.getSizeInBits()), EltVT),
3120 DAG.getConstant(0, EltVT));
3122 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems);
3129 case ISD::SHL_PARTS:
3130 case ISD::SRA_PARTS:
3131 case ISD::SRL_PARTS: {
3132 SmallVector<SDValue, 8> Ops;
3133 bool Changed = false;
3134 unsigned N = Node->getNumOperands();
3135 for (unsigned i = 0; i + 1 < N; ++i) {
3136 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3137 Changed |= Ops.back() != Node->getOperand(i);
3139 Ops.push_back(LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(N-1))));
3140 Changed |= Ops.back() != Node->getOperand(N-1);
3142 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
3144 switch (TLI.getOperationAction(Node->getOpcode(),
3145 Node->getValueType(0))) {
3146 default: assert(0 && "This action is not supported yet!");
3147 case TargetLowering::Legal: break;
3148 case TargetLowering::Custom:
3149 Tmp1 = TLI.LowerOperation(Result, DAG);
3150 if (Tmp1.getNode()) {
3151 SDValue Tmp2, RetVal(0, 0);
3152 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
3153 Tmp2 = LegalizeOp(Tmp1.getValue(i));
3154 AddLegalizedOperand(SDValue(Node, i), Tmp2);
3155 if (i == Op.getResNo())
3158 assert(RetVal.getNode() && "Illegal result number");
3164 // Since these produce multiple values, make sure to remember that we
3165 // legalized all of them.
3166 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3167 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
3168 return Result.getValue(Op.getResNo());
3190 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3191 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3193 if ((Node->getOpcode() == ISD::SHL ||
3194 Node->getOpcode() == ISD::SRL ||
3195 Node->getOpcode() == ISD::SRA) &&
3196 !Node->getValueType(0).isVector())
3197 Tmp2 = DAG.getShiftAmountOperand(Tmp2);
3199 switch (getTypeAction(Tmp2.getValueType())) {
3200 case Expand: assert(0 && "Not possible");
3202 Tmp2 = LegalizeOp(Tmp2); // Legalize the RHS.
3205 Tmp2 = PromoteOp(Tmp2); // Promote the RHS.
3209 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3211 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3212 default: assert(0 && "BinOp legalize operation not supported");
3213 case TargetLowering::Legal: break;
3214 case TargetLowering::Custom:
3215 Tmp1 = TLI.LowerOperation(Result, DAG);
3216 if (Tmp1.getNode()) {
3220 // Fall through if the custom lower can't deal with the operation
3221 case TargetLowering::Expand: {
3222 MVT VT = Op.getValueType();
3224 // See if multiply or divide can be lowered using two-result operations.
3225 SDVTList VTs = DAG.getVTList(VT, VT);
3226 if (Node->getOpcode() == ISD::MUL) {
3227 // We just need the low half of the multiply; try both the signed
3228 // and unsigned forms. If the target supports both SMUL_LOHI and
3229 // UMUL_LOHI, form a preference by checking which forms of plain
3230 // MULH it supports.
3231 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3232 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3233 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3234 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3235 unsigned OpToUse = 0;
3236 if (HasSMUL_LOHI && !HasMULHS) {
3237 OpToUse = ISD::SMUL_LOHI;
3238 } else if (HasUMUL_LOHI && !HasMULHU) {
3239 OpToUse = ISD::UMUL_LOHI;
3240 } else if (HasSMUL_LOHI) {
3241 OpToUse = ISD::SMUL_LOHI;
3242 } else if (HasUMUL_LOHI) {
3243 OpToUse = ISD::UMUL_LOHI;
3246 Result = SDValue(DAG.getNode(OpToUse, dl, VTs, Tmp1, Tmp2).getNode(),
3251 if (Node->getOpcode() == ISD::MULHS &&
3252 TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
3253 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl,
3254 VTs, Tmp1, Tmp2).getNode(),
3258 if (Node->getOpcode() == ISD::MULHU &&
3259 TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) {
3260 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl,
3261 VTs, Tmp1, Tmp2).getNode(),
3265 if (Node->getOpcode() == ISD::SDIV &&
3266 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
3267 Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
3268 VTs, Tmp1, Tmp2).getNode(),
3272 if (Node->getOpcode() == ISD::UDIV &&
3273 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
3274 Result = SDValue(DAG.getNode(ISD::UDIVREM, dl,
3275 VTs, Tmp1, Tmp2).getNode(),
3280 // Check to see if we have a libcall for this operator.
3281 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3282 bool isSigned = false;
3283 switch (Node->getOpcode()) {
3286 if (VT == MVT::i32) {
3287 LC = Node->getOpcode() == ISD::UDIV
3288 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3289 isSigned = Node->getOpcode() == ISD::SDIV;
3294 LC = RTLIB::MUL_I32;
3295 else if (VT == MVT::i64)
3296 LC = RTLIB::MUL_I64;
3299 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3300 RTLIB::POW_PPCF128);
3303 LC = GetFPLibCall(VT, RTLIB::DIV_F32, RTLIB::DIV_F64, RTLIB::DIV_F80,
3304 RTLIB::DIV_PPCF128);
3308 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3310 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3314 assert(Node->getValueType(0).isVector() &&
3315 "Cannot expand this binary operator!");
3316 // Expand the operation into a bunch of nasty scalar code.
3317 Result = LegalizeOp(UnrollVectorOp(Op));
3320 case TargetLowering::Promote: {
3321 switch (Node->getOpcode()) {
3322 default: assert(0 && "Do not know how to promote this BinOp!");
3326 MVT OVT = Node->getValueType(0);
3327 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3328 assert(OVT.isVector() && "Cannot promote this BinOp!");
3329 // Bit convert each of the values to the new type.
3330 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1);
3331 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
3332 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3333 // Bit convert the result back the original type.
3334 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
3342 case ISD::SMUL_LOHI:
3343 case ISD::UMUL_LOHI:
3346 // These nodes will only be produced by target-specific lowering, so
3347 // they shouldn't be here if they aren't legal.
3348 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3349 "This must be legal!");
3351 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3352 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3353 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3356 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3357 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3358 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3359 case Expand: assert(0 && "Not possible");
3361 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3364 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3368 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3370 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3371 default: assert(0 && "Operation not supported");
3372 case TargetLowering::Custom:
3373 Tmp1 = TLI.LowerOperation(Result, DAG);
3374 if (Tmp1.getNode()) Result = Tmp1;
3376 case TargetLowering::Legal: break;
3377 case TargetLowering::Expand: {
3378 // If this target supports fabs/fneg natively and select is cheap,
3379 // do this efficiently.
3380 if (!TLI.isSelectExpensive() &&
3381 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3382 TargetLowering::Legal &&
3383 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3384 TargetLowering::Legal) {
3385 // Get the sign bit of the RHS.
3387 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3388 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
3389 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(IVT),
3390 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3391 // Get the absolute value of the result.
3392 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
3393 // Select between the nabs and abs value based on the sign bit of
3395 Result = DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
3396 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(),
3399 Result = LegalizeOp(Result);
3403 // Otherwise, do bitwise ops!
3405 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3406 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3407 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), Result);
3408 Result = LegalizeOp(Result);
3416 Tmp1 = LegalizeOp(Node->getOperand(0));
3417 Tmp2 = LegalizeOp(Node->getOperand(1));
3418 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3419 Tmp3 = Result.getValue(0);
3420 Tmp4 = Result.getValue(1);
3422 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3423 default: assert(0 && "This action is not supported yet!");
3424 case TargetLowering::Legal:
3426 case TargetLowering::Custom:
3427 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3428 if (Tmp1.getNode() != NULL) {
3429 Tmp3 = LegalizeOp(Tmp1);
3430 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3434 // Since this produces two values, make sure to remember that we legalized
3436 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3437 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3438 return Op.getResNo() ? Tmp4 : Tmp3;
3442 Tmp1 = LegalizeOp(Node->getOperand(0));
3443 Tmp2 = LegalizeOp(Node->getOperand(1));
3444 Tmp3 = LegalizeOp(Node->getOperand(2));
3445 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3446 Tmp3 = Result.getValue(0);
3447 Tmp4 = Result.getValue(1);
3449 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3450 default: assert(0 && "This action is not supported yet!");
3451 case TargetLowering::Legal:
3453 case TargetLowering::Custom:
3454 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3455 if (Tmp1.getNode() != NULL) {
3456 Tmp3 = LegalizeOp(Tmp1);
3457 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3461 // Since this produces two values, make sure to remember that we legalized
3463 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3464 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3465 return Op.getResNo() ? Tmp4 : Tmp3;
3467 case ISD::BUILD_PAIR: {
3468 MVT PairTy = Node->getValueType(0);
3469 // TODO: handle the case where the Lo and Hi operands are not of legal type
3470 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3471 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3472 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3473 case TargetLowering::Promote:
3474 case TargetLowering::Custom:
3475 assert(0 && "Cannot promote/custom this yet!");
3476 case TargetLowering::Legal:
3477 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3478 Result = DAG.getNode(ISD::BUILD_PAIR, dl, PairTy, Tmp1, Tmp2);
3480 case TargetLowering::Expand:
3481 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Tmp1);
3482 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Tmp2);
3483 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3484 DAG.getConstant(PairTy.getSizeInBits()/2,
3485 TLI.getShiftAmountTy()));
3486 Result = DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2);
3495 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3496 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3498 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3499 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3500 case TargetLowering::Custom:
3503 case TargetLowering::Legal:
3504 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3506 Tmp1 = TLI.LowerOperation(Result, DAG);
3507 if (Tmp1.getNode()) Result = Tmp1;
3510 case TargetLowering::Expand: {
3511 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3512 bool isSigned = DivOpc == ISD::SDIV;
3513 MVT VT = Node->getValueType(0);
3515 // See if remainder can be lowered using two-result operations.
3516 SDVTList VTs = DAG.getVTList(VT, VT);
3517 if (Node->getOpcode() == ISD::SREM &&
3518 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
3519 Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
3520 VTs, Tmp1, Tmp2).getNode(), 1);
3523 if (Node->getOpcode() == ISD::UREM &&
3524 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
3525 Result = SDValue(DAG.getNode(ISD::UDIVREM, dl,
3526 VTs, Tmp1, Tmp2).getNode(), 1);
3530 if (VT.isInteger()) {
3531 if (TLI.getOperationAction(DivOpc, VT) ==
3532 TargetLowering::Legal) {
3534 Result = DAG.getNode(DivOpc, dl, VT, Tmp1, Tmp2);
3535 Result = DAG.getNode(ISD::MUL, dl, VT, Result, Tmp2);
3536 Result = DAG.getNode(ISD::SUB, dl, VT, Tmp1, Result);
3537 } else if (VT.isVector()) {
3538 Result = LegalizeOp(UnrollVectorOp(Op));
3540 assert(VT == MVT::i32 &&
3541 "Cannot expand this binary operator!");
3542 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3543 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3545 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3548 assert(VT.isFloatingPoint() &&
3549 "remainder op must have integer or floating-point type");
3550 if (VT.isVector()) {
3551 Result = LegalizeOp(UnrollVectorOp(Op));
3553 // Floating point mod -> fmod libcall.
3554 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3555 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3557 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3565 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3566 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3568 MVT VT = Node->getValueType(0);
3569 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3570 default: assert(0 && "This action is not supported yet!");
3571 case TargetLowering::Custom:
3574 case TargetLowering::Legal:
3575 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3576 Result = Result.getValue(0);
3577 Tmp1 = Result.getValue(1);
3580 Tmp2 = TLI.LowerOperation(Result, DAG);
3581 if (Tmp2.getNode()) {
3582 Result = LegalizeOp(Tmp2);
3583 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3587 case TargetLowering::Expand: {
3588 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3589 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
3590 // Increment the pointer, VAList, to the next vaarg
3591 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
3592 DAG.getConstant(TLI.getTargetData()->
3593 getTypePaddedSize(VT.getTypeForMVT()),
3594 TLI.getPointerTy()));
3595 // Store the incremented VAList to the legalized pointer
3596 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
3597 // Load the actual argument out of the pointer VAList
3598 Result = DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0);
3599 Tmp1 = LegalizeOp(Result.getValue(1));
3600 Result = LegalizeOp(Result);
3604 // Since VAARG produces two values, make sure to remember that we
3605 // legalized both of them.
3606 AddLegalizedOperand(SDValue(Node, 0), Result);
3607 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3608 return Op.getResNo() ? Tmp1 : Result;
3612 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3613 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3614 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3616 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3617 default: assert(0 && "This action is not supported yet!");
3618 case TargetLowering::Custom:
3621 case TargetLowering::Legal:
3622 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3623 Node->getOperand(3), Node->getOperand(4));
3625 Tmp1 = TLI.LowerOperation(Result, DAG);
3626 if (Tmp1.getNode()) Result = Tmp1;
3629 case TargetLowering::Expand:
3630 // This defaults to loading a pointer from the input and storing it to the
3631 // output, returning the chain.
3632 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3633 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3634 Tmp4 = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp3, VS, 0);
3635 Result = DAG.getStore(Tmp4.getValue(1), dl, Tmp4, Tmp2, VD, 0);
3641 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3642 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3644 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3645 default: assert(0 && "This action is not supported yet!");
3646 case TargetLowering::Custom:
3649 case TargetLowering::Legal:
3650 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3652 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3653 if (Tmp1.getNode()) Result = Tmp1;
3656 case TargetLowering::Expand:
3657 Result = Tmp1; // Default to a no-op, return the chain
3663 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3664 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3666 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3668 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3669 default: assert(0 && "This action is not supported yet!");
3670 case TargetLowering::Legal: break;
3671 case TargetLowering::Custom:
3672 Tmp1 = TLI.LowerOperation(Result, DAG);
3673 if (Tmp1.getNode()) Result = Tmp1;
3680 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3681 Tmp2 = LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(1))); // RHS
3682 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3683 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3685 assert(0 && "ROTL/ROTR legalize operation not supported");
3687 case TargetLowering::Legal:
3689 case TargetLowering::Custom:
3690 Tmp1 = TLI.LowerOperation(Result, DAG);
3691 if (Tmp1.getNode()) Result = Tmp1;
3693 case TargetLowering::Promote:
3694 assert(0 && "Do not know how to promote ROTL/ROTR");
3696 case TargetLowering::Expand:
3697 assert(0 && "Do not know how to expand ROTL/ROTR");
3703 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3704 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3705 case TargetLowering::Custom:
3706 assert(0 && "Cannot custom legalize this yet!");
3707 case TargetLowering::Legal:
3708 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3710 case TargetLowering::Promote: {
3711 MVT OVT = Tmp1.getValueType();
3712 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3713 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3715 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
3716 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3717 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3718 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3721 case TargetLowering::Expand:
3722 Result = ExpandBSWAP(Tmp1, dl);
3730 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3731 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3732 case TargetLowering::Custom:
3733 case TargetLowering::Legal:
3734 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3735 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3736 TargetLowering::Custom) {
3737 Tmp1 = TLI.LowerOperation(Result, DAG);
3738 if (Tmp1.getNode()) {
3743 case TargetLowering::Promote: {
3744 MVT OVT = Tmp1.getValueType();
3745 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3747 // Zero extend the argument.
3748 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
3749 // Perform the larger operation, then subtract if needed.
3750 Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Tmp1);
3751 switch (Node->getOpcode()) {
3756 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3757 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3758 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3760 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3761 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3764 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3765 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3766 DAG.getConstant(NVT.getSizeInBits() -
3767 OVT.getSizeInBits(), NVT));
3772 case TargetLowering::Expand:
3773 Result = ExpandBitCount(Node->getOpcode(), Tmp1, dl);
3793 case ISD::FNEARBYINT:
3794 Tmp1 = LegalizeOp(Node->getOperand(0));
3795 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3796 case TargetLowering::Promote:
3797 case TargetLowering::Custom:
3800 case TargetLowering::Legal:
3801 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3803 Tmp1 = TLI.LowerOperation(Result, DAG);
3804 if (Tmp1.getNode()) Result = Tmp1;
3807 case TargetLowering::Expand:
3808 switch (Node->getOpcode()) {
3809 default: assert(0 && "Unreachable!");
3811 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3812 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3813 Result = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp2, Tmp1);
3816 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3817 MVT VT = Node->getValueType(0);
3818 Tmp2 = DAG.getConstantFP(0.0, VT);
3819 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3820 Tmp1, Tmp2, ISD::SETUGT);
3821 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3822 Result = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3837 case ISD::FNEARBYINT: {
3838 MVT VT = Node->getValueType(0);
3840 // Expand unsupported unary vector operators by unrolling them.
3841 if (VT.isVector()) {
3842 Result = LegalizeOp(UnrollVectorOp(Op));
3846 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3847 switch(Node->getOpcode()) {
3849 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3850 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3853 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3854 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3857 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3858 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3861 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3862 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3865 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3866 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3869 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3870 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3873 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3874 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3877 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3878 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3881 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3882 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3885 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3886 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3889 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3890 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3893 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3894 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3896 case ISD::FNEARBYINT:
3897 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3898 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3901 default: assert(0 && "Unreachable!");
3904 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3912 MVT VT = Node->getValueType(0);
3914 // Expand unsupported unary vector operators by unrolling them.
3915 if (VT.isVector()) {
3916 Result = LegalizeOp(UnrollVectorOp(Op));
3920 // We always lower FPOWI into a libcall. No target support for it yet.
3921 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3922 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3924 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3927 case ISD::BIT_CONVERT:
3928 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3929 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3930 Node->getValueType(0), dl);
3931 } else if (Op.getOperand(0).getValueType().isVector()) {
3932 // The input has to be a vector type, we have to either scalarize it, pack
3933 // it, or convert it based on whether the input vector type is legal.
3934 SDNode *InVal = Node->getOperand(0).getNode();
3935 int InIx = Node->getOperand(0).getResNo();
3936 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3937 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3939 // Figure out if there is a simple type corresponding to this Vector
3940 // type. If so, convert to the vector type.
3941 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3942 if (TLI.isTypeLegal(TVT)) {
3943 // Turn this into a bit convert of the vector input.
3944 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
3945 LegalizeOp(Node->getOperand(0)));
3947 } else if (NumElems == 1) {
3948 // Turn this into a bit convert of the scalar input.
3949 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
3950 ScalarizeVectorOp(Node->getOperand(0)));
3953 // FIXME: UNIMP! Store then reload
3954 assert(0 && "Cast from unsupported vector type not implemented yet!");
3957 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3958 Node->getOperand(0).getValueType())) {
3959 default: assert(0 && "Unknown operation action!");
3960 case TargetLowering::Expand:
3961 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3962 Node->getValueType(0), dl);
3964 case TargetLowering::Legal:
3965 Tmp1 = LegalizeOp(Node->getOperand(0));
3966 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3971 case ISD::CONVERT_RNDSAT: {
3972 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
3974 default: assert(0 && "Unknown cvt code!");
3985 SDValue DTyOp = Node->getOperand(1);
3986 SDValue STyOp = Node->getOperand(2);
3987 SDValue RndOp = Node->getOperand(3);
3988 SDValue SatOp = Node->getOperand(4);
3989 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3990 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3992 Tmp1 = LegalizeOp(Node->getOperand(0));
3993 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp,
3995 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3996 TargetLowering::Custom) {
3997 Tmp1 = TLI.LowerOperation(Result, DAG);
3998 if (Tmp1.getNode()) Result = Tmp1;
4002 Result = PromoteOp(Node->getOperand(0));
4003 // For FP, make Op1 a i32
4005 Result = DAG.getConvertRndSat(Op.getValueType(), dl, Result,
4006 DTyOp, STyOp, RndOp, SatOp, CvtCode);
4011 } // end switch CvtCode
4014 // Conversion operators. The source and destination have different types.
4015 case ISD::SINT_TO_FP:
4016 case ISD::UINT_TO_FP: {
4017 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
4018 Result = LegalizeINT_TO_FP(Result, isSigned,
4019 Node->getValueType(0), Node->getOperand(0), dl);
4023 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4025 Tmp1 = LegalizeOp(Node->getOperand(0));
4026 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
4027 default: assert(0 && "Unknown TRUNCATE legalization operation action!");
4028 case TargetLowering::Custom:
4031 case TargetLowering::Legal:
4032 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4034 Tmp1 = TLI.LowerOperation(Result, DAG);
4035 if (Tmp1.getNode()) Result = Tmp1;
4038 case TargetLowering::Expand:
4039 assert(Result.getValueType().isVector() && "must be vector type");
4040 // Unroll the truncate. We should do better.
4041 Result = LegalizeOp(UnrollVectorOp(Result));
4045 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4047 // Since the result is legal, we should just be able to truncate the low
4048 // part of the source.
4049 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
4052 Result = PromoteOp(Node->getOperand(0));
4053 Result = DAG.getNode(ISD::TRUNCATE, dl, Op.getValueType(), Result);
4058 case ISD::FP_TO_SINT:
4059 case ISD::FP_TO_UINT:
4060 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4062 Tmp1 = LegalizeOp(Node->getOperand(0));
4064 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
4065 default: assert(0 && "Unknown operation action!");
4066 case TargetLowering::Custom:
4069 case TargetLowering::Legal:
4070 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4072 Tmp1 = TLI.LowerOperation(Result, DAG);
4073 if (Tmp1.getNode()) Result = Tmp1;
4076 case TargetLowering::Promote:
4077 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
4078 Node->getOpcode() == ISD::FP_TO_SINT,
4081 case TargetLowering::Expand:
4082 if (Node->getOpcode() == ISD::FP_TO_UINT) {
4083 SDValue True, False;
4084 MVT VT = Node->getOperand(0).getValueType();
4085 MVT NVT = Node->getValueType(0);
4086 const uint64_t zero[] = {0, 0};
4087 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
4088 APInt x = APInt::getSignBit(NVT.getSizeInBits());
4089 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
4090 Tmp2 = DAG.getConstantFP(apf, VT);
4091 Tmp3 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
4092 Node->getOperand(0),
4094 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
4095 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
4096 DAG.getNode(ISD::FSUB, dl, VT,
4097 Node->getOperand(0), Tmp2));
4098 False = DAG.getNode(ISD::XOR, dl, NVT, False,
4099 DAG.getConstant(x, NVT));
4100 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp3, True, False);
4103 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
4109 MVT VT = Op.getValueType();
4110 MVT OVT = Node->getOperand(0).getValueType();
4111 // Convert ppcf128 to i32
4112 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
4113 if (Node->getOpcode() == ISD::FP_TO_SINT) {
4114 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
4115 Node->getOperand(0), DAG.getValueType(MVT::f64));
4116 Result = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Result,
4117 DAG.getIntPtrConstant(1));
4118 Result = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Result);
4120 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
4121 APFloat apf = APFloat(APInt(128, 2, TwoE31));
4122 Tmp2 = DAG.getConstantFP(apf, OVT);
4123 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
4124 // FIXME: generated code sucks.
4125 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Node->getOperand(0),
4127 DAG.getNode(ISD::ADD, dl, MVT::i32,
4128 DAG.getNode(ISD::FP_TO_SINT, dl, VT,
4129 DAG.getNode(ISD::FSUB, dl, OVT,
4130 Node->getOperand(0), Tmp2)),
4131 DAG.getConstant(0x80000000, MVT::i32)),
4132 DAG.getNode(ISD::FP_TO_SINT, dl, VT,
4133 Node->getOperand(0)),
4134 DAG.getCondCode(ISD::SETGE));
4138 // Convert f32 / f64 to i32 / i64 / i128.
4139 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
4140 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
4141 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
4143 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
4147 Tmp1 = PromoteOp(Node->getOperand(0));
4148 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
4149 Result = LegalizeOp(Result);
4154 case ISD::FP_EXTEND: {
4155 MVT DstVT = Op.getValueType();
4156 MVT SrcVT = Op.getOperand(0).getValueType();
4157 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4158 // The only other way we can lower this is to turn it into a STORE,
4159 // LOAD pair, targetting a temporary location (a stack slot).
4160 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT, dl);
4163 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4164 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4166 Tmp1 = LegalizeOp(Node->getOperand(0));
4167 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4170 Tmp1 = PromoteOp(Node->getOperand(0));
4171 Result = DAG.getNode(ISD::FP_EXTEND, dl, Op.getValueType(), Tmp1);
4176 case ISD::FP_ROUND: {
4177 MVT DstVT = Op.getValueType();
4178 MVT SrcVT = Op.getOperand(0).getValueType();
4179 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4180 if (SrcVT == MVT::ppcf128) {
4182 ExpandOp(Node->getOperand(0), Lo, Result);
4183 // Round it the rest of the way (e.g. to f32) if needed.
4184 if (DstVT!=MVT::f64)
4185 Result = DAG.getNode(ISD::FP_ROUND, dl,
4186 DstVT, Result, Op.getOperand(1));
4189 // The only other way we can lower this is to turn it into a STORE,
4190 // LOAD pair, targetting a temporary location (a stack slot).
4191 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT, dl);
4194 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4195 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4197 Tmp1 = LegalizeOp(Node->getOperand(0));
4198 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4201 Tmp1 = PromoteOp(Node->getOperand(0));
4202 Result = DAG.getNode(ISD::FP_ROUND, dl, Op.getValueType(), Tmp1,
4203 Node->getOperand(1));
4208 case ISD::ANY_EXTEND:
4209 case ISD::ZERO_EXTEND:
4210 case ISD::SIGN_EXTEND:
4211 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4212 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4214 Tmp1 = LegalizeOp(Node->getOperand(0));
4215 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4216 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4217 TargetLowering::Custom) {
4218 Tmp1 = TLI.LowerOperation(Result, DAG);
4219 if (Tmp1.getNode()) Result = Tmp1;
4223 switch (Node->getOpcode()) {
4224 case ISD::ANY_EXTEND:
4225 Tmp1 = PromoteOp(Node->getOperand(0));
4226 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Tmp1);
4228 case ISD::ZERO_EXTEND:
4229 Result = PromoteOp(Node->getOperand(0));
4230 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result);
4231 Result = DAG.getZeroExtendInReg(Result, dl,
4232 Node->getOperand(0).getValueType());
4234 case ISD::SIGN_EXTEND:
4235 Result = PromoteOp(Node->getOperand(0));
4236 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result);
4237 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(),
4239 DAG.getValueType(Node->getOperand(0).getValueType()));
4244 case ISD::FP_ROUND_INREG:
4245 case ISD::SIGN_EXTEND_INREG: {
4246 Tmp1 = LegalizeOp(Node->getOperand(0));
4247 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
4249 // If this operation is not supported, convert it to a shl/shr or load/store
4251 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
4252 default: assert(0 && "This action not supported for this op yet!");
4253 case TargetLowering::Legal:
4254 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4256 case TargetLowering::Expand:
4257 // If this is an integer extend and shifts are supported, do that.
4258 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
4259 // NOTE: we could fall back on load/store here too for targets without
4260 // SAR. However, it is doubtful that any exist.
4261 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
4262 ExtraVT.getSizeInBits();
4263 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
4264 Result = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
4265 Node->getOperand(0), ShiftCst);
4266 Result = DAG.getNode(ISD::SRA, dl, Node->getValueType(0),
4268 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
4269 // The only way we can lower this is to turn it into a TRUNCSTORE,
4270 // EXTLOAD pair, targetting a temporary location (a stack slot).
4272 // NOTE: there is a choice here between constantly creating new stack
4273 // slots and always reusing the same one. We currently always create
4274 // new ones, as reuse may inhibit scheduling.
4275 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
4276 Node->getValueType(0), dl);
4278 assert(0 && "Unknown op");
4284 case ISD::TRAMPOLINE: {
4286 for (unsigned i = 0; i != 6; ++i)
4287 Ops[i] = LegalizeOp(Node->getOperand(i));
4288 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
4289 // The only option for this node is to custom lower it.
4290 Result = TLI.LowerOperation(Result, DAG);
4291 assert(Result.getNode() && "Should always custom lower!");
4293 // Since trampoline produces two values, make sure to remember that we
4294 // legalized both of them.
4295 Tmp1 = LegalizeOp(Result.getValue(1));
4296 Result = LegalizeOp(Result);
4297 AddLegalizedOperand(SDValue(Node, 0), Result);
4298 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
4299 return Op.getResNo() ? Tmp1 : Result;
4301 case ISD::FLT_ROUNDS_: {
4302 MVT VT = Node->getValueType(0);
4303 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4304 default: assert(0 && "This action not supported for this op yet!");
4305 case TargetLowering::Custom:
4306 Result = TLI.LowerOperation(Op, DAG);
4307 if (Result.getNode()) break;
4309 case TargetLowering::Legal:
4310 // If this operation is not supported, lower it to constant 1
4311 Result = DAG.getConstant(1, VT);
4317 MVT VT = Node->getValueType(0);
4318 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4319 default: assert(0 && "This action not supported for this op yet!");
4320 case TargetLowering::Legal:
4321 Tmp1 = LegalizeOp(Node->getOperand(0));
4322 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4324 case TargetLowering::Custom:
4325 Result = TLI.LowerOperation(Op, DAG);
4326 if (Result.getNode()) break;
4328 case TargetLowering::Expand:
4329 // If this operation is not supported, lower it to 'abort()' call
4330 Tmp1 = LegalizeOp(Node->getOperand(0));
4331 TargetLowering::ArgListTy Args;
4332 std::pair<SDValue, SDValue> CallResult =
4333 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4334 false, false, false, false, CallingConv::C, false,
4335 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4337 Result = CallResult.second;
4345 MVT VT = Node->getValueType(0);
4346 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4347 default: assert(0 && "This action not supported for this op yet!");
4348 case TargetLowering::Custom:
4349 Result = TLI.LowerOperation(Op, DAG);
4350 if (Result.getNode()) break;
4352 case TargetLowering::Legal: {
4353 SDValue LHS = LegalizeOp(Node->getOperand(0));
4354 SDValue RHS = LegalizeOp(Node->getOperand(1));
4356 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
4357 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
4359 MVT OType = Node->getValueType(1);
4361 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
4363 // LHSSign -> LHS >= 0
4364 // RHSSign -> RHS >= 0
4365 // SumSign -> Sum >= 0
4368 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4370 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
4372 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
4373 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
4374 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
4375 Node->getOpcode() == ISD::SADDO ?
4376 ISD::SETEQ : ISD::SETNE);
4378 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
4379 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
4381 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
4383 MVT ValueVTs[] = { LHS.getValueType(), OType };
4384 SDValue Ops[] = { Sum, Cmp };
4386 Result = DAG.getNode(ISD::MERGE_VALUES, dl,
4387 DAG.getVTList(&ValueVTs[0], 2),
4389 SDNode *RNode = Result.getNode();
4390 DAG.ReplaceAllUsesWith(Node, RNode);
4399 MVT VT = Node->getValueType(0);
4400 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4401 default: assert(0 && "This action not supported for this op yet!");
4402 case TargetLowering::Custom:
4403 Result = TLI.LowerOperation(Op, DAG);
4404 if (Result.getNode()) break;
4406 case TargetLowering::Legal: {
4407 SDValue LHS = LegalizeOp(Node->getOperand(0));
4408 SDValue RHS = LegalizeOp(Node->getOperand(1));
4410 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
4411 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
4413 MVT OType = Node->getValueType(1);
4414 SDValue Cmp = DAG.getSetCC(dl, OType, Sum, LHS,
4415 Node->getOpcode () == ISD::UADDO ?
4416 ISD::SETULT : ISD::SETUGT);
4418 MVT ValueVTs[] = { LHS.getValueType(), OType };
4419 SDValue Ops[] = { Sum, Cmp };
4421 Result = DAG.getNode(ISD::MERGE_VALUES, dl,
4422 DAG.getVTList(&ValueVTs[0], 2),
4424 SDNode *RNode = Result.getNode();
4425 DAG.ReplaceAllUsesWith(Node, RNode);
4434 MVT VT = Node->getValueType(0);
4435 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4436 default: assert(0 && "This action is not supported at all!");
4437 case TargetLowering::Custom:
4438 Result = TLI.LowerOperation(Op, DAG);
4439 if (Result.getNode()) break;
4441 case TargetLowering::Legal:
4442 // FIXME: According to Hacker's Delight, this can be implemented in
4443 // target independent lowering, but it would be inefficient, since it
4444 // requires a division + a branch.
4445 assert(0 && "Target independent lowering is not supported for SMULO/UMULO!");
4453 assert(Result.getValueType() == Op.getValueType() &&
4454 "Bad legalization!");
4456 // Make sure that the generated code is itself legal.
4458 Result = LegalizeOp(Result);
4460 // Note that LegalizeOp may be reentered even from single-use nodes, which
4461 // means that we always must cache transformed nodes.
4462 AddLegalizedOperand(Op, Result);
4466 /// PromoteOp - Given an operation that produces a value in an invalid type,
4467 /// promote it to compute the value into a larger type. The produced value will
4468 /// have the correct bits for the low portion of the register, but no guarantee
4469 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4470 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4471 MVT VT = Op.getValueType();
4472 MVT NVT = TLI.getTypeToTransformTo(VT);
4473 assert(getTypeAction(VT) == Promote &&
4474 "Caller should expand or legalize operands that are not promotable!");
4475 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4476 "Cannot promote to smaller type!");
4478 SDValue Tmp1, Tmp2, Tmp3;
4480 SDNode *Node = Op.getNode();
4481 DebugLoc dl = Node->getDebugLoc();
4483 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4484 if (I != PromotedNodes.end()) return I->second;
4486 switch (Node->getOpcode()) {
4487 case ISD::CopyFromReg:
4488 assert(0 && "CopyFromReg must be legal!");
4491 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4493 assert(0 && "Do not know how to promote this operator!");
4496 Result = DAG.getUNDEF(NVT);
4500 Result = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Op);
4502 Result = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Op);
4503 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4505 case ISD::ConstantFP:
4506 Result = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op);
4507 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4511 MVT VT0 = Node->getOperand(0).getValueType();
4512 assert(isTypeLegal(TLI.getSetCCResultType(VT0))
4513 && "SetCC type is not legal??");
4514 Result = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(VT0),
4515 Node->getOperand(0), Node->getOperand(1),
4516 Node->getOperand(2));
4520 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4522 Result = LegalizeOp(Node->getOperand(0));
4523 assert(Result.getValueType().bitsGE(NVT) &&
4524 "This truncation doesn't make sense!");
4525 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4526 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Result);
4529 // The truncation is not required, because we don't guarantee anything
4530 // about high bits anyway.
4531 Result = PromoteOp(Node->getOperand(0));
4534 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4535 // Truncate the low part of the expanded value to the result type
4536 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Tmp1);
4539 case ISD::SIGN_EXTEND:
4540 case ISD::ZERO_EXTEND:
4541 case ISD::ANY_EXTEND:
4542 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4543 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4545 // Input is legal? Just do extend all the way to the larger type.
4546 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0));
4549 // Promote the reg if it's smaller.
4550 Result = PromoteOp(Node->getOperand(0));
4551 // The high bits are not guaranteed to be anything. Insert an extend.
4552 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4553 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
4554 DAG.getValueType(Node->getOperand(0).getValueType()));
4555 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4556 Result = DAG.getZeroExtendInReg(Result, dl,
4557 Node->getOperand(0).getValueType());
4561 case ISD::CONVERT_RNDSAT: {
4562 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4563 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
4564 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
4565 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
4566 "can only promote integers");
4567 Result = DAG.getConvertRndSat(NVT, dl, Node->getOperand(0),
4568 Node->getOperand(1), Node->getOperand(2),
4569 Node->getOperand(3), Node->getOperand(4),
4574 case ISD::BIT_CONVERT:
4575 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4576 Node->getValueType(0), dl);
4577 Result = PromoteOp(Result);
4580 case ISD::FP_EXTEND:
4581 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4583 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4584 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4585 case Promote: assert(0 && "Unreachable with 2 FP types!");
4587 if (Node->getConstantOperandVal(1) == 0) {
4588 // Input is legal? Do an FP_ROUND_INREG.
4589 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Node->getOperand(0),
4590 DAG.getValueType(VT));
4592 // Just remove the truncate, it isn't affecting the value.
4593 Result = DAG.getNode(ISD::FP_ROUND, dl, NVT, Node->getOperand(0),
4594 Node->getOperand(1));
4599 case ISD::SINT_TO_FP:
4600 case ISD::UINT_TO_FP:
4601 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4603 // No extra round required here.
4604 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0));
4608 Result = PromoteOp(Node->getOperand(0));
4609 if (Node->getOpcode() == ISD::SINT_TO_FP)
4610 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(),
4612 DAG.getValueType(Node->getOperand(0).getValueType()));
4614 Result = DAG.getZeroExtendInReg(Result, dl,
4615 Node->getOperand(0).getValueType());
4616 // No extra round required here.
4617 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Result);
4620 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4621 Node->getOperand(0), dl);
4622 // Round if we cannot tolerate excess precision.
4623 if (NoExcessFPPrecision)
4624 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4625 DAG.getValueType(VT));
4630 case ISD::SIGN_EXTEND_INREG:
4631 Result = PromoteOp(Node->getOperand(0));
4632 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
4633 Node->getOperand(1));
4635 case ISD::FP_TO_SINT:
4636 case ISD::FP_TO_UINT:
4637 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4640 Tmp1 = Node->getOperand(0);
4643 // The input result is prerounded, so we don't have to do anything
4645 Tmp1 = PromoteOp(Node->getOperand(0));
4648 // If we're promoting a UINT to a larger size, check to see if the new node
4649 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4650 // we can use that instead. This allows us to generate better code for
4651 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4652 // legal, such as PowerPC.
4653 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4654 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
4655 (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT) ||
4656 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4657 Result = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Tmp1);
4659 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4665 Tmp1 = PromoteOp(Node->getOperand(0));
4666 assert(Tmp1.getValueType() == NVT);
4667 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4668 // NOTE: we do not have to do any extra rounding here for
4669 // NoExcessFPPrecision, because we know the input will have the appropriate
4670 // precision, and these operations don't modify precision at all.
4685 case ISD::FNEARBYINT:
4686 Tmp1 = PromoteOp(Node->getOperand(0));
4687 assert(Tmp1.getValueType() == NVT);
4688 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4689 if (NoExcessFPPrecision)
4690 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4691 DAG.getValueType(VT));
4696 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4697 // directly as well, which may be better.
4698 Tmp1 = PromoteOp(Node->getOperand(0));
4699 Tmp2 = Node->getOperand(1);
4700 if (Node->getOpcode() == ISD::FPOW)
4701 Tmp2 = PromoteOp(Tmp2);
4702 assert(Tmp1.getValueType() == NVT);
4703 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4704 if (NoExcessFPPrecision)
4705 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4706 DAG.getValueType(VT));
4710 case ISD::ATOMIC_CMP_SWAP: {
4711 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4712 Tmp2 = PromoteOp(Node->getOperand(2));
4713 Tmp3 = PromoteOp(Node->getOperand(3));
4714 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
4715 AtomNode->getChain(),
4716 AtomNode->getBasePtr(), Tmp2, Tmp3,
4717 AtomNode->getSrcValue(),
4718 AtomNode->getAlignment());
4719 // Remember that we legalized the chain.
4720 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4723 case ISD::ATOMIC_LOAD_ADD:
4724 case ISD::ATOMIC_LOAD_SUB:
4725 case ISD::ATOMIC_LOAD_AND:
4726 case ISD::ATOMIC_LOAD_OR:
4727 case ISD::ATOMIC_LOAD_XOR:
4728 case ISD::ATOMIC_LOAD_NAND:
4729 case ISD::ATOMIC_LOAD_MIN:
4730 case ISD::ATOMIC_LOAD_MAX:
4731 case ISD::ATOMIC_LOAD_UMIN:
4732 case ISD::ATOMIC_LOAD_UMAX:
4733 case ISD::ATOMIC_SWAP: {
4734 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4735 Tmp2 = PromoteOp(Node->getOperand(2));
4736 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
4737 AtomNode->getChain(),
4738 AtomNode->getBasePtr(), Tmp2,
4739 AtomNode->getSrcValue(),
4740 AtomNode->getAlignment());
4741 // Remember that we legalized the chain.
4742 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4752 // The input may have strange things in the top bits of the registers, but
4753 // these operations don't care. They may have weird bits going out, but
4754 // that too is okay if they are integer operations.
4755 Tmp1 = PromoteOp(Node->getOperand(0));
4756 Tmp2 = PromoteOp(Node->getOperand(1));
4757 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4758 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4763 Tmp1 = PromoteOp(Node->getOperand(0));
4764 Tmp2 = PromoteOp(Node->getOperand(1));
4765 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4766 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4768 // Floating point operations will give excess precision that we may not be
4769 // able to tolerate. If we DO allow excess precision, just leave it,
4770 // otherwise excise it.
4771 // FIXME: Why would we need to round FP ops more than integer ones?
4772 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4773 if (NoExcessFPPrecision)
4774 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4775 DAG.getValueType(VT));
4780 // These operators require that their input be sign extended.
4781 Tmp1 = PromoteOp(Node->getOperand(0));
4782 Tmp2 = PromoteOp(Node->getOperand(1));
4783 if (NVT.isInteger()) {
4784 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
4785 DAG.getValueType(VT));
4786 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2,
4787 DAG.getValueType(VT));
4789 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4791 // Perform FP_ROUND: this is probably overly pessimistic.
4792 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4793 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4794 DAG.getValueType(VT));
4798 case ISD::FCOPYSIGN:
4799 // These operators require that their input be fp extended.
4800 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4801 case Expand: assert(0 && "not implemented");
4802 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4803 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4805 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4806 case Expand: assert(0 && "not implemented");
4807 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4808 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4810 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4812 // Perform FP_ROUND: this is probably overly pessimistic.
4813 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4814 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4815 DAG.getValueType(VT));
4820 // These operators require that their input be zero extended.
4821 Tmp1 = PromoteOp(Node->getOperand(0));
4822 Tmp2 = PromoteOp(Node->getOperand(1));
4823 assert(NVT.isInteger() && "Operators don't apply to FP!");
4824 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
4825 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT);
4826 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4830 Tmp1 = PromoteOp(Node->getOperand(0));
4831 Result = DAG.getNode(ISD::SHL, dl, NVT, Tmp1, Node->getOperand(1));
4834 // The input value must be properly sign extended.
4835 Tmp1 = PromoteOp(Node->getOperand(0));
4836 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
4837 DAG.getValueType(VT));
4838 Result = DAG.getNode(ISD::SRA, dl, NVT, Tmp1, Node->getOperand(1));
4841 // The input value must be properly zero extended.
4842 Tmp1 = PromoteOp(Node->getOperand(0));
4843 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
4844 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, Node->getOperand(1));
4848 Tmp1 = Node->getOperand(0); // Get the chain.
4849 Tmp2 = Node->getOperand(1); // Get the pointer.
4850 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4851 Tmp3 = DAG.getVAArg(VT, dl, Tmp1, Tmp2, Node->getOperand(2));
4852 Result = TLI.LowerOperation(Tmp3, DAG);
4854 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4855 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
4856 // Increment the pointer, VAList, to the next vaarg
4857 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
4858 DAG.getConstant(VT.getSizeInBits()/8,
4859 TLI.getPointerTy()));
4860 // Store the incremented VAList to the legalized pointer
4861 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
4862 // Load the actual argument out of the pointer VAList
4863 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Tmp3, VAList, NULL, 0, VT);
4865 // Remember that we legalized the chain.
4866 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4870 LoadSDNode *LD = cast<LoadSDNode>(Node);
4871 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4872 ? ISD::EXTLOAD : LD->getExtensionType();
4873 Result = DAG.getExtLoad(ExtType, dl, NVT,
4874 LD->getChain(), LD->getBasePtr(),
4875 LD->getSrcValue(), LD->getSrcValueOffset(),
4878 LD->getAlignment());
4879 // Remember that we legalized the chain.
4880 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4884 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4885 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4887 MVT VT2 = Tmp2.getValueType();
4888 assert(VT2 == Tmp3.getValueType()
4889 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4890 // Ensure that the resulting node is at least the same size as the operands'
4891 // value types, because we cannot assume that TLI.getSetCCValueType() is
4893 Result = DAG.getNode(ISD::SELECT, dl, VT2, Node->getOperand(0), Tmp2, Tmp3);
4896 case ISD::SELECT_CC:
4897 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4898 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4899 Result = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
4900 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4903 Tmp1 = Node->getOperand(0);
4904 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
4905 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4906 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
4907 DAG.getConstant(NVT.getSizeInBits() -
4909 TLI.getShiftAmountTy()));
4914 // Zero extend the argument
4915 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4916 // Perform the larger operation, then subtract if needed.
4917 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4918 switch(Node->getOpcode()) {
4923 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4924 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
4925 DAG.getConstant(NVT.getSizeInBits(), NVT),
4927 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
4928 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4931 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4932 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4933 DAG.getConstant(NVT.getSizeInBits() -
4934 VT.getSizeInBits(), NVT));
4938 case ISD::EXTRACT_SUBVECTOR:
4939 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4941 case ISD::EXTRACT_VECTOR_ELT:
4942 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4946 assert(Result.getNode() && "Didn't set a result!");
4948 // Make sure the result is itself legal.
4949 Result = LegalizeOp(Result);
4951 // Remember that we promoted this!
4952 AddPromotedOperand(Op, Result);
4956 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4957 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4958 /// based on the vector type. The return type of this matches the element type
4959 /// of the vector, which may not be legal for the target.
4960 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
4961 // We know that operand #0 is the Vec vector. If the index is a constant
4962 // or if the invec is a supported hardware type, we can use it. Otherwise,
4963 // lower to a store then an indexed load.
4964 SDValue Vec = Op.getOperand(0);
4965 SDValue Idx = Op.getOperand(1);
4966 DebugLoc dl = Op.getDebugLoc();
4968 MVT TVT = Vec.getValueType();
4969 unsigned NumElems = TVT.getVectorNumElements();
4971 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4972 default: assert(0 && "This action is not supported yet!");
4973 case TargetLowering::Custom: {
4974 Vec = LegalizeOp(Vec);
4975 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4976 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
4981 case TargetLowering::Legal:
4982 if (isTypeLegal(TVT)) {
4983 Vec = LegalizeOp(Vec);
4984 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4988 case TargetLowering::Promote:
4989 assert(TVT.isVector() && "not vector type");
4990 // fall thru to expand since vectors are by default are promote
4991 case TargetLowering::Expand:
4995 if (NumElems == 1) {
4996 // This must be an access of the only element. Return it.
4997 Op = ScalarizeVectorOp(Vec);
4998 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4999 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
5000 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5002 SplitVectorOp(Vec, Lo, Hi);
5003 if (CIdx->getZExtValue() < NumLoElts) {
5007 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
5008 Idx.getValueType());
5011 // It's now an extract from the appropriate high or low part. Recurse.
5012 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5013 Op = ExpandEXTRACT_VECTOR_ELT(Op);
5015 // Store the value to a temporary stack slot, then LOAD the scalar
5016 // element back out.
5017 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
5018 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
5020 // Add the offset to the index.
5021 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
5022 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
5023 DAG.getConstant(EltSize, Idx.getValueType()));
5025 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
5026 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
5028 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
5030 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
5032 Op = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0);
5037 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
5038 /// we assume the operation can be split if it is not already legal.
5039 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
5040 // We know that operand #0 is the Vec vector. For now we assume the index
5041 // is a constant and that the extracted result is a supported hardware type.
5042 SDValue Vec = Op.getOperand(0);
5043 SDValue Idx = LegalizeOp(Op.getOperand(1));
5045 unsigned NumElems = Vec.getValueType().getVectorNumElements();
5047 if (NumElems == Op.getValueType().getVectorNumElements()) {
5048 // This must be an access of the desired vector length. Return it.
5052 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5054 SplitVectorOp(Vec, Lo, Hi);
5055 if (CIdx->getZExtValue() < NumElems/2) {
5059 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
5060 Idx.getValueType());
5063 // It's now an extract from the appropriate high or low part. Recurse.
5064 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5065 return ExpandEXTRACT_SUBVECTOR(Op);
5068 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
5069 /// with condition CC on the current target. This usually involves legalizing
5070 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
5071 /// there may be no choice but to create a new SetCC node to represent the
5072 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
5073 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
5074 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
5078 SDValue Tmp1, Tmp2, Tmp3, Result;
5080 switch (getTypeAction(LHS.getValueType())) {
5082 Tmp1 = LegalizeOp(LHS); // LHS
5083 Tmp2 = LegalizeOp(RHS); // RHS
5086 Tmp1 = PromoteOp(LHS); // LHS
5087 Tmp2 = PromoteOp(RHS); // RHS
5089 // If this is an FP compare, the operands have already been extended.
5090 if (LHS.getValueType().isInteger()) {
5091 MVT VT = LHS.getValueType();
5092 MVT NVT = TLI.getTypeToTransformTo(VT);
5094 // Otherwise, we have to insert explicit sign or zero extends. Note
5095 // that we could insert sign extends for ALL conditions, but zero extend
5096 // is cheaper on many machines (an AND instead of two shifts), so prefer
5098 switch (cast<CondCodeSDNode>(CC)->get()) {
5099 default: assert(0 && "Unknown integer comparison!");
5106 // ALL of these operations will work if we either sign or zero extend
5107 // the operands (including the unsigned comparisons!). Zero extend is
5108 // usually a simpler/cheaper operation, so prefer it.
5109 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
5110 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT);
5116 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
5117 DAG.getValueType(VT));
5118 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2,
5119 DAG.getValueType(VT));
5120 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
5121 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
5127 MVT VT = LHS.getValueType();
5128 if (VT == MVT::f32 || VT == MVT::f64) {
5129 // Expand into one or more soft-fp libcall(s).
5130 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
5131 switch (cast<CondCodeSDNode>(CC)->get()) {
5134 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5138 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
5142 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5146 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5150 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5154 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5157 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5160 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
5163 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5164 switch (cast<CondCodeSDNode>(CC)->get()) {
5166 // SETONE = SETOLT | SETOGT
5167 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5170 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5173 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5176 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5179 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5182 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5184 default: assert(0 && "Unsupported FP setcc!");
5189 SDValue Ops[2] = { LHS, RHS };
5190 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2, dl).getNode(),
5191 false /*sign irrelevant*/, Dummy);
5192 Tmp2 = DAG.getConstant(0, MVT::i32);
5193 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
5194 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
5195 Tmp1 = DAG.getNode(ISD::SETCC, dl,
5196 TLI.getSetCCResultType(Tmp1.getValueType()),
5198 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2, dl).getNode(),
5199 false /*sign irrelevant*/, Dummy);
5200 Tmp2 = DAG.getNode(ISD::SETCC, dl,
5201 TLI.getSetCCResultType(LHS.getValueType()), LHS,
5202 Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
5203 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5206 LHS = LegalizeOp(Tmp1);
5211 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5212 ExpandOp(LHS, LHSLo, LHSHi);
5213 ExpandOp(RHS, RHSLo, RHSHi);
5214 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5216 if (VT==MVT::ppcf128) {
5217 // FIXME: This generated code sucks. We want to generate
5218 // FCMPU crN, hi1, hi2
5220 // FCMPU crN, lo1, lo2
5221 // The following can be improved, but not that much.
5222 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5223 LHSHi, RHSHi, ISD::SETOEQ);
5224 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
5225 LHSLo, RHSLo, CCCode);
5226 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5227 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5228 LHSHi, RHSHi, ISD::SETUNE);
5229 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5230 LHSHi, RHSHi, CCCode);
5231 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5232 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3);
5241 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
5242 if (RHSCST->isAllOnesValue()) {
5243 // Comparison to -1.
5244 Tmp1 = DAG.getNode(ISD::AND, dl,LHSLo.getValueType(), LHSLo, LHSHi);
5249 Tmp1 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
5250 Tmp2 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
5251 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5252 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
5255 // If this is a comparison of the sign bit, just look at the top part.
5257 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
5258 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
5259 CST->isNullValue()) || // X < 0
5260 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
5261 CST->isAllOnesValue())) { // X > -1
5267 // FIXME: This generated code sucks.
5268 ISD::CondCode LowCC;
5270 default: assert(0 && "Unknown integer setcc!");
5272 case ISD::SETULT: LowCC = ISD::SETULT; break;
5274 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5276 case ISD::SETULE: LowCC = ISD::SETULE; break;
5278 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5281 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
5282 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
5283 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
5285 // NOTE: on targets without efficient SELECT of bools, we can always use
5286 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5287 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
5288 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
5289 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
5290 if (!Tmp1.getNode())
5291 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
5292 LHSLo, RHSLo, LowCC);
5293 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5294 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
5295 if (!Tmp2.getNode())
5296 Tmp2 = DAG.getNode(ISD::SETCC, dl,
5297 TLI.getSetCCResultType(LHSHi.getValueType()),
5300 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
5301 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
5302 if ((Tmp1C && Tmp1C->isNullValue()) ||
5303 (Tmp2C && Tmp2C->isNullValue() &&
5304 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
5305 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
5306 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
5307 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
5308 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
5309 // low part is known false, returns high part.
5310 // For LE / GE, if high part is known false, ignore the low part.
5311 // For LT / GT, if high part is known true, ignore the low part.
5315 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5316 LHSHi, RHSHi, ISD::SETEQ, false,
5317 DagCombineInfo, dl);
5318 if (!Result.getNode())
5319 Result=DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5320 LHSHi, RHSHi, ISD::SETEQ);
5321 Result = LegalizeOp(DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
5322 Result, Tmp1, Tmp2));
5333 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
5334 /// condition code CC on the current target. This routine assumes LHS and rHS
5335 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
5336 /// illegal condition code into AND / OR of multiple SETCC values.
5337 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
5338 SDValue &LHS, SDValue &RHS,
5341 MVT OpVT = LHS.getValueType();
5342 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5343 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
5344 default: assert(0 && "Unknown condition code action!");
5345 case TargetLowering::Legal:
5348 case TargetLowering::Expand: {
5349 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
5352 default: assert(0 && "Don't know how to expand this condition!"); abort();
5353 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
5354 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5355 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5356 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5357 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5358 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5359 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5360 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5361 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5362 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5363 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5364 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5365 // FIXME: Implement more expansions.
5368 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
5369 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
5370 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
5378 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
5379 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
5380 /// a load from the stack slot to DestVT, extending it if needed.
5381 /// The resultant code need not be legal.
5382 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
5386 // Create the stack frame object.
5388 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
5390 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
5392 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
5393 int SPFI = StackPtrFI->getIndex();
5394 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
5396 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
5397 unsigned SlotSize = SlotVT.getSizeInBits();
5398 unsigned DestSize = DestVT.getSizeInBits();
5399 unsigned DestAlign =
5400 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForMVT());
5402 // Emit a store to the stack slot. Use a truncstore if the input value is
5403 // later than DestVT.
5406 if (SrcSize > SlotSize)
5407 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
5408 SV, 0, SlotVT, false, SrcAlign);
5410 assert(SrcSize == SlotSize && "Invalid store");
5411 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
5412 SV, 0, false, SrcAlign);
5415 // Result is a load from the stack slot.
5416 if (SlotSize == DestSize)
5417 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign);
5419 assert(SlotSize < DestSize && "Unknown extension!");
5420 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
5424 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
5425 DebugLoc dl = Node->getDebugLoc();
5426 // Create a vector sized/aligned stack slot, store the value to element #0,
5427 // then load the whole vector back out.
5428 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
5430 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
5431 int SPFI = StackPtrFI->getIndex();
5433 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
5435 PseudoSourceValue::getFixedStack(SPFI), 0,
5436 Node->getValueType(0).getVectorElementType());
5437 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
5438 PseudoSourceValue::getFixedStack(SPFI), 0);
5442 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
5443 /// support the operation, but do support the resultant vector type.
5444 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
5445 unsigned NumElems = Node->getNumOperands();
5446 SDValue SplatValue = Node->getOperand(0);
5447 DebugLoc dl = Node->getDebugLoc();
5448 MVT VT = Node->getValueType(0);
5449 MVT OpVT = SplatValue.getValueType();
5450 MVT EltVT = VT.getVectorElementType();
5452 // If the only non-undef value is the low element, turn this into a
5453 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
5454 bool isOnlyLowElement = true;
5456 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
5457 // and use a bitmask instead of a list of elements.
5458 // FIXME: this doesn't treat <0, u, 0, u> for example, as a splat.
5459 std::map<SDValue, std::vector<unsigned> > Values;
5460 Values[SplatValue].push_back(0);
5461 bool isConstant = true;
5462 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
5463 SplatValue.getOpcode() != ISD::UNDEF)
5466 for (unsigned i = 1; i < NumElems; ++i) {
5467 SDValue V = Node->getOperand(i);
5468 Values[V].push_back(i);
5469 if (V.getOpcode() != ISD::UNDEF)
5470 isOnlyLowElement = false;
5471 if (SplatValue != V)
5472 SplatValue = SDValue(0, 0);
5474 // If this isn't a constant element or an undef, we can't use a constant
5476 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
5477 V.getOpcode() != ISD::UNDEF)
5481 if (isOnlyLowElement) {
5482 // If the low element is an undef too, then this whole things is an undef.
5483 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
5484 return DAG.getUNDEF(VT);
5485 // Otherwise, turn this into a scalar_to_vector node.
5486 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
5489 // If all elements are constants, create a load from the constant pool.
5491 std::vector<Constant*> CV;
5492 for (unsigned i = 0, e = NumElems; i != e; ++i) {
5493 if (ConstantFPSDNode *V =
5494 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
5495 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
5496 } else if (ConstantSDNode *V =
5497 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
5498 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
5500 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
5501 const Type *OpNTy = OpVT.getTypeForMVT();
5502 CV.push_back(UndefValue::get(OpNTy));
5505 Constant *CP = ConstantVector::get(CV);
5506 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5507 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5508 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5509 PseudoSourceValue::getConstantPool(), 0,
5513 if (SplatValue.getNode()) { // Splat of one value?
5514 // Build the shuffle constant vector: <0, 0, 0, 0>
5515 SmallVector<int, 8> ZeroVec(NumElems, 0);
5517 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5518 if (TLI.isShuffleMaskLegal(ZeroVec, Node->getValueType(0))) {
5519 // Get the splatted value into the low element of a vector register.
5521 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, SplatValue);
5523 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5524 return DAG.getVectorShuffle(VT, dl, LowValVec, DAG.getUNDEF(VT),
5529 // If there are only two unique elements, we may be able to turn this into a
5531 if (Values.size() == 2) {
5532 // Get the two values in deterministic order.
5533 SDValue Val1 = Node->getOperand(1);
5535 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5536 if (MI->first != Val1)
5539 Val2 = (++MI)->first;
5541 // If Val1 is an undef, make sure it ends up as Val2, to ensure that our
5542 // vector shuffle has the undef vector on the RHS.
5543 if (Val1.getOpcode() == ISD::UNDEF)
5544 std::swap(Val1, Val2);
5546 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5547 SmallVector<int, 8> ShuffleMask(NumElems, -1);
5549 // Set elements of the shuffle mask for Val1.
5550 std::vector<unsigned> &Val1Elts = Values[Val1];
5551 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5552 ShuffleMask[Val1Elts[i]] = 0;
5554 // Set elements of the shuffle mask for Val2.
5555 std::vector<unsigned> &Val2Elts = Values[Val2];
5556 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5557 if (Val2.getOpcode() != ISD::UNDEF)
5558 ShuffleMask[Val2Elts[i]] = NumElems;
5560 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5561 if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR, VT) &&
5562 TLI.isShuffleMaskLegal(ShuffleMask, VT)) {
5563 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val1);
5564 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val2);
5565 return DAG.getVectorShuffle(VT, dl, Val1, Val2, &ShuffleMask[0]);
5569 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5570 // aligned object on the stack, store each element into it, then load
5571 // the result as a vector.
5572 // Create the stack frame object.
5573 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5574 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
5575 const Value *SV = PseudoSourceValue::getFixedStack(FI);
5577 // Emit a store of each element to the stack slot.
5578 SmallVector<SDValue, 8> Stores;
5579 unsigned TypeByteSize = OpVT.getSizeInBits() / 8;
5580 // Store (in the right endianness) the elements to memory.
5581 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5582 // Ignore undef elements.
5583 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5585 unsigned Offset = TypeByteSize*i;
5587 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5588 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
5590 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
5595 if (!Stores.empty()) // Not all undef elements?
5596 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5597 &Stores[0], Stores.size());
5599 StoreChain = DAG.getEntryNode();
5601 // Result is a load from the stack slot.
5602 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0);
5605 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5606 SDValue Op, SDValue Amt,
5607 SDValue &Lo, SDValue &Hi,
5609 // Expand the subcomponents.
5611 ExpandOp(Op, LHSL, LHSH);
5613 SDValue Ops[] = { LHSL, LHSH, Amt };
5614 MVT VT = LHSL.getValueType();
5615 Lo = DAG.getNode(NodeOp, dl, DAG.getVTList(VT, VT), Ops, 3);
5616 Hi = Lo.getValue(1);
5620 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5621 /// smaller elements. If we can't find a way that is more efficient than a
5622 /// libcall on this target, return false. Otherwise, return true with the
5623 /// low-parts expanded into Lo and Hi.
5624 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
5625 SDValue &Lo, SDValue &Hi,
5627 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5628 "This is not a shift!");
5630 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5631 SDValue ShAmt = LegalizeOp(Amt);
5632 MVT ShTy = ShAmt.getValueType();
5633 unsigned ShBits = ShTy.getSizeInBits();
5634 unsigned VTBits = Op.getValueType().getSizeInBits();
5635 unsigned NVTBits = NVT.getSizeInBits();
5637 // Handle the case when Amt is an immediate.
5638 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5639 unsigned Cst = CN->getZExtValue();
5640 // Expand the incoming operand to be shifted, so that we have its parts
5642 ExpandOp(Op, InL, InH);
5646 Lo = DAG.getConstant(0, NVT);
5647 Hi = DAG.getConstant(0, NVT);
5648 } else if (Cst > NVTBits) {
5649 Lo = DAG.getConstant(0, NVT);
5650 Hi = DAG.getNode(ISD::SHL, dl,
5651 NVT, InL, DAG.getConstant(Cst-NVTBits, ShTy));
5652 } else if (Cst == NVTBits) {
5653 Lo = DAG.getConstant(0, NVT);
5656 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Cst, ShTy));
5657 Hi = DAG.getNode(ISD::OR, dl, NVT,
5658 DAG.getNode(ISD::SHL, dl, NVT, InH, DAG.getConstant(Cst, ShTy)),
5659 DAG.getNode(ISD::SRL, dl, NVT, InL,
5660 DAG.getConstant(NVTBits-Cst, ShTy)));
5665 Lo = DAG.getConstant(0, NVT);
5666 Hi = DAG.getConstant(0, NVT);
5667 } else if (Cst > NVTBits) {
5668 Lo = DAG.getNode(ISD::SRL, dl, NVT,
5669 InH, DAG.getConstant(Cst-NVTBits, ShTy));
5670 Hi = DAG.getConstant(0, NVT);
5671 } else if (Cst == NVTBits) {
5673 Hi = DAG.getConstant(0, NVT);
5675 Lo = DAG.getNode(ISD::OR, dl, NVT,
5676 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
5677 DAG.getNode(ISD::SHL, dl, NVT, InH,
5678 DAG.getConstant(NVTBits-Cst, ShTy)));
5679 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
5684 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
5685 DAG.getConstant(NVTBits-1, ShTy));
5686 } else if (Cst > NVTBits) {
5687 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
5688 DAG.getConstant(Cst-NVTBits, ShTy));
5689 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
5690 DAG.getConstant(NVTBits-1, ShTy));
5691 } else if (Cst == NVTBits) {
5693 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
5694 DAG.getConstant(NVTBits-1, ShTy));
5696 Lo = DAG.getNode(ISD::OR, dl, NVT,
5697 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
5698 DAG.getNode(ISD::SHL, dl,
5699 NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5700 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
5706 // Okay, the shift amount isn't constant. However, if we can tell that it is
5707 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5708 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5709 APInt KnownZero, KnownOne;
5710 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5712 // If we know that if any of the high bits of the shift amount are one, then
5713 // we can do this as a couple of simple shifts.
5714 if (KnownOne.intersects(Mask)) {
5715 // Mask out the high bit, which we know is set.
5716 Amt = DAG.getNode(ISD::AND, dl, Amt.getValueType(), Amt,
5717 DAG.getConstant(~Mask, Amt.getValueType()));
5719 // Expand the incoming operand to be shifted, so that we have its parts
5721 ExpandOp(Op, InL, InH);
5724 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5725 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
5728 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5729 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
5732 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
5733 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5734 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
5739 // If we know that the high bits of the shift amount are all zero, then we can
5740 // do this as a couple of simple shifts.
5741 if ((KnownZero & Mask) == Mask) {
5743 SDValue Amt2 = DAG.getNode(ISD::SUB, dl, Amt.getValueType(),
5744 DAG.getConstant(NVTBits, Amt.getValueType()),
5747 // Expand the incoming operand to be shifted, so that we have its parts
5749 ExpandOp(Op, InL, InH);
5752 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
5753 Hi = DAG.getNode(ISD::OR, dl, NVT,
5754 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
5755 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2));
5758 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
5759 Lo = DAG.getNode(ISD::OR, dl, NVT,
5760 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
5761 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
5764 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
5765 Lo = DAG.getNode(ISD::OR, dl, NVT,
5766 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
5767 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
5776 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5777 // does not fit into a register, return the lo part and set the hi part to the
5778 // by-reg argument. If it does fit into a single register, return the result
5779 // and leave the Hi part unset.
5780 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5781 bool isSigned, SDValue &Hi) {
5782 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5783 // The input chain to this libcall is the entry node of the function.
5784 // Legalizing the call will automatically add the previous call to the
5786 SDValue InChain = DAG.getEntryNode();
5788 TargetLowering::ArgListTy Args;
5789 TargetLowering::ArgListEntry Entry;
5790 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5791 MVT ArgVT = Node->getOperand(i).getValueType();
5792 const Type *ArgTy = ArgVT.getTypeForMVT();
5793 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5794 Entry.isSExt = isSigned;
5795 Entry.isZExt = !isSigned;
5796 Args.push_back(Entry);
5798 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5799 TLI.getPointerTy());
5801 // Splice the libcall in wherever FindInputOutputChains tells us to.
5802 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5803 std::pair<SDValue, SDValue> CallInfo =
5804 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5805 CallingConv::C, false, Callee, Args, DAG,
5806 Node->getDebugLoc());
5808 // Legalize the call sequence, starting with the chain. This will advance
5809 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5810 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5811 LegalizeOp(CallInfo.second);
5813 switch (getTypeAction(CallInfo.first.getValueType())) {
5814 default: assert(0 && "Unknown thing");
5816 Result = CallInfo.first;
5819 ExpandOp(CallInfo.first, Result, Hi);
5825 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5827 SDValue SelectionDAGLegalize::
5828 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op,
5830 bool isCustom = false;
5832 switch (getTypeAction(Op.getValueType())) {
5834 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5835 Op.getValueType())) {
5836 default: assert(0 && "Unknown operation action!");
5837 case TargetLowering::Custom:
5840 case TargetLowering::Legal:
5841 Tmp1 = LegalizeOp(Op);
5842 if (Result.getNode())
5843 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5845 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl,
5848 Tmp1 = TLI.LowerOperation(Result, DAG);
5849 if (Tmp1.getNode()) Result = Tmp1;
5852 case TargetLowering::Expand:
5853 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy, dl);
5855 case TargetLowering::Promote:
5856 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned, dl);
5861 Result = ExpandIntToFP(isSigned, DestTy, Op, dl) ;
5864 Tmp1 = PromoteOp(Op);
5866 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp1.getValueType(),
5867 Tmp1, DAG.getValueType(Op.getValueType()));
5869 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, Op.getValueType());
5871 if (Result.getNode())
5872 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5874 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl,
5876 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5882 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5884 SDValue SelectionDAGLegalize::
5885 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl) {
5886 MVT SourceVT = Source.getValueType();
5887 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5889 // Expand unsupported int-to-fp vector casts by unrolling them.
5890 if (DestTy.isVector()) {
5892 return LegalizeOp(UnrollVectorOp(Source));
5893 MVT DestEltTy = DestTy.getVectorElementType();
5894 if (DestTy.getVectorNumElements() == 1) {
5895 SDValue Scalar = ScalarizeVectorOp(Source);
5896 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5897 DestEltTy, Scalar, dl);
5898 return DAG.getNode(ISD::BUILD_VECTOR, dl, DestTy, Result);
5901 SplitVectorOp(Source, Lo, Hi);
5902 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5903 DestTy.getVectorNumElements() / 2);
5904 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
5906 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
5908 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, DestTy, LoResult,
5912 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5913 if (!isSigned && SourceVT != MVT::i32) {
5914 // The integer value loaded will be incorrectly if the 'sign bit' of the
5915 // incoming integer is set. To handle this, we dynamically test to see if
5916 // it is set, and, if so, add a fudge factor.
5920 ExpandOp(Source, Lo, Hi);
5921 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, Lo, Hi);
5923 // The comparison for the sign bit will use the entire operand.
5927 // Check to see if the target has a custom way to lower this. If so, use
5928 // it. (Note we've already expanded the operand in this case.)
5929 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) {
5930 default: assert(0 && "This action not implemented for this operation!");
5931 case TargetLowering::Legal:
5932 case TargetLowering::Expand:
5933 break; // This case is handled below.
5934 case TargetLowering::Custom: {
5935 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, dl, DestTy,
5938 return LegalizeOp(NV);
5939 break; // The target decided this was legal after all
5943 // If this is unsigned, and not supported, first perform the conversion to
5944 // signed, then adjust the result if the sign bit is set.
5945 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source, dl);
5947 SDValue SignSet = DAG.getSetCC(dl,
5948 TLI.getSetCCResultType(Hi.getValueType()),
5949 Hi, DAG.getConstant(0, Hi.getValueType()),
5951 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5952 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
5953 SignSet, Four, Zero);
5954 uint64_t FF = 0x5f800000ULL;
5955 if (TLI.isLittleEndian()) FF <<= 32;
5956 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5958 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5959 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5960 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
5961 Alignment = std::min(Alignment, 4u);
5963 if (DestTy == MVT::f32)
5964 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
5965 PseudoSourceValue::getConstantPool(), 0,
5967 else if (DestTy.bitsGT(MVT::f32))
5968 // FIXME: Avoid the extend by construction the right constantpool?
5969 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, dl, DestTy, DAG.getEntryNode(),
5971 PseudoSourceValue::getConstantPool(), 0,
5972 MVT::f32, false, Alignment);
5974 assert(0 && "Unexpected conversion");
5976 MVT SCVT = SignedConv.getValueType();
5977 if (SCVT != DestTy) {
5978 // Destination type needs to be expanded as well. The FADD now we are
5979 // constructing will be expanded into a libcall.
5980 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5981 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5982 SignedConv = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy,
5983 SignedConv, SignedConv.getValue(1));
5985 SignedConv = DAG.getNode(ISD::BIT_CONVERT, dl, DestTy, SignedConv);
5987 return DAG.getNode(ISD::FADD, dl, DestTy, SignedConv, FudgeInReg);
5990 // Check to see if the target has a custom way to lower this. If so, use it.
5991 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5992 default: assert(0 && "This action not implemented for this operation!");
5993 case TargetLowering::Legal:
5994 case TargetLowering::Expand:
5995 break; // This case is handled below.
5996 case TargetLowering::Custom: {
5997 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, dl, DestTy,
6000 return LegalizeOp(NV);
6001 break; // The target decided this was legal after all
6005 // Expand the source, then glue it back together for the call. We must expand
6006 // the source in case it is shared (this pass of legalize must traverse it).
6008 SDValue SrcLo, SrcHi;
6009 ExpandOp(Source, SrcLo, SrcHi);
6010 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, SrcLo, SrcHi);
6013 RTLIB::Libcall LC = isSigned ?
6014 RTLIB::getSINTTOFP(SourceVT, DestTy) :
6015 RTLIB::getUINTTOFP(SourceVT, DestTy);
6016 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
6018 Source = DAG.getNode(ISD::SINT_TO_FP, dl, DestTy, Source);
6020 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
6021 if (Result.getValueType() != DestTy && HiPart.getNode())
6022 Result = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy, Result, HiPart);
6026 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
6027 /// INT_TO_FP operation of the specified operand when the target requests that
6028 /// we expand it. At this point, we know that the result and operand types are
6029 /// legal for the target.
6030 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
6034 if (Op0.getValueType() == MVT::i32) {
6035 // simple 32-bit [signed|unsigned] integer to float/double expansion
6037 // Get the stack frame index of a 8 byte buffer.
6038 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
6040 // word offset constant for Hi/Lo address computation
6041 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
6042 // set up Hi and Lo (into buffer) address based on endian
6043 SDValue Hi = StackSlot;
6044 SDValue Lo = DAG.getNode(ISD::ADD, dl,
6045 TLI.getPointerTy(), StackSlot, WordOff);
6046 if (TLI.isLittleEndian())
6049 // if signed map to unsigned space
6052 // constant used to invert sign bit (signed to unsigned mapping)
6053 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
6054 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
6058 // store the lo of the constructed double - based on integer input
6059 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
6060 Op0Mapped, Lo, NULL, 0);
6061 // initial hi portion of constructed double
6062 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
6063 // store the hi of the constructed double - biased exponent
6064 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
6065 // load the constructed double
6066 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
6067 // FP constant to bias correct the final result
6068 SDValue Bias = DAG.getConstantFP(isSigned ?
6069 BitsToDouble(0x4330000080000000ULL) :
6070 BitsToDouble(0x4330000000000000ULL),
6072 // subtract the bias
6073 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
6076 // handle final rounding
6077 if (DestVT == MVT::f64) {
6080 } else if (DestVT.bitsLT(MVT::f64)) {
6081 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
6082 DAG.getIntPtrConstant(0));
6083 } else if (DestVT.bitsGT(MVT::f64)) {
6084 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
6088 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
6089 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
6091 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
6092 Op0, DAG.getConstant(0, Op0.getValueType()),
6094 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
6095 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
6096 SignSet, Four, Zero);
6098 // If the sign bit of the integer is set, the large number will be treated
6099 // as a negative number. To counteract this, the dynamic code adds an
6100 // offset depending on the data type.
6102 switch (Op0.getValueType().getSimpleVT()) {
6103 default: assert(0 && "Unsupported integer type!");
6104 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
6105 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
6106 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
6107 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
6109 if (TLI.isLittleEndian()) FF <<= 32;
6110 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
6112 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
6113 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6114 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
6115 Alignment = std::min(Alignment, 4u);
6117 if (DestVT == MVT::f32)
6118 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
6119 PseudoSourceValue::getConstantPool(), 0,
6123 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
6124 DAG.getEntryNode(), CPIdx,
6125 PseudoSourceValue::getConstantPool(), 0,
6126 MVT::f32, false, Alignment));
6129 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
6132 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
6133 /// *INT_TO_FP operation of the specified operand when the target requests that
6134 /// we promote it. At this point, we know that the result and operand types are
6135 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
6136 /// operation that takes a larger input.
6137 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
6141 // First step, figure out the appropriate *INT_TO_FP operation to use.
6142 MVT NewInTy = LegalOp.getValueType();
6144 unsigned OpToUse = 0;
6146 // Scan for the appropriate larger type to use.
6148 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
6149 assert(NewInTy.isInteger() && "Ran out of possibilities!");
6151 // If the target supports SINT_TO_FP of this type, use it.
6152 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
6154 case TargetLowering::Legal:
6155 if (!TLI.isTypeLegal(NewInTy))
6156 break; // Can't use this datatype.
6158 case TargetLowering::Custom:
6159 OpToUse = ISD::SINT_TO_FP;
6163 if (isSigned) continue;
6165 // If the target supports UINT_TO_FP of this type, use it.
6166 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
6168 case TargetLowering::Legal:
6169 if (!TLI.isTypeLegal(NewInTy))
6170 break; // Can't use this datatype.
6172 case TargetLowering::Custom:
6173 OpToUse = ISD::UINT_TO_FP;
6178 // Otherwise, try a larger type.
6181 // Okay, we found the operation and type to use. Zero extend our input to the
6182 // desired type then run the operation on it.
6183 return DAG.getNode(OpToUse, dl, DestVT,
6184 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
6185 dl, NewInTy, LegalOp));
6188 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
6189 /// FP_TO_*INT operation of the specified operand when the target requests that
6190 /// we promote it. At this point, we know that the result and operand types are
6191 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
6192 /// operation that returns a larger result.
6193 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
6197 // First step, figure out the appropriate FP_TO*INT operation to use.
6198 MVT NewOutTy = DestVT;
6200 unsigned OpToUse = 0;
6202 // Scan for the appropriate larger type to use.
6204 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
6205 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
6207 // If the target supports FP_TO_SINT returning this type, use it.
6208 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
6210 case TargetLowering::Legal:
6211 if (!TLI.isTypeLegal(NewOutTy))
6212 break; // Can't use this datatype.
6214 case TargetLowering::Custom:
6215 OpToUse = ISD::FP_TO_SINT;
6220 // If the target supports FP_TO_UINT of this type, use it.
6221 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
6223 case TargetLowering::Legal:
6224 if (!TLI.isTypeLegal(NewOutTy))
6225 break; // Can't use this datatype.
6227 case TargetLowering::Custom:
6228 OpToUse = ISD::FP_TO_UINT;
6233 // Otherwise, try a larger type.
6237 // Okay, we found the operation and type to use.
6238 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
6240 // If the operation produces an invalid type, it must be custom lowered. Use
6241 // the target lowering hooks to expand it. Just keep the low part of the
6242 // expanded operation, we know that we're truncating anyway.
6243 if (getTypeAction(NewOutTy) == Expand) {
6244 SmallVector<SDValue, 2> Results;
6245 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG);
6246 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!");
6247 Operation = Results[0];
6250 // Truncate the result of the extended FP_TO_*INT operation to the desired
6252 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
6255 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
6257 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
6258 MVT VT = Op.getValueType();
6259 MVT SHVT = TLI.getShiftAmountTy();
6260 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
6261 switch (VT.getSimpleVT()) {
6262 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
6264 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6265 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6266 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
6268 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
6269 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6270 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6271 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
6272 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
6273 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
6274 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
6275 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
6276 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
6278 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
6279 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
6280 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
6281 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6282 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6283 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
6284 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
6285 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
6286 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
6287 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
6288 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
6289 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
6290 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
6291 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
6292 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
6293 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
6294 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
6295 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
6296 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
6297 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
6298 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
6302 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
6304 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
6307 default: assert(0 && "Cannot expand this yet!");
6309 static const uint64_t mask[6] = {
6310 0x5555555555555555ULL, 0x3333333333333333ULL,
6311 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
6312 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
6314 MVT VT = Op.getValueType();
6315 MVT ShVT = TLI.getShiftAmountTy();
6316 unsigned len = VT.getSizeInBits();
6317 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6318 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
6319 unsigned EltSize = VT.isVector() ?
6320 VT.getVectorElementType().getSizeInBits() : len;
6321 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
6322 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6323 Op = DAG.getNode(ISD::ADD, dl, VT,
6324 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
6325 DAG.getNode(ISD::AND, dl, VT,
6326 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
6332 // for now, we do this:
6333 // x = x | (x >> 1);
6334 // x = x | (x >> 2);
6336 // x = x | (x >>16);
6337 // x = x | (x >>32); // for 64-bit input
6338 // return popcount(~x);
6340 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
6341 MVT VT = Op.getValueType();
6342 MVT ShVT = TLI.getShiftAmountTy();
6343 unsigned len = VT.getSizeInBits();
6344 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6345 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6346 Op = DAG.getNode(ISD::OR, dl, VT, Op,
6347 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
6349 Op = DAG.getNOT(dl, Op, VT);
6350 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
6353 // for now, we use: { return popcount(~x & (x - 1)); }
6354 // unless the target has ctlz but not ctpop, in which case we use:
6355 // { return 32 - nlz(~x & (x-1)); }
6356 // see also http://www.hackersdelight.org/HDcode/ntz.cc
6357 MVT VT = Op.getValueType();
6358 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
6359 DAG.getNOT(dl, Op, VT),
6360 DAG.getNode(ISD::SUB, dl, VT, Op,
6361 DAG.getConstant(1, VT)));
6362 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6363 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
6364 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
6365 return DAG.getNode(ISD::SUB, dl, VT,
6366 DAG.getConstant(VT.getSizeInBits(), VT),
6367 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
6368 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
6373 /// ExpandOp - Expand the specified SDValue into its two component pieces
6374 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
6375 /// LegalizedNodes map is filled in for any results that are not expanded, the
6376 /// ExpandedNodes map is filled in for any results that are expanded, and the
6377 /// Lo/Hi values are returned.
6378 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
6379 MVT VT = Op.getValueType();
6380 MVT NVT = TLI.getTypeToTransformTo(VT);
6381 SDNode *Node = Op.getNode();
6382 DebugLoc dl = Node->getDebugLoc();
6383 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
6384 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
6385 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
6387 // See if we already expanded it.
6388 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
6389 = ExpandedNodes.find(Op);
6390 if (I != ExpandedNodes.end()) {
6391 Lo = I->second.first;
6392 Hi = I->second.second;
6396 switch (Node->getOpcode()) {
6397 case ISD::CopyFromReg:
6398 assert(0 && "CopyFromReg must be legal!");
6399 case ISD::FP_ROUND_INREG:
6400 if (VT == MVT::ppcf128 &&
6401 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
6402 TargetLowering::Custom) {
6403 SDValue SrcLo, SrcHi, Src;
6404 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
6405 Src = DAG.getNode(ISD::BUILD_PAIR, dl, VT, SrcLo, SrcHi);
6407 TLI.LowerOperation(DAG.getNode(ISD::FP_ROUND_INREG, dl, VT, Src,
6408 Op.getOperand(1)), DAG);
6409 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
6410 Lo = Result.getNode()->getOperand(0);
6411 Hi = Result.getNode()->getOperand(1);
6417 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
6419 assert(0 && "Do not know how to expand this operator!");
6421 case ISD::EXTRACT_ELEMENT:
6422 ExpandOp(Node->getOperand(0), Lo, Hi);
6423 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
6424 return ExpandOp(Hi, Lo, Hi);
6425 return ExpandOp(Lo, Lo, Hi);
6426 case ISD::EXTRACT_VECTOR_ELT:
6427 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
6428 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
6429 return ExpandOp(Lo, Lo, Hi);
6431 Lo = DAG.getUNDEF(NVT);
6432 Hi = DAG.getUNDEF(NVT);
6434 case ISD::Constant: {
6435 unsigned NVTBits = NVT.getSizeInBits();
6436 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
6437 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
6438 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
6441 case ISD::ConstantFP: {
6442 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
6443 if (CFP->getValueType(0) == MVT::ppcf128) {
6444 APInt api = CFP->getValueAPF().bitcastToAPInt();
6445 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
6447 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
6451 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
6452 if (getTypeAction(Lo.getValueType()) == Expand)
6453 ExpandOp(Lo, Lo, Hi);
6456 case ISD::BUILD_PAIR:
6457 // Return the operands.
6458 Lo = Node->getOperand(0);
6459 Hi = Node->getOperand(1);
6462 case ISD::MERGE_VALUES:
6463 if (Node->getNumValues() == 1) {
6464 ExpandOp(Op.getOperand(0), Lo, Hi);
6467 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
6468 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
6469 Op.getValue(1).getValueType() == MVT::Other &&
6470 "unhandled MERGE_VALUES");
6471 ExpandOp(Op.getOperand(0), Lo, Hi);
6472 // Remember that we legalized the chain.
6473 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
6476 case ISD::SIGN_EXTEND_INREG:
6477 ExpandOp(Node->getOperand(0), Lo, Hi);
6478 // sext_inreg the low part if needed.
6479 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Lo, Node->getOperand(1));
6481 // The high part gets the sign extension from the lo-part. This handles
6482 // things like sextinreg V:i64 from i8.
6483 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6484 DAG.getConstant(NVT.getSizeInBits()-1,
6485 TLI.getShiftAmountTy()));
6489 ExpandOp(Node->getOperand(0), Lo, Hi);
6490 SDValue TempLo = DAG.getNode(ISD::BSWAP, dl, NVT, Hi);
6491 Hi = DAG.getNode(ISD::BSWAP, dl, NVT, Lo);
6497 ExpandOp(Node->getOperand(0), Lo, Hi);
6498 Lo = DAG.getNode(ISD::ADD, dl, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
6499 DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
6500 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
6501 Hi = DAG.getConstant(0, NVT);
6505 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
6506 ExpandOp(Node->getOperand(0), Lo, Hi);
6507 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6508 SDValue HLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
6509 SDValue TopNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), HLZ,
6511 SDValue LowPart = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
6512 LowPart = DAG.getNode(ISD::ADD, dl, NVT, LowPart, BitsC);
6514 Lo = DAG.getNode(ISD::SELECT, dl, NVT, TopNotZero, HLZ, LowPart);
6515 Hi = DAG.getConstant(0, NVT);
6520 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
6521 ExpandOp(Node->getOperand(0), Lo, Hi);
6522 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6523 SDValue LTZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
6524 SDValue BotNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), LTZ,
6526 SDValue HiPart = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
6527 HiPart = DAG.getNode(ISD::ADD, dl, NVT, HiPart, BitsC);
6529 Lo = DAG.getNode(ISD::SELECT, dl, NVT, BotNotZero, LTZ, HiPart);
6530 Hi = DAG.getConstant(0, NVT);
6535 SDValue Ch = Node->getOperand(0); // Legalize the chain.
6536 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6537 Lo = DAG.getVAArg(NVT, dl, Ch, Ptr, Node->getOperand(2));
6538 Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, Node->getOperand(2));
6540 // Remember that we legalized the chain.
6541 Hi = LegalizeOp(Hi);
6542 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6543 if (TLI.isBigEndian())
6549 LoadSDNode *LD = cast<LoadSDNode>(Node);
6550 SDValue Ch = LD->getChain(); // Legalize the chain.
6551 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6552 ISD::LoadExtType ExtType = LD->getExtensionType();
6553 const Value *SV = LD->getSrcValue();
6554 int SVOffset = LD->getSrcValueOffset();
6555 unsigned Alignment = LD->getAlignment();
6556 bool isVolatile = LD->isVolatile();
6558 if (ExtType == ISD::NON_EXTLOAD) {
6559 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset,
6560 isVolatile, Alignment);
6561 if (VT == MVT::f32 || VT == MVT::f64) {
6562 // f32->i32 or f64->i64 one to one expansion.
6563 // Remember that we legalized the chain.
6564 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6565 // Recursively expand the new load.
6566 if (getTypeAction(NVT) == Expand)
6567 ExpandOp(Lo, Lo, Hi);
6571 // Increment the pointer to the other half.
6572 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6573 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
6574 DAG.getIntPtrConstant(IncrementSize));
6575 SVOffset += IncrementSize;
6576 Alignment = MinAlign(Alignment, IncrementSize);
6577 Hi = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset,
6578 isVolatile, Alignment);
6580 // Build a factor node to remember that this load is independent of the
6582 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
6585 // Remember that we legalized the chain.
6586 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6587 if (TLI.isBigEndian())
6590 MVT EVT = LD->getMemoryVT();
6592 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6593 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6594 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6595 SDValue Load = DAG.getLoad(EVT, dl, Ch, Ptr, SV,
6596 SVOffset, isVolatile, Alignment);
6597 // Remember that we legalized the chain.
6598 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6599 ExpandOp(DAG.getNode(ISD::FP_EXTEND, dl, VT, Load), Lo, Hi);
6604 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV,
6605 SVOffset, isVolatile, Alignment);
6607 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, SV,
6608 SVOffset, EVT, isVolatile,
6611 // Remember that we legalized the chain.
6612 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6614 if (ExtType == ISD::SEXTLOAD) {
6615 // The high part is obtained by SRA'ing all but one of the bits of the
6617 unsigned LoSize = Lo.getValueType().getSizeInBits();
6618 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6619 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6620 } else if (ExtType == ISD::ZEXTLOAD) {
6621 // The high part is just a zero.
6622 Hi = DAG.getConstant(0, NVT);
6623 } else /* if (ExtType == ISD::EXTLOAD) */ {
6624 // The high part is undefined.
6625 Hi = DAG.getUNDEF(NVT);
6632 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6633 SDValue LL, LH, RL, RH;
6634 ExpandOp(Node->getOperand(0), LL, LH);
6635 ExpandOp(Node->getOperand(1), RL, RH);
6636 Lo = DAG.getNode(Node->getOpcode(), dl, NVT, LL, RL);
6637 Hi = DAG.getNode(Node->getOpcode(), dl, NVT, LH, RH);
6641 SDValue LL, LH, RL, RH;
6642 ExpandOp(Node->getOperand(1), LL, LH);
6643 ExpandOp(Node->getOperand(2), RL, RH);
6644 if (getTypeAction(NVT) == Expand)
6645 NVT = TLI.getTypeToExpandTo(NVT);
6646 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LL, RL);
6648 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LH, RH);
6651 case ISD::SELECT_CC: {
6652 SDValue TL, TH, FL, FH;
6653 ExpandOp(Node->getOperand(2), TL, TH);
6654 ExpandOp(Node->getOperand(3), FL, FH);
6655 if (getTypeAction(NVT) == Expand)
6656 NVT = TLI.getTypeToExpandTo(NVT);
6657 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
6658 Node->getOperand(1), TL, FL, Node->getOperand(4));
6660 Hi = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
6661 Node->getOperand(1), TH, FH, Node->getOperand(4));
6664 case ISD::ANY_EXTEND:
6665 // The low part is any extension of the input (which degenerates to a copy).
6666 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0));
6667 // The high part is undefined.
6668 Hi = DAG.getUNDEF(NVT);
6670 case ISD::SIGN_EXTEND: {
6671 // The low part is just a sign extension of the input (which degenerates to
6673 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Node->getOperand(0));
6675 // The high part is obtained by SRA'ing all but one of the bits of the lo
6677 unsigned LoSize = Lo.getValueType().getSizeInBits();
6678 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6679 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6682 case ISD::ZERO_EXTEND:
6683 // The low part is just a zero extension of the input (which degenerates to
6685 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
6687 // The high part is just a zero.
6688 Hi = DAG.getConstant(0, NVT);
6691 case ISD::TRUNCATE: {
6692 // The input value must be larger than this value. Expand *it*.
6694 ExpandOp(Node->getOperand(0), NewLo, Hi);
6696 // The low part is now either the right size, or it is closer. If not the
6697 // right size, make an illegal truncate so we recursively expand it.
6698 if (NewLo.getValueType() != Node->getValueType(0))
6699 NewLo = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), NewLo);
6700 ExpandOp(NewLo, Lo, Hi);
6704 case ISD::BIT_CONVERT: {
6706 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6707 // If the target wants to, allow it to lower this itself.
6708 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6709 case Expand: assert(0 && "cannot expand FP!");
6710 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6711 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6713 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp), DAG);
6716 // f32 / f64 must be expanded to i32 / i64.
6717 if (VT == MVT::f32 || VT == MVT::f64) {
6718 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
6719 if (getTypeAction(NVT) == Expand)
6720 ExpandOp(Lo, Lo, Hi);
6724 // If source operand will be expanded to the same type as VT, i.e.
6725 // i64 <- f64, i32 <- f32, expand the source operand instead.
6726 MVT VT0 = Node->getOperand(0).getValueType();
6727 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6728 ExpandOp(Node->getOperand(0), Lo, Hi);
6732 // Turn this into a load/store pair by default.
6733 if (Tmp.getNode() == 0)
6734 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT, dl);
6736 ExpandOp(Tmp, Lo, Hi);
6740 case ISD::READCYCLECOUNTER: {
6741 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6742 TargetLowering::Custom &&
6743 "Must custom expand ReadCycleCounter");
6744 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6745 assert(Tmp.getNode() && "Node must be custom expanded!");
6746 ExpandOp(Tmp.getValue(0), Lo, Hi);
6747 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6748 LegalizeOp(Tmp.getValue(1)));
6752 case ISD::ATOMIC_CMP_SWAP: {
6753 // This operation does not need a loop.
6754 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6755 assert(Tmp.getNode() && "Node must be custom expanded!");
6756 ExpandOp(Tmp.getValue(0), Lo, Hi);
6757 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6758 LegalizeOp(Tmp.getValue(1)));
6762 case ISD::ATOMIC_LOAD_ADD:
6763 case ISD::ATOMIC_LOAD_SUB:
6764 case ISD::ATOMIC_LOAD_AND:
6765 case ISD::ATOMIC_LOAD_OR:
6766 case ISD::ATOMIC_LOAD_XOR:
6767 case ISD::ATOMIC_LOAD_NAND:
6768 case ISD::ATOMIC_SWAP: {
6769 // These operations require a loop to be generated. We can't do that yet,
6770 // so substitute a target-dependent pseudo and expand that later.
6771 SDValue In2Lo, In2Hi, In2;
6772 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6773 In2 = DAG.getNode(ISD::BUILD_PAIR, dl, VT, In2Lo, In2Hi);
6774 AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
6776 DAG.getAtomic(Op.getOpcode(), dl, Anode->getMemoryVT(),
6777 Op.getOperand(0), Op.getOperand(1), In2,
6778 Anode->getSrcValue(), Anode->getAlignment());
6779 SDValue Result = TLI.LowerOperation(Replace, DAG);
6780 ExpandOp(Result.getValue(0), Lo, Hi);
6781 // Remember that we legalized the chain.
6782 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Result.getValue(1)));
6786 // These operators cannot be expanded directly, emit them as calls to
6787 // library functions.
6788 case ISD::FP_TO_SINT: {
6789 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6791 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6792 case Expand: assert(0 && "cannot expand FP!");
6793 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6794 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6797 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op), DAG);
6799 // Now that the custom expander is done, expand the result, which is still
6802 ExpandOp(Op, Lo, Hi);
6807 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6809 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6810 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6814 case ISD::FP_TO_UINT: {
6815 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6817 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6818 case Expand: assert(0 && "cannot expand FP!");
6819 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6820 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6823 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, dl, VT, Op), DAG);
6825 // Now that the custom expander is done, expand the result.
6827 ExpandOp(Op, Lo, Hi);
6832 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6834 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6835 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6840 // If the target wants custom lowering, do so.
6841 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6842 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6843 SDValue Op = DAG.getNode(ISD::SHL, dl, VT, Node->getOperand(0), ShiftAmt);
6844 Op = TLI.LowerOperation(Op, DAG);
6846 // Now that the custom expander is done, expand the result, which is
6848 ExpandOp(Op, Lo, Hi);
6853 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6854 // this X << 1 as X+X.
6855 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6856 if (ShAmt->getAPIntValue() == 1 &&
6857 TLI.isOperationLegalOrCustom(ISD::ADDC, NVT) &&
6858 TLI.isOperationLegalOrCustom(ISD::ADDE, NVT)) {
6859 SDValue LoOps[2], HiOps[3];
6860 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6861 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6862 LoOps[1] = LoOps[0];
6863 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
6865 HiOps[1] = HiOps[0];
6866 HiOps[2] = Lo.getValue(1);
6867 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
6872 // If we can emit an efficient shift operation, do so now.
6873 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6876 // If this target supports SHL_PARTS, use it.
6877 TargetLowering::LegalizeAction Action =
6878 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6879 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6880 Action == TargetLowering::Custom) {
6881 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0),
6882 ShiftAmt, Lo, Hi, dl);
6886 // Otherwise, emit a libcall.
6887 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6892 // If the target wants custom lowering, do so.
6893 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6894 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6895 SDValue Op = DAG.getNode(ISD::SRA, dl, VT, Node->getOperand(0), ShiftAmt);
6896 Op = TLI.LowerOperation(Op, DAG);
6898 // Now that the custom expander is done, expand the result, which is
6900 ExpandOp(Op, Lo, Hi);
6905 // If we can emit an efficient shift operation, do so now.
6906 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6909 // If this target supports SRA_PARTS, use it.
6910 TargetLowering::LegalizeAction Action =
6911 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6912 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6913 Action == TargetLowering::Custom) {
6914 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0),
6915 ShiftAmt, Lo, Hi, dl);
6919 // Otherwise, emit a libcall.
6920 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6925 // If the target wants custom lowering, do so.
6926 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6927 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6928 SDValue Op = DAG.getNode(ISD::SRL, dl, VT, Node->getOperand(0), ShiftAmt);
6929 Op = TLI.LowerOperation(Op, DAG);
6931 // Now that the custom expander is done, expand the result, which is
6933 ExpandOp(Op, Lo, Hi);
6938 // If we can emit an efficient shift operation, do so now.
6939 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6942 // If this target supports SRL_PARTS, use it.
6943 TargetLowering::LegalizeAction Action =
6944 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6945 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6946 Action == TargetLowering::Custom) {
6947 ExpandShiftParts(ISD::SRL_PARTS,
6948 Node->getOperand(0), ShiftAmt, Lo, Hi, dl);
6952 // Otherwise, emit a libcall.
6953 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6959 // If the target wants to custom expand this, let them.
6960 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6961 TargetLowering::Custom) {
6962 SDValue Result = TLI.LowerOperation(Op, DAG);
6963 if (Result.getNode()) {
6964 ExpandOp(Result, Lo, Hi);
6968 // Expand the subcomponents.
6969 SDValue LHSL, LHSH, RHSL, RHSH;
6970 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6971 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6972 SDValue LoOps[2], HiOps[3];
6978 //cascaded check to see if any smaller size has a a carry flag.
6979 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
6980 bool hasCarry = false;
6981 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
6982 MVT AVT = MVT::getIntegerVT(BitSize);
6983 if (TLI.isOperationLegalOrCustom(OpV, AVT)) {
6990 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6991 if (Node->getOpcode() == ISD::ADD) {
6992 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
6993 HiOps[2] = Lo.getValue(1);
6994 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
6996 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
6997 HiOps[2] = Lo.getValue(1);
6998 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
7002 if (Node->getOpcode() == ISD::ADD) {
7003 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
7004 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
7005 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
7006 Lo, LoOps[0], ISD::SETULT);
7007 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
7008 DAG.getConstant(1, NVT),
7009 DAG.getConstant(0, NVT));
7010 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
7011 Lo, LoOps[1], ISD::SETULT);
7012 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
7013 DAG.getConstant(1, NVT),
7015 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
7017 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
7018 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
7019 SDValue Cmp = DAG.getSetCC(dl, NVT, LoOps[0], LoOps[1], ISD::SETULT);
7020 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
7021 DAG.getConstant(1, NVT),
7022 DAG.getConstant(0, NVT));
7023 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
7031 // Expand the subcomponents.
7032 SDValue LHSL, LHSH, RHSL, RHSH;
7033 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7034 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7035 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7036 SDValue LoOps[2] = { LHSL, RHSL };
7037 SDValue HiOps[3] = { LHSH, RHSH };
7039 if (Node->getOpcode() == ISD::ADDC) {
7040 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
7041 HiOps[2] = Lo.getValue(1);
7042 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
7044 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
7045 HiOps[2] = Lo.getValue(1);
7046 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
7048 // Remember that we legalized the flag.
7049 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7054 // Expand the subcomponents.
7055 SDValue LHSL, LHSH, RHSL, RHSH;
7056 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7057 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7058 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7059 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
7060 SDValue HiOps[3] = { LHSH, RHSH };
7062 Lo = DAG.getNode(Node->getOpcode(), dl, VTList, LoOps, 3);
7063 HiOps[2] = Lo.getValue(1);
7064 Hi = DAG.getNode(Node->getOpcode(), dl, VTList, HiOps, 3);
7066 // Remember that we legalized the flag.
7067 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7071 // If the target wants to custom expand this, let them.
7072 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
7073 SDValue New = TLI.LowerOperation(Op, DAG);
7074 if (New.getNode()) {
7075 ExpandOp(New, Lo, Hi);
7080 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
7081 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
7082 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
7083 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
7084 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
7085 SDValue LL, LH, RL, RH;
7086 ExpandOp(Node->getOperand(0), LL, LH);
7087 ExpandOp(Node->getOperand(1), RL, RH);
7088 unsigned OuterBitSize = Op.getValueSizeInBits();
7089 unsigned InnerBitSize = RH.getValueSizeInBits();
7090 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
7091 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
7092 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
7093 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
7094 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
7095 // The inputs are both zero-extended.
7097 // We can emit a umul_lohi.
7098 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
7099 Hi = SDValue(Lo.getNode(), 1);
7103 // We can emit a mulhu+mul.
7104 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7105 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
7109 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
7110 // The input values are both sign-extended.
7112 // We can emit a smul_lohi.
7113 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
7114 Hi = SDValue(Lo.getNode(), 1);
7118 // We can emit a mulhs+mul.
7119 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7120 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
7125 // Lo,Hi = umul LHS, RHS.
7126 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
7127 DAG.getVTList(NVT, NVT), LL, RL);
7129 Hi = UMulLOHI.getValue(1);
7130 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
7131 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
7132 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
7133 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
7137 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7138 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
7139 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
7140 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
7141 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
7142 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
7147 // If nothing else, we can make a libcall.
7148 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
7152 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
7155 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
7158 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
7161 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
7165 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
7168 RTLIB::ADD_PPCF128),
7172 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
7175 RTLIB::SUB_PPCF128),
7179 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
7182 RTLIB::MUL_PPCF128),
7186 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
7189 RTLIB::DIV_PPCF128),
7192 case ISD::FP_EXTEND: {
7193 if (VT == MVT::ppcf128) {
7194 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
7195 Node->getOperand(0).getValueType()==MVT::f64);
7196 const uint64_t zero = 0;
7197 if (Node->getOperand(0).getValueType()==MVT::f32)
7198 Hi = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Node->getOperand(0));
7200 Hi = Node->getOperand(0);
7201 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7204 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
7205 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
7206 Lo = ExpandLibCall(LC, Node, true, Hi);
7209 case ISD::FP_ROUND: {
7210 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
7212 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
7213 Lo = ExpandLibCall(LC, Node, true, Hi);
7228 case ISD::FNEARBYINT:
7231 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
7232 switch(Node->getOpcode()) {
7234 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
7235 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
7238 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
7239 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
7242 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
7243 RTLIB::COS_F80, RTLIB::COS_PPCF128);
7246 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
7247 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
7250 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
7251 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
7254 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
7255 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
7258 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
7259 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
7262 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
7263 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
7266 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
7267 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
7270 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
7271 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
7274 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
7275 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
7278 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
7279 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
7281 case ISD::FNEARBYINT:
7282 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
7283 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
7286 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
7287 RTLIB::POW_PPCF128);
7290 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
7291 RTLIB::POWI_PPCF128);
7293 default: assert(0 && "Unreachable!");
7295 Lo = ExpandLibCall(LC, Node, false, Hi);
7299 if (VT == MVT::ppcf128) {
7301 ExpandOp(Node->getOperand(0), Lo, Tmp);
7302 Hi = DAG.getNode(ISD::FABS, dl, NVT, Tmp);
7303 // lo = hi==fabs(hi) ? lo : -lo;
7304 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Hi, Tmp,
7305 Lo, DAG.getNode(ISD::FNEG, dl, NVT, Lo),
7306 DAG.getCondCode(ISD::SETEQ));
7309 SDValue Mask = (VT == MVT::f64)
7310 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
7311 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
7312 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask);
7313 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
7314 Lo = DAG.getNode(ISD::AND, dl, NVT, Lo, Mask);
7315 if (getTypeAction(NVT) == Expand)
7316 ExpandOp(Lo, Lo, Hi);
7320 if (VT == MVT::ppcf128) {
7321 ExpandOp(Node->getOperand(0), Lo, Hi);
7322 Lo = DAG.getNode(ISD::FNEG, dl, MVT::f64, Lo);
7323 Hi = DAG.getNode(ISD::FNEG, dl, MVT::f64, Hi);
7326 SDValue Mask = (VT == MVT::f64)
7327 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
7328 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
7329 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask);
7330 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
7331 Lo = DAG.getNode(ISD::XOR, dl, NVT, Lo, Mask);
7332 if (getTypeAction(NVT) == Expand)
7333 ExpandOp(Lo, Lo, Hi);
7336 case ISD::FCOPYSIGN: {
7337 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
7338 if (getTypeAction(NVT) == Expand)
7339 ExpandOp(Lo, Lo, Hi);
7342 case ISD::SINT_TO_FP:
7343 case ISD::UINT_TO_FP: {
7344 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
7345 MVT SrcVT = Node->getOperand(0).getValueType();
7347 // Promote the operand if needed. Do this before checking for
7348 // ppcf128 so conversions of i16 and i8 work.
7349 if (getTypeAction(SrcVT) == Promote) {
7350 SDValue Tmp = PromoteOp(Node->getOperand(0));
7352 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp.getValueType(), Tmp,
7353 DAG.getValueType(SrcVT))
7354 : DAG.getZeroExtendInReg(Tmp, dl, SrcVT);
7355 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
7356 SrcVT = Node->getOperand(0).getValueType();
7359 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
7360 static const uint64_t zero = 0;
7362 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
7363 Node->getOperand(0)));
7364 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7366 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
7367 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
7368 Node->getOperand(0)));
7369 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7370 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
7371 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
7372 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl,
7373 MVT::ppcf128, Node->getOperand(0),
7374 DAG.getConstant(0, MVT::i32),
7375 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
7377 (APFloat(APInt(128, 2, TwoE32)),
7380 DAG.getCondCode(ISD::SETLT)),
7385 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
7386 // si64->ppcf128 done by libcall, below
7387 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
7388 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::ppcf128,
7389 Node->getOperand(0)), Lo, Hi);
7390 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
7391 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
7392 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl, MVT::ppcf128,
7393 Node->getOperand(0),
7394 DAG.getConstant(0, MVT::i64),
7395 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
7397 (APFloat(APInt(128, 2, TwoE64)),
7400 DAG.getCondCode(ISD::SETLT)),
7405 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
7406 Node->getOperand(0), dl);
7407 if (getTypeAction(Lo.getValueType()) == Expand)
7408 // float to i32 etc. can be 'expanded' to a single node.
7409 ExpandOp(Lo, Lo, Hi);
7414 // Make sure the resultant values have been legalized themselves, unless this
7415 // is a type that requires multi-step expansion.
7416 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
7417 Lo = LegalizeOp(Lo);
7419 // Don't legalize the high part if it is expanded to a single node.
7420 Hi = LegalizeOp(Hi);
7423 // Remember in a map if the values will be reused later.
7425 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7426 assert(isNew && "Value already expanded?!?");
7430 /// SplitVectorOp - Given an operand of vector type, break it down into
7431 /// two smaller values, still of vector type.
7432 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
7434 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
7435 SDNode *Node = Op.getNode();
7436 DebugLoc dl = Node->getDebugLoc();
7437 unsigned NumElements = Op.getValueType().getVectorNumElements();
7438 assert(NumElements > 1 && "Cannot split a single element vector!");
7440 MVT NewEltVT = Op.getValueType().getVectorElementType();
7442 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
7443 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
7445 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
7446 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
7448 // See if we already split it.
7449 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
7450 = SplitNodes.find(Op);
7451 if (I != SplitNodes.end()) {
7452 Lo = I->second.first;
7453 Hi = I->second.second;
7457 switch (Node->getOpcode()) {
7462 assert(0 && "Unhandled operation in SplitVectorOp!");
7464 Lo = DAG.getUNDEF(NewVT_Lo);
7465 Hi = DAG.getUNDEF(NewVT_Hi);
7467 case ISD::BUILD_PAIR:
7468 Lo = Node->getOperand(0);
7469 Hi = Node->getOperand(1);
7471 case ISD::INSERT_VECTOR_ELT: {
7472 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
7473 SplitVectorOp(Node->getOperand(0), Lo, Hi);
7474 unsigned Index = Idx->getZExtValue();
7475 SDValue ScalarOp = Node->getOperand(1);
7476 if (Index < NewNumElts_Lo)
7477 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Lo, Lo, ScalarOp,
7478 DAG.getIntPtrConstant(Index));
7480 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Hi, Hi, ScalarOp,
7481 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
7484 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
7485 Node->getOperand(1),
7486 Node->getOperand(2), dl);
7487 SplitVectorOp(Tmp, Lo, Hi);
7490 case ISD::VECTOR_SHUFFLE: {
7491 // Build the low part.
7492 SDValue Mask = Node->getOperand(2);
7493 SmallVector<SDValue, 8> Ops;
7494 MVT PtrVT = TLI.getPointerTy();
7496 // Insert all of the elements from the input that are needed. We use
7497 // buildvector of extractelement here because the input vectors will have
7498 // to be legalized, so this makes the code simpler.
7499 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
7500 SDValue IdxNode = Mask.getOperand(i);
7501 if (IdxNode.getOpcode() == ISD::UNDEF) {
7502 Ops.push_back(DAG.getUNDEF(NewEltVT));
7505 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7506 SDValue InVec = Node->getOperand(0);
7507 if (Idx >= NumElements) {
7508 InVec = Node->getOperand(1);
7511 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
7512 DAG.getConstant(Idx, PtrVT)));
7514 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &Ops[0], Ops.size());
7517 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
7518 SDValue IdxNode = Mask.getOperand(i);
7519 if (IdxNode.getOpcode() == ISD::UNDEF) {
7520 Ops.push_back(DAG.getUNDEF(NewEltVT));
7523 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7524 SDValue InVec = Node->getOperand(0);
7525 if (Idx >= NumElements) {
7526 InVec = Node->getOperand(1);
7529 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
7530 DAG.getConstant(Idx, PtrVT)));
7532 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &Ops[0], Ops.size());
7535 case ISD::BUILD_VECTOR: {
7536 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7537 Node->op_begin()+NewNumElts_Lo);
7538 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &LoOps[0], LoOps.size());
7540 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
7542 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &HiOps[0], HiOps.size());
7545 case ISD::CONCAT_VECTORS: {
7546 // FIXME: Handle non-power-of-two vectors?
7547 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
7548 if (NewNumSubvectors == 1) {
7549 Lo = Node->getOperand(0);
7550 Hi = Node->getOperand(1);
7552 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7553 Node->op_begin()+NewNumSubvectors);
7554 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Lo,
7555 &LoOps[0], LoOps.size());
7557 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
7559 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Hi,
7560 &HiOps[0], HiOps.size());
7564 case ISD::EXTRACT_SUBVECTOR: {
7565 SDValue Vec = Op.getOperand(0);
7566 SDValue Idx = Op.getOperand(1);
7567 MVT IdxVT = Idx.getValueType();
7569 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Lo, Vec, Idx);
7570 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
7572 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec,
7573 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo,
7576 Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx,
7577 DAG.getConstant(NewNumElts_Lo, IdxVT));
7578 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec, Idx);
7583 SDValue Cond = Node->getOperand(0);
7585 SDValue LL, LH, RL, RH;
7586 SplitVectorOp(Node->getOperand(1), LL, LH);
7587 SplitVectorOp(Node->getOperand(2), RL, RH);
7589 if (Cond.getValueType().isVector()) {
7590 // Handle a vector merge.
7592 SplitVectorOp(Cond, CL, CH);
7593 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, CL, LL, RL);
7594 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, CH, LH, RH);
7596 // Handle a simple select with vector operands.
7597 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, Cond, LL, RL);
7598 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, Cond, LH, RH);
7602 case ISD::SELECT_CC: {
7603 SDValue CondLHS = Node->getOperand(0);
7604 SDValue CondRHS = Node->getOperand(1);
7605 SDValue CondCode = Node->getOperand(4);
7607 SDValue LL, LH, RL, RH;
7608 SplitVectorOp(Node->getOperand(2), LL, LH);
7609 SplitVectorOp(Node->getOperand(3), RL, RH);
7611 // Handle a simple select with vector operands.
7612 Lo = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Lo, CondLHS, CondRHS,
7614 Hi = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Hi, CondLHS, CondRHS,
7619 SDValue LL, LH, RL, RH;
7620 SplitVectorOp(Node->getOperand(0), LL, LH);
7621 SplitVectorOp(Node->getOperand(1), RL, RH);
7622 Lo = DAG.getNode(ISD::VSETCC, dl, NewVT_Lo, LL, RL, Node->getOperand(2));
7623 Hi = DAG.getNode(ISD::VSETCC, dl, NewVT_Hi, LH, RH, Node->getOperand(2));
7645 SDValue LL, LH, RL, RH;
7646 SplitVectorOp(Node->getOperand(0), LL, LH);
7647 SplitVectorOp(Node->getOperand(1), RL, RH);
7649 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, LL, RL);
7650 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, LH, RH);
7656 SplitVectorOp(Node->getOperand(0), L, H);
7658 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L, Node->getOperand(1));
7659 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H, Node->getOperand(1));
7675 case ISD::FP_TO_SINT:
7676 case ISD::FP_TO_UINT:
7677 case ISD::SINT_TO_FP:
7678 case ISD::UINT_TO_FP:
7680 case ISD::ANY_EXTEND:
7681 case ISD::SIGN_EXTEND:
7682 case ISD::ZERO_EXTEND:
7683 case ISD::FP_EXTEND: {
7685 SplitVectorOp(Node->getOperand(0), L, H);
7687 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L);
7688 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H);
7691 case ISD::CONVERT_RNDSAT: {
7692 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
7694 SplitVectorOp(Node->getOperand(0), L, H);
7695 SDValue DTyOpL = DAG.getValueType(NewVT_Lo);
7696 SDValue DTyOpH = DAG.getValueType(NewVT_Hi);
7697 SDValue STyOpL = DAG.getValueType(L.getValueType());
7698 SDValue STyOpH = DAG.getValueType(H.getValueType());
7700 SDValue RndOp = Node->getOperand(3);
7701 SDValue SatOp = Node->getOperand(4);
7703 Lo = DAG.getConvertRndSat(NewVT_Lo, dl, L, DTyOpL, STyOpL,
7704 RndOp, SatOp, CvtCode);
7705 Hi = DAG.getConvertRndSat(NewVT_Hi, dl, H, DTyOpH, STyOpH,
7706 RndOp, SatOp, CvtCode);
7710 LoadSDNode *LD = cast<LoadSDNode>(Node);
7711 SDValue Ch = LD->getChain();
7712 SDValue Ptr = LD->getBasePtr();
7713 ISD::LoadExtType ExtType = LD->getExtensionType();
7714 const Value *SV = LD->getSrcValue();
7715 int SVOffset = LD->getSrcValueOffset();
7716 MVT MemoryVT = LD->getMemoryVT();
7717 unsigned Alignment = LD->getAlignment();
7718 bool isVolatile = LD->isVolatile();
7720 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7721 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
7723 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7724 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7725 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7727 Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7728 NewVT_Lo, Ch, Ptr, Offset,
7729 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7730 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7731 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
7732 DAG.getIntPtrConstant(IncrementSize));
7733 SVOffset += IncrementSize;
7734 Alignment = MinAlign(Alignment, IncrementSize);
7735 Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7736 NewVT_Hi, Ch, Ptr, Offset,
7737 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7739 // Build a factor node to remember that this load is independent of the
7741 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
7744 // Remember that we legalized the chain.
7745 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7748 case ISD::BIT_CONVERT: {
7749 // We know the result is a vector. The input may be either a vector or a
7751 SDValue InOp = Node->getOperand(0);
7752 if (!InOp.getValueType().isVector() ||
7753 InOp.getValueType().getVectorNumElements() == 1) {
7754 // The input is a scalar or single-element vector.
7755 // Lower to a store/load so that it can be split.
7756 // FIXME: this could be improved probably.
7757 unsigned LdAlign = TLI.getTargetData()->
7758 getPrefTypeAlignment(Op.getValueType().getTypeForMVT());
7759 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7760 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7762 SDValue St = DAG.getStore(DAG.getEntryNode(), dl,
7764 PseudoSourceValue::getFixedStack(FI), 0);
7765 InOp = DAG.getLoad(Op.getValueType(), dl, St, Ptr,
7766 PseudoSourceValue::getFixedStack(FI), 0);
7768 // Split the vector and convert each of the pieces now.
7769 SplitVectorOp(InOp, Lo, Hi);
7770 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Lo, Lo);
7771 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Hi, Hi);
7776 // Remember in a map if the values will be reused later.
7778 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7779 assert(isNew && "Value already split?!?");
7784 /// ScalarizeVectorOp - Given an operand of single-element vector type
7785 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7786 /// scalar (e.g. f32) value.
7787 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7788 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7789 SDNode *Node = Op.getNode();
7790 DebugLoc dl = Node->getDebugLoc();
7791 MVT NewVT = Op.getValueType().getVectorElementType();
7792 assert(Op.getValueType().getVectorNumElements() == 1);
7794 // See if we already scalarized it.
7795 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7796 if (I != ScalarizedNodes.end()) return I->second;
7799 switch (Node->getOpcode()) {
7802 Node->dump(&DAG); cerr << "\n";
7804 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7821 Result = DAG.getNode(Node->getOpcode(), dl,
7823 ScalarizeVectorOp(Node->getOperand(0)),
7824 ScalarizeVectorOp(Node->getOperand(1)));
7836 case ISD::FP_TO_SINT:
7837 case ISD::FP_TO_UINT:
7838 case ISD::SINT_TO_FP:
7839 case ISD::UINT_TO_FP:
7840 case ISD::SIGN_EXTEND:
7841 case ISD::ZERO_EXTEND:
7842 case ISD::ANY_EXTEND:
7844 case ISD::FP_EXTEND:
7845 Result = DAG.getNode(Node->getOpcode(), dl,
7847 ScalarizeVectorOp(Node->getOperand(0)));
7849 case ISD::CONVERT_RNDSAT: {
7850 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
7851 Result = DAG.getConvertRndSat(NewVT, dl, Op0,
7852 DAG.getValueType(NewVT),
7853 DAG.getValueType(Op0.getValueType()),
7854 Node->getOperand(3),
7855 Node->getOperand(4),
7856 cast<CvtRndSatSDNode>(Node)->getCvtCode());
7861 Result = DAG.getNode(Node->getOpcode(), dl,
7863 ScalarizeVectorOp(Node->getOperand(0)),
7864 Node->getOperand(1));
7867 LoadSDNode *LD = cast<LoadSDNode>(Node);
7868 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7869 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7870 ISD::LoadExtType ExtType = LD->getExtensionType();
7871 const Value *SV = LD->getSrcValue();
7872 int SVOffset = LD->getSrcValueOffset();
7873 MVT MemoryVT = LD->getMemoryVT();
7874 unsigned Alignment = LD->getAlignment();
7875 bool isVolatile = LD->isVolatile();
7877 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7878 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
7880 Result = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7881 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7882 MemoryVT.getVectorElementType(),
7883 isVolatile, Alignment);
7885 // Remember that we legalized the chain.
7886 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7889 case ISD::BUILD_VECTOR:
7890 Result = Node->getOperand(0);
7892 case ISD::INSERT_VECTOR_ELT:
7893 // Returning the inserted scalar element.
7894 Result = Node->getOperand(1);
7896 case ISD::CONCAT_VECTORS:
7897 assert(Node->getOperand(0).getValueType() == NewVT &&
7898 "Concat of non-legal vectors not yet supported!");
7899 Result = Node->getOperand(0);
7901 case ISD::VECTOR_SHUFFLE: {
7902 // Figure out if the scalar is the LHS or RHS and return it.
7903 SDValue EltNum = Node->getOperand(2).getOperand(0);
7904 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7905 Result = ScalarizeVectorOp(Node->getOperand(1));
7907 Result = ScalarizeVectorOp(Node->getOperand(0));
7910 case ISD::EXTRACT_SUBVECTOR:
7911 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT,
7912 Node->getOperand(0), Node->getOperand(1));
7914 case ISD::BIT_CONVERT: {
7915 SDValue Op0 = Op.getOperand(0);
7916 if (Op0.getValueType().getVectorNumElements() == 1)
7917 Op0 = ScalarizeVectorOp(Op0);
7918 Result = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, Op0);
7922 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Op.getOperand(0),
7923 ScalarizeVectorOp(Op.getOperand(1)),
7924 ScalarizeVectorOp(Op.getOperand(2)));
7926 case ISD::SELECT_CC:
7927 Result = DAG.getNode(ISD::SELECT_CC, dl, NewVT, Node->getOperand(0),
7928 Node->getOperand(1),
7929 ScalarizeVectorOp(Op.getOperand(2)),
7930 ScalarizeVectorOp(Op.getOperand(3)),
7931 Node->getOperand(4));
7934 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7935 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7936 Result = DAG.getNode(ISD::SETCC, dl,
7937 TLI.getSetCCResultType(Op0.getValueType()),
7938 Op0, Op1, Op.getOperand(2));
7939 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Result,
7940 DAG.getConstant(-1ULL, NewVT),
7941 DAG.getConstant(0ULL, NewVT));
7946 if (TLI.isTypeLegal(NewVT))
7947 Result = LegalizeOp(Result);
7948 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7949 assert(isNew && "Value already scalarized?");
7955 SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
7956 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op);
7957 if (I != WidenNodes.end()) return I->second;
7959 MVT VT = Op.getValueType();
7960 assert(VT.isVector() && "Cannot widen non-vector type!");
7963 SDNode *Node = Op.getNode();
7964 DebugLoc dl = Node->getDebugLoc();
7965 MVT EVT = VT.getVectorElementType();
7967 unsigned NumElts = VT.getVectorNumElements();
7968 unsigned NewNumElts = WidenVT.getVectorNumElements();
7969 assert(NewNumElts > NumElts && "Cannot widen to smaller type!");
7970 assert(NewNumElts < 17);
7972 // When widen is called, it is assumed that it is more efficient to use a
7973 // wide type. The default action is to widen to operation to a wider legal
7974 // vector type and then do the operation if it is legal by calling LegalizeOp
7975 // again. If there is no vector equivalent, we will unroll the operation, do
7976 // it, and rebuild the vector. If most of the operations are vectorizible to
7977 // the legal type, the resulting code will be more efficient. If this is not
7978 // the case, the resulting code will preform badly as we end up generating
7979 // code to pack/unpack the results. It is the function that calls widen
7980 // that is responsible for seeing this doesn't happen.
7981 switch (Node->getOpcode()) {
7986 assert(0 && "Unexpected operation in WidenVectorOp!");
7988 case ISD::CopyFromReg:
7989 assert(0 && "CopyFromReg doesn't need widening!");
7991 case ISD::ConstantFP:
7992 // To build a vector of these elements, clients should call BuildVector
7993 // and with each element instead of creating a node with a vector type
7994 assert(0 && "Unexpected operation in WidenVectorOp!");
7996 // Variable Arguments with vector types doesn't make any sense to me
7997 assert(0 && "Unexpected operation in WidenVectorOp!");
8000 Result = DAG.getUNDEF(WidenVT);
8002 case ISD::BUILD_VECTOR: {
8003 // Build a vector with undefined for the new nodes
8004 SDValueVector NewOps(Node->op_begin(), Node->op_end());
8005 for (unsigned i = NumElts; i < NewNumElts; ++i) {
8006 NewOps.push_back(DAG.getUNDEF(EVT));
8008 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT,
8009 &NewOps[0], NewOps.size());
8012 case ISD::INSERT_VECTOR_ELT: {
8013 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8014 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WidenVT, Tmp1,
8015 Node->getOperand(1), Node->getOperand(2));
8018 case ISD::VECTOR_SHUFFLE: {
8019 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8020 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8021 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Node);
8022 SmallVector<int, 8> NewMask;
8023 for (unsigned i = 0; i < NumElts; ++i) {
8024 int Idx = SVOp->getMaskElt(i);
8025 if (Idx < (int)NumElts)
8026 NewMask.push_back(Idx);
8028 NewMask.push_back(Idx + NewNumElts - NumElts);
8030 for (unsigned i = NumElts; i < NewNumElts; ++i)
8031 NewMask.push_back(-1);
8033 Result = DAG.getVectorShuffle(WidenVT, dl, Tmp1, Tmp2, &NewMask[0]);
8037 // If the load widen returns true, we can use a single load for the
8038 // vector. Otherwise, it is returning a token factor for multiple
8041 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT))
8042 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1)));
8044 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0)));
8048 case ISD::BIT_CONVERT: {
8049 SDValue Tmp1 = Node->getOperand(0);
8050 // Converts between two different types so we need to determine
8051 // the correct widen type for the input operand.
8052 MVT InVT = Tmp1.getValueType();
8053 unsigned WidenSize = WidenVT.getSizeInBits();
8054 if (InVT.isVector()) {
8055 MVT InEltVT = InVT.getVectorElementType();
8056 unsigned InEltSize = InEltVT.getSizeInBits();
8057 assert(WidenSize % InEltSize == 0 &&
8058 "can not widen bit convert that are not multiple of element type");
8059 MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize);
8060 Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT);
8061 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
8062 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Tmp1);
8064 // If the result size is a multiple of the input size, widen the input
8065 // and then convert.
8066 unsigned InSize = InVT.getSizeInBits();
8067 assert(WidenSize % InSize == 0 &&
8068 "can not widen bit convert that are not multiple of element type");
8069 unsigned NewNumElts = WidenSize / InSize;
8070 SmallVector<SDValue, 16> Ops(NewNumElts);
8071 SDValue UndefVal = DAG.getUNDEF(InVT);
8073 for (unsigned i = 1; i < NewNumElts; ++i)
8076 MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts);
8077 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, &Ops[0], NewNumElts);
8078 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Result);
8083 case ISD::SINT_TO_FP:
8084 case ISD::UINT_TO_FP:
8085 case ISD::FP_TO_SINT:
8086 case ISD::FP_TO_UINT:
8087 case ISD::FP_ROUND: {
8088 SDValue Tmp1 = Node->getOperand(0);
8089 // Converts between two different types so we need to determine
8090 // the correct widen type for the input operand.
8091 MVT TVT = Tmp1.getValueType();
8092 assert(TVT.isVector() && "can not widen non vector type");
8093 MVT TEVT = TVT.getVectorElementType();
8094 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts);
8095 Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
8096 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts);
8097 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
8101 case ISD::FP_EXTEND:
8102 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
8104 case ISD::SIGN_EXTEND:
8105 case ISD::ZERO_EXTEND:
8106 case ISD::ANY_EXTEND:
8107 case ISD::SIGN_EXTEND_INREG:
8116 // Unary op widening
8118 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8119 assert(Tmp1.getValueType() == WidenVT);
8120 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
8123 case ISD::CONVERT_RNDSAT: {
8124 SDValue RndOp = Node->getOperand(3);
8125 SDValue SatOp = Node->getOperand(4);
8126 SDValue SrcOp = Node->getOperand(0);
8128 // Converts between two different types so we need to determine
8129 // the correct widen type for the input operand.
8130 MVT SVT = SrcOp.getValueType();
8131 assert(SVT.isVector() && "can not widen non vector type");
8132 MVT SEVT = SVT.getVectorElementType();
8133 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts);
8135 SrcOp = WidenVectorOp(SrcOp, SWidenVT);
8136 assert(SrcOp.getValueType() == WidenVT);
8137 SDValue DTyOp = DAG.getValueType(WidenVT);
8138 SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
8139 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
8141 Result = DAG.getConvertRndSat(WidenVT, dl, SrcOp, DTyOp, STyOp,
8142 RndOp, SatOp, CvtCode);
8162 case ISD::FCOPYSIGN:
8166 // Binary op widening
8167 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8168 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8169 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8170 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2);
8177 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8178 assert(Tmp1.getValueType() == WidenVT);
8179 SDValue ShOp = Node->getOperand(1);
8180 MVT ShVT = ShOp.getValueType();
8181 MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(),
8182 WidenVT.getVectorNumElements());
8183 ShOp = WidenVectorOp(ShOp, NewShVT);
8184 assert(ShOp.getValueType() == NewShVT);
8185 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, ShOp);
8189 case ISD::EXTRACT_VECTOR_ELT: {
8190 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8191 assert(Tmp1.getValueType() == WidenVT);
8192 Result = DAG.getNode(Node->getOpcode(), dl, EVT, Tmp1, Node->getOperand(1));
8195 case ISD::CONCAT_VECTORS: {
8196 // We concurrently support only widen on a multiple of the incoming vector.
8197 // We could widen on a multiple of the incoming operand if necessary.
8198 unsigned NumConcat = NewNumElts / NumElts;
8199 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
8200 SDValue UndefVal = DAG.getUNDEF(VT);
8201 SmallVector<SDValue, 8> MOps;
8203 for (unsigned i = 1; i != NumConcat; ++i) {
8204 MOps.push_back(UndefVal);
8206 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
8207 &MOps[0], MOps.size()));
8210 case ISD::EXTRACT_SUBVECTOR: {
8211 SDValue Tmp1 = Node->getOperand(0);
8212 SDValue Idx = Node->getOperand(1);
8213 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
8214 if (CIdx && CIdx->getZExtValue() == 0) {
8215 // Since we are access the start of the vector, the incoming
8216 // vector type might be the proper.
8217 MVT Tmp1VT = Tmp1.getValueType();
8218 if (Tmp1VT == WidenVT)
8221 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements();
8222 if (Tmp1VTNumElts < NewNumElts)
8223 Result = WidenVectorOp(Tmp1, WidenVT);
8225 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, Tmp1, Idx);
8227 } else if (NewNumElts % NumElts == 0) {
8228 // Widen the extracted subvector.
8229 unsigned NumConcat = NewNumElts / NumElts;
8230 SDValue UndefVal = DAG.getUNDEF(VT);
8231 SmallVector<SDValue, 8> MOps;
8233 for (unsigned i = 1; i != NumConcat; ++i) {
8234 MOps.push_back(UndefVal);
8236 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
8237 &MOps[0], MOps.size()));
8239 assert(0 && "can not widen extract subvector");
8240 // This could be implemented using insert and build vector but I would
8241 // like to see when this happens.
8247 // Determine new condition widen type and widen
8248 SDValue Cond1 = Node->getOperand(0);
8249 MVT CondVT = Cond1.getValueType();
8250 assert(CondVT.isVector() && "can not widen non vector type");
8251 MVT CondEVT = CondVT.getVectorElementType();
8252 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8253 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8254 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen");
8256 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT);
8257 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT);
8258 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8259 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Tmp1, Tmp2);
8263 case ISD::SELECT_CC: {
8264 // Determine new condition widen type and widen
8265 SDValue Cond1 = Node->getOperand(0);
8266 SDValue Cond2 = Node->getOperand(1);
8267 MVT CondVT = Cond1.getValueType();
8268 assert(CondVT.isVector() && "can not widen non vector type");
8269 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs");
8270 MVT CondEVT = CondVT.getVectorElementType();
8271 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8272 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8273 Cond2 = WidenVectorOp(Cond2, CondWidenVT);
8274 assert(Cond1.getValueType() == CondWidenVT &&
8275 Cond2.getValueType() == CondWidenVT && "condition not widen");
8277 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT);
8278 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT);
8279 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT &&
8280 "operands not widen");
8281 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Cond2, Tmp1,
8282 Tmp2, Node->getOperand(4));
8286 // Determine widen for the operand
8287 SDValue Tmp1 = Node->getOperand(0);
8288 MVT TmpVT = Tmp1.getValueType();
8289 assert(TmpVT.isVector() && "can not widen non vector type");
8290 MVT TmpEVT = TmpVT.getVectorElementType();
8291 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts);
8292 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT);
8293 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT);
8294 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2,
8295 Node->getOperand(2));
8298 case ISD::ATOMIC_CMP_SWAP:
8299 case ISD::ATOMIC_LOAD_ADD:
8300 case ISD::ATOMIC_LOAD_SUB:
8301 case ISD::ATOMIC_LOAD_AND:
8302 case ISD::ATOMIC_LOAD_OR:
8303 case ISD::ATOMIC_LOAD_XOR:
8304 case ISD::ATOMIC_LOAD_NAND:
8305 case ISD::ATOMIC_LOAD_MIN:
8306 case ISD::ATOMIC_LOAD_MAX:
8307 case ISD::ATOMIC_LOAD_UMIN:
8308 case ISD::ATOMIC_LOAD_UMAX:
8309 case ISD::ATOMIC_SWAP: {
8310 // For now, we assume that using vectors for these operations don't make
8311 // much sense so we just split it. We return an empty result
8313 SplitVectorOp(Op, X, Y);
8318 } // end switch (Node->getOpcode())
8320 assert(Result.getNode() && "Didn't set a result!");
8322 Result = LegalizeOp(Result);
8324 AddWidenedOperand(Op, Result);
8328 // Utility function to find a legal vector type and its associated element
8329 // type from a preferred width and whose vector type must be the same size
8331 // TLI: Target lowering used to determine legal types
8332 // Width: Preferred width of element type
8333 // VVT: Vector value type whose size we must match.
8334 // Returns VecEVT and EVT - the vector type and its associated element type
8335 static void FindWidenVecType(const TargetLowering &TLI, unsigned Width, MVT VVT,
8336 MVT& EVT, MVT& VecEVT) {
8337 // We start with the preferred width, make it a power of 2 and see if
8338 // we can find a vector type of that width. If not, we reduce it by
8339 // another power of 2. If we have widen the type, a vector of bytes should
8341 assert(TLI.isTypeLegal(VVT));
8342 unsigned EWidth = Width + 1;
8345 EWidth = (1 << Log2_32(EWidth-1));
8346 EVT = MVT::getIntegerVT(EWidth);
8347 unsigned NumEVT = VVT.getSizeInBits()/EWidth;
8348 VecEVT = MVT::getVectorVT(EVT, NumEVT);
8349 } while (!TLI.isTypeLegal(VecEVT) ||
8350 VVT.getSizeInBits() != VecEVT.getSizeInBits());
8353 SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
8363 // We assume that we have good rules to handle loading power of two loads so
8364 // we break down the operations to power of 2 loads. The strategy is to
8365 // load the largest power of 2 that we can easily transform to a legal vector
8366 // and then insert into that vector, and the cast the result into the legal
8367 // vector that we want. This avoids unnecessary stack converts.
8368 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
8369 // the load is nonvolatile, we an use a wider load for the value.
8370 // Find a vector length we can load a large chunk
8373 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8374 EVTWidth = EVT.getSizeInBits();
8376 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV, SVOffset,
8377 isVolatile, Alignment);
8378 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecEVT, LdOp);
8379 LdChain.push_back(LdOp.getValue(1));
8381 // Check if we can load the element with one instruction
8382 if (LdWidth == EVTWidth) {
8383 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
8386 // The vector element order is endianness dependent.
8388 LdWidth -= EVTWidth;
8389 unsigned Offset = 0;
8391 while (LdWidth > 0) {
8392 unsigned Increment = EVTWidth / 8;
8393 Offset += Increment;
8394 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8395 DAG.getIntPtrConstant(Increment));
8397 if (LdWidth < EVTWidth) {
8398 // Our current type we are using is too large, use a smaller size by
8399 // using a smaller power of 2
8400 unsigned oEVTWidth = EVTWidth;
8401 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8402 EVTWidth = EVT.getSizeInBits();
8403 // Readjust position and vector position based on new load type
8404 Idx = Idx * (oEVTWidth/EVTWidth);
8405 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
8408 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV,
8409 SVOffset+Offset, isVolatile,
8410 MinAlign(Alignment, Offset));
8411 LdChain.push_back(LdOp.getValue(1));
8412 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecEVT, VecOp, LdOp,
8413 DAG.getIntPtrConstant(Idx++));
8415 LdWidth -= EVTWidth;
8418 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
8421 bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
8425 // TODO: Add support for ConcatVec and the ability to load many vector
8426 // types (e.g., v4i8). This will not work when a vector register
8427 // to memory mapping is strange (e.g., vector elements are not
8428 // stored in some sequential order).
8430 // It must be true that the widen vector type is bigger than where
8431 // we need to load from.
8432 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
8433 MVT LdVT = LD->getMemoryVT();
8434 DebugLoc dl = LD->getDebugLoc();
8435 assert(LdVT.isVector() && NVT.isVector());
8436 assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
8439 SDValue Chain = LD->getChain();
8440 SDValue BasePtr = LD->getBasePtr();
8441 int SVOffset = LD->getSrcValueOffset();
8442 unsigned Alignment = LD->getAlignment();
8443 bool isVolatile = LD->isVolatile();
8444 const Value *SV = LD->getSrcValue();
8445 unsigned int LdWidth = LdVT.getSizeInBits();
8447 // Load value as a large register
8448 SDValueVector LdChain;
8449 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
8450 Alignment, isVolatile, LdWidth, NVT, dl);
8452 if (LdChain.size() == 1) {
8457 TFOp=DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8458 &LdChain[0], LdChain.size());
8464 void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
8474 // Breaks the stores into a series of power of 2 width stores. For any
8475 // width, we convert the vector to the vector of element size that we
8476 // want to store. This avoids requiring a stack convert.
8478 // Find a width of the element type we can store with
8479 MVT VVT = ValOp.getValueType();
8482 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8483 EVTWidth = EVT.getSizeInBits();
8485 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, ValOp);
8486 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
8487 DAG.getIntPtrConstant(0));
8488 SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset,
8489 isVolatile, Alignment);
8490 StChain.push_back(StOp);
8492 // Check if we are done
8493 if (StWidth == EVTWidth) {
8498 StWidth -= EVTWidth;
8499 unsigned Offset = 0;
8501 while (StWidth > 0) {
8502 unsigned Increment = EVTWidth / 8;
8503 Offset += Increment;
8504 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8505 DAG.getIntPtrConstant(Increment));
8507 if (StWidth < EVTWidth) {
8508 // Our current type we are using is too large, use a smaller size by
8509 // using a smaller power of 2
8510 unsigned oEVTWidth = EVTWidth;
8511 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8512 EVTWidth = EVT.getSizeInBits();
8513 // Readjust position and vector position based on new load type
8514 Idx = Idx * (oEVTWidth/EVTWidth);
8515 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
8518 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
8519 DAG.getIntPtrConstant(Idx++));
8520 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
8521 SVOffset + Offset, isVolatile,
8522 MinAlign(Alignment, Offset)));
8523 StWidth -= EVTWidth;
8528 SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
8531 // TODO: It might be cleaner if we can use SplitVector and have more legal
8532 // vector types that can be stored into memory (e.g., v4xi8 can
8533 // be stored as a word). This will not work when a vector register
8534 // to memory mapping is strange (e.g., vector elements are not
8535 // stored in some sequential order).
8537 MVT StVT = ST->getMemoryVT();
8538 SDValue ValOp = ST->getValue();
8539 DebugLoc dl = ST->getDebugLoc();
8541 // Check if we have widen this node with another value
8542 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
8543 if (I != WidenNodes.end())
8546 MVT VVT = ValOp.getValueType();
8548 // It must be true that we the widen vector type is bigger than where
8549 // we need to store.
8550 assert(StVT.isVector() && VVT.isVector());
8551 assert(StVT.bitsLT(VVT));
8552 assert(StVT.getVectorElementType() == VVT.getVectorElementType());
8555 SDValueVector StChain;
8556 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(),
8557 ST->getSrcValueOffset(), ST->getAlignment(),
8558 ST->isVolatile(), ValOp, StVT.getSizeInBits(), dl);
8559 if (StChain.size() == 1)
8562 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8563 &StChain[0], StChain.size());
8567 // SelectionDAG::Legalize - This is the entry point for the file.
8569 void SelectionDAG::Legalize(bool TypesNeedLegalizing, bool Fast) {
8570 /// run - This is the main entry point to this class.
8572 SelectionDAGLegalize(*this, TypesNeedLegalizing, Fast).LegalizeDAG();