1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/Constants.h"
27 #include "llvm/DerivedTypes.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/SmallPtrSet.h"
39 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
40 cl::desc("Pop up a window to show dags before legalize"));
42 static const bool ViewLegalizeDAGs = 0;
45 //===----------------------------------------------------------------------===//
46 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
47 /// hacks on it until the target machine can handle it. This involves
48 /// eliminating value sizes the machine cannot handle (promoting small sizes to
49 /// large sizes or splitting up large values into small values) as well as
50 /// eliminating operations the machine cannot handle.
52 /// This code also does a small amount of optimization and recognition of idioms
53 /// as part of its processing. For example, if a target does not support a
54 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
55 /// will attempt merge setcc and brc instructions into brcc's.
58 class VISIBILITY_HIDDEN SelectionDAGLegalize {
62 // Libcall insertion helpers.
64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
65 /// legalized. We use this to ensure that calls are properly serialized
66 /// against each other, including inserted libcalls.
67 SDOperand LastCALLSEQ_END;
69 /// IsLegalizingCall - This member is used *only* for purposes of providing
70 /// helpful assertions that a libcall isn't created while another call is
71 /// being legalized (which could lead to non-serialized call sequences).
72 bool IsLegalizingCall;
75 Legal, // The target natively supports this operation.
76 Promote, // This operation should be executed in a larger type.
77 Expand // Try to expand this to other ops, otherwise use a libcall.
80 /// ValueTypeActions - This is a bitvector that contains two bits for each
81 /// value type, where the two bits correspond to the LegalizeAction enum.
82 /// This can be queried with "getTypeAction(VT)".
83 TargetLowering::ValueTypeActionImpl ValueTypeActions;
85 /// LegalizedNodes - For nodes that are of legal width, and that have more
86 /// than one use, this map indicates what regularized operand to use. This
87 /// allows us to avoid legalizing the same thing more than once.
88 DenseMap<SDOperand, SDOperand> LegalizedNodes;
90 /// PromotedNodes - For nodes that are below legal width, and that have more
91 /// than one use, this map indicates what promoted value to use. This allows
92 /// us to avoid promoting the same thing more than once.
93 DenseMap<SDOperand, SDOperand> PromotedNodes;
95 /// ExpandedNodes - For nodes that need to be expanded this map indicates
96 /// which which operands are the expanded version of the input. This allows
97 /// us to avoid expanding the same node more than once.
98 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
100 /// SplitNodes - For vector nodes that need to be split, this map indicates
101 /// which which operands are the split version of the input. This allows us
102 /// to avoid splitting the same node more than once.
103 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
105 /// ScalarizedNodes - For nodes that need to be converted from vector types to
106 /// scalar types, this contains the mapping of ones we have already
107 /// processed to the result.
108 std::map<SDOperand, SDOperand> ScalarizedNodes;
110 void AddLegalizedOperand(SDOperand From, SDOperand To) {
111 LegalizedNodes.insert(std::make_pair(From, To));
112 // If someone requests legalization of the new node, return itself.
114 LegalizedNodes.insert(std::make_pair(To, To));
116 void AddPromotedOperand(SDOperand From, SDOperand To) {
117 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
118 assert(isNew && "Got into the map somehow?");
119 // If someone requests legalization of the new node, return itself.
120 LegalizedNodes.insert(std::make_pair(To, To));
125 SelectionDAGLegalize(SelectionDAG &DAG);
127 /// getTypeAction - Return how we should legalize values of this type, either
128 /// it is already legal or we need to expand it into multiple registers of
129 /// smaller integer type, or we need to promote it to a larger type.
130 LegalizeAction getTypeAction(MVT::ValueType VT) const {
131 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
134 /// isTypeLegal - Return true if this type is legal on this target.
136 bool isTypeLegal(MVT::ValueType VT) const {
137 return getTypeAction(VT) == Legal;
143 /// HandleOp - Legalize, Promote, or Expand the specified operand as
144 /// appropriate for its type.
145 void HandleOp(SDOperand Op);
147 /// LegalizeOp - We know that the specified value has a legal type.
148 /// Recursively ensure that the operands have legal types, then return the
150 SDOperand LegalizeOp(SDOperand O);
152 /// UnrollVectorOp - We know that the given vector has a legal type, however
153 /// the operation it performs is not legal and is an operation that we have
154 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
155 /// operating on each element individually.
156 SDOperand UnrollVectorOp(SDOperand O);
158 /// PromoteOp - Given an operation that produces a value in an invalid type,
159 /// promote it to compute the value into a larger type. The produced value
160 /// will have the correct bits for the low portion of the register, but no
161 /// guarantee is made about the top bits: it may be zero, sign-extended, or
163 SDOperand PromoteOp(SDOperand O);
165 /// ExpandOp - Expand the specified SDOperand into its two component pieces
166 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
167 /// the LegalizeNodes map is filled in for any results that are not expanded,
168 /// the ExpandedNodes map is filled in for any results that are expanded, and
169 /// the Lo/Hi values are returned. This applies to integer types and Vector
171 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
173 /// SplitVectorOp - Given an operand of vector type, break it down into
174 /// two smaller values.
175 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
177 /// ScalarizeVectorOp - Given an operand of single-element vector type
178 /// (e.g. v1f32), convert it into the equivalent operation that returns a
179 /// scalar (e.g. f32) value.
180 SDOperand ScalarizeVectorOp(SDOperand O);
182 /// isShuffleLegal - Return true if a vector shuffle is legal with the
183 /// specified mask and type. Targets can specify exactly which masks they
184 /// support and the code generator is tasked with not creating illegal masks.
186 /// Note that this will also return true for shuffles that are promoted to a
189 /// If this is a legal shuffle, this method returns the (possibly promoted)
190 /// build_vector Mask. If it's not a legal shuffle, it returns null.
191 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
193 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
194 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
196 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
198 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
200 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
203 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT,
204 MVT::ValueType DestVT);
205 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
206 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
207 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
209 MVT::ValueType DestVT);
210 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
212 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
215 SDOperand ExpandBSWAP(SDOperand Op);
216 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
217 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
218 SDOperand &Lo, SDOperand &Hi);
219 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
220 SDOperand &Lo, SDOperand &Hi);
222 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
223 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
227 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
228 /// specified mask and type. Targets can specify exactly which masks they
229 /// support and the code generator is tasked with not creating illegal masks.
231 /// Note that this will also return true for shuffles that are promoted to a
233 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
234 SDOperand Mask) const {
235 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
237 case TargetLowering::Legal:
238 case TargetLowering::Custom:
240 case TargetLowering::Promote: {
241 // If this is promoted to a different type, convert the shuffle mask and
242 // ask if it is legal in the promoted type!
243 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
245 // If we changed # elements, change the shuffle mask.
246 unsigned NumEltsGrowth =
247 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
248 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
249 if (NumEltsGrowth > 1) {
250 // Renumber the elements.
251 SmallVector<SDOperand, 8> Ops;
252 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
253 SDOperand InOp = Mask.getOperand(i);
254 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
255 if (InOp.getOpcode() == ISD::UNDEF)
256 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
258 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
259 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
263 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
269 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
272 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
273 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
274 ValueTypeActions(TLI.getValueTypeActions()) {
275 assert(MVT::LAST_VALUETYPE <= 32 &&
276 "Too many value types for ValueTypeActions to hold!");
279 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
280 /// contains all of a nodes operands before it contains the node.
281 static void ComputeTopDownOrdering(SelectionDAG &DAG,
282 SmallVector<SDNode*, 64> &Order) {
284 DenseMap<SDNode*, unsigned> Visited;
285 std::vector<SDNode*> Worklist;
286 Worklist.reserve(128);
288 // Compute ordering from all of the leaves in the graphs, those (like the
289 // entry node) that have no operands.
290 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
291 E = DAG.allnodes_end(); I != E; ++I) {
292 if (I->getNumOperands() == 0) {
294 Worklist.push_back(I);
298 while (!Worklist.empty()) {
299 SDNode *N = Worklist.back();
302 if (++Visited[N] != N->getNumOperands())
303 continue; // Haven't visited all operands yet
307 // Now that we have N in, add anything that uses it if all of their operands
309 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
311 Worklist.push_back(*UI);
314 assert(Order.size() == Visited.size() &&
316 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
317 "Error: DAG is cyclic!");
321 void SelectionDAGLegalize::LegalizeDAG() {
322 LastCALLSEQ_END = DAG.getEntryNode();
323 IsLegalizingCall = false;
325 // The legalize process is inherently a bottom-up recursive process (users
326 // legalize their uses before themselves). Given infinite stack space, we
327 // could just start legalizing on the root and traverse the whole graph. In
328 // practice however, this causes us to run out of stack space on large basic
329 // blocks. To avoid this problem, compute an ordering of the nodes where each
330 // node is only legalized after all of its operands are legalized.
331 SmallVector<SDNode*, 64> Order;
332 ComputeTopDownOrdering(DAG, Order);
334 for (unsigned i = 0, e = Order.size(); i != e; ++i)
335 HandleOp(SDOperand(Order[i], 0));
337 // Finally, it's possible the root changed. Get the new root.
338 SDOperand OldRoot = DAG.getRoot();
339 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
340 DAG.setRoot(LegalizedNodes[OldRoot]);
342 ExpandedNodes.clear();
343 LegalizedNodes.clear();
344 PromotedNodes.clear();
346 ScalarizedNodes.clear();
348 // Remove dead nodes now.
349 DAG.RemoveDeadNodes();
353 /// FindCallEndFromCallStart - Given a chained node that is part of a call
354 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
355 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
356 if (Node->getOpcode() == ISD::CALLSEQ_END)
358 if (Node->use_empty())
359 return 0; // No CallSeqEnd
361 // The chain is usually at the end.
362 SDOperand TheChain(Node, Node->getNumValues()-1);
363 if (TheChain.getValueType() != MVT::Other) {
364 // Sometimes it's at the beginning.
365 TheChain = SDOperand(Node, 0);
366 if (TheChain.getValueType() != MVT::Other) {
367 // Otherwise, hunt for it.
368 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
369 if (Node->getValueType(i) == MVT::Other) {
370 TheChain = SDOperand(Node, i);
374 // Otherwise, we walked into a node without a chain.
375 if (TheChain.getValueType() != MVT::Other)
380 for (SDNode::use_iterator UI = Node->use_begin(),
381 E = Node->use_end(); UI != E; ++UI) {
383 // Make sure to only follow users of our token chain.
385 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
386 if (User->getOperand(i) == TheChain)
387 if (SDNode *Result = FindCallEndFromCallStart(User))
393 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
394 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
395 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
396 assert(Node && "Didn't find callseq_start for a call??");
397 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
399 assert(Node->getOperand(0).getValueType() == MVT::Other &&
400 "Node doesn't have a token chain argument!");
401 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
404 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
405 /// see if any uses can reach Dest. If no dest operands can get to dest,
406 /// legalize them, legalize ourself, and return false, otherwise, return true.
408 /// Keep track of the nodes we fine that actually do lead to Dest in
409 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
411 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
412 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
413 if (N == Dest) return true; // N certainly leads to Dest :)
415 // If we've already processed this node and it does lead to Dest, there is no
416 // need to reprocess it.
417 if (NodesLeadingTo.count(N)) return true;
419 // If the first result of this node has been already legalized, then it cannot
421 switch (getTypeAction(N->getValueType(0))) {
423 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
426 if (PromotedNodes.count(SDOperand(N, 0))) return false;
429 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
433 // Okay, this node has not already been legalized. Check and legalize all
434 // operands. If none lead to Dest, then we can legalize this node.
435 bool OperandsLeadToDest = false;
436 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
437 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
438 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
440 if (OperandsLeadToDest) {
441 NodesLeadingTo.insert(N);
445 // Okay, this node looks safe, legalize it and return false.
446 HandleOp(SDOperand(N, 0));
450 /// HandleOp - Legalize, Promote, or Expand the specified operand as
451 /// appropriate for its type.
452 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
453 MVT::ValueType VT = Op.getValueType();
454 switch (getTypeAction(VT)) {
455 default: assert(0 && "Bad type action!");
456 case Legal: (void)LegalizeOp(Op); break;
457 case Promote: (void)PromoteOp(Op); break;
459 if (!MVT::isVector(VT)) {
460 // If this is an illegal scalar, expand it into its two component
463 if (Op.getOpcode() == ISD::TargetConstant)
464 break; // Allow illegal target nodes.
466 } else if (MVT::getVectorNumElements(VT) == 1) {
467 // If this is an illegal single element vector, convert it to a
469 (void)ScalarizeVectorOp(Op);
471 // Otherwise, this is an illegal multiple element vector.
472 // Split it in half and legalize both parts.
474 SplitVectorOp(Op, X, Y);
480 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
481 /// a load from the constant pool.
482 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
483 SelectionDAG &DAG, TargetLowering &TLI) {
486 // If a FP immediate is precise when represented as a float and if the
487 // target can do an extending load from float to double, we put it into
488 // the constant pool as a float, even if it's is statically typed as a
490 MVT::ValueType VT = CFP->getValueType(0);
491 bool isDouble = VT == MVT::f64;
492 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
495 if (VT!=MVT::f64 && VT!=MVT::f32)
496 assert(0 && "Invalid type expansion");
497 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(),
498 isDouble ? MVT::i64 : MVT::i32);
501 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) &&
502 // Only do this if the target has a native EXTLOAD instruction from f32.
503 // Do not try to be clever about long doubles (so far)
504 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
505 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
510 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
512 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
513 CPIdx, PseudoSourceValue::getConstantPool(),
516 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
517 PseudoSourceValue::getConstantPool(), 0);
522 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
525 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
526 SelectionDAG &DAG, TargetLowering &TLI) {
527 MVT::ValueType VT = Node->getValueType(0);
528 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
529 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
530 "fcopysign expansion only supported for f32 and f64");
531 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
533 // First get the sign bit of second operand.
534 SDOperand Mask1 = (SrcVT == MVT::f64)
535 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
536 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
537 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
538 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
539 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
540 // Shift right or sign-extend it if the two operands have different types.
541 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
543 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
544 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
545 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
546 } else if (SizeDiff < 0)
547 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
549 // Clear the sign bit of first operand.
550 SDOperand Mask2 = (VT == MVT::f64)
551 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
552 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
553 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
554 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
555 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
557 // Or the value with the sign bit.
558 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
562 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
564 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
565 TargetLowering &TLI) {
566 SDOperand Chain = ST->getChain();
567 SDOperand Ptr = ST->getBasePtr();
568 SDOperand Val = ST->getValue();
569 MVT::ValueType VT = Val.getValueType();
570 int Alignment = ST->getAlignment();
571 int SVOffset = ST->getSrcValueOffset();
572 if (MVT::isFloatingPoint(ST->getMemoryVT())) {
573 // Expand to a bitconvert of the value to the integer type of the
574 // same size, then a (misaligned) int store.
575 MVT::ValueType intVT;
578 else if (VT==MVT::f32)
581 assert(0 && "Unaligned load of unsupported floating point type");
583 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
584 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
585 SVOffset, ST->isVolatile(), Alignment);
587 assert(MVT::isInteger(ST->getMemoryVT()) &&
588 "Unaligned store of unknown type.");
589 // Get the half-size VT
590 MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1;
591 int NumBits = MVT::getSizeInBits(NewStoredVT);
592 int IncrementSize = NumBits / 8;
594 // Divide the stored value in two parts.
595 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
597 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
599 // Store the two parts
600 SDOperand Store1, Store2;
601 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
602 ST->getSrcValue(), SVOffset, NewStoredVT,
603 ST->isVolatile(), Alignment);
604 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
605 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
606 Alignment = MinAlign(Alignment, IncrementSize);
607 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
608 ST->getSrcValue(), SVOffset + IncrementSize,
609 NewStoredVT, ST->isVolatile(), Alignment);
611 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
614 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
616 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
617 TargetLowering &TLI) {
618 int SVOffset = LD->getSrcValueOffset();
619 SDOperand Chain = LD->getChain();
620 SDOperand Ptr = LD->getBasePtr();
621 MVT::ValueType VT = LD->getValueType(0);
622 MVT::ValueType LoadedVT = LD->getMemoryVT();
623 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT)) {
624 // Expand to a (misaligned) integer load of the same size,
625 // then bitconvert to floating point.
626 MVT::ValueType intVT;
627 if (LoadedVT == MVT::f64)
629 else if (LoadedVT == MVT::f32)
632 assert(0 && "Unaligned load of unsupported floating point type");
634 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
635 SVOffset, LD->isVolatile(),
637 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
639 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
641 SDOperand Ops[] = { Result, Chain };
642 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
645 assert((MVT::isInteger(LoadedVT) || MVT::isVector(LoadedVT)) &&
646 "Unaligned load of unsupported type.");
648 // Compute the new VT that is half the size of the old one. We either have an
649 // integer MVT or we have a vector MVT.
650 unsigned NumBits = MVT::getSizeInBits(LoadedVT);
651 MVT::ValueType NewLoadedVT;
652 if (!MVT::isVector(LoadedVT)) {
653 NewLoadedVT = MVT::getIntegerType(NumBits/2);
655 // FIXME: This is not right for <1 x anything> it is also not right for
656 // non-power-of-two vectors.
657 NewLoadedVT = MVT::getVectorType(MVT::getVectorElementType(LoadedVT),
658 MVT::getVectorNumElements(LoadedVT)/2);
662 unsigned Alignment = LD->getAlignment();
663 unsigned IncrementSize = NumBits / 8;
664 ISD::LoadExtType HiExtType = LD->getExtensionType();
666 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
667 if (HiExtType == ISD::NON_EXTLOAD)
668 HiExtType = ISD::ZEXTLOAD;
670 // Load the value in two parts
672 if (TLI.isLittleEndian()) {
673 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
674 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
675 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
676 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
677 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
678 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
679 MinAlign(Alignment, IncrementSize));
681 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
682 NewLoadedVT,LD->isVolatile(), Alignment);
683 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
684 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
685 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
686 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
687 MinAlign(Alignment, IncrementSize));
690 // aggregate the two parts
691 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
692 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
693 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
695 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
698 SDOperand Ops[] = { Result, TF };
699 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
702 /// UnrollVectorOp - We know that the given vector has a legal type, however
703 /// the operation it performs is not legal and is an operation that we have
704 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
705 /// operating on each element individually.
706 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
707 MVT::ValueType VT = Op.getValueType();
708 assert(isTypeLegal(VT) &&
709 "Caller should expand or promote operands that are not legal!");
710 assert(Op.Val->getNumValues() == 1 &&
711 "Can't unroll a vector with multiple results!");
712 unsigned NE = MVT::getVectorNumElements(VT);
713 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
715 SmallVector<SDOperand, 8> Scalars;
716 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
717 for (unsigned i = 0; i != NE; ++i) {
718 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
719 SDOperand Operand = Op.getOperand(j);
720 MVT::ValueType OperandVT = Operand.getValueType();
721 if (MVT::isVector(OperandVT)) {
722 // A vector operand; extract a single element.
723 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
724 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
727 DAG.getConstant(i, MVT::i32));
729 // A scalar operand; just use it as is.
730 Operands[j] = Operand;
733 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
734 &Operands[0], Operands.size()));
737 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
740 /// GetFPLibCall - Return the right libcall for the given floating point type.
741 static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
742 RTLIB::Libcall Call_F32,
743 RTLIB::Libcall Call_F64,
744 RTLIB::Libcall Call_F80,
745 RTLIB::Libcall Call_PPCF128) {
747 VT == MVT::f32 ? Call_F32 :
748 VT == MVT::f64 ? Call_F64 :
749 VT == MVT::f80 ? Call_F80 :
750 VT == MVT::ppcf128 ? Call_PPCF128 :
751 RTLIB::UNKNOWN_LIBCALL;
754 /// LegalizeOp - We know that the specified value has a legal type, and
755 /// that its operands are legal. Now ensure that the operation itself
756 /// is legal, recursively ensuring that the operands' operations remain
758 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
759 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
762 assert(isTypeLegal(Op.getValueType()) &&
763 "Caller should expand or promote operands that are not legal!");
764 SDNode *Node = Op.Val;
766 // If this operation defines any values that cannot be represented in a
767 // register on this target, make sure to expand or promote them.
768 if (Node->getNumValues() > 1) {
769 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
770 if (getTypeAction(Node->getValueType(i)) != Legal) {
771 HandleOp(Op.getValue(i));
772 assert(LegalizedNodes.count(Op) &&
773 "Handling didn't add legal operands!");
774 return LegalizedNodes[Op];
778 // Note that LegalizeOp may be reentered even from single-use nodes, which
779 // means that we always must cache transformed nodes.
780 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
781 if (I != LegalizedNodes.end()) return I->second;
783 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
784 SDOperand Result = Op;
785 bool isCustom = false;
787 switch (Node->getOpcode()) {
788 case ISD::FrameIndex:
789 case ISD::EntryToken:
791 case ISD::BasicBlock:
792 case ISD::TargetFrameIndex:
793 case ISD::TargetJumpTable:
794 case ISD::TargetConstant:
795 case ISD::TargetConstantFP:
796 case ISD::TargetConstantPool:
797 case ISD::TargetGlobalAddress:
798 case ISD::TargetGlobalTLSAddress:
799 case ISD::TargetExternalSymbol:
802 case ISD::MEMOPERAND:
805 // Primitives must all be legal.
806 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
807 "This must be legal!");
810 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
811 // If this is a target node, legalize it by legalizing the operands then
812 // passing it through.
813 SmallVector<SDOperand, 8> Ops;
814 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
815 Ops.push_back(LegalizeOp(Node->getOperand(i)));
817 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
819 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
820 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
821 return Result.getValue(Op.ResNo);
823 // Otherwise this is an unhandled builtin node. splat.
825 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
827 assert(0 && "Do not know how to legalize this operator!");
829 case ISD::GLOBAL_OFFSET_TABLE:
830 case ISD::GlobalAddress:
831 case ISD::GlobalTLSAddress:
832 case ISD::ExternalSymbol:
833 case ISD::ConstantPool:
834 case ISD::JumpTable: // Nothing to do.
835 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
836 default: assert(0 && "This action is not supported yet!");
837 case TargetLowering::Custom:
838 Tmp1 = TLI.LowerOperation(Op, DAG);
839 if (Tmp1.Val) Result = Tmp1;
840 // FALLTHROUGH if the target doesn't want to lower this op after all.
841 case TargetLowering::Legal:
846 case ISD::RETURNADDR:
847 // The only option for these nodes is to custom lower them. If the target
848 // does not custom lower them, then return zero.
849 Tmp1 = TLI.LowerOperation(Op, DAG);
853 Result = DAG.getConstant(0, TLI.getPointerTy());
855 case ISD::FRAME_TO_ARGS_OFFSET: {
856 MVT::ValueType VT = Node->getValueType(0);
857 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
858 default: assert(0 && "This action is not supported yet!");
859 case TargetLowering::Custom:
860 Result = TLI.LowerOperation(Op, DAG);
861 if (Result.Val) break;
863 case TargetLowering::Legal:
864 Result = DAG.getConstant(0, VT);
869 case ISD::EXCEPTIONADDR: {
870 Tmp1 = LegalizeOp(Node->getOperand(0));
871 MVT::ValueType VT = Node->getValueType(0);
872 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
873 default: assert(0 && "This action is not supported yet!");
874 case TargetLowering::Expand: {
875 unsigned Reg = TLI.getExceptionAddressRegister();
876 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
879 case TargetLowering::Custom:
880 Result = TLI.LowerOperation(Op, DAG);
881 if (Result.Val) break;
883 case TargetLowering::Legal: {
884 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
885 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
891 if (Result.Val->getNumValues() == 1) break;
893 assert(Result.Val->getNumValues() == 2 &&
894 "Cannot return more than two values!");
896 // Since we produced two values, make sure to remember that we
897 // legalized both of them.
898 Tmp1 = LegalizeOp(Result);
899 Tmp2 = LegalizeOp(Result.getValue(1));
900 AddLegalizedOperand(Op.getValue(0), Tmp1);
901 AddLegalizedOperand(Op.getValue(1), Tmp2);
902 return Op.ResNo ? Tmp2 : Tmp1;
903 case ISD::EHSELECTION: {
904 Tmp1 = LegalizeOp(Node->getOperand(0));
905 Tmp2 = LegalizeOp(Node->getOperand(1));
906 MVT::ValueType VT = Node->getValueType(0);
907 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
908 default: assert(0 && "This action is not supported yet!");
909 case TargetLowering::Expand: {
910 unsigned Reg = TLI.getExceptionSelectorRegister();
911 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
914 case TargetLowering::Custom:
915 Result = TLI.LowerOperation(Op, DAG);
916 if (Result.Val) break;
918 case TargetLowering::Legal: {
919 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
920 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
926 if (Result.Val->getNumValues() == 1) break;
928 assert(Result.Val->getNumValues() == 2 &&
929 "Cannot return more than two values!");
931 // Since we produced two values, make sure to remember that we
932 // legalized both of them.
933 Tmp1 = LegalizeOp(Result);
934 Tmp2 = LegalizeOp(Result.getValue(1));
935 AddLegalizedOperand(Op.getValue(0), Tmp1);
936 AddLegalizedOperand(Op.getValue(1), Tmp2);
937 return Op.ResNo ? Tmp2 : Tmp1;
938 case ISD::EH_RETURN: {
939 MVT::ValueType VT = Node->getValueType(0);
940 // The only "good" option for this node is to custom lower it.
941 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
942 default: assert(0 && "This action is not supported at all!");
943 case TargetLowering::Custom:
944 Result = TLI.LowerOperation(Op, DAG);
945 if (Result.Val) break;
947 case TargetLowering::Legal:
948 // Target does not know, how to lower this, lower to noop
949 Result = LegalizeOp(Node->getOperand(0));
954 case ISD::AssertSext:
955 case ISD::AssertZext:
956 Tmp1 = LegalizeOp(Node->getOperand(0));
957 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
959 case ISD::MERGE_VALUES:
960 // Legalize eliminates MERGE_VALUES nodes.
961 Result = Node->getOperand(Op.ResNo);
963 case ISD::CopyFromReg:
964 Tmp1 = LegalizeOp(Node->getOperand(0));
965 Result = Op.getValue(0);
966 if (Node->getNumValues() == 2) {
967 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
969 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
970 if (Node->getNumOperands() == 3) {
971 Tmp2 = LegalizeOp(Node->getOperand(2));
972 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
974 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
976 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
978 // Since CopyFromReg produces two values, make sure to remember that we
979 // legalized both of them.
980 AddLegalizedOperand(Op.getValue(0), Result);
981 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
982 return Result.getValue(Op.ResNo);
984 MVT::ValueType VT = Op.getValueType();
985 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
986 default: assert(0 && "This action is not supported yet!");
987 case TargetLowering::Expand:
988 if (MVT::isInteger(VT))
989 Result = DAG.getConstant(0, VT);
990 else if (MVT::isFloatingPoint(VT))
991 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
994 assert(0 && "Unknown value type!");
996 case TargetLowering::Legal:
1002 case ISD::INTRINSIC_W_CHAIN:
1003 case ISD::INTRINSIC_WO_CHAIN:
1004 case ISD::INTRINSIC_VOID: {
1005 SmallVector<SDOperand, 8> Ops;
1006 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1007 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1008 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1010 // Allow the target to custom lower its intrinsics if it wants to.
1011 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1012 TargetLowering::Custom) {
1013 Tmp3 = TLI.LowerOperation(Result, DAG);
1014 if (Tmp3.Val) Result = Tmp3;
1017 if (Result.Val->getNumValues() == 1) break;
1019 // Must have return value and chain result.
1020 assert(Result.Val->getNumValues() == 2 &&
1021 "Cannot return more than two values!");
1023 // Since loads produce two values, make sure to remember that we
1024 // legalized both of them.
1025 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1026 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1027 return Result.getValue(Op.ResNo);
1031 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
1032 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1034 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
1035 case TargetLowering::Promote:
1036 default: assert(0 && "This action is not supported yet!");
1037 case TargetLowering::Expand: {
1038 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1039 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1040 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
1042 if (MMI && (useDEBUG_LOC || useLABEL)) {
1043 const std::string &FName =
1044 cast<StringSDNode>(Node->getOperand(3))->getValue();
1045 const std::string &DirName =
1046 cast<StringSDNode>(Node->getOperand(4))->getValue();
1047 unsigned SrcFile = MMI->RecordSource(DirName, FName);
1049 SmallVector<SDOperand, 8> Ops;
1050 Ops.push_back(Tmp1); // chain
1051 SDOperand LineOp = Node->getOperand(1);
1052 SDOperand ColOp = Node->getOperand(2);
1055 Ops.push_back(LineOp); // line #
1056 Ops.push_back(ColOp); // col #
1057 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1058 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1060 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
1061 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
1062 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1063 Ops.push_back(DAG.getConstant(ID, MVT::i32));
1064 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label
1065 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size());
1068 Result = Tmp1; // chain
1072 case TargetLowering::Legal:
1073 if (Tmp1 != Node->getOperand(0) ||
1074 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1075 SmallVector<SDOperand, 8> Ops;
1076 Ops.push_back(Tmp1);
1077 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1078 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1079 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1081 // Otherwise promote them.
1082 Ops.push_back(PromoteOp(Node->getOperand(1)));
1083 Ops.push_back(PromoteOp(Node->getOperand(2)));
1085 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1086 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1087 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1094 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1095 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1096 default: assert(0 && "This action is not supported yet!");
1097 case TargetLowering::Legal:
1098 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1099 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1100 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1101 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1106 case ISD::DEBUG_LOC:
1107 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1108 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1109 default: assert(0 && "This action is not supported yet!");
1110 case TargetLowering::Legal:
1111 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1112 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1113 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1114 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1115 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1121 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!");
1122 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1123 default: assert(0 && "This action is not supported yet!");
1124 case TargetLowering::Legal:
1125 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1126 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1127 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand.
1128 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1130 case TargetLowering::Expand:
1131 Result = LegalizeOp(Node->getOperand(0));
1136 case ISD::MEMBARRIER: {
1137 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1138 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1139 default: assert(0 && "This action is not supported yet!");
1140 case TargetLowering::Legal: {
1142 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1143 for (int x = 1; x < 6; ++x)
1144 Ops[x] = PromoteOp(Node->getOperand(x));
1145 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1148 case TargetLowering::Expand:
1149 //There is no libgcc call for this op
1150 Result = Node->getOperand(0); // Noop
1156 case ISD::ATOMIC_LCS:
1157 case ISD::ATOMIC_LAS:
1158 case ISD::ATOMIC_SWAP: {
1159 assert(((Node->getNumOperands() == 4 && Node->getOpcode() == ISD::ATOMIC_LCS) ||
1160 (Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_LAS) ||
1161 (Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_SWAP)) &&
1162 "Invalid MemBarrier node!");
1163 int num = Node->getOpcode() == ISD::ATOMIC_LCS ? 4 : 3;
1164 MVT::ValueType VT = Node->getValueType(0);
1165 switch (TLI.getOperationAction(ISD::ATOMIC_LCS, VT)) {
1166 default: assert(0 && "This action is not supported yet!");
1167 case TargetLowering::Legal: {
1169 for (int x = 0; x < num; ++x)
1170 Ops[x] = LegalizeOp(Node->getOperand(x));
1171 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num);
1172 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1173 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1174 return Result.getValue(Op.ResNo);
1181 case ISD::Constant: {
1182 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1184 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1186 // We know we don't need to expand constants here, constants only have one
1187 // value and we check that it is fine above.
1189 if (opAction == TargetLowering::Custom) {
1190 Tmp1 = TLI.LowerOperation(Result, DAG);
1196 case ISD::ConstantFP: {
1197 // Spill FP immediates to the constant pool if the target cannot directly
1198 // codegen them. Targets often have some immediate values that can be
1199 // efficiently generated into an FP register without a load. We explicitly
1200 // leave these constants as ConstantFP nodes for the target to deal with.
1201 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1203 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1204 default: assert(0 && "This action is not supported yet!");
1205 case TargetLowering::Legal:
1207 case TargetLowering::Custom:
1208 Tmp3 = TLI.LowerOperation(Result, DAG);
1214 case TargetLowering::Expand: {
1215 // Check to see if this FP immediate is already legal.
1216 bool isLegal = false;
1217 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1218 E = TLI.legal_fpimm_end(); I != E; ++I) {
1219 if (CFP->isExactlyValue(*I)) {
1224 // If this is a legal constant, turn it into a TargetConstantFP node.
1227 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1232 case ISD::TokenFactor:
1233 if (Node->getNumOperands() == 2) {
1234 Tmp1 = LegalizeOp(Node->getOperand(0));
1235 Tmp2 = LegalizeOp(Node->getOperand(1));
1236 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1237 } else if (Node->getNumOperands() == 3) {
1238 Tmp1 = LegalizeOp(Node->getOperand(0));
1239 Tmp2 = LegalizeOp(Node->getOperand(1));
1240 Tmp3 = LegalizeOp(Node->getOperand(2));
1241 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1243 SmallVector<SDOperand, 8> Ops;
1244 // Legalize the operands.
1245 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1246 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1247 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1251 case ISD::FORMAL_ARGUMENTS:
1253 // The only option for this is to custom lower it.
1254 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1255 assert(Tmp3.Val && "Target didn't custom lower this node!");
1257 // The number of incoming and outgoing values should match; unless the final
1258 // outgoing value is a flag.
1259 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1260 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1261 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1263 "Lowering call/formal_arguments produced unexpected # results!");
1265 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1266 // remember that we legalized all of them, so it doesn't get relegalized.
1267 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1268 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1270 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1273 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1276 case ISD::EXTRACT_SUBREG: {
1277 Tmp1 = LegalizeOp(Node->getOperand(0));
1278 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1279 assert(idx && "Operand must be a constant");
1280 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1281 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1284 case ISD::INSERT_SUBREG: {
1285 Tmp1 = LegalizeOp(Node->getOperand(0));
1286 Tmp2 = LegalizeOp(Node->getOperand(1));
1287 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1288 assert(idx && "Operand must be a constant");
1289 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1290 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1293 case ISD::BUILD_VECTOR:
1294 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1295 default: assert(0 && "This action is not supported yet!");
1296 case TargetLowering::Custom:
1297 Tmp3 = TLI.LowerOperation(Result, DAG);
1303 case TargetLowering::Expand:
1304 Result = ExpandBUILD_VECTOR(Result.Val);
1308 case ISD::INSERT_VECTOR_ELT:
1309 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1310 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1312 // The type of the value to insert may not be legal, even though the vector
1313 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1315 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1316 default: assert(0 && "Cannot expand insert element operand");
1317 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1318 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1320 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1322 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1323 Node->getValueType(0))) {
1324 default: assert(0 && "This action is not supported yet!");
1325 case TargetLowering::Legal:
1327 case TargetLowering::Custom:
1328 Tmp4 = TLI.LowerOperation(Result, DAG);
1334 case TargetLowering::Expand: {
1335 // If the insert index is a constant, codegen this as a scalar_to_vector,
1336 // then a shuffle that inserts it into the right position in the vector.
1337 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1338 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1339 // match the element type of the vector being created.
1340 if (Tmp2.getValueType() ==
1341 MVT::getVectorElementType(Op.getValueType())) {
1342 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1343 Tmp1.getValueType(), Tmp2);
1345 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1346 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1347 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1349 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1350 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1351 // elt 0 of the RHS.
1352 SmallVector<SDOperand, 8> ShufOps;
1353 for (unsigned i = 0; i != NumElts; ++i) {
1354 if (i != InsertPos->getValue())
1355 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1357 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1359 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1360 &ShufOps[0], ShufOps.size());
1362 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1363 Tmp1, ScVec, ShufMask);
1364 Result = LegalizeOp(Result);
1369 // If the target doesn't support this, we have to spill the input vector
1370 // to a temporary stack slot, update the element, then reload it. This is
1371 // badness. We could also load the value into a vector register (either
1372 // with a "move to register" or "extload into register" instruction, then
1373 // permute it into place, if the idx is a constant and if the idx is
1374 // supported by the target.
1375 MVT::ValueType VT = Tmp1.getValueType();
1376 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1377 MVT::ValueType IdxVT = Tmp3.getValueType();
1378 MVT::ValueType PtrVT = TLI.getPointerTy();
1379 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
1381 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val);
1382 int SPFI = StackPtrFI->getIndex();
1384 // Store the vector.
1385 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
1386 PseudoSourceValue::getFixedStack(),
1389 // Truncate or zero extend offset to target pointer type.
1390 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1391 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1392 // Add the offset to the index.
1393 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1394 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1395 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1396 // Store the scalar value.
1397 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
1398 PseudoSourceValue::getFixedStack(), SPFI, EltVT);
1399 // Load the updated vector.
1400 Result = DAG.getLoad(VT, Ch, StackPtr,
1401 PseudoSourceValue::getFixedStack(), SPFI);
1406 case ISD::SCALAR_TO_VECTOR:
1407 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1408 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1412 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1413 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1414 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1415 Node->getValueType(0))) {
1416 default: assert(0 && "This action is not supported yet!");
1417 case TargetLowering::Legal:
1419 case TargetLowering::Custom:
1420 Tmp3 = TLI.LowerOperation(Result, DAG);
1426 case TargetLowering::Expand:
1427 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1431 case ISD::VECTOR_SHUFFLE:
1432 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1433 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1434 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1436 // Allow targets to custom lower the SHUFFLEs they support.
1437 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1438 default: assert(0 && "Unknown operation action!");
1439 case TargetLowering::Legal:
1440 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1441 "vector shuffle should not be created if not legal!");
1443 case TargetLowering::Custom:
1444 Tmp3 = TLI.LowerOperation(Result, DAG);
1450 case TargetLowering::Expand: {
1451 MVT::ValueType VT = Node->getValueType(0);
1452 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1453 MVT::ValueType PtrVT = TLI.getPointerTy();
1454 SDOperand Mask = Node->getOperand(2);
1455 unsigned NumElems = Mask.getNumOperands();
1456 SmallVector<SDOperand,8> Ops;
1457 for (unsigned i = 0; i != NumElems; ++i) {
1458 SDOperand Arg = Mask.getOperand(i);
1459 if (Arg.getOpcode() == ISD::UNDEF) {
1460 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1462 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1463 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1465 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1466 DAG.getConstant(Idx, PtrVT)));
1468 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1469 DAG.getConstant(Idx - NumElems, PtrVT)));
1472 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1475 case TargetLowering::Promote: {
1476 // Change base type to a different vector type.
1477 MVT::ValueType OVT = Node->getValueType(0);
1478 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1480 // Cast the two input vectors.
1481 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1482 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1484 // Convert the shuffle mask to the right # elements.
1485 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1486 assert(Tmp3.Val && "Shuffle not legal?");
1487 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1488 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1494 case ISD::EXTRACT_VECTOR_ELT:
1495 Tmp1 = Node->getOperand(0);
1496 Tmp2 = LegalizeOp(Node->getOperand(1));
1497 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1498 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1501 case ISD::EXTRACT_SUBVECTOR:
1502 Tmp1 = Node->getOperand(0);
1503 Tmp2 = LegalizeOp(Node->getOperand(1));
1504 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1505 Result = ExpandEXTRACT_SUBVECTOR(Result);
1508 case ISD::CALLSEQ_START: {
1509 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1511 // Recursively Legalize all of the inputs of the call end that do not lead
1512 // to this call start. This ensures that any libcalls that need be inserted
1513 // are inserted *before* the CALLSEQ_START.
1514 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1515 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1516 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1520 // Now that we legalized all of the inputs (which may have inserted
1521 // libcalls) create the new CALLSEQ_START node.
1522 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1524 // Merge in the last call, to ensure that this call start after the last
1526 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1527 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1528 Tmp1 = LegalizeOp(Tmp1);
1531 // Do not try to legalize the target-specific arguments (#1+).
1532 if (Tmp1 != Node->getOperand(0)) {
1533 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1535 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1538 // Remember that the CALLSEQ_START is legalized.
1539 AddLegalizedOperand(Op.getValue(0), Result);
1540 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1541 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1543 // Now that the callseq_start and all of the non-call nodes above this call
1544 // sequence have been legalized, legalize the call itself. During this
1545 // process, no libcalls can/will be inserted, guaranteeing that no calls
1547 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1548 SDOperand InCallSEQ = LastCALLSEQ_END;
1549 // Note that we are selecting this call!
1550 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1551 IsLegalizingCall = true;
1553 // Legalize the call, starting from the CALLSEQ_END.
1554 LegalizeOp(LastCALLSEQ_END);
1555 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1558 case ISD::CALLSEQ_END:
1559 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1560 // will cause this node to be legalized as well as handling libcalls right.
1561 if (LastCALLSEQ_END.Val != Node) {
1562 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1563 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1564 assert(I != LegalizedNodes.end() &&
1565 "Legalizing the call start should have legalized this node!");
1569 // Otherwise, the call start has been legalized and everything is going
1570 // according to plan. Just legalize ourselves normally here.
1571 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1572 // Do not try to legalize the target-specific arguments (#1+), except for
1573 // an optional flag input.
1574 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1575 if (Tmp1 != Node->getOperand(0)) {
1576 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1578 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1581 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1582 if (Tmp1 != Node->getOperand(0) ||
1583 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1584 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1587 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1590 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1591 // This finishes up call legalization.
1592 IsLegalizingCall = false;
1594 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1595 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1596 if (Node->getNumValues() == 2)
1597 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1598 return Result.getValue(Op.ResNo);
1599 case ISD::DYNAMIC_STACKALLOC: {
1600 MVT::ValueType VT = Node->getValueType(0);
1601 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1602 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1603 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1604 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1606 Tmp1 = Result.getValue(0);
1607 Tmp2 = Result.getValue(1);
1608 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1609 default: assert(0 && "This action is not supported yet!");
1610 case TargetLowering::Expand: {
1611 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1612 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1613 " not tell us which reg is the stack pointer!");
1614 SDOperand Chain = Tmp1.getOperand(0);
1616 // Chain the dynamic stack allocation so that it doesn't modify the stack
1617 // pointer when other instructions are using the stack.
1618 Chain = DAG.getCALLSEQ_START(Chain,
1619 DAG.getConstant(0, TLI.getPointerTy()));
1621 SDOperand Size = Tmp2.getOperand(1);
1622 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1623 Chain = SP.getValue(1);
1624 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1625 unsigned StackAlign =
1626 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1627 if (Align > StackAlign)
1628 SP = DAG.getNode(ISD::AND, VT, SP,
1629 DAG.getConstant(-(uint64_t)Align, VT));
1630 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1631 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1634 DAG.getCALLSEQ_END(Chain,
1635 DAG.getConstant(0, TLI.getPointerTy()),
1636 DAG.getConstant(0, TLI.getPointerTy()),
1639 Tmp1 = LegalizeOp(Tmp1);
1640 Tmp2 = LegalizeOp(Tmp2);
1643 case TargetLowering::Custom:
1644 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1646 Tmp1 = LegalizeOp(Tmp3);
1647 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1650 case TargetLowering::Legal:
1653 // Since this op produce two values, make sure to remember that we
1654 // legalized both of them.
1655 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1656 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1657 return Op.ResNo ? Tmp2 : Tmp1;
1659 case ISD::INLINEASM: {
1660 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1661 bool Changed = false;
1662 // Legalize all of the operands of the inline asm, in case they are nodes
1663 // that need to be expanded or something. Note we skip the asm string and
1664 // all of the TargetConstant flags.
1665 SDOperand Op = LegalizeOp(Ops[0]);
1666 Changed = Op != Ops[0];
1669 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1670 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1671 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1672 for (++i; NumVals; ++i, --NumVals) {
1673 SDOperand Op = LegalizeOp(Ops[i]);
1682 Op = LegalizeOp(Ops.back());
1683 Changed |= Op != Ops.back();
1688 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1690 // INLINE asm returns a chain and flag, make sure to add both to the map.
1691 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1692 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1693 return Result.getValue(Op.ResNo);
1696 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1697 // Ensure that libcalls are emitted before a branch.
1698 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1699 Tmp1 = LegalizeOp(Tmp1);
1700 LastCALLSEQ_END = DAG.getEntryNode();
1702 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1705 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1706 // Ensure that libcalls are emitted before a branch.
1707 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1708 Tmp1 = LegalizeOp(Tmp1);
1709 LastCALLSEQ_END = DAG.getEntryNode();
1711 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1712 default: assert(0 && "Indirect target must be legal type (pointer)!");
1714 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1717 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1720 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1721 // Ensure that libcalls are emitted before a branch.
1722 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1723 Tmp1 = LegalizeOp(Tmp1);
1724 LastCALLSEQ_END = DAG.getEntryNode();
1726 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1727 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1729 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1730 default: assert(0 && "This action is not supported yet!");
1731 case TargetLowering::Legal: break;
1732 case TargetLowering::Custom:
1733 Tmp1 = TLI.LowerOperation(Result, DAG);
1734 if (Tmp1.Val) Result = Tmp1;
1736 case TargetLowering::Expand: {
1737 SDOperand Chain = Result.getOperand(0);
1738 SDOperand Table = Result.getOperand(1);
1739 SDOperand Index = Result.getOperand(2);
1741 MVT::ValueType PTy = TLI.getPointerTy();
1742 MachineFunction &MF = DAG.getMachineFunction();
1743 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1744 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1745 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1748 switch (EntrySize) {
1749 default: assert(0 && "Size of jump table not supported yet."); break;
1750 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1751 PseudoSourceValue::getJumpTable(), 0); break;
1752 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1753 PseudoSourceValue::getJumpTable(), 0); break;
1757 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1758 // For PIC, the sequence is:
1759 // BRIND(load(Jumptable + index) + RelocBase)
1760 // RelocBase can be JumpTable, GOT or some sort of global base.
1761 if (PTy != MVT::i32)
1762 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1763 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1764 TLI.getPICJumpTableRelocBase(Table, DAG));
1766 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1771 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1772 // Ensure that libcalls are emitted before a return.
1773 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1774 Tmp1 = LegalizeOp(Tmp1);
1775 LastCALLSEQ_END = DAG.getEntryNode();
1777 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1778 case Expand: assert(0 && "It's impossible to expand bools");
1780 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1783 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1785 // The top bits of the promoted condition are not necessarily zero, ensure
1786 // that the value is properly zero extended.
1787 if (!DAG.MaskedValueIsZero(Tmp2,
1788 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1789 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1793 // Basic block destination (Op#2) is always legal.
1794 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1796 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1797 default: assert(0 && "This action is not supported yet!");
1798 case TargetLowering::Legal: break;
1799 case TargetLowering::Custom:
1800 Tmp1 = TLI.LowerOperation(Result, DAG);
1801 if (Tmp1.Val) Result = Tmp1;
1803 case TargetLowering::Expand:
1804 // Expand brcond's setcc into its constituent parts and create a BR_CC
1806 if (Tmp2.getOpcode() == ISD::SETCC) {
1807 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1808 Tmp2.getOperand(0), Tmp2.getOperand(1),
1809 Node->getOperand(2));
1811 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1812 DAG.getCondCode(ISD::SETNE), Tmp2,
1813 DAG.getConstant(0, Tmp2.getValueType()),
1814 Node->getOperand(2));
1820 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1821 // Ensure that libcalls are emitted before a branch.
1822 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1823 Tmp1 = LegalizeOp(Tmp1);
1824 Tmp2 = Node->getOperand(2); // LHS
1825 Tmp3 = Node->getOperand(3); // RHS
1826 Tmp4 = Node->getOperand(1); // CC
1828 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1829 LastCALLSEQ_END = DAG.getEntryNode();
1831 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1832 // the LHS is a legal SETCC itself. In this case, we need to compare
1833 // the result against zero to select between true and false values.
1834 if (Tmp3.Val == 0) {
1835 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1836 Tmp4 = DAG.getCondCode(ISD::SETNE);
1839 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1840 Node->getOperand(4));
1842 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1843 default: assert(0 && "Unexpected action for BR_CC!");
1844 case TargetLowering::Legal: break;
1845 case TargetLowering::Custom:
1846 Tmp4 = TLI.LowerOperation(Result, DAG);
1847 if (Tmp4.Val) Result = Tmp4;
1852 LoadSDNode *LD = cast<LoadSDNode>(Node);
1853 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1854 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1856 ISD::LoadExtType ExtType = LD->getExtensionType();
1857 if (ExtType == ISD::NON_EXTLOAD) {
1858 MVT::ValueType VT = Node->getValueType(0);
1859 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1860 Tmp3 = Result.getValue(0);
1861 Tmp4 = Result.getValue(1);
1863 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1864 default: assert(0 && "This action is not supported yet!");
1865 case TargetLowering::Legal:
1866 // If this is an unaligned load and the target doesn't support it,
1868 if (!TLI.allowsUnalignedMemoryAccesses()) {
1869 unsigned ABIAlignment = TLI.getTargetData()->
1870 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
1871 if (LD->getAlignment() < ABIAlignment){
1872 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1874 Tmp3 = Result.getOperand(0);
1875 Tmp4 = Result.getOperand(1);
1876 Tmp3 = LegalizeOp(Tmp3);
1877 Tmp4 = LegalizeOp(Tmp4);
1881 case TargetLowering::Custom:
1882 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1884 Tmp3 = LegalizeOp(Tmp1);
1885 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1888 case TargetLowering::Promote: {
1889 // Only promote a load of vector type to another.
1890 assert(MVT::isVector(VT) && "Cannot promote this load!");
1891 // Change base type to a different vector type.
1892 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1894 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1895 LD->getSrcValueOffset(),
1896 LD->isVolatile(), LD->getAlignment());
1897 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1898 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1902 // Since loads produce two values, make sure to remember that we
1903 // legalized both of them.
1904 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1905 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1906 return Op.ResNo ? Tmp4 : Tmp3;
1908 MVT::ValueType SrcVT = LD->getMemoryVT();
1909 unsigned SrcWidth = MVT::getSizeInBits(SrcVT);
1910 int SVOffset = LD->getSrcValueOffset();
1911 unsigned Alignment = LD->getAlignment();
1912 bool isVolatile = LD->isVolatile();
1914 if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) &&
1915 // Some targets pretend to have an i1 loading operation, and actually
1916 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1917 // bits are guaranteed to be zero; it helps the optimizers understand
1918 // that these bits are zero. It is also useful for EXTLOAD, since it
1919 // tells the optimizers that those bits are undefined. It would be
1920 // nice to have an effective generic way of getting these benefits...
1921 // Until such a way is found, don't insist on promoting i1 here.
1922 (SrcVT != MVT::i1 ||
1923 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1924 // Promote to a byte-sized load if not loading an integral number of
1925 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1926 unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT);
1927 MVT::ValueType NVT = MVT::getIntegerType(NewWidth);
1930 // The extra bits are guaranteed to be zero, since we stored them that
1931 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1933 ISD::LoadExtType NewExtType =
1934 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1936 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
1937 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1938 NVT, isVolatile, Alignment);
1940 Ch = Result.getValue(1); // The chain.
1942 if (ExtType == ISD::SEXTLOAD)
1943 // Having the top bits zero doesn't help when sign extending.
1944 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1945 Result, DAG.getValueType(SrcVT));
1946 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1947 // All the top bits are guaranteed to be zero - inform the optimizers.
1948 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
1949 DAG.getValueType(SrcVT));
1951 Tmp1 = LegalizeOp(Result);
1952 Tmp2 = LegalizeOp(Ch);
1953 } else if (SrcWidth & (SrcWidth - 1)) {
1954 // If not loading a power-of-2 number of bits, expand as two loads.
1955 assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) &&
1956 "Unsupported extload!");
1957 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1958 assert(RoundWidth < SrcWidth);
1959 unsigned ExtraWidth = SrcWidth - RoundWidth;
1960 assert(ExtraWidth < RoundWidth);
1961 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1962 "Load size not an integral number of bytes!");
1963 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
1964 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
1965 SDOperand Lo, Hi, Ch;
1966 unsigned IncrementSize;
1968 if (TLI.isLittleEndian()) {
1969 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1970 // Load the bottom RoundWidth bits.
1971 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
1972 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1975 // Load the remaining ExtraWidth bits.
1976 IncrementSize = RoundWidth / 8;
1977 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1978 DAG.getIntPtrConstant(IncrementSize));
1979 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1980 LD->getSrcValue(), SVOffset + IncrementSize,
1981 ExtraVT, isVolatile,
1982 MinAlign(Alignment, IncrementSize));
1984 // Build a factor node to remember that this load is independent of the
1986 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1989 // Move the top bits to the right place.
1990 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
1991 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1993 // Join the hi and lo parts.
1994 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
1996 // Big endian - avoid unaligned loads.
1997 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1998 // Load the top RoundWidth bits.
1999 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2000 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2003 // Load the remaining ExtraWidth bits.
2004 IncrementSize = RoundWidth / 8;
2005 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2006 DAG.getIntPtrConstant(IncrementSize));
2007 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2008 LD->getSrcValue(), SVOffset + IncrementSize,
2009 ExtraVT, isVolatile,
2010 MinAlign(Alignment, IncrementSize));
2012 // Build a factor node to remember that this load is independent of the
2014 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2017 // Move the top bits to the right place.
2018 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2019 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2021 // Join the hi and lo parts.
2022 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2025 Tmp1 = LegalizeOp(Result);
2026 Tmp2 = LegalizeOp(Ch);
2028 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2029 default: assert(0 && "This action is not supported yet!");
2030 case TargetLowering::Custom:
2033 case TargetLowering::Legal:
2034 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2035 Tmp1 = Result.getValue(0);
2036 Tmp2 = Result.getValue(1);
2039 Tmp3 = TLI.LowerOperation(Result, DAG);
2041 Tmp1 = LegalizeOp(Tmp3);
2042 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2045 // If this is an unaligned load and the target doesn't support it,
2047 if (!TLI.allowsUnalignedMemoryAccesses()) {
2048 unsigned ABIAlignment = TLI.getTargetData()->
2049 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
2050 if (LD->getAlignment() < ABIAlignment){
2051 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
2053 Tmp1 = Result.getOperand(0);
2054 Tmp2 = Result.getOperand(1);
2055 Tmp1 = LegalizeOp(Tmp1);
2056 Tmp2 = LegalizeOp(Tmp2);
2061 case TargetLowering::Expand:
2062 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2063 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2064 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2065 LD->getSrcValueOffset(),
2066 LD->isVolatile(), LD->getAlignment());
2067 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2068 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2069 Tmp2 = LegalizeOp(Load.getValue(1));
2072 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2073 // Turn the unsupported load into an EXTLOAD followed by an explicit
2074 // zero/sign extend inreg.
2075 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2076 Tmp1, Tmp2, LD->getSrcValue(),
2077 LD->getSrcValueOffset(), SrcVT,
2078 LD->isVolatile(), LD->getAlignment());
2080 if (ExtType == ISD::SEXTLOAD)
2081 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2082 Result, DAG.getValueType(SrcVT));
2084 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2085 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2086 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2091 // Since loads produce two values, make sure to remember that we legalized
2093 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2094 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2095 return Op.ResNo ? Tmp2 : Tmp1;
2098 case ISD::EXTRACT_ELEMENT: {
2099 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
2100 switch (getTypeAction(OpTy)) {
2101 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2103 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2105 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2106 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
2107 TLI.getShiftAmountTy()));
2108 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2111 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2112 Node->getOperand(0));
2116 // Get both the low and high parts.
2117 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2118 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2119 Result = Tmp2; // 1 -> Hi
2121 Result = Tmp1; // 0 -> Lo
2127 case ISD::CopyToReg:
2128 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2130 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2131 "Register type must be legal!");
2132 // Legalize the incoming value (must be a legal type).
2133 Tmp2 = LegalizeOp(Node->getOperand(2));
2134 if (Node->getNumValues() == 1) {
2135 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2137 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2138 if (Node->getNumOperands() == 4) {
2139 Tmp3 = LegalizeOp(Node->getOperand(3));
2140 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2143 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2146 // Since this produces two values, make sure to remember that we legalized
2148 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2149 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2155 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2157 // Ensure that libcalls are emitted before a return.
2158 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2159 Tmp1 = LegalizeOp(Tmp1);
2160 LastCALLSEQ_END = DAG.getEntryNode();
2162 switch (Node->getNumOperands()) {
2164 Tmp2 = Node->getOperand(1);
2165 Tmp3 = Node->getOperand(2); // Signness
2166 switch (getTypeAction(Tmp2.getValueType())) {
2168 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2171 if (!MVT::isVector(Tmp2.getValueType())) {
2173 ExpandOp(Tmp2, Lo, Hi);
2175 // Big endian systems want the hi reg first.
2176 if (TLI.isBigEndian())
2180 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2182 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2183 Result = LegalizeOp(Result);
2185 SDNode *InVal = Tmp2.Val;
2186 int InIx = Tmp2.ResNo;
2187 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
2188 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
2190 // Figure out if there is a simple type corresponding to this Vector
2191 // type. If so, convert to the vector type.
2192 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2193 if (TLI.isTypeLegal(TVT)) {
2194 // Turn this into a return of the vector type.
2195 Tmp2 = LegalizeOp(Tmp2);
2196 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2197 } else if (NumElems == 1) {
2198 // Turn this into a return of the scalar type.
2199 Tmp2 = ScalarizeVectorOp(Tmp2);
2200 Tmp2 = LegalizeOp(Tmp2);
2201 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2203 // FIXME: Returns of gcc generic vectors smaller than a legal type
2204 // should be returned in integer registers!
2206 // The scalarized value type may not be legal, e.g. it might require
2207 // promotion or expansion. Relegalize the return.
2208 Result = LegalizeOp(Result);
2210 // FIXME: Returns of gcc generic vectors larger than a legal vector
2211 // type should be returned by reference!
2213 SplitVectorOp(Tmp2, Lo, Hi);
2214 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2215 Result = LegalizeOp(Result);
2220 Tmp2 = PromoteOp(Node->getOperand(1));
2221 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2222 Result = LegalizeOp(Result);
2227 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2229 default: { // ret <values>
2230 SmallVector<SDOperand, 8> NewValues;
2231 NewValues.push_back(Tmp1);
2232 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2233 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2235 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2236 NewValues.push_back(Node->getOperand(i+1));
2240 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
2241 "FIXME: TODO: implement returning non-legal vector types!");
2242 ExpandOp(Node->getOperand(i), Lo, Hi);
2243 NewValues.push_back(Lo);
2244 NewValues.push_back(Node->getOperand(i+1));
2246 NewValues.push_back(Hi);
2247 NewValues.push_back(Node->getOperand(i+1));
2252 assert(0 && "Can't promote multiple return value yet!");
2255 if (NewValues.size() == Node->getNumOperands())
2256 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2258 Result = DAG.getNode(ISD::RET, MVT::Other,
2259 &NewValues[0], NewValues.size());
2264 if (Result.getOpcode() == ISD::RET) {
2265 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2266 default: assert(0 && "This action is not supported yet!");
2267 case TargetLowering::Legal: break;
2268 case TargetLowering::Custom:
2269 Tmp1 = TLI.LowerOperation(Result, DAG);
2270 if (Tmp1.Val) Result = Tmp1;
2276 StoreSDNode *ST = cast<StoreSDNode>(Node);
2277 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2278 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2279 int SVOffset = ST->getSrcValueOffset();
2280 unsigned Alignment = ST->getAlignment();
2281 bool isVolatile = ST->isVolatile();
2283 if (!ST->isTruncatingStore()) {
2284 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2285 // FIXME: We shouldn't do this for TargetConstantFP's.
2286 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2287 // to phase ordering between legalized code and the dag combiner. This
2288 // probably means that we need to integrate dag combiner and legalizer
2290 // We generally can't do this one for long doubles.
2291 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2292 if (CFP->getValueType(0) == MVT::f32 &&
2293 getTypeAction(MVT::i32) == Legal) {
2294 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF().
2295 convertToAPInt().getZExtValue(),
2297 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2298 SVOffset, isVolatile, Alignment);
2300 } else if (CFP->getValueType(0) == MVT::f64) {
2301 // If this target supports 64-bit registers, do a single 64-bit store.
2302 if (getTypeAction(MVT::i64) == Legal) {
2303 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2304 getZExtValue(), MVT::i64);
2305 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2306 SVOffset, isVolatile, Alignment);
2308 } else if (getTypeAction(MVT::i32) == Legal) {
2309 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2310 // stores. If the target supports neither 32- nor 64-bits, this
2311 // xform is certainly not worth it.
2312 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue();
2313 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32);
2314 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32);
2315 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2317 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2318 SVOffset, isVolatile, Alignment);
2319 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2320 DAG.getIntPtrConstant(4));
2321 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2322 isVolatile, MinAlign(Alignment, 4U));
2324 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2330 switch (getTypeAction(ST->getMemoryVT())) {
2332 Tmp3 = LegalizeOp(ST->getValue());
2333 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2336 MVT::ValueType VT = Tmp3.getValueType();
2337 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2338 default: assert(0 && "This action is not supported yet!");
2339 case TargetLowering::Legal:
2340 // If this is an unaligned store and the target doesn't support it,
2342 if (!TLI.allowsUnalignedMemoryAccesses()) {
2343 unsigned ABIAlignment = TLI.getTargetData()->
2344 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2345 if (ST->getAlignment() < ABIAlignment)
2346 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2350 case TargetLowering::Custom:
2351 Tmp1 = TLI.LowerOperation(Result, DAG);
2352 if (Tmp1.Val) Result = Tmp1;
2354 case TargetLowering::Promote:
2355 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2356 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2357 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2358 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2359 ST->getSrcValue(), SVOffset, isVolatile,
2366 // Truncate the value and store the result.
2367 Tmp3 = PromoteOp(ST->getValue());
2368 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2369 SVOffset, ST->getMemoryVT(),
2370 isVolatile, Alignment);
2374 unsigned IncrementSize = 0;
2377 // If this is a vector type, then we have to calculate the increment as
2378 // the product of the element size in bytes, and the number of elements
2379 // in the high half of the vector.
2380 if (MVT::isVector(ST->getValue().getValueType())) {
2381 SDNode *InVal = ST->getValue().Val;
2382 int InIx = ST->getValue().ResNo;
2383 MVT::ValueType InVT = InVal->getValueType(InIx);
2384 unsigned NumElems = MVT::getVectorNumElements(InVT);
2385 MVT::ValueType EVT = MVT::getVectorElementType(InVT);
2387 // Figure out if there is a simple type corresponding to this Vector
2388 // type. If so, convert to the vector type.
2389 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2390 if (TLI.isTypeLegal(TVT)) {
2391 // Turn this into a normal store of the vector type.
2392 Tmp3 = LegalizeOp(ST->getValue());
2393 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2394 SVOffset, isVolatile, Alignment);
2395 Result = LegalizeOp(Result);
2397 } else if (NumElems == 1) {
2398 // Turn this into a normal store of the scalar type.
2399 Tmp3 = ScalarizeVectorOp(ST->getValue());
2400 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2401 SVOffset, isVolatile, Alignment);
2402 // The scalarized value type may not be legal, e.g. it might require
2403 // promotion or expansion. Relegalize the scalar store.
2404 Result = LegalizeOp(Result);
2407 SplitVectorOp(ST->getValue(), Lo, Hi);
2408 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
2409 MVT::getSizeInBits(EVT)/8;
2412 ExpandOp(ST->getValue(), Lo, Hi);
2413 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2415 if (TLI.isBigEndian())
2419 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2420 SVOffset, isVolatile, Alignment);
2422 if (Hi.Val == NULL) {
2423 // Must be int <-> float one-to-one expansion.
2428 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2429 DAG.getIntPtrConstant(IncrementSize));
2430 assert(isTypeLegal(Tmp2.getValueType()) &&
2431 "Pointers must be legal!");
2432 SVOffset += IncrementSize;
2433 Alignment = MinAlign(Alignment, IncrementSize);
2434 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2435 SVOffset, isVolatile, Alignment);
2436 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2440 switch (getTypeAction(ST->getValue().getValueType())) {
2442 Tmp3 = LegalizeOp(ST->getValue());
2445 // We can promote the value, the truncstore will still take care of it.
2446 Tmp3 = PromoteOp(ST->getValue());
2449 // Just store the low part. This may become a non-trunc store, so make
2450 // sure to use getTruncStore, not UpdateNodeOperands below.
2451 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2452 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2453 SVOffset, MVT::i8, isVolatile, Alignment);
2456 MVT::ValueType StVT = ST->getMemoryVT();
2457 unsigned StWidth = MVT::getSizeInBits(StVT);
2459 if (StWidth != MVT::getStoreSizeInBits(StVT)) {
2460 // Promote to a byte-sized store with upper bits zero if not
2461 // storing an integral number of bytes. For example, promote
2462 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2463 MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT));
2464 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2465 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2466 SVOffset, NVT, isVolatile, Alignment);
2467 } else if (StWidth & (StWidth - 1)) {
2468 // If not storing a power-of-2 number of bits, expand as two stores.
2469 assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) &&
2470 "Unsupported truncstore!");
2471 unsigned RoundWidth = 1 << Log2_32(StWidth);
2472 assert(RoundWidth < StWidth);
2473 unsigned ExtraWidth = StWidth - RoundWidth;
2474 assert(ExtraWidth < RoundWidth);
2475 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2476 "Store size not an integral number of bytes!");
2477 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
2478 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
2480 unsigned IncrementSize;
2482 if (TLI.isLittleEndian()) {
2483 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2484 // Store the bottom RoundWidth bits.
2485 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2487 isVolatile, Alignment);
2489 // Store the remaining ExtraWidth bits.
2490 IncrementSize = RoundWidth / 8;
2491 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2492 DAG.getIntPtrConstant(IncrementSize));
2493 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2494 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2495 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2496 SVOffset + IncrementSize, ExtraVT, isVolatile,
2497 MinAlign(Alignment, IncrementSize));
2499 // Big endian - avoid unaligned stores.
2500 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2501 // Store the top RoundWidth bits.
2502 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2503 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2504 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2505 RoundVT, isVolatile, Alignment);
2507 // Store the remaining ExtraWidth bits.
2508 IncrementSize = RoundWidth / 8;
2509 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2510 DAG.getIntPtrConstant(IncrementSize));
2511 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2512 SVOffset + IncrementSize, ExtraVT, isVolatile,
2513 MinAlign(Alignment, IncrementSize));
2516 // The order of the stores doesn't matter.
2517 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2519 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2520 Tmp2 != ST->getBasePtr())
2521 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2524 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2525 default: assert(0 && "This action is not supported yet!");
2526 case TargetLowering::Legal:
2527 // If this is an unaligned store and the target doesn't support it,
2529 if (!TLI.allowsUnalignedMemoryAccesses()) {
2530 unsigned ABIAlignment = TLI.getTargetData()->
2531 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2532 if (ST->getAlignment() < ABIAlignment)
2533 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2537 case TargetLowering::Custom:
2538 Result = TLI.LowerOperation(Result, DAG);
2541 // TRUNCSTORE:i16 i32 -> STORE i16
2542 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2543 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2544 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2545 isVolatile, Alignment);
2553 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2554 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2556 case ISD::STACKSAVE:
2557 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2558 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2559 Tmp1 = Result.getValue(0);
2560 Tmp2 = Result.getValue(1);
2562 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2563 default: assert(0 && "This action is not supported yet!");
2564 case TargetLowering::Legal: break;
2565 case TargetLowering::Custom:
2566 Tmp3 = TLI.LowerOperation(Result, DAG);
2568 Tmp1 = LegalizeOp(Tmp3);
2569 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2572 case TargetLowering::Expand:
2573 // Expand to CopyFromReg if the target set
2574 // StackPointerRegisterToSaveRestore.
2575 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2576 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2577 Node->getValueType(0));
2578 Tmp2 = Tmp1.getValue(1);
2580 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2581 Tmp2 = Node->getOperand(0);
2586 // Since stacksave produce two values, make sure to remember that we
2587 // legalized both of them.
2588 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2589 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2590 return Op.ResNo ? Tmp2 : Tmp1;
2592 case ISD::STACKRESTORE:
2593 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2594 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2595 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2597 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2598 default: assert(0 && "This action is not supported yet!");
2599 case TargetLowering::Legal: break;
2600 case TargetLowering::Custom:
2601 Tmp1 = TLI.LowerOperation(Result, DAG);
2602 if (Tmp1.Val) Result = Tmp1;
2604 case TargetLowering::Expand:
2605 // Expand to CopyToReg if the target set
2606 // StackPointerRegisterToSaveRestore.
2607 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2608 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2616 case ISD::READCYCLECOUNTER:
2617 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2618 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2619 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2620 Node->getValueType(0))) {
2621 default: assert(0 && "This action is not supported yet!");
2622 case TargetLowering::Legal:
2623 Tmp1 = Result.getValue(0);
2624 Tmp2 = Result.getValue(1);
2626 case TargetLowering::Custom:
2627 Result = TLI.LowerOperation(Result, DAG);
2628 Tmp1 = LegalizeOp(Result.getValue(0));
2629 Tmp2 = LegalizeOp(Result.getValue(1));
2633 // Since rdcc produce two values, make sure to remember that we legalized
2635 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2636 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2640 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2641 case Expand: assert(0 && "It's impossible to expand bools");
2643 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2646 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2647 // Make sure the condition is either zero or one.
2648 if (!DAG.MaskedValueIsZero(Tmp1,
2649 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2650 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2653 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2654 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2656 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2658 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2659 default: assert(0 && "This action is not supported yet!");
2660 case TargetLowering::Legal: break;
2661 case TargetLowering::Custom: {
2662 Tmp1 = TLI.LowerOperation(Result, DAG);
2663 if (Tmp1.Val) Result = Tmp1;
2666 case TargetLowering::Expand:
2667 if (Tmp1.getOpcode() == ISD::SETCC) {
2668 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2670 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2672 Result = DAG.getSelectCC(Tmp1,
2673 DAG.getConstant(0, Tmp1.getValueType()),
2674 Tmp2, Tmp3, ISD::SETNE);
2677 case TargetLowering::Promote: {
2678 MVT::ValueType NVT =
2679 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2680 unsigned ExtOp, TruncOp;
2681 if (MVT::isVector(Tmp2.getValueType())) {
2682 ExtOp = ISD::BIT_CONVERT;
2683 TruncOp = ISD::BIT_CONVERT;
2684 } else if (MVT::isInteger(Tmp2.getValueType())) {
2685 ExtOp = ISD::ANY_EXTEND;
2686 TruncOp = ISD::TRUNCATE;
2688 ExtOp = ISD::FP_EXTEND;
2689 TruncOp = ISD::FP_ROUND;
2691 // Promote each of the values to the new type.
2692 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2693 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2694 // Perform the larger operation, then round down.
2695 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2696 if (TruncOp != ISD::FP_ROUND)
2697 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2699 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2700 DAG.getIntPtrConstant(0));
2705 case ISD::SELECT_CC: {
2706 Tmp1 = Node->getOperand(0); // LHS
2707 Tmp2 = Node->getOperand(1); // RHS
2708 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2709 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2710 SDOperand CC = Node->getOperand(4);
2712 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2714 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2715 // the LHS is a legal SETCC itself. In this case, we need to compare
2716 // the result against zero to select between true and false values.
2717 if (Tmp2.Val == 0) {
2718 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2719 CC = DAG.getCondCode(ISD::SETNE);
2721 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2723 // Everything is legal, see if we should expand this op or something.
2724 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2725 default: assert(0 && "This action is not supported yet!");
2726 case TargetLowering::Legal: break;
2727 case TargetLowering::Custom:
2728 Tmp1 = TLI.LowerOperation(Result, DAG);
2729 if (Tmp1.Val) Result = Tmp1;
2735 Tmp1 = Node->getOperand(0);
2736 Tmp2 = Node->getOperand(1);
2737 Tmp3 = Node->getOperand(2);
2738 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2740 // If we had to Expand the SetCC operands into a SELECT node, then it may
2741 // not always be possible to return a true LHS & RHS. In this case, just
2742 // return the value we legalized, returned in the LHS
2743 if (Tmp2.Val == 0) {
2748 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2749 default: assert(0 && "Cannot handle this action for SETCC yet!");
2750 case TargetLowering::Custom:
2753 case TargetLowering::Legal:
2754 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2756 Tmp4 = TLI.LowerOperation(Result, DAG);
2757 if (Tmp4.Val) Result = Tmp4;
2760 case TargetLowering::Promote: {
2761 // First step, figure out the appropriate operation to use.
2762 // Allow SETCC to not be supported for all legal data types
2763 // Mostly this targets FP
2764 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2765 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2767 // Scan for the appropriate larger type to use.
2769 NewInTy = (MVT::ValueType)(NewInTy+1);
2771 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2772 "Fell off of the edge of the integer world");
2773 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2774 "Fell off of the edge of the floating point world");
2776 // If the target supports SETCC of this type, use it.
2777 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2780 if (MVT::isInteger(NewInTy))
2781 assert(0 && "Cannot promote Legal Integer SETCC yet");
2783 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2784 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2786 Tmp1 = LegalizeOp(Tmp1);
2787 Tmp2 = LegalizeOp(Tmp2);
2788 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2789 Result = LegalizeOp(Result);
2792 case TargetLowering::Expand:
2793 // Expand a setcc node into a select_cc of the same condition, lhs, and
2794 // rhs that selects between const 1 (true) and const 0 (false).
2795 MVT::ValueType VT = Node->getValueType(0);
2796 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2797 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2804 case ISD::MEMMOVE: {
2805 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2806 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2808 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2809 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2810 case Expand: assert(0 && "Cannot expand a byte!");
2812 Tmp3 = LegalizeOp(Node->getOperand(2));
2815 Tmp3 = PromoteOp(Node->getOperand(2));
2819 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2823 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2825 // Length is too big, just take the lo-part of the length.
2827 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2831 Tmp4 = LegalizeOp(Node->getOperand(3));
2834 Tmp4 = PromoteOp(Node->getOperand(3));
2839 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2840 case Expand: assert(0 && "Cannot expand this yet!");
2842 Tmp5 = LegalizeOp(Node->getOperand(4));
2845 Tmp5 = PromoteOp(Node->getOperand(4));
2850 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool
2851 case Expand: assert(0 && "Cannot expand this yet!");
2853 Tmp6 = LegalizeOp(Node->getOperand(5));
2856 Tmp6 = PromoteOp(Node->getOperand(5));
2860 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2861 default: assert(0 && "This action not implemented for this operation!");
2862 case TargetLowering::Custom:
2865 case TargetLowering::Legal: {
2866 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 };
2867 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
2869 Tmp1 = TLI.LowerOperation(Result, DAG);
2870 if (Tmp1.Val) Result = Tmp1;
2874 case TargetLowering::Expand: {
2875 // Otherwise, the target does not support this operation. Lower the
2876 // operation to an explicit libcall as appropriate.
2877 MVT::ValueType IntPtr = TLI.getPointerTy();
2878 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2879 TargetLowering::ArgListTy Args;
2880 TargetLowering::ArgListEntry Entry;
2882 const char *FnName = 0;
2883 if (Node->getOpcode() == ISD::MEMSET) {
2884 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2885 Args.push_back(Entry);
2886 // Extend the (previously legalized) ubyte argument to be an int value
2888 if (Tmp3.getValueType() > MVT::i32)
2889 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2891 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2892 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2893 Args.push_back(Entry);
2894 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2895 Args.push_back(Entry);
2898 } else if (Node->getOpcode() == ISD::MEMCPY ||
2899 Node->getOpcode() == ISD::MEMMOVE) {
2900 Entry.Ty = IntPtrTy;
2901 Entry.Node = Tmp2; Args.push_back(Entry);
2902 Entry.Node = Tmp3; Args.push_back(Entry);
2903 Entry.Node = Tmp4; Args.push_back(Entry);
2904 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2906 assert(0 && "Unknown op!");
2909 std::pair<SDOperand,SDOperand> CallResult =
2910 TLI.LowerCallTo(Tmp1, Type::VoidTy,
2911 false, false, false, CallingConv::C, false,
2912 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2913 Result = CallResult.second;
2920 case ISD::SHL_PARTS:
2921 case ISD::SRA_PARTS:
2922 case ISD::SRL_PARTS: {
2923 SmallVector<SDOperand, 8> Ops;
2924 bool Changed = false;
2925 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2926 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2927 Changed |= Ops.back() != Node->getOperand(i);
2930 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2932 switch (TLI.getOperationAction(Node->getOpcode(),
2933 Node->getValueType(0))) {
2934 default: assert(0 && "This action is not supported yet!");
2935 case TargetLowering::Legal: break;
2936 case TargetLowering::Custom:
2937 Tmp1 = TLI.LowerOperation(Result, DAG);
2939 SDOperand Tmp2, RetVal(0, 0);
2940 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2941 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2942 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2946 assert(RetVal.Val && "Illegal result number");
2952 // Since these produce multiple values, make sure to remember that we
2953 // legalized all of them.
2954 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2955 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2956 return Result.getValue(Op.ResNo);
2978 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2979 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2980 case Expand: assert(0 && "Not possible");
2982 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2985 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2989 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2991 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2992 default: assert(0 && "BinOp legalize operation not supported");
2993 case TargetLowering::Legal: break;
2994 case TargetLowering::Custom:
2995 Tmp1 = TLI.LowerOperation(Result, DAG);
2996 if (Tmp1.Val) Result = Tmp1;
2998 case TargetLowering::Expand: {
2999 MVT::ValueType VT = Op.getValueType();
3001 // See if multiply or divide can be lowered using two-result operations.
3002 SDVTList VTs = DAG.getVTList(VT, VT);
3003 if (Node->getOpcode() == ISD::MUL) {
3004 // We just need the low half of the multiply; try both the signed
3005 // and unsigned forms. If the target supports both SMUL_LOHI and
3006 // UMUL_LOHI, form a preference by checking which forms of plain
3007 // MULH it supports.
3008 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
3009 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
3010 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
3011 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
3012 unsigned OpToUse = 0;
3013 if (HasSMUL_LOHI && !HasMULHS) {
3014 OpToUse = ISD::SMUL_LOHI;
3015 } else if (HasUMUL_LOHI && !HasMULHU) {
3016 OpToUse = ISD::UMUL_LOHI;
3017 } else if (HasSMUL_LOHI) {
3018 OpToUse = ISD::SMUL_LOHI;
3019 } else if (HasUMUL_LOHI) {
3020 OpToUse = ISD::UMUL_LOHI;
3023 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
3027 if (Node->getOpcode() == ISD::MULHS &&
3028 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3029 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3032 if (Node->getOpcode() == ISD::MULHU &&
3033 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3034 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3037 if (Node->getOpcode() == ISD::SDIV &&
3038 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3039 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3042 if (Node->getOpcode() == ISD::UDIV &&
3043 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3044 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3048 // Check to see if we have a libcall for this operator.
3049 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3050 bool isSigned = false;
3051 switch (Node->getOpcode()) {
3054 if (VT == MVT::i32) {
3055 LC = Node->getOpcode() == ISD::UDIV
3056 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3057 isSigned = Node->getOpcode() == ISD::SDIV;
3061 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3062 RTLIB::POW_PPCF128);
3066 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3068 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3072 assert(MVT::isVector(Node->getValueType(0)) &&
3073 "Cannot expand this binary operator!");
3074 // Expand the operation into a bunch of nasty scalar code.
3075 Result = LegalizeOp(UnrollVectorOp(Op));
3078 case TargetLowering::Promote: {
3079 switch (Node->getOpcode()) {
3080 default: assert(0 && "Do not know how to promote this BinOp!");
3084 MVT::ValueType OVT = Node->getValueType(0);
3085 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3086 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
3087 // Bit convert each of the values to the new type.
3088 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3089 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3090 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3091 // Bit convert the result back the original type.
3092 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3100 case ISD::SMUL_LOHI:
3101 case ISD::UMUL_LOHI:
3104 // These nodes will only be produced by target-specific lowering, so
3105 // they shouldn't be here if they aren't legal.
3106 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3107 "This must be legal!");
3109 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3110 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3111 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3114 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3115 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3116 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3117 case Expand: assert(0 && "Not possible");
3119 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3122 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3126 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3128 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3129 default: assert(0 && "Operation not supported");
3130 case TargetLowering::Custom:
3131 Tmp1 = TLI.LowerOperation(Result, DAG);
3132 if (Tmp1.Val) Result = Tmp1;
3134 case TargetLowering::Legal: break;
3135 case TargetLowering::Expand: {
3136 // If this target supports fabs/fneg natively and select is cheap,
3137 // do this efficiently.
3138 if (!TLI.isSelectExpensive() &&
3139 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3140 TargetLowering::Legal &&
3141 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3142 TargetLowering::Legal) {
3143 // Get the sign bit of the RHS.
3144 MVT::ValueType IVT =
3145 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3146 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3147 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
3148 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3149 // Get the absolute value of the result.
3150 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3151 // Select between the nabs and abs value based on the sign bit of
3153 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3154 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3157 Result = LegalizeOp(Result);
3161 // Otherwise, do bitwise ops!
3162 MVT::ValueType NVT =
3163 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3164 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3165 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3166 Result = LegalizeOp(Result);
3174 Tmp1 = LegalizeOp(Node->getOperand(0));
3175 Tmp2 = LegalizeOp(Node->getOperand(1));
3176 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3177 // Since this produces two values, make sure to remember that we legalized
3179 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3180 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3185 Tmp1 = LegalizeOp(Node->getOperand(0));
3186 Tmp2 = LegalizeOp(Node->getOperand(1));
3187 Tmp3 = LegalizeOp(Node->getOperand(2));
3188 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3189 // Since this produces two values, make sure to remember that we legalized
3191 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3192 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3195 case ISD::BUILD_PAIR: {
3196 MVT::ValueType PairTy = Node->getValueType(0);
3197 // TODO: handle the case where the Lo and Hi operands are not of legal type
3198 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3199 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3200 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3201 case TargetLowering::Promote:
3202 case TargetLowering::Custom:
3203 assert(0 && "Cannot promote/custom this yet!");
3204 case TargetLowering::Legal:
3205 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3206 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3208 case TargetLowering::Expand:
3209 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3210 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3211 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3212 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
3213 TLI.getShiftAmountTy()));
3214 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3223 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3224 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3226 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3227 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3228 case TargetLowering::Custom:
3231 case TargetLowering::Legal:
3232 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3234 Tmp1 = TLI.LowerOperation(Result, DAG);
3235 if (Tmp1.Val) Result = Tmp1;
3238 case TargetLowering::Expand: {
3239 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3240 bool isSigned = DivOpc == ISD::SDIV;
3241 MVT::ValueType VT = Node->getValueType(0);
3243 // See if remainder can be lowered using two-result operations.
3244 SDVTList VTs = DAG.getVTList(VT, VT);
3245 if (Node->getOpcode() == ISD::SREM &&
3246 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3247 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3250 if (Node->getOpcode() == ISD::UREM &&
3251 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3252 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3256 if (MVT::isInteger(VT)) {
3257 if (TLI.getOperationAction(DivOpc, VT) ==
3258 TargetLowering::Legal) {
3260 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3261 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3262 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3263 } else if (MVT::isVector(VT)) {
3264 Result = LegalizeOp(UnrollVectorOp(Op));
3266 assert(VT == MVT::i32 &&
3267 "Cannot expand this binary operator!");
3268 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3269 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3271 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3274 assert(MVT::isFloatingPoint(VT) &&
3275 "remainder op must have integer or floating-point type");
3276 if (MVT::isVector(VT)) {
3277 Result = LegalizeOp(UnrollVectorOp(Op));
3279 // Floating point mod -> fmod libcall.
3280 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3281 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3283 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3284 false/*sign irrelevant*/, Dummy);
3292 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3293 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3295 MVT::ValueType VT = Node->getValueType(0);
3296 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3297 default: assert(0 && "This action is not supported yet!");
3298 case TargetLowering::Custom:
3301 case TargetLowering::Legal:
3302 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3303 Result = Result.getValue(0);
3304 Tmp1 = Result.getValue(1);
3307 Tmp2 = TLI.LowerOperation(Result, DAG);
3309 Result = LegalizeOp(Tmp2);
3310 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3314 case TargetLowering::Expand: {
3315 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3316 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3317 // Increment the pointer, VAList, to the next vaarg
3318 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3319 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3320 TLI.getPointerTy()));
3321 // Store the incremented VAList to the legalized pointer
3322 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3323 // Load the actual argument out of the pointer VAList
3324 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3325 Tmp1 = LegalizeOp(Result.getValue(1));
3326 Result = LegalizeOp(Result);
3330 // Since VAARG produces two values, make sure to remember that we
3331 // legalized both of them.
3332 AddLegalizedOperand(SDOperand(Node, 0), Result);
3333 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3334 return Op.ResNo ? Tmp1 : Result;
3338 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3339 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3340 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3342 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3343 default: assert(0 && "This action is not supported yet!");
3344 case TargetLowering::Custom:
3347 case TargetLowering::Legal:
3348 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3349 Node->getOperand(3), Node->getOperand(4));
3351 Tmp1 = TLI.LowerOperation(Result, DAG);
3352 if (Tmp1.Val) Result = Tmp1;
3355 case TargetLowering::Expand:
3356 // This defaults to loading a pointer from the input and storing it to the
3357 // output, returning the chain.
3358 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3359 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3360 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VD, 0);
3361 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VS, 0);
3367 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3368 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3370 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3371 default: assert(0 && "This action is not supported yet!");
3372 case TargetLowering::Custom:
3375 case TargetLowering::Legal:
3376 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3378 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3379 if (Tmp1.Val) Result = Tmp1;
3382 case TargetLowering::Expand:
3383 Result = Tmp1; // Default to a no-op, return the chain
3389 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3390 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3392 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3394 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3395 default: assert(0 && "This action is not supported yet!");
3396 case TargetLowering::Legal: break;
3397 case TargetLowering::Custom:
3398 Tmp1 = TLI.LowerOperation(Result, DAG);
3399 if (Tmp1.Val) Result = Tmp1;
3406 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3407 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3408 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3409 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3411 assert(0 && "ROTL/ROTR legalize operation not supported");
3413 case TargetLowering::Legal:
3415 case TargetLowering::Custom:
3416 Tmp1 = TLI.LowerOperation(Result, DAG);
3417 if (Tmp1.Val) Result = Tmp1;
3419 case TargetLowering::Promote:
3420 assert(0 && "Do not know how to promote ROTL/ROTR");
3422 case TargetLowering::Expand:
3423 assert(0 && "Do not know how to expand ROTL/ROTR");
3429 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3430 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3431 case TargetLowering::Custom:
3432 assert(0 && "Cannot custom legalize this yet!");
3433 case TargetLowering::Legal:
3434 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3436 case TargetLowering::Promote: {
3437 MVT::ValueType OVT = Tmp1.getValueType();
3438 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3439 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
3441 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3442 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3443 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3444 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3447 case TargetLowering::Expand:
3448 Result = ExpandBSWAP(Tmp1);
3456 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3457 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3458 case TargetLowering::Custom:
3459 case TargetLowering::Legal:
3460 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3461 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3462 TargetLowering::Custom) {
3463 Tmp1 = TLI.LowerOperation(Result, DAG);
3469 case TargetLowering::Promote: {
3470 MVT::ValueType OVT = Tmp1.getValueType();
3471 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3473 // Zero extend the argument.
3474 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3475 // Perform the larger operation, then subtract if needed.
3476 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3477 switch (Node->getOpcode()) {
3482 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3483 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3484 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3486 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3487 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
3490 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3491 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3492 DAG.getConstant(MVT::getSizeInBits(NVT) -
3493 MVT::getSizeInBits(OVT), NVT));
3498 case TargetLowering::Expand:
3499 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3510 Tmp1 = LegalizeOp(Node->getOperand(0));
3511 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3512 case TargetLowering::Promote:
3513 case TargetLowering::Custom:
3516 case TargetLowering::Legal:
3517 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3519 Tmp1 = TLI.LowerOperation(Result, DAG);
3520 if (Tmp1.Val) Result = Tmp1;
3523 case TargetLowering::Expand:
3524 switch (Node->getOpcode()) {
3525 default: assert(0 && "Unreachable!");
3527 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3528 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3529 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3532 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3533 MVT::ValueType VT = Node->getValueType(0);
3534 Tmp2 = DAG.getConstantFP(0.0, VT);
3535 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
3536 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3537 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3543 MVT::ValueType VT = Node->getValueType(0);
3545 // Expand unsupported unary vector operators by unrolling them.
3546 if (MVT::isVector(VT)) {
3547 Result = LegalizeOp(UnrollVectorOp(Op));
3551 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3552 switch(Node->getOpcode()) {
3554 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3555 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3558 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3559 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3562 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3563 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3565 default: assert(0 && "Unreachable!");
3568 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3569 false/*sign irrelevant*/, Dummy);
3577 MVT::ValueType VT = Node->getValueType(0);
3579 // Expand unsupported unary vector operators by unrolling them.
3580 if (MVT::isVector(VT)) {
3581 Result = LegalizeOp(UnrollVectorOp(Op));
3585 // We always lower FPOWI into a libcall. No target support for it yet.
3586 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3587 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3589 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3590 false/*sign irrelevant*/, Dummy);
3593 case ISD::BIT_CONVERT:
3594 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3595 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3596 Node->getValueType(0));
3597 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3598 // The input has to be a vector type, we have to either scalarize it, pack
3599 // it, or convert it based on whether the input vector type is legal.
3600 SDNode *InVal = Node->getOperand(0).Val;
3601 int InIx = Node->getOperand(0).ResNo;
3602 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
3603 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
3605 // Figure out if there is a simple type corresponding to this Vector
3606 // type. If so, convert to the vector type.
3607 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3608 if (TLI.isTypeLegal(TVT)) {
3609 // Turn this into a bit convert of the vector input.
3610 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3611 LegalizeOp(Node->getOperand(0)));
3613 } else if (NumElems == 1) {
3614 // Turn this into a bit convert of the scalar input.
3615 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3616 ScalarizeVectorOp(Node->getOperand(0)));
3619 // FIXME: UNIMP! Store then reload
3620 assert(0 && "Cast from unsupported vector type not implemented yet!");
3623 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3624 Node->getOperand(0).getValueType())) {
3625 default: assert(0 && "Unknown operation action!");
3626 case TargetLowering::Expand:
3627 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3628 Node->getValueType(0));
3630 case TargetLowering::Legal:
3631 Tmp1 = LegalizeOp(Node->getOperand(0));
3632 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3638 // Conversion operators. The source and destination have different types.
3639 case ISD::SINT_TO_FP:
3640 case ISD::UINT_TO_FP: {
3641 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3642 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3644 switch (TLI.getOperationAction(Node->getOpcode(),
3645 Node->getOperand(0).getValueType())) {
3646 default: assert(0 && "Unknown operation action!");
3647 case TargetLowering::Custom:
3650 case TargetLowering::Legal:
3651 Tmp1 = LegalizeOp(Node->getOperand(0));
3652 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3654 Tmp1 = TLI.LowerOperation(Result, DAG);
3655 if (Tmp1.Val) Result = Tmp1;
3658 case TargetLowering::Expand:
3659 Result = ExpandLegalINT_TO_FP(isSigned,
3660 LegalizeOp(Node->getOperand(0)),
3661 Node->getValueType(0));
3663 case TargetLowering::Promote:
3664 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3665 Node->getValueType(0),
3671 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3672 Node->getValueType(0), Node->getOperand(0));
3675 Tmp1 = PromoteOp(Node->getOperand(0));
3677 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3678 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3680 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3681 Node->getOperand(0).getValueType());
3683 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3684 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3690 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3692 Tmp1 = LegalizeOp(Node->getOperand(0));
3693 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3696 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3698 // Since the result is legal, we should just be able to truncate the low
3699 // part of the source.
3700 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3703 Result = PromoteOp(Node->getOperand(0));
3704 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3709 case ISD::FP_TO_SINT:
3710 case ISD::FP_TO_UINT:
3711 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3713 Tmp1 = LegalizeOp(Node->getOperand(0));
3715 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3716 default: assert(0 && "Unknown operation action!");
3717 case TargetLowering::Custom:
3720 case TargetLowering::Legal:
3721 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3723 Tmp1 = TLI.LowerOperation(Result, DAG);
3724 if (Tmp1.Val) Result = Tmp1;
3727 case TargetLowering::Promote:
3728 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3729 Node->getOpcode() == ISD::FP_TO_SINT);
3731 case TargetLowering::Expand:
3732 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3733 SDOperand True, False;
3734 MVT::ValueType VT = Node->getOperand(0).getValueType();
3735 MVT::ValueType NVT = Node->getValueType(0);
3736 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1;
3737 const uint64_t zero[] = {0, 0};
3738 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3739 uint64_t x = 1ULL << ShiftAmt;
3740 (void)apf.convertFromZeroExtendedInteger
3741 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven);
3742 Tmp2 = DAG.getConstantFP(apf, VT);
3743 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3744 Node->getOperand(0), Tmp2, ISD::SETLT);
3745 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3746 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3747 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3749 False = DAG.getNode(ISD::XOR, NVT, False,
3750 DAG.getConstant(1ULL << ShiftAmt, NVT));
3751 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3754 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3760 MVT::ValueType VT = Op.getValueType();
3761 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3762 // Convert ppcf128 to i32
3763 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3764 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3765 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3766 Node->getOperand(0), DAG.getValueType(MVT::f64));
3767 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3768 DAG.getIntPtrConstant(1));
3769 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3771 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3772 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3773 Tmp2 = DAG.getConstantFP(apf, OVT);
3774 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3775 // FIXME: generated code sucks.
3776 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3777 DAG.getNode(ISD::ADD, MVT::i32,
3778 DAG.getNode(ISD::FP_TO_SINT, VT,
3779 DAG.getNode(ISD::FSUB, OVT,
3780 Node->getOperand(0), Tmp2)),
3781 DAG.getConstant(0x80000000, MVT::i32)),
3782 DAG.getNode(ISD::FP_TO_SINT, VT,
3783 Node->getOperand(0)),
3784 DAG.getCondCode(ISD::SETGE));
3788 // Convert f32 / f64 to i32 / i64.
3789 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3790 switch (Node->getOpcode()) {
3791 case ISD::FP_TO_SINT: {
3792 if (OVT == MVT::f32)
3793 LC = (VT == MVT::i32)
3794 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3795 else if (OVT == MVT::f64)
3796 LC = (VT == MVT::i32)
3797 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3798 else if (OVT == MVT::f80) {
3799 assert(VT == MVT::i64);
3800 LC = RTLIB::FPTOSINT_F80_I64;
3802 else if (OVT == MVT::ppcf128) {
3803 assert(VT == MVT::i64);
3804 LC = RTLIB::FPTOSINT_PPCF128_I64;
3808 case ISD::FP_TO_UINT: {
3809 if (OVT == MVT::f32)
3810 LC = (VT == MVT::i32)
3811 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3812 else if (OVT == MVT::f64)
3813 LC = (VT == MVT::i32)
3814 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3815 else if (OVT == MVT::f80) {
3816 LC = (VT == MVT::i32)
3817 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64;
3819 else if (OVT == MVT::ppcf128) {
3820 assert(VT == MVT::i64);
3821 LC = RTLIB::FPTOUINT_PPCF128_I64;
3825 default: assert(0 && "Unreachable!");
3828 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3829 false/*sign irrelevant*/, Dummy);
3833 Tmp1 = PromoteOp(Node->getOperand(0));
3834 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3835 Result = LegalizeOp(Result);
3840 case ISD::FP_EXTEND: {
3841 MVT::ValueType DstVT = Op.getValueType();
3842 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3843 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3844 // The only other way we can lower this is to turn it into a STORE,
3845 // LOAD pair, targetting a temporary location (a stack slot).
3846 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3849 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3850 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3852 Tmp1 = LegalizeOp(Node->getOperand(0));
3853 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3856 Tmp1 = PromoteOp(Node->getOperand(0));
3857 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3862 case ISD::FP_ROUND: {
3863 MVT::ValueType DstVT = Op.getValueType();
3864 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3865 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3866 if (SrcVT == MVT::ppcf128) {
3868 ExpandOp(Node->getOperand(0), Lo, Result);
3869 // Round it the rest of the way (e.g. to f32) if needed.
3870 if (DstVT!=MVT::f64)
3871 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3874 // The only other way we can lower this is to turn it into a STORE,
3875 // LOAD pair, targetting a temporary location (a stack slot).
3876 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3879 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3880 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3882 Tmp1 = LegalizeOp(Node->getOperand(0));
3883 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3886 Tmp1 = PromoteOp(Node->getOperand(0));
3887 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3888 Node->getOperand(1));
3893 case ISD::ANY_EXTEND:
3894 case ISD::ZERO_EXTEND:
3895 case ISD::SIGN_EXTEND:
3896 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3897 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3899 Tmp1 = LegalizeOp(Node->getOperand(0));
3900 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3901 TargetLowering::Custom) {
3902 Tmp2 = TLI.LowerOperation(Result, DAG);
3907 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3910 switch (Node->getOpcode()) {
3911 case ISD::ANY_EXTEND:
3912 Tmp1 = PromoteOp(Node->getOperand(0));
3913 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3915 case ISD::ZERO_EXTEND:
3916 Result = PromoteOp(Node->getOperand(0));
3917 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3918 Result = DAG.getZeroExtendInReg(Result,
3919 Node->getOperand(0).getValueType());
3921 case ISD::SIGN_EXTEND:
3922 Result = PromoteOp(Node->getOperand(0));
3923 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3924 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3926 DAG.getValueType(Node->getOperand(0).getValueType()));
3931 case ISD::FP_ROUND_INREG:
3932 case ISD::SIGN_EXTEND_INREG: {
3933 Tmp1 = LegalizeOp(Node->getOperand(0));
3934 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3936 // If this operation is not supported, convert it to a shl/shr or load/store
3938 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3939 default: assert(0 && "This action not supported for this op yet!");
3940 case TargetLowering::Legal:
3941 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3943 case TargetLowering::Expand:
3944 // If this is an integer extend and shifts are supported, do that.
3945 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3946 // NOTE: we could fall back on load/store here too for targets without
3947 // SAR. However, it is doubtful that any exist.
3948 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3949 MVT::getSizeInBits(ExtraVT);
3950 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3951 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3952 Node->getOperand(0), ShiftCst);
3953 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3955 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3956 // The only way we can lower this is to turn it into a TRUNCSTORE,
3957 // EXTLOAD pair, targetting a temporary location (a stack slot).
3959 // NOTE: there is a choice here between constantly creating new stack
3960 // slots and always reusing the same one. We currently always create
3961 // new ones, as reuse may inhibit scheduling.
3962 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3963 Node->getValueType(0));
3965 assert(0 && "Unknown op");
3971 case ISD::TRAMPOLINE: {
3973 for (unsigned i = 0; i != 6; ++i)
3974 Ops[i] = LegalizeOp(Node->getOperand(i));
3975 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3976 // The only option for this node is to custom lower it.
3977 Result = TLI.LowerOperation(Result, DAG);
3978 assert(Result.Val && "Should always custom lower!");
3980 // Since trampoline produces two values, make sure to remember that we
3981 // legalized both of them.
3982 Tmp1 = LegalizeOp(Result.getValue(1));
3983 Result = LegalizeOp(Result);
3984 AddLegalizedOperand(SDOperand(Node, 0), Result);
3985 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3986 return Op.ResNo ? Tmp1 : Result;
3988 case ISD::FLT_ROUNDS_: {
3989 MVT::ValueType VT = Node->getValueType(0);
3990 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3991 default: assert(0 && "This action not supported for this op yet!");
3992 case TargetLowering::Custom:
3993 Result = TLI.LowerOperation(Op, DAG);
3994 if (Result.Val) break;
3996 case TargetLowering::Legal:
3997 // If this operation is not supported, lower it to constant 1
3998 Result = DAG.getConstant(1, VT);
4003 MVT::ValueType VT = Node->getValueType(0);
4004 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4005 default: assert(0 && "This action not supported for this op yet!");
4006 case TargetLowering::Legal:
4007 Tmp1 = LegalizeOp(Node->getOperand(0));
4008 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4010 case TargetLowering::Custom:
4011 Result = TLI.LowerOperation(Op, DAG);
4012 if (Result.Val) break;
4014 case TargetLowering::Expand:
4015 // If this operation is not supported, lower it to 'abort()' call
4016 Tmp1 = LegalizeOp(Node->getOperand(0));
4017 TargetLowering::ArgListTy Args;
4018 std::pair<SDOperand,SDOperand> CallResult =
4019 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4020 false, false, false, CallingConv::C, false,
4021 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4023 Result = CallResult.second;
4030 assert(Result.getValueType() == Op.getValueType() &&
4031 "Bad legalization!");
4033 // Make sure that the generated code is itself legal.
4035 Result = LegalizeOp(Result);
4037 // Note that LegalizeOp may be reentered even from single-use nodes, which
4038 // means that we always must cache transformed nodes.
4039 AddLegalizedOperand(Op, Result);
4043 /// PromoteOp - Given an operation that produces a value in an invalid type,
4044 /// promote it to compute the value into a larger type. The produced value will
4045 /// have the correct bits for the low portion of the register, but no guarantee
4046 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4047 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
4048 MVT::ValueType VT = Op.getValueType();
4049 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4050 assert(getTypeAction(VT) == Promote &&
4051 "Caller should expand or legalize operands that are not promotable!");
4052 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
4053 "Cannot promote to smaller type!");
4055 SDOperand Tmp1, Tmp2, Tmp3;
4057 SDNode *Node = Op.Val;
4059 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
4060 if (I != PromotedNodes.end()) return I->second;
4062 switch (Node->getOpcode()) {
4063 case ISD::CopyFromReg:
4064 assert(0 && "CopyFromReg must be legal!");
4067 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4069 assert(0 && "Do not know how to promote this operator!");
4072 Result = DAG.getNode(ISD::UNDEF, NVT);
4076 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4078 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4079 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4081 case ISD::ConstantFP:
4082 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4083 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4087 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
4088 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
4089 Node->getOperand(1), Node->getOperand(2));
4093 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4095 Result = LegalizeOp(Node->getOperand(0));
4096 assert(Result.getValueType() >= NVT &&
4097 "This truncation doesn't make sense!");
4098 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
4099 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4102 // The truncation is not required, because we don't guarantee anything
4103 // about high bits anyway.
4104 Result = PromoteOp(Node->getOperand(0));
4107 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4108 // Truncate the low part of the expanded value to the result type
4109 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4112 case ISD::SIGN_EXTEND:
4113 case ISD::ZERO_EXTEND:
4114 case ISD::ANY_EXTEND:
4115 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4116 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4118 // Input is legal? Just do extend all the way to the larger type.
4119 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4122 // Promote the reg if it's smaller.
4123 Result = PromoteOp(Node->getOperand(0));
4124 // The high bits are not guaranteed to be anything. Insert an extend.
4125 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4126 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4127 DAG.getValueType(Node->getOperand(0).getValueType()));
4128 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4129 Result = DAG.getZeroExtendInReg(Result,
4130 Node->getOperand(0).getValueType());
4134 case ISD::BIT_CONVERT:
4135 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4136 Node->getValueType(0));
4137 Result = PromoteOp(Result);
4140 case ISD::FP_EXTEND:
4141 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4143 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4144 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4145 case Promote: assert(0 && "Unreachable with 2 FP types!");
4147 if (Node->getConstantOperandVal(1) == 0) {
4148 // Input is legal? Do an FP_ROUND_INREG.
4149 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4150 DAG.getValueType(VT));
4152 // Just remove the truncate, it isn't affecting the value.
4153 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4154 Node->getOperand(1));
4159 case ISD::SINT_TO_FP:
4160 case ISD::UINT_TO_FP:
4161 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4163 // No extra round required here.
4164 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4168 Result = PromoteOp(Node->getOperand(0));
4169 if (Node->getOpcode() == ISD::SINT_TO_FP)
4170 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4172 DAG.getValueType(Node->getOperand(0).getValueType()));
4174 Result = DAG.getZeroExtendInReg(Result,
4175 Node->getOperand(0).getValueType());
4176 // No extra round required here.
4177 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4180 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4181 Node->getOperand(0));
4182 // Round if we cannot tolerate excess precision.
4183 if (NoExcessFPPrecision)
4184 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4185 DAG.getValueType(VT));
4190 case ISD::SIGN_EXTEND_INREG:
4191 Result = PromoteOp(Node->getOperand(0));
4192 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4193 Node->getOperand(1));
4195 case ISD::FP_TO_SINT:
4196 case ISD::FP_TO_UINT:
4197 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4200 Tmp1 = Node->getOperand(0);
4203 // The input result is prerounded, so we don't have to do anything
4205 Tmp1 = PromoteOp(Node->getOperand(0));
4208 // If we're promoting a UINT to a larger size, check to see if the new node
4209 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4210 // we can use that instead. This allows us to generate better code for
4211 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4212 // legal, such as PowerPC.
4213 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4214 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4215 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4216 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4217 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4219 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4225 Tmp1 = PromoteOp(Node->getOperand(0));
4226 assert(Tmp1.getValueType() == NVT);
4227 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4228 // NOTE: we do not have to do any extra rounding here for
4229 // NoExcessFPPrecision, because we know the input will have the appropriate
4230 // precision, and these operations don't modify precision at all.
4236 Tmp1 = PromoteOp(Node->getOperand(0));
4237 assert(Tmp1.getValueType() == NVT);
4238 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4239 if (NoExcessFPPrecision)
4240 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4241 DAG.getValueType(VT));
4245 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4246 // directly as well, which may be better.
4247 Tmp1 = PromoteOp(Node->getOperand(0));
4248 assert(Tmp1.getValueType() == NVT);
4249 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4250 if (NoExcessFPPrecision)
4251 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4252 DAG.getValueType(VT));
4256 case ISD::ATOMIC_LCS: {
4257 Tmp2 = PromoteOp(Node->getOperand(2));
4258 Tmp3 = PromoteOp(Node->getOperand(3));
4259 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0),
4260 Node->getOperand(1), Tmp2, Tmp3,
4261 cast<AtomicSDNode>(Node)->getVT());
4262 // Remember that we legalized the chain.
4263 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4266 case ISD::ATOMIC_LAS:
4267 case ISD::ATOMIC_SWAP: {
4268 Tmp2 = PromoteOp(Node->getOperand(2));
4269 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0),
4270 Node->getOperand(1), Tmp2,
4271 cast<AtomicSDNode>(Node)->getVT());
4272 // Remember that we legalized the chain.
4273 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4283 // The input may have strange things in the top bits of the registers, but
4284 // these operations don't care. They may have weird bits going out, but
4285 // that too is okay if they are integer operations.
4286 Tmp1 = PromoteOp(Node->getOperand(0));
4287 Tmp2 = PromoteOp(Node->getOperand(1));
4288 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4289 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4294 Tmp1 = PromoteOp(Node->getOperand(0));
4295 Tmp2 = PromoteOp(Node->getOperand(1));
4296 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4297 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4299 // Floating point operations will give excess precision that we may not be
4300 // able to tolerate. If we DO allow excess precision, just leave it,
4301 // otherwise excise it.
4302 // FIXME: Why would we need to round FP ops more than integer ones?
4303 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4304 if (NoExcessFPPrecision)
4305 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4306 DAG.getValueType(VT));
4311 // These operators require that their input be sign extended.
4312 Tmp1 = PromoteOp(Node->getOperand(0));
4313 Tmp2 = PromoteOp(Node->getOperand(1));
4314 if (MVT::isInteger(NVT)) {
4315 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4316 DAG.getValueType(VT));
4317 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4318 DAG.getValueType(VT));
4320 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4322 // Perform FP_ROUND: this is probably overly pessimistic.
4323 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
4324 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4325 DAG.getValueType(VT));
4329 case ISD::FCOPYSIGN:
4330 // These operators require that their input be fp extended.
4331 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4332 case Expand: assert(0 && "not implemented");
4333 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4334 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4336 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4337 case Expand: assert(0 && "not implemented");
4338 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4339 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4341 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4343 // Perform FP_ROUND: this is probably overly pessimistic.
4344 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4345 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4346 DAG.getValueType(VT));
4351 // These operators require that their input be zero extended.
4352 Tmp1 = PromoteOp(Node->getOperand(0));
4353 Tmp2 = PromoteOp(Node->getOperand(1));
4354 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
4355 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4356 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4357 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4361 Tmp1 = PromoteOp(Node->getOperand(0));
4362 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4365 // The input value must be properly sign extended.
4366 Tmp1 = PromoteOp(Node->getOperand(0));
4367 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4368 DAG.getValueType(VT));
4369 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4372 // The input value must be properly zero extended.
4373 Tmp1 = PromoteOp(Node->getOperand(0));
4374 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4375 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4379 Tmp1 = Node->getOperand(0); // Get the chain.
4380 Tmp2 = Node->getOperand(1); // Get the pointer.
4381 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4382 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4383 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
4385 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4386 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4387 // Increment the pointer, VAList, to the next vaarg
4388 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4389 DAG.getConstant(MVT::getSizeInBits(VT)/8,
4390 TLI.getPointerTy()));
4391 // Store the incremented VAList to the legalized pointer
4392 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4393 // Load the actual argument out of the pointer VAList
4394 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4396 // Remember that we legalized the chain.
4397 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4401 LoadSDNode *LD = cast<LoadSDNode>(Node);
4402 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4403 ? ISD::EXTLOAD : LD->getExtensionType();
4404 Result = DAG.getExtLoad(ExtType, NVT,
4405 LD->getChain(), LD->getBasePtr(),
4406 LD->getSrcValue(), LD->getSrcValueOffset(),
4409 LD->getAlignment());
4410 // Remember that we legalized the chain.
4411 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4415 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4416 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4417 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
4419 case ISD::SELECT_CC:
4420 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4421 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4422 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4423 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4426 Tmp1 = Node->getOperand(0);
4427 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4428 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4429 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4430 DAG.getConstant(MVT::getSizeInBits(NVT) -
4431 MVT::getSizeInBits(VT),
4432 TLI.getShiftAmountTy()));
4437 // Zero extend the argument
4438 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4439 // Perform the larger operation, then subtract if needed.
4440 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4441 switch(Node->getOpcode()) {
4446 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4447 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
4448 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
4450 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4451 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
4454 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4455 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4456 DAG.getConstant(MVT::getSizeInBits(NVT) -
4457 MVT::getSizeInBits(VT), NVT));
4461 case ISD::EXTRACT_SUBVECTOR:
4462 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4464 case ISD::EXTRACT_VECTOR_ELT:
4465 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4469 assert(Result.Val && "Didn't set a result!");
4471 // Make sure the result is itself legal.
4472 Result = LegalizeOp(Result);
4474 // Remember that we promoted this!
4475 AddPromotedOperand(Op, Result);
4479 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4480 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4481 /// based on the vector type. The return type of this matches the element type
4482 /// of the vector, which may not be legal for the target.
4483 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4484 // We know that operand #0 is the Vec vector. If the index is a constant
4485 // or if the invec is a supported hardware type, we can use it. Otherwise,
4486 // lower to a store then an indexed load.
4487 SDOperand Vec = Op.getOperand(0);
4488 SDOperand Idx = Op.getOperand(1);
4490 MVT::ValueType TVT = Vec.getValueType();
4491 unsigned NumElems = MVT::getVectorNumElements(TVT);
4493 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4494 default: assert(0 && "This action is not supported yet!");
4495 case TargetLowering::Custom: {
4496 Vec = LegalizeOp(Vec);
4497 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4498 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4503 case TargetLowering::Legal:
4504 if (isTypeLegal(TVT)) {
4505 Vec = LegalizeOp(Vec);
4506 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4510 case TargetLowering::Expand:
4514 if (NumElems == 1) {
4515 // This must be an access of the only element. Return it.
4516 Op = ScalarizeVectorOp(Vec);
4517 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4518 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4519 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4521 SplitVectorOp(Vec, Lo, Hi);
4522 if (CIdx->getValue() < NumLoElts) {
4526 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4527 Idx.getValueType());
4530 // It's now an extract from the appropriate high or low part. Recurse.
4531 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4532 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4534 // Store the value to a temporary stack slot, then LOAD the scalar
4535 // element back out.
4536 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4537 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4539 // Add the offset to the index.
4540 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
4541 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4542 DAG.getConstant(EltSize, Idx.getValueType()));
4544 if (MVT::getSizeInBits(Idx.getValueType()) >
4545 MVT::getSizeInBits(TLI.getPointerTy()))
4546 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4548 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4550 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4552 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4557 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4558 /// we assume the operation can be split if it is not already legal.
4559 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4560 // We know that operand #0 is the Vec vector. For now we assume the index
4561 // is a constant and that the extracted result is a supported hardware type.
4562 SDOperand Vec = Op.getOperand(0);
4563 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4565 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
4567 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
4568 // This must be an access of the desired vector length. Return it.
4572 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4574 SplitVectorOp(Vec, Lo, Hi);
4575 if (CIdx->getValue() < NumElems/2) {
4579 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4582 // It's now an extract from the appropriate high or low part. Recurse.
4583 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4584 return ExpandEXTRACT_SUBVECTOR(Op);
4587 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4588 /// with condition CC on the current target. This usually involves legalizing
4589 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4590 /// there may be no choice but to create a new SetCC node to represent the
4591 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4592 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4593 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4596 SDOperand Tmp1, Tmp2, Tmp3, Result;
4598 switch (getTypeAction(LHS.getValueType())) {
4600 Tmp1 = LegalizeOp(LHS); // LHS
4601 Tmp2 = LegalizeOp(RHS); // RHS
4604 Tmp1 = PromoteOp(LHS); // LHS
4605 Tmp2 = PromoteOp(RHS); // RHS
4607 // If this is an FP compare, the operands have already been extended.
4608 if (MVT::isInteger(LHS.getValueType())) {
4609 MVT::ValueType VT = LHS.getValueType();
4610 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4612 // Otherwise, we have to insert explicit sign or zero extends. Note
4613 // that we could insert sign extends for ALL conditions, but zero extend
4614 // is cheaper on many machines (an AND instead of two shifts), so prefer
4616 switch (cast<CondCodeSDNode>(CC)->get()) {
4617 default: assert(0 && "Unknown integer comparison!");
4624 // ALL of these operations will work if we either sign or zero extend
4625 // the operands (including the unsigned comparisons!). Zero extend is
4626 // usually a simpler/cheaper operation, so prefer it.
4627 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4628 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4634 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4635 DAG.getValueType(VT));
4636 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4637 DAG.getValueType(VT));
4643 MVT::ValueType VT = LHS.getValueType();
4644 if (VT == MVT::f32 || VT == MVT::f64) {
4645 // Expand into one or more soft-fp libcall(s).
4646 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4647 switch (cast<CondCodeSDNode>(CC)->get()) {
4650 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4654 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4658 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4662 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4666 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4670 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4673 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4676 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4679 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4680 switch (cast<CondCodeSDNode>(CC)->get()) {
4682 // SETONE = SETOLT | SETOGT
4683 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4686 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4689 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4692 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4695 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4698 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4700 default: assert(0 && "Unsupported FP setcc!");
4705 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4706 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4707 false /*sign irrelevant*/, Dummy);
4708 Tmp2 = DAG.getConstant(0, MVT::i32);
4709 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4710 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4711 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4712 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4713 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4714 false /*sign irrelevant*/, Dummy);
4715 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4716 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4717 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4725 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4726 ExpandOp(LHS, LHSLo, LHSHi);
4727 ExpandOp(RHS, RHSLo, RHSHi);
4728 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4730 if (VT==MVT::ppcf128) {
4731 // FIXME: This generated code sucks. We want to generate
4732 // FCMP crN, hi1, hi2
4734 // FCMP crN, lo1, lo2
4735 // The following can be improved, but not that much.
4736 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4737 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
4738 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4739 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
4740 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
4741 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4742 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4751 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4752 if (RHSCST->isAllOnesValue()) {
4753 // Comparison to -1.
4754 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4759 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4760 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4761 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4762 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4765 // If this is a comparison of the sign bit, just look at the top part.
4767 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4768 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4769 CST->getValue() == 0) || // X < 0
4770 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4771 CST->isAllOnesValue())) { // X > -1
4777 // FIXME: This generated code sucks.
4778 ISD::CondCode LowCC;
4780 default: assert(0 && "Unknown integer setcc!");
4782 case ISD::SETULT: LowCC = ISD::SETULT; break;
4784 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4786 case ISD::SETULE: LowCC = ISD::SETULE; break;
4788 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4791 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4792 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4793 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4795 // NOTE: on targets without efficient SELECT of bools, we can always use
4796 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4797 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4798 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4799 false, DagCombineInfo);
4801 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4802 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4803 CCCode, false, DagCombineInfo);
4805 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC);
4807 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4808 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4809 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4810 (Tmp2C && Tmp2C->getValue() == 0 &&
4811 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4812 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4813 (Tmp2C && Tmp2C->getValue() == 1 &&
4814 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4815 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4816 // low part is known false, returns high part.
4817 // For LE / GE, if high part is known false, ignore the low part.
4818 // For LT / GT, if high part is known true, ignore the low part.
4822 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4823 ISD::SETEQ, false, DagCombineInfo);
4825 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4826 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4827 Result, Tmp1, Tmp2));
4838 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4839 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4840 /// a load from the stack slot to DestVT, extending it if needed.
4841 /// The resultant code need not be legal.
4842 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4843 MVT::ValueType SlotVT,
4844 MVT::ValueType DestVT) {
4845 // Create the stack frame object.
4846 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
4848 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4849 int SPFI = StackPtrFI->getIndex();
4851 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType());
4852 unsigned SlotSize = MVT::getSizeInBits(SlotVT);
4853 unsigned DestSize = MVT::getSizeInBits(DestVT);
4855 // Emit a store to the stack slot. Use a truncstore if the input value is
4856 // later than DestVT.
4858 if (SrcSize > SlotSize)
4859 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4860 PseudoSourceValue::getFixedStack(),
4863 assert(SrcSize == SlotSize && "Invalid store");
4864 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4865 PseudoSourceValue::getFixedStack(),
4869 // Result is a load from the stack slot.
4870 if (SlotSize == DestSize)
4871 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4873 assert(SlotSize < DestSize && "Unknown extension!");
4874 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT);
4877 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4878 // Create a vector sized/aligned stack slot, store the value to element #0,
4879 // then load the whole vector back out.
4880 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4882 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4883 int SPFI = StackPtrFI->getIndex();
4885 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4886 PseudoSourceValue::getFixedStack(), SPFI);
4887 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4888 PseudoSourceValue::getFixedStack(), SPFI);
4892 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4893 /// support the operation, but do support the resultant vector type.
4894 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4896 // If the only non-undef value is the low element, turn this into a
4897 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4898 unsigned NumElems = Node->getNumOperands();
4899 bool isOnlyLowElement = true;
4900 SDOperand SplatValue = Node->getOperand(0);
4901 std::map<SDOperand, std::vector<unsigned> > Values;
4902 Values[SplatValue].push_back(0);
4903 bool isConstant = true;
4904 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4905 SplatValue.getOpcode() != ISD::UNDEF)
4908 for (unsigned i = 1; i < NumElems; ++i) {
4909 SDOperand V = Node->getOperand(i);
4910 Values[V].push_back(i);
4911 if (V.getOpcode() != ISD::UNDEF)
4912 isOnlyLowElement = false;
4913 if (SplatValue != V)
4914 SplatValue = SDOperand(0,0);
4916 // If this isn't a constant element or an undef, we can't use a constant
4918 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4919 V.getOpcode() != ISD::UNDEF)
4923 if (isOnlyLowElement) {
4924 // If the low element is an undef too, then this whole things is an undef.
4925 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4926 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4927 // Otherwise, turn this into a scalar_to_vector node.
4928 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4929 Node->getOperand(0));
4932 // If all elements are constants, create a load from the constant pool.
4934 MVT::ValueType VT = Node->getValueType(0);
4936 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4937 std::vector<Constant*> CV;
4938 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4939 if (ConstantFPSDNode *V =
4940 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4941 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4942 } else if (ConstantSDNode *V =
4943 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4944 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4946 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4947 CV.push_back(UndefValue::get(OpNTy));
4950 Constant *CP = ConstantVector::get(CV);
4951 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4952 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4953 PseudoSourceValue::getConstantPool(), 0);
4956 if (SplatValue.Val) { // Splat of one value?
4957 // Build the shuffle constant vector: <0, 0, 0, 0>
4958 MVT::ValueType MaskVT =
4959 MVT::getIntVectorWithNumElements(NumElems);
4960 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4961 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4962 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4963 &ZeroVec[0], ZeroVec.size());
4965 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4966 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4967 // Get the splatted value into the low element of a vector register.
4968 SDOperand LowValVec =
4969 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4971 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4972 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4973 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4978 // If there are only two unique elements, we may be able to turn this into a
4980 if (Values.size() == 2) {
4981 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4982 MVT::ValueType MaskVT =
4983 MVT::getIntVectorWithNumElements(NumElems);
4984 std::vector<SDOperand> MaskVec(NumElems);
4986 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4987 E = Values.end(); I != E; ++I) {
4988 for (std::vector<unsigned>::iterator II = I->second.begin(),
4989 EE = I->second.end(); II != EE; ++II)
4990 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4993 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4994 &MaskVec[0], MaskVec.size());
4996 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4997 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4998 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4999 SmallVector<SDOperand, 8> Ops;
5000 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
5001 E = Values.end(); I != E; ++I) {
5002 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
5006 Ops.push_back(ShuffleMask);
5008 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5009 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
5010 &Ops[0], Ops.size());
5014 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5015 // aligned object on the stack, store each element into it, then load
5016 // the result as a vector.
5017 MVT::ValueType VT = Node->getValueType(0);
5018 // Create the stack frame object.
5019 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
5021 // Emit a store of each element to the stack slot.
5022 SmallVector<SDOperand, 8> Stores;
5023 unsigned TypeByteSize =
5024 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
5025 // Store (in the right endianness) the elements to memory.
5026 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5027 // Ignore undef elements.
5028 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5030 unsigned Offset = TypeByteSize*i;
5032 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5033 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5035 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5039 SDOperand StoreChain;
5040 if (!Stores.empty()) // Not all undef elements?
5041 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5042 &Stores[0], Stores.size());
5044 StoreChain = DAG.getEntryNode();
5046 // Result is a load from the stack slot.
5047 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5050 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5051 SDOperand Op, SDOperand Amt,
5052 SDOperand &Lo, SDOperand &Hi) {
5053 // Expand the subcomponents.
5054 SDOperand LHSL, LHSH;
5055 ExpandOp(Op, LHSL, LHSH);
5057 SDOperand Ops[] = { LHSL, LHSH, Amt };
5058 MVT::ValueType VT = LHSL.getValueType();
5059 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5060 Hi = Lo.getValue(1);
5064 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5065 /// smaller elements. If we can't find a way that is more efficient than a
5066 /// libcall on this target, return false. Otherwise, return true with the
5067 /// low-parts expanded into Lo and Hi.
5068 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
5069 SDOperand &Lo, SDOperand &Hi) {
5070 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5071 "This is not a shift!");
5073 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
5074 SDOperand ShAmt = LegalizeOp(Amt);
5075 MVT::ValueType ShTy = ShAmt.getValueType();
5076 unsigned ShBits = MVT::getSizeInBits(ShTy);
5077 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
5078 unsigned NVTBits = MVT::getSizeInBits(NVT);
5080 // Handle the case when Amt is an immediate.
5081 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
5082 unsigned Cst = CN->getValue();
5083 // Expand the incoming operand to be shifted, so that we have its parts
5085 ExpandOp(Op, InL, InH);
5089 Lo = DAG.getConstant(0, NVT);
5090 Hi = DAG.getConstant(0, NVT);
5091 } else if (Cst > NVTBits) {
5092 Lo = DAG.getConstant(0, NVT);
5093 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5094 } else if (Cst == NVTBits) {
5095 Lo = DAG.getConstant(0, NVT);
5098 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5099 Hi = DAG.getNode(ISD::OR, NVT,
5100 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5101 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5106 Lo = DAG.getConstant(0, NVT);
5107 Hi = DAG.getConstant(0, NVT);
5108 } else if (Cst > NVTBits) {
5109 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5110 Hi = DAG.getConstant(0, NVT);
5111 } else if (Cst == NVTBits) {
5113 Hi = DAG.getConstant(0, NVT);
5115 Lo = DAG.getNode(ISD::OR, NVT,
5116 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5117 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5118 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5123 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5124 DAG.getConstant(NVTBits-1, ShTy));
5125 } else if (Cst > NVTBits) {
5126 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5127 DAG.getConstant(Cst-NVTBits, ShTy));
5128 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5129 DAG.getConstant(NVTBits-1, ShTy));
5130 } else if (Cst == NVTBits) {
5132 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5133 DAG.getConstant(NVTBits-1, ShTy));
5135 Lo = DAG.getNode(ISD::OR, NVT,
5136 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5137 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5138 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5144 // Okay, the shift amount isn't constant. However, if we can tell that it is
5145 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5146 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5147 APInt KnownZero, KnownOne;
5148 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5150 // If we know that if any of the high bits of the shift amount are one, then
5151 // we can do this as a couple of simple shifts.
5152 if (KnownOne.intersects(Mask)) {
5153 // Mask out the high bit, which we know is set.
5154 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5155 DAG.getConstant(~Mask, Amt.getValueType()));
5157 // Expand the incoming operand to be shifted, so that we have its parts
5159 ExpandOp(Op, InL, InH);
5162 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5163 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5166 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5167 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5170 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5171 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5172 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5177 // If we know that the high bits of the shift amount are all zero, then we can
5178 // do this as a couple of simple shifts.
5179 if ((KnownZero & Mask) == Mask) {
5181 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5182 DAG.getConstant(NVTBits, Amt.getValueType()),
5185 // Expand the incoming operand to be shifted, so that we have its parts
5187 ExpandOp(Op, InL, InH);
5190 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5191 Hi = DAG.getNode(ISD::OR, NVT,
5192 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5193 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5196 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5197 Lo = DAG.getNode(ISD::OR, NVT,
5198 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5199 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5202 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5203 Lo = DAG.getNode(ISD::OR, NVT,
5204 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5205 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5214 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5215 // does not fit into a register, return the lo part and set the hi part to the
5216 // by-reg argument. If it does fit into a single register, return the result
5217 // and leave the Hi part unset.
5218 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
5219 bool isSigned, SDOperand &Hi) {
5220 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5221 // The input chain to this libcall is the entry node of the function.
5222 // Legalizing the call will automatically add the previous call to the
5224 SDOperand InChain = DAG.getEntryNode();
5226 TargetLowering::ArgListTy Args;
5227 TargetLowering::ArgListEntry Entry;
5228 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5229 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
5230 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
5231 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5232 Entry.isSExt = isSigned;
5233 Entry.isZExt = !isSigned;
5234 Args.push_back(Entry);
5236 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
5238 // Splice the libcall in wherever FindInputOutputChains tells us to.
5239 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
5240 std::pair<SDOperand,SDOperand> CallInfo =
5241 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
5242 false, Callee, Args, DAG);
5244 // Legalize the call sequence, starting with the chain. This will advance
5245 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5246 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5247 LegalizeOp(CallInfo.second);
5249 switch (getTypeAction(CallInfo.first.getValueType())) {
5250 default: assert(0 && "Unknown thing");
5252 Result = CallInfo.first;
5255 ExpandOp(CallInfo.first, Result, Hi);
5262 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5264 SDOperand SelectionDAGLegalize::
5265 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
5266 assert(getTypeAction(Source.getValueType()) == Expand &&
5267 "This is not an expansion!");
5268 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
5271 assert(Source.getValueType() == MVT::i64 &&
5272 "This only works for 64-bit -> FP");
5273 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
5274 // incoming integer is set. To handle this, we dynamically test to see if
5275 // it is set, and, if so, add a fudge factor.
5277 ExpandOp(Source, Lo, Hi);
5279 // If this is unsigned, and not supported, first perform the conversion to
5280 // signed, then adjust the result if the sign bit is set.
5281 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
5282 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
5284 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
5285 DAG.getConstant(0, Hi.getValueType()),
5287 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5288 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5289 SignSet, Four, Zero);
5290 uint64_t FF = 0x5f800000ULL;
5291 if (TLI.isLittleEndian()) FF <<= 32;
5292 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5294 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5295 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5296 SDOperand FudgeInReg;
5297 if (DestTy == MVT::f32)
5298 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5299 PseudoSourceValue::getConstantPool(), 0);
5300 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
5301 // FIXME: Avoid the extend by construction the right constantpool?
5302 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5304 PseudoSourceValue::getConstantPool(), 0,
5307 assert(0 && "Unexpected conversion");
5309 MVT::ValueType SCVT = SignedConv.getValueType();
5310 if (SCVT != DestTy) {
5311 // Destination type needs to be expanded as well. The FADD now we are
5312 // constructing will be expanded into a libcall.
5313 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
5314 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
5315 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
5316 SignedConv, SignedConv.getValue(1));
5318 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5320 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5323 // Check to see if the target has a custom way to lower this. If so, use it.
5324 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
5325 default: assert(0 && "This action not implemented for this operation!");
5326 case TargetLowering::Legal:
5327 case TargetLowering::Expand:
5328 break; // This case is handled below.
5329 case TargetLowering::Custom: {
5330 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5333 return LegalizeOp(NV);
5334 break; // The target decided this was legal after all
5338 // Expand the source, then glue it back together for the call. We must expand
5339 // the source in case it is shared (this pass of legalize must traverse it).
5340 SDOperand SrcLo, SrcHi;
5341 ExpandOp(Source, SrcLo, SrcHi);
5342 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
5345 if (DestTy == MVT::f32)
5346 LC = RTLIB::SINTTOFP_I64_F32;
5348 assert(DestTy == MVT::f64 && "Unknown fp value type!");
5349 LC = RTLIB::SINTTOFP_I64_F64;
5352 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
5353 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5354 SDOperand UnusedHiPart;
5355 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
5359 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5360 /// INT_TO_FP operation of the specified operand when the target requests that
5361 /// we expand it. At this point, we know that the result and operand types are
5362 /// legal for the target.
5363 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5365 MVT::ValueType DestVT) {
5366 if (Op0.getValueType() == MVT::i32) {
5367 // simple 32-bit [signed|unsigned] integer to float/double expansion
5369 // Get the stack frame index of a 8 byte buffer.
5370 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5372 // word offset constant for Hi/Lo address computation
5373 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5374 // set up Hi and Lo (into buffer) address based on endian
5375 SDOperand Hi = StackSlot;
5376 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5377 if (TLI.isLittleEndian())
5380 // if signed map to unsigned space
5381 SDOperand Op0Mapped;
5383 // constant used to invert sign bit (signed to unsigned mapping)
5384 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5385 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5389 // store the lo of the constructed double - based on integer input
5390 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5391 Op0Mapped, Lo, NULL, 0);
5392 // initial hi portion of constructed double
5393 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5394 // store the hi of the constructed double - biased exponent
5395 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5396 // load the constructed double
5397 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5398 // FP constant to bias correct the final result
5399 SDOperand Bias = DAG.getConstantFP(isSigned ?
5400 BitsToDouble(0x4330000080000000ULL)
5401 : BitsToDouble(0x4330000000000000ULL),
5403 // subtract the bias
5404 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5407 // handle final rounding
5408 if (DestVT == MVT::f64) {
5411 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
5412 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5413 DAG.getIntPtrConstant(0));
5414 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
5415 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5419 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5420 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5422 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
5423 DAG.getConstant(0, Op0.getValueType()),
5425 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5426 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5427 SignSet, Four, Zero);
5429 // If the sign bit of the integer is set, the large number will be treated
5430 // as a negative number. To counteract this, the dynamic code adds an
5431 // offset depending on the data type.
5433 switch (Op0.getValueType()) {
5434 default: assert(0 && "Unsupported integer type!");
5435 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5436 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5437 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5438 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5440 if (TLI.isLittleEndian()) FF <<= 32;
5441 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5443 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5444 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5445 SDOperand FudgeInReg;
5446 if (DestVT == MVT::f32)
5447 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5448 PseudoSourceValue::getConstantPool(), 0);
5451 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5452 DAG.getEntryNode(), CPIdx,
5453 PseudoSourceValue::getConstantPool(), 0,
5457 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5460 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5461 /// *INT_TO_FP operation of the specified operand when the target requests that
5462 /// we promote it. At this point, we know that the result and operand types are
5463 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5464 /// operation that takes a larger input.
5465 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5466 MVT::ValueType DestVT,
5468 // First step, figure out the appropriate *INT_TO_FP operation to use.
5469 MVT::ValueType NewInTy = LegalOp.getValueType();
5471 unsigned OpToUse = 0;
5473 // Scan for the appropriate larger type to use.
5475 NewInTy = (MVT::ValueType)(NewInTy+1);
5476 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
5478 // If the target supports SINT_TO_FP of this type, use it.
5479 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5481 case TargetLowering::Legal:
5482 if (!TLI.isTypeLegal(NewInTy))
5483 break; // Can't use this datatype.
5485 case TargetLowering::Custom:
5486 OpToUse = ISD::SINT_TO_FP;
5490 if (isSigned) continue;
5492 // If the target supports UINT_TO_FP of this type, use it.
5493 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5495 case TargetLowering::Legal:
5496 if (!TLI.isTypeLegal(NewInTy))
5497 break; // Can't use this datatype.
5499 case TargetLowering::Custom:
5500 OpToUse = ISD::UINT_TO_FP;
5505 // Otherwise, try a larger type.
5508 // Okay, we found the operation and type to use. Zero extend our input to the
5509 // desired type then run the operation on it.
5510 return DAG.getNode(OpToUse, DestVT,
5511 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5515 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5516 /// FP_TO_*INT operation of the specified operand when the target requests that
5517 /// we promote it. At this point, we know that the result and operand types are
5518 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5519 /// operation that returns a larger result.
5520 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5521 MVT::ValueType DestVT,
5523 // First step, figure out the appropriate FP_TO*INT operation to use.
5524 MVT::ValueType NewOutTy = DestVT;
5526 unsigned OpToUse = 0;
5528 // Scan for the appropriate larger type to use.
5530 NewOutTy = (MVT::ValueType)(NewOutTy+1);
5531 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
5533 // If the target supports FP_TO_SINT returning this type, use it.
5534 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5536 case TargetLowering::Legal:
5537 if (!TLI.isTypeLegal(NewOutTy))
5538 break; // Can't use this datatype.
5540 case TargetLowering::Custom:
5541 OpToUse = ISD::FP_TO_SINT;
5546 // If the target supports FP_TO_UINT of this type, use it.
5547 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5549 case TargetLowering::Legal:
5550 if (!TLI.isTypeLegal(NewOutTy))
5551 break; // Can't use this datatype.
5553 case TargetLowering::Custom:
5554 OpToUse = ISD::FP_TO_UINT;
5559 // Otherwise, try a larger type.
5563 // Okay, we found the operation and type to use.
5564 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5566 // If the operation produces an invalid type, it must be custom lowered. Use
5567 // the target lowering hooks to expand it. Just keep the low part of the
5568 // expanded operation, we know that we're truncating anyway.
5569 if (getTypeAction(NewOutTy) == Expand) {
5570 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
5571 assert(Operation.Val && "Didn't return anything");
5574 // Truncate the result of the extended FP_TO_*INT operation to the desired
5576 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5579 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5581 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5582 MVT::ValueType VT = Op.getValueType();
5583 MVT::ValueType SHVT = TLI.getShiftAmountTy();
5584 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5586 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5588 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5589 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5590 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5592 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5593 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5594 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5595 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5596 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5597 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5598 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5599 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5600 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5602 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5603 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5604 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5605 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5606 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5607 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5608 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5609 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5610 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5611 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5612 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5613 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5614 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5615 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5616 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5617 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5618 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5619 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5620 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5621 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5622 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5626 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5628 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5630 default: assert(0 && "Cannot expand this yet!");
5632 static const uint64_t mask[6] = {
5633 0x5555555555555555ULL, 0x3333333333333333ULL,
5634 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5635 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5637 MVT::ValueType VT = Op.getValueType();
5638 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5639 unsigned len = MVT::getSizeInBits(VT);
5640 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5641 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5642 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5643 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5644 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5645 DAG.getNode(ISD::AND, VT,
5646 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5651 // for now, we do this:
5652 // x = x | (x >> 1);
5653 // x = x | (x >> 2);
5655 // x = x | (x >>16);
5656 // x = x | (x >>32); // for 64-bit input
5657 // return popcount(~x);
5659 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5660 MVT::ValueType VT = Op.getValueType();
5661 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5662 unsigned len = MVT::getSizeInBits(VT);
5663 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5664 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5665 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5667 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5668 return DAG.getNode(ISD::CTPOP, VT, Op);
5671 // for now, we use: { return popcount(~x & (x - 1)); }
5672 // unless the target has ctlz but not ctpop, in which case we use:
5673 // { return 32 - nlz(~x & (x-1)); }
5674 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5675 MVT::ValueType VT = Op.getValueType();
5676 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5677 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5678 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5679 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5680 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5681 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5682 TLI.isOperationLegal(ISD::CTLZ, VT))
5683 return DAG.getNode(ISD::SUB, VT,
5684 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5685 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5686 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5691 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5692 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5693 /// LegalizeNodes map is filled in for any results that are not expanded, the
5694 /// ExpandedNodes map is filled in for any results that are expanded, and the
5695 /// Lo/Hi values are returned.
5696 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5697 MVT::ValueType VT = Op.getValueType();
5698 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5699 SDNode *Node = Op.Val;
5700 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5701 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5702 MVT::isVector(VT)) &&
5703 "Cannot expand to FP value or to larger int value!");
5705 // See if we already expanded it.
5706 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5707 = ExpandedNodes.find(Op);
5708 if (I != ExpandedNodes.end()) {
5709 Lo = I->second.first;
5710 Hi = I->second.second;
5714 switch (Node->getOpcode()) {
5715 case ISD::CopyFromReg:
5716 assert(0 && "CopyFromReg must be legal!");
5717 case ISD::FP_ROUND_INREG:
5718 if (VT == MVT::ppcf128 &&
5719 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5720 TargetLowering::Custom) {
5721 SDOperand SrcLo, SrcHi, Src;
5722 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5723 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5724 SDOperand Result = TLI.LowerOperation(
5725 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5726 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5727 Lo = Result.Val->getOperand(0);
5728 Hi = Result.Val->getOperand(1);
5734 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5736 assert(0 && "Do not know how to expand this operator!");
5738 case ISD::EXTRACT_VECTOR_ELT:
5739 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5740 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5741 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5742 return ExpandOp(Lo, Lo, Hi);
5744 NVT = TLI.getTypeToExpandTo(VT);
5745 Lo = DAG.getNode(ISD::UNDEF, NVT);
5746 Hi = DAG.getNode(ISD::UNDEF, NVT);
5748 case ISD::Constant: {
5749 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
5750 Lo = DAG.getConstant(Cst, NVT);
5751 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
5754 case ISD::ConstantFP: {
5755 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5756 if (CFP->getValueType(0) == MVT::ppcf128) {
5757 APInt api = CFP->getValueAPF().convertToAPInt();
5758 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5760 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5764 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5765 if (getTypeAction(Lo.getValueType()) == Expand)
5766 ExpandOp(Lo, Lo, Hi);
5769 case ISD::BUILD_PAIR:
5770 // Return the operands.
5771 Lo = Node->getOperand(0);
5772 Hi = Node->getOperand(1);
5775 case ISD::MERGE_VALUES:
5776 if (Node->getNumValues() == 1) {
5777 ExpandOp(Op.getOperand(0), Lo, Hi);
5780 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5781 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5782 Op.getValue(1).getValueType() == MVT::Other &&
5783 "unhandled MERGE_VALUES");
5784 ExpandOp(Op.getOperand(0), Lo, Hi);
5785 // Remember that we legalized the chain.
5786 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5789 case ISD::SIGN_EXTEND_INREG:
5790 ExpandOp(Node->getOperand(0), Lo, Hi);
5791 // sext_inreg the low part if needed.
5792 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5794 // The high part gets the sign extension from the lo-part. This handles
5795 // things like sextinreg V:i64 from i8.
5796 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5797 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5798 TLI.getShiftAmountTy()));
5802 ExpandOp(Node->getOperand(0), Lo, Hi);
5803 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5804 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5810 ExpandOp(Node->getOperand(0), Lo, Hi);
5811 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5812 DAG.getNode(ISD::CTPOP, NVT, Lo),
5813 DAG.getNode(ISD::CTPOP, NVT, Hi));
5814 Hi = DAG.getConstant(0, NVT);
5818 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5819 ExpandOp(Node->getOperand(0), Lo, Hi);
5820 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5821 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5822 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5824 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5825 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5827 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5828 Hi = DAG.getConstant(0, NVT);
5833 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5834 ExpandOp(Node->getOperand(0), Lo, Hi);
5835 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5836 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5837 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5839 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5840 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5842 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5843 Hi = DAG.getConstant(0, NVT);
5848 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5849 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5850 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5851 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5853 // Remember that we legalized the chain.
5854 Hi = LegalizeOp(Hi);
5855 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5856 if (TLI.isBigEndian())
5862 LoadSDNode *LD = cast<LoadSDNode>(Node);
5863 SDOperand Ch = LD->getChain(); // Legalize the chain.
5864 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5865 ISD::LoadExtType ExtType = LD->getExtensionType();
5866 int SVOffset = LD->getSrcValueOffset();
5867 unsigned Alignment = LD->getAlignment();
5868 bool isVolatile = LD->isVolatile();
5870 if (ExtType == ISD::NON_EXTLOAD) {
5871 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5872 isVolatile, Alignment);
5873 if (VT == MVT::f32 || VT == MVT::f64) {
5874 // f32->i32 or f64->i64 one to one expansion.
5875 // Remember that we legalized the chain.
5876 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5877 // Recursively expand the new load.
5878 if (getTypeAction(NVT) == Expand)
5879 ExpandOp(Lo, Lo, Hi);
5883 // Increment the pointer to the other half.
5884 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5885 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5886 DAG.getIntPtrConstant(IncrementSize));
5887 SVOffset += IncrementSize;
5888 Alignment = MinAlign(Alignment, IncrementSize);
5889 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5890 isVolatile, Alignment);
5892 // Build a factor node to remember that this load is independent of the
5894 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5897 // Remember that we legalized the chain.
5898 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5899 if (TLI.isBigEndian())
5902 MVT::ValueType EVT = LD->getMemoryVT();
5904 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5905 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5906 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5907 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5908 SVOffset, isVolatile, Alignment);
5909 // Remember that we legalized the chain.
5910 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5911 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5916 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5917 SVOffset, isVolatile, Alignment);
5919 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5920 SVOffset, EVT, isVolatile,
5923 // Remember that we legalized the chain.
5924 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5926 if (ExtType == ISD::SEXTLOAD) {
5927 // The high part is obtained by SRA'ing all but one of the bits of the
5929 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5930 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5931 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5932 } else if (ExtType == ISD::ZEXTLOAD) {
5933 // The high part is just a zero.
5934 Hi = DAG.getConstant(0, NVT);
5935 } else /* if (ExtType == ISD::EXTLOAD) */ {
5936 // The high part is undefined.
5937 Hi = DAG.getNode(ISD::UNDEF, NVT);
5944 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5945 SDOperand LL, LH, RL, RH;
5946 ExpandOp(Node->getOperand(0), LL, LH);
5947 ExpandOp(Node->getOperand(1), RL, RH);
5948 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5949 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5953 SDOperand LL, LH, RL, RH;
5954 ExpandOp(Node->getOperand(1), LL, LH);
5955 ExpandOp(Node->getOperand(2), RL, RH);
5956 if (getTypeAction(NVT) == Expand)
5957 NVT = TLI.getTypeToExpandTo(NVT);
5958 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5960 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5963 case ISD::SELECT_CC: {
5964 SDOperand TL, TH, FL, FH;
5965 ExpandOp(Node->getOperand(2), TL, TH);
5966 ExpandOp(Node->getOperand(3), FL, FH);
5967 if (getTypeAction(NVT) == Expand)
5968 NVT = TLI.getTypeToExpandTo(NVT);
5969 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5970 Node->getOperand(1), TL, FL, Node->getOperand(4));
5972 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5973 Node->getOperand(1), TH, FH, Node->getOperand(4));
5976 case ISD::ANY_EXTEND:
5977 // The low part is any extension of the input (which degenerates to a copy).
5978 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5979 // The high part is undefined.
5980 Hi = DAG.getNode(ISD::UNDEF, NVT);
5982 case ISD::SIGN_EXTEND: {
5983 // The low part is just a sign extension of the input (which degenerates to
5985 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5987 // The high part is obtained by SRA'ing all but one of the bits of the lo
5989 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5990 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5991 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5994 case ISD::ZERO_EXTEND:
5995 // The low part is just a zero extension of the input (which degenerates to
5997 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5999 // The high part is just a zero.
6000 Hi = DAG.getConstant(0, NVT);
6003 case ISD::TRUNCATE: {
6004 // The input value must be larger than this value. Expand *it*.
6006 ExpandOp(Node->getOperand(0), NewLo, Hi);
6008 // The low part is now either the right size, or it is closer. If not the
6009 // right size, make an illegal truncate so we recursively expand it.
6010 if (NewLo.getValueType() != Node->getValueType(0))
6011 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6012 ExpandOp(NewLo, Lo, Hi);
6016 case ISD::BIT_CONVERT: {
6018 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6019 // If the target wants to, allow it to lower this itself.
6020 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6021 case Expand: assert(0 && "cannot expand FP!");
6022 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6023 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6025 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6028 // f32 / f64 must be expanded to i32 / i64.
6029 if (VT == MVT::f32 || VT == MVT::f64) {
6030 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6031 if (getTypeAction(NVT) == Expand)
6032 ExpandOp(Lo, Lo, Hi);
6036 // If source operand will be expanded to the same type as VT, i.e.
6037 // i64 <- f64, i32 <- f32, expand the source operand instead.
6038 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
6039 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6040 ExpandOp(Node->getOperand(0), Lo, Hi);
6044 // Turn this into a load/store pair by default.
6046 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6048 ExpandOp(Tmp, Lo, Hi);
6052 case ISD::READCYCLECOUNTER: {
6053 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6054 TargetLowering::Custom &&
6055 "Must custom expand ReadCycleCounter");
6056 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6057 assert(Tmp.Val && "Node must be custom expanded!");
6058 ExpandOp(Tmp.getValue(0), Lo, Hi);
6059 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6060 LegalizeOp(Tmp.getValue(1)));
6064 // These operators cannot be expanded directly, emit them as calls to
6065 // library functions.
6066 case ISD::FP_TO_SINT: {
6067 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6069 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6070 case Expand: assert(0 && "cannot expand FP!");
6071 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6072 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6075 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6077 // Now that the custom expander is done, expand the result, which is still
6080 ExpandOp(Op, Lo, Hi);
6085 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6086 if (Node->getOperand(0).getValueType() == MVT::f32)
6087 LC = RTLIB::FPTOSINT_F32_I64;
6088 else if (Node->getOperand(0).getValueType() == MVT::f64)
6089 LC = RTLIB::FPTOSINT_F64_I64;
6090 else if (Node->getOperand(0).getValueType() == MVT::f80)
6091 LC = RTLIB::FPTOSINT_F80_I64;
6092 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6093 LC = RTLIB::FPTOSINT_PPCF128_I64;
6094 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6095 false/*sign irrelevant*/, Hi);
6099 case ISD::FP_TO_UINT: {
6100 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6102 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6103 case Expand: assert(0 && "cannot expand FP!");
6104 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6105 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6108 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6110 // Now that the custom expander is done, expand the result.
6112 ExpandOp(Op, Lo, Hi);
6117 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6118 if (Node->getOperand(0).getValueType() == MVT::f32)
6119 LC = RTLIB::FPTOUINT_F32_I64;
6120 else if (Node->getOperand(0).getValueType() == MVT::f64)
6121 LC = RTLIB::FPTOUINT_F64_I64;
6122 else if (Node->getOperand(0).getValueType() == MVT::f80)
6123 LC = RTLIB::FPTOUINT_F80_I64;
6124 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6125 LC = RTLIB::FPTOUINT_PPCF128_I64;
6126 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6127 false/*sign irrelevant*/, Hi);
6132 // If the target wants custom lowering, do so.
6133 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6134 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6135 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6136 Op = TLI.LowerOperation(Op, DAG);
6138 // Now that the custom expander is done, expand the result, which is
6140 ExpandOp(Op, Lo, Hi);
6145 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6146 // this X << 1 as X+X.
6147 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6148 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6149 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6150 SDOperand LoOps[2], HiOps[3];
6151 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6152 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6153 LoOps[1] = LoOps[0];
6154 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6156 HiOps[1] = HiOps[0];
6157 HiOps[2] = Lo.getValue(1);
6158 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6163 // If we can emit an efficient shift operation, do so now.
6164 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6167 // If this target supports SHL_PARTS, use it.
6168 TargetLowering::LegalizeAction Action =
6169 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6170 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6171 Action == TargetLowering::Custom) {
6172 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6176 // Otherwise, emit a libcall.
6177 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
6178 false/*left shift=unsigned*/, Hi);
6183 // If the target wants custom lowering, do so.
6184 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6185 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6186 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6187 Op = TLI.LowerOperation(Op, DAG);
6189 // Now that the custom expander is done, expand the result, which is
6191 ExpandOp(Op, Lo, Hi);
6196 // If we can emit an efficient shift operation, do so now.
6197 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6200 // If this target supports SRA_PARTS, use it.
6201 TargetLowering::LegalizeAction Action =
6202 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6203 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6204 Action == TargetLowering::Custom) {
6205 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6209 // Otherwise, emit a libcall.
6210 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
6211 true/*ashr is signed*/, Hi);
6216 // If the target wants custom lowering, do so.
6217 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6218 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6219 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6220 Op = TLI.LowerOperation(Op, DAG);
6222 // Now that the custom expander is done, expand the result, which is
6224 ExpandOp(Op, Lo, Hi);
6229 // If we can emit an efficient shift operation, do so now.
6230 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6233 // If this target supports SRL_PARTS, use it.
6234 TargetLowering::LegalizeAction Action =
6235 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6236 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6237 Action == TargetLowering::Custom) {
6238 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6242 // Otherwise, emit a libcall.
6243 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
6244 false/*lshr is unsigned*/, Hi);
6250 // If the target wants to custom expand this, let them.
6251 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6252 TargetLowering::Custom) {
6253 Op = TLI.LowerOperation(Op, DAG);
6255 ExpandOp(Op, Lo, Hi);
6260 // Expand the subcomponents.
6261 SDOperand LHSL, LHSH, RHSL, RHSH;
6262 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6263 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6264 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6265 SDOperand LoOps[2], HiOps[3];
6270 if (Node->getOpcode() == ISD::ADD) {
6271 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6272 HiOps[2] = Lo.getValue(1);
6273 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6275 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6276 HiOps[2] = Lo.getValue(1);
6277 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6284 // Expand the subcomponents.
6285 SDOperand LHSL, LHSH, RHSL, RHSH;
6286 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6287 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6288 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6289 SDOperand LoOps[2] = { LHSL, RHSL };
6290 SDOperand HiOps[3] = { LHSH, RHSH };
6292 if (Node->getOpcode() == ISD::ADDC) {
6293 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6294 HiOps[2] = Lo.getValue(1);
6295 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6297 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6298 HiOps[2] = Lo.getValue(1);
6299 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6301 // Remember that we legalized the flag.
6302 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6307 // Expand the subcomponents.
6308 SDOperand LHSL, LHSH, RHSL, RHSH;
6309 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6310 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6311 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6312 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6313 SDOperand HiOps[3] = { LHSH, RHSH };
6315 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6316 HiOps[2] = Lo.getValue(1);
6317 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6319 // Remember that we legalized the flag.
6320 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6324 // If the target wants to custom expand this, let them.
6325 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6326 SDOperand New = TLI.LowerOperation(Op, DAG);
6328 ExpandOp(New, Lo, Hi);
6333 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6334 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6335 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6336 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6337 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6338 SDOperand LL, LH, RL, RH;
6339 ExpandOp(Node->getOperand(0), LL, LH);
6340 ExpandOp(Node->getOperand(1), RL, RH);
6341 unsigned BitSize = MVT::getSizeInBits(RH.getValueType());
6342 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6343 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6344 // FIXME: generalize this to handle other bit sizes
6345 if (LHSSB == 32 && RHSSB == 32 &&
6346 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) &&
6347 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) {
6348 // The inputs are both zero-extended.
6350 // We can emit a umul_lohi.
6351 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6352 Hi = SDOperand(Lo.Val, 1);
6356 // We can emit a mulhu+mul.
6357 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6358 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6362 if (LHSSB > BitSize && RHSSB > BitSize) {
6363 // The input values are both sign-extended.
6365 // We can emit a smul_lohi.
6366 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6367 Hi = SDOperand(Lo.Val, 1);
6371 // We can emit a mulhs+mul.
6372 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6373 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6378 // Lo,Hi = umul LHS, RHS.
6379 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6380 DAG.getVTList(NVT, NVT), LL, RL);
6382 Hi = UMulLOHI.getValue(1);
6383 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6384 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6385 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6386 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6390 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6391 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6392 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6393 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6394 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6395 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6400 // If nothing else, we can make a libcall.
6401 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
6402 false/*sign irrelevant*/, Hi);
6406 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
6409 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
6412 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
6415 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
6419 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32,
6422 RTLIB::ADD_PPCF128)),
6426 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32,
6429 RTLIB::SUB_PPCF128)),
6433 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32,
6436 RTLIB::MUL_PPCF128)),
6440 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32,
6443 RTLIB::DIV_PPCF128)),
6446 case ISD::FP_EXTEND:
6447 if (VT == MVT::ppcf128) {
6448 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6449 Node->getOperand(0).getValueType()==MVT::f64);
6450 const uint64_t zero = 0;
6451 if (Node->getOperand(0).getValueType()==MVT::f32)
6452 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6454 Hi = Node->getOperand(0);
6455 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6458 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
6461 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
6464 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32,
6467 RTLIB::POWI_PPCF128)),
6473 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6474 switch(Node->getOpcode()) {
6476 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6477 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6480 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6481 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6484 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6485 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6487 default: assert(0 && "Unreachable!");
6489 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
6493 if (VT == MVT::ppcf128) {
6495 ExpandOp(Node->getOperand(0), Lo, Tmp);
6496 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6497 // lo = hi==fabs(hi) ? lo : -lo;
6498 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6499 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6500 DAG.getCondCode(ISD::SETEQ));
6503 SDOperand Mask = (VT == MVT::f64)
6504 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6505 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6506 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6507 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6508 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6509 if (getTypeAction(NVT) == Expand)
6510 ExpandOp(Lo, Lo, Hi);
6514 if (VT == MVT::ppcf128) {
6515 ExpandOp(Node->getOperand(0), Lo, Hi);
6516 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6517 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6520 SDOperand Mask = (VT == MVT::f64)
6521 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6522 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6523 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6524 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6525 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6526 if (getTypeAction(NVT) == Expand)
6527 ExpandOp(Lo, Lo, Hi);
6530 case ISD::FCOPYSIGN: {
6531 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6532 if (getTypeAction(NVT) == Expand)
6533 ExpandOp(Lo, Lo, Hi);
6536 case ISD::SINT_TO_FP:
6537 case ISD::UINT_TO_FP: {
6538 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6539 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
6540 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) {
6541 static uint64_t zero = 0;
6543 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6544 Node->getOperand(0)));
6545 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6547 static uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6548 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6549 Node->getOperand(0)));
6550 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6551 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6552 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6553 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6554 DAG.getConstant(0, MVT::i32),
6555 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6557 APFloat(APInt(128, 2, TwoE32)),
6560 DAG.getCondCode(ISD::SETLT)),
6565 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6566 // si64->ppcf128 done by libcall, below
6567 static uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6568 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6570 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6571 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6572 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6573 DAG.getConstant(0, MVT::i64),
6574 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6576 APFloat(APInt(128, 2, TwoE64)),
6579 DAG.getCondCode(ISD::SETLT)),
6583 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6584 if (Node->getOperand(0).getValueType() == MVT::i64) {
6586 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
6587 else if (VT == MVT::f64)
6588 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
6589 else if (VT == MVT::f80) {
6591 LC = RTLIB::SINTTOFP_I64_F80;
6593 else if (VT == MVT::ppcf128) {
6595 LC = RTLIB::SINTTOFP_I64_PPCF128;
6599 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
6601 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
6604 // Promote the operand if needed.
6605 if (getTypeAction(SrcVT) == Promote) {
6606 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6608 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6609 DAG.getValueType(SrcVT))
6610 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6611 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6614 const char *LibCall = TLI.getLibcallName(LC);
6616 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
6618 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6619 Node->getOperand(0));
6620 if (getTypeAction(Lo.getValueType()) == Expand)
6621 ExpandOp(Lo, Lo, Hi);
6627 // Make sure the resultant values have been legalized themselves, unless this
6628 // is a type that requires multi-step expansion.
6629 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6630 Lo = LegalizeOp(Lo);
6632 // Don't legalize the high part if it is expanded to a single node.
6633 Hi = LegalizeOp(Hi);
6636 // Remember in a map if the values will be reused later.
6637 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6638 assert(isNew && "Value already expanded?!?");
6641 /// SplitVectorOp - Given an operand of vector type, break it down into
6642 /// two smaller values, still of vector type.
6643 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6645 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
6646 SDNode *Node = Op.Val;
6647 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
6648 assert(NumElements > 1 && "Cannot split a single element vector!");
6650 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
6652 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6653 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6655 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
6656 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
6658 // See if we already split it.
6659 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6660 = SplitNodes.find(Op);
6661 if (I != SplitNodes.end()) {
6662 Lo = I->second.first;
6663 Hi = I->second.second;
6667 switch (Node->getOpcode()) {
6672 assert(0 && "Unhandled operation in SplitVectorOp!");
6674 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6675 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6677 case ISD::BUILD_PAIR:
6678 Lo = Node->getOperand(0);
6679 Hi = Node->getOperand(1);
6681 case ISD::INSERT_VECTOR_ELT: {
6682 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6683 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
6684 SDOperand ScalarOp = Node->getOperand(1);
6685 if (Index < NewNumElts_Lo)
6686 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6687 DAG.getConstant(Index, TLI.getPointerTy()));
6689 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6690 DAG.getConstant(Index - NewNumElts_Lo,
6691 TLI.getPointerTy()));
6694 case ISD::VECTOR_SHUFFLE: {
6695 // Build the low part.
6696 SDOperand Mask = Node->getOperand(2);
6697 SmallVector<SDOperand, 8> Ops;
6698 MVT::ValueType PtrVT = TLI.getPointerTy();
6700 // Insert all of the elements from the input that are needed. We use
6701 // buildvector of extractelement here because the input vectors will have
6702 // to be legalized, so this makes the code simpler.
6703 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6704 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6705 SDOperand InVec = Node->getOperand(0);
6706 if (Idx >= NumElements) {
6707 InVec = Node->getOperand(1);
6710 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6711 DAG.getConstant(Idx, PtrVT)));
6713 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6716 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6717 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6718 SDOperand InVec = Node->getOperand(0);
6719 if (Idx >= NumElements) {
6720 InVec = Node->getOperand(1);
6723 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6724 DAG.getConstant(Idx, PtrVT)));
6726 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6729 case ISD::BUILD_VECTOR: {
6730 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6731 Node->op_begin()+NewNumElts_Lo);
6732 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6734 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6736 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6739 case ISD::CONCAT_VECTORS: {
6740 // FIXME: Handle non-power-of-two vectors?
6741 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6742 if (NewNumSubvectors == 1) {
6743 Lo = Node->getOperand(0);
6744 Hi = Node->getOperand(1);
6746 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6747 Node->op_begin()+NewNumSubvectors);
6748 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6750 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6752 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6757 SDOperand Cond = Node->getOperand(0);
6759 SDOperand LL, LH, RL, RH;
6760 SplitVectorOp(Node->getOperand(1), LL, LH);
6761 SplitVectorOp(Node->getOperand(2), RL, RH);
6763 if (MVT::isVector(Cond.getValueType())) {
6764 // Handle a vector merge.
6766 SplitVectorOp(Cond, CL, CH);
6767 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6768 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6770 // Handle a simple select with vector operands.
6771 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6772 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6792 SDOperand LL, LH, RL, RH;
6793 SplitVectorOp(Node->getOperand(0), LL, LH);
6794 SplitVectorOp(Node->getOperand(1), RL, RH);
6796 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6797 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6802 SplitVectorOp(Node->getOperand(0), L, H);
6804 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6805 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6816 case ISD::FP_TO_SINT:
6817 case ISD::FP_TO_UINT:
6818 case ISD::SINT_TO_FP:
6819 case ISD::UINT_TO_FP: {
6821 SplitVectorOp(Node->getOperand(0), L, H);
6823 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6824 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6828 LoadSDNode *LD = cast<LoadSDNode>(Node);
6829 SDOperand Ch = LD->getChain();
6830 SDOperand Ptr = LD->getBasePtr();
6831 const Value *SV = LD->getSrcValue();
6832 int SVOffset = LD->getSrcValueOffset();
6833 unsigned Alignment = LD->getAlignment();
6834 bool isVolatile = LD->isVolatile();
6836 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6837 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
6838 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6839 DAG.getIntPtrConstant(IncrementSize));
6840 SVOffset += IncrementSize;
6841 Alignment = MinAlign(Alignment, IncrementSize);
6842 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6844 // Build a factor node to remember that this load is independent of the
6846 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6849 // Remember that we legalized the chain.
6850 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6853 case ISD::BIT_CONVERT: {
6854 // We know the result is a vector. The input may be either a vector or a
6856 SDOperand InOp = Node->getOperand(0);
6857 if (!MVT::isVector(InOp.getValueType()) ||
6858 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
6859 // The input is a scalar or single-element vector.
6860 // Lower to a store/load so that it can be split.
6861 // FIXME: this could be improved probably.
6862 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6863 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val);
6865 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6867 PseudoSourceValue::getFixedStack(),
6869 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
6870 PseudoSourceValue::getFixedStack(),
6873 // Split the vector and convert each of the pieces now.
6874 SplitVectorOp(InOp, Lo, Hi);
6875 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6876 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6881 // Remember in a map if the values will be reused later.
6883 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6884 assert(isNew && "Value already split?!?");
6888 /// ScalarizeVectorOp - Given an operand of single-element vector type
6889 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6890 /// scalar (e.g. f32) value.
6891 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6892 assert(MVT::isVector(Op.getValueType()) &&
6893 "Bad ScalarizeVectorOp invocation!");
6894 SDNode *Node = Op.Val;
6895 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
6896 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
6898 // See if we already scalarized it.
6899 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
6900 if (I != ScalarizedNodes.end()) return I->second;
6903 switch (Node->getOpcode()) {
6906 Node->dump(&DAG); cerr << "\n";
6908 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
6925 Result = DAG.getNode(Node->getOpcode(),
6927 ScalarizeVectorOp(Node->getOperand(0)),
6928 ScalarizeVectorOp(Node->getOperand(1)));
6935 Result = DAG.getNode(Node->getOpcode(),
6937 ScalarizeVectorOp(Node->getOperand(0)));
6940 Result = DAG.getNode(Node->getOpcode(),
6942 ScalarizeVectorOp(Node->getOperand(0)),
6943 Node->getOperand(1));
6946 LoadSDNode *LD = cast<LoadSDNode>(Node);
6947 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
6948 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
6950 const Value *SV = LD->getSrcValue();
6951 int SVOffset = LD->getSrcValueOffset();
6952 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
6953 LD->isVolatile(), LD->getAlignment());
6955 // Remember that we legalized the chain.
6956 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
6959 case ISD::BUILD_VECTOR:
6960 Result = Node->getOperand(0);
6962 case ISD::INSERT_VECTOR_ELT:
6963 // Returning the inserted scalar element.
6964 Result = Node->getOperand(1);
6966 case ISD::CONCAT_VECTORS:
6967 assert(Node->getOperand(0).getValueType() == NewVT &&
6968 "Concat of non-legal vectors not yet supported!");
6969 Result = Node->getOperand(0);
6971 case ISD::VECTOR_SHUFFLE: {
6972 // Figure out if the scalar is the LHS or RHS and return it.
6973 SDOperand EltNum = Node->getOperand(2).getOperand(0);
6974 if (cast<ConstantSDNode>(EltNum)->getValue())
6975 Result = ScalarizeVectorOp(Node->getOperand(1));
6977 Result = ScalarizeVectorOp(Node->getOperand(0));
6980 case ISD::EXTRACT_SUBVECTOR:
6981 Result = Node->getOperand(0);
6982 assert(Result.getValueType() == NewVT);
6984 case ISD::BIT_CONVERT:
6985 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
6988 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
6989 ScalarizeVectorOp(Op.getOperand(1)),
6990 ScalarizeVectorOp(Op.getOperand(2)));
6994 if (TLI.isTypeLegal(NewVT))
6995 Result = LegalizeOp(Result);
6996 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
6997 assert(isNew && "Value already scalarized?");
7002 // SelectionDAG::Legalize - This is the entry point for the file.
7004 void SelectionDAG::Legalize() {
7005 if (ViewLegalizeDAGs) viewGraph();
7007 /// run - This is the main entry point to this class.
7009 SelectionDAGLegalize(*this).LegalizeDAG();