1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/SetVector.h"
16 #include "llvm/ADT/SmallPtrSet.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/Analysis.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineJumpTableInfo.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/DebugInfo.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetSubtargetInfo.h"
40 #define DEBUG_TYPE "legalizedag"
42 //===----------------------------------------------------------------------===//
43 /// This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class SelectionDAGLegalize {
56 const TargetMachine &TM;
57 const TargetLowering &TLI;
60 /// \brief The set of nodes which have already been legalized. We hold a
61 /// reference to it in order to update as necessary on node deletion.
62 SmallPtrSetImpl<SDNode *> &LegalizedNodes;
64 /// \brief A set of all the nodes updated during legalization.
65 SmallSetVector<SDNode *, 16> *UpdatedNodes;
67 EVT getSetCCResultType(EVT VT) const {
68 return TLI.getSetCCResultType(*DAG.getContext(), VT);
71 // Libcall insertion helpers.
74 SelectionDAGLegalize(SelectionDAG &DAG,
75 SmallPtrSetImpl<SDNode *> &LegalizedNodes,
76 SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
77 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
78 LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
80 /// \brief Legalizes the given operation.
81 void LegalizeOp(SDNode *Node);
84 SDValue OptimizeFloatStore(StoreSDNode *ST);
86 void LegalizeLoadOps(SDNode *Node);
87 void LegalizeStoreOps(SDNode *Node);
89 /// Some targets cannot handle a variable
90 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
91 /// is necessary to spill the vector being inserted into to memory, perform
92 /// the insert there, and then read the result back.
93 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
94 SDValue Idx, SDLoc dl);
95 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
96 SDValue Idx, SDLoc dl);
98 /// Return a vector shuffle operation which
99 /// performs the same shuffe in terms of order or result bytes, but on a type
100 /// whose vector element type is narrower than the original shuffle type.
101 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
102 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
103 SDValue N1, SDValue N2,
104 ArrayRef<int> Mask) const;
106 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
107 bool &NeedInvert, SDLoc dl);
109 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
110 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
111 unsigned NumOps, bool isSigned, SDLoc dl);
113 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
114 SDNode *Node, bool isSigned);
115 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
116 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
117 RTLIB::Libcall Call_F128,
118 RTLIB::Libcall Call_PPCF128);
119 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
120 RTLIB::Libcall Call_I8,
121 RTLIB::Libcall Call_I16,
122 RTLIB::Libcall Call_I32,
123 RTLIB::Libcall Call_I64,
124 RTLIB::Libcall Call_I128);
125 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
126 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
128 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
129 SDValue ExpandBUILD_VECTOR(SDNode *Node);
130 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
131 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
132 SmallVectorImpl<SDValue> &Results);
133 SDValue ExpandFCOPYSIGN(SDNode *Node);
134 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
136 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
138 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
141 SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
142 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
144 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
145 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
146 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
148 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
150 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
152 void ExpandNode(SDNode *Node);
153 void PromoteNode(SDNode *Node);
156 // Node replacement helpers
157 void ReplacedNode(SDNode *N) {
158 LegalizedNodes.erase(N);
160 UpdatedNodes->insert(N);
162 void ReplaceNode(SDNode *Old, SDNode *New) {
163 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
164 dbgs() << " with: "; New->dump(&DAG));
166 assert(Old->getNumValues() == New->getNumValues() &&
167 "Replacing one node with another that produces a different number "
169 DAG.ReplaceAllUsesWith(Old, New);
170 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i)
171 DAG.TransferDbgValues(SDValue(Old, i), SDValue(New, i));
173 UpdatedNodes->insert(New);
176 void ReplaceNode(SDValue Old, SDValue New) {
177 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
178 dbgs() << " with: "; New->dump(&DAG));
180 DAG.ReplaceAllUsesWith(Old, New);
181 DAG.TransferDbgValues(Old, New);
183 UpdatedNodes->insert(New.getNode());
184 ReplacedNode(Old.getNode());
186 void ReplaceNode(SDNode *Old, const SDValue *New) {
187 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
189 DAG.ReplaceAllUsesWith(Old, New);
190 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
191 DEBUG(dbgs() << (i == 0 ? " with: "
194 DAG.TransferDbgValues(SDValue(Old, i), New[i]);
196 UpdatedNodes->insert(New[i].getNode());
203 /// Return a vector shuffle operation which
204 /// performs the same shuffe in terms of order or result bytes, but on a type
205 /// whose vector element type is narrower than the original shuffle type.
206 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
208 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
209 SDValue N1, SDValue N2,
210 ArrayRef<int> Mask) const {
211 unsigned NumMaskElts = VT.getVectorNumElements();
212 unsigned NumDestElts = NVT.getVectorNumElements();
213 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
215 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
217 if (NumEltsGrowth == 1)
218 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
220 SmallVector<int, 8> NewMask;
221 for (unsigned i = 0; i != NumMaskElts; ++i) {
223 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
225 NewMask.push_back(-1);
227 NewMask.push_back(Idx * NumEltsGrowth + j);
230 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
231 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
232 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
235 /// Expands the ConstantFP node to an integer constant or
236 /// a load from the constant pool.
238 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
242 // If a FP immediate is precise when represented as a float and if the
243 // target can do an extending load from float to double, we put it into
244 // the constant pool as a float, even if it's is statically typed as a
245 // double. This shrinks FP constants and canonicalizes them for targets where
246 // an FP extending load is the same cost as a normal load (such as on the x87
247 // fp stack or PPC FP unit).
248 EVT VT = CFP->getValueType(0);
249 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
251 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
252 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), dl,
253 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
258 while (SVT != MVT::f32 && SVT != MVT::f16) {
259 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
260 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
261 // Only do this if the target has a native EXTLOAD instruction from
263 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
264 TLI.ShouldShrinkFPConstant(OrigVT)) {
265 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
266 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
272 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
273 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
276 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
278 CPIdx, MachinePointerInfo::getConstantPool(),
279 VT, false, false, false, Alignment);
283 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
284 MachinePointerInfo::getConstantPool(), false, false, false,
289 /// Expands an unaligned store to 2 half-size stores.
290 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
291 const TargetLowering &TLI,
292 SelectionDAGLegalize *DAGLegalize) {
293 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
294 "unaligned indexed stores not implemented!");
295 SDValue Chain = ST->getChain();
296 SDValue Ptr = ST->getBasePtr();
297 SDValue Val = ST->getValue();
298 EVT VT = Val.getValueType();
299 int Alignment = ST->getAlignment();
300 unsigned AS = ST->getAddressSpace();
303 if (ST->getMemoryVT().isFloatingPoint() ||
304 ST->getMemoryVT().isVector()) {
305 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
306 if (TLI.isTypeLegal(intVT)) {
307 // Expand to a bitconvert of the value to the integer type of the
308 // same size, then a (misaligned) int store.
309 // FIXME: Does not handle truncating floating point stores!
310 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
311 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
312 ST->isVolatile(), ST->isNonTemporal(), Alignment);
313 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
316 // Do a (aligned) store to a stack slot, then copy from the stack slot
317 // to the final destination using (unaligned) integer loads and stores.
318 EVT StoredVT = ST->getMemoryVT();
320 TLI.getRegisterType(*DAG.getContext(),
321 EVT::getIntegerVT(*DAG.getContext(),
322 StoredVT.getSizeInBits()));
323 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
324 unsigned RegBytes = RegVT.getSizeInBits() / 8;
325 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
327 // Make sure the stack slot is also aligned for the register type.
328 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
330 // Perform the original store, only redirected to the stack slot.
331 SDValue Store = DAG.getTruncStore(Chain, dl,
332 Val, StackPtr, MachinePointerInfo(),
333 StoredVT, false, false, 0);
334 SDValue Increment = DAG.getConstant(RegBytes, dl, TLI.getPointerTy(AS));
335 SmallVector<SDValue, 8> Stores;
338 // Do all but one copies using the full register width.
339 for (unsigned i = 1; i < NumRegs; i++) {
340 // Load one integer register's worth from the stack slot.
341 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
342 MachinePointerInfo(),
343 false, false, false, 0);
344 // Store it to the final location. Remember the store.
345 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
346 ST->getPointerInfo().getWithOffset(Offset),
347 ST->isVolatile(), ST->isNonTemporal(),
348 MinAlign(ST->getAlignment(), Offset)));
349 // Increment the pointers.
351 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
353 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
356 // The last store may be partial. Do a truncating store. On big-endian
357 // machines this requires an extending load from the stack slot to ensure
358 // that the bits are in the right place.
359 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
360 8 * (StoredBytes - Offset));
362 // Load from the stack slot.
363 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
364 MachinePointerInfo(),
365 MemVT, false, false, false, 0);
367 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
369 .getWithOffset(Offset),
370 MemVT, ST->isVolatile(),
372 MinAlign(ST->getAlignment(), Offset),
374 // The order of the stores doesn't matter - say it with a TokenFactor.
375 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
376 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
379 assert(ST->getMemoryVT().isInteger() &&
380 !ST->getMemoryVT().isVector() &&
381 "Unaligned store of unknown type.");
382 // Get the half-size VT
383 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
384 int NumBits = NewStoredVT.getSizeInBits();
385 int IncrementSize = NumBits / 8;
387 // Divide the stored value in two parts.
388 SDValue ShiftAmount = DAG.getConstant(NumBits, dl,
389 TLI.getShiftAmountTy(Val.getValueType()));
391 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
393 // Store the two parts
394 SDValue Store1, Store2;
395 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
396 ST->getPointerInfo(), NewStoredVT,
397 ST->isVolatile(), ST->isNonTemporal(), Alignment);
399 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
400 DAG.getConstant(IncrementSize, dl, TLI.getPointerTy(AS)));
401 Alignment = MinAlign(Alignment, IncrementSize);
402 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
403 ST->getPointerInfo().getWithOffset(IncrementSize),
404 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
405 Alignment, ST->getAAInfo());
408 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
409 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
412 /// Expands an unaligned load to 2 half-size loads.
414 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
415 const TargetLowering &TLI,
416 SDValue &ValResult, SDValue &ChainResult) {
417 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
418 "unaligned indexed loads not implemented!");
419 SDValue Chain = LD->getChain();
420 SDValue Ptr = LD->getBasePtr();
421 EVT VT = LD->getValueType(0);
422 EVT LoadedVT = LD->getMemoryVT();
424 if (VT.isFloatingPoint() || VT.isVector()) {
425 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
426 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
427 // Expand to a (misaligned) integer load of the same size,
428 // then bitconvert to floating point or vector.
429 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
430 LD->getMemOperand());
431 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
433 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
434 ISD::ANY_EXTEND, dl, VT, Result);
441 // Copy the value to a (aligned) stack slot using (unaligned) integer
442 // loads and stores, then do a (aligned) load from the stack slot.
443 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
444 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
445 unsigned RegBytes = RegVT.getSizeInBits() / 8;
446 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
448 // Make sure the stack slot is also aligned for the register type.
449 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
451 SDValue Increment = DAG.getConstant(RegBytes, dl, TLI.getPointerTy());
452 SmallVector<SDValue, 8> Stores;
453 SDValue StackPtr = StackBase;
456 // Do all but one copies using the full register width.
457 for (unsigned i = 1; i < NumRegs; i++) {
458 // Load one integer register's worth from the original location.
459 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
460 LD->getPointerInfo().getWithOffset(Offset),
461 LD->isVolatile(), LD->isNonTemporal(),
463 MinAlign(LD->getAlignment(), Offset),
465 // Follow the load with a store to the stack slot. Remember the store.
466 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
467 MachinePointerInfo(), false, false, 0));
468 // Increment the pointers.
470 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
471 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
475 // The last copy may be partial. Do an extending load.
476 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
477 8 * (LoadedBytes - Offset));
478 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
479 LD->getPointerInfo().getWithOffset(Offset),
480 MemVT, LD->isVolatile(),
483 MinAlign(LD->getAlignment(), Offset),
485 // Follow the load with a store to the stack slot. Remember the store.
486 // On big-endian machines this requires a truncating store to ensure
487 // that the bits end up in the right place.
488 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
489 MachinePointerInfo(), MemVT,
492 // The order of the stores doesn't matter - say it with a TokenFactor.
493 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
495 // Finally, perform the original load only redirected to the stack slot.
496 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
497 MachinePointerInfo(), LoadedVT, false,false, false,
500 // Callers expect a MERGE_VALUES node.
505 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
506 "Unaligned load of unsupported type.");
508 // Compute the new VT that is half the size of the old one. This is an
510 unsigned NumBits = LoadedVT.getSizeInBits();
512 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
515 unsigned Alignment = LD->getAlignment();
516 unsigned IncrementSize = NumBits / 8;
517 ISD::LoadExtType HiExtType = LD->getExtensionType();
519 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
520 if (HiExtType == ISD::NON_EXTLOAD)
521 HiExtType = ISD::ZEXTLOAD;
523 // Load the value in two parts
525 if (TLI.isLittleEndian()) {
526 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
527 NewLoadedVT, LD->isVolatile(),
528 LD->isNonTemporal(), LD->isInvariant(), Alignment,
530 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
531 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
532 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
533 LD->getPointerInfo().getWithOffset(IncrementSize),
534 NewLoadedVT, LD->isVolatile(),
535 LD->isNonTemporal(),LD->isInvariant(),
536 MinAlign(Alignment, IncrementSize), LD->getAAInfo());
538 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
539 NewLoadedVT, LD->isVolatile(),
540 LD->isNonTemporal(), LD->isInvariant(), Alignment,
542 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
543 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
544 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
545 LD->getPointerInfo().getWithOffset(IncrementSize),
546 NewLoadedVT, LD->isVolatile(),
547 LD->isNonTemporal(), LD->isInvariant(),
548 MinAlign(Alignment, IncrementSize), LD->getAAInfo());
551 // aggregate the two parts
552 SDValue ShiftAmount = DAG.getConstant(NumBits, dl,
553 TLI.getShiftAmountTy(Hi.getValueType()));
554 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
555 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
557 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
564 /// Some target cannot handle a variable insertion index for the
565 /// INSERT_VECTOR_ELT instruction. In this case, it
566 /// is necessary to spill the vector being inserted into to memory, perform
567 /// the insert there, and then read the result back.
568 SDValue SelectionDAGLegalize::
569 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
575 // If the target doesn't support this, we have to spill the input vector
576 // to a temporary stack slot, update the element, then reload it. This is
577 // badness. We could also load the value into a vector register (either
578 // with a "move to register" or "extload into register" instruction, then
579 // permute it into place, if the idx is a constant and if the idx is
580 // supported by the target.
581 EVT VT = Tmp1.getValueType();
582 EVT EltVT = VT.getVectorElementType();
583 EVT IdxVT = Tmp3.getValueType();
584 EVT PtrVT = TLI.getPointerTy();
585 SDValue StackPtr = DAG.CreateStackTemporary(VT);
587 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
590 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
591 MachinePointerInfo::getFixedStack(SPFI),
594 // Truncate or zero extend offset to target pointer type.
595 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
596 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
597 // Add the offset to the index.
598 unsigned EltSize = EltVT.getSizeInBits()/8;
599 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,
600 DAG.getConstant(EltSize, dl, IdxVT));
601 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
602 // Store the scalar value.
603 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
605 // Load the updated vector.
606 return DAG.getLoad(VT, dl, Ch, StackPtr,
607 MachinePointerInfo::getFixedStack(SPFI), false, false,
612 SDValue SelectionDAGLegalize::
613 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
614 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
615 // SCALAR_TO_VECTOR requires that the type of the value being inserted
616 // match the element type of the vector being created, except for
617 // integers in which case the inserted value can be over width.
618 EVT EltVT = Vec.getValueType().getVectorElementType();
619 if (Val.getValueType() == EltVT ||
620 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
621 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
622 Vec.getValueType(), Val);
624 unsigned NumElts = Vec.getValueType().getVectorNumElements();
625 // We generate a shuffle of InVec and ScVec, so the shuffle mask
626 // should be 0,1,2,3,4,5... with the appropriate element replaced with
628 SmallVector<int, 8> ShufOps;
629 for (unsigned i = 0; i != NumElts; ++i)
630 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
632 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
636 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
639 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
640 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
641 // FIXME: We shouldn't do this for TargetConstantFP's.
642 // FIXME: move this to the DAG Combiner! Note that we can't regress due
643 // to phase ordering between legalized code and the dag combiner. This
644 // probably means that we need to integrate dag combiner and legalizer
646 // We generally can't do this one for long doubles.
647 SDValue Chain = ST->getChain();
648 SDValue Ptr = ST->getBasePtr();
649 unsigned Alignment = ST->getAlignment();
650 bool isVolatile = ST->isVolatile();
651 bool isNonTemporal = ST->isNonTemporal();
652 AAMDNodes AAInfo = ST->getAAInfo();
654 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
655 if (CFP->getValueType(0) == MVT::f32 &&
656 TLI.isTypeLegal(MVT::i32)) {
657 SDValue Con = DAG.getConstant(CFP->getValueAPF().
658 bitcastToAPInt().zextOrTrunc(32),
659 SDLoc(CFP), MVT::i32);
660 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
661 isVolatile, isNonTemporal, Alignment, AAInfo);
664 if (CFP->getValueType(0) == MVT::f64) {
665 // If this target supports 64-bit registers, do a single 64-bit store.
666 if (TLI.isTypeLegal(MVT::i64)) {
667 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
668 zextOrTrunc(64), SDLoc(CFP), MVT::i64);
669 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
670 isVolatile, isNonTemporal, Alignment, AAInfo);
673 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
674 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
675 // stores. If the target supports neither 32- nor 64-bits, this
676 // xform is certainly not worth it.
677 const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt();
678 SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32);
679 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32);
680 if (TLI.isBigEndian()) std::swap(Lo, Hi);
682 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
683 isNonTemporal, Alignment, AAInfo);
684 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
685 DAG.getConstant(4, dl, Ptr.getValueType()));
686 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
687 ST->getPointerInfo().getWithOffset(4),
688 isVolatile, isNonTemporal, MinAlign(Alignment, 4U),
691 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
695 return SDValue(nullptr, 0);
698 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
699 StoreSDNode *ST = cast<StoreSDNode>(Node);
700 SDValue Chain = ST->getChain();
701 SDValue Ptr = ST->getBasePtr();
704 unsigned Alignment = ST->getAlignment();
705 bool isVolatile = ST->isVolatile();
706 bool isNonTemporal = ST->isNonTemporal();
707 AAMDNodes AAInfo = ST->getAAInfo();
709 if (!ST->isTruncatingStore()) {
710 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
711 ReplaceNode(ST, OptStore);
716 SDValue Value = ST->getValue();
717 MVT VT = Value.getSimpleValueType();
718 switch (TLI.getOperationAction(ISD::STORE, VT)) {
719 default: llvm_unreachable("This action is not supported yet!");
720 case TargetLowering::Legal: {
721 // If this is an unaligned store and the target doesn't support it,
723 unsigned AS = ST->getAddressSpace();
724 unsigned Align = ST->getAlignment();
725 if (!TLI.allowsMisalignedMemoryAccesses(ST->getMemoryVT(), AS, Align)) {
726 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
727 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
728 if (Align < ABIAlignment)
729 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
733 case TargetLowering::Custom: {
734 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
735 if (Res && Res != SDValue(Node, 0))
736 ReplaceNode(SDValue(Node, 0), Res);
739 case TargetLowering::Promote: {
740 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
741 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
742 "Can only promote stores to same size type");
743 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
745 DAG.getStore(Chain, dl, Value, Ptr,
746 ST->getPointerInfo(), isVolatile,
747 isNonTemporal, Alignment, AAInfo);
748 ReplaceNode(SDValue(Node, 0), Result);
755 SDValue Value = ST->getValue();
757 EVT StVT = ST->getMemoryVT();
758 unsigned StWidth = StVT.getSizeInBits();
760 if (StWidth != StVT.getStoreSizeInBits()) {
761 // Promote to a byte-sized store with upper bits zero if not
762 // storing an integral number of bytes. For example, promote
763 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
764 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
765 StVT.getStoreSizeInBits());
766 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
768 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
769 NVT, isVolatile, isNonTemporal, Alignment, AAInfo);
770 ReplaceNode(SDValue(Node, 0), Result);
771 } else if (StWidth & (StWidth - 1)) {
772 // If not storing a power-of-2 number of bits, expand as two stores.
773 assert(!StVT.isVector() && "Unsupported truncstore!");
774 unsigned RoundWidth = 1 << Log2_32(StWidth);
775 assert(RoundWidth < StWidth);
776 unsigned ExtraWidth = StWidth - RoundWidth;
777 assert(ExtraWidth < RoundWidth);
778 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
779 "Store size not an integral number of bytes!");
780 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
781 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
783 unsigned IncrementSize;
785 if (TLI.isLittleEndian()) {
786 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
787 // Store the bottom RoundWidth bits.
788 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
790 isVolatile, isNonTemporal, Alignment,
793 // Store the remaining ExtraWidth bits.
794 IncrementSize = RoundWidth / 8;
795 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
796 DAG.getConstant(IncrementSize, dl,
797 Ptr.getValueType()));
798 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
799 DAG.getConstant(RoundWidth, dl,
800 TLI.getShiftAmountTy(Value.getValueType())));
801 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
802 ST->getPointerInfo().getWithOffset(IncrementSize),
803 ExtraVT, isVolatile, isNonTemporal,
804 MinAlign(Alignment, IncrementSize), AAInfo);
806 // Big endian - avoid unaligned stores.
807 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
808 // Store the top RoundWidth bits.
809 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
810 DAG.getConstant(ExtraWidth, dl,
811 TLI.getShiftAmountTy(Value.getValueType())));
812 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
813 RoundVT, isVolatile, isNonTemporal, Alignment,
816 // Store the remaining ExtraWidth bits.
817 IncrementSize = RoundWidth / 8;
818 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
819 DAG.getConstant(IncrementSize, dl,
820 Ptr.getValueType()));
821 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
822 ST->getPointerInfo().getWithOffset(IncrementSize),
823 ExtraVT, isVolatile, isNonTemporal,
824 MinAlign(Alignment, IncrementSize), AAInfo);
827 // The order of the stores doesn't matter.
828 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
829 ReplaceNode(SDValue(Node, 0), Result);
831 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(),
832 StVT.getSimpleVT())) {
833 default: llvm_unreachable("This action is not supported yet!");
834 case TargetLowering::Legal: {
835 unsigned AS = ST->getAddressSpace();
836 unsigned Align = ST->getAlignment();
837 // If this is an unaligned store and the target doesn't support it,
839 if (!TLI.allowsMisalignedMemoryAccesses(ST->getMemoryVT(), AS, Align)) {
840 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
841 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
842 if (Align < ABIAlignment)
843 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
847 case TargetLowering::Custom: {
848 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
849 if (Res && Res != SDValue(Node, 0))
850 ReplaceNode(SDValue(Node, 0), Res);
853 case TargetLowering::Expand:
854 assert(!StVT.isVector() &&
855 "Vector Stores are handled in LegalizeVectorOps");
857 // TRUNCSTORE:i16 i32 -> STORE i16
858 assert(TLI.isTypeLegal(StVT) &&
859 "Do not know how to expand this store!");
860 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
862 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
863 isVolatile, isNonTemporal, Alignment, AAInfo);
864 ReplaceNode(SDValue(Node, 0), Result);
871 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
872 LoadSDNode *LD = cast<LoadSDNode>(Node);
873 SDValue Chain = LD->getChain(); // The chain.
874 SDValue Ptr = LD->getBasePtr(); // The base pointer.
875 SDValue Value; // The value returned by the load op.
878 ISD::LoadExtType ExtType = LD->getExtensionType();
879 if (ExtType == ISD::NON_EXTLOAD) {
880 MVT VT = Node->getSimpleValueType(0);
881 SDValue RVal = SDValue(Node, 0);
882 SDValue RChain = SDValue(Node, 1);
884 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
885 default: llvm_unreachable("This action is not supported yet!");
886 case TargetLowering::Legal: {
887 unsigned AS = LD->getAddressSpace();
888 unsigned Align = LD->getAlignment();
889 // If this is an unaligned load and the target doesn't support it,
891 if (!TLI.allowsMisalignedMemoryAccesses(LD->getMemoryVT(), AS, Align)) {
892 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
893 unsigned ABIAlignment =
894 TLI.getDataLayout()->getABITypeAlignment(Ty);
895 if (Align < ABIAlignment){
896 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
901 case TargetLowering::Custom: {
902 SDValue Res = TLI.LowerOperation(RVal, DAG);
905 RChain = Res.getValue(1);
909 case TargetLowering::Promote: {
910 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
911 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
912 "Can only promote loads to same size type");
914 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
915 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
916 RChain = Res.getValue(1);
920 if (RChain.getNode() != Node) {
921 assert(RVal.getNode() != Node && "Load must be completely replaced");
922 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
923 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
925 UpdatedNodes->insert(RVal.getNode());
926 UpdatedNodes->insert(RChain.getNode());
933 EVT SrcVT = LD->getMemoryVT();
934 unsigned SrcWidth = SrcVT.getSizeInBits();
935 unsigned Alignment = LD->getAlignment();
936 bool isVolatile = LD->isVolatile();
937 bool isNonTemporal = LD->isNonTemporal();
938 bool isInvariant = LD->isInvariant();
939 AAMDNodes AAInfo = LD->getAAInfo();
941 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
942 // Some targets pretend to have an i1 loading operation, and actually
943 // load an i8. This trick is correct for ZEXTLOAD because the top 7
944 // bits are guaranteed to be zero; it helps the optimizers understand
945 // that these bits are zero. It is also useful for EXTLOAD, since it
946 // tells the optimizers that those bits are undefined. It would be
947 // nice to have an effective generic way of getting these benefits...
948 // Until such a way is found, don't insist on promoting i1 here.
950 TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
951 TargetLowering::Promote)) {
952 // Promote to a byte-sized load if not loading an integral number of
953 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
954 unsigned NewWidth = SrcVT.getStoreSizeInBits();
955 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
958 // The extra bits are guaranteed to be zero, since we stored them that
959 // way. A zext load from NVT thus automatically gives zext from SrcVT.
961 ISD::LoadExtType NewExtType =
962 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
965 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
966 Chain, Ptr, LD->getPointerInfo(),
967 NVT, isVolatile, isNonTemporal, isInvariant, Alignment,
970 Ch = Result.getValue(1); // The chain.
972 if (ExtType == ISD::SEXTLOAD)
973 // Having the top bits zero doesn't help when sign extending.
974 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
975 Result.getValueType(),
976 Result, DAG.getValueType(SrcVT));
977 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
978 // All the top bits are guaranteed to be zero - inform the optimizers.
979 Result = DAG.getNode(ISD::AssertZext, dl,
980 Result.getValueType(), Result,
981 DAG.getValueType(SrcVT));
985 } else if (SrcWidth & (SrcWidth - 1)) {
986 // If not loading a power-of-2 number of bits, expand as two loads.
987 assert(!SrcVT.isVector() && "Unsupported extload!");
988 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
989 assert(RoundWidth < SrcWidth);
990 unsigned ExtraWidth = SrcWidth - RoundWidth;
991 assert(ExtraWidth < RoundWidth);
992 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
993 "Load size not an integral number of bytes!");
994 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
995 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
997 unsigned IncrementSize;
999 if (TLI.isLittleEndian()) {
1000 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1001 // Load the bottom RoundWidth bits.
1002 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1004 LD->getPointerInfo(), RoundVT, isVolatile,
1005 isNonTemporal, isInvariant, Alignment, AAInfo);
1007 // Load the remaining ExtraWidth bits.
1008 IncrementSize = RoundWidth / 8;
1009 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1010 DAG.getConstant(IncrementSize, dl,
1011 Ptr.getValueType()));
1012 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1013 LD->getPointerInfo().getWithOffset(IncrementSize),
1014 ExtraVT, isVolatile, isNonTemporal, isInvariant,
1015 MinAlign(Alignment, IncrementSize), AAInfo);
1017 // Build a factor node to remember that this load is independent of
1019 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1022 // Move the top bits to the right place.
1023 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1024 DAG.getConstant(RoundWidth, dl,
1025 TLI.getShiftAmountTy(Hi.getValueType())));
1027 // Join the hi and lo parts.
1028 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1030 // Big endian - avoid unaligned loads.
1031 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1032 // Load the top RoundWidth bits.
1033 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1034 LD->getPointerInfo(), RoundVT, isVolatile,
1035 isNonTemporal, isInvariant, Alignment, AAInfo);
1037 // Load the remaining ExtraWidth bits.
1038 IncrementSize = RoundWidth / 8;
1039 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1040 DAG.getConstant(IncrementSize, dl,
1041 Ptr.getValueType()));
1042 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1043 dl, Node->getValueType(0), Chain, Ptr,
1044 LD->getPointerInfo().getWithOffset(IncrementSize),
1045 ExtraVT, isVolatile, isNonTemporal, isInvariant,
1046 MinAlign(Alignment, IncrementSize), AAInfo);
1048 // Build a factor node to remember that this load is independent of
1050 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1053 // Move the top bits to the right place.
1054 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1055 DAG.getConstant(ExtraWidth, dl,
1056 TLI.getShiftAmountTy(Hi.getValueType())));
1058 // Join the hi and lo parts.
1059 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1064 bool isCustom = false;
1065 switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0),
1066 SrcVT.getSimpleVT())) {
1067 default: llvm_unreachable("This action is not supported yet!");
1068 case TargetLowering::Custom:
1071 case TargetLowering::Legal: {
1072 Value = SDValue(Node, 0);
1073 Chain = SDValue(Node, 1);
1076 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1077 if (Res.getNode()) {
1079 Chain = Res.getValue(1);
1082 // If this is an unaligned load and the target doesn't support
1084 EVT MemVT = LD->getMemoryVT();
1085 unsigned AS = LD->getAddressSpace();
1086 unsigned Align = LD->getAlignment();
1087 if (!TLI.allowsMisalignedMemoryAccesses(MemVT, AS, Align)) {
1088 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1089 unsigned ABIAlignment = TLI.getDataLayout()->getABITypeAlignment(Ty);
1090 if (Align < ABIAlignment){
1091 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, Value, Chain);
1097 case TargetLowering::Expand:
1098 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, Node->getValueType(0), SrcVT)) {
1099 // If the source type is not legal, see if there is a legal extload to
1100 // an intermediate type that we can then extend further.
1101 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
1102 if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
1103 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) {
1104 // If we are loading a legal type, this is a non-extload followed by a
1106 ISD::LoadExtType MidExtType =
1107 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
1109 SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr,
1110 SrcVT, LD->getMemOperand());
1112 ISD::getExtForLoadExtType(SrcVT.isFloatingPoint(), ExtType);
1113 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1114 Chain = Load.getValue(1);
1119 assert(!SrcVT.isVector() &&
1120 "Vector Loads are handled in LegalizeVectorOps");
1122 // FIXME: This does not work for vectors on most targets. Sign-
1123 // and zero-extend operations are currently folded into extending
1124 // loads, whether they are legal or not, and then we end up here
1125 // without any support for legalizing them.
1126 assert(ExtType != ISD::EXTLOAD &&
1127 "EXTLOAD should always be supported!");
1128 // Turn the unsupported load into an EXTLOAD followed by an
1129 // explicit zero/sign extend inreg.
1130 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1131 Node->getValueType(0),
1133 LD->getMemOperand());
1135 if (ExtType == ISD::SEXTLOAD)
1136 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1137 Result.getValueType(),
1138 Result, DAG.getValueType(SrcVT));
1140 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1142 Chain = Result.getValue(1);
1147 // Since loads produce two values, make sure to remember that we legalized
1149 if (Chain.getNode() != Node) {
1150 assert(Value.getNode() != Node && "Load must be completely replaced");
1151 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1152 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1154 UpdatedNodes->insert(Value.getNode());
1155 UpdatedNodes->insert(Chain.getNode());
1161 /// Return a legal replacement for the given operation, with all legal operands.
1162 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1163 DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
1165 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1169 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1170 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1171 TargetLowering::TypeLegal &&
1172 "Unexpected illegal type!");
1174 for (const SDValue &Op : Node->op_values())
1175 assert((TLI.getTypeAction(*DAG.getContext(),
1176 Op.getValueType()) == TargetLowering::TypeLegal ||
1177 Op.getOpcode() == ISD::TargetConstant) &&
1178 "Unexpected illegal type!");
1181 // Figure out the correct action; the way to query this varies by opcode
1182 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1183 bool SimpleFinishLegalizing = true;
1184 switch (Node->getOpcode()) {
1185 case ISD::INTRINSIC_W_CHAIN:
1186 case ISD::INTRINSIC_WO_CHAIN:
1187 case ISD::INTRINSIC_VOID:
1188 case ISD::STACKSAVE:
1189 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1192 Action = TLI.getOperationAction(Node->getOpcode(),
1193 Node->getValueType(0));
1194 if (Action != TargetLowering::Promote)
1195 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1197 case ISD::FP_TO_FP16:
1198 case ISD::SINT_TO_FP:
1199 case ISD::UINT_TO_FP:
1200 case ISD::EXTRACT_VECTOR_ELT:
1201 Action = TLI.getOperationAction(Node->getOpcode(),
1202 Node->getOperand(0).getValueType());
1204 case ISD::FP_ROUND_INREG:
1205 case ISD::SIGN_EXTEND_INREG: {
1206 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1207 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1210 case ISD::ATOMIC_STORE: {
1211 Action = TLI.getOperationAction(Node->getOpcode(),
1212 Node->getOperand(2).getValueType());
1215 case ISD::SELECT_CC:
1218 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1219 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1220 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1221 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1222 ISD::CondCode CCCode =
1223 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1224 Action = TLI.getCondCodeAction(CCCode, OpVT);
1225 if (Action == TargetLowering::Legal) {
1226 if (Node->getOpcode() == ISD::SELECT_CC)
1227 Action = TLI.getOperationAction(Node->getOpcode(),
1228 Node->getValueType(0));
1230 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1236 // FIXME: Model these properly. LOAD and STORE are complicated, and
1237 // STORE expects the unlegalized operand in some cases.
1238 SimpleFinishLegalizing = false;
1240 case ISD::CALLSEQ_START:
1241 case ISD::CALLSEQ_END:
1242 // FIXME: This shouldn't be necessary. These nodes have special properties
1243 // dealing with the recursive nature of legalization. Removing this
1244 // special case should be done as part of making LegalizeDAG non-recursive.
1245 SimpleFinishLegalizing = false;
1247 case ISD::EXTRACT_ELEMENT:
1248 case ISD::FLT_ROUNDS_:
1250 case ISD::MERGE_VALUES:
1251 case ISD::EH_RETURN:
1252 case ISD::FRAME_TO_ARGS_OFFSET:
1253 case ISD::EH_SJLJ_SETJMP:
1254 case ISD::EH_SJLJ_LONGJMP:
1255 // These operations lie about being legal: when they claim to be legal,
1256 // they should actually be expanded.
1257 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1258 if (Action == TargetLowering::Legal)
1259 Action = TargetLowering::Expand;
1261 case ISD::INIT_TRAMPOLINE:
1262 case ISD::ADJUST_TRAMPOLINE:
1263 case ISD::FRAMEADDR:
1264 case ISD::RETURNADDR:
1265 // These operations lie about being legal: when they claim to be legal,
1266 // they should actually be custom-lowered.
1267 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1268 if (Action == TargetLowering::Legal)
1269 Action = TargetLowering::Custom;
1271 case ISD::READ_REGISTER:
1272 case ISD::WRITE_REGISTER:
1273 // Named register is legal in the DAG, but blocked by register name
1274 // selection if not implemented by target (to chose the correct register)
1275 // They'll be converted to Copy(To/From)Reg.
1276 Action = TargetLowering::Legal;
1278 case ISD::DEBUGTRAP:
1279 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1280 if (Action == TargetLowering::Expand) {
1281 // replace ISD::DEBUGTRAP with ISD::TRAP
1283 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1284 Node->getOperand(0));
1285 ReplaceNode(Node, NewVal.getNode());
1286 LegalizeOp(NewVal.getNode());
1292 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1293 Action = TargetLowering::Legal;
1295 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1300 if (SimpleFinishLegalizing) {
1301 SDNode *NewNode = Node;
1302 switch (Node->getOpcode()) {
1309 // Legalizing shifts/rotates requires adjusting the shift amount
1310 // to the appropriate width.
1311 if (!Node->getOperand(1).getValueType().isVector()) {
1313 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1314 Node->getOperand(1));
1315 HandleSDNode Handle(SAO);
1316 LegalizeOp(SAO.getNode());
1317 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1321 case ISD::SRL_PARTS:
1322 case ISD::SRA_PARTS:
1323 case ISD::SHL_PARTS:
1324 // Legalizing shifts/rotates requires adjusting the shift amount
1325 // to the appropriate width.
1326 if (!Node->getOperand(2).getValueType().isVector()) {
1328 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1329 Node->getOperand(2));
1330 HandleSDNode Handle(SAO);
1331 LegalizeOp(SAO.getNode());
1332 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1333 Node->getOperand(1),
1339 if (NewNode != Node) {
1340 ReplaceNode(Node, NewNode);
1344 case TargetLowering::Legal:
1346 case TargetLowering::Custom: {
1347 // FIXME: The handling for custom lowering with multiple results is
1349 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1350 if (Res.getNode()) {
1351 if (!(Res.getNode() != Node || Res.getResNo() != 0))
1354 if (Node->getNumValues() == 1) {
1355 // We can just directly replace this node with the lowered value.
1356 ReplaceNode(SDValue(Node, 0), Res);
1360 SmallVector<SDValue, 8> ResultVals;
1361 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1362 ResultVals.push_back(Res.getValue(i));
1363 ReplaceNode(Node, ResultVals.data());
1368 case TargetLowering::Expand:
1371 case TargetLowering::Promote:
1377 switch (Node->getOpcode()) {
1384 llvm_unreachable("Do not know how to legalize this operator!");
1386 case ISD::CALLSEQ_START:
1387 case ISD::CALLSEQ_END:
1390 return LegalizeLoadOps(Node);
1393 return LegalizeStoreOps(Node);
1398 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1399 SDValue Vec = Op.getOperand(0);
1400 SDValue Idx = Op.getOperand(1);
1403 // Before we generate a new store to a temporary stack slot, see if there is
1404 // already one that we can use. There often is because when we scalarize
1405 // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1406 // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1407 // the vector. If all are expanded here, we don't want one store per vector
1409 SDValue StackPtr, Ch;
1410 for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1411 UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1413 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1414 if (ST->isIndexed() || ST->isTruncatingStore() ||
1415 ST->getValue() != Vec)
1418 // Make sure that nothing else could have stored into the destination of
1420 if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1423 StackPtr = ST->getBasePtr();
1424 Ch = SDValue(ST, 0);
1429 if (!Ch.getNode()) {
1430 // Store the value to a temporary stack slot, then LOAD the returned part.
1431 StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1432 Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1433 MachinePointerInfo(), false, false, 0);
1436 // Add the offset to the index.
1438 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1439 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1440 DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
1442 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1443 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1447 if (Op.getValueType().isVector())
1448 NewLoad = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,
1449 MachinePointerInfo(), false, false, false, 0);
1451 NewLoad = DAG.getExtLoad(
1452 ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, MachinePointerInfo(),
1453 Vec.getValueType().getVectorElementType(), false, false, false, 0);
1455 // Replace the chain going out of the store, by the one out of the load.
1456 DAG.ReplaceAllUsesOfValueWith(Ch, SDValue(NewLoad.getNode(), 1));
1458 // We introduced a cycle though, so update the loads operands, making sure
1459 // to use the original store's chain as an incoming chain.
1460 SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1462 NewLoadOperands[0] = Ch;
1464 SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0);
1468 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1469 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1471 SDValue Vec = Op.getOperand(0);
1472 SDValue Part = Op.getOperand(1);
1473 SDValue Idx = Op.getOperand(2);
1476 // Store the value to a temporary stack slot, then LOAD the returned part.
1478 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1479 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1480 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1482 // First store the whole vector.
1483 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1486 // Then store the inserted part.
1488 // Add the offset to the index.
1490 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1492 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1493 DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
1494 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1496 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1499 // Store the subvector.
1500 Ch = DAG.getStore(Ch, dl, Part, SubStackPtr,
1501 MachinePointerInfo(), false, false, 0);
1503 // Finally, load the updated vector.
1504 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1505 false, false, false, 0);
1508 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1509 // We can't handle this case efficiently. Allocate a sufficiently
1510 // aligned object on the stack, store each element into it, then load
1511 // the result as a vector.
1512 // Create the stack frame object.
1513 EVT VT = Node->getValueType(0);
1514 EVT EltVT = VT.getVectorElementType();
1516 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1517 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1518 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1520 // Emit a store of each element to the stack slot.
1521 SmallVector<SDValue, 8> Stores;
1522 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1523 // Store (in the right endianness) the elements to memory.
1524 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1525 // Ignore undef elements.
1526 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1528 unsigned Offset = TypeByteSize*i;
1530 SDValue Idx = DAG.getConstant(Offset, dl, FIPtr.getValueType());
1531 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1533 // If the destination vector element type is narrower than the source
1534 // element type, only store the bits necessary.
1535 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1536 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1537 Node->getOperand(i), Idx,
1538 PtrInfo.getWithOffset(Offset),
1539 EltVT, false, false, 0));
1541 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1542 Node->getOperand(i), Idx,
1543 PtrInfo.getWithOffset(Offset),
1548 if (!Stores.empty()) // Not all undef elements?
1549 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1551 StoreChain = DAG.getEntryNode();
1553 // Result is a load from the stack slot.
1554 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1555 false, false, false, 0);
1558 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1560 SDValue Tmp1 = Node->getOperand(0);
1561 SDValue Tmp2 = Node->getOperand(1);
1563 // Get the sign bit of the RHS. First obtain a value that has the same
1564 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1566 EVT FloatVT = Tmp2.getValueType();
1567 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1568 if (TLI.isTypeLegal(IVT)) {
1569 // Convert to an integer with the same sign bit.
1570 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1572 // Store the float to memory, then load the sign part out as an integer.
1573 MVT LoadTy = TLI.getPointerTy();
1574 // First create a temporary that is aligned for both the load and store.
1575 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1576 // Then store the float to it.
1578 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1580 if (TLI.isBigEndian()) {
1581 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1582 // Load out a legal integer with the same sign bit as the float.
1583 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1584 false, false, false, 0);
1585 } else { // Little endian
1586 SDValue LoadPtr = StackPtr;
1587 // The float may be wider than the integer we are going to load. Advance
1588 // the pointer so that the loaded integer will contain the sign bit.
1589 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1590 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1591 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), LoadPtr,
1592 DAG.getConstant(ByteOffset, dl,
1593 LoadPtr.getValueType()));
1594 // Load a legal integer containing the sign bit.
1595 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1596 false, false, false, 0);
1597 // Move the sign bit to the top bit of the loaded integer.
1598 unsigned BitShift = LoadTy.getSizeInBits() -
1599 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1600 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1602 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1603 DAG.getConstant(BitShift, dl,
1604 TLI.getShiftAmountTy(SignBit.getValueType())));
1607 // Now get the sign bit proper, by seeing whether the value is negative.
1608 SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
1610 DAG.getConstant(0, dl, SignBit.getValueType()),
1612 // Get the absolute value of the result.
1613 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1614 // Select between the nabs and abs value based on the sign bit of
1616 return DAG.getSelect(dl, AbsVal.getValueType(), SignBit,
1617 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1621 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1622 SmallVectorImpl<SDValue> &Results) {
1623 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1624 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1625 " not tell us which reg is the stack pointer!");
1627 EVT VT = Node->getValueType(0);
1628 SDValue Tmp1 = SDValue(Node, 0);
1629 SDValue Tmp2 = SDValue(Node, 1);
1630 SDValue Tmp3 = Node->getOperand(2);
1631 SDValue Chain = Tmp1.getOperand(0);
1633 // Chain the dynamic stack allocation so that it doesn't modify the stack
1634 // pointer when other instructions are using the stack.
1635 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
1637 SDValue Size = Tmp2.getOperand(1);
1638 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1639 Chain = SP.getValue(1);
1640 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1641 unsigned StackAlign =
1642 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
1643 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1644 if (Align > StackAlign)
1645 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1646 DAG.getConstant(-(uint64_t)Align, dl, VT));
1647 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1649 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
1650 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
1652 Results.push_back(Tmp1);
1653 Results.push_back(Tmp2);
1656 /// Legalize a SETCC with given LHS and RHS and condition code CC on the current
1659 /// If the SETCC has been legalized using AND / OR, then the legalized node
1660 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1661 /// will be set to false.
1663 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1664 /// then the values of LHS and RHS will be swapped, CC will be set to the
1665 /// new condition, and NeedInvert will be set to false.
1667 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1668 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1669 /// will be set to true. The caller must invert the result of the SETCC with
1670 /// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1671 /// of a true/false result.
1673 /// \returns true if the SetCC has been legalized, false if it hasn't.
1674 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1675 SDValue &LHS, SDValue &RHS,
1679 MVT OpVT = LHS.getSimpleValueType();
1680 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1682 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1683 default: llvm_unreachable("Unknown condition code action!");
1684 case TargetLowering::Legal:
1687 case TargetLowering::Expand: {
1688 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1689 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1690 std::swap(LHS, RHS);
1691 CC = DAG.getCondCode(InvCC);
1694 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1697 default: llvm_unreachable("Don't know how to expand this condition!");
1699 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1700 == TargetLowering::Legal
1701 && "If SETO is expanded, SETOEQ must be legal!");
1702 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1704 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1705 == TargetLowering::Legal
1706 && "If SETUO is expanded, SETUNE must be legal!");
1707 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1720 // If we are floating point, assign and break, otherwise fall through.
1721 if (!OpVT.isInteger()) {
1722 // We can use the 4th bit to tell if we are the unordered
1723 // or ordered version of the opcode.
1724 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1725 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1726 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1729 // Fallthrough if we are unsigned integer.
1734 // We only support using the inverted operation, which is computed above
1735 // and not a different manner of supporting expanding these cases.
1736 llvm_unreachable("Don't know how to expand this condition!");
1739 // Try inverting the result of the inverse condition.
1740 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1741 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1742 CC = DAG.getCondCode(InvCC);
1746 // If inverting the condition didn't work then we have no means to expand
1748 llvm_unreachable("Don't know how to expand this condition!");
1751 SDValue SetCC1, SetCC2;
1752 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1753 // If we aren't the ordered or unorder operation,
1754 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1755 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1756 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1758 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1759 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1760 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1762 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1771 /// Emit a store/load combination to the stack. This stores
1772 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1773 /// a load from the stack slot to DestVT, extending it if needed.
1774 /// The resultant code need not be legal.
1775 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1779 // Create the stack frame object.
1781 TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType().
1782 getTypeForEVT(*DAG.getContext()));
1783 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1785 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1786 int SPFI = StackPtrFI->getIndex();
1787 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1789 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1790 unsigned SlotSize = SlotVT.getSizeInBits();
1791 unsigned DestSize = DestVT.getSizeInBits();
1792 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1793 unsigned DestAlign = TLI.getDataLayout()->getPrefTypeAlignment(DestType);
1795 // Emit a store to the stack slot. Use a truncstore if the input value is
1796 // later than DestVT.
1799 if (SrcSize > SlotSize)
1800 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1801 PtrInfo, SlotVT, false, false, SrcAlign);
1803 assert(SrcSize == SlotSize && "Invalid store");
1804 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1805 PtrInfo, false, false, SrcAlign);
1808 // Result is a load from the stack slot.
1809 if (SlotSize == DestSize)
1810 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1811 false, false, false, DestAlign);
1813 assert(SlotSize < DestSize && "Unknown extension!");
1814 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1815 PtrInfo, SlotVT, false, false, false, DestAlign);
1818 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1820 // Create a vector sized/aligned stack slot, store the value to element #0,
1821 // then load the whole vector back out.
1822 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1824 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1825 int SPFI = StackPtrFI->getIndex();
1827 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1829 MachinePointerInfo::getFixedStack(SPFI),
1830 Node->getValueType(0).getVectorElementType(),
1832 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1833 MachinePointerInfo::getFixedStack(SPFI),
1834 false, false, false, 0);
1838 ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
1839 const TargetLowering &TLI, SDValue &Res) {
1840 unsigned NumElems = Node->getNumOperands();
1842 EVT VT = Node->getValueType(0);
1844 // Try to group the scalars into pairs, shuffle the pairs together, then
1845 // shuffle the pairs of pairs together, etc. until the vector has
1846 // been built. This will work only if all of the necessary shuffle masks
1849 // We do this in two phases; first to check the legality of the shuffles,
1850 // and next, assuming that all shuffles are legal, to create the new nodes.
1851 for (int Phase = 0; Phase < 2; ++Phase) {
1852 SmallVector<std::pair<SDValue, SmallVector<int, 16> >, 16> IntermedVals,
1854 for (unsigned i = 0; i < NumElems; ++i) {
1855 SDValue V = Node->getOperand(i);
1856 if (V.getOpcode() == ISD::UNDEF)
1861 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1862 IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
1865 while (IntermedVals.size() > 2) {
1866 NewIntermedVals.clear();
1867 for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1868 // This vector and the next vector are shuffled together (simply to
1869 // append the one to the other).
1870 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1872 SmallVector<int, 16> FinalIndices;
1873 FinalIndices.reserve(IntermedVals[i].second.size() +
1874 IntermedVals[i+1].second.size());
1877 for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1880 FinalIndices.push_back(IntermedVals[i].second[j]);
1882 for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1884 ShuffleVec[k] = NumElems + j;
1885 FinalIndices.push_back(IntermedVals[i+1].second[j]);
1890 Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
1891 IntermedVals[i+1].first,
1893 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1895 NewIntermedVals.push_back(
1896 std::make_pair(Shuffle, std::move(FinalIndices)));
1899 // If we had an odd number of defined values, then append the last
1900 // element to the array of new vectors.
1901 if ((IntermedVals.size() & 1) != 0)
1902 NewIntermedVals.push_back(IntermedVals.back());
1904 IntermedVals.swap(NewIntermedVals);
1907 assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1908 "Invalid number of intermediate vectors");
1909 SDValue Vec1 = IntermedVals[0].first;
1911 if (IntermedVals.size() > 1)
1912 Vec2 = IntermedVals[1].first;
1914 Vec2 = DAG.getUNDEF(VT);
1916 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1917 for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1918 ShuffleVec[IntermedVals[0].second[i]] = i;
1919 for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1920 ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1923 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1924 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1931 /// Expand a BUILD_VECTOR node on targets that don't
1932 /// support the operation, but do support the resultant vector type.
1933 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1934 unsigned NumElems = Node->getNumOperands();
1935 SDValue Value1, Value2;
1937 EVT VT = Node->getValueType(0);
1938 EVT OpVT = Node->getOperand(0).getValueType();
1939 EVT EltVT = VT.getVectorElementType();
1941 // If the only non-undef value is the low element, turn this into a
1942 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1943 bool isOnlyLowElement = true;
1944 bool MoreThanTwoValues = false;
1945 bool isConstant = true;
1946 for (unsigned i = 0; i < NumElems; ++i) {
1947 SDValue V = Node->getOperand(i);
1948 if (V.getOpcode() == ISD::UNDEF)
1951 isOnlyLowElement = false;
1952 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1955 if (!Value1.getNode()) {
1957 } else if (!Value2.getNode()) {
1960 } else if (V != Value1 && V != Value2) {
1961 MoreThanTwoValues = true;
1965 if (!Value1.getNode())
1966 return DAG.getUNDEF(VT);
1968 if (isOnlyLowElement)
1969 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1971 // If all elements are constants, create a load from the constant pool.
1973 SmallVector<Constant*, 16> CV;
1974 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1975 if (ConstantFPSDNode *V =
1976 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1977 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1978 } else if (ConstantSDNode *V =
1979 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1981 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1983 // If OpVT and EltVT don't match, EltVT is not legal and the
1984 // element values have been promoted/truncated earlier. Undo this;
1985 // we don't want a v16i8 to become a v16i32 for example.
1986 const ConstantInt *CI = V->getConstantIntValue();
1987 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1988 CI->getZExtValue()));
1991 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1992 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1993 CV.push_back(UndefValue::get(OpNTy));
1996 Constant *CP = ConstantVector::get(CV);
1997 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1998 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1999 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
2000 MachinePointerInfo::getConstantPool(),
2001 false, false, false, Alignment);
2004 SmallSet<SDValue, 16> DefinedValues;
2005 for (unsigned i = 0; i < NumElems; ++i) {
2006 if (Node->getOperand(i).getOpcode() == ISD::UNDEF)
2008 DefinedValues.insert(Node->getOperand(i));
2011 if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
2012 if (!MoreThanTwoValues) {
2013 SmallVector<int, 8> ShuffleVec(NumElems, -1);
2014 for (unsigned i = 0; i < NumElems; ++i) {
2015 SDValue V = Node->getOperand(i);
2016 if (V.getOpcode() == ISD::UNDEF)
2018 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2020 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
2021 // Get the splatted value into the low element of a vector register.
2022 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2024 if (Value2.getNode())
2025 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2027 Vec2 = DAG.getUNDEF(VT);
2029 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2030 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2034 if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
2039 // Otherwise, we can't handle this case efficiently.
2040 return ExpandVectorBuildThroughStack(Node);
2043 // Expand a node into a call to a libcall. If the result value
2044 // does not fit into a register, return the lo part and set the hi part to the
2045 // by-reg argument. If it does fit into a single register, return the result
2046 // and leave the Hi part unset.
2047 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2049 TargetLowering::ArgListTy Args;
2050 TargetLowering::ArgListEntry Entry;
2051 for (const SDValue &Op : Node->op_values()) {
2052 EVT ArgVT = Op.getValueType();
2053 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2056 Entry.isSExt = isSigned;
2057 Entry.isZExt = !isSigned;
2058 Args.push_back(Entry);
2060 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2061 TLI.getPointerTy());
2063 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2065 // By default, the input chain to this libcall is the entry node of the
2066 // function. If the libcall is going to be emitted as a tail call then
2067 // TLI.isUsedByReturnOnly will change it to the right chain if the return
2068 // node which is being folded has a non-entry input chain.
2069 SDValue InChain = DAG.getEntryNode();
2071 // isTailCall may be true since the callee does not reference caller stack
2072 // frame. Check if it's in the right position.
2073 SDValue TCChain = InChain;
2074 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
2078 TargetLowering::CallLoweringInfo CLI(DAG);
2079 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2080 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2081 .setTailCall(isTailCall).setSExtResult(isSigned).setZExtResult(!isSigned);
2083 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2085 if (!CallInfo.second.getNode())
2086 // It's a tailcall, return the chain (which is the DAG root).
2087 return DAG.getRoot();
2089 return CallInfo.first;
2092 /// Generate a libcall taking the given operands as arguments
2093 /// and returning a result of type RetVT.
2094 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2095 const SDValue *Ops, unsigned NumOps,
2096 bool isSigned, SDLoc dl) {
2097 TargetLowering::ArgListTy Args;
2098 Args.reserve(NumOps);
2100 TargetLowering::ArgListEntry Entry;
2101 for (unsigned i = 0; i != NumOps; ++i) {
2102 Entry.Node = Ops[i];
2103 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2104 Entry.isSExt = isSigned;
2105 Entry.isZExt = !isSigned;
2106 Args.push_back(Entry);
2108 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2109 TLI.getPointerTy());
2111 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2113 TargetLowering::CallLoweringInfo CLI(DAG);
2114 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
2115 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2116 .setSExtResult(isSigned).setZExtResult(!isSigned);
2118 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
2120 return CallInfo.first;
2123 // Expand a node into a call to a libcall. Similar to
2124 // ExpandLibCall except that the first operand is the in-chain.
2125 std::pair<SDValue, SDValue>
2126 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2129 SDValue InChain = Node->getOperand(0);
2131 TargetLowering::ArgListTy Args;
2132 TargetLowering::ArgListEntry Entry;
2133 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2134 EVT ArgVT = Node->getOperand(i).getValueType();
2135 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2136 Entry.Node = Node->getOperand(i);
2138 Entry.isSExt = isSigned;
2139 Entry.isZExt = !isSigned;
2140 Args.push_back(Entry);
2142 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2143 TLI.getPointerTy());
2145 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2147 TargetLowering::CallLoweringInfo CLI(DAG);
2148 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2149 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2150 .setSExtResult(isSigned).setZExtResult(!isSigned);
2152 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2157 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2158 RTLIB::Libcall Call_F32,
2159 RTLIB::Libcall Call_F64,
2160 RTLIB::Libcall Call_F80,
2161 RTLIB::Libcall Call_F128,
2162 RTLIB::Libcall Call_PPCF128) {
2164 switch (Node->getSimpleValueType(0).SimpleTy) {
2165 default: llvm_unreachable("Unexpected request for libcall!");
2166 case MVT::f32: LC = Call_F32; break;
2167 case MVT::f64: LC = Call_F64; break;
2168 case MVT::f80: LC = Call_F80; break;
2169 case MVT::f128: LC = Call_F128; break;
2170 case MVT::ppcf128: LC = Call_PPCF128; break;
2172 return ExpandLibCall(LC, Node, false);
2175 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2176 RTLIB::Libcall Call_I8,
2177 RTLIB::Libcall Call_I16,
2178 RTLIB::Libcall Call_I32,
2179 RTLIB::Libcall Call_I64,
2180 RTLIB::Libcall Call_I128) {
2182 switch (Node->getSimpleValueType(0).SimpleTy) {
2183 default: llvm_unreachable("Unexpected request for libcall!");
2184 case MVT::i8: LC = Call_I8; break;
2185 case MVT::i16: LC = Call_I16; break;
2186 case MVT::i32: LC = Call_I32; break;
2187 case MVT::i64: LC = Call_I64; break;
2188 case MVT::i128: LC = Call_I128; break;
2190 return ExpandLibCall(LC, Node, isSigned);
2193 /// Return true if divmod libcall is available.
2194 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2195 const TargetLowering &TLI) {
2197 switch (Node->getSimpleValueType(0).SimpleTy) {
2198 default: llvm_unreachable("Unexpected request for libcall!");
2199 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2200 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2201 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2202 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2203 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2206 return TLI.getLibcallName(LC) != nullptr;
2209 /// Only issue divrem libcall if both quotient and remainder are needed.
2210 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2211 // The other use might have been replaced with a divrem already.
2212 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2213 unsigned OtherOpcode = 0;
2215 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2217 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2219 SDValue Op0 = Node->getOperand(0);
2220 SDValue Op1 = Node->getOperand(1);
2221 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2222 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2226 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2227 User->getOperand(0) == Op0 &&
2228 User->getOperand(1) == Op1)
2234 /// Issue libcalls to __{u}divmod to compute div / rem pairs.
2236 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2237 SmallVectorImpl<SDValue> &Results) {
2238 unsigned Opcode = Node->getOpcode();
2239 bool isSigned = Opcode == ISD::SDIVREM;
2242 switch (Node->getSimpleValueType(0).SimpleTy) {
2243 default: llvm_unreachable("Unexpected request for libcall!");
2244 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2245 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2246 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2247 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2248 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2251 // The input chain to this libcall is the entry node of the function.
2252 // Legalizing the call will automatically add the previous call to the
2254 SDValue InChain = DAG.getEntryNode();
2256 EVT RetVT = Node->getValueType(0);
2257 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2259 TargetLowering::ArgListTy Args;
2260 TargetLowering::ArgListEntry Entry;
2261 for (const SDValue &Op : Node->op_values()) {
2262 EVT ArgVT = Op.getValueType();
2263 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2266 Entry.isSExt = isSigned;
2267 Entry.isZExt = !isSigned;
2268 Args.push_back(Entry);
2271 // Also pass the return address of the remainder.
2272 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2274 Entry.Ty = RetTy->getPointerTo();
2275 Entry.isSExt = isSigned;
2276 Entry.isZExt = !isSigned;
2277 Args.push_back(Entry);
2279 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2280 TLI.getPointerTy());
2283 TargetLowering::CallLoweringInfo CLI(DAG);
2284 CLI.setDebugLoc(dl).setChain(InChain)
2285 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2286 .setSExtResult(isSigned).setZExtResult(!isSigned);
2288 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2290 // Remainder is loaded back from the stack frame.
2291 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2292 MachinePointerInfo(), false, false, false, 0);
2293 Results.push_back(CallInfo.first);
2294 Results.push_back(Rem);
2297 /// Return true if sincos libcall is available.
2298 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2300 switch (Node->getSimpleValueType(0).SimpleTy) {
2301 default: llvm_unreachable("Unexpected request for libcall!");
2302 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2303 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2304 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2305 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2306 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2308 return TLI.getLibcallName(LC) != nullptr;
2311 /// Return true if sincos libcall is available and can be used to combine sin
2313 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2314 const TargetMachine &TM) {
2315 if (!isSinCosLibcallAvailable(Node, TLI))
2317 // GNU sin/cos functions set errno while sincos does not. Therefore
2318 // combining sin and cos is only safe if unsafe-fpmath is enabled.
2319 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2320 if (isGNU && !TM.Options.UnsafeFPMath)
2325 /// Only issue sincos libcall if both sin and cos are needed.
2326 static bool useSinCos(SDNode *Node) {
2327 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2328 ? ISD::FCOS : ISD::FSIN;
2330 SDValue Op0 = Node->getOperand(0);
2331 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2332 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2336 // The other user might have been turned into sincos already.
2337 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2343 /// Issue libcalls to sincos to compute sin / cos pairs.
2345 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2346 SmallVectorImpl<SDValue> &Results) {
2348 switch (Node->getSimpleValueType(0).SimpleTy) {
2349 default: llvm_unreachable("Unexpected request for libcall!");
2350 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2351 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2352 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2353 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2354 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2357 // The input chain to this libcall is the entry node of the function.
2358 // Legalizing the call will automatically add the previous call to the
2360 SDValue InChain = DAG.getEntryNode();
2362 EVT RetVT = Node->getValueType(0);
2363 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2365 TargetLowering::ArgListTy Args;
2366 TargetLowering::ArgListEntry Entry;
2368 // Pass the argument.
2369 Entry.Node = Node->getOperand(0);
2371 Entry.isSExt = false;
2372 Entry.isZExt = false;
2373 Args.push_back(Entry);
2375 // Pass the return address of sin.
2376 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2377 Entry.Node = SinPtr;
2378 Entry.Ty = RetTy->getPointerTo();
2379 Entry.isSExt = false;
2380 Entry.isZExt = false;
2381 Args.push_back(Entry);
2383 // Also pass the return address of the cos.
2384 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2385 Entry.Node = CosPtr;
2386 Entry.Ty = RetTy->getPointerTo();
2387 Entry.isSExt = false;
2388 Entry.isZExt = false;
2389 Args.push_back(Entry);
2391 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2392 TLI.getPointerTy());
2395 TargetLowering::CallLoweringInfo CLI(DAG);
2396 CLI.setDebugLoc(dl).setChain(InChain)
2397 .setCallee(TLI.getLibcallCallingConv(LC),
2398 Type::getVoidTy(*DAG.getContext()), Callee, std::move(Args), 0);
2400 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2402 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2403 MachinePointerInfo(), false, false, false, 0));
2404 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2405 MachinePointerInfo(), false, false, false, 0));
2408 /// This function is responsible for legalizing a
2409 /// INT_TO_FP operation of the specified operand when the target requests that
2410 /// we expand it. At this point, we know that the result and operand types are
2411 /// legal for the target.
2412 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2416 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2417 // simple 32-bit [signed|unsigned] integer to float/double expansion
2419 // Get the stack frame index of a 8 byte buffer.
2420 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2422 // word offset constant for Hi/Lo address computation
2423 SDValue WordOff = DAG.getConstant(sizeof(int), dl,
2424 StackSlot.getValueType());
2425 // set up Hi and Lo (into buffer) address based on endian
2426 SDValue Hi = StackSlot;
2427 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2428 StackSlot, WordOff);
2429 if (TLI.isLittleEndian())
2432 // if signed map to unsigned space
2435 // constant used to invert sign bit (signed to unsigned mapping)
2436 SDValue SignBit = DAG.getConstant(0x80000000u, dl, MVT::i32);
2437 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2441 // store the lo of the constructed double - based on integer input
2442 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2443 Op0Mapped, Lo, MachinePointerInfo(),
2445 // initial hi portion of constructed double
2446 SDValue InitialHi = DAG.getConstant(0x43300000u, dl, MVT::i32);
2447 // store the hi of the constructed double - biased exponent
2448 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2449 MachinePointerInfo(),
2451 // load the constructed double
2452 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2453 MachinePointerInfo(), false, false, false, 0);
2454 // FP constant to bias correct the final result
2455 SDValue Bias = DAG.getConstantFP(isSigned ?
2456 BitsToDouble(0x4330000080000000ULL) :
2457 BitsToDouble(0x4330000000000000ULL),
2459 // subtract the bias
2460 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2463 // handle final rounding
2464 if (DestVT == MVT::f64) {
2467 } else if (DestVT.bitsLT(MVT::f64)) {
2468 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2469 DAG.getIntPtrConstant(0, dl));
2470 } else if (DestVT.bitsGT(MVT::f64)) {
2471 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2475 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2476 // Code below here assumes !isSigned without checking again.
2478 // Implementation of unsigned i64 to f64 following the algorithm in
2479 // __floatundidf in compiler_rt. This implementation has the advantage
2480 // of performing rounding correctly, both in the default rounding mode
2481 // and in all alternate rounding modes.
2482 // TODO: Generalize this for use with other types.
2483 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2485 DAG.getConstant(UINT64_C(0x4330000000000000), dl, MVT::i64);
2486 SDValue TwoP84PlusTwoP52 =
2487 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), dl,
2490 DAG.getConstant(UINT64_C(0x4530000000000000), dl, MVT::i64);
2492 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2493 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2494 DAG.getConstant(32, dl, MVT::i64));
2495 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2496 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2497 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2498 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2499 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2501 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2504 // Implementation of unsigned i64 to f32.
2505 // TODO: Generalize this for use with other types.
2506 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2507 // For unsigned conversions, convert them to signed conversions using the
2508 // algorithm from the x86_64 __floatundidf in compiler_rt.
2510 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2512 SDValue ShiftConst =
2513 DAG.getConstant(1, dl, TLI.getShiftAmountTy(Op0.getValueType()));
2514 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2515 SDValue AndConst = DAG.getConstant(1, dl, MVT::i64);
2516 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2517 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2519 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2520 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2522 // TODO: This really should be implemented using a branch rather than a
2523 // select. We happen to get lucky and machinesink does the right
2524 // thing most of the time. This would be a good candidate for a
2525 //pseudo-op, or, even better, for whole-function isel.
2526 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2527 Op0, DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
2528 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2531 // Otherwise, implement the fully general conversion.
2533 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2534 DAG.getConstant(UINT64_C(0xfffffffffffff800), dl, MVT::i64));
2535 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2536 DAG.getConstant(UINT64_C(0x800), dl, MVT::i64));
2537 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2538 DAG.getConstant(UINT64_C(0x7ff), dl, MVT::i64));
2539 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), And2,
2540 DAG.getConstant(UINT64_C(0), dl, MVT::i64),
2542 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2543 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), Op0,
2544 DAG.getConstant(UINT64_C(0x0020000000000000), dl,
2547 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2548 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2550 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2551 DAG.getConstant(32, dl, SHVT));
2552 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2553 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2555 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), dl,
2557 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2558 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2559 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2560 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2561 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2562 DAG.getIntPtrConstant(0, dl));
2565 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2567 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2569 DAG.getConstant(0, dl, Op0.getValueType()),
2571 SDValue Zero = DAG.getIntPtrConstant(0, dl),
2572 Four = DAG.getIntPtrConstant(4, dl);
2573 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2574 SignSet, Four, Zero);
2576 // If the sign bit of the integer is set, the large number will be treated
2577 // as a negative number. To counteract this, the dynamic code adds an
2578 // offset depending on the data type.
2580 switch (Op0.getSimpleValueType().SimpleTy) {
2581 default: llvm_unreachable("Unsupported integer type!");
2582 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2583 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2584 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2585 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2587 if (TLI.isLittleEndian()) FF <<= 32;
2588 Constant *FudgeFactor = ConstantInt::get(
2589 Type::getInt64Ty(*DAG.getContext()), FF);
2591 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2592 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2593 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2594 Alignment = std::min(Alignment, 4u);
2596 if (DestVT == MVT::f32)
2597 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2598 MachinePointerInfo::getConstantPool(),
2599 false, false, false, Alignment);
2601 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2602 DAG.getEntryNode(), CPIdx,
2603 MachinePointerInfo::getConstantPool(),
2604 MVT::f32, false, false, false, Alignment);
2605 HandleSDNode Handle(Load);
2606 LegalizeOp(Load.getNode());
2607 FudgeInReg = Handle.getValue();
2610 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2613 /// This function is responsible for legalizing a
2614 /// *INT_TO_FP operation of the specified operand when the target requests that
2615 /// we promote it. At this point, we know that the result and operand types are
2616 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2617 /// operation that takes a larger input.
2618 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2622 // First step, figure out the appropriate *INT_TO_FP operation to use.
2623 EVT NewInTy = LegalOp.getValueType();
2625 unsigned OpToUse = 0;
2627 // Scan for the appropriate larger type to use.
2629 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2630 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2632 // If the target supports SINT_TO_FP of this type, use it.
2633 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2634 OpToUse = ISD::SINT_TO_FP;
2637 if (isSigned) continue;
2639 // If the target supports UINT_TO_FP of this type, use it.
2640 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2641 OpToUse = ISD::UINT_TO_FP;
2645 // Otherwise, try a larger type.
2648 // Okay, we found the operation and type to use. Zero extend our input to the
2649 // desired type then run the operation on it.
2650 return DAG.getNode(OpToUse, dl, DestVT,
2651 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2652 dl, NewInTy, LegalOp));
2655 /// This function is responsible for legalizing a
2656 /// FP_TO_*INT operation of the specified operand when the target requests that
2657 /// we promote it. At this point, we know that the result and operand types are
2658 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2659 /// operation that returns a larger result.
2660 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2664 // First step, figure out the appropriate FP_TO*INT operation to use.
2665 EVT NewOutTy = DestVT;
2667 unsigned OpToUse = 0;
2669 // Scan for the appropriate larger type to use.
2671 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2672 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2674 // A larger signed type can hold all unsigned values of the requested type,
2675 // so using FP_TO_SINT is valid
2676 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2677 OpToUse = ISD::FP_TO_SINT;
2681 // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2682 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2683 OpToUse = ISD::FP_TO_UINT;
2687 // Otherwise, try a larger type.
2691 // Okay, we found the operation and type to use.
2692 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2694 // Truncate the result of the extended FP_TO_*INT operation to the desired
2696 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2699 /// Open code the operations for BSWAP of the specified operation.
2700 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2701 EVT VT = Op.getValueType();
2702 EVT SHVT = TLI.getShiftAmountTy(VT);
2703 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2704 switch (VT.getSimpleVT().SimpleTy) {
2705 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2707 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2708 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2709 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2711 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2712 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2713 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2714 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2715 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2716 DAG.getConstant(0xFF0000, dl, VT));
2717 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
2718 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2719 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2720 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2722 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2723 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2724 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2725 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2726 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2727 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2728 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2729 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2730 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7,
2731 DAG.getConstant(255ULL<<48, dl, VT));
2732 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6,
2733 DAG.getConstant(255ULL<<40, dl, VT));
2734 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5,
2735 DAG.getConstant(255ULL<<32, dl, VT));
2736 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4,
2737 DAG.getConstant(255ULL<<24, dl, VT));
2738 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2739 DAG.getConstant(255ULL<<16, dl, VT));
2740 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2,
2741 DAG.getConstant(255ULL<<8 , dl, VT));
2742 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2743 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2744 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2745 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2746 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2747 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2748 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2752 /// Expand the specified bitcount instruction into operations.
2753 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2756 default: llvm_unreachable("Cannot expand this yet!");
2758 EVT VT = Op.getValueType();
2759 EVT ShVT = TLI.getShiftAmountTy(VT);
2760 unsigned Len = VT.getSizeInBits();
2762 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2763 "CTPOP not implemented for this type.");
2765 // This is the "best" algorithm from
2766 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2768 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)),
2770 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)),
2772 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)),
2774 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)),
2777 // v = v - ((v >> 1) & 0x55555555...)
2778 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2779 DAG.getNode(ISD::AND, dl, VT,
2780 DAG.getNode(ISD::SRL, dl, VT, Op,
2781 DAG.getConstant(1, dl, ShVT)),
2783 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2784 Op = DAG.getNode(ISD::ADD, dl, VT,
2785 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2786 DAG.getNode(ISD::AND, dl, VT,
2787 DAG.getNode(ISD::SRL, dl, VT, Op,
2788 DAG.getConstant(2, dl, ShVT)),
2790 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2791 Op = DAG.getNode(ISD::AND, dl, VT,
2792 DAG.getNode(ISD::ADD, dl, VT, Op,
2793 DAG.getNode(ISD::SRL, dl, VT, Op,
2794 DAG.getConstant(4, dl, ShVT))),
2796 // v = (v * 0x01010101...) >> (Len - 8)
2797 Op = DAG.getNode(ISD::SRL, dl, VT,
2798 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2799 DAG.getConstant(Len - 8, dl, ShVT));
2803 case ISD::CTLZ_ZERO_UNDEF:
2804 // This trivially expands to CTLZ.
2805 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2807 // for now, we do this:
2808 // x = x | (x >> 1);
2809 // x = x | (x >> 2);
2811 // x = x | (x >>16);
2812 // x = x | (x >>32); // for 64-bit input
2813 // return popcount(~x);
2815 // Ref: "Hacker's Delight" by Henry Warren
2816 EVT VT = Op.getValueType();
2817 EVT ShVT = TLI.getShiftAmountTy(VT);
2818 unsigned len = VT.getSizeInBits();
2819 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2820 SDValue Tmp3 = DAG.getConstant(1ULL << i, dl, ShVT);
2821 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2822 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2824 Op = DAG.getNOT(dl, Op, VT);
2825 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2827 case ISD::CTTZ_ZERO_UNDEF:
2828 // This trivially expands to CTTZ.
2829 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2831 // for now, we use: { return popcount(~x & (x - 1)); }
2832 // unless the target has ctlz but not ctpop, in which case we use:
2833 // { return 32 - nlz(~x & (x-1)); }
2834 // Ref: "Hacker's Delight" by Henry Warren
2835 EVT VT = Op.getValueType();
2836 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2837 DAG.getNOT(dl, Op, VT),
2838 DAG.getNode(ISD::SUB, dl, VT, Op,
2839 DAG.getConstant(1, dl, VT)));
2840 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2841 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2842 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2843 return DAG.getNode(ISD::SUB, dl, VT,
2844 DAG.getConstant(VT.getSizeInBits(), dl, VT),
2845 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2846 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2851 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2852 unsigned Opc = Node->getOpcode();
2853 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2854 RTLIB::Libcall LC = RTLIB::getATOMIC(Opc, VT);
2855 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
2857 return ExpandChainLibCall(LC, Node, false);
2860 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2861 SmallVector<SDValue, 8> Results;
2863 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2865 switch (Node->getOpcode()) {
2868 case ISD::CTLZ_ZERO_UNDEF:
2870 case ISD::CTTZ_ZERO_UNDEF:
2871 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2872 Results.push_back(Tmp1);
2875 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2877 case ISD::FRAMEADDR:
2878 case ISD::RETURNADDR:
2879 case ISD::FRAME_TO_ARGS_OFFSET:
2880 Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
2882 case ISD::FLT_ROUNDS_:
2883 Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0)));
2885 case ISD::EH_RETURN:
2889 case ISD::EH_SJLJ_LONGJMP:
2890 // If the target didn't expand these, there's nothing to do, so just
2891 // preserve the chain and be done.
2892 Results.push_back(Node->getOperand(0));
2894 case ISD::EH_SJLJ_SETJMP:
2895 // If the target didn't expand this, just return 'zero' and preserve the
2897 Results.push_back(DAG.getConstant(0, dl, MVT::i32));
2898 Results.push_back(Node->getOperand(0));
2900 case ISD::ATOMIC_FENCE: {
2901 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2902 // FIXME: handle "fence singlethread" more efficiently.
2903 TargetLowering::ArgListTy Args;
2905 TargetLowering::CallLoweringInfo CLI(DAG);
2906 CLI.setDebugLoc(dl).setChain(Node->getOperand(0))
2907 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2908 DAG.getExternalSymbol("__sync_synchronize",
2909 TLI.getPointerTy()), std::move(Args), 0);
2911 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2913 Results.push_back(CallResult.second);
2916 case ISD::ATOMIC_LOAD: {
2917 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2918 SDValue Zero = DAG.getConstant(0, dl, Node->getValueType(0));
2919 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2920 SDValue Swap = DAG.getAtomicCmpSwap(
2921 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2922 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
2923 cast<AtomicSDNode>(Node)->getMemOperand(),
2924 cast<AtomicSDNode>(Node)->getOrdering(),
2925 cast<AtomicSDNode>(Node)->getOrdering(),
2926 cast<AtomicSDNode>(Node)->getSynchScope());
2927 Results.push_back(Swap.getValue(0));
2928 Results.push_back(Swap.getValue(1));
2931 case ISD::ATOMIC_STORE: {
2932 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2933 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2934 cast<AtomicSDNode>(Node)->getMemoryVT(),
2935 Node->getOperand(0),
2936 Node->getOperand(1), Node->getOperand(2),
2937 cast<AtomicSDNode>(Node)->getMemOperand(),
2938 cast<AtomicSDNode>(Node)->getOrdering(),
2939 cast<AtomicSDNode>(Node)->getSynchScope());
2940 Results.push_back(Swap.getValue(1));
2943 // By default, atomic intrinsics are marked Legal and lowered. Targets
2944 // which don't support them directly, however, may want libcalls, in which
2945 // case they mark them Expand, and we get here.
2946 case ISD::ATOMIC_SWAP:
2947 case ISD::ATOMIC_LOAD_ADD:
2948 case ISD::ATOMIC_LOAD_SUB:
2949 case ISD::ATOMIC_LOAD_AND:
2950 case ISD::ATOMIC_LOAD_OR:
2951 case ISD::ATOMIC_LOAD_XOR:
2952 case ISD::ATOMIC_LOAD_NAND:
2953 case ISD::ATOMIC_LOAD_MIN:
2954 case ISD::ATOMIC_LOAD_MAX:
2955 case ISD::ATOMIC_LOAD_UMIN:
2956 case ISD::ATOMIC_LOAD_UMAX:
2957 case ISD::ATOMIC_CMP_SWAP: {
2958 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2959 Results.push_back(Tmp.first);
2960 Results.push_back(Tmp.second);
2963 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
2964 // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
2965 // splits out the success value as a comparison. Expanding the resulting
2966 // ATOMIC_CMP_SWAP will produce a libcall.
2967 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2968 SDValue Res = DAG.getAtomicCmpSwap(
2969 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2970 Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
2971 Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand(),
2972 cast<AtomicSDNode>(Node)->getSuccessOrdering(),
2973 cast<AtomicSDNode>(Node)->getFailureOrdering(),
2974 cast<AtomicSDNode>(Node)->getSynchScope());
2976 SDValue Success = DAG.getSetCC(SDLoc(Node), Node->getValueType(1),
2977 Res, Node->getOperand(2), ISD::SETEQ);
2979 Results.push_back(Res.getValue(0));
2980 Results.push_back(Success);
2981 Results.push_back(Res.getValue(1));
2984 case ISD::DYNAMIC_STACKALLOC:
2985 ExpandDYNAMIC_STACKALLOC(Node, Results);
2987 case ISD::MERGE_VALUES:
2988 for (unsigned i = 0; i < Node->getNumValues(); i++)
2989 Results.push_back(Node->getOperand(i));
2992 EVT VT = Node->getValueType(0);
2994 Results.push_back(DAG.getConstant(0, dl, VT));
2996 assert(VT.isFloatingPoint() && "Unknown value type!");
2997 Results.push_back(DAG.getConstantFP(0, dl, VT));
3002 // If this operation is not supported, lower it to 'abort()' call
3003 TargetLowering::ArgListTy Args;
3004 TargetLowering::CallLoweringInfo CLI(DAG);
3005 CLI.setDebugLoc(dl).setChain(Node->getOperand(0))
3006 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3007 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3008 std::move(Args), 0);
3009 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3011 Results.push_back(CallResult.second);
3016 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3017 Node->getValueType(0), dl);
3018 Results.push_back(Tmp1);
3020 case ISD::FP_EXTEND:
3021 Tmp1 = EmitStackConvert(Node->getOperand(0),
3022 Node->getOperand(0).getValueType(),
3023 Node->getValueType(0), dl);
3024 Results.push_back(Tmp1);
3026 case ISD::SIGN_EXTEND_INREG: {
3027 // NOTE: we could fall back on load/store here too for targets without
3028 // SAR. However, it is doubtful that any exist.
3029 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3030 EVT VT = Node->getValueType(0);
3031 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
3034 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
3035 ExtraVT.getScalarType().getSizeInBits();
3036 SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
3037 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3038 Node->getOperand(0), ShiftCst);
3039 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3040 Results.push_back(Tmp1);
3043 case ISD::FP_ROUND_INREG: {
3044 // The only way we can lower this is to turn it into a TRUNCSTORE,
3045 // EXTLOAD pair, targeting a temporary location (a stack slot).
3047 // NOTE: there is a choice here between constantly creating new stack
3048 // slots and always reusing the same one. We currently always create
3049 // new ones, as reuse may inhibit scheduling.
3050 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3051 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
3052 Node->getValueType(0), dl);
3053 Results.push_back(Tmp1);
3056 case ISD::SINT_TO_FP:
3057 case ISD::UINT_TO_FP:
3058 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3059 Node->getOperand(0), Node->getValueType(0), dl);
3060 Results.push_back(Tmp1);
3062 case ISD::FP_TO_SINT:
3063 if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
3064 Results.push_back(Tmp1);
3066 case ISD::FP_TO_UINT: {
3067 SDValue True, False;
3068 EVT VT = Node->getOperand(0).getValueType();
3069 EVT NVT = Node->getValueType(0);
3070 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
3071 APInt::getNullValue(VT.getSizeInBits()));
3072 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3073 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3074 Tmp1 = DAG.getConstantFP(apf, dl, VT);
3075 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
3076 Node->getOperand(0),
3078 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3079 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3080 DAG.getNode(ISD::FSUB, dl, VT,
3081 Node->getOperand(0), Tmp1));
3082 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3083 DAG.getConstant(x, dl, NVT));
3084 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
3085 Results.push_back(Tmp1);
3089 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3090 EVT VT = Node->getValueType(0);
3091 Tmp1 = Node->getOperand(0);
3092 Tmp2 = Node->getOperand(1);
3093 unsigned Align = Node->getConstantOperandVal(3);
3095 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
3096 MachinePointerInfo(V),
3097 false, false, false, 0);
3098 SDValue VAList = VAListLoad;
3100 if (Align > TLI.getMinStackArgumentAlignment()) {
3101 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
3103 VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3104 DAG.getConstant(Align - 1, dl,
3105 VAList.getValueType()));
3107 VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList,
3108 DAG.getConstant(-(int64_t)Align, dl,
3109 VAList.getValueType()));
3112 // Increment the pointer, VAList, to the next vaarg
3113 Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3114 DAG.getConstant(TLI.getDataLayout()->
3115 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
3117 VAList.getValueType()));
3118 // Store the incremented VAList to the legalized pointer
3119 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
3120 MachinePointerInfo(V), false, false, 0);
3121 // Load the actual argument out of the pointer VAList
3122 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
3123 false, false, false, 0));
3124 Results.push_back(Results[0].getValue(1));
3128 // This defaults to loading a pointer from the input and storing it to the
3129 // output, returning the chain.
3130 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3131 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3132 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
3133 Node->getOperand(2), MachinePointerInfo(VS),
3134 false, false, false, 0);
3135 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3136 MachinePointerInfo(VD), false, false, 0);
3137 Results.push_back(Tmp1);
3140 case ISD::EXTRACT_VECTOR_ELT:
3141 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3142 // This must be an access of the only element. Return it.
3143 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3144 Node->getOperand(0));
3146 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3147 Results.push_back(Tmp1);
3149 case ISD::EXTRACT_SUBVECTOR:
3150 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3152 case ISD::INSERT_SUBVECTOR:
3153 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3155 case ISD::CONCAT_VECTORS: {
3156 Results.push_back(ExpandVectorBuildThroughStack(Node));
3159 case ISD::SCALAR_TO_VECTOR:
3160 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3162 case ISD::INSERT_VECTOR_ELT:
3163 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3164 Node->getOperand(1),
3165 Node->getOperand(2), dl));
3167 case ISD::VECTOR_SHUFFLE: {
3168 SmallVector<int, 32> NewMask;
3169 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3171 EVT VT = Node->getValueType(0);
3172 EVT EltVT = VT.getVectorElementType();
3173 SDValue Op0 = Node->getOperand(0);
3174 SDValue Op1 = Node->getOperand(1);
3175 if (!TLI.isTypeLegal(EltVT)) {
3177 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3179 // BUILD_VECTOR operands are allowed to be wider than the element type.
3180 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3182 if (NewEltVT.bitsLT(EltVT)) {
3184 // Convert shuffle node.
3185 // If original node was v4i64 and the new EltVT is i32,
3186 // cast operands to v8i32 and re-build the mask.
3188 // Calculate new VT, the size of the new VT should be equal to original.
3190 EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3191 VT.getSizeInBits() / NewEltVT.getSizeInBits());
3192 assert(NewVT.bitsEq(VT));
3194 // cast operands to new VT
3195 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3196 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3198 // Convert the shuffle mask
3199 unsigned int factor =
3200 NewVT.getVectorNumElements()/VT.getVectorNumElements();
3202 // EltVT gets smaller
3205 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3207 for (unsigned fi = 0; fi < factor; ++fi)
3208 NewMask.push_back(Mask[i]);
3211 for (unsigned fi = 0; fi < factor; ++fi)
3212 NewMask.push_back(Mask[i]*factor+fi);
3220 unsigned NumElems = VT.getVectorNumElements();
3221 SmallVector<SDValue, 16> Ops;
3222 for (unsigned i = 0; i != NumElems; ++i) {
3224 Ops.push_back(DAG.getUNDEF(EltVT));
3227 unsigned Idx = Mask[i];
3229 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3231 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy())));
3233 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3235 DAG.getConstant(Idx - NumElems, dl,
3236 TLI.getVectorIdxTy())));
3239 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3240 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3241 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3242 Results.push_back(Tmp1);
3245 case ISD::EXTRACT_ELEMENT: {
3246 EVT OpTy = Node->getOperand(0).getValueType();
3247 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3249 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3250 DAG.getConstant(OpTy.getSizeInBits()/2, dl,
3251 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3252 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3255 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3256 Node->getOperand(0));
3258 Results.push_back(Tmp1);
3261 case ISD::STACKSAVE:
3262 // Expand to CopyFromReg if the target set
3263 // StackPointerRegisterToSaveRestore.
3264 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3265 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3266 Node->getValueType(0)));
3267 Results.push_back(Results[0].getValue(1));
3269 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3270 Results.push_back(Node->getOperand(0));
3273 case ISD::STACKRESTORE:
3274 // Expand to CopyToReg if the target set
3275 // StackPointerRegisterToSaveRestore.
3276 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3277 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3278 Node->getOperand(1)));
3280 Results.push_back(Node->getOperand(0));
3283 case ISD::FCOPYSIGN:
3284 Results.push_back(ExpandFCOPYSIGN(Node));
3287 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3288 Tmp1 = DAG.getConstantFP(-0.0, dl, Node->getValueType(0));
3289 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3290 Node->getOperand(0));
3291 Results.push_back(Tmp1);
3294 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3295 EVT VT = Node->getValueType(0);
3296 Tmp1 = Node->getOperand(0);
3297 Tmp2 = DAG.getConstantFP(0.0, dl, VT);
3298 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
3299 Tmp1, Tmp2, ISD::SETUGT);
3300 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3301 Tmp1 = DAG.getSelect(dl, VT, Tmp2, Tmp1, Tmp3);
3302 Results.push_back(Tmp1);
3309 // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
3311 switch (Node->getOpcode()) {
3312 default: llvm_unreachable("How did we get here?");
3313 case ISD::SMAX: Pred = ISD::SETGT; break;
3314 case ISD::SMIN: Pred = ISD::SETLT; break;
3315 case ISD::UMAX: Pred = ISD::SETUGT; break;
3316 case ISD::UMIN: Pred = ISD::SETULT; break;
3318 Tmp1 = Node->getOperand(0);
3319 Tmp2 = Node->getOperand(1);
3320 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp1, Tmp2, Pred);
3321 Results.push_back(Tmp1);
3326 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
3327 RTLIB::FMIN_F80, RTLIB::FMIN_F128,
3328 RTLIB::FMIN_PPCF128));
3331 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
3332 RTLIB::FMAX_F80, RTLIB::FMAX_F128,
3333 RTLIB::FMAX_PPCF128));
3336 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3337 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3338 RTLIB::SQRT_PPCF128));
3342 EVT VT = Node->getValueType(0);
3343 bool isSIN = Node->getOpcode() == ISD::FSIN;
3344 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3345 // fcos which share the same operand and both are used.
3346 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3347 canCombineSinCosLibcall(Node, TLI, TM))
3348 && useSinCos(Node)) {
3349 SDVTList VTs = DAG.getVTList(VT, VT);
3350 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3352 Tmp1 = Tmp1.getValue(1);
3353 Results.push_back(Tmp1);
3355 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3356 RTLIB::SIN_F80, RTLIB::SIN_F128,
3357 RTLIB::SIN_PPCF128));
3359 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3360 RTLIB::COS_F80, RTLIB::COS_F128,
3361 RTLIB::COS_PPCF128));
3366 // Expand into sincos libcall.
3367 ExpandSinCosLibCall(Node, Results);
3370 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3371 RTLIB::LOG_F80, RTLIB::LOG_F128,
3372 RTLIB::LOG_PPCF128));
3375 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3376 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3377 RTLIB::LOG2_PPCF128));
3380 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3381 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3382 RTLIB::LOG10_PPCF128));
3385 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3386 RTLIB::EXP_F80, RTLIB::EXP_F128,
3387 RTLIB::EXP_PPCF128));
3390 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3391 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3392 RTLIB::EXP2_PPCF128));
3395 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3396 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3397 RTLIB::TRUNC_PPCF128));
3400 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3401 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3402 RTLIB::FLOOR_PPCF128));
3405 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3406 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3407 RTLIB::CEIL_PPCF128));
3410 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3411 RTLIB::RINT_F80, RTLIB::RINT_F128,
3412 RTLIB::RINT_PPCF128));
3414 case ISD::FNEARBYINT:
3415 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3416 RTLIB::NEARBYINT_F64,
3417 RTLIB::NEARBYINT_F80,
3418 RTLIB::NEARBYINT_F128,
3419 RTLIB::NEARBYINT_PPCF128));
3422 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3426 RTLIB::ROUND_PPCF128));
3429 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3430 RTLIB::POWI_F80, RTLIB::POWI_F128,
3431 RTLIB::POWI_PPCF128));
3434 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3435 RTLIB::POW_F80, RTLIB::POW_F128,
3436 RTLIB::POW_PPCF128));
3439 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3440 RTLIB::DIV_F80, RTLIB::DIV_F128,
3441 RTLIB::DIV_PPCF128));
3444 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3445 RTLIB::REM_F80, RTLIB::REM_F128,
3446 RTLIB::REM_PPCF128));
3449 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3450 RTLIB::FMA_F80, RTLIB::FMA_F128,
3451 RTLIB::FMA_PPCF128));
3454 llvm_unreachable("Illegal fmad should never be formed");
3457 Results.push_back(ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
3458 RTLIB::ADD_F80, RTLIB::ADD_F128,
3459 RTLIB::ADD_PPCF128));
3462 Results.push_back(ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
3463 RTLIB::MUL_F80, RTLIB::MUL_F128,
3464 RTLIB::MUL_PPCF128));
3466 case ISD::FP16_TO_FP: {
3467 if (Node->getValueType(0) == MVT::f32) {
3468 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3472 // We can extend to types bigger than f32 in two steps without changing the
3473 // result. Since "f16 -> f32" is much more commonly available, give CodeGen
3474 // the option of emitting that before resorting to a libcall.
3476 DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3478 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
3481 case ISD::FP_TO_FP16: {
3482 if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {
3483 SDValue Op = Node->getOperand(0);
3484 MVT SVT = Op.getSimpleValueType();
3485 if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3486 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3487 // Under fastmath, we can expand this node into a fround followed by
3488 // a float-half conversion.
3489 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
3490 DAG.getIntPtrConstant(0, dl));
3492 DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, FloatVal));
3498 RTLIB::getFPROUND(Node->getOperand(0).getValueType(), MVT::f16);
3499 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
3500 Results.push_back(ExpandLibCall(LC, Node, false));
3503 case ISD::ConstantFP: {
3504 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3505 // Check to see if this FP immediate is already legal.
3506 // If this is a legal constant, turn it into a TargetConstantFP node.
3507 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3508 Results.push_back(ExpandConstantFP(CFP, true));
3512 EVT VT = Node->getValueType(0);
3513 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3514 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3515 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3516 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3517 Results.push_back(Tmp1);
3519 Results.push_back(ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
3520 RTLIB::SUB_F80, RTLIB::SUB_F128,
3521 RTLIB::SUB_PPCF128));
3526 EVT VT = Node->getValueType(0);
3527 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3528 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3529 "Don't know how to expand this subtraction!");
3530 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3531 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
3533 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT));
3534 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3539 EVT VT = Node->getValueType(0);
3540 bool isSigned = Node->getOpcode() == ISD::SREM;
3541 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3542 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3543 Tmp2 = Node->getOperand(0);
3544 Tmp3 = Node->getOperand(1);
3545 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3546 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3547 // If div is legal, it's better to do the normal expansion
3548 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
3549 useDivRem(Node, isSigned, false))) {
3550 SDVTList VTs = DAG.getVTList(VT, VT);
3551 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3552 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3554 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3555 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3556 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3557 } else if (isSigned)
3558 Tmp1 = ExpandIntLibCall(Node, true,
3560 RTLIB::SREM_I16, RTLIB::SREM_I32,
3561 RTLIB::SREM_I64, RTLIB::SREM_I128);
3563 Tmp1 = ExpandIntLibCall(Node, false,
3565 RTLIB::UREM_I16, RTLIB::UREM_I32,
3566 RTLIB::UREM_I64, RTLIB::UREM_I128);
3567 Results.push_back(Tmp1);
3572 bool isSigned = Node->getOpcode() == ISD::SDIV;
3573 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3574 EVT VT = Node->getValueType(0);
3575 SDVTList VTs = DAG.getVTList(VT, VT);
3576 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3577 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3578 useDivRem(Node, isSigned, true)))
3579 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3580 Node->getOperand(1));
3582 Tmp1 = ExpandIntLibCall(Node, true,
3584 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3585 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3587 Tmp1 = ExpandIntLibCall(Node, false,
3589 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3590 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3591 Results.push_back(Tmp1);
3596 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3598 EVT VT = Node->getValueType(0);
3599 SDVTList VTs = DAG.getVTList(VT, VT);
3600 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3601 "If this wasn't legal, it shouldn't have been created!");
3602 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3603 Node->getOperand(1));
3604 Results.push_back(Tmp1.getValue(1));
3609 // Expand into divrem libcall
3610 ExpandDivRemLibCall(Node, Results);
3613 EVT VT = Node->getValueType(0);
3614 SDVTList VTs = DAG.getVTList(VT, VT);
3615 // See if multiply or divide can be lowered using two-result operations.
3616 // We just need the low half of the multiply; try both the signed
3617 // and unsigned forms. If the target supports both SMUL_LOHI and
3618 // UMUL_LOHI, form a preference by checking which forms of plain
3619 // MULH it supports.
3620 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3621 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3622 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3623 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3624 unsigned OpToUse = 0;
3625 if (HasSMUL_LOHI && !HasMULHS) {
3626 OpToUse = ISD::SMUL_LOHI;
3627 } else if (HasUMUL_LOHI && !HasMULHU) {
3628 OpToUse = ISD::UMUL_LOHI;
3629 } else if (HasSMUL_LOHI) {
3630 OpToUse = ISD::SMUL_LOHI;
3631 } else if (HasUMUL_LOHI) {
3632 OpToUse = ISD::UMUL_LOHI;
3635 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3636 Node->getOperand(1)));
3641 EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3642 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3643 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3644 TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3645 TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3646 TLI.expandMUL(Node, Lo, Hi, HalfType, DAG)) {
3647 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3648 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3649 SDValue Shift = DAG.getConstant(HalfType.getSizeInBits(), dl,
3650 TLI.getShiftAmountTy(HalfType));
3651 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3652 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3656 Tmp1 = ExpandIntLibCall(Node, false,
3658 RTLIB::MUL_I16, RTLIB::MUL_I32,
3659 RTLIB::MUL_I64, RTLIB::MUL_I128);
3660 Results.push_back(Tmp1);
3665 SDValue LHS = Node->getOperand(0);
3666 SDValue RHS = Node->getOperand(1);
3667 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3668 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3670 Results.push_back(Sum);
3671 EVT ResultType = Node->getValueType(1);
3672 EVT OType = getSetCCResultType(Node->getValueType(0));
3674 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
3676 // LHSSign -> LHS >= 0
3677 // RHSSign -> RHS >= 0
3678 // SumSign -> Sum >= 0
3681 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3683 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3685 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3686 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3687 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3688 Node->getOpcode() == ISD::SADDO ?
3689 ISD::SETEQ : ISD::SETNE);
3691 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3692 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3694 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3695 Results.push_back(DAG.getBoolExtOrTrunc(Cmp, dl, ResultType, ResultType));
3700 SDValue LHS = Node->getOperand(0);
3701 SDValue RHS = Node->getOperand(1);
3702 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3703 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3705 Results.push_back(Sum);
3707 EVT ResultType = Node->getValueType(1);
3708 EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3710 = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT;
3711 SDValue SetCC = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3713 Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType));
3718 EVT VT = Node->getValueType(0);
3719 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3720 SDValue LHS = Node->getOperand(0);
3721 SDValue RHS = Node->getOperand(1);
3724 static const unsigned Ops[2][3] =
3725 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3726 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3727 bool isSigned = Node->getOpcode() == ISD::SMULO;
3728 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3729 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3730 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3731 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3732 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3734 TopHalf = BottomHalf.getValue(1);
3735 } else if (TLI.isTypeLegal(WideVT)) {
3736 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3737 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3738 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3739 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3740 DAG.getIntPtrConstant(0, dl));
3741 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3742 DAG.getIntPtrConstant(1, dl));
3744 // We can fall back to a libcall with an illegal type for the MUL if we
3745 // have a libcall big enough.
3746 // Also, we can fall back to a division in some cases, but that's a big
3747 // performance hit in the general case.
3748 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3749 if (WideVT == MVT::i16)
3750 LC = RTLIB::MUL_I16;
3751 else if (WideVT == MVT::i32)
3752 LC = RTLIB::MUL_I32;
3753 else if (WideVT == MVT::i64)
3754 LC = RTLIB::MUL_I64;
3755 else if (WideVT == MVT::i128)
3756 LC = RTLIB::MUL_I128;
3757 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3759 // The high part is obtained by SRA'ing all but one of the bits of low
3761 unsigned LoSize = VT.getSizeInBits();
3762 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3763 DAG.getConstant(LoSize - 1, dl,
3764 TLI.getPointerTy()));
3765 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3766 DAG.getConstant(LoSize - 1, dl,
3767 TLI.getPointerTy()));
3769 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3770 // pre-lowered to the correct types. This all depends upon WideVT not
3771 // being a legal type for the architecture and thus has to be split to
3773 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3774 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3775 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3776 DAG.getIntPtrConstant(0, dl));
3777 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3778 DAG.getIntPtrConstant(1, dl));
3779 // Ret is a node with an illegal type. Because such things are not
3780 // generally permitted during this phase of legalization, make sure the
3781 // node has no more uses. The above EXTRACT_ELEMENT nodes should have been
3783 assert(Ret->use_empty() &&
3784 "Unexpected uses of illegally type from expanded lib call.");
3788 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, dl,
3789 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3790 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3791 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3794 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3795 DAG.getConstant(0, dl, VT), ISD::SETNE);
3797 Results.push_back(BottomHalf);
3798 Results.push_back(TopHalf);
3801 case ISD::BUILD_PAIR: {
3802 EVT PairTy = Node->getValueType(0);
3803 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3804 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3805 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3806 DAG.getConstant(PairTy.getSizeInBits()/2, dl,
3807 TLI.getShiftAmountTy(PairTy)));
3808 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3812 Tmp1 = Node->getOperand(0);
3813 Tmp2 = Node->getOperand(1);
3814 Tmp3 = Node->getOperand(2);
3815 if (Tmp1.getOpcode() == ISD::SETCC) {
3816 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3818 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3820 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3821 DAG.getConstant(0, dl, Tmp1.getValueType()),
3822 Tmp2, Tmp3, ISD::SETNE);
3824 Results.push_back(Tmp1);
3827 SDValue Chain = Node->getOperand(0);
3828 SDValue Table = Node->getOperand(1);
3829 SDValue Index = Node->getOperand(2);
3831 EVT PTy = TLI.getPointerTy();
3833 const DataLayout &TD = *TLI.getDataLayout();
3834 unsigned EntrySize =
3835 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3837 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
3838 DAG.getConstant(EntrySize, dl, Index.getValueType()));
3839 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3842 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3843 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3844 MachinePointerInfo::getJumpTable(), MemVT,
3845 false, false, false, 0);
3847 if (TM.getRelocationModel() == Reloc::PIC_) {
3848 // For PIC, the sequence is:
3849 // BRIND(load(Jumptable + index) + RelocBase)
3850 // RelocBase can be JumpTable, GOT or some sort of global base.
3851 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3852 TLI.getPICJumpTableRelocBase(Table, DAG));
3854 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3855 Results.push_back(Tmp1);
3859 // Expand brcond's setcc into its constituent parts and create a BR_CC
3861 Tmp1 = Node->getOperand(0);
3862 Tmp2 = Node->getOperand(1);
3863 if (Tmp2.getOpcode() == ISD::SETCC) {
3864 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3865 Tmp1, Tmp2.getOperand(2),
3866 Tmp2.getOperand(0), Tmp2.getOperand(1),
3867 Node->getOperand(2));
3869 // We test only the i1 bit. Skip the AND if UNDEF.
3870 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3871 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3872 DAG.getConstant(1, dl, Tmp2.getValueType()));
3873 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3874 DAG.getCondCode(ISD::SETNE), Tmp3,
3875 DAG.getConstant(0, dl, Tmp3.getValueType()),
3876 Node->getOperand(2));
3878 Results.push_back(Tmp1);
3881 Tmp1 = Node->getOperand(0);
3882 Tmp2 = Node->getOperand(1);
3883 Tmp3 = Node->getOperand(2);
3884 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3885 Tmp3, NeedInvert, dl);
3888 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3889 // condition code, create a new SETCC node.
3891 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3894 // If we expanded the SETCC by inverting the condition code, then wrap
3895 // the existing SETCC in a NOT to restore the intended condition.
3897 Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3899 Results.push_back(Tmp1);
3903 // Otherwise, SETCC for the given comparison type must be completely
3904 // illegal; expand it into a SELECT_CC.
3905 EVT VT = Node->getValueType(0);
3907 switch (TLI.getBooleanContents(Tmp1->getValueType(0))) {
3908 case TargetLowering::ZeroOrOneBooleanContent:
3909 case TargetLowering::UndefinedBooleanContent:
3912 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3916 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3917 DAG.getConstant(TrueValue, dl, VT),
3918 DAG.getConstant(0, dl, VT),
3920 Results.push_back(Tmp1);
3923 case ISD::SELECT_CC: {
3924 Tmp1 = Node->getOperand(0); // LHS
3925 Tmp2 = Node->getOperand(1); // RHS
3926 Tmp3 = Node->getOperand(2); // True
3927 Tmp4 = Node->getOperand(3); // False
3928 EVT VT = Node->getValueType(0);
3929 SDValue CC = Node->getOperand(4);
3930 ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3932 if (TLI.isCondCodeLegal(CCOp, Tmp1.getSimpleValueType())) {
3933 // If the condition code is legal, then we need to expand this
3934 // node using SETCC and SELECT.
3935 EVT CmpVT = Tmp1.getValueType();
3936 assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3937 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3939 EVT CCVT = TLI.getSetCCResultType(*DAG.getContext(), CmpVT);
3940 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
3941 Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
3945 // SELECT_CC is legal, so the condition code must not be.
3946 bool Legalized = false;
3947 // Try to legalize by inverting the condition. This is for targets that
3948 // might support an ordered version of a condition, but not the unordered
3949 // version (or vice versa).
3950 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
3951 Tmp1.getValueType().isInteger());
3952 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
3953 // Use the new condition code and swap true and false
3955 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3957 // If The inverse is not legal, then try to swap the arguments using
3958 // the inverse condition code.
3959 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3960 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
3961 // The swapped inverse condition is legal, so swap true and false,
3964 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3969 Legalized = LegalizeSetCCCondCode(
3970 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3973 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3975 // If we expanded the SETCC by inverting the condition code, then swap
3976 // the True/False operands to match.
3978 std::swap(Tmp3, Tmp4);
3980 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3981 // condition code, create a new SELECT_CC node.
3983 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3984 Tmp1, Tmp2, Tmp3, Tmp4, CC);
3986 Tmp2 = DAG.getConstant(0, dl, Tmp1.getValueType());
3987 CC = DAG.getCondCode(ISD::SETNE);
3988 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3989 Tmp2, Tmp3, Tmp4, CC);
3992 Results.push_back(Tmp1);
3996 Tmp1 = Node->getOperand(0); // Chain
3997 Tmp2 = Node->getOperand(2); // LHS
3998 Tmp3 = Node->getOperand(3); // RHS
3999 Tmp4 = Node->getOperand(1); // CC
4001 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
4002 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
4004 assert(Legalized && "Can't legalize BR_CC with legal condition!");
4006 // If we expanded the SETCC by inverting the condition code, then wrap
4007 // the existing SETCC in a NOT to restore the intended condition.
4009 Tmp4 = DAG.getNOT(dl, Tmp4, Tmp4->getValueType(0));
4011 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
4013 if (Tmp4.getNode()) {
4014 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
4015 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
4017 Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
4018 Tmp4 = DAG.getCondCode(ISD::SETNE);
4019 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
4020 Tmp2, Tmp3, Node->getOperand(4));
4022 Results.push_back(Tmp1);
4025 case ISD::BUILD_VECTOR:
4026 Results.push_back(ExpandBUILD_VECTOR(Node));
4031 // Scalarize vector SRA/SRL/SHL.
4032 EVT VT = Node->getValueType(0);
4033 assert(VT.isVector() && "Unable to legalize non-vector shift");
4034 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
4035 unsigned NumElem = VT.getVectorNumElements();
4037 SmallVector<SDValue, 8> Scalars;
4038 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
4039 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4041 Node->getOperand(0),
4042 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy()));
4043 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4045 Node->getOperand(1),
4046 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy()));
4047 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
4048 VT.getScalarType(), Ex, Sh));
4051 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Scalars);
4052 ReplaceNode(SDValue(Node, 0), Result);
4055 case ISD::GLOBAL_OFFSET_TABLE:
4056 case ISD::GlobalAddress:
4057 case ISD::GlobalTLSAddress:
4058 case ISD::ExternalSymbol:
4059 case ISD::ConstantPool:
4060 case ISD::JumpTable:
4061 case ISD::INTRINSIC_W_CHAIN:
4062 case ISD::INTRINSIC_WO_CHAIN:
4063 case ISD::INTRINSIC_VOID:
4064 // FIXME: Custom lowering for these operations shouldn't return null!
4068 // Replace the original node with the legalized result.
4069 if (!Results.empty())
4070 ReplaceNode(Node, Results.data());
4073 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4074 SmallVector<SDValue, 8> Results;
4075 MVT OVT = Node->getSimpleValueType(0);
4076 if (Node->getOpcode() == ISD::UINT_TO_FP ||
4077 Node->getOpcode() == ISD::SINT_TO_FP ||
4078 Node->getOpcode() == ISD::SETCC) {
4079 OVT = Node->getOperand(0).getSimpleValueType();
4081 if (Node->getOpcode() == ISD::BR_CC)
4082 OVT = Node->getOperand(2).getSimpleValueType();
4083 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4085 SDValue Tmp1, Tmp2, Tmp3;
4086 switch (Node->getOpcode()) {
4088 case ISD::CTTZ_ZERO_UNDEF:
4090 case ISD::CTLZ_ZERO_UNDEF:
4092 // Zero extend the argument.
4093 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4094 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4095 // already the correct result.
4096 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4097 if (Node->getOpcode() == ISD::CTTZ) {
4098 // FIXME: This should set a bit in the zero extended value instead.
4099 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
4100 Tmp1, DAG.getConstant(NVT.getSizeInBits(), dl, NVT),
4102 Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
4103 DAG.getConstant(OVT.getSizeInBits(), dl, NVT), Tmp1);
4104 } else if (Node->getOpcode() == ISD::CTLZ ||
4105 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4106 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4107 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4108 DAG.getConstant(NVT.getSizeInBits() -
4109 OVT.getSizeInBits(), dl, NVT));
4111 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4114 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4115 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4116 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4117 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
4118 DAG.getConstant(DiffBits, dl,
4119 TLI.getShiftAmountTy(NVT)));
4120 Results.push_back(Tmp1);
4123 case ISD::FP_TO_UINT:
4124 case ISD::FP_TO_SINT:
4125 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4126 Node->getOpcode() == ISD::FP_TO_SINT, dl);
4127 Results.push_back(Tmp1);
4129 case ISD::UINT_TO_FP:
4130 case ISD::SINT_TO_FP:
4131 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4132 Node->getOpcode() == ISD::SINT_TO_FP, dl);
4133 Results.push_back(Tmp1);
4136 SDValue Chain = Node->getOperand(0); // Get the chain.
4137 SDValue Ptr = Node->getOperand(1); // Get the pointer.
4140 if (OVT.isVector()) {
4141 TruncOp = ISD::BITCAST;
4143 assert(OVT.isInteger()
4144 && "VAARG promotion is supported only for vectors or integer types");
4145 TruncOp = ISD::TRUNCATE;
4148 // Perform the larger operation, then convert back
4149 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4150 Node->getConstantOperandVal(3));
4151 Chain = Tmp1.getValue(1);
4153 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4155 // Modified the chain result - switch anything that used the old chain to
4157 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4158 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4160 UpdatedNodes->insert(Tmp2.getNode());
4161 UpdatedNodes->insert(Chain.getNode());
4169 unsigned ExtOp, TruncOp;
4170 if (OVT.isVector()) {
4171 ExtOp = ISD::BITCAST;
4172 TruncOp = ISD::BITCAST;
4174 assert(OVT.isInteger() && "Cannot promote logic operation");
4175 ExtOp = ISD::ANY_EXTEND;
4176 TruncOp = ISD::TRUNCATE;
4178 // Promote each of the values to the new type.
4179 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4180 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4181 // Perform the larger operation, then convert back
4182 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4183 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4187 unsigned ExtOp, TruncOp;
4188 if (Node->getValueType(0).isVector() ||
4189 Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4190 ExtOp = ISD::BITCAST;
4191 TruncOp = ISD::BITCAST;
4192 } else if (Node->getValueType(0).isInteger()) {
4193 ExtOp = ISD::ANY_EXTEND;
4194 TruncOp = ISD::TRUNCATE;
4196 ExtOp = ISD::FP_EXTEND;
4197 TruncOp = ISD::FP_ROUND;
4199 Tmp1 = Node->getOperand(0);
4200 // Promote each of the values to the new type.
4201 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4202 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4203 // Perform the larger operation, then round down.
4204 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4205 if (TruncOp != ISD::FP_ROUND)
4206 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4208 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4209 DAG.getIntPtrConstant(0, dl));
4210 Results.push_back(Tmp1);
4213 case ISD::VECTOR_SHUFFLE: {
4214 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4216 // Cast the two input vectors.
4217 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4218 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4220 // Convert the shuffle mask to the right # elements.
4221 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4222 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4223 Results.push_back(Tmp1);
4227 unsigned ExtOp = ISD::FP_EXTEND;
4228 if (NVT.isInteger()) {
4229 ISD::CondCode CCCode =
4230 cast<CondCodeSDNode>(Node->getOperand(2))->get();
4231 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4233 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4234 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4235 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4236 Tmp1, Tmp2, Node->getOperand(2)));
4240 unsigned ExtOp = ISD::FP_EXTEND;
4241 if (NVT.isInteger()) {
4242 ISD::CondCode CCCode =
4243 cast<CondCodeSDNode>(Node->getOperand(1))->get();
4244 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4246 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4247 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
4248 Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0),
4249 Node->getOperand(0), Node->getOperand(1),
4250 Tmp1, Tmp2, Node->getOperand(4)));
4260 case ISD::FCOPYSIGN:
4262 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4263 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4264 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4265 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4266 Tmp3, DAG.getIntPtrConstant(0, dl)));
4270 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4271 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4272 Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
4274 DAG.getNode(ISD::FP_ROUND, dl, OVT,
4275 DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
4276 DAG.getIntPtrConstant(0, dl)));
4280 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4281 Tmp2 = Node->getOperand(1);
4282 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4283 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4284 Tmp3, DAG.getIntPtrConstant(0, dl)));
4290 case ISD::FNEARBYINT:
4303 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4304 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4305 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4306 Tmp2, DAG.getIntPtrConstant(0, dl)));
4311 // Replace the original node with the legalized result.
4312 if (!Results.empty())
4313 ReplaceNode(Node, Results.data());
4316 /// This is the entry point for the file.
4317 void SelectionDAG::Legalize() {
4318 AssignTopologicalOrder();
4320 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4321 SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
4323 // Visit all the nodes. We start in topological order, so that we see
4324 // nodes with their original operands intact. Legalization can produce
4325 // new nodes which may themselves need to be legalized. Iterate until all
4326 // nodes have been legalized.
4328 bool AnyLegalized = false;
4329 for (auto NI = allnodes_end(); NI != allnodes_begin();) {
4333 if (N->use_empty() && N != getRoot().getNode()) {
4339 if (LegalizedNodes.insert(N).second) {
4340 AnyLegalized = true;
4341 Legalizer.LegalizeOp(N);
4343 if (N->use_empty() && N != getRoot().getNode()) {
4354 // Remove dead nodes now.
4358 bool SelectionDAG::LegalizeOp(SDNode *N,
4359 SmallSetVector<SDNode *, 16> &UpdatedNodes) {
4360 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4361 SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
4363 // Directly insert the node in question, and legalize it. This will recurse
4364 // as needed through operands.
4365 LegalizedNodes.insert(N);
4366 Legalizer.LegalizeOp(N);
4368 return LegalizedNodes.count(N);