1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/DwarfWriter.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetSubtarget.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/DerivedTypes.h"
31 #include "llvm/Function.h"
32 #include "llvm/GlobalVariable.h"
33 #include "llvm/LLVMContext.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Compiler.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/ADT/DenseMap.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/ADT/SmallPtrSet.h"
44 //===----------------------------------------------------------------------===//
45 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
46 /// hacks on it until the target machine can handle it. This involves
47 /// eliminating value sizes the machine cannot handle (promoting small sizes to
48 /// large sizes or splitting up large values into small values) as well as
49 /// eliminating operations the machine cannot handle.
51 /// This code also does a small amount of optimization and recognition of idioms
52 /// as part of its processing. For example, if a target does not support a
53 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
54 /// will attempt merge setcc and brc instructions into brcc's.
57 class VISIBILITY_HIDDEN SelectionDAGLegalize {
60 CodeGenOpt::Level OptLevel;
62 // Libcall insertion helpers.
64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
65 /// legalized. We use this to ensure that calls are properly serialized
66 /// against each other, including inserted libcalls.
67 SDValue LastCALLSEQ_END;
69 /// IsLegalizingCall - This member is used *only* for purposes of providing
70 /// helpful assertions that a libcall isn't created while another call is
71 /// being legalized (which could lead to non-serialized call sequences).
72 bool IsLegalizingCall;
75 Legal, // The target natively supports this operation.
76 Promote, // This operation should be executed in a larger type.
77 Expand // Try to expand this to other ops, otherwise use a libcall.
80 /// ValueTypeActions - This is a bitvector that contains two bits for each
81 /// value type, where the two bits correspond to the LegalizeAction enum.
82 /// This can be queried with "getTypeAction(VT)".
83 TargetLowering::ValueTypeActionImpl ValueTypeActions;
85 /// LegalizedNodes - For nodes that are of legal width, and that have more
86 /// than one use, this map indicates what regularized operand to use. This
87 /// allows us to avoid legalizing the same thing more than once.
88 DenseMap<SDValue, SDValue> LegalizedNodes;
90 void AddLegalizedOperand(SDValue From, SDValue To) {
91 LegalizedNodes.insert(std::make_pair(From, To));
92 // If someone requests legalization of the new node, return itself.
94 LegalizedNodes.insert(std::make_pair(To, To));
98 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol);
100 /// getTypeAction - Return how we should legalize values of this type, either
101 /// it is already legal or we need to expand it into multiple registers of
102 /// smaller integer type, or we need to promote it to a larger type.
103 LegalizeAction getTypeAction(MVT VT) const {
104 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
107 /// isTypeLegal - Return true if this type is legal on this target.
109 bool isTypeLegal(MVT VT) const {
110 return getTypeAction(VT) == Legal;
116 /// LegalizeOp - We know that the specified value has a legal type.
117 /// Recursively ensure that the operands have legal types, then return the
119 SDValue LegalizeOp(SDValue O);
121 SDValue OptimizeFloatStore(StoreSDNode *ST);
123 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
124 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
125 /// is necessary to spill the vector being inserted into to memory, perform
126 /// the insert there, and then read the result back.
127 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
128 SDValue Idx, DebugLoc dl);
129 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
130 SDValue Idx, DebugLoc dl);
132 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
133 /// performs the same shuffe in terms of order or result bytes, but on a type
134 /// whose vector element type is narrower than the original shuffle type.
135 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
136 SDValue ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl,
137 SDValue N1, SDValue N2,
138 SmallVectorImpl<int> &Mask) const;
140 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
141 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
143 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
146 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
147 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
148 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
149 RTLIB::Libcall Call_PPCF128);
150 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, RTLIB::Libcall Call_I16,
151 RTLIB::Libcall Call_I32, RTLIB::Libcall Call_I64,
152 RTLIB::Libcall Call_I128);
154 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl);
155 SDValue ExpandBUILD_VECTOR(SDNode *Node);
156 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
157 SDValue ExpandDBG_STOPPOINT(SDNode *Node);
158 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
159 SmallVectorImpl<SDValue> &Results);
160 SDValue ExpandFCOPYSIGN(SDNode *Node);
161 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT,
163 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned,
165 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned,
168 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
169 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
171 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
172 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
174 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
175 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
179 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
180 /// performs the same shuffe in terms of order or result bytes, but on a type
181 /// whose vector element type is narrower than the original shuffle type.
182 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
184 SelectionDAGLegalize::ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl,
185 SDValue N1, SDValue N2,
186 SmallVectorImpl<int> &Mask) const {
187 MVT EltVT = NVT.getVectorElementType();
188 unsigned NumMaskElts = VT.getVectorNumElements();
189 unsigned NumDestElts = NVT.getVectorNumElements();
190 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
192 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
194 if (NumEltsGrowth == 1)
195 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
197 SmallVector<int, 8> NewMask;
198 for (unsigned i = 0; i != NumMaskElts; ++i) {
200 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
202 NewMask.push_back(-1);
204 NewMask.push_back(Idx * NumEltsGrowth + j);
207 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
208 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
209 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
212 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
213 CodeGenOpt::Level ol)
214 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
215 ValueTypeActions(TLI.getValueTypeActions()) {
216 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
217 "Too many value types for ValueTypeActions to hold!");
220 void SelectionDAGLegalize::LegalizeDAG() {
221 LastCALLSEQ_END = DAG.getEntryNode();
222 IsLegalizingCall = false;
224 // The legalize process is inherently a bottom-up recursive process (users
225 // legalize their uses before themselves). Given infinite stack space, we
226 // could just start legalizing on the root and traverse the whole graph. In
227 // practice however, this causes us to run out of stack space on large basic
228 // blocks. To avoid this problem, compute an ordering of the nodes where each
229 // node is only legalized after all of its operands are legalized.
230 DAG.AssignTopologicalOrder();
231 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
232 E = prior(DAG.allnodes_end()); I != next(E); ++I)
233 LegalizeOp(SDValue(I, 0));
235 // Finally, it's possible the root changed. Get the new root.
236 SDValue OldRoot = DAG.getRoot();
237 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
238 DAG.setRoot(LegalizedNodes[OldRoot]);
240 LegalizedNodes.clear();
242 // Remove dead nodes now.
243 DAG.RemoveDeadNodes();
247 /// FindCallEndFromCallStart - Given a chained node that is part of a call
248 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
249 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
250 if (Node->getOpcode() == ISD::CALLSEQ_END)
252 if (Node->use_empty())
253 return 0; // No CallSeqEnd
255 // The chain is usually at the end.
256 SDValue TheChain(Node, Node->getNumValues()-1);
257 if (TheChain.getValueType() != MVT::Other) {
258 // Sometimes it's at the beginning.
259 TheChain = SDValue(Node, 0);
260 if (TheChain.getValueType() != MVT::Other) {
261 // Otherwise, hunt for it.
262 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
263 if (Node->getValueType(i) == MVT::Other) {
264 TheChain = SDValue(Node, i);
268 // Otherwise, we walked into a node without a chain.
269 if (TheChain.getValueType() != MVT::Other)
274 for (SDNode::use_iterator UI = Node->use_begin(),
275 E = Node->use_end(); UI != E; ++UI) {
277 // Make sure to only follow users of our token chain.
279 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
280 if (User->getOperand(i) == TheChain)
281 if (SDNode *Result = FindCallEndFromCallStart(User))
287 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
288 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
289 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
290 assert(Node && "Didn't find callseq_start for a call??");
291 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
293 assert(Node->getOperand(0).getValueType() == MVT::Other &&
294 "Node doesn't have a token chain argument!");
295 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
298 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
299 /// see if any uses can reach Dest. If no dest operands can get to dest,
300 /// legalize them, legalize ourself, and return false, otherwise, return true.
302 /// Keep track of the nodes we fine that actually do lead to Dest in
303 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
305 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
306 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
307 if (N == Dest) return true; // N certainly leads to Dest :)
309 // If we've already processed this node and it does lead to Dest, there is no
310 // need to reprocess it.
311 if (NodesLeadingTo.count(N)) return true;
313 // If the first result of this node has been already legalized, then it cannot
315 if (LegalizedNodes.count(SDValue(N, 0))) return false;
317 // Okay, this node has not already been legalized. Check and legalize all
318 // operands. If none lead to Dest, then we can legalize this node.
319 bool OperandsLeadToDest = false;
320 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
321 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
322 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
324 if (OperandsLeadToDest) {
325 NodesLeadingTo.insert(N);
329 // Okay, this node looks safe, legalize it and return false.
330 LegalizeOp(SDValue(N, 0));
334 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
335 /// a load from the constant pool.
336 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
337 SelectionDAG &DAG, const TargetLowering &TLI) {
339 DebugLoc dl = CFP->getDebugLoc();
340 LLVMContext *Context = DAG.getContext();
342 // If a FP immediate is precise when represented as a float and if the
343 // target can do an extending load from float to double, we put it into
344 // the constant pool as a float, even if it's is statically typed as a
345 // double. This shrinks FP constants and canonicalizes them for targets where
346 // an FP extending load is the same cost as a normal load (such as on the x87
347 // fp stack or PPC FP unit).
348 MVT VT = CFP->getValueType(0);
349 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
351 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
352 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
353 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
358 while (SVT != MVT::f32) {
359 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
360 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
361 // Only do this if the target has a native EXTLOAD instruction from
363 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
364 TLI.ShouldShrinkFPConstant(OrigVT)) {
365 const Type *SType = SVT.getTypeForMVT(*DAG.getContext());
366 LLVMC = cast<ConstantFP>(Context->getConstantExprFPTrunc(LLVMC, SType));
372 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
373 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
375 return DAG.getExtLoad(ISD::EXTLOAD, dl,
376 OrigVT, DAG.getEntryNode(),
377 CPIdx, PseudoSourceValue::getConstantPool(),
378 0, VT, false, Alignment);
379 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
380 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
383 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
385 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
386 const TargetLowering &TLI) {
387 SDValue Chain = ST->getChain();
388 SDValue Ptr = ST->getBasePtr();
389 SDValue Val = ST->getValue();
390 MVT VT = Val.getValueType();
391 int Alignment = ST->getAlignment();
392 int SVOffset = ST->getSrcValueOffset();
393 DebugLoc dl = ST->getDebugLoc();
394 if (ST->getMemoryVT().isFloatingPoint() ||
395 ST->getMemoryVT().isVector()) {
396 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
397 if (TLI.isTypeLegal(intVT)) {
398 // Expand to a bitconvert of the value to the integer type of the
399 // same size, then a (misaligned) int store.
400 // FIXME: Does not handle truncating floating point stores!
401 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
402 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
403 SVOffset, ST->isVolatile(), Alignment);
405 // Do a (aligned) store to a stack slot, then copy from the stack slot
406 // to the final destination using (unaligned) integer loads and stores.
407 MVT StoredVT = ST->getMemoryVT();
409 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
410 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
411 unsigned RegBytes = RegVT.getSizeInBits() / 8;
412 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
414 // Make sure the stack slot is also aligned for the register type.
415 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
417 // Perform the original store, only redirected to the stack slot.
418 SDValue Store = DAG.getTruncStore(Chain, dl,
419 Val, StackPtr, NULL, 0, StoredVT);
420 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
421 SmallVector<SDValue, 8> Stores;
424 // Do all but one copies using the full register width.
425 for (unsigned i = 1; i < NumRegs; i++) {
426 // Load one integer register's worth from the stack slot.
427 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0);
428 // Store it to the final location. Remember the store.
429 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
430 ST->getSrcValue(), SVOffset + Offset,
432 MinAlign(ST->getAlignment(), Offset)));
433 // Increment the pointers.
435 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
437 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
440 // The last store may be partial. Do a truncating store. On big-endian
441 // machines this requires an extending load from the stack slot to ensure
442 // that the bits are in the right place.
443 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
445 // Load from the stack slot.
446 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
449 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
450 ST->getSrcValue(), SVOffset + Offset,
451 MemVT, ST->isVolatile(),
452 MinAlign(ST->getAlignment(), Offset)));
453 // The order of the stores doesn't matter - say it with a TokenFactor.
454 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
458 assert(ST->getMemoryVT().isInteger() &&
459 !ST->getMemoryVT().isVector() &&
460 "Unaligned store of unknown type.");
461 // Get the half-size VT
463 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
464 int NumBits = NewStoredVT.getSizeInBits();
465 int IncrementSize = NumBits / 8;
467 // Divide the stored value in two parts.
468 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
470 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
472 // Store the two parts
473 SDValue Store1, Store2;
474 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
475 ST->getSrcValue(), SVOffset, NewStoredVT,
476 ST->isVolatile(), Alignment);
477 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
478 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
479 Alignment = MinAlign(Alignment, IncrementSize);
480 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
481 ST->getSrcValue(), SVOffset + IncrementSize,
482 NewStoredVT, ST->isVolatile(), Alignment);
484 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
487 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
489 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
490 const TargetLowering &TLI) {
491 int SVOffset = LD->getSrcValueOffset();
492 SDValue Chain = LD->getChain();
493 SDValue Ptr = LD->getBasePtr();
494 MVT VT = LD->getValueType(0);
495 MVT LoadedVT = LD->getMemoryVT();
496 DebugLoc dl = LD->getDebugLoc();
497 if (VT.isFloatingPoint() || VT.isVector()) {
498 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
499 if (TLI.isTypeLegal(intVT)) {
500 // Expand to a (misaligned) integer load of the same size,
501 // then bitconvert to floating point or vector.
502 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
503 SVOffset, LD->isVolatile(),
505 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
506 if (VT.isFloatingPoint() && LoadedVT != VT)
507 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
509 SDValue Ops[] = { Result, Chain };
510 return DAG.getMergeValues(Ops, 2, dl);
512 // Copy the value to a (aligned) stack slot using (unaligned) integer
513 // loads and stores, then do a (aligned) load from the stack slot.
514 MVT RegVT = TLI.getRegisterType(intVT);
515 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
516 unsigned RegBytes = RegVT.getSizeInBits() / 8;
517 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
519 // Make sure the stack slot is also aligned for the register type.
520 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
522 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
523 SmallVector<SDValue, 8> Stores;
524 SDValue StackPtr = StackBase;
527 // Do all but one copies using the full register width.
528 for (unsigned i = 1; i < NumRegs; i++) {
529 // Load one integer register's worth from the original location.
530 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
531 SVOffset + Offset, LD->isVolatile(),
532 MinAlign(LD->getAlignment(), Offset));
533 // Follow the load with a store to the stack slot. Remember the store.
534 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
536 // Increment the pointers.
538 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
539 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
543 // The last copy may be partial. Do an extending load.
544 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
545 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
546 LD->getSrcValue(), SVOffset + Offset,
547 MemVT, LD->isVolatile(),
548 MinAlign(LD->getAlignment(), Offset));
549 // Follow the load with a store to the stack slot. Remember the store.
550 // On big-endian machines this requires a truncating store to ensure
551 // that the bits end up in the right place.
552 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
555 // The order of the stores doesn't matter - say it with a TokenFactor.
556 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
559 // Finally, perform the original load only redirected to the stack slot.
560 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
563 // Callers expect a MERGE_VALUES node.
564 SDValue Ops[] = { Load, TF };
565 return DAG.getMergeValues(Ops, 2, dl);
568 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
569 "Unaligned load of unsupported type.");
571 // Compute the new VT that is half the size of the old one. This is an
573 unsigned NumBits = LoadedVT.getSizeInBits();
575 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
578 unsigned Alignment = LD->getAlignment();
579 unsigned IncrementSize = NumBits / 8;
580 ISD::LoadExtType HiExtType = LD->getExtensionType();
582 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
583 if (HiExtType == ISD::NON_EXTLOAD)
584 HiExtType = ISD::ZEXTLOAD;
586 // Load the value in two parts
588 if (TLI.isLittleEndian()) {
589 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
590 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
591 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
592 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
593 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
594 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
595 MinAlign(Alignment, IncrementSize));
597 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
598 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
599 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
600 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
601 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
602 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
603 MinAlign(Alignment, IncrementSize));
606 // aggregate the two parts
607 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
608 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
609 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
611 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
614 SDValue Ops[] = { Result, TF };
615 return DAG.getMergeValues(Ops, 2, dl);
618 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
619 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
620 /// is necessary to spill the vector being inserted into to memory, perform
621 /// the insert there, and then read the result back.
622 SDValue SelectionDAGLegalize::
623 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
629 // If the target doesn't support this, we have to spill the input vector
630 // to a temporary stack slot, update the element, then reload it. This is
631 // badness. We could also load the value into a vector register (either
632 // with a "move to register" or "extload into register" instruction, then
633 // permute it into place, if the idx is a constant and if the idx is
634 // supported by the target.
635 MVT VT = Tmp1.getValueType();
636 MVT EltVT = VT.getVectorElementType();
637 MVT IdxVT = Tmp3.getValueType();
638 MVT PtrVT = TLI.getPointerTy();
639 SDValue StackPtr = DAG.CreateStackTemporary(VT);
641 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
644 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
645 PseudoSourceValue::getFixedStack(SPFI), 0);
647 // Truncate or zero extend offset to target pointer type.
648 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
649 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
650 // Add the offset to the index.
651 unsigned EltSize = EltVT.getSizeInBits()/8;
652 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
653 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
654 // Store the scalar value.
655 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
656 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
657 // Load the updated vector.
658 return DAG.getLoad(VT, dl, Ch, StackPtr,
659 PseudoSourceValue::getFixedStack(SPFI), 0);
663 SDValue SelectionDAGLegalize::
664 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
665 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
666 // SCALAR_TO_VECTOR requires that the type of the value being inserted
667 // match the element type of the vector being created, except for
668 // integers in which case the inserted value can be over width.
669 MVT EltVT = Vec.getValueType().getVectorElementType();
670 if (Val.getValueType() == EltVT ||
671 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
672 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
673 Vec.getValueType(), Val);
675 unsigned NumElts = Vec.getValueType().getVectorNumElements();
676 // We generate a shuffle of InVec and ScVec, so the shuffle mask
677 // should be 0,1,2,3,4,5... with the appropriate element replaced with
679 SmallVector<int, 8> ShufOps;
680 for (unsigned i = 0; i != NumElts; ++i)
681 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
683 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
687 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
690 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
691 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
692 // FIXME: We shouldn't do this for TargetConstantFP's.
693 // FIXME: move this to the DAG Combiner! Note that we can't regress due
694 // to phase ordering between legalized code and the dag combiner. This
695 // probably means that we need to integrate dag combiner and legalizer
697 // We generally can't do this one for long doubles.
698 SDValue Tmp1 = ST->getChain();
699 SDValue Tmp2 = ST->getBasePtr();
701 int SVOffset = ST->getSrcValueOffset();
702 unsigned Alignment = ST->getAlignment();
703 bool isVolatile = ST->isVolatile();
704 DebugLoc dl = ST->getDebugLoc();
705 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
706 if (CFP->getValueType(0) == MVT::f32 &&
707 getTypeAction(MVT::i32) == Legal) {
708 Tmp3 = DAG.getConstant(CFP->getValueAPF().
709 bitcastToAPInt().zextOrTrunc(32),
711 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
712 SVOffset, isVolatile, Alignment);
713 } else if (CFP->getValueType(0) == MVT::f64) {
714 // If this target supports 64-bit registers, do a single 64-bit store.
715 if (getTypeAction(MVT::i64) == Legal) {
716 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
717 zextOrTrunc(64), MVT::i64);
718 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
719 SVOffset, isVolatile, Alignment);
720 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
721 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
722 // stores. If the target supports neither 32- nor 64-bits, this
723 // xform is certainly not worth it.
724 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
725 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
726 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
727 if (TLI.isBigEndian()) std::swap(Lo, Hi);
729 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
730 SVOffset, isVolatile, Alignment);
731 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
732 DAG.getIntPtrConstant(4));
733 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
734 isVolatile, MinAlign(Alignment, 4U));
736 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
743 /// LegalizeOp - We know that the specified value has a legal type, and
744 /// that its operands are legal. Now ensure that the operation itself
745 /// is legal, recursively ensuring that the operands' operations remain
747 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
748 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
751 SDNode *Node = Op.getNode();
752 DebugLoc dl = Node->getDebugLoc();
754 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
755 assert(getTypeAction(Node->getValueType(i)) == Legal &&
756 "Unexpected illegal type!");
758 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
759 assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
760 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
761 "Unexpected illegal type!");
763 // Note that LegalizeOp may be reentered even from single-use nodes, which
764 // means that we always must cache transformed nodes.
765 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
766 if (I != LegalizedNodes.end()) return I->second;
768 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
770 bool isCustom = false;
772 // Figure out the correct action; the way to query this varies by opcode
773 TargetLowering::LegalizeAction Action;
774 bool SimpleFinishLegalizing = true;
775 switch (Node->getOpcode()) {
776 case ISD::INTRINSIC_W_CHAIN:
777 case ISD::INTRINSIC_WO_CHAIN:
778 case ISD::INTRINSIC_VOID:
781 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
783 case ISD::SINT_TO_FP:
784 case ISD::UINT_TO_FP:
785 case ISD::EXTRACT_VECTOR_ELT:
786 Action = TLI.getOperationAction(Node->getOpcode(),
787 Node->getOperand(0).getValueType());
789 case ISD::FP_ROUND_INREG:
790 case ISD::SIGN_EXTEND_INREG: {
791 MVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
792 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
798 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
799 Node->getOpcode() == ISD::SETCC ? 2 : 1;
800 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
801 MVT OpVT = Node->getOperand(CompareOperand).getValueType();
802 ISD::CondCode CCCode =
803 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
804 Action = TLI.getCondCodeAction(CCCode, OpVT);
805 if (Action == TargetLowering::Legal) {
806 if (Node->getOpcode() == ISD::SELECT_CC)
807 Action = TLI.getOperationAction(Node->getOpcode(),
808 Node->getValueType(0));
810 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
816 // FIXME: Model these properly. LOAD and STORE are complicated, and
817 // STORE expects the unlegalized operand in some cases.
818 SimpleFinishLegalizing = false;
820 case ISD::CALLSEQ_START:
821 case ISD::CALLSEQ_END:
822 // FIXME: This shouldn't be necessary. These nodes have special properties
823 // dealing with the recursive nature of legalization. Removing this
824 // special case should be done as part of making LegalizeDAG non-recursive.
825 SimpleFinishLegalizing = false;
828 // FIXME: Legalization for calls requires custom-lowering the call before
829 // legalizing the operands! (I haven't looked into precisely why.)
830 SimpleFinishLegalizing = false;
832 case ISD::EXTRACT_ELEMENT:
833 case ISD::FLT_ROUNDS_:
841 case ISD::MERGE_VALUES:
843 case ISD::FRAME_TO_ARGS_OFFSET:
844 // These operations lie about being legal: when they claim to be legal,
845 // they should actually be expanded.
846 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
847 if (Action == TargetLowering::Legal)
848 Action = TargetLowering::Expand;
850 case ISD::TRAMPOLINE:
852 case ISD::RETURNADDR:
853 case ISD::FORMAL_ARGUMENTS:
854 // These operations lie about being legal: when they claim to be legal,
855 // they should actually be custom-lowered.
856 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
857 if (Action == TargetLowering::Legal)
858 Action = TargetLowering::Custom;
860 case ISD::BUILD_VECTOR:
861 // A weird case: legalization for BUILD_VECTOR never legalizes the
863 // FIXME: This really sucks... changing it isn't semantically incorrect,
864 // but it massively pessimizes the code for floating-point BUILD_VECTORs
865 // because ConstantFP operands get legalized into constant pool loads
866 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
867 // though, because BUILD_VECTORS usually get lowered into other nodes
868 // which get legalized properly.
869 SimpleFinishLegalizing = false;
872 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
873 Action = TargetLowering::Legal;
875 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
880 if (SimpleFinishLegalizing) {
881 SmallVector<SDValue, 8> Ops, ResultVals;
882 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
883 Ops.push_back(LegalizeOp(Node->getOperand(i)));
884 switch (Node->getOpcode()) {
892 // Branches tweak the chain to include LastCALLSEQ_END
893 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
895 Ops[0] = LegalizeOp(Ops[0]);
896 LastCALLSEQ_END = DAG.getEntryNode();
903 // Legalizing shifts/rotates requires adjusting the shift amount
904 // to the appropriate width.
905 if (!Ops[1].getValueType().isVector())
906 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1]));
910 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(),
913 case TargetLowering::Legal:
914 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
915 ResultVals.push_back(Result.getValue(i));
917 case TargetLowering::Custom:
918 // FIXME: The handling for custom lowering with multiple results is
920 Tmp1 = TLI.LowerOperation(Result, DAG);
921 if (Tmp1.getNode()) {
922 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
924 ResultVals.push_back(Tmp1);
926 ResultVals.push_back(Tmp1.getValue(i));
932 case TargetLowering::Expand:
933 ExpandNode(Result.getNode(), ResultVals);
935 case TargetLowering::Promote:
936 PromoteNode(Result.getNode(), ResultVals);
939 if (!ResultVals.empty()) {
940 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
941 if (ResultVals[i] != SDValue(Node, i))
942 ResultVals[i] = LegalizeOp(ResultVals[i]);
943 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
945 return ResultVals[Op.getResNo()];
949 switch (Node->getOpcode()) {
952 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
954 llvm_unreachable("Do not know how to legalize this operator!");
956 // The only option for this is to custom lower it.
957 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
958 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
959 // A call within a calling sequence must be legalized to something
960 // other than the normal CALLSEQ_END. Violating this gets Legalize
961 // into an infinite loop.
962 assert ((!IsLegalizingCall ||
963 Node->getOpcode() != ISD::CALL ||
964 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
965 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
967 // The number of incoming and outgoing values should match; unless the final
968 // outgoing value is a flag.
969 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
970 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
971 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
973 "Lowering call/formal_arguments produced unexpected # results!");
975 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
976 // remember that we legalized all of them, so it doesn't get relegalized.
977 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
978 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
980 Tmp1 = LegalizeOp(Tmp3.getValue(i));
981 if (Op.getResNo() == i)
983 AddLegalizedOperand(SDValue(Node, i), Tmp1);
986 case ISD::BUILD_VECTOR:
987 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
988 default: llvm_unreachable("This action is not supported yet!");
989 case TargetLowering::Custom:
990 Tmp3 = TLI.LowerOperation(Result, DAG);
991 if (Tmp3.getNode()) {
996 case TargetLowering::Expand:
997 Result = ExpandBUILD_VECTOR(Result.getNode());
1001 case ISD::CALLSEQ_START: {
1002 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1004 // Recursively Legalize all of the inputs of the call end that do not lead
1005 // to this call start. This ensures that any libcalls that need be inserted
1006 // are inserted *before* the CALLSEQ_START.
1007 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1008 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1009 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1013 // Now that we legalized all of the inputs (which may have inserted
1014 // libcalls) create the new CALLSEQ_START node.
1015 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1017 // Merge in the last call, to ensure that this call start after the last
1019 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1020 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1021 Tmp1, LastCALLSEQ_END);
1022 Tmp1 = LegalizeOp(Tmp1);
1025 // Do not try to legalize the target-specific arguments (#1+).
1026 if (Tmp1 != Node->getOperand(0)) {
1027 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1029 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1032 // Remember that the CALLSEQ_START is legalized.
1033 AddLegalizedOperand(Op.getValue(0), Result);
1034 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1035 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1037 // Now that the callseq_start and all of the non-call nodes above this call
1038 // sequence have been legalized, legalize the call itself. During this
1039 // process, no libcalls can/will be inserted, guaranteeing that no calls
1041 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1042 // Note that we are selecting this call!
1043 LastCALLSEQ_END = SDValue(CallEnd, 0);
1044 IsLegalizingCall = true;
1046 // Legalize the call, starting from the CALLSEQ_END.
1047 LegalizeOp(LastCALLSEQ_END);
1048 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1051 case ISD::CALLSEQ_END:
1052 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1053 // will cause this node to be legalized as well as handling libcalls right.
1054 if (LastCALLSEQ_END.getNode() != Node) {
1055 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1056 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1057 assert(I != LegalizedNodes.end() &&
1058 "Legalizing the call start should have legalized this node!");
1062 // Otherwise, the call start has been legalized and everything is going
1063 // according to plan. Just legalize ourselves normally here.
1064 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1065 // Do not try to legalize the target-specific arguments (#1+), except for
1066 // an optional flag input.
1067 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1068 if (Tmp1 != Node->getOperand(0)) {
1069 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1071 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1074 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1075 if (Tmp1 != Node->getOperand(0) ||
1076 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1077 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1080 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1083 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1084 // This finishes up call legalization.
1085 IsLegalizingCall = false;
1087 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1088 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1089 if (Node->getNumValues() == 2)
1090 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1091 return Result.getValue(Op.getResNo());
1093 LoadSDNode *LD = cast<LoadSDNode>(Node);
1094 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1095 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1097 ISD::LoadExtType ExtType = LD->getExtensionType();
1098 if (ExtType == ISD::NON_EXTLOAD) {
1099 MVT VT = Node->getValueType(0);
1100 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1101 Tmp3 = Result.getValue(0);
1102 Tmp4 = Result.getValue(1);
1104 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1105 default: llvm_unreachable("This action is not supported yet!");
1106 case TargetLowering::Legal:
1107 // If this is an unaligned load and the target doesn't support it,
1109 if (!TLI.allowsUnalignedMemoryAccesses()) {
1110 unsigned ABIAlignment = TLI.getTargetData()->
1111 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT(
1112 *DAG.getContext()));
1113 if (LD->getAlignment() < ABIAlignment){
1114 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
1116 Tmp3 = Result.getOperand(0);
1117 Tmp4 = Result.getOperand(1);
1118 Tmp3 = LegalizeOp(Tmp3);
1119 Tmp4 = LegalizeOp(Tmp4);
1123 case TargetLowering::Custom:
1124 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1125 if (Tmp1.getNode()) {
1126 Tmp3 = LegalizeOp(Tmp1);
1127 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1130 case TargetLowering::Promote: {
1131 // Only promote a load of vector type to another.
1132 assert(VT.isVector() && "Cannot promote this load!");
1133 // Change base type to a different vector type.
1134 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1136 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1137 LD->getSrcValueOffset(),
1138 LD->isVolatile(), LD->getAlignment());
1139 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
1140 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1144 // Since loads produce two values, make sure to remember that we
1145 // legalized both of them.
1146 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1147 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1148 return Op.getResNo() ? Tmp4 : Tmp3;
1150 MVT SrcVT = LD->getMemoryVT();
1151 unsigned SrcWidth = SrcVT.getSizeInBits();
1152 int SVOffset = LD->getSrcValueOffset();
1153 unsigned Alignment = LD->getAlignment();
1154 bool isVolatile = LD->isVolatile();
1156 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1157 // Some targets pretend to have an i1 loading operation, and actually
1158 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1159 // bits are guaranteed to be zero; it helps the optimizers understand
1160 // that these bits are zero. It is also useful for EXTLOAD, since it
1161 // tells the optimizers that those bits are undefined. It would be
1162 // nice to have an effective generic way of getting these benefits...
1163 // Until such a way is found, don't insist on promoting i1 here.
1164 (SrcVT != MVT::i1 ||
1165 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1166 // Promote to a byte-sized load if not loading an integral number of
1167 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1168 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1169 MVT NVT = MVT::getIntegerVT(NewWidth);
1172 // The extra bits are guaranteed to be zero, since we stored them that
1173 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1175 ISD::LoadExtType NewExtType =
1176 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1178 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
1179 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1180 NVT, isVolatile, Alignment);
1182 Ch = Result.getValue(1); // The chain.
1184 if (ExtType == ISD::SEXTLOAD)
1185 // Having the top bits zero doesn't help when sign extending.
1186 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1187 Result.getValueType(),
1188 Result, DAG.getValueType(SrcVT));
1189 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1190 // All the top bits are guaranteed to be zero - inform the optimizers.
1191 Result = DAG.getNode(ISD::AssertZext, dl,
1192 Result.getValueType(), Result,
1193 DAG.getValueType(SrcVT));
1195 Tmp1 = LegalizeOp(Result);
1196 Tmp2 = LegalizeOp(Ch);
1197 } else if (SrcWidth & (SrcWidth - 1)) {
1198 // If not loading a power-of-2 number of bits, expand as two loads.
1199 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
1200 "Unsupported extload!");
1201 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1202 assert(RoundWidth < SrcWidth);
1203 unsigned ExtraWidth = SrcWidth - RoundWidth;
1204 assert(ExtraWidth < RoundWidth);
1205 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1206 "Load size not an integral number of bytes!");
1207 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
1208 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
1210 unsigned IncrementSize;
1212 if (TLI.isLittleEndian()) {
1213 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1214 // Load the bottom RoundWidth bits.
1215 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
1216 Node->getValueType(0), Tmp1, Tmp2,
1217 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1220 // Load the remaining ExtraWidth bits.
1221 IncrementSize = RoundWidth / 8;
1222 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1223 DAG.getIntPtrConstant(IncrementSize));
1224 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1225 LD->getSrcValue(), SVOffset + IncrementSize,
1226 ExtraVT, isVolatile,
1227 MinAlign(Alignment, IncrementSize));
1229 // Build a factor node to remember that this load is independent of the
1231 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1234 // Move the top bits to the right place.
1235 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1236 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1238 // Join the hi and lo parts.
1239 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1241 // Big endian - avoid unaligned loads.
1242 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1243 // Load the top RoundWidth bits.
1244 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1245 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1248 // Load the remaining ExtraWidth bits.
1249 IncrementSize = RoundWidth / 8;
1250 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1251 DAG.getIntPtrConstant(IncrementSize));
1252 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
1253 Node->getValueType(0), Tmp1, Tmp2,
1254 LD->getSrcValue(), SVOffset + IncrementSize,
1255 ExtraVT, isVolatile,
1256 MinAlign(Alignment, IncrementSize));
1258 // Build a factor node to remember that this load is independent of the
1260 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1263 // Move the top bits to the right place.
1264 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1265 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1267 // Join the hi and lo parts.
1268 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1271 Tmp1 = LegalizeOp(Result);
1272 Tmp2 = LegalizeOp(Ch);
1274 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1275 default: llvm_unreachable("This action is not supported yet!");
1276 case TargetLowering::Custom:
1279 case TargetLowering::Legal:
1280 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1281 Tmp1 = Result.getValue(0);
1282 Tmp2 = Result.getValue(1);
1285 Tmp3 = TLI.LowerOperation(Result, DAG);
1286 if (Tmp3.getNode()) {
1287 Tmp1 = LegalizeOp(Tmp3);
1288 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1291 // If this is an unaligned load and the target doesn't support it,
1293 if (!TLI.allowsUnalignedMemoryAccesses()) {
1294 unsigned ABIAlignment = TLI.getTargetData()->
1295 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT(
1296 *DAG.getContext()));
1297 if (LD->getAlignment() < ABIAlignment){
1298 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
1300 Tmp1 = Result.getOperand(0);
1301 Tmp2 = Result.getOperand(1);
1302 Tmp1 = LegalizeOp(Tmp1);
1303 Tmp2 = LegalizeOp(Tmp2);
1308 case TargetLowering::Expand:
1309 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1310 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1311 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1312 LD->getSrcValueOffset(),
1313 LD->isVolatile(), LD->getAlignment());
1314 Result = DAG.getNode(ISD::FP_EXTEND, dl,
1315 Node->getValueType(0), Load);
1316 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1317 Tmp2 = LegalizeOp(Load.getValue(1));
1320 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1321 // Turn the unsupported load into an EXTLOAD followed by an explicit
1322 // zero/sign extend inreg.
1323 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1324 Tmp1, Tmp2, LD->getSrcValue(),
1325 LD->getSrcValueOffset(), SrcVT,
1326 LD->isVolatile(), LD->getAlignment());
1328 if (ExtType == ISD::SEXTLOAD)
1329 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1330 Result.getValueType(),
1331 Result, DAG.getValueType(SrcVT));
1333 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
1334 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1335 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1340 // Since loads produce two values, make sure to remember that we legalized
1342 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1343 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1344 return Op.getResNo() ? Tmp2 : Tmp1;
1348 StoreSDNode *ST = cast<StoreSDNode>(Node);
1349 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1350 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1351 int SVOffset = ST->getSrcValueOffset();
1352 unsigned Alignment = ST->getAlignment();
1353 bool isVolatile = ST->isVolatile();
1355 if (!ST->isTruncatingStore()) {
1356 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1357 Result = SDValue(OptStore, 0);
1362 Tmp3 = LegalizeOp(ST->getValue());
1363 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1366 MVT VT = Tmp3.getValueType();
1367 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1368 default: llvm_unreachable("This action is not supported yet!");
1369 case TargetLowering::Legal:
1370 // If this is an unaligned store and the target doesn't support it,
1372 if (!TLI.allowsUnalignedMemoryAccesses()) {
1373 unsigned ABIAlignment = TLI.getTargetData()->
1374 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT(
1375 *DAG.getContext()));
1376 if (ST->getAlignment() < ABIAlignment)
1377 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
1381 case TargetLowering::Custom:
1382 Tmp1 = TLI.LowerOperation(Result, DAG);
1383 if (Tmp1.getNode()) Result = Tmp1;
1385 case TargetLowering::Promote:
1386 assert(VT.isVector() && "Unknown legal promote case!");
1387 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
1388 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1389 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1390 ST->getSrcValue(), SVOffset, isVolatile,
1397 Tmp3 = LegalizeOp(ST->getValue());
1399 MVT StVT = ST->getMemoryVT();
1400 unsigned StWidth = StVT.getSizeInBits();
1402 if (StWidth != StVT.getStoreSizeInBits()) {
1403 // Promote to a byte-sized store with upper bits zero if not
1404 // storing an integral number of bytes. For example, promote
1405 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1406 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
1407 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1408 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1409 SVOffset, NVT, isVolatile, Alignment);
1410 } else if (StWidth & (StWidth - 1)) {
1411 // If not storing a power-of-2 number of bits, expand as two stores.
1412 assert(StVT.isExtended() && !StVT.isVector() &&
1413 "Unsupported truncstore!");
1414 unsigned RoundWidth = 1 << Log2_32(StWidth);
1415 assert(RoundWidth < StWidth);
1416 unsigned ExtraWidth = StWidth - RoundWidth;
1417 assert(ExtraWidth < RoundWidth);
1418 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1419 "Store size not an integral number of bytes!");
1420 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
1421 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
1423 unsigned IncrementSize;
1425 if (TLI.isLittleEndian()) {
1426 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1427 // Store the bottom RoundWidth bits.
1428 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1430 isVolatile, Alignment);
1432 // Store the remaining ExtraWidth bits.
1433 IncrementSize = RoundWidth / 8;
1434 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1435 DAG.getIntPtrConstant(IncrementSize));
1436 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1437 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1438 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1439 SVOffset + IncrementSize, ExtraVT, isVolatile,
1440 MinAlign(Alignment, IncrementSize));
1442 // Big endian - avoid unaligned stores.
1443 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1444 // Store the top RoundWidth bits.
1445 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1446 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1447 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1448 SVOffset, RoundVT, isVolatile, Alignment);
1450 // Store the remaining ExtraWidth bits.
1451 IncrementSize = RoundWidth / 8;
1452 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1453 DAG.getIntPtrConstant(IncrementSize));
1454 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1455 SVOffset + IncrementSize, ExtraVT, isVolatile,
1456 MinAlign(Alignment, IncrementSize));
1459 // The order of the stores doesn't matter.
1460 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1462 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1463 Tmp2 != ST->getBasePtr())
1464 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1467 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1468 default: llvm_unreachable("This action is not supported yet!");
1469 case TargetLowering::Legal:
1470 // If this is an unaligned store and the target doesn't support it,
1472 if (!TLI.allowsUnalignedMemoryAccesses()) {
1473 unsigned ABIAlignment = TLI.getTargetData()->
1474 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT(
1475 *DAG.getContext()));
1476 if (ST->getAlignment() < ABIAlignment)
1477 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
1481 case TargetLowering::Custom:
1482 Result = TLI.LowerOperation(Result, DAG);
1485 // TRUNCSTORE:i16 i32 -> STORE i16
1486 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
1487 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1488 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1489 SVOffset, isVolatile, Alignment);
1497 assert(Result.getValueType() == Op.getValueType() &&
1498 "Bad legalization!");
1500 // Make sure that the generated code is itself legal.
1502 Result = LegalizeOp(Result);
1504 // Note that LegalizeOp may be reentered even from single-use nodes, which
1505 // means that we always must cache transformed nodes.
1506 AddLegalizedOperand(Op, Result);
1510 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1511 SDValue Vec = Op.getOperand(0);
1512 SDValue Idx = Op.getOperand(1);
1513 DebugLoc dl = Op.getDebugLoc();
1514 // Store the value to a temporary stack slot, then LOAD the returned part.
1515 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1516 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
1518 // Add the offset to the index.
1520 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1521 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1522 DAG.getConstant(EltSize, Idx.getValueType()));
1524 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1525 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1527 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1529 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1531 if (Op.getValueType().isVector())
1532 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0);
1534 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1535 NULL, 0, Vec.getValueType().getVectorElementType());
1538 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1539 // We can't handle this case efficiently. Allocate a sufficiently
1540 // aligned object on the stack, store each element into it, then load
1541 // the result as a vector.
1542 // Create the stack frame object.
1543 MVT VT = Node->getValueType(0);
1544 MVT OpVT = Node->getOperand(0).getValueType();
1545 DebugLoc dl = Node->getDebugLoc();
1546 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1547 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1548 const Value *SV = PseudoSourceValue::getFixedStack(FI);
1550 // Emit a store of each element to the stack slot.
1551 SmallVector<SDValue, 8> Stores;
1552 unsigned TypeByteSize = OpVT.getSizeInBits() / 8;
1553 // Store (in the right endianness) the elements to memory.
1554 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1555 // Ignore undef elements.
1556 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1558 unsigned Offset = TypeByteSize*i;
1560 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1561 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1563 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
1568 if (!Stores.empty()) // Not all undef elements?
1569 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1570 &Stores[0], Stores.size());
1572 StoreChain = DAG.getEntryNode();
1574 // Result is a load from the stack slot.
1575 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0);
1578 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1579 DebugLoc dl = Node->getDebugLoc();
1580 SDValue Tmp1 = Node->getOperand(0);
1581 SDValue Tmp2 = Node->getOperand(1);
1582 assert((Tmp2.getValueType() == MVT::f32 ||
1583 Tmp2.getValueType() == MVT::f64) &&
1584 "Ugly special-cased code!");
1585 // Get the sign bit of the RHS.
1587 MVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32;
1588 if (isTypeLegal(IVT)) {
1589 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
1591 assert(isTypeLegal(TLI.getPointerTy()) &&
1592 (TLI.getPointerTy() == MVT::i32 ||
1593 TLI.getPointerTy() == MVT::i64) &&
1594 "Legal type for load?!");
1595 SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType());
1596 SDValue StorePtr = StackPtr, LoadPtr = StackPtr;
1598 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0);
1599 if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian())
1600 LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(),
1601 LoadPtr, DAG.getIntPtrConstant(4));
1602 SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(),
1603 Ch, LoadPtr, NULL, 0, MVT::i32);
1606 DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1607 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1609 // Get the absolute value of the result.
1610 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1611 // Select between the nabs and abs value based on the sign bit of
1613 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1614 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1618 SDValue SelectionDAGLegalize::ExpandDBG_STOPPOINT(SDNode* Node) {
1619 DebugLoc dl = Node->getDebugLoc();
1620 DwarfWriter *DW = DAG.getDwarfWriter();
1621 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
1623 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
1625 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1626 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
1627 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) {
1628 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit()));
1630 unsigned Line = DSP->getLine();
1631 unsigned Col = DSP->getColumn();
1633 if (OptLevel == CodeGenOpt::None) {
1634 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
1635 // won't hurt anything.
1637 return DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Node->getOperand(0),
1638 DAG.getConstant(Line, MVT::i32),
1639 DAG.getConstant(Col, MVT::i32),
1640 DAG.getSrcValue(CU.getGV()));
1642 unsigned ID = DW->RecordSourceLine(Line, Col, CU);
1643 return DAG.getLabel(ISD::DBG_LABEL, dl, Node->getOperand(0), ID);
1647 return Node->getOperand(0);
1650 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1651 SmallVectorImpl<SDValue> &Results) {
1652 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1653 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1654 " not tell us which reg is the stack pointer!");
1655 DebugLoc dl = Node->getDebugLoc();
1656 MVT VT = Node->getValueType(0);
1657 SDValue Tmp1 = SDValue(Node, 0);
1658 SDValue Tmp2 = SDValue(Node, 1);
1659 SDValue Tmp3 = Node->getOperand(2);
1660 SDValue Chain = Tmp1.getOperand(0);
1662 // Chain the dynamic stack allocation so that it doesn't modify the stack
1663 // pointer when other instructions are using the stack.
1664 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1666 SDValue Size = Tmp2.getOperand(1);
1667 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1668 Chain = SP.getValue(1);
1669 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1670 unsigned StackAlign =
1671 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1672 if (Align > StackAlign)
1673 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1674 DAG.getConstant(-(uint64_t)Align, VT));
1675 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1676 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1678 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1679 DAG.getIntPtrConstant(0, true), SDValue());
1681 Results.push_back(Tmp1);
1682 Results.push_back(Tmp2);
1685 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1686 /// condition code CC on the current target. This routine assumes LHS and rHS
1687 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
1688 /// illegal condition code into AND / OR of multiple SETCC values.
1689 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
1690 SDValue &LHS, SDValue &RHS,
1693 MVT OpVT = LHS.getValueType();
1694 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1695 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1696 default: llvm_unreachable("Unknown condition code action!");
1697 case TargetLowering::Legal:
1700 case TargetLowering::Expand: {
1701 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1704 default: llvm_unreachable("Don't know how to expand this condition!");
1705 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1706 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1707 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1708 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1709 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1710 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1711 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1712 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1713 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1714 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1715 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1716 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1717 // FIXME: Implement more expansions.
1720 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1721 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1722 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1730 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1731 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1732 /// a load from the stack slot to DestVT, extending it if needed.
1733 /// The resultant code need not be legal.
1734 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1738 // Create the stack frame object.
1740 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1741 getTypeForMVT(*DAG.getContext()));
1742 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1744 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1745 int SPFI = StackPtrFI->getIndex();
1746 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
1748 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1749 unsigned SlotSize = SlotVT.getSizeInBits();
1750 unsigned DestSize = DestVT.getSizeInBits();
1751 unsigned DestAlign =
1752 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForMVT(
1753 *DAG.getContext()));
1755 // Emit a store to the stack slot. Use a truncstore if the input value is
1756 // later than DestVT.
1759 if (SrcSize > SlotSize)
1760 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1761 SV, 0, SlotVT, false, SrcAlign);
1763 assert(SrcSize == SlotSize && "Invalid store");
1764 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1765 SV, 0, false, SrcAlign);
1768 // Result is a load from the stack slot.
1769 if (SlotSize == DestSize)
1770 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign);
1772 assert(SlotSize < DestSize && "Unknown extension!");
1773 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
1777 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1778 DebugLoc dl = Node->getDebugLoc();
1779 // Create a vector sized/aligned stack slot, store the value to element #0,
1780 // then load the whole vector back out.
1781 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1783 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1784 int SPFI = StackPtrFI->getIndex();
1786 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1788 PseudoSourceValue::getFixedStack(SPFI), 0,
1789 Node->getValueType(0).getVectorElementType());
1790 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1791 PseudoSourceValue::getFixedStack(SPFI), 0);
1795 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1796 /// support the operation, but do support the resultant vector type.
1797 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1798 LLVMContext *Context = DAG.getContext();
1799 unsigned NumElems = Node->getNumOperands();
1800 SDValue Value1, Value2;
1801 DebugLoc dl = Node->getDebugLoc();
1802 MVT VT = Node->getValueType(0);
1803 MVT OpVT = Node->getOperand(0).getValueType();
1804 MVT EltVT = VT.getVectorElementType();
1806 // If the only non-undef value is the low element, turn this into a
1807 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1808 bool isOnlyLowElement = true;
1809 bool MoreThanTwoValues = false;
1810 bool isConstant = true;
1811 for (unsigned i = 0; i < NumElems; ++i) {
1812 SDValue V = Node->getOperand(i);
1813 if (V.getOpcode() == ISD::UNDEF)
1816 isOnlyLowElement = false;
1817 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1820 if (!Value1.getNode()) {
1822 } else if (!Value2.getNode()) {
1825 } else if (V != Value1 && V != Value2) {
1826 MoreThanTwoValues = true;
1830 if (!Value1.getNode())
1831 return DAG.getUNDEF(VT);
1833 if (isOnlyLowElement)
1834 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1836 // If all elements are constants, create a load from the constant pool.
1838 std::vector<Constant*> CV;
1839 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1840 if (ConstantFPSDNode *V =
1841 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1842 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1843 } else if (ConstantSDNode *V =
1844 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1845 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1847 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1848 const Type *OpNTy = OpVT.getTypeForMVT(*DAG.getContext());
1849 CV.push_back(Context->getUndef(OpNTy));
1852 Constant *CP = Context->getConstantVector(CV);
1853 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1854 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1855 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1856 PseudoSourceValue::getConstantPool(), 0,
1860 if (!MoreThanTwoValues) {
1861 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1862 for (unsigned i = 0; i < NumElems; ++i) {
1863 SDValue V = Node->getOperand(i);
1864 if (V.getOpcode() == ISD::UNDEF)
1866 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1868 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1869 // Get the splatted value into the low element of a vector register.
1870 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1872 if (Value2.getNode())
1873 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1875 Vec2 = DAG.getUNDEF(VT);
1877 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1878 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1882 // Otherwise, we can't handle this case efficiently.
1883 return ExpandVectorBuildThroughStack(Node);
1886 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1887 // does not fit into a register, return the lo part and set the hi part to the
1888 // by-reg argument. If it does fit into a single register, return the result
1889 // and leave the Hi part unset.
1890 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1892 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
1893 // The input chain to this libcall is the entry node of the function.
1894 // Legalizing the call will automatically add the previous call to the
1896 SDValue InChain = DAG.getEntryNode();
1898 TargetLowering::ArgListTy Args;
1899 TargetLowering::ArgListEntry Entry;
1900 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1901 MVT ArgVT = Node->getOperand(i).getValueType();
1902 const Type *ArgTy = ArgVT.getTypeForMVT(*DAG.getContext());
1903 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1904 Entry.isSExt = isSigned;
1905 Entry.isZExt = !isSigned;
1906 Args.push_back(Entry);
1908 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1909 TLI.getPointerTy());
1911 // Splice the libcall in wherever FindInputOutputChains tells us to.
1912 const Type *RetTy = Node->getValueType(0).getTypeForMVT(*DAG.getContext());
1913 std::pair<SDValue, SDValue> CallInfo =
1914 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
1915 0, CallingConv::C, false, Callee, Args, DAG,
1916 Node->getDebugLoc());
1918 // Legalize the call sequence, starting with the chain. This will advance
1919 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
1920 // was added by LowerCallTo (guaranteeing proper serialization of calls).
1921 LegalizeOp(CallInfo.second);
1922 return CallInfo.first;
1925 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1926 RTLIB::Libcall Call_F32,
1927 RTLIB::Libcall Call_F64,
1928 RTLIB::Libcall Call_F80,
1929 RTLIB::Libcall Call_PPCF128) {
1931 switch (Node->getValueType(0).getSimpleVT()) {
1932 default: llvm_unreachable("Unexpected request for libcall!");
1933 case MVT::f32: LC = Call_F32; break;
1934 case MVT::f64: LC = Call_F64; break;
1935 case MVT::f80: LC = Call_F80; break;
1936 case MVT::ppcf128: LC = Call_PPCF128; break;
1938 return ExpandLibCall(LC, Node, false);
1941 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1942 RTLIB::Libcall Call_I16,
1943 RTLIB::Libcall Call_I32,
1944 RTLIB::Libcall Call_I64,
1945 RTLIB::Libcall Call_I128) {
1947 switch (Node->getValueType(0).getSimpleVT()) {
1948 default: llvm_unreachable("Unexpected request for libcall!");
1949 case MVT::i16: LC = Call_I16; break;
1950 case MVT::i32: LC = Call_I32; break;
1951 case MVT::i64: LC = Call_I64; break;
1952 case MVT::i128: LC = Call_I128; break;
1954 return ExpandLibCall(LC, Node, isSigned);
1957 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
1958 /// INT_TO_FP operation of the specified operand when the target requests that
1959 /// we expand it. At this point, we know that the result and operand types are
1960 /// legal for the target.
1961 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
1965 if (Op0.getValueType() == MVT::i32) {
1966 // simple 32-bit [signed|unsigned] integer to float/double expansion
1968 // Get the stack frame index of a 8 byte buffer.
1969 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
1971 // word offset constant for Hi/Lo address computation
1972 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
1973 // set up Hi and Lo (into buffer) address based on endian
1974 SDValue Hi = StackSlot;
1975 SDValue Lo = DAG.getNode(ISD::ADD, dl,
1976 TLI.getPointerTy(), StackSlot, WordOff);
1977 if (TLI.isLittleEndian())
1980 // if signed map to unsigned space
1983 // constant used to invert sign bit (signed to unsigned mapping)
1984 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
1985 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
1989 // store the lo of the constructed double - based on integer input
1990 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
1991 Op0Mapped, Lo, NULL, 0);
1992 // initial hi portion of constructed double
1993 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
1994 // store the hi of the constructed double - biased exponent
1995 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
1996 // load the constructed double
1997 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
1998 // FP constant to bias correct the final result
1999 SDValue Bias = DAG.getConstantFP(isSigned ?
2000 BitsToDouble(0x4330000080000000ULL) :
2001 BitsToDouble(0x4330000000000000ULL),
2003 // subtract the bias
2004 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2007 // handle final rounding
2008 if (DestVT == MVT::f64) {
2011 } else if (DestVT.bitsLT(MVT::f64)) {
2012 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2013 DAG.getIntPtrConstant(0));
2014 } else if (DestVT.bitsGT(MVT::f64)) {
2015 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2019 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2020 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2022 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2023 Op0, DAG.getConstant(0, Op0.getValueType()),
2025 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2026 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2027 SignSet, Four, Zero);
2029 // If the sign bit of the integer is set, the large number will be treated
2030 // as a negative number. To counteract this, the dynamic code adds an
2031 // offset depending on the data type.
2033 switch (Op0.getValueType().getSimpleVT()) {
2034 default: llvm_unreachable("Unsupported integer type!");
2035 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2036 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2037 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2038 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2040 if (TLI.isLittleEndian()) FF <<= 32;
2041 Constant *FudgeFactor = DAG.getContext()->getConstantInt(Type::Int64Ty, FF);
2043 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2044 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2045 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2046 Alignment = std::min(Alignment, 4u);
2048 if (DestVT == MVT::f32)
2049 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2050 PseudoSourceValue::getConstantPool(), 0,
2054 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2055 DAG.getEntryNode(), CPIdx,
2056 PseudoSourceValue::getConstantPool(), 0,
2057 MVT::f32, false, Alignment));
2060 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2063 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2064 /// *INT_TO_FP operation of the specified operand when the target requests that
2065 /// we promote it. At this point, we know that the result and operand types are
2066 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2067 /// operation that takes a larger input.
2068 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2072 // First step, figure out the appropriate *INT_TO_FP operation to use.
2073 MVT NewInTy = LegalOp.getValueType();
2075 unsigned OpToUse = 0;
2077 // Scan for the appropriate larger type to use.
2079 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
2080 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2082 // If the target supports SINT_TO_FP of this type, use it.
2083 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2084 OpToUse = ISD::SINT_TO_FP;
2087 if (isSigned) continue;
2089 // If the target supports UINT_TO_FP of this type, use it.
2090 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2091 OpToUse = ISD::UINT_TO_FP;
2095 // Otherwise, try a larger type.
2098 // Okay, we found the operation and type to use. Zero extend our input to the
2099 // desired type then run the operation on it.
2100 return DAG.getNode(OpToUse, dl, DestVT,
2101 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2102 dl, NewInTy, LegalOp));
2105 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2106 /// FP_TO_*INT operation of the specified operand when the target requests that
2107 /// we promote it. At this point, we know that the result and operand types are
2108 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2109 /// operation that returns a larger result.
2110 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2114 // First step, figure out the appropriate FP_TO*INT operation to use.
2115 MVT NewOutTy = DestVT;
2117 unsigned OpToUse = 0;
2119 // Scan for the appropriate larger type to use.
2121 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
2122 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2124 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2125 OpToUse = ISD::FP_TO_SINT;
2129 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2130 OpToUse = ISD::FP_TO_UINT;
2134 // Otherwise, try a larger type.
2138 // Okay, we found the operation and type to use.
2139 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2141 // Truncate the result of the extended FP_TO_*INT operation to the desired
2143 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2146 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2148 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2149 MVT VT = Op.getValueType();
2150 MVT SHVT = TLI.getShiftAmountTy();
2151 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2152 switch (VT.getSimpleVT()) {
2153 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2155 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2156 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2157 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2159 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2160 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2161 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2162 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2163 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2164 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2165 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2166 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2167 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2169 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2170 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2171 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2172 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2173 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2174 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2175 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2176 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2177 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2178 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2179 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2180 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2181 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2182 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2183 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2184 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2185 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2186 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2187 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2188 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2189 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2193 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2195 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2198 default: llvm_unreachable("Cannot expand this yet!");
2200 static const uint64_t mask[6] = {
2201 0x5555555555555555ULL, 0x3333333333333333ULL,
2202 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
2203 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
2205 MVT VT = Op.getValueType();
2206 MVT ShVT = TLI.getShiftAmountTy();
2207 unsigned len = VT.getSizeInBits();
2208 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2209 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
2210 unsigned EltSize = VT.isVector() ?
2211 VT.getVectorElementType().getSizeInBits() : len;
2212 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
2213 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2214 Op = DAG.getNode(ISD::ADD, dl, VT,
2215 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
2216 DAG.getNode(ISD::AND, dl, VT,
2217 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
2223 // for now, we do this:
2224 // x = x | (x >> 1);
2225 // x = x | (x >> 2);
2227 // x = x | (x >>16);
2228 // x = x | (x >>32); // for 64-bit input
2229 // return popcount(~x);
2231 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2232 MVT VT = Op.getValueType();
2233 MVT ShVT = TLI.getShiftAmountTy();
2234 unsigned len = VT.getSizeInBits();
2235 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2236 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2237 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2238 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2240 Op = DAG.getNOT(dl, Op, VT);
2241 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2244 // for now, we use: { return popcount(~x & (x - 1)); }
2245 // unless the target has ctlz but not ctpop, in which case we use:
2246 // { return 32 - nlz(~x & (x-1)); }
2247 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2248 MVT VT = Op.getValueType();
2249 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2250 DAG.getNOT(dl, Op, VT),
2251 DAG.getNode(ISD::SUB, dl, VT, Op,
2252 DAG.getConstant(1, VT)));
2253 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2254 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2255 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2256 return DAG.getNode(ISD::SUB, dl, VT,
2257 DAG.getConstant(VT.getSizeInBits(), VT),
2258 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2259 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2264 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2265 SmallVectorImpl<SDValue> &Results) {
2266 DebugLoc dl = Node->getDebugLoc();
2267 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2268 switch (Node->getOpcode()) {
2272 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2273 Results.push_back(Tmp1);
2276 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2278 case ISD::FRAMEADDR:
2279 case ISD::RETURNADDR:
2280 case ISD::FRAME_TO_ARGS_OFFSET:
2281 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2283 case ISD::FLT_ROUNDS_:
2284 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2286 case ISD::EH_RETURN:
2288 case ISD::DBG_LABEL:
2291 case ISD::MEMBARRIER:
2293 Results.push_back(Node->getOperand(0));
2295 case ISD::DBG_STOPPOINT:
2296 Results.push_back(ExpandDBG_STOPPOINT(Node));
2298 case ISD::DYNAMIC_STACKALLOC:
2299 ExpandDYNAMIC_STACKALLOC(Node, Results);
2301 case ISD::MERGE_VALUES:
2302 for (unsigned i = 0; i < Node->getNumValues(); i++)
2303 Results.push_back(Node->getOperand(i));
2306 MVT VT = Node->getValueType(0);
2308 Results.push_back(DAG.getConstant(0, VT));
2309 else if (VT.isFloatingPoint())
2310 Results.push_back(DAG.getConstantFP(0, VT));
2312 llvm_unreachable("Unknown value type!");
2316 // If this operation is not supported, lower it to 'abort()' call
2317 TargetLowering::ArgListTy Args;
2318 std::pair<SDValue, SDValue> CallResult =
2319 TLI.LowerCallTo(Node->getOperand(0), Type::VoidTy,
2320 false, false, false, false, 0, CallingConv::C, false,
2321 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2323 Results.push_back(CallResult.second);
2327 case ISD::BIT_CONVERT:
2328 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2329 Node->getValueType(0), dl);
2330 Results.push_back(Tmp1);
2332 case ISD::FP_EXTEND:
2333 Tmp1 = EmitStackConvert(Node->getOperand(0),
2334 Node->getOperand(0).getValueType(),
2335 Node->getValueType(0), dl);
2336 Results.push_back(Tmp1);
2338 case ISD::SIGN_EXTEND_INREG: {
2339 // NOTE: we could fall back on load/store here too for targets without
2340 // SAR. However, it is doubtful that any exist.
2341 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2342 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
2343 ExtraVT.getSizeInBits();
2344 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2345 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2346 Node->getOperand(0), ShiftCst);
2347 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2348 Results.push_back(Tmp1);
2351 case ISD::FP_ROUND_INREG: {
2352 // The only way we can lower this is to turn it into a TRUNCSTORE,
2353 // EXTLOAD pair, targetting a temporary location (a stack slot).
2355 // NOTE: there is a choice here between constantly creating new stack
2356 // slots and always reusing the same one. We currently always create
2357 // new ones, as reuse may inhibit scheduling.
2358 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2359 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2360 Node->getValueType(0), dl);
2361 Results.push_back(Tmp1);
2364 case ISD::SINT_TO_FP:
2365 case ISD::UINT_TO_FP:
2366 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2367 Node->getOperand(0), Node->getValueType(0), dl);
2368 Results.push_back(Tmp1);
2370 case ISD::FP_TO_UINT: {
2371 SDValue True, False;
2372 MVT VT = Node->getOperand(0).getValueType();
2373 MVT NVT = Node->getValueType(0);
2374 const uint64_t zero[] = {0, 0};
2375 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
2376 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2377 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2378 Tmp1 = DAG.getConstantFP(apf, VT);
2379 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2380 Node->getOperand(0),
2382 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2383 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2384 DAG.getNode(ISD::FSUB, dl, VT,
2385 Node->getOperand(0), Tmp1));
2386 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2387 DAG.getConstant(x, NVT));
2388 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2389 Results.push_back(Tmp1);
2393 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2394 MVT VT = Node->getValueType(0);
2395 Tmp1 = Node->getOperand(0);
2396 Tmp2 = Node->getOperand(1);
2397 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
2398 // Increment the pointer, VAList, to the next vaarg
2399 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2400 DAG.getConstant(TLI.getTargetData()->
2401 getTypeAllocSize(VT.getTypeForMVT(
2402 *DAG.getContext())),
2403 TLI.getPointerTy()));
2404 // Store the incremented VAList to the legalized pointer
2405 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
2406 // Load the actual argument out of the pointer VAList
2407 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0));
2408 Results.push_back(Results[0].getValue(1));
2412 // This defaults to loading a pointer from the input and storing it to the
2413 // output, returning the chain.
2414 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2415 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2416 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2417 Node->getOperand(2), VS, 0);
2418 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0);
2419 Results.push_back(Tmp1);
2422 case ISD::EXTRACT_VECTOR_ELT:
2423 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2424 // This must be an access of the only element. Return it.
2425 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
2426 Node->getOperand(0));
2428 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2429 Results.push_back(Tmp1);
2431 case ISD::EXTRACT_SUBVECTOR:
2432 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2434 case ISD::CONCAT_VECTORS: {
2435 Results.push_back(ExpandVectorBuildThroughStack(Node));
2438 case ISD::SCALAR_TO_VECTOR:
2439 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2441 case ISD::INSERT_VECTOR_ELT:
2442 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2443 Node->getOperand(1),
2444 Node->getOperand(2), dl));
2446 case ISD::VECTOR_SHUFFLE: {
2447 SmallVector<int, 8> Mask;
2448 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
2450 MVT VT = Node->getValueType(0);
2451 MVT EltVT = VT.getVectorElementType();
2452 unsigned NumElems = VT.getVectorNumElements();
2453 SmallVector<SDValue, 8> Ops;
2454 for (unsigned i = 0; i != NumElems; ++i) {
2456 Ops.push_back(DAG.getUNDEF(EltVT));
2459 unsigned Idx = Mask[i];
2461 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2462 Node->getOperand(0),
2463 DAG.getIntPtrConstant(Idx)));
2465 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2466 Node->getOperand(1),
2467 DAG.getIntPtrConstant(Idx - NumElems)));
2469 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2470 Results.push_back(Tmp1);
2473 case ISD::EXTRACT_ELEMENT: {
2474 MVT OpTy = Node->getOperand(0).getValueType();
2475 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2477 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2478 DAG.getConstant(OpTy.getSizeInBits()/2,
2479 TLI.getShiftAmountTy()));
2480 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2483 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2484 Node->getOperand(0));
2486 Results.push_back(Tmp1);
2489 case ISD::STACKSAVE:
2490 // Expand to CopyFromReg if the target set
2491 // StackPointerRegisterToSaveRestore.
2492 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2493 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2494 Node->getValueType(0)));
2495 Results.push_back(Results[0].getValue(1));
2497 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2498 Results.push_back(Node->getOperand(0));
2501 case ISD::STACKRESTORE:
2502 // Expand to CopyToReg if the target set
2503 // StackPointerRegisterToSaveRestore.
2504 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2505 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2506 Node->getOperand(1)));
2508 Results.push_back(Node->getOperand(0));
2511 case ISD::FCOPYSIGN:
2512 Results.push_back(ExpandFCOPYSIGN(Node));
2515 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2516 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2517 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
2518 Node->getOperand(0));
2519 Results.push_back(Tmp1);
2522 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2523 MVT VT = Node->getValueType(0);
2524 Tmp1 = Node->getOperand(0);
2525 Tmp2 = DAG.getConstantFP(0.0, VT);
2526 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2527 Tmp1, Tmp2, ISD::SETUGT);
2528 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
2529 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
2530 Results.push_back(Tmp1);
2534 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
2535 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
2538 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
2539 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
2542 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
2543 RTLIB::COS_F80, RTLIB::COS_PPCF128));
2546 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
2547 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
2550 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
2551 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
2554 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
2555 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
2558 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
2559 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
2562 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
2563 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
2566 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
2567 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
2570 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
2571 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
2574 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
2575 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
2578 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
2579 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
2581 case ISD::FNEARBYINT:
2582 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
2583 RTLIB::NEARBYINT_F64,
2584 RTLIB::NEARBYINT_F80,
2585 RTLIB::NEARBYINT_PPCF128));
2588 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
2589 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
2592 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
2593 RTLIB::POW_F80, RTLIB::POW_PPCF128));
2596 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
2597 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
2600 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
2601 RTLIB::REM_F80, RTLIB::REM_PPCF128));
2603 case ISD::ConstantFP: {
2604 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
2605 // Check to see if this FP immediate is already legal.
2606 bool isLegal = false;
2607 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
2608 E = TLI.legal_fpimm_end(); I != E; ++I) {
2609 if (CFP->isExactlyValue(*I)) {
2614 // If this is a legal constant, turn it into a TargetConstantFP node.
2616 Results.push_back(SDValue(Node, 0));
2618 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
2621 case ISD::EHSELECTION: {
2622 unsigned Reg = TLI.getExceptionSelectorRegister();
2623 assert(Reg && "Can't expand to unknown register!");
2624 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
2625 Node->getValueType(0)));
2626 Results.push_back(Results[0].getValue(1));
2629 case ISD::EXCEPTIONADDR: {
2630 unsigned Reg = TLI.getExceptionAddressRegister();
2631 assert(Reg && "Can't expand to unknown register!");
2632 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
2633 Node->getValueType(0)));
2634 Results.push_back(Results[0].getValue(1));
2638 MVT VT = Node->getValueType(0);
2639 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
2640 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
2641 "Don't know how to expand this subtraction!");
2642 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
2643 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
2644 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
2645 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
2650 MVT VT = Node->getValueType(0);
2651 SDVTList VTs = DAG.getVTList(VT, VT);
2652 bool isSigned = Node->getOpcode() == ISD::SREM;
2653 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
2654 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2655 Tmp2 = Node->getOperand(0);
2656 Tmp3 = Node->getOperand(1);
2657 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
2658 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
2659 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
2661 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
2662 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
2663 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
2664 } else if (isSigned) {
2665 Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SREM_I16, RTLIB::SREM_I32,
2666 RTLIB::SREM_I64, RTLIB::SREM_I128);
2668 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UREM_I16, RTLIB::UREM_I32,
2669 RTLIB::UREM_I64, RTLIB::UREM_I128);
2671 Results.push_back(Tmp1);
2676 bool isSigned = Node->getOpcode() == ISD::SDIV;
2677 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2678 MVT VT = Node->getValueType(0);
2679 SDVTList VTs = DAG.getVTList(VT, VT);
2680 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT))
2681 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
2682 Node->getOperand(1));
2684 Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SDIV_I16, RTLIB::SDIV_I32,
2685 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
2687 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UDIV_I16, RTLIB::UDIV_I32,
2688 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
2689 Results.push_back(Tmp1);
2694 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
2696 MVT VT = Node->getValueType(0);
2697 SDVTList VTs = DAG.getVTList(VT, VT);
2698 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
2699 "If this wasn't legal, it shouldn't have been created!");
2700 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
2701 Node->getOperand(1));
2702 Results.push_back(Tmp1.getValue(1));
2706 MVT VT = Node->getValueType(0);
2707 SDVTList VTs = DAG.getVTList(VT, VT);
2708 // See if multiply or divide can be lowered using two-result operations.
2709 // We just need the low half of the multiply; try both the signed
2710 // and unsigned forms. If the target supports both SMUL_LOHI and
2711 // UMUL_LOHI, form a preference by checking which forms of plain
2712 // MULH it supports.
2713 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
2714 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
2715 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
2716 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
2717 unsigned OpToUse = 0;
2718 if (HasSMUL_LOHI && !HasMULHS) {
2719 OpToUse = ISD::SMUL_LOHI;
2720 } else if (HasUMUL_LOHI && !HasMULHU) {
2721 OpToUse = ISD::UMUL_LOHI;
2722 } else if (HasSMUL_LOHI) {
2723 OpToUse = ISD::SMUL_LOHI;
2724 } else if (HasUMUL_LOHI) {
2725 OpToUse = ISD::UMUL_LOHI;
2728 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
2729 Node->getOperand(1)));
2732 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::MUL_I16, RTLIB::MUL_I32,
2733 RTLIB::MUL_I64, RTLIB::MUL_I128);
2734 Results.push_back(Tmp1);
2739 SDValue LHS = Node->getOperand(0);
2740 SDValue RHS = Node->getOperand(1);
2741 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2742 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2744 Results.push_back(Sum);
2745 MVT OType = Node->getValueType(1);
2747 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2749 // LHSSign -> LHS >= 0
2750 // RHSSign -> RHS >= 0
2751 // SumSign -> Sum >= 0
2754 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2756 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2758 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2759 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2760 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2761 Node->getOpcode() == ISD::SADDO ?
2762 ISD::SETEQ : ISD::SETNE);
2764 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2765 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2767 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2768 Results.push_back(Cmp);
2773 SDValue LHS = Node->getOperand(0);
2774 SDValue RHS = Node->getOperand(1);
2775 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
2776 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2778 Results.push_back(Sum);
2779 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
2780 Node->getOpcode () == ISD::UADDO ?
2781 ISD::SETULT : ISD::SETUGT));
2786 MVT VT = Node->getValueType(0);
2787 SDValue LHS = Node->getOperand(0);
2788 SDValue RHS = Node->getOperand(1);
2791 static unsigned Ops[2][3] =
2792 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
2793 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
2794 bool isSigned = Node->getOpcode() == ISD::SMULO;
2795 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
2796 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
2797 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
2798 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
2799 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
2801 TopHalf = BottomHalf.getValue(1);
2802 } else if (TLI.isTypeLegal(MVT::getIntegerVT(VT.getSizeInBits() * 2))) {
2803 MVT WideVT = MVT::getIntegerVT(VT.getSizeInBits() * 2);
2804 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
2805 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
2806 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
2807 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
2808 DAG.getIntPtrConstant(0));
2809 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
2810 DAG.getIntPtrConstant(1));
2812 // FIXME: We should be able to fall back to a libcall with an illegal
2813 // type in some cases cases.
2814 // Also, we can fall back to a division in some cases, but that's a big
2815 // performance hit in the general case.
2816 llvm_unreachable("Don't know how to expand this operation yet!");
2819 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy());
2820 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
2821 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
2824 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
2825 DAG.getConstant(0, VT), ISD::SETNE);
2827 Results.push_back(BottomHalf);
2828 Results.push_back(TopHalf);
2831 case ISD::BUILD_PAIR: {
2832 MVT PairTy = Node->getValueType(0);
2833 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
2834 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
2835 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
2836 DAG.getConstant(PairTy.getSizeInBits()/2,
2837 TLI.getShiftAmountTy()));
2838 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
2842 Tmp1 = Node->getOperand(0);
2843 Tmp2 = Node->getOperand(1);
2844 Tmp3 = Node->getOperand(2);
2845 if (Tmp1.getOpcode() == ISD::SETCC) {
2846 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
2848 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2850 Tmp1 = DAG.getSelectCC(dl, Tmp1,
2851 DAG.getConstant(0, Tmp1.getValueType()),
2852 Tmp2, Tmp3, ISD::SETNE);
2854 Results.push_back(Tmp1);
2857 SDValue Chain = Node->getOperand(0);
2858 SDValue Table = Node->getOperand(1);
2859 SDValue Index = Node->getOperand(2);
2861 MVT PTy = TLI.getPointerTy();
2862 MachineFunction &MF = DAG.getMachineFunction();
2863 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
2864 Index= DAG.getNode(ISD::MUL, dl, PTy,
2865 Index, DAG.getConstant(EntrySize, PTy));
2866 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2868 MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
2869 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
2870 PseudoSourceValue::getJumpTable(), 0, MemVT);
2872 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2873 // For PIC, the sequence is:
2874 // BRIND(load(Jumptable + index) + RelocBase)
2875 // RelocBase can be JumpTable, GOT or some sort of global base.
2876 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
2877 TLI.getPICJumpTableRelocBase(Table, DAG));
2879 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
2880 Results.push_back(Tmp1);
2884 // Expand brcond's setcc into its constituent parts and create a BR_CC
2886 Tmp1 = Node->getOperand(0);
2887 Tmp2 = Node->getOperand(1);
2888 if (Tmp2.getOpcode() == ISD::SETCC) {
2889 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
2890 Tmp1, Tmp2.getOperand(2),
2891 Tmp2.getOperand(0), Tmp2.getOperand(1),
2892 Node->getOperand(2));
2894 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
2895 DAG.getCondCode(ISD::SETNE), Tmp2,
2896 DAG.getConstant(0, Tmp2.getValueType()),
2897 Node->getOperand(2));
2899 Results.push_back(Tmp1);
2902 Tmp1 = Node->getOperand(0);
2903 Tmp2 = Node->getOperand(1);
2904 Tmp3 = Node->getOperand(2);
2905 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
2907 // If we expanded the SETCC into an AND/OR, return the new node
2908 if (Tmp2.getNode() == 0) {
2909 Results.push_back(Tmp1);
2913 // Otherwise, SETCC for the given comparison type must be completely
2914 // illegal; expand it into a SELECT_CC.
2915 MVT VT = Node->getValueType(0);
2916 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
2917 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
2918 Results.push_back(Tmp1);
2921 case ISD::SELECT_CC: {
2922 Tmp1 = Node->getOperand(0); // LHS
2923 Tmp2 = Node->getOperand(1); // RHS
2924 Tmp3 = Node->getOperand(2); // True
2925 Tmp4 = Node->getOperand(3); // False
2926 SDValue CC = Node->getOperand(4);
2928 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
2929 Tmp1, Tmp2, CC, dl);
2931 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
2932 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2933 CC = DAG.getCondCode(ISD::SETNE);
2934 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
2936 Results.push_back(Tmp1);
2940 Tmp1 = Node->getOperand(0); // Chain
2941 Tmp2 = Node->getOperand(2); // LHS
2942 Tmp3 = Node->getOperand(3); // RHS
2943 Tmp4 = Node->getOperand(1); // CC
2945 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
2946 Tmp2, Tmp3, Tmp4, dl);
2947 LastCALLSEQ_END = DAG.getEntryNode();
2949 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
2950 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2951 Tmp4 = DAG.getCondCode(ISD::SETNE);
2952 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
2953 Tmp3, Node->getOperand(4));
2954 Results.push_back(Tmp1);
2957 case ISD::GLOBAL_OFFSET_TABLE:
2958 case ISD::GlobalAddress:
2959 case ISD::GlobalTLSAddress:
2960 case ISD::ExternalSymbol:
2961 case ISD::ConstantPool:
2962 case ISD::JumpTable:
2963 case ISD::INTRINSIC_W_CHAIN:
2964 case ISD::INTRINSIC_WO_CHAIN:
2965 case ISD::INTRINSIC_VOID:
2966 // FIXME: Custom lowering for these operations shouldn't return null!
2967 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2968 Results.push_back(SDValue(Node, i));
2972 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
2973 SmallVectorImpl<SDValue> &Results) {
2974 MVT OVT = Node->getValueType(0);
2975 if (Node->getOpcode() == ISD::UINT_TO_FP ||
2976 Node->getOpcode() == ISD::SINT_TO_FP) {
2977 OVT = Node->getOperand(0).getValueType();
2979 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2980 DebugLoc dl = Node->getDebugLoc();
2981 SDValue Tmp1, Tmp2, Tmp3;
2982 switch (Node->getOpcode()) {
2986 // Zero extend the argument.
2987 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
2988 // Perform the larger operation.
2989 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
2990 if (Node->getOpcode() == ISD::CTTZ) {
2991 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2992 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
2993 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
2995 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
2996 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
2997 } else if (Node->getOpcode() == ISD::CTLZ) {
2998 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2999 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3000 DAG.getConstant(NVT.getSizeInBits() -
3001 OVT.getSizeInBits(), NVT));
3003 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3006 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3007 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
3008 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3009 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3010 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3011 Results.push_back(Tmp1);
3014 case ISD::FP_TO_UINT:
3015 case ISD::FP_TO_SINT:
3016 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3017 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3018 Results.push_back(Tmp1);
3020 case ISD::UINT_TO_FP:
3021 case ISD::SINT_TO_FP:
3022 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3023 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3024 Results.push_back(Tmp1);
3029 unsigned ExtOp, TruncOp;
3030 if (OVT.isVector()) {
3031 ExtOp = ISD::BIT_CONVERT;
3032 TruncOp = ISD::BIT_CONVERT;
3033 } else if (OVT.isInteger()) {
3034 ExtOp = ISD::ANY_EXTEND;
3035 TruncOp = ISD::TRUNCATE;
3037 llvm_report_error("Cannot promote logic operation");
3039 // Promote each of the values to the new type.
3040 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3041 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3042 // Perform the larger operation, then convert back
3043 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3044 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3048 unsigned ExtOp, TruncOp;
3049 if (Node->getValueType(0).isVector()) {
3050 ExtOp = ISD::BIT_CONVERT;
3051 TruncOp = ISD::BIT_CONVERT;
3052 } else if (Node->getValueType(0).isInteger()) {
3053 ExtOp = ISD::ANY_EXTEND;
3054 TruncOp = ISD::TRUNCATE;
3056 ExtOp = ISD::FP_EXTEND;
3057 TruncOp = ISD::FP_ROUND;
3059 Tmp1 = Node->getOperand(0);
3060 // Promote each of the values to the new type.
3061 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3062 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3063 // Perform the larger operation, then round down.
3064 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3065 if (TruncOp != ISD::FP_ROUND)
3066 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3068 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3069 DAG.getIntPtrConstant(0));
3070 Results.push_back(Tmp1);
3073 case ISD::VECTOR_SHUFFLE: {
3074 SmallVector<int, 8> Mask;
3075 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3077 // Cast the two input vectors.
3078 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
3079 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1));
3081 // Convert the shuffle mask to the right # elements.
3082 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3083 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1);
3084 Results.push_back(Tmp1);
3088 // First step, figure out the appropriate operation to use.
3089 // Allow SETCC to not be supported for all legal data types
3090 // Mostly this targets FP
3091 MVT NewInTy = Node->getOperand(0).getValueType();
3092 MVT OldVT = NewInTy; OldVT = OldVT;
3094 // Scan for the appropriate larger type to use.
3096 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
3098 assert(NewInTy.isInteger() == OldVT.isInteger() &&
3099 "Fell off of the edge of the integer world");
3100 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
3101 "Fell off of the edge of the floating point world");
3103 // If the target supports SETCC of this type, use it.
3104 if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy))
3107 if (NewInTy.isInteger())
3108 llvm_unreachable("Cannot promote Legal Integer SETCC yet");
3110 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1);
3111 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2);
3113 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3114 Tmp1, Tmp2, Node->getOperand(2)));
3120 // SelectionDAG::Legalize - This is the entry point for the file.
3122 void SelectionDAG::Legalize(bool TypesNeedLegalizing,
3123 CodeGenOpt::Level OptLevel) {
3124 /// run - This is the main entry point to this class.
3126 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG();