1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Support/MathExtras.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
27 //===----------------------------------------------------------------------===//
28 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
29 /// hacks on it until the target machine can handle it. This involves
30 /// eliminating value sizes the machine cannot handle (promoting small sizes to
31 /// large sizes or splitting up large values into small values) as well as
32 /// eliminating operations the machine cannot handle.
34 /// This code also does a small amount of optimization and recognition of idioms
35 /// as part of its processing. For example, if a target does not support a
36 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
37 /// will attempt merge setcc and brc instructions into brcc's.
40 class SelectionDAGLegalize {
44 /// LegalizeAction - This enum indicates what action we should take for each
45 /// value type the can occur in the program.
47 Legal, // The target natively supports this value type.
48 Promote, // This should be promoted to the next larger type.
49 Expand, // This integer type should be broken into smaller pieces.
52 /// ValueTypeActions - This is a bitvector that contains two bits for each
53 /// value type, where the two bits correspond to the LegalizeAction enum.
54 /// This can be queried with "getTypeAction(VT)".
55 unsigned long long ValueTypeActions;
57 /// NeedsAnotherIteration - This is set when we expand a large integer
58 /// operation into smaller integer operations, but the smaller operations are
59 /// not set. This occurs only rarely in practice, for targets that don't have
60 /// 32-bit or larger integer registers.
61 bool NeedsAnotherIteration;
63 /// LegalizedNodes - For nodes that are of legal width, and that have more
64 /// than one use, this map indicates what regularized operand to use. This
65 /// allows us to avoid legalizing the same thing more than once.
66 std::map<SDOperand, SDOperand> LegalizedNodes;
68 /// PromotedNodes - For nodes that are below legal width, and that have more
69 /// than one use, this map indicates what promoted value to use. This allows
70 /// us to avoid promoting the same thing more than once.
71 std::map<SDOperand, SDOperand> PromotedNodes;
73 /// ExpandedNodes - For nodes that need to be expanded, and which have more
74 /// than one use, this map indicates which which operands are the expanded
75 /// version of the input. This allows us to avoid expanding the same node
77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
79 void AddLegalizedOperand(SDOperand From, SDOperand To) {
80 LegalizedNodes.insert(std::make_pair(From, To));
81 // If someone requests legalization of the new node, return itself.
83 LegalizedNodes.insert(std::make_pair(To, To));
85 void AddPromotedOperand(SDOperand From, SDOperand To) {
86 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
87 assert(isNew && "Got into the map somehow?");
88 // If someone requests legalization of the new node, return itself.
89 LegalizedNodes.insert(std::make_pair(To, To));
94 SelectionDAGLegalize(SelectionDAG &DAG);
96 /// Run - While there is still lowering to do, perform a pass over the DAG.
97 /// Most regularization can be done in a single pass, but targets that require
98 /// large values to be split into registers multiple times (e.g. i64 -> 4x
99 /// i16) require iteration for these values (the first iteration will demote
100 /// to i32, the second will demote to i16).
103 NeedsAnotherIteration = false;
105 } while (NeedsAnotherIteration);
108 /// getTypeAction - Return how we should legalize values of this type, either
109 /// it is already legal or we need to expand it into multiple registers of
110 /// smaller integer type, or we need to promote it to a larger type.
111 LegalizeAction getTypeAction(MVT::ValueType VT) const {
112 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3);
115 /// isTypeLegal - Return true if this type is legal on this target.
117 bool isTypeLegal(MVT::ValueType VT) const {
118 return getTypeAction(VT) == Legal;
124 SDOperand LegalizeOp(SDOperand O);
125 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
126 SDOperand PromoteOp(SDOperand O);
128 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
130 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
133 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
134 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
136 MVT::ValueType DestVT);
137 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
139 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
142 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
143 SDOperand &Lo, SDOperand &Hi);
144 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
145 SDOperand &Lo, SDOperand &Hi);
146 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
147 SDOperand &Lo, SDOperand &Hi);
149 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain);
151 SDOperand getIntPtrConstant(uint64_t Val) {
152 return DAG.getConstant(Val, TLI.getPointerTy());
157 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
159 default: assert(0 && "Don't know how to scalarize this opcode!");
160 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
161 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
162 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
166 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
167 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
168 ValueTypeActions(TLI.getValueTypeActions()) {
169 assert(MVT::LAST_VALUETYPE <= 32 &&
170 "Too many value types for ValueTypeActions to hold!");
173 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
174 /// INT_TO_FP operation of the specified operand when the target requests that
175 /// we expand it. At this point, we know that the result and operand types are
176 /// legal for the target.
177 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
179 MVT::ValueType DestVT) {
180 if (Op0.getValueType() == MVT::i32) {
181 // simple 32-bit [signed|unsigned] integer to float/double expansion
183 // get the stack frame index of a 8 byte buffer
184 MachineFunction &MF = DAG.getMachineFunction();
185 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
186 // get address of 8 byte buffer
187 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
188 // word offset constant for Hi/Lo address computation
189 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
190 // set up Hi and Lo (into buffer) address based on endian
192 if (TLI.isLittleEndian()) {
193 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
197 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
199 // if signed map to unsigned space
202 // constant used to invert sign bit (signed to unsigned mapping)
203 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
204 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
208 // store the lo of the constructed double - based on integer input
209 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
210 Op0Mapped, Lo, DAG.getSrcValue(NULL));
211 // initial hi portion of constructed double
212 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
213 // store the hi of the constructed double - biased exponent
214 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
215 InitialHi, Hi, DAG.getSrcValue(NULL));
216 // load the constructed double
217 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
218 DAG.getSrcValue(NULL));
219 // FP constant to bias correct the final result
220 SDOperand Bias = DAG.getConstantFP(isSigned ?
221 BitsToDouble(0x4330000080000000ULL)
222 : BitsToDouble(0x4330000000000000ULL),
225 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
228 // handle final rounding
229 if (DestVT == MVT::f64) {
233 // if f32 then cast to f32
234 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
236 return LegalizeOp(Result);
238 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
239 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
241 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
242 DAG.getConstant(0, Op0.getValueType()),
244 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
245 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
246 SignSet, Four, Zero);
248 // If the sign bit of the integer is set, the large number will be treated
249 // as a negative number. To counteract this, the dynamic code adds an
250 // offset depending on the data type.
252 switch (Op0.getValueType()) {
253 default: assert(0 && "Unsupported integer type!");
254 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
255 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
256 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
257 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
259 if (TLI.isLittleEndian()) FF <<= 32;
260 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
262 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
263 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
264 SDOperand FudgeInReg;
265 if (DestVT == MVT::f32)
266 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
267 DAG.getSrcValue(NULL));
269 assert(DestVT == MVT::f64 && "Unexpected conversion");
270 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
271 DAG.getEntryNode(), CPIdx,
272 DAG.getSrcValue(NULL), MVT::f32));
275 return LegalizeOp(DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg));
278 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
279 /// *INT_TO_FP operation of the specified operand when the target requests that
280 /// we promote it. At this point, we know that the result and operand types are
281 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
282 /// operation that takes a larger input.
283 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
284 MVT::ValueType DestVT,
286 // First step, figure out the appropriate *INT_TO_FP operation to use.
287 MVT::ValueType NewInTy = LegalOp.getValueType();
289 unsigned OpToUse = 0;
291 // Scan for the appropriate larger type to use.
293 NewInTy = (MVT::ValueType)(NewInTy+1);
294 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
296 // If the target supports SINT_TO_FP of this type, use it.
297 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
299 case TargetLowering::Legal:
300 if (!TLI.isTypeLegal(NewInTy))
301 break; // Can't use this datatype.
303 case TargetLowering::Custom:
304 OpToUse = ISD::SINT_TO_FP;
308 if (isSigned) continue;
310 // If the target supports UINT_TO_FP of this type, use it.
311 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
313 case TargetLowering::Legal:
314 if (!TLI.isTypeLegal(NewInTy))
315 break; // Can't use this datatype.
317 case TargetLowering::Custom:
318 OpToUse = ISD::UINT_TO_FP;
323 // Otherwise, try a larger type.
326 // Okay, we found the operation and type to use. Zero extend our input to the
327 // desired type then run the operation on it.
328 SDOperand N = DAG.getNode(OpToUse, DestVT,
329 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
331 // Make sure to legalize any nodes we create here.
332 return LegalizeOp(N);
335 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
336 /// FP_TO_*INT operation of the specified operand when the target requests that
337 /// we promote it. At this point, we know that the result and operand types are
338 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
339 /// operation that returns a larger result.
340 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
341 MVT::ValueType DestVT,
343 // First step, figure out the appropriate FP_TO*INT operation to use.
344 MVT::ValueType NewOutTy = DestVT;
346 unsigned OpToUse = 0;
348 // Scan for the appropriate larger type to use.
350 NewOutTy = (MVT::ValueType)(NewOutTy+1);
351 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
353 // If the target supports FP_TO_SINT returning this type, use it.
354 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
356 case TargetLowering::Legal:
357 if (!TLI.isTypeLegal(NewOutTy))
358 break; // Can't use this datatype.
360 case TargetLowering::Custom:
361 OpToUse = ISD::FP_TO_SINT;
366 // If the target supports FP_TO_UINT of this type, use it.
367 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
369 case TargetLowering::Legal:
370 if (!TLI.isTypeLegal(NewOutTy))
371 break; // Can't use this datatype.
373 case TargetLowering::Custom:
374 OpToUse = ISD::FP_TO_UINT;
379 // Otherwise, try a larger type.
382 // Okay, we found the operation and type to use. Truncate the result of the
383 // extended FP_TO_*INT operation to the desired size.
384 SDOperand N = DAG.getNode(ISD::TRUNCATE, DestVT,
385 DAG.getNode(OpToUse, NewOutTy, LegalOp));
386 // Make sure to legalize any nodes we create here in the next pass.
387 return LegalizeOp(N);
390 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
391 /// not been visited yet and if all of its operands have already been visited.
392 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
393 std::map<SDNode*, unsigned> &Visited) {
394 if (++Visited[N] != N->getNumOperands())
395 return; // Haven't visited all operands yet
399 if (N->hasOneUse()) { // Tail recurse in common case.
400 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
404 // Now that we have N in, add anything that uses it if all of their operands
406 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
407 ComputeTopDownOrdering(*UI, Order, Visited);
411 void SelectionDAGLegalize::LegalizeDAG() {
412 // The legalize process is inherently a bottom-up recursive process (users
413 // legalize their uses before themselves). Given infinite stack space, we
414 // could just start legalizing on the root and traverse the whole graph. In
415 // practice however, this causes us to run out of stack space on large basic
416 // blocks. To avoid this problem, compute an ordering of the nodes where each
417 // node is only legalized after all of its operands are legalized.
418 std::map<SDNode*, unsigned> Visited;
419 std::vector<SDNode*> Order;
421 // Compute ordering from all of the leaves in the graphs, those (like the
422 // entry node) that have no operands.
423 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
424 E = DAG.allnodes_end(); I != E; ++I) {
425 if (I->getNumOperands() == 0) {
427 ComputeTopDownOrdering(I, Order, Visited);
431 assert(Order.size() == Visited.size() &&
433 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
434 "Error: DAG is cyclic!");
437 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
438 SDNode *N = Order[i];
439 switch (getTypeAction(N->getValueType(0))) {
440 default: assert(0 && "Bad type action!");
442 LegalizeOp(SDOperand(N, 0));
445 PromoteOp(SDOperand(N, 0));
449 ExpandOp(SDOperand(N, 0), X, Y);
455 // Finally, it's possible the root changed. Get the new root.
456 SDOperand OldRoot = DAG.getRoot();
457 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
458 DAG.setRoot(LegalizedNodes[OldRoot]);
460 ExpandedNodes.clear();
461 LegalizedNodes.clear();
462 PromotedNodes.clear();
464 // Remove dead nodes now.
465 DAG.RemoveDeadNodes(OldRoot.Val);
468 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
469 assert(isTypeLegal(Op.getValueType()) &&
470 "Caller should expand or promote operands that are not legal!");
471 SDNode *Node = Op.Val;
473 // If this operation defines any values that cannot be represented in a
474 // register on this target, make sure to expand or promote them.
475 if (Node->getNumValues() > 1) {
476 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
477 switch (getTypeAction(Node->getValueType(i))) {
478 case Legal: break; // Nothing to do.
481 ExpandOp(Op.getValue(i), T1, T2);
482 assert(LegalizedNodes.count(Op) &&
483 "Expansion didn't add legal operands!");
484 return LegalizedNodes[Op];
487 PromoteOp(Op.getValue(i));
488 assert(LegalizedNodes.count(Op) &&
489 "Expansion didn't add legal operands!");
490 return LegalizedNodes[Op];
494 // Note that LegalizeOp may be reentered even from single-use nodes, which
495 // means that we always must cache transformed nodes.
496 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
497 if (I != LegalizedNodes.end()) return I->second;
499 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
501 SDOperand Result = Op;
503 switch (Node->getOpcode()) {
505 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
506 // If this is a target node, legalize it by legalizing the operands then
507 // passing it through.
508 std::vector<SDOperand> Ops;
509 bool Changed = false;
510 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
511 Ops.push_back(LegalizeOp(Node->getOperand(i)));
512 Changed = Changed || Node->getOperand(i) != Ops.back();
515 if (Node->getNumValues() == 1)
516 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops);
518 std::vector<MVT::ValueType> VTs(Node->value_begin(),
520 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
523 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
524 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
525 return Result.getValue(Op.ResNo);
527 // Otherwise this is an unhandled builtin node. splat.
528 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
529 assert(0 && "Do not know how to legalize this operator!");
531 case ISD::EntryToken:
532 case ISD::FrameIndex:
533 case ISD::TargetFrameIndex:
535 case ISD::TargetConstant:
536 case ISD::TargetConstantPool:
537 case ISD::GlobalAddress:
538 case ISD::TargetGlobalAddress:
539 case ISD::ExternalSymbol:
540 case ISD::TargetExternalSymbol:
541 case ISD::ConstantPool: // Nothing to do.
542 case ISD::BasicBlock:
547 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
548 default: assert(0 && "This action is not supported yet!");
549 case TargetLowering::Custom: {
550 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
552 Result = LegalizeOp(Tmp);
555 } // FALLTHROUGH if the target doesn't want to lower this op after all.
556 case TargetLowering::Legal:
557 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!");
561 case ISD::AssertSext:
562 case ISD::AssertZext:
563 Tmp1 = LegalizeOp(Node->getOperand(0));
564 if (Tmp1 != Node->getOperand(0))
565 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
566 Node->getOperand(1));
568 case ISD::MERGE_VALUES:
569 return LegalizeOp(Node->getOperand(Op.ResNo));
570 case ISD::CopyFromReg:
571 Tmp1 = LegalizeOp(Node->getOperand(0));
572 Result = Op.getValue(0);
573 if (Node->getNumValues() == 2) {
574 if (Tmp1 != Node->getOperand(0))
575 Result = DAG.getCopyFromReg(Tmp1,
576 cast<RegisterSDNode>(Node->getOperand(1))->getReg(),
577 Node->getValueType(0));
579 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
580 if (Node->getNumOperands() == 3)
581 Tmp2 = LegalizeOp(Node->getOperand(2));
582 if (Tmp1 != Node->getOperand(0) ||
583 (Node->getNumOperands() == 3 && Tmp2 != Node->getOperand(2)))
584 Result = DAG.getCopyFromReg(Tmp1,
585 cast<RegisterSDNode>(Node->getOperand(1))->getReg(),
586 Node->getValueType(0), Tmp2);
587 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
589 // Since CopyFromReg produces two values, make sure to remember that we
590 // legalized both of them.
591 AddLegalizedOperand(Op.getValue(0), Result);
592 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
593 return Result.getValue(Op.ResNo);
595 MVT::ValueType VT = Op.getValueType();
596 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
597 default: assert(0 && "This action is not supported yet!");
598 case TargetLowering::Expand:
599 case TargetLowering::Promote:
600 if (MVT::isInteger(VT))
601 Result = DAG.getConstant(0, VT);
602 else if (MVT::isFloatingPoint(VT))
603 Result = DAG.getConstantFP(0, VT);
605 assert(0 && "Unknown value type!");
607 case TargetLowering::Legal:
614 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
615 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
617 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
618 case TargetLowering::Promote:
619 default: assert(0 && "This action is not supported yet!");
620 case TargetLowering::Expand: {
621 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
622 if (TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other) && DebugInfo) {
623 std::vector<SDOperand> Ops;
624 Ops.push_back(Tmp1); // chain
625 Ops.push_back(Node->getOperand(1)); // line #
626 Ops.push_back(Node->getOperand(2)); // col #
627 const std::string &fname =
628 cast<StringSDNode>(Node->getOperand(3))->getValue();
629 const std::string &dirname =
630 cast<StringSDNode>(Node->getOperand(4))->getValue();
631 unsigned srcfile = DebugInfo->getUniqueSourceID(fname, dirname);
632 Ops.push_back(DAG.getConstant(srcfile, MVT::i32)); // source file id
633 unsigned id = DebugInfo->getNextUniqueID();
634 Ops.push_back(DAG.getConstant(id, MVT::i32)); // label id
635 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
637 Result = Tmp1; // chain
639 Result = LegalizeOp(Result); // Relegalize new nodes.
642 case TargetLowering::Legal:
643 if (Tmp1 != Node->getOperand(0) ||
644 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
645 std::vector<SDOperand> Ops;
647 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
648 Ops.push_back(Node->getOperand(1)); // line # must be legal.
649 Ops.push_back(Node->getOperand(2)); // col # must be legal.
651 // Otherwise promote them.
652 Ops.push_back(PromoteOp(Node->getOperand(1)));
653 Ops.push_back(PromoteOp(Node->getOperand(2)));
655 Ops.push_back(Node->getOperand(3)); // filename must be legal.
656 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
657 Result = DAG.getNode(ISD::LOCATION, MVT::Other, Ops);
664 assert(Node->getNumOperands() == 5 && "Invalid DEBUG_LOC node!");
665 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
666 case TargetLowering::Promote:
667 case TargetLowering::Expand:
668 default: assert(0 && "This action is not supported yet!");
669 case TargetLowering::Legal: {
671 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
672 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
673 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
674 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
675 Tmp5 = LegalizeOp(Node->getOperand(4)); // Legalize the label id.
677 if (Tmp1 != Node->getOperand(0) ||
678 Tmp2 != Node->getOperand(1) ||
679 Tmp3 != Node->getOperand(2) ||
680 Tmp4 != Node->getOperand(3) ||
681 Tmp5 != Node->getOperand(4)) {
683 DAG.getNode(ISD::DEBUG_LOC,MVT::Other, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
691 // We know we don't need to expand constants here, constants only have one
692 // value and we check that it is fine above.
694 // FIXME: Maybe we should handle things like targets that don't support full
695 // 32-bit immediates?
697 case ISD::ConstantFP: {
698 // Spill FP immediates to the constant pool if the target cannot directly
699 // codegen them. Targets often have some immediate values that can be
700 // efficiently generated into an FP register without a load. We explicitly
701 // leave these constants as ConstantFP nodes for the target to deal with.
703 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
705 // Check to see if this FP immediate is already legal.
706 bool isLegal = false;
707 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
708 E = TLI.legal_fpimm_end(); I != E; ++I)
709 if (CFP->isExactlyValue(*I)) {
715 // Otherwise we need to spill the constant to memory.
718 // If a FP immediate is precise when represented as a float, we put it
719 // into the constant pool as a float, even if it's is statically typed
721 MVT::ValueType VT = CFP->getValueType(0);
722 bool isDouble = VT == MVT::f64;
723 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
724 Type::FloatTy, CFP->getValue());
725 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
726 // Only do this if the target has a native EXTLOAD instruction from
728 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
729 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
735 LegalizeOp(DAG.getConstantPool(LLVMC, TLI.getPointerTy()));
737 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
738 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
740 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
741 DAG.getSrcValue(NULL));
746 case ISD::ConstantVec: {
747 // We assume that vector constants are not legal, and will be immediately
748 // spilled to the constant pool.
750 // FIXME: revisit this when we have some kind of mechanism by which targets
751 // can decided legality of vector constants, of which there may be very
754 // Create a ConstantPacked, and put it in the constant pool.
755 std::vector<Constant*> CV;
756 MVT::ValueType VT = Node->getValueType(0);
757 for (unsigned I = 0, E = Node->getNumOperands(); I < E; ++I) {
758 SDOperand OpN = Node->getOperand(I);
759 const Type* OpNTy = MVT::getTypeForValueType(OpN.getValueType());
760 if (MVT::isFloatingPoint(VT))
761 CV.push_back(ConstantFP::get(OpNTy,
762 cast<ConstantFPSDNode>(OpN)->getValue()));
764 CV.push_back(ConstantUInt::get(OpNTy,
765 cast<ConstantSDNode>(OpN)->getValue()));
767 Constant *CP = ConstantPacked::get(CV);
768 SDOperand CPIdx = LegalizeOp(DAG.getConstantPool(CP, TLI.getPointerTy()));
769 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
772 case ISD::TokenFactor:
773 if (Node->getNumOperands() == 2) {
774 bool Changed = false;
775 SDOperand Op0 = LegalizeOp(Node->getOperand(0));
776 SDOperand Op1 = LegalizeOp(Node->getOperand(1));
777 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1))
778 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
780 std::vector<SDOperand> Ops;
781 bool Changed = false;
782 // Legalize the operands.
783 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
784 SDOperand Op = Node->getOperand(i);
785 Ops.push_back(LegalizeOp(Op));
786 Changed |= Ops[i] != Op;
789 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
793 case ISD::CALLSEQ_START:
794 case ISD::CALLSEQ_END:
795 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
796 // Do not try to legalize the target-specific arguments (#1+)
797 Tmp2 = Node->getOperand(0);
799 Node->setAdjCallChain(Tmp1);
801 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These
802 // nodes are treated specially and are mutated in place. This makes the dag
803 // legalization process more efficient and also makes libcall insertion
806 case ISD::DYNAMIC_STACKALLOC:
807 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
808 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
809 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
810 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
811 Tmp3 != Node->getOperand(2)) {
812 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
813 std::vector<SDOperand> Ops;
814 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
815 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
817 Result = Op.getValue(0);
819 // Since this op produces two values, make sure to remember that we
820 // legalized both of them.
821 AddLegalizedOperand(SDOperand(Node, 0), Result);
822 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
823 return Result.getValue(Op.ResNo);
827 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
828 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
830 bool Changed = false;
831 std::vector<SDOperand> Ops;
832 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
833 Ops.push_back(LegalizeOp(Node->getOperand(i)));
834 Changed |= Ops.back() != Node->getOperand(i);
837 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) {
838 std::vector<MVT::ValueType> RetTyVTs;
839 RetTyVTs.reserve(Node->getNumValues());
840 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
841 RetTyVTs.push_back(Node->getValueType(i));
842 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
843 Node->getOpcode() == ISD::TAILCALL), 0);
845 Result = Result.getValue(0);
847 // Since calls produce multiple values, make sure to remember that we
848 // legalized all of them.
849 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
850 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
851 return Result.getValue(Op.ResNo);
854 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
855 if (Tmp1 != Node->getOperand(0))
856 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1));
860 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
862 switch (getTypeAction(Node->getOperand(1).getValueType())) {
863 case Expand: assert(0 && "It's impossible to expand bools");
865 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
868 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
872 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
873 default: assert(0 && "This action is not supported yet!");
874 case TargetLowering::Expand:
875 // Expand brcond's setcc into its constituent parts and create a BR_CC
877 if (Tmp2.getOpcode() == ISD::SETCC) {
878 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
879 Tmp2.getOperand(0), Tmp2.getOperand(1),
880 Node->getOperand(2));
882 // Make sure the condition is either zero or one. It may have been
883 // promoted from something else.
884 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
886 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
887 DAG.getCondCode(ISD::SETNE), Tmp2,
888 DAG.getConstant(0, Tmp2.getValueType()),
889 Node->getOperand(2));
891 Result = LegalizeOp(Result); // Relegalize new nodes.
893 case TargetLowering::Custom: {
895 TLI.LowerOperation(DAG.getNode(ISD::BRCOND, Node->getValueType(0),
896 Tmp1, Tmp2, Node->getOperand(2)), DAG);
898 Result = LegalizeOp(Tmp);
901 // FALLTHROUGH if the target thinks it is legal.
903 case TargetLowering::Legal:
904 // Basic block destination (Op#2) is always legal.
905 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
906 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
907 Node->getOperand(2));
912 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
913 if (!isTypeLegal(Node->getOperand(2).getValueType())) {
914 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
915 Node->getOperand(2), // LHS
916 Node->getOperand(3), // RHS
917 Node->getOperand(1)));
918 // If we get a SETCC back from legalizing the SETCC node we just
919 // created, then use its LHS, RHS, and CC directly in creating a new
920 // node. Otherwise, select between the true and false value based on
921 // comparing the result of the legalized with zero.
922 if (Tmp2.getOpcode() == ISD::SETCC) {
923 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
924 Tmp2.getOperand(0), Tmp2.getOperand(1),
925 Node->getOperand(4));
927 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
928 DAG.getCondCode(ISD::SETNE),
929 Tmp2, DAG.getConstant(0, Tmp2.getValueType()),
930 Node->getOperand(4));
935 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
936 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
938 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
939 default: assert(0 && "Unexpected action for BR_CC!");
940 case TargetLowering::Custom: {
941 Tmp4 = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1),
942 Tmp2, Tmp3, Node->getOperand(4));
943 Tmp4 = TLI.LowerOperation(Tmp4, DAG);
945 Result = LegalizeOp(Tmp4);
948 } // FALLTHROUGH if the target doesn't want to lower this op after all.
949 case TargetLowering::Legal:
950 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
951 Tmp3 != Node->getOperand(3)) {
952 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1),
953 Tmp2, Tmp3, Node->getOperand(4));
958 case ISD::BRCONDTWOWAY:
959 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
960 switch (getTypeAction(Node->getOperand(1).getValueType())) {
961 case Expand: assert(0 && "It's impossible to expand bools");
963 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
966 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
969 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR
971 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) {
972 case TargetLowering::Promote:
973 default: assert(0 && "This action is not supported yet!");
974 case TargetLowering::Legal:
975 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
976 std::vector<SDOperand> Ops;
979 Ops.push_back(Node->getOperand(2));
980 Ops.push_back(Node->getOperand(3));
981 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops);
984 case TargetLowering::Expand:
985 // If BRTWOWAY_CC is legal for this target, then simply expand this node
986 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a
988 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
989 if (Tmp2.getOpcode() == ISD::SETCC) {
990 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
991 Tmp2.getOperand(0), Tmp2.getOperand(1),
992 Node->getOperand(2), Node->getOperand(3));
994 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
995 DAG.getConstant(0, Tmp2.getValueType()),
996 Node->getOperand(2), Node->getOperand(3));
999 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
1000 Node->getOperand(2));
1001 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3));
1003 Result = LegalizeOp(Result); // Relegalize new nodes.
1007 case ISD::BRTWOWAY_CC:
1008 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1009 if (isTypeLegal(Node->getOperand(2).getValueType())) {
1010 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
1011 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
1012 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
1013 Tmp3 != Node->getOperand(3)) {
1014 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3,
1015 Node->getOperand(4), Node->getOperand(5));
1019 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
1020 Node->getOperand(2), // LHS
1021 Node->getOperand(3), // RHS
1022 Node->getOperand(1)));
1023 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR
1025 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) {
1026 default: assert(0 && "This action is not supported yet!");
1027 case TargetLowering::Legal:
1028 // If we get a SETCC back from legalizing the SETCC node we just
1029 // created, then use its LHS, RHS, and CC directly in creating a new
1030 // node. Otherwise, select between the true and false value based on
1031 // comparing the result of the legalized with zero.
1032 if (Tmp2.getOpcode() == ISD::SETCC) {
1033 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
1034 Tmp2.getOperand(0), Tmp2.getOperand(1),
1035 Node->getOperand(4), Node->getOperand(5));
1037 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
1038 DAG.getConstant(0, Tmp2.getValueType()),
1039 Node->getOperand(4), Node->getOperand(5));
1042 case TargetLowering::Expand:
1043 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
1044 Node->getOperand(4));
1045 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5));
1048 Result = LegalizeOp(Result); // Relegalize new nodes.
1052 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1053 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1055 MVT::ValueType VT = Node->getValueType(0);
1056 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1057 default: assert(0 && "This action is not supported yet!");
1058 case TargetLowering::Custom: {
1059 SDOperand Op = DAG.getLoad(Node->getValueType(0),
1060 Tmp1, Tmp2, Node->getOperand(2));
1061 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
1063 Result = LegalizeOp(Tmp);
1064 // Since loads produce two values, make sure to remember that we legalized
1066 AddLegalizedOperand(SDOperand(Node, 0), Result);
1067 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1068 return Result.getValue(Op.ResNo);
1070 // FALLTHROUGH if the target thinks it is legal.
1072 case TargetLowering::Legal:
1073 if (Tmp1 != Node->getOperand(0) ||
1074 Tmp2 != Node->getOperand(1))
1075 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2,
1076 Node->getOperand(2));
1078 Result = SDOperand(Node, 0);
1080 // Since loads produce two values, make sure to remember that we legalized
1082 AddLegalizedOperand(SDOperand(Node, 0), Result);
1083 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1084 return Result.getValue(Op.ResNo);
1086 assert(0 && "Unreachable");
1090 case ISD::ZEXTLOAD: {
1091 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1092 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1094 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
1095 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
1096 default: assert(0 && "This action is not supported yet!");
1097 case TargetLowering::Promote:
1098 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
1099 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
1100 Tmp1, Tmp2, Node->getOperand(2), MVT::i8);
1101 // Since loads produce two values, make sure to remember that we legalized
1103 AddLegalizedOperand(SDOperand(Node, 0), Result);
1104 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1105 return Result.getValue(Op.ResNo);
1107 case TargetLowering::Custom: {
1108 SDOperand Op = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
1109 Tmp1, Tmp2, Node->getOperand(2),
1111 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
1113 Result = LegalizeOp(Tmp);
1114 // Since loads produce two values, make sure to remember that we legalized
1116 AddLegalizedOperand(SDOperand(Node, 0), Result);
1117 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1118 return Result.getValue(Op.ResNo);
1120 // FALLTHROUGH if the target thinks it is legal.
1122 case TargetLowering::Legal:
1123 if (Tmp1 != Node->getOperand(0) ||
1124 Tmp2 != Node->getOperand(1))
1125 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
1126 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1128 Result = SDOperand(Node, 0);
1130 // Since loads produce two values, make sure to remember that we legalized
1132 AddLegalizedOperand(SDOperand(Node, 0), Result);
1133 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1134 return Result.getValue(Op.ResNo);
1135 case TargetLowering::Expand:
1136 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1137 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1138 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
1139 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1140 Result = LegalizeOp(Result); // Relegalize new nodes.
1141 Load = LegalizeOp(Load);
1142 AddLegalizedOperand(SDOperand(Node, 0), Result);
1143 AddLegalizedOperand(SDOperand(Node, 1), Load.getValue(1));
1145 return Load.getValue(1);
1148 assert(Node->getOpcode() != ISD::EXTLOAD &&
1149 "EXTLOAD should always be supported!");
1150 // Turn the unsupported load into an EXTLOAD followed by an explicit
1151 // zero/sign extend inreg.
1152 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1153 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1155 if (Node->getOpcode() == ISD::SEXTLOAD)
1156 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1157 Result, DAG.getValueType(SrcVT));
1159 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1160 Result = LegalizeOp(Result); // Relegalize new nodes.
1161 ValRes = LegalizeOp(ValRes); // Relegalize new nodes.
1162 AddLegalizedOperand(SDOperand(Node, 0), ValRes);
1163 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1165 return Result.getValue(1);
1168 assert(0 && "Unreachable");
1170 case ISD::EXTRACT_ELEMENT: {
1171 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1172 switch (getTypeAction(OpTy)) {
1174 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1177 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1179 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1180 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1181 TLI.getShiftAmountTy()));
1182 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1185 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1186 Node->getOperand(0));
1188 Result = LegalizeOp(Result);
1191 // Get both the low and high parts.
1192 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1193 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1194 Result = Tmp2; // 1 -> Hi
1196 Result = Tmp1; // 0 -> Lo
1202 case ISD::CopyToReg:
1203 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1205 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1206 "Register type must be legal!");
1207 // Legalize the incoming value (must be a legal type).
1208 Tmp2 = LegalizeOp(Node->getOperand(2));
1209 if (Node->getNumValues() == 1) {
1210 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2))
1211 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1,
1212 Node->getOperand(1), Tmp2);
1214 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1215 if (Node->getNumOperands() == 4)
1216 Tmp3 = LegalizeOp(Node->getOperand(3));
1217 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
1218 (Node->getNumOperands() == 4 && Tmp3 != Node->getOperand(3))) {
1219 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1220 Result = DAG.getCopyToReg(Tmp1, Reg, Tmp2, Tmp3);
1223 // Since this produces two values, make sure to remember that we legalized
1225 AddLegalizedOperand(SDOperand(Node, 0), Result);
1226 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1227 return Result.getValue(Op.ResNo);
1232 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1233 switch (Node->getNumOperands()) {
1235 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1237 Tmp2 = LegalizeOp(Node->getOperand(1));
1238 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1239 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
1243 ExpandOp(Node->getOperand(1), Lo, Hi);
1244 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
1248 Tmp2 = PromoteOp(Node->getOperand(1));
1249 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
1254 if (Tmp1 != Node->getOperand(0))
1255 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1);
1257 default: { // ret <values>
1258 std::vector<SDOperand> NewValues;
1259 NewValues.push_back(Tmp1);
1260 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1261 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1263 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1267 ExpandOp(Node->getOperand(i), Lo, Hi);
1268 NewValues.push_back(Lo);
1269 NewValues.push_back(Hi);
1273 assert(0 && "Can't promote multiple return value yet!");
1275 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
1281 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1282 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1284 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1285 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1286 if (CFP->getValueType(0) == MVT::f32) {
1287 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
1288 DAG.getConstant(FloatToBits(CFP->getValue()),
1291 Node->getOperand(3));
1293 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1294 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
1295 DAG.getConstant(DoubleToBits(CFP->getValue()),
1298 Node->getOperand(3));
1303 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1305 SDOperand Val = LegalizeOp(Node->getOperand(1));
1306 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) ||
1307 Tmp2 != Node->getOperand(2))
1308 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2,
1309 Node->getOperand(3));
1311 MVT::ValueType VT = Result.Val->getOperand(1).getValueType();
1312 switch (TLI.getOperationAction(Result.Val->getOpcode(), VT)) {
1313 default: assert(0 && "This action is not supported yet!");
1314 case TargetLowering::Custom: {
1315 SDOperand Tmp = TLI.LowerOperation(Result, DAG);
1317 Result = LegalizeOp(Tmp);
1320 // FALLTHROUGH if the target thinks it is legal.
1322 case TargetLowering::Legal:
1329 // Truncate the value and store the result.
1330 Tmp3 = PromoteOp(Node->getOperand(1));
1331 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1332 Node->getOperand(3),
1333 DAG.getValueType(Node->getOperand(1).getValueType()));
1338 unsigned IncrementSize;
1339 ExpandOp(Node->getOperand(1), Lo, Hi);
1341 if (!TLI.isLittleEndian())
1344 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1345 Node->getOperand(3));
1346 // If this is a vector type, then we have to calculate the increment as
1347 // the product of the element size in bytes, and the number of elements
1348 // in the high half of the vector.
1349 if (MVT::Vector == Hi.getValueType()) {
1350 unsigned NumElems = cast<ConstantSDNode>(Hi.getOperand(2))->getValue();
1351 MVT::ValueType EVT = cast<VTSDNode>(Hi.getOperand(3))->getVT();
1352 IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8;
1354 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1356 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1357 getIntPtrConstant(IncrementSize));
1358 assert(isTypeLegal(Tmp2.getValueType()) &&
1359 "Pointers must be legal!");
1360 //Again, claiming both parts of the store came form the same Instr
1361 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1362 Node->getOperand(3));
1363 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1369 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1370 if (Tmp1 != Node->getOperand(0))
1371 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1));
1373 case ISD::READCYCLECOUNTER:
1374 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1375 if (Tmp1 != Node->getOperand(0)) {
1376 std::vector<MVT::ValueType> rtypes;
1377 std::vector<SDOperand> rvals;
1378 rtypes.push_back(MVT::i64);
1379 rtypes.push_back(MVT::Other);
1380 rvals.push_back(Tmp1);
1381 Result = DAG.getNode(ISD::READCYCLECOUNTER, rtypes, rvals);
1384 // Since rdcc produce two values, make sure to remember that we legalized
1386 AddLegalizedOperand(SDOperand(Node, 0), Result);
1387 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1388 return Result.getValue(Op.ResNo);
1390 case ISD::TRUNCSTORE: {
1391 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1392 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1394 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1397 assert(0 && "Cannot handle illegal TRUNCSTORE yet!");
1399 Tmp2 = LegalizeOp(Node->getOperand(1));
1401 // The only promote case we handle is TRUNCSTORE:i1 X into
1402 // -> TRUNCSTORE:i8 (and X, 1)
1403 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1404 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1405 TargetLowering::Promote) {
1406 // Promote the bool to a mask then store.
1407 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1408 DAG.getConstant(1, Tmp2.getValueType()));
1409 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1410 Node->getOperand(3), DAG.getValueType(MVT::i8));
1412 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1413 Tmp3 != Node->getOperand(2)) {
1414 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1415 Node->getOperand(3), Node->getOperand(4));
1418 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT();
1419 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) {
1420 default: assert(0 && "This action is not supported yet!");
1421 case TargetLowering::Custom: {
1422 SDOperand Tmp = TLI.LowerOperation(Result, DAG);
1424 Result = LegalizeOp(Tmp);
1427 // FALLTHROUGH if the target thinks it is legal.
1429 case TargetLowering::Legal:
1438 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1439 case Expand: assert(0 && "It's impossible to expand bools");
1441 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1444 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1447 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1448 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1450 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1451 default: assert(0 && "This action is not supported yet!");
1452 case TargetLowering::Expand:
1453 if (Tmp1.getOpcode() == ISD::SETCC) {
1454 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1456 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1458 // Make sure the condition is either zero or one. It may have been
1459 // promoted from something else.
1460 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1461 Result = DAG.getSelectCC(Tmp1,
1462 DAG.getConstant(0, Tmp1.getValueType()),
1463 Tmp2, Tmp3, ISD::SETNE);
1465 Result = LegalizeOp(Result); // Relegalize new nodes.
1467 case TargetLowering::Custom: {
1469 TLI.LowerOperation(DAG.getNode(ISD::SELECT, Node->getValueType(0),
1470 Tmp1, Tmp2, Tmp3), DAG);
1472 Result = LegalizeOp(Tmp);
1475 // FALLTHROUGH if the target thinks it is legal.
1477 case TargetLowering::Legal:
1478 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1479 Tmp3 != Node->getOperand(2))
1480 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0),
1483 case TargetLowering::Promote: {
1484 MVT::ValueType NVT =
1485 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1486 unsigned ExtOp, TruncOp;
1487 if (MVT::isInteger(Tmp2.getValueType())) {
1488 ExtOp = ISD::ANY_EXTEND;
1489 TruncOp = ISD::TRUNCATE;
1491 ExtOp = ISD::FP_EXTEND;
1492 TruncOp = ISD::FP_ROUND;
1494 // Promote each of the values to the new type.
1495 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1496 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1497 // Perform the larger operation, then round down.
1498 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1499 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1504 case ISD::SELECT_CC:
1505 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1506 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1508 if (isTypeLegal(Node->getOperand(0).getValueType())) {
1509 // Everything is legal, see if we should expand this op or something.
1510 switch (TLI.getOperationAction(ISD::SELECT_CC,
1511 Node->getOperand(0).getValueType())) {
1512 default: assert(0 && "This action is not supported yet!");
1513 case TargetLowering::Custom: {
1515 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0),
1516 Node->getOperand(0),
1517 Node->getOperand(1), Tmp3, Tmp4,
1518 Node->getOperand(4)), DAG);
1520 Result = LegalizeOp(Tmp);
1523 } // FALLTHROUGH if the target can't lower this operation after all.
1524 case TargetLowering::Legal:
1525 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1526 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1527 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1528 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) {
1529 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1,Tmp2,
1530 Tmp3, Tmp4, Node->getOperand(4));
1536 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
1537 Node->getOperand(0), // LHS
1538 Node->getOperand(1), // RHS
1539 Node->getOperand(4)));
1540 // If we get a SETCC back from legalizing the SETCC node we just
1541 // created, then use its LHS, RHS, and CC directly in creating a new
1542 // node. Otherwise, select between the true and false value based on
1543 // comparing the result of the legalized with zero.
1544 if (Tmp1.getOpcode() == ISD::SETCC) {
1545 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(),
1546 Tmp1.getOperand(0), Tmp1.getOperand(1),
1547 Tmp3, Tmp4, Tmp1.getOperand(2));
1549 Result = DAG.getSelectCC(Tmp1,
1550 DAG.getConstant(0, Tmp1.getValueType()),
1551 Tmp3, Tmp4, ISD::SETNE);
1556 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1558 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1559 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1562 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS
1563 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS
1565 // If this is an FP compare, the operands have already been extended.
1566 if (MVT::isInteger(Node->getOperand(0).getValueType())) {
1567 MVT::ValueType VT = Node->getOperand(0).getValueType();
1568 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
1570 // Otherwise, we have to insert explicit sign or zero extends. Note
1571 // that we could insert sign extends for ALL conditions, but zero extend
1572 // is cheaper on many machines (an AND instead of two shifts), so prefer
1574 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1575 default: assert(0 && "Unknown integer comparison!");
1582 // ALL of these operations will work if we either sign or zero extend
1583 // the operands (including the unsigned comparisons!). Zero extend is
1584 // usually a simpler/cheaper operation, so prefer it.
1585 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
1586 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
1592 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
1593 DAG.getValueType(VT));
1594 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
1595 DAG.getValueType(VT));
1601 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
1602 ExpandOp(Node->getOperand(0), LHSLo, LHSHi);
1603 ExpandOp(Node->getOperand(1), RHSLo, RHSHi);
1604 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1608 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
1609 if (RHSCST->isAllOnesValue()) {
1610 // Comparison to -1.
1611 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1616 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1617 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1618 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
1619 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1622 // If this is a comparison of the sign bit, just look at the top part.
1624 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
1625 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT &&
1626 CST->getValue() == 0) || // X < 0
1627 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT &&
1628 (CST->isAllOnesValue()))) { // X > -1
1634 // FIXME: This generated code sucks.
1635 ISD::CondCode LowCC;
1636 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1637 default: assert(0 && "Unknown integer setcc!");
1639 case ISD::SETULT: LowCC = ISD::SETULT; break;
1641 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1643 case ISD::SETULE: LowCC = ISD::SETULE; break;
1645 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1648 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1649 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1650 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1652 // NOTE: on targets without efficient SELECT of bools, we can always use
1653 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1654 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC);
1655 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi,
1656 Node->getOperand(2));
1657 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ);
1658 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1659 Result, Tmp1, Tmp2));
1660 AddLegalizedOperand(SDOperand(Node, 0), Result);
1665 switch(TLI.getOperationAction(ISD::SETCC,
1666 Node->getOperand(0).getValueType())) {
1668 assert(0 && "Cannot handle this action for SETCC yet!");
1670 case TargetLowering::Promote: {
1671 // First step, figure out the appropriate operation to use.
1672 // Allow SETCC to not be supported for all legal data types
1673 // Mostly this targets FP
1674 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1675 MVT::ValueType OldVT = NewInTy;
1677 // Scan for the appropriate larger type to use.
1679 NewInTy = (MVT::ValueType)(NewInTy+1);
1681 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1682 "Fell off of the edge of the integer world");
1683 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1684 "Fell off of the edge of the floating point world");
1686 // If the target supports SETCC of this type, use it.
1687 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
1690 if (MVT::isInteger(NewInTy))
1691 assert(0 && "Cannot promote Legal Integer SETCC yet");
1693 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1694 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
1697 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1698 Node->getOperand(2));
1701 case TargetLowering::Custom: {
1703 TLI.LowerOperation(DAG.getNode(ISD::SETCC, Node->getValueType(0),
1704 Tmp1, Tmp2, Node->getOperand(2)), DAG);
1706 Result = LegalizeOp(Tmp);
1709 // FALLTHROUGH if the target thinks it is legal.
1711 case TargetLowering::Legal:
1712 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1713 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1714 Node->getOperand(2));
1716 case TargetLowering::Expand:
1717 // Expand a setcc node into a select_cc of the same condition, lhs, and
1718 // rhs that selects between const 1 (true) and const 0 (false).
1719 MVT::ValueType VT = Node->getValueType(0);
1720 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1721 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1722 Node->getOperand(2));
1723 Result = LegalizeOp(Result);
1730 case ISD::MEMMOVE: {
1731 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1732 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1734 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1735 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1736 case Expand: assert(0 && "Cannot expand a byte!");
1738 Tmp3 = LegalizeOp(Node->getOperand(2));
1741 Tmp3 = PromoteOp(Node->getOperand(2));
1745 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1749 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1751 // Length is too big, just take the lo-part of the length.
1753 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
1757 Tmp4 = LegalizeOp(Node->getOperand(3));
1760 Tmp4 = PromoteOp(Node->getOperand(3));
1765 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
1766 case Expand: assert(0 && "Cannot expand this yet!");
1768 Tmp5 = LegalizeOp(Node->getOperand(4));
1771 Tmp5 = PromoteOp(Node->getOperand(4));
1775 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1776 default: assert(0 && "This action not implemented for this operation!");
1777 case TargetLowering::Custom: {
1779 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1,
1780 Tmp2, Tmp3, Tmp4, Tmp5), DAG);
1782 Result = LegalizeOp(Tmp);
1785 // FALLTHROUGH if the target thinks it is legal.
1787 case TargetLowering::Legal:
1788 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1789 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) ||
1790 Tmp5 != Node->getOperand(4)) {
1791 std::vector<SDOperand> Ops;
1792 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
1793 Ops.push_back(Tmp4); Ops.push_back(Tmp5);
1794 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops);
1797 case TargetLowering::Expand: {
1798 // Otherwise, the target does not support this operation. Lower the
1799 // operation to an explicit libcall as appropriate.
1800 MVT::ValueType IntPtr = TLI.getPointerTy();
1801 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType();
1802 std::vector<std::pair<SDOperand, const Type*> > Args;
1804 const char *FnName = 0;
1805 if (Node->getOpcode() == ISD::MEMSET) {
1806 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1807 // Extend the ubyte argument to be an int value for the call.
1808 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
1809 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
1810 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1813 } else if (Node->getOpcode() == ISD::MEMCPY ||
1814 Node->getOpcode() == ISD::MEMMOVE) {
1815 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1816 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
1817 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1818 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
1820 assert(0 && "Unknown op!");
1823 std::pair<SDOperand,SDOperand> CallResult =
1824 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
1825 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
1826 Result = LegalizeOp(CallResult.second);
1834 Tmp1 = LegalizeOp(Node->getOperand(0));
1835 Tmp2 = LegalizeOp(Node->getOperand(1));
1837 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1838 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1839 std::vector<SDOperand> Ops;
1840 Ops.push_back(Tmp1);
1841 Ops.push_back(Tmp2);
1842 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1844 Result = SDOperand(Node, 0);
1845 // Since these produce two values, make sure to remember that we legalized
1847 AddLegalizedOperand(SDOperand(Node, 0), Result);
1848 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1849 return Result.getValue(Op.ResNo);
1850 case ISD::WRITEPORT:
1851 Tmp1 = LegalizeOp(Node->getOperand(0));
1852 Tmp2 = LegalizeOp(Node->getOperand(1));
1853 Tmp3 = LegalizeOp(Node->getOperand(2));
1854 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1855 Tmp3 != Node->getOperand(2))
1856 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1860 Tmp1 = LegalizeOp(Node->getOperand(0));
1861 Tmp2 = LegalizeOp(Node->getOperand(1));
1863 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1864 case TargetLowering::Custom:
1865 default: assert(0 && "This action not implemented for this operation!");
1866 case TargetLowering::Legal:
1867 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1868 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1869 std::vector<SDOperand> Ops;
1870 Ops.push_back(Tmp1);
1871 Ops.push_back(Tmp2);
1872 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1874 Result = SDOperand(Node, 0);
1876 case TargetLowering::Expand:
1877 // Replace this with a load from memory.
1878 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0),
1879 Node->getOperand(1), DAG.getSrcValue(NULL));
1880 Result = LegalizeOp(Result);
1884 // Since these produce two values, make sure to remember that we legalized
1886 AddLegalizedOperand(SDOperand(Node, 0), Result);
1887 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1888 return Result.getValue(Op.ResNo);
1891 Tmp1 = LegalizeOp(Node->getOperand(0));
1892 Tmp2 = LegalizeOp(Node->getOperand(1));
1893 Tmp3 = LegalizeOp(Node->getOperand(2));
1895 switch (TLI.getOperationAction(Node->getOpcode(),
1896 Node->getOperand(1).getValueType())) {
1897 case TargetLowering::Custom:
1898 default: assert(0 && "This action not implemented for this operation!");
1899 case TargetLowering::Legal:
1900 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1901 Tmp3 != Node->getOperand(2))
1902 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1904 case TargetLowering::Expand:
1905 // Replace this with a store to memory.
1906 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0),
1907 Node->getOperand(1), Node->getOperand(2),
1908 DAG.getSrcValue(NULL));
1909 Result = LegalizeOp(Result);
1914 case ISD::ADD_PARTS:
1915 case ISD::SUB_PARTS:
1916 case ISD::SHL_PARTS:
1917 case ISD::SRA_PARTS:
1918 case ISD::SRL_PARTS: {
1919 std::vector<SDOperand> Ops;
1920 bool Changed = false;
1921 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1922 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1923 Changed |= Ops.back() != Node->getOperand(i);
1926 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1927 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
1930 // Since these produce multiple values, make sure to remember that we
1931 // legalized all of them.
1932 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1933 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
1934 return Result.getValue(Op.ResNo);
1955 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1956 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1957 case Expand: assert(0 && "Not possible");
1959 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
1962 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
1965 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1966 case TargetLowering::Custom: {
1967 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2);
1968 SDOperand Tmp = TLI.LowerOperation(Result, DAG);
1970 Tmp = LegalizeOp(Tmp); // Relegalize input.
1971 AddLegalizedOperand(Op, Tmp);
1973 } //else it was considered legal and we fall through
1975 case TargetLowering::Legal:
1976 if (Tmp1 != Node->getOperand(0) ||
1977 Tmp2 != Node->getOperand(1))
1978 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
1981 assert(0 && "Operation not supported");
1985 case ISD::BUILD_PAIR: {
1986 MVT::ValueType PairTy = Node->getValueType(0);
1987 // TODO: handle the case where the Lo and Hi operands are not of legal type
1988 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
1989 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
1990 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
1991 case TargetLowering::Legal:
1992 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1993 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
1995 case TargetLowering::Promote:
1996 case TargetLowering::Custom:
1997 assert(0 && "Cannot promote/custom this yet!");
1998 case TargetLowering::Expand:
1999 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2000 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2001 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2002 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2003 TLI.getShiftAmountTy()));
2004 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2));
2013 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2014 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2015 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2016 case TargetLowering::Custom: {
2017 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2);
2018 SDOperand Tmp = TLI.LowerOperation(Result, DAG);
2020 Tmp = LegalizeOp(Tmp); // Relegalize input.
2021 AddLegalizedOperand(Op, Tmp);
2023 } //else it was considered legal and we fall through
2025 case TargetLowering::Legal:
2026 if (Tmp1 != Node->getOperand(0) ||
2027 Tmp2 != Node->getOperand(1))
2028 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
2031 case TargetLowering::Promote:
2032 assert(0 && "Cannot promote handle this yet!");
2033 case TargetLowering::Expand:
2034 if (MVT::isInteger(Node->getValueType(0))) {
2035 MVT::ValueType VT = Node->getValueType(0);
2036 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2037 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
2038 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2039 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2041 // Floating point mod -> fmod libcall.
2042 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
2044 Result = ExpandLibCall(FnName, Node, Dummy);
2053 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2054 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2055 case TargetLowering::Legal:
2056 if (Tmp1 != Node->getOperand(0))
2057 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2059 case TargetLowering::Promote: {
2060 MVT::ValueType OVT = Tmp1.getValueType();
2061 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2063 // Zero extend the argument.
2064 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2065 // Perform the larger operation, then subtract if needed.
2066 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2067 switch(Node->getOpcode())
2073 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2074 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2075 DAG.getConstant(getSizeInBits(NVT), NVT),
2077 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2078 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2081 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2082 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2083 DAG.getConstant(getSizeInBits(NVT) -
2084 getSizeInBits(OVT), NVT));
2089 case TargetLowering::Custom:
2090 assert(0 && "Cannot custom handle this yet!");
2091 case TargetLowering::Expand:
2092 switch(Node->getOpcode())
2095 static const uint64_t mask[6] = {
2096 0x5555555555555555ULL, 0x3333333333333333ULL,
2097 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
2098 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
2100 MVT::ValueType VT = Tmp1.getValueType();
2101 MVT::ValueType ShVT = TLI.getShiftAmountTy();
2102 unsigned len = getSizeInBits(VT);
2103 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2104 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
2105 Tmp2 = DAG.getConstant(mask[i], VT);
2106 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2107 Tmp1 = DAG.getNode(ISD::ADD, VT,
2108 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2),
2109 DAG.getNode(ISD::AND, VT,
2110 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3),
2117 /* for now, we do this:
2122 x = x | (x >>32); // for 64-bit input
2123 return popcount(~x);
2125 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */
2126 MVT::ValueType VT = Tmp1.getValueType();
2127 MVT::ValueType ShVT = TLI.getShiftAmountTy();
2128 unsigned len = getSizeInBits(VT);
2129 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2130 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2131 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1,
2132 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3));
2134 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT));
2135 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
2139 // for now, we use: { return popcount(~x & (x - 1)); }
2140 // unless the target has ctlz but not ctpop, in which case we use:
2141 // { return 32 - nlz(~x & (x-1)); }
2142 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2143 MVT::ValueType VT = Tmp1.getValueType();
2144 Tmp2 = DAG.getConstant(~0ULL, VT);
2145 Tmp3 = DAG.getNode(ISD::AND, VT,
2146 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2),
2147 DAG.getNode(ISD::SUB, VT, Tmp1,
2148 DAG.getConstant(1, VT)));
2149 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead
2150 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
2151 TLI.isOperationLegal(ISD::CTLZ, VT)) {
2152 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT,
2153 DAG.getConstant(getSizeInBits(VT), VT),
2154 DAG.getNode(ISD::CTLZ, VT, Tmp3)));
2156 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
2161 assert(0 && "Cannot expand this yet!");
2174 Tmp1 = LegalizeOp(Node->getOperand(0));
2175 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2176 case TargetLowering::Legal:
2177 if (Tmp1 != Node->getOperand(0))
2178 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2180 case TargetLowering::Promote:
2181 case TargetLowering::Custom:
2182 assert(0 && "Cannot promote/custom handle this yet!");
2183 case TargetLowering::Expand:
2184 switch(Node->getOpcode()) {
2186 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2187 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2188 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0),
2193 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2194 MVT::ValueType VT = Node->getValueType(0);
2195 Tmp2 = DAG.getConstantFP(0.0, VT);
2196 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2197 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2198 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2199 Result = LegalizeOp(Result);
2205 MVT::ValueType VT = Node->getValueType(0);
2206 const char *FnName = 0;
2207 switch(Node->getOpcode()) {
2208 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2209 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2210 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2211 default: assert(0 && "Unreachable!");
2214 Result = ExpandLibCall(FnName, Node, Dummy);
2218 assert(0 && "Unreachable!");
2224 case ISD::BIT_CONVERT:
2225 if (!isTypeLegal(Node->getOperand(0).getValueType()))
2226 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2228 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2229 Node->getOperand(0).getValueType())) {
2230 default: assert(0 && "Unknown operation action!");
2231 case TargetLowering::Expand:
2232 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2234 case TargetLowering::Legal:
2235 Tmp1 = LegalizeOp(Node->getOperand(0));
2236 if (Tmp1 != Node->getOperand(0))
2237 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Tmp1);
2242 // Conversion operators. The source and destination have different types.
2243 case ISD::SINT_TO_FP:
2244 case ISD::UINT_TO_FP: {
2245 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2246 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2248 switch (TLI.getOperationAction(Node->getOpcode(),
2249 Node->getOperand(0).getValueType())) {
2250 default: assert(0 && "Unknown operation action!");
2251 case TargetLowering::Expand:
2252 Result = ExpandLegalINT_TO_FP(isSigned,
2253 LegalizeOp(Node->getOperand(0)),
2254 Node->getValueType(0));
2255 AddLegalizedOperand(Op, Result);
2257 case TargetLowering::Promote:
2258 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2259 Node->getValueType(0),
2261 AddLegalizedOperand(Op, Result);
2263 case TargetLowering::Legal:
2265 case TargetLowering::Custom: {
2266 Tmp1 = LegalizeOp(Node->getOperand(0));
2268 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2269 Tmp = TLI.LowerOperation(Tmp, DAG);
2271 Tmp = LegalizeOp(Tmp); // Relegalize input.
2272 AddLegalizedOperand(Op, Tmp);
2275 assert(0 && "Target Must Lower this");
2280 Tmp1 = LegalizeOp(Node->getOperand(0));
2281 if (Tmp1 != Node->getOperand(0))
2282 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2285 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2286 Node->getValueType(0), Node->getOperand(0));
2290 Result = PromoteOp(Node->getOperand(0));
2291 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2292 Result, DAG.getValueType(Node->getOperand(0).getValueType()));
2293 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result);
2295 Result = PromoteOp(Node->getOperand(0));
2296 Result = DAG.getZeroExtendInReg(Result,
2297 Node->getOperand(0).getValueType());
2298 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result);
2305 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2307 Tmp1 = LegalizeOp(Node->getOperand(0));
2308 if (Tmp1 != Node->getOperand(0))
2309 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2312 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2314 // Since the result is legal, we should just be able to truncate the low
2315 // part of the source.
2316 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2319 Result = PromoteOp(Node->getOperand(0));
2320 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2325 case ISD::FP_TO_SINT:
2326 case ISD::FP_TO_UINT:
2327 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2329 Tmp1 = LegalizeOp(Node->getOperand(0));
2331 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2332 default: assert(0 && "Unknown operation action!");
2333 case TargetLowering::Expand:
2334 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2335 SDOperand True, False;
2336 MVT::ValueType VT = Node->getOperand(0).getValueType();
2337 MVT::ValueType NVT = Node->getValueType(0);
2338 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2339 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2340 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2341 Node->getOperand(0), Tmp2, ISD::SETLT);
2342 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2343 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2344 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2346 False = DAG.getNode(ISD::XOR, NVT, False,
2347 DAG.getConstant(1ULL << ShiftAmt, NVT));
2348 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False));
2349 AddLegalizedOperand(SDOperand(Node, 0), Result);
2352 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2355 case TargetLowering::Promote:
2356 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2357 Node->getOpcode() == ISD::FP_TO_SINT);
2358 AddLegalizedOperand(Op, Result);
2360 case TargetLowering::Custom: {
2362 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2363 Tmp = TLI.LowerOperation(Tmp, DAG);
2365 Tmp = LegalizeOp(Tmp);
2366 AddLegalizedOperand(Op, Tmp);
2369 // The target thinks this is legal afterall.
2373 case TargetLowering::Legal:
2377 if (Tmp1 != Node->getOperand(0))
2378 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2381 assert(0 && "Shouldn't need to expand other operators here!");
2383 Result = PromoteOp(Node->getOperand(0));
2384 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2389 case ISD::ANY_EXTEND:
2390 case ISD::ZERO_EXTEND:
2391 case ISD::SIGN_EXTEND:
2392 case ISD::FP_EXTEND:
2394 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2396 Tmp1 = LegalizeOp(Node->getOperand(0));
2397 if (Tmp1 != Node->getOperand(0))
2398 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2401 assert(0 && "Shouldn't need to expand other operators here!");
2404 switch (Node->getOpcode()) {
2405 case ISD::ANY_EXTEND:
2406 Result = PromoteOp(Node->getOperand(0));
2407 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2409 case ISD::ZERO_EXTEND:
2410 Result = PromoteOp(Node->getOperand(0));
2411 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2412 Result = DAG.getZeroExtendInReg(Result,
2413 Node->getOperand(0).getValueType());
2415 case ISD::SIGN_EXTEND:
2416 Result = PromoteOp(Node->getOperand(0));
2417 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2418 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2420 DAG.getValueType(Node->getOperand(0).getValueType()));
2422 case ISD::FP_EXTEND:
2423 Result = PromoteOp(Node->getOperand(0));
2424 if (Result.getValueType() != Op.getValueType())
2425 // Dynamically dead while we have only 2 FP types.
2426 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2429 Result = PromoteOp(Node->getOperand(0));
2430 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2435 case ISD::FP_ROUND_INREG:
2436 case ISD::SIGN_EXTEND_INREG: {
2437 Tmp1 = LegalizeOp(Node->getOperand(0));
2438 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2440 // If this operation is not supported, convert it to a shl/shr or load/store
2442 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2443 default: assert(0 && "This action not supported for this op yet!");
2444 case TargetLowering::Legal:
2445 if (Tmp1 != Node->getOperand(0))
2446 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
2447 DAG.getValueType(ExtraVT));
2449 case TargetLowering::Expand:
2450 // If this is an integer extend and shifts are supported, do that.
2451 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2452 // NOTE: we could fall back on load/store here too for targets without
2453 // SAR. However, it is doubtful that any exist.
2454 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2455 MVT::getSizeInBits(ExtraVT);
2456 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2457 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2458 Node->getOperand(0), ShiftCst);
2459 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2461 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2462 // The only way we can lower this is to turn it into a STORETRUNC,
2463 // EXTLOAD pair, targetting a temporary location (a stack slot).
2465 // NOTE: there is a choice here between constantly creating new stack
2466 // slots and always reusing the same one. We currently always create
2467 // new ones, as reuse may inhibit scheduling.
2468 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2469 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
2470 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
2471 MachineFunction &MF = DAG.getMachineFunction();
2473 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2474 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2475 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2476 Node->getOperand(0), StackSlot,
2477 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2478 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2479 Result, StackSlot, DAG.getSrcValue(NULL),
2482 assert(0 && "Unknown op");
2484 Result = LegalizeOp(Result);
2491 // Note that LegalizeOp may be reentered even from single-use nodes, which
2492 // means that we always must cache transformed nodes.
2493 AddLegalizedOperand(Op, Result);
2497 /// PromoteOp - Given an operation that produces a value in an invalid type,
2498 /// promote it to compute the value into a larger type. The produced value will
2499 /// have the correct bits for the low portion of the register, but no guarantee
2500 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2501 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2502 MVT::ValueType VT = Op.getValueType();
2503 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2504 assert(getTypeAction(VT) == Promote &&
2505 "Caller should expand or legalize operands that are not promotable!");
2506 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2507 "Cannot promote to smaller type!");
2509 SDOperand Tmp1, Tmp2, Tmp3;
2512 SDNode *Node = Op.Val;
2514 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2515 if (I != PromotedNodes.end()) return I->second;
2517 // Promotion needs an optimization step to clean up after it, and is not
2518 // careful to avoid operations the target does not support. Make sure that
2519 // all generated operations are legalized in the next iteration.
2520 NeedsAnotherIteration = true;
2522 switch (Node->getOpcode()) {
2523 case ISD::CopyFromReg:
2524 assert(0 && "CopyFromReg must be legal!");
2526 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2527 assert(0 && "Do not know how to promote this operator!");
2530 Result = DAG.getNode(ISD::UNDEF, NVT);
2534 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2536 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2537 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2539 case ISD::ConstantFP:
2540 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2541 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2545 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2546 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2547 Node->getOperand(1), Node->getOperand(2));
2548 Result = LegalizeOp(Result);
2552 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2554 Result = LegalizeOp(Node->getOperand(0));
2555 assert(Result.getValueType() >= NVT &&
2556 "This truncation doesn't make sense!");
2557 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2558 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2561 // The truncation is not required, because we don't guarantee anything
2562 // about high bits anyway.
2563 Result = PromoteOp(Node->getOperand(0));
2566 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2567 // Truncate the low part of the expanded value to the result type
2568 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2571 case ISD::SIGN_EXTEND:
2572 case ISD::ZERO_EXTEND:
2573 case ISD::ANY_EXTEND:
2574 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2575 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2577 // Input is legal? Just do extend all the way to the larger type.
2578 Result = LegalizeOp(Node->getOperand(0));
2579 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2582 // Promote the reg if it's smaller.
2583 Result = PromoteOp(Node->getOperand(0));
2584 // The high bits are not guaranteed to be anything. Insert an extend.
2585 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2586 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2587 DAG.getValueType(Node->getOperand(0).getValueType()));
2588 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2589 Result = DAG.getZeroExtendInReg(Result,
2590 Node->getOperand(0).getValueType());
2594 case ISD::BIT_CONVERT:
2595 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2596 Result = PromoteOp(Result);
2599 case ISD::FP_EXTEND:
2600 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2602 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2603 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2604 case Promote: assert(0 && "Unreachable with 2 FP types!");
2606 // Input is legal? Do an FP_ROUND_INREG.
2607 Result = LegalizeOp(Node->getOperand(0));
2608 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2609 DAG.getValueType(VT));
2614 case ISD::SINT_TO_FP:
2615 case ISD::UINT_TO_FP:
2616 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2618 Result = LegalizeOp(Node->getOperand(0));
2619 // No extra round required here.
2620 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2624 Result = PromoteOp(Node->getOperand(0));
2625 if (Node->getOpcode() == ISD::SINT_TO_FP)
2626 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2628 DAG.getValueType(Node->getOperand(0).getValueType()));
2630 Result = DAG.getZeroExtendInReg(Result,
2631 Node->getOperand(0).getValueType());
2632 // No extra round required here.
2633 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2636 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
2637 Node->getOperand(0));
2638 // Round if we cannot tolerate excess precision.
2639 if (NoExcessFPPrecision)
2640 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2641 DAG.getValueType(VT));
2646 case ISD::SIGN_EXTEND_INREG:
2647 Result = PromoteOp(Node->getOperand(0));
2648 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2649 Node->getOperand(1));
2651 case ISD::FP_TO_SINT:
2652 case ISD::FP_TO_UINT:
2653 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2655 Tmp1 = LegalizeOp(Node->getOperand(0));
2658 // The input result is prerounded, so we don't have to do anything
2660 Tmp1 = PromoteOp(Node->getOperand(0));
2663 assert(0 && "not implemented");
2665 // If we're promoting a UINT to a larger size, check to see if the new node
2666 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
2667 // we can use that instead. This allows us to generate better code for
2668 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
2669 // legal, such as PowerPC.
2670 if (Node->getOpcode() == ISD::FP_TO_UINT &&
2671 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
2672 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
2673 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
2674 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
2676 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2682 Tmp1 = PromoteOp(Node->getOperand(0));
2683 assert(Tmp1.getValueType() == NVT);
2684 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2685 // NOTE: we do not have to do any extra rounding here for
2686 // NoExcessFPPrecision, because we know the input will have the appropriate
2687 // precision, and these operations don't modify precision at all.
2693 Tmp1 = PromoteOp(Node->getOperand(0));
2694 assert(Tmp1.getValueType() == NVT);
2695 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2696 if(NoExcessFPPrecision)
2697 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2698 DAG.getValueType(VT));
2707 // The input may have strange things in the top bits of the registers, but
2708 // these operations don't care. They may have weird bits going out, but
2709 // that too is okay if they are integer operations.
2710 Tmp1 = PromoteOp(Node->getOperand(0));
2711 Tmp2 = PromoteOp(Node->getOperand(1));
2712 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2713 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2718 // The input may have strange things in the top bits of the registers, but
2719 // these operations don't care.
2720 Tmp1 = PromoteOp(Node->getOperand(0));
2721 Tmp2 = PromoteOp(Node->getOperand(1));
2722 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2723 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2725 // Floating point operations will give excess precision that we may not be
2726 // able to tolerate. If we DO allow excess precision, just leave it,
2727 // otherwise excise it.
2728 // FIXME: Why would we need to round FP ops more than integer ones?
2729 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
2730 if (NoExcessFPPrecision)
2731 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2732 DAG.getValueType(VT));
2737 // These operators require that their input be sign extended.
2738 Tmp1 = PromoteOp(Node->getOperand(0));
2739 Tmp2 = PromoteOp(Node->getOperand(1));
2740 if (MVT::isInteger(NVT)) {
2741 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2742 DAG.getValueType(VT));
2743 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
2744 DAG.getValueType(VT));
2746 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2748 // Perform FP_ROUND: this is probably overly pessimistic.
2749 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
2750 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2751 DAG.getValueType(VT));
2755 // These operators require that their input be fp extended.
2756 Tmp1 = PromoteOp(Node->getOperand(0));
2757 Tmp2 = PromoteOp(Node->getOperand(1));
2758 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2760 // Perform FP_ROUND: this is probably overly pessimistic.
2761 if (NoExcessFPPrecision)
2762 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2763 DAG.getValueType(VT));
2768 // These operators require that their input be zero extended.
2769 Tmp1 = PromoteOp(Node->getOperand(0));
2770 Tmp2 = PromoteOp(Node->getOperand(1));
2771 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
2772 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2773 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
2774 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2778 Tmp1 = PromoteOp(Node->getOperand(0));
2779 Tmp2 = LegalizeOp(Node->getOperand(1));
2780 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2);
2783 // The input value must be properly sign extended.
2784 Tmp1 = PromoteOp(Node->getOperand(0));
2785 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2786 DAG.getValueType(VT));
2787 Tmp2 = LegalizeOp(Node->getOperand(1));
2788 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2);
2791 // The input value must be properly zero extended.
2792 Tmp1 = PromoteOp(Node->getOperand(0));
2793 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2794 Tmp2 = LegalizeOp(Node->getOperand(1));
2795 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2);
2798 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2799 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2800 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2,
2801 Node->getOperand(2), VT);
2802 // Remember that we legalized the chain.
2803 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2808 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2809 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2810 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2,
2811 Node->getOperand(2),
2812 cast<VTSDNode>(Node->getOperand(3))->getVT());
2813 // Remember that we legalized the chain.
2814 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2817 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2818 case Expand: assert(0 && "It's impossible to expand bools");
2820 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition.
2823 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2826 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
2827 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
2828 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3);
2830 case ISD::SELECT_CC:
2831 Tmp2 = PromoteOp(Node->getOperand(2)); // True
2832 Tmp3 = PromoteOp(Node->getOperand(3)); // False
2833 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
2834 Node->getOperand(1), Tmp2, Tmp3,
2835 Node->getOperand(4));
2839 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2840 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
2842 std::vector<SDOperand> Ops;
2843 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i)
2844 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2846 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
2847 "Can only promote single result calls");
2848 std::vector<MVT::ValueType> RetTyVTs;
2849 RetTyVTs.reserve(2);
2850 RetTyVTs.push_back(NVT);
2851 RetTyVTs.push_back(MVT::Other);
2852 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
2853 Node->getOpcode() == ISD::TAILCALL);
2854 Result = SDOperand(NC, 0);
2856 // Insert the new chain mapping.
2857 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2863 Tmp1 = Node->getOperand(0);
2864 //Zero extend the argument
2865 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2866 // Perform the larger operation, then subtract if needed.
2867 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2868 switch(Node->getOpcode())
2874 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2875 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2876 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
2877 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2878 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1);
2881 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2882 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2883 DAG.getConstant(getSizeInBits(NVT) -
2884 getSizeInBits(VT), NVT));
2890 assert(Result.Val && "Didn't set a result!");
2891 AddPromotedOperand(Op, Result);
2895 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
2896 /// The resultant code need not be legal. Note that SrcOp is the input operand
2897 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
2898 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
2900 // Create the stack frame object.
2901 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2902 unsigned ByteSize = MVT::getSizeInBits(DestVT)/8;
2903 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
2904 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
2906 // Emit a store to the stack slot.
2907 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
2908 SrcOp, FIPtr, DAG.getSrcValue(NULL));
2909 // Result is a load from the stack slot.
2910 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0));
2913 /// ExpandAddSub - Find a clever way to expand this add operation into
2915 void SelectionDAGLegalize::
2916 ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
2917 SDOperand &Lo, SDOperand &Hi) {
2918 // Expand the subcomponents.
2919 SDOperand LHSL, LHSH, RHSL, RHSH;
2920 ExpandOp(LHS, LHSL, LHSH);
2921 ExpandOp(RHS, RHSL, RHSH);
2923 std::vector<SDOperand> Ops;
2924 Ops.push_back(LHSL);
2925 Ops.push_back(LHSH);
2926 Ops.push_back(RHSL);
2927 Ops.push_back(RHSH);
2928 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
2929 Lo = DAG.getNode(NodeOp, VTs, Ops);
2930 Hi = Lo.getValue(1);
2933 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
2934 SDOperand Op, SDOperand Amt,
2935 SDOperand &Lo, SDOperand &Hi) {
2936 // Expand the subcomponents.
2937 SDOperand LHSL, LHSH;
2938 ExpandOp(Op, LHSL, LHSH);
2940 std::vector<SDOperand> Ops;
2941 Ops.push_back(LHSL);
2942 Ops.push_back(LHSH);
2944 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
2945 Lo = DAG.getNode(NodeOp, VTs, Ops);
2946 Hi = Lo.getValue(1);
2950 /// ExpandShift - Try to find a clever way to expand this shift operation out to
2951 /// smaller elements. If we can't find a way that is more efficient than a
2952 /// libcall on this target, return false. Otherwise, return true with the
2953 /// low-parts expanded into Lo and Hi.
2954 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
2955 SDOperand &Lo, SDOperand &Hi) {
2956 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
2957 "This is not a shift!");
2959 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
2960 SDOperand ShAmt = LegalizeOp(Amt);
2961 MVT::ValueType ShTy = ShAmt.getValueType();
2962 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
2963 unsigned NVTBits = MVT::getSizeInBits(NVT);
2965 // Handle the case when Amt is an immediate. Other cases are currently broken
2966 // and are disabled.
2967 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
2968 unsigned Cst = CN->getValue();
2969 // Expand the incoming operand to be shifted, so that we have its parts
2971 ExpandOp(Op, InL, InH);
2975 Lo = DAG.getConstant(0, NVT);
2976 Hi = DAG.getConstant(0, NVT);
2977 } else if (Cst > NVTBits) {
2978 Lo = DAG.getConstant(0, NVT);
2979 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
2980 } else if (Cst == NVTBits) {
2981 Lo = DAG.getConstant(0, NVT);
2984 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
2985 Hi = DAG.getNode(ISD::OR, NVT,
2986 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
2987 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
2992 Lo = DAG.getConstant(0, NVT);
2993 Hi = DAG.getConstant(0, NVT);
2994 } else if (Cst > NVTBits) {
2995 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
2996 Hi = DAG.getConstant(0, NVT);
2997 } else if (Cst == NVTBits) {
2999 Hi = DAG.getConstant(0, NVT);
3001 Lo = DAG.getNode(ISD::OR, NVT,
3002 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3003 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3004 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
3009 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
3010 DAG.getConstant(NVTBits-1, ShTy));
3011 } else if (Cst > NVTBits) {
3012 Lo = DAG.getNode(ISD::SRA, NVT, InH,
3013 DAG.getConstant(Cst-NVTBits, ShTy));
3014 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3015 DAG.getConstant(NVTBits-1, ShTy));
3016 } else if (Cst == NVTBits) {
3018 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3019 DAG.getConstant(NVTBits-1, ShTy));
3021 Lo = DAG.getNode(ISD::OR, NVT,
3022 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3023 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3024 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
3029 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy,
3030 // so disable it for now. Currently targets are handling this via SHL_PARTS
3034 // If we have an efficient select operation (or if the selects will all fold
3035 // away), lower to some complex code, otherwise just emit the libcall.
3036 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt))
3040 ExpandOp(Op, InL, InH);
3041 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt
3042 DAG.getConstant(NVTBits, ShTy), ShAmt);
3044 // Compare the unmasked shift amount against 32.
3045 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt,
3046 DAG.getConstant(NVTBits, ShTy), ISD::SETGE);
3048 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) {
3049 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31
3050 DAG.getConstant(NVTBits-1, ShTy));
3051 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31
3052 DAG.getConstant(NVTBits-1, ShTy));
3055 if (Opc == ISD::SHL) {
3056 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt)
3057 DAG.getNode(ISD::SHL, NVT, InH, ShAmt),
3058 DAG.getNode(ISD::SRL, NVT, InL, NAmt));
3059 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31
3061 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
3062 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2);
3064 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT,
3065 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt,
3066 DAG.getConstant(32, ShTy),
3068 DAG.getConstant(0, NVT),
3069 DAG.getNode(ISD::SHL, NVT, InH, NAmt));
3070 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt)
3072 DAG.getNode(ISD::SRL, NVT, InL, ShAmt));
3073 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31
3076 if (Opc == ISD::SRA)
3077 HiPart = DAG.getNode(ISD::SRA, NVT, InH,
3078 DAG.getConstant(NVTBits-1, ShTy));
3080 HiPart = DAG.getConstant(0, NVT);
3081 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
3082 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2);
3087 /// FindLatestCallSeqStart - Scan up the dag to find the latest (highest
3088 /// NodeDepth) node that is an CallSeqStart operation and occurs later than
3090 static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found) {
3091 if (Node->getNodeDepth() <= Found->getNodeDepth()) return;
3093 // If we found an CALLSEQ_START, we already know this node occurs later
3094 // than the Found node. Just remember this node and return.
3095 if (Node->getOpcode() == ISD::CALLSEQ_START) {
3100 // Otherwise, scan the operands of Node to see if any of them is a call.
3101 assert(Node->getNumOperands() != 0 &&
3102 "All leaves should have depth equal to the entry node!");
3103 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i)
3104 FindLatestCallSeqStart(Node->getOperand(i).Val, Found);
3106 // Tail recurse for the last iteration.
3107 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val,
3112 /// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest
3113 /// NodeDepth) node that is an CallSeqEnd operation and occurs more recent
3115 static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found,
3116 std::set<SDNode*> &Visited) {
3117 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) ||
3118 !Visited.insert(Node).second) return;
3120 // If we found an CALLSEQ_END, we already know this node occurs earlier
3121 // than the Found node. Just remember this node and return.
3122 if (Node->getOpcode() == ISD::CALLSEQ_END) {
3127 // Otherwise, scan the operands of Node to see if any of them is a call.
3128 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
3129 if (UI == E) return;
3130 for (--E; UI != E; ++UI)
3131 FindEarliestCallSeqEnd(*UI, Found, Visited);
3133 // Tail recurse for the last iteration.
3134 FindEarliestCallSeqEnd(*UI, Found, Visited);
3137 /// FindCallSeqEnd - Given a chained node that is part of a call sequence,
3138 /// find the CALLSEQ_END node that terminates the call sequence.
3139 static SDNode *FindCallSeqEnd(SDNode *Node) {
3140 if (Node->getOpcode() == ISD::CALLSEQ_END)
3142 if (Node->use_empty())
3143 return 0; // No CallSeqEnd
3145 SDOperand TheChain(Node, Node->getNumValues()-1);
3146 if (TheChain.getValueType() != MVT::Other)
3147 TheChain = SDOperand(Node, 0);
3148 if (TheChain.getValueType() != MVT::Other)
3151 for (SDNode::use_iterator UI = Node->use_begin(),
3152 E = Node->use_end(); UI != E; ++UI) {
3154 // Make sure to only follow users of our token chain.
3156 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
3157 if (User->getOperand(i) == TheChain)
3158 if (SDNode *Result = FindCallSeqEnd(User))
3164 /// FindCallSeqStart - Given a chained node that is part of a call sequence,
3165 /// find the CALLSEQ_START node that initiates the call sequence.
3166 static SDNode *FindCallSeqStart(SDNode *Node) {
3167 assert(Node && "Didn't find callseq_start for a call??");
3168 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
3170 assert(Node->getOperand(0).getValueType() == MVT::Other &&
3171 "Node doesn't have a token chain argument!");
3172 return FindCallSeqStart(Node->getOperand(0).Val);
3176 /// FindInputOutputChains - If we are replacing an operation with a call we need
3177 /// to find the call that occurs before and the call that occurs after it to
3178 /// properly serialize the calls in the block. The returned operand is the
3179 /// input chain value for the new call (e.g. the entry node or the previous
3180 /// call), and OutChain is set to be the chain node to update to point to the
3181 /// end of the call chain.
3182 static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain,
3184 SDNode *LatestCallSeqStart = Entry.Val;
3185 SDNode *LatestCallSeqEnd = 0;
3186 FindLatestCallSeqStart(OpNode, LatestCallSeqStart);
3187 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n";
3189 // It is possible that no ISD::CALLSEQ_START was found because there is no
3190 // previous call in the function. LatestCallStackDown may in that case be
3191 // the entry node itself. Do not attempt to find a matching CALLSEQ_END
3192 // unless LatestCallStackDown is an CALLSEQ_START.
3193 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) {
3194 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart);
3195 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n";
3197 LatestCallSeqEnd = Entry.Val;
3199 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd");
3201 // Finally, find the first call that this must come before, first we find the
3202 // CallSeqEnd that ends the call.
3204 std::set<SDNode*> Visited;
3205 FindEarliestCallSeqEnd(OpNode, OutChain, Visited);
3207 // If we found one, translate from the adj up to the callseq_start.
3209 OutChain = FindCallSeqStart(OutChain);
3211 return SDOperand(LatestCallSeqEnd, 0);
3214 /// SpliceCallInto - Given the result chain of a libcall (CallResult), and a
3215 void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult,
3217 // Nothing to splice it into?
3218 if (OutChain == 0) return;
3220 assert(OutChain->getOperand(0).getValueType() == MVT::Other);
3223 // Form a token factor node merging the old inval and the new inval.
3224 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult,
3225 OutChain->getOperand(0));
3226 // Change the node to refer to the new token.
3227 OutChain->setAdjCallChain(InToken);
3231 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
3232 // does not fit into a register, return the lo part and set the hi part to the
3233 // by-reg argument. If it does fit into a single register, return the result
3234 // and leave the Hi part unset.
3235 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3238 SDOperand InChain = FindInputOutputChains(Node, OutChain,
3239 DAG.getEntryNode());
3240 if (InChain.Val == 0)
3241 InChain = DAG.getEntryNode();
3243 TargetLowering::ArgListTy Args;
3244 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3245 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3246 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3247 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3249 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3251 // Splice the libcall in wherever FindInputOutputChains tells us to.
3252 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3253 std::pair<SDOperand,SDOperand> CallInfo =
3254 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3258 switch (getTypeAction(CallInfo.first.getValueType())) {
3259 default: assert(0 && "Unknown thing");
3261 Result = CallInfo.first;
3264 assert(0 && "Cannot promote this yet!");
3266 ExpandOp(CallInfo.first, Result, Hi);
3267 CallInfo.second = LegalizeOp(CallInfo.second);
3271 SpliceCallInto(CallInfo.second, OutChain);
3272 NeedsAnotherIteration = true;
3277 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3278 /// destination type is legal.
3279 SDOperand SelectionDAGLegalize::
3280 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3281 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3282 assert(getTypeAction(Source.getValueType()) == Expand &&
3283 "This is not an expansion!");
3284 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3287 assert(Source.getValueType() == MVT::i64 &&
3288 "This only works for 64-bit -> FP");
3289 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3290 // incoming integer is set. To handle this, we dynamically test to see if
3291 // it is set, and, if so, add a fudge factor.
3293 ExpandOp(Source, Lo, Hi);
3295 // If this is unsigned, and not supported, first perform the conversion to
3296 // signed, then adjust the result if the sign bit is set.
3297 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3298 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3300 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3301 DAG.getConstant(0, Hi.getValueType()),
3303 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3304 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3305 SignSet, Four, Zero);
3306 uint64_t FF = 0x5f800000ULL;
3307 if (TLI.isLittleEndian()) FF <<= 32;
3308 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3310 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3311 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3312 SDOperand FudgeInReg;
3313 if (DestTy == MVT::f32)
3314 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3315 DAG.getSrcValue(NULL));
3317 assert(DestTy == MVT::f64 && "Unexpected conversion");
3318 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3319 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
3321 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3324 // Check to see if the target has a custom way to lower this. If so, use it.
3325 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3326 default: assert(0 && "This action not implemented for this operation!");
3327 case TargetLowering::Legal:
3328 case TargetLowering::Expand:
3329 break; // This case is handled below.
3330 case TargetLowering::Custom: {
3331 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3334 return LegalizeOp(NV);
3335 break; // The target decided this was legal after all
3339 // Expand the source, then glue it back together for the call. We must expand
3340 // the source in case it is shared (this pass of legalize must traverse it).
3341 SDOperand SrcLo, SrcHi;
3342 ExpandOp(Source, SrcLo, SrcHi);
3343 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
3345 SDNode *OutChain = 0;
3346 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain,
3347 DAG.getEntryNode());
3348 const char *FnName = 0;
3349 if (DestTy == MVT::f32)
3350 FnName = "__floatdisf";
3352 assert(DestTy == MVT::f64 && "Unknown fp value type!");
3353 FnName = "__floatdidf";
3356 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy());
3358 TargetLowering::ArgListTy Args;
3359 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType());
3361 Args.push_back(std::make_pair(Source, ArgTy));
3363 // We don't care about token chains for libcalls. We just use the entry
3364 // node as our input and ignore the output chain. This allows us to place
3365 // calls wherever we need them to satisfy data dependences.
3366 const Type *RetTy = MVT::getTypeForValueType(DestTy);
3368 std::pair<SDOperand,SDOperand> CallResult =
3369 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true,
3372 SpliceCallInto(CallResult.second, OutChain);
3373 return CallResult.first;
3378 /// ExpandOp - Expand the specified SDOperand into its two component pieces
3379 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
3380 /// LegalizeNodes map is filled in for any results that are not expanded, the
3381 /// ExpandedNodes map is filled in for any results that are expanded, and the
3382 /// Lo/Hi values are returned.
3383 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
3384 MVT::ValueType VT = Op.getValueType();
3385 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3386 SDNode *Node = Op.Val;
3387 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
3388 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
3389 "Cannot expand FP values!");
3390 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
3391 "Cannot expand to FP value or to larger int value!");
3393 // See if we already expanded it.
3394 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
3395 = ExpandedNodes.find(Op);
3396 if (I != ExpandedNodes.end()) {
3397 Lo = I->second.first;
3398 Hi = I->second.second;
3402 // Expanding to multiple registers needs to perform an optimization step, and
3403 // is not careful to avoid operations the target does not support. Make sure
3404 // that all generated operations are legalized in the next iteration.
3405 NeedsAnotherIteration = true;
3407 switch (Node->getOpcode()) {
3408 case ISD::CopyFromReg:
3409 assert(0 && "CopyFromReg must be legal!");
3411 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
3412 assert(0 && "Do not know how to expand this operator!");
3415 Lo = DAG.getNode(ISD::UNDEF, NVT);
3416 Hi = DAG.getNode(ISD::UNDEF, NVT);
3418 case ISD::Constant: {
3419 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
3420 Lo = DAG.getConstant(Cst, NVT);
3421 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
3424 case ISD::ConstantVec: {
3425 unsigned NumElements = Node->getNumOperands();
3426 // If we only have two elements left in the constant vector, just break it
3427 // apart into the two scalar constants it contains. Otherwise, bisect the
3428 // ConstantVec, and return each half as a new ConstantVec.
3429 // FIXME: this is hard coded as big endian, it may have to change to support
3430 // SSE and Alpha MVI
3431 if (NumElements == 2) {
3432 Hi = Node->getOperand(0);
3433 Lo = Node->getOperand(1);
3436 std::vector<SDOperand> LoOps, HiOps;
3437 for (unsigned I = 0, E = NumElements; I < E; ++I) {
3438 HiOps.push_back(Node->getOperand(I));
3439 LoOps.push_back(Node->getOperand(I+NumElements));
3441 Lo = DAG.getNode(ISD::ConstantVec, MVT::Vector, LoOps);
3442 Hi = DAG.getNode(ISD::ConstantVec, MVT::Vector, HiOps);
3447 case ISD::BUILD_PAIR:
3448 // Legalize both operands. FIXME: in the future we should handle the case
3449 // where the two elements are not legal.
3450 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
3451 Lo = LegalizeOp(Node->getOperand(0));
3452 Hi = LegalizeOp(Node->getOperand(1));
3455 case ISD::SIGN_EXTEND_INREG:
3456 ExpandOp(Node->getOperand(0), Lo, Hi);
3457 // Sign extend the lo-part.
3458 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
3459 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
3460 TLI.getShiftAmountTy()));
3461 // sext_inreg the low part if needed.
3462 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
3466 ExpandOp(Node->getOperand(0), Lo, Hi);
3467 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
3468 DAG.getNode(ISD::CTPOP, NVT, Lo),
3469 DAG.getNode(ISD::CTPOP, NVT, Hi));
3470 Hi = DAG.getConstant(0, NVT);
3474 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
3475 ExpandOp(Node->getOperand(0), Lo, Hi);
3476 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3477 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
3478 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
3480 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
3481 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
3483 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
3484 Hi = DAG.getConstant(0, NVT);
3489 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
3490 ExpandOp(Node->getOperand(0), Lo, Hi);
3491 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3492 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
3493 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
3495 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
3496 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
3498 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
3499 Hi = DAG.getConstant(0, NVT);
3504 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3505 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3506 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3508 // Increment the pointer to the other half.
3509 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
3510 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3511 getIntPtrConstant(IncrementSize));
3512 //Is this safe? declaring that the two parts of the split load
3513 //are from the same instruction?
3514 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3516 // Build a factor node to remember that this load is independent of the
3518 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3521 // Remember that we legalized the chain.
3522 AddLegalizedOperand(Op.getValue(1), TF);
3523 if (!TLI.isLittleEndian())
3528 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3529 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3530 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue();
3531 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3533 // If we only have two elements, turn into a pair of scalar loads.
3534 // FIXME: handle case where a vector of two elements is fine, such as
3535 // 2 x double on SSE2.
3536 if (NumElements == 2) {
3537 Lo = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4));
3538 // Increment the pointer to the other half.
3539 unsigned IncrementSize = MVT::getSizeInBits(EVT)/8;
3540 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3541 getIntPtrConstant(IncrementSize));
3542 //Is this safe? declaring that the two parts of the split load
3543 //are from the same instruction?
3544 Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4));
3546 NumElements /= 2; // Split the vector in half
3547 Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4));
3548 unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8;
3549 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3550 getIntPtrConstant(IncrementSize));
3551 //Is this safe? declaring that the two parts of the split load
3552 //are from the same instruction?
3553 Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4));
3556 // Build a factor node to remember that this load is independent of the
3558 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3561 // Remember that we legalized the chain.
3562 AddLegalizedOperand(Op.getValue(1), TF);
3563 if (!TLI.isLittleEndian())
3570 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue();
3571 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3572 SDOperand LL, LH, RL, RH;
3574 ExpandOp(Node->getOperand(0), LL, LH);
3575 ExpandOp(Node->getOperand(1), RL, RH);
3577 // If we only have two elements, turn into a pair of scalar loads.
3578 // FIXME: handle case where a vector of two elements is fine, such as
3579 // 2 x double on SSE2.
3580 if (NumElements == 2) {
3581 unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT);
3582 Lo = DAG.getNode(Opc, EVT, LL, RL);
3583 Hi = DAG.getNode(Opc, EVT, LH, RH);
3585 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, LL.getOperand(2),
3587 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, LH.getOperand(2),
3594 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3595 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
3597 bool Changed = false;
3598 std::vector<SDOperand> Ops;
3599 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
3600 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3601 Changed |= Ops.back() != Node->getOperand(i);
3604 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
3605 "Can only expand a call once so far, not i64 -> i16!");
3607 std::vector<MVT::ValueType> RetTyVTs;
3608 RetTyVTs.reserve(3);
3609 RetTyVTs.push_back(NVT);
3610 RetTyVTs.push_back(NVT);
3611 RetTyVTs.push_back(MVT::Other);
3612 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops,
3613 Node->getOpcode() == ISD::TAILCALL);
3614 Lo = SDOperand(NC, 0);
3615 Hi = SDOperand(NC, 1);
3617 // Insert the new chain mapping.
3618 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2));
3623 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
3624 SDOperand LL, LH, RL, RH;
3625 ExpandOp(Node->getOperand(0), LL, LH);
3626 ExpandOp(Node->getOperand(1), RL, RH);
3627 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
3628 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
3632 SDOperand C, LL, LH, RL, RH;
3634 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3635 case Expand: assert(0 && "It's impossible to expand bools");
3637 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
3640 C = PromoteOp(Node->getOperand(0)); // Promote the condition.
3643 ExpandOp(Node->getOperand(1), LL, LH);
3644 ExpandOp(Node->getOperand(2), RL, RH);
3645 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL);
3646 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH);
3649 case ISD::SELECT_CC: {
3650 SDOperand TL, TH, FL, FH;
3651 ExpandOp(Node->getOperand(2), TL, TH);
3652 ExpandOp(Node->getOperand(3), FL, FH);
3653 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3654 Node->getOperand(1), TL, FL, Node->getOperand(4));
3655 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3656 Node->getOperand(1), TH, FH, Node->getOperand(4));
3657 Lo = LegalizeOp(Lo);
3658 Hi = LegalizeOp(Hi);
3661 case ISD::SEXTLOAD: {
3662 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3663 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3664 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3667 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3669 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3672 // Remember that we legalized the chain.
3673 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3675 // The high part is obtained by SRA'ing all but one of the bits of the lo
3677 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3678 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3679 TLI.getShiftAmountTy()));
3680 Lo = LegalizeOp(Lo);
3681 Hi = LegalizeOp(Hi);
3684 case ISD::ZEXTLOAD: {
3685 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3686 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3687 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3690 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3692 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3695 // Remember that we legalized the chain.
3696 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3698 // The high part is just a zero.
3699 Hi = LegalizeOp(DAG.getConstant(0, NVT));
3700 Lo = LegalizeOp(Lo);
3703 case ISD::EXTLOAD: {
3704 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3705 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3706 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3709 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3711 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3714 // Remember that we legalized the chain.
3715 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3717 // The high part is undefined.
3718 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT));
3719 Lo = LegalizeOp(Lo);
3722 case ISD::ANY_EXTEND: {
3724 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3725 case Expand: assert(0 && "expand-expand not implemented yet!");
3726 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3728 In = PromoteOp(Node->getOperand(0));
3732 // The low part is any extension of the input (which degenerates to a copy).
3733 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In);
3734 // The high part is undefined.
3735 Hi = DAG.getNode(ISD::UNDEF, NVT);
3738 case ISD::SIGN_EXTEND: {
3740 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3741 case Expand: assert(0 && "expand-expand not implemented yet!");
3742 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3744 In = PromoteOp(Node->getOperand(0));
3745 // Emit the appropriate sign_extend_inreg to get the value we want.
3746 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In,
3747 DAG.getValueType(Node->getOperand(0).getValueType()));
3751 // The low part is just a sign extension of the input (which degenerates to
3753 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In);
3755 // The high part is obtained by SRA'ing all but one of the bits of the lo
3757 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3758 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3759 TLI.getShiftAmountTy()));
3762 case ISD::ZERO_EXTEND: {
3764 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3765 case Expand: assert(0 && "expand-expand not implemented yet!");
3766 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3768 In = PromoteOp(Node->getOperand(0));
3769 // Emit the appropriate zero_extend_inreg to get the value we want.
3770 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType());
3774 // The low part is just a zero extension of the input (which degenerates to
3776 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In);
3778 // The high part is just a zero.
3779 Hi = DAG.getConstant(0, NVT);
3783 case ISD::BIT_CONVERT: {
3784 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0),
3785 Node->getOperand(0));
3786 ExpandOp(Tmp, Lo, Hi);
3790 case ISD::READCYCLECOUNTER: {
3791 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
3792 TargetLowering::Custom &&
3793 "Must custom expand ReadCycleCounter");
3794 SDOperand T = TLI.LowerOperation(Op, DAG);
3795 assert(T.Val && "Node must be custom expanded!");
3796 Lo = LegalizeOp(T.getValue(0));
3797 Hi = LegalizeOp(T.getValue(1));
3798 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
3799 LegalizeOp(T.getValue(2)));
3803 // These operators cannot be expanded directly, emit them as calls to
3804 // library functions.
3805 case ISD::FP_TO_SINT:
3806 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
3808 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3809 case Expand: assert(0 && "cannot expand FP!");
3810 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
3811 case Promote: Op = PromoteOp(Node->getOperand(0)); break;
3814 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
3816 // Now that the custom expander is done, expand the result, which is still
3819 ExpandOp(Op, Lo, Hi);
3824 if (Node->getOperand(0).getValueType() == MVT::f32)
3825 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
3827 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
3830 case ISD::FP_TO_UINT:
3831 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
3832 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT,
3833 LegalizeOp(Node->getOperand(0)));
3834 // Now that the custom expander is done, expand the result, which is still
3836 Op = TLI.LowerOperation(Op, DAG);
3838 ExpandOp(Op, Lo, Hi);
3843 if (Node->getOperand(0).getValueType() == MVT::f32)
3844 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
3846 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
3850 // If the target wants custom lowering, do so.
3851 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
3852 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0),
3853 LegalizeOp(Node->getOperand(1)));
3854 Op = TLI.LowerOperation(Op, DAG);
3856 // Now that the custom expander is done, expand the result, which is
3858 ExpandOp(Op, Lo, Hi);
3863 // If we can emit an efficient shift operation, do so now.
3864 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3867 // If this target supports SHL_PARTS, use it.
3868 if (TLI.isOperationLegal(ISD::SHL_PARTS, NVT)) {
3869 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1),
3874 // Otherwise, emit a libcall.
3875 Lo = ExpandLibCall("__ashldi3", Node, Hi);
3879 // If the target wants custom lowering, do so.
3880 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
3881 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0),
3882 LegalizeOp(Node->getOperand(1)));
3883 Op = TLI.LowerOperation(Op, DAG);
3885 // Now that the custom expander is done, expand the result, which is
3887 ExpandOp(Op, Lo, Hi);
3892 // If we can emit an efficient shift operation, do so now.
3893 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3896 // If this target supports SRA_PARTS, use it.
3897 if (TLI.isOperationLegal(ISD::SRA_PARTS, NVT)) {
3898 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1),
3903 // Otherwise, emit a libcall.
3904 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
3907 // If the target wants custom lowering, do so.
3908 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
3909 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0),
3910 LegalizeOp(Node->getOperand(1)));
3911 Op = TLI.LowerOperation(Op, DAG);
3913 // Now that the custom expander is done, expand the result, which is
3915 ExpandOp(Op, Lo, Hi);
3920 // If we can emit an efficient shift operation, do so now.
3921 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3924 // If this target supports SRL_PARTS, use it.
3925 if (TLI.isOperationLegal(ISD::SRL_PARTS, NVT)) {
3926 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1),
3931 // Otherwise, emit a libcall.
3932 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
3936 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1),
3940 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1),
3944 if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
3945 SDOperand LL, LH, RL, RH;
3946 ExpandOp(Node->getOperand(0), LL, LH);
3947 ExpandOp(Node->getOperand(1), RL, RH);
3948 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
3949 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
3950 // extended the sign bit of the low half through the upper half, and if so
3951 // emit a MULHS instead of the alternate sequence that is valid for any
3952 // i64 x i64 multiply.
3953 if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
3954 // is RH an extension of the sign bit of RL?
3955 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
3956 RH.getOperand(1).getOpcode() == ISD::Constant &&
3957 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
3958 // is LH an extension of the sign bit of LL?
3959 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
3960 LH.getOperand(1).getOpcode() == ISD::Constant &&
3961 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
3962 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
3964 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
3965 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
3966 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
3967 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
3968 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
3970 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
3972 Lo = ExpandLibCall("__muldi3" , Node, Hi); break;
3976 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
3977 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
3978 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
3979 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
3982 // Remember in a map if the values will be reused later.
3983 bool isNew = ExpandedNodes.insert(std::make_pair(Op,
3984 std::make_pair(Lo, Hi))).second;
3985 assert(isNew && "Value already expanded?!?");
3987 // Make sure the resultant values have been legalized themselves, unless this
3988 // is a type that requires multi-step expansion.
3989 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
3990 Lo = LegalizeOp(Lo);
3991 Hi = LegalizeOp(Hi);
3996 // SelectionDAG::Legalize - This is the entry point for the file.
3998 void SelectionDAG::Legalize() {
3999 /// run - This is the main entry point to this class.
4001 SelectionDAGLegalize(*this).Run();