1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Target/TargetLowering.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Compiler.h"
25 #include "llvm/ADT/SmallVector.h"
32 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
33 cl::desc("Pop up a window to show dags before legalize"));
35 static const bool ViewLegalizeDAGs = 0;
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class VISIBILITY_HIDDEN SelectionDAGLegalize {
55 // Libcall insertion helpers.
57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
58 /// legalized. We use this to ensure that calls are properly serialized
59 /// against each other, including inserted libcalls.
60 SDOperand LastCALLSEQ_END;
62 /// IsLegalizingCall - This member is used *only* for purposes of providing
63 /// helpful assertions that a libcall isn't created while another call is
64 /// being legalized (which could lead to non-serialized call sequences).
65 bool IsLegalizingCall;
68 Legal, // The target natively supports this operation.
69 Promote, // This operation should be executed in a larger type.
70 Expand // Try to expand this to other ops, otherwise use a libcall.
73 /// ValueTypeActions - This is a bitvector that contains two bits for each
74 /// value type, where the two bits correspond to the LegalizeAction enum.
75 /// This can be queried with "getTypeAction(VT)".
76 TargetLowering::ValueTypeActionImpl ValueTypeActions;
78 /// LegalizedNodes - For nodes that are of legal width, and that have more
79 /// than one use, this map indicates what regularized operand to use. This
80 /// allows us to avoid legalizing the same thing more than once.
81 std::map<SDOperand, SDOperand> LegalizedNodes;
83 /// PromotedNodes - For nodes that are below legal width, and that have more
84 /// than one use, this map indicates what promoted value to use. This allows
85 /// us to avoid promoting the same thing more than once.
86 std::map<SDOperand, SDOperand> PromotedNodes;
88 /// ExpandedNodes - For nodes that need to be expanded this map indicates
89 /// which which operands are the expanded version of the input. This allows
90 /// us to avoid expanding the same node more than once.
91 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
93 /// SplitNodes - For vector nodes that need to be split, this map indicates
94 /// which which operands are the split version of the input. This allows us
95 /// to avoid splitting the same node more than once.
96 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
98 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
99 /// concrete packed types, this contains the mapping of ones we have already
100 /// processed to the result.
101 std::map<SDOperand, SDOperand> PackedNodes;
103 void AddLegalizedOperand(SDOperand From, SDOperand To) {
104 LegalizedNodes.insert(std::make_pair(From, To));
105 // If someone requests legalization of the new node, return itself.
107 LegalizedNodes.insert(std::make_pair(To, To));
109 void AddPromotedOperand(SDOperand From, SDOperand To) {
110 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
111 assert(isNew && "Got into the map somehow?");
112 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
118 SelectionDAGLegalize(SelectionDAG &DAG);
120 /// getTypeAction - Return how we should legalize values of this type, either
121 /// it is already legal or we need to expand it into multiple registers of
122 /// smaller integer type, or we need to promote it to a larger type.
123 LegalizeAction getTypeAction(MVT::ValueType VT) const {
124 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
127 /// isTypeLegal - Return true if this type is legal on this target.
129 bool isTypeLegal(MVT::ValueType VT) const {
130 return getTypeAction(VT) == Legal;
136 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
137 /// appropriate for its type.
138 void HandleOp(SDOperand Op);
140 /// LegalizeOp - We know that the specified value has a legal type.
141 /// Recursively ensure that the operands have legal types, then return the
143 SDOperand LegalizeOp(SDOperand O);
145 /// PromoteOp - Given an operation that produces a value in an invalid type,
146 /// promote it to compute the value into a larger type. The produced value
147 /// will have the correct bits for the low portion of the register, but no
148 /// guarantee is made about the top bits: it may be zero, sign-extended, or
150 SDOperand PromoteOp(SDOperand O);
152 /// ExpandOp - Expand the specified SDOperand into its two component pieces
153 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
154 /// the LegalizeNodes map is filled in for any results that are not expanded,
155 /// the ExpandedNodes map is filled in for any results that are expanded, and
156 /// the Lo/Hi values are returned. This applies to integer types and Vector
158 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
160 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
161 /// two smaller values of MVT::Vector type.
162 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
164 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
165 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
166 /// this is called, we know that PackedVT is the right type for the result and
167 /// we know that this type is legal for the target.
168 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
170 /// isShuffleLegal - Return true if a vector shuffle is legal with the
171 /// specified mask and type. Targets can specify exactly which masks they
172 /// support and the code generator is tasked with not creating illegal masks.
174 /// Note that this will also return true for shuffles that are promoted to a
177 /// If this is a legal shuffle, this method returns the (possibly promoted)
178 /// build_vector Mask. If it's not a legal shuffle, it returns null.
179 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
181 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
182 std::set<SDNode*> &NodesLeadingTo);
184 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
186 SDOperand CreateStackTemporary(MVT::ValueType VT);
188 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
190 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
193 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
194 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
195 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
196 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
198 MVT::ValueType DestVT);
199 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
201 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
204 SDOperand ExpandBSWAP(SDOperand Op);
205 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
206 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
207 SDOperand &Lo, SDOperand &Hi);
208 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
209 SDOperand &Lo, SDOperand &Hi);
211 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
212 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
214 SDOperand getIntPtrConstant(uint64_t Val) {
215 return DAG.getConstant(Val, TLI.getPointerTy());
220 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
221 /// specified mask and type. Targets can specify exactly which masks they
222 /// support and the code generator is tasked with not creating illegal masks.
224 /// Note that this will also return true for shuffles that are promoted to a
226 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
227 SDOperand Mask) const {
228 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
230 case TargetLowering::Legal:
231 case TargetLowering::Custom:
233 case TargetLowering::Promote: {
234 // If this is promoted to a different type, convert the shuffle mask and
235 // ask if it is legal in the promoted type!
236 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
238 // If we changed # elements, change the shuffle mask.
239 unsigned NumEltsGrowth =
240 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
241 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
242 if (NumEltsGrowth > 1) {
243 // Renumber the elements.
244 SmallVector<SDOperand, 8> Ops;
245 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
246 SDOperand InOp = Mask.getOperand(i);
247 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
248 if (InOp.getOpcode() == ISD::UNDEF)
249 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
251 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
252 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
256 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
262 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
265 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
266 /// specified vector opcode.
267 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
269 default: assert(0 && "Don't know how to scalarize this opcode!");
270 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
271 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
272 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
273 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
274 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
275 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
276 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
277 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
281 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
282 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
283 ValueTypeActions(TLI.getValueTypeActions()) {
284 assert(MVT::LAST_VALUETYPE <= 32 &&
285 "Too many value types for ValueTypeActions to hold!");
288 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
289 /// not been visited yet and if all of its operands have already been visited.
290 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
291 std::map<SDNode*, unsigned> &Visited) {
292 if (++Visited[N] != N->getNumOperands())
293 return; // Haven't visited all operands yet
297 if (N->hasOneUse()) { // Tail recurse in common case.
298 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
302 // Now that we have N in, add anything that uses it if all of their operands
304 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
305 ComputeTopDownOrdering(*UI, Order, Visited);
309 void SelectionDAGLegalize::LegalizeDAG() {
310 LastCALLSEQ_END = DAG.getEntryNode();
311 IsLegalizingCall = false;
313 // The legalize process is inherently a bottom-up recursive process (users
314 // legalize their uses before themselves). Given infinite stack space, we
315 // could just start legalizing on the root and traverse the whole graph. In
316 // practice however, this causes us to run out of stack space on large basic
317 // blocks. To avoid this problem, compute an ordering of the nodes where each
318 // node is only legalized after all of its operands are legalized.
319 std::map<SDNode*, unsigned> Visited;
320 std::vector<SDNode*> Order;
322 // Compute ordering from all of the leaves in the graphs, those (like the
323 // entry node) that have no operands.
324 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
325 E = DAG.allnodes_end(); I != E; ++I) {
326 if (I->getNumOperands() == 0) {
328 ComputeTopDownOrdering(I, Order, Visited);
332 assert(Order.size() == Visited.size() &&
334 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
335 "Error: DAG is cyclic!");
338 for (unsigned i = 0, e = Order.size(); i != e; ++i)
339 HandleOp(SDOperand(Order[i], 0));
341 // Finally, it's possible the root changed. Get the new root.
342 SDOperand OldRoot = DAG.getRoot();
343 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
344 DAG.setRoot(LegalizedNodes[OldRoot]);
346 ExpandedNodes.clear();
347 LegalizedNodes.clear();
348 PromotedNodes.clear();
352 // Remove dead nodes now.
353 DAG.RemoveDeadNodes();
357 /// FindCallEndFromCallStart - Given a chained node that is part of a call
358 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
359 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
360 if (Node->getOpcode() == ISD::CALLSEQ_END)
362 if (Node->use_empty())
363 return 0; // No CallSeqEnd
365 // The chain is usually at the end.
366 SDOperand TheChain(Node, Node->getNumValues()-1);
367 if (TheChain.getValueType() != MVT::Other) {
368 // Sometimes it's at the beginning.
369 TheChain = SDOperand(Node, 0);
370 if (TheChain.getValueType() != MVT::Other) {
371 // Otherwise, hunt for it.
372 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
373 if (Node->getValueType(i) == MVT::Other) {
374 TheChain = SDOperand(Node, i);
378 // Otherwise, we walked into a node without a chain.
379 if (TheChain.getValueType() != MVT::Other)
384 for (SDNode::use_iterator UI = Node->use_begin(),
385 E = Node->use_end(); UI != E; ++UI) {
387 // Make sure to only follow users of our token chain.
389 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
390 if (User->getOperand(i) == TheChain)
391 if (SDNode *Result = FindCallEndFromCallStart(User))
397 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
398 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
399 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
400 assert(Node && "Didn't find callseq_start for a call??");
401 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
403 assert(Node->getOperand(0).getValueType() == MVT::Other &&
404 "Node doesn't have a token chain argument!");
405 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
408 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
409 /// see if any uses can reach Dest. If no dest operands can get to dest,
410 /// legalize them, legalize ourself, and return false, otherwise, return true.
412 /// Keep track of the nodes we fine that actually do lead to Dest in
413 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
415 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
416 std::set<SDNode*> &NodesLeadingTo) {
417 if (N == Dest) return true; // N certainly leads to Dest :)
419 // If we've already processed this node and it does lead to Dest, there is no
420 // need to reprocess it.
421 if (NodesLeadingTo.count(N)) return true;
423 // If the first result of this node has been already legalized, then it cannot
425 switch (getTypeAction(N->getValueType(0))) {
427 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
430 if (PromotedNodes.count(SDOperand(N, 0))) return false;
433 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
437 // Okay, this node has not already been legalized. Check and legalize all
438 // operands. If none lead to Dest, then we can legalize this node.
439 bool OperandsLeadToDest = false;
440 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
441 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
442 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
444 if (OperandsLeadToDest) {
445 NodesLeadingTo.insert(N);
449 // Okay, this node looks safe, legalize it and return false.
450 HandleOp(SDOperand(N, 0));
454 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
455 /// appropriate for its type.
456 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
457 switch (getTypeAction(Op.getValueType())) {
458 default: assert(0 && "Bad type action!");
459 case Legal: LegalizeOp(Op); break;
460 case Promote: PromoteOp(Op); break;
462 if (Op.getValueType() != MVT::Vector) {
467 unsigned NumOps = N->getNumOperands();
468 unsigned NumElements =
469 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
470 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
471 MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
472 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
473 // In the common case, this is a legal vector type, convert it to the
474 // packed operation and type now.
475 PackVectorOp(Op, PackedVT);
476 } else if (NumElements == 1) {
477 // Otherwise, if this is a single element vector, convert it to a
479 PackVectorOp(Op, EVT);
481 // Otherwise, this is a multiple element vector that isn't supported.
482 // Split it in half and legalize both parts.
484 SplitVectorOp(Op, X, Y);
492 /// LegalizeOp - We know that the specified value has a legal type.
493 /// Recursively ensure that the operands have legal types, then return the
495 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
496 assert(isTypeLegal(Op.getValueType()) &&
497 "Caller should expand or promote operands that are not legal!");
498 SDNode *Node = Op.Val;
500 // If this operation defines any values that cannot be represented in a
501 // register on this target, make sure to expand or promote them.
502 if (Node->getNumValues() > 1) {
503 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
504 if (getTypeAction(Node->getValueType(i)) != Legal) {
505 HandleOp(Op.getValue(i));
506 assert(LegalizedNodes.count(Op) &&
507 "Handling didn't add legal operands!");
508 return LegalizedNodes[Op];
512 // Note that LegalizeOp may be reentered even from single-use nodes, which
513 // means that we always must cache transformed nodes.
514 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
515 if (I != LegalizedNodes.end()) return I->second;
517 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
518 SDOperand Result = Op;
519 bool isCustom = false;
521 switch (Node->getOpcode()) {
522 case ISD::FrameIndex:
523 case ISD::EntryToken:
525 case ISD::BasicBlock:
526 case ISD::TargetFrameIndex:
527 case ISD::TargetJumpTable:
528 case ISD::TargetConstant:
529 case ISD::TargetConstantFP:
530 case ISD::TargetConstantPool:
531 case ISD::TargetGlobalAddress:
532 case ISD::TargetExternalSymbol:
537 case ISD::GLOBAL_OFFSET_TABLE:
538 // Primitives must all be legal.
539 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
540 "This must be legal!");
543 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
544 // If this is a target node, legalize it by legalizing the operands then
545 // passing it through.
546 SmallVector<SDOperand, 8> Ops;
547 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
548 Ops.push_back(LegalizeOp(Node->getOperand(i)));
550 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
552 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
553 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
554 return Result.getValue(Op.ResNo);
556 // Otherwise this is an unhandled builtin node. splat.
558 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
560 assert(0 && "Do not know how to legalize this operator!");
562 case ISD::GlobalAddress:
563 case ISD::ExternalSymbol:
564 case ISD::ConstantPool:
565 case ISD::JumpTable: // Nothing to do.
566 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
567 default: assert(0 && "This action is not supported yet!");
568 case TargetLowering::Custom:
569 Tmp1 = TLI.LowerOperation(Op, DAG);
570 if (Tmp1.Val) Result = Tmp1;
571 // FALLTHROUGH if the target doesn't want to lower this op after all.
572 case TargetLowering::Legal:
576 case ISD::AssertSext:
577 case ISD::AssertZext:
578 Tmp1 = LegalizeOp(Node->getOperand(0));
579 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
581 case ISD::MERGE_VALUES:
582 // Legalize eliminates MERGE_VALUES nodes.
583 Result = Node->getOperand(Op.ResNo);
585 case ISD::CopyFromReg:
586 Tmp1 = LegalizeOp(Node->getOperand(0));
587 Result = Op.getValue(0);
588 if (Node->getNumValues() == 2) {
589 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
591 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
592 if (Node->getNumOperands() == 3) {
593 Tmp2 = LegalizeOp(Node->getOperand(2));
594 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
596 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
598 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
600 // Since CopyFromReg produces two values, make sure to remember that we
601 // legalized both of them.
602 AddLegalizedOperand(Op.getValue(0), Result);
603 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
604 return Result.getValue(Op.ResNo);
606 MVT::ValueType VT = Op.getValueType();
607 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
608 default: assert(0 && "This action is not supported yet!");
609 case TargetLowering::Expand:
610 if (MVT::isInteger(VT))
611 Result = DAG.getConstant(0, VT);
612 else if (MVT::isFloatingPoint(VT))
613 Result = DAG.getConstantFP(0, VT);
615 assert(0 && "Unknown value type!");
617 case TargetLowering::Legal:
623 case ISD::INTRINSIC_W_CHAIN:
624 case ISD::INTRINSIC_WO_CHAIN:
625 case ISD::INTRINSIC_VOID: {
626 SmallVector<SDOperand, 8> Ops;
627 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
628 Ops.push_back(LegalizeOp(Node->getOperand(i)));
629 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
631 // Allow the target to custom lower its intrinsics if it wants to.
632 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
633 TargetLowering::Custom) {
634 Tmp3 = TLI.LowerOperation(Result, DAG);
635 if (Tmp3.Val) Result = Tmp3;
638 if (Result.Val->getNumValues() == 1) break;
640 // Must have return value and chain result.
641 assert(Result.Val->getNumValues() == 2 &&
642 "Cannot return more than two values!");
644 // Since loads produce two values, make sure to remember that we
645 // legalized both of them.
646 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
647 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
648 return Result.getValue(Op.ResNo);
652 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
653 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
655 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
656 case TargetLowering::Promote:
657 default: assert(0 && "This action is not supported yet!");
658 case TargetLowering::Expand: {
659 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
660 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
661 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
663 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
664 const std::string &FName =
665 cast<StringSDNode>(Node->getOperand(3))->getValue();
666 const std::string &DirName =
667 cast<StringSDNode>(Node->getOperand(4))->getValue();
668 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
670 SmallVector<SDOperand, 8> Ops;
671 Ops.push_back(Tmp1); // chain
672 SDOperand LineOp = Node->getOperand(1);
673 SDOperand ColOp = Node->getOperand(2);
676 Ops.push_back(LineOp); // line #
677 Ops.push_back(ColOp); // col #
678 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
679 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
681 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
682 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
683 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
684 Ops.push_back(DAG.getConstant(ID, MVT::i32));
685 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,&Ops[0],Ops.size());
688 Result = Tmp1; // chain
692 case TargetLowering::Legal:
693 if (Tmp1 != Node->getOperand(0) ||
694 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
695 SmallVector<SDOperand, 8> Ops;
697 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
698 Ops.push_back(Node->getOperand(1)); // line # must be legal.
699 Ops.push_back(Node->getOperand(2)); // col # must be legal.
701 // Otherwise promote them.
702 Ops.push_back(PromoteOp(Node->getOperand(1)));
703 Ops.push_back(PromoteOp(Node->getOperand(2)));
705 Ops.push_back(Node->getOperand(3)); // filename must be legal.
706 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
707 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
714 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
715 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
716 default: assert(0 && "This action is not supported yet!");
717 case TargetLowering::Legal:
718 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
719 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
720 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
721 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
722 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
727 case ISD::DEBUG_LABEL:
728 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
729 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
730 default: assert(0 && "This action is not supported yet!");
731 case TargetLowering::Legal:
732 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
733 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
734 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
740 // We know we don't need to expand constants here, constants only have one
741 // value and we check that it is fine above.
743 // FIXME: Maybe we should handle things like targets that don't support full
744 // 32-bit immediates?
746 case ISD::ConstantFP: {
747 // Spill FP immediates to the constant pool if the target cannot directly
748 // codegen them. Targets often have some immediate values that can be
749 // efficiently generated into an FP register without a load. We explicitly
750 // leave these constants as ConstantFP nodes for the target to deal with.
751 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
753 // Check to see if this FP immediate is already legal.
754 bool isLegal = false;
755 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
756 E = TLI.legal_fpimm_end(); I != E; ++I)
757 if (CFP->isExactlyValue(*I)) {
762 // If this is a legal constant, turn it into a TargetConstantFP node.
764 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
768 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
769 default: assert(0 && "This action is not supported yet!");
770 case TargetLowering::Custom:
771 Tmp3 = TLI.LowerOperation(Result, DAG);
777 case TargetLowering::Expand:
778 // Otherwise we need to spill the constant to memory.
781 // If a FP immediate is precise when represented as a float and if the
782 // target can do an extending load from float to double, we put it into
783 // the constant pool as a float, even if it's is statically typed as a
785 MVT::ValueType VT = CFP->getValueType(0);
786 bool isDouble = VT == MVT::f64;
787 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
788 Type::FloatTy, CFP->getValue());
789 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
790 // Only do this if the target has a native EXTLOAD instruction from
792 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
793 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
798 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
800 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
801 CPIdx, NULL, 0, MVT::f32);
803 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
808 case ISD::TokenFactor:
809 if (Node->getNumOperands() == 2) {
810 Tmp1 = LegalizeOp(Node->getOperand(0));
811 Tmp2 = LegalizeOp(Node->getOperand(1));
812 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
813 } else if (Node->getNumOperands() == 3) {
814 Tmp1 = LegalizeOp(Node->getOperand(0));
815 Tmp2 = LegalizeOp(Node->getOperand(1));
816 Tmp3 = LegalizeOp(Node->getOperand(2));
817 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
819 SmallVector<SDOperand, 8> Ops;
820 // Legalize the operands.
821 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
822 Ops.push_back(LegalizeOp(Node->getOperand(i)));
823 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
827 case ISD::FORMAL_ARGUMENTS:
829 // The only option for this is to custom lower it.
830 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
831 assert(Tmp3.Val && "Target didn't custom lower this node!");
832 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
833 "Lowering call/formal_arguments produced unexpected # results!");
835 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
836 // remember that we legalized all of them, so it doesn't get relegalized.
837 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
838 Tmp1 = LegalizeOp(Tmp3.getValue(i));
841 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
845 case ISD::BUILD_VECTOR:
846 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
847 default: assert(0 && "This action is not supported yet!");
848 case TargetLowering::Custom:
849 Tmp3 = TLI.LowerOperation(Result, DAG);
855 case TargetLowering::Expand:
856 Result = ExpandBUILD_VECTOR(Result.Val);
860 case ISD::INSERT_VECTOR_ELT:
861 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
862 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
863 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
864 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
866 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
867 Node->getValueType(0))) {
868 default: assert(0 && "This action is not supported yet!");
869 case TargetLowering::Legal:
871 case TargetLowering::Custom:
872 Tmp3 = TLI.LowerOperation(Result, DAG);
878 case TargetLowering::Expand: {
879 // If the insert index is a constant, codegen this as a scalar_to_vector,
880 // then a shuffle that inserts it into the right position in the vector.
881 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
882 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
883 Tmp1.getValueType(), Tmp2);
885 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
886 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
887 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT);
889 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
890 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
892 SmallVector<SDOperand, 8> ShufOps;
893 for (unsigned i = 0; i != NumElts; ++i) {
894 if (i != InsertPos->getValue())
895 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
897 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
899 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
900 &ShufOps[0], ShufOps.size());
902 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
903 Tmp1, ScVec, ShufMask);
904 Result = LegalizeOp(Result);
908 // If the target doesn't support this, we have to spill the input vector
909 // to a temporary stack slot, update the element, then reload it. This is
910 // badness. We could also load the value into a vector register (either
911 // with a "move to register" or "extload into register" instruction, then
912 // permute it into place, if the idx is a constant and if the idx is
913 // supported by the target.
914 MVT::ValueType VT = Tmp1.getValueType();
915 MVT::ValueType EltVT = Tmp2.getValueType();
916 MVT::ValueType IdxVT = Tmp3.getValueType();
917 MVT::ValueType PtrVT = TLI.getPointerTy();
918 SDOperand StackPtr = CreateStackTemporary(VT);
920 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
922 // Truncate or zero extend offset to target pointer type.
923 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
924 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
925 // Add the offset to the index.
926 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
927 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
928 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
929 // Store the scalar value.
930 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
931 // Load the updated vector.
932 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
937 case ISD::SCALAR_TO_VECTOR:
938 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
939 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
943 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
944 Result = DAG.UpdateNodeOperands(Result, Tmp1);
945 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
946 Node->getValueType(0))) {
947 default: assert(0 && "This action is not supported yet!");
948 case TargetLowering::Legal:
950 case TargetLowering::Custom:
951 Tmp3 = TLI.LowerOperation(Result, DAG);
957 case TargetLowering::Expand:
958 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
962 case ISD::VECTOR_SHUFFLE:
963 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
964 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
965 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
967 // Allow targets to custom lower the SHUFFLEs they support.
968 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
969 default: assert(0 && "Unknown operation action!");
970 case TargetLowering::Legal:
971 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
972 "vector shuffle should not be created if not legal!");
974 case TargetLowering::Custom:
975 Tmp3 = TLI.LowerOperation(Result, DAG);
981 case TargetLowering::Expand: {
982 MVT::ValueType VT = Node->getValueType(0);
983 MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
984 MVT::ValueType PtrVT = TLI.getPointerTy();
985 SDOperand Mask = Node->getOperand(2);
986 unsigned NumElems = Mask.getNumOperands();
987 SmallVector<SDOperand,8> Ops;
988 for (unsigned i = 0; i != NumElems; ++i) {
989 SDOperand Arg = Mask.getOperand(i);
990 if (Arg.getOpcode() == ISD::UNDEF) {
991 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
993 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
994 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
996 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
997 DAG.getConstant(Idx, PtrVT)));
999 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1000 DAG.getConstant(Idx - NumElems, PtrVT)));
1003 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1006 case TargetLowering::Promote: {
1007 // Change base type to a different vector type.
1008 MVT::ValueType OVT = Node->getValueType(0);
1009 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1011 // Cast the two input vectors.
1012 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1013 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1015 // Convert the shuffle mask to the right # elements.
1016 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1017 assert(Tmp3.Val && "Shuffle not legal?");
1018 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1019 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1025 case ISD::EXTRACT_VECTOR_ELT:
1026 Tmp1 = LegalizeOp(Node->getOperand(0));
1027 Tmp2 = LegalizeOp(Node->getOperand(1));
1028 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1030 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
1031 Tmp1.getValueType())) {
1032 default: assert(0 && "This action is not supported yet!");
1033 case TargetLowering::Legal:
1035 case TargetLowering::Custom:
1036 Tmp3 = TLI.LowerOperation(Result, DAG);
1042 case TargetLowering::Expand:
1043 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1048 case ISD::VEXTRACT_VECTOR_ELT:
1049 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
1052 case ISD::CALLSEQ_START: {
1053 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1055 // Recursively Legalize all of the inputs of the call end that do not lead
1056 // to this call start. This ensures that any libcalls that need be inserted
1057 // are inserted *before* the CALLSEQ_START.
1058 {std::set<SDNode*> NodesLeadingTo;
1059 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1060 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1064 // Now that we legalized all of the inputs (which may have inserted
1065 // libcalls) create the new CALLSEQ_START node.
1066 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1068 // Merge in the last call, to ensure that this call start after the last
1070 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1071 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1072 Tmp1 = LegalizeOp(Tmp1);
1075 // Do not try to legalize the target-specific arguments (#1+).
1076 if (Tmp1 != Node->getOperand(0)) {
1077 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1079 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1082 // Remember that the CALLSEQ_START is legalized.
1083 AddLegalizedOperand(Op.getValue(0), Result);
1084 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1085 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1087 // Now that the callseq_start and all of the non-call nodes above this call
1088 // sequence have been legalized, legalize the call itself. During this
1089 // process, no libcalls can/will be inserted, guaranteeing that no calls
1091 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1092 SDOperand InCallSEQ = LastCALLSEQ_END;
1093 // Note that we are selecting this call!
1094 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1095 IsLegalizingCall = true;
1097 // Legalize the call, starting from the CALLSEQ_END.
1098 LegalizeOp(LastCALLSEQ_END);
1099 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1102 case ISD::CALLSEQ_END:
1103 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1104 // will cause this node to be legalized as well as handling libcalls right.
1105 if (LastCALLSEQ_END.Val != Node) {
1106 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1107 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1108 assert(I != LegalizedNodes.end() &&
1109 "Legalizing the call start should have legalized this node!");
1113 // Otherwise, the call start has been legalized and everything is going
1114 // according to plan. Just legalize ourselves normally here.
1115 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1116 // Do not try to legalize the target-specific arguments (#1+), except for
1117 // an optional flag input.
1118 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1119 if (Tmp1 != Node->getOperand(0)) {
1120 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1122 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1125 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1126 if (Tmp1 != Node->getOperand(0) ||
1127 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1128 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1131 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1134 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1135 // This finishes up call legalization.
1136 IsLegalizingCall = false;
1138 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1139 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1140 if (Node->getNumValues() == 2)
1141 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1142 return Result.getValue(Op.ResNo);
1143 case ISD::DYNAMIC_STACKALLOC: {
1144 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1145 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1146 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1147 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1149 Tmp1 = Result.getValue(0);
1150 Tmp2 = Result.getValue(1);
1151 switch (TLI.getOperationAction(Node->getOpcode(),
1152 Node->getValueType(0))) {
1153 default: assert(0 && "This action is not supported yet!");
1154 case TargetLowering::Expand: {
1155 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1156 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1157 " not tell us which reg is the stack pointer!");
1158 SDOperand Chain = Tmp1.getOperand(0);
1159 SDOperand Size = Tmp2.getOperand(1);
1160 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1161 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1162 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1163 Tmp1 = LegalizeOp(Tmp1);
1164 Tmp2 = LegalizeOp(Tmp2);
1167 case TargetLowering::Custom:
1168 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1170 Tmp1 = LegalizeOp(Tmp3);
1171 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1174 case TargetLowering::Legal:
1177 // Since this op produce two values, make sure to remember that we
1178 // legalized both of them.
1179 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1180 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1181 return Op.ResNo ? Tmp2 : Tmp1;
1183 case ISD::INLINEASM: {
1184 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1185 bool Changed = false;
1186 // Legalize all of the operands of the inline asm, in case they are nodes
1187 // that need to be expanded or something. Note we skip the asm string and
1188 // all of the TargetConstant flags.
1189 SDOperand Op = LegalizeOp(Ops[0]);
1190 Changed = Op != Ops[0];
1193 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1194 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1195 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1196 for (++i; NumVals; ++i, --NumVals) {
1197 SDOperand Op = LegalizeOp(Ops[i]);
1206 Op = LegalizeOp(Ops.back());
1207 Changed |= Op != Ops.back();
1212 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1214 // INLINE asm returns a chain and flag, make sure to add both to the map.
1215 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1216 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1217 return Result.getValue(Op.ResNo);
1220 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1221 // Ensure that libcalls are emitted before a branch.
1222 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1223 Tmp1 = LegalizeOp(Tmp1);
1224 LastCALLSEQ_END = DAG.getEntryNode();
1226 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1229 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1230 // Ensure that libcalls are emitted before a branch.
1231 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1232 Tmp1 = LegalizeOp(Tmp1);
1233 LastCALLSEQ_END = DAG.getEntryNode();
1235 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1236 default: assert(0 && "Indirect target must be legal type (pointer)!");
1238 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1241 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1244 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1245 // Ensure that libcalls are emitted before a return.
1246 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1247 Tmp1 = LegalizeOp(Tmp1);
1248 LastCALLSEQ_END = DAG.getEntryNode();
1250 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1251 case Expand: assert(0 && "It's impossible to expand bools");
1253 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1256 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1260 // Basic block destination (Op#2) is always legal.
1261 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1263 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1264 default: assert(0 && "This action is not supported yet!");
1265 case TargetLowering::Legal: break;
1266 case TargetLowering::Custom:
1267 Tmp1 = TLI.LowerOperation(Result, DAG);
1268 if (Tmp1.Val) Result = Tmp1;
1270 case TargetLowering::Expand:
1271 // Expand brcond's setcc into its constituent parts and create a BR_CC
1273 if (Tmp2.getOpcode() == ISD::SETCC) {
1274 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1275 Tmp2.getOperand(0), Tmp2.getOperand(1),
1276 Node->getOperand(2));
1278 // Make sure the condition is either zero or one. It may have been
1279 // promoted from something else.
1280 unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType());
1281 if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1))
1282 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1284 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1285 DAG.getCondCode(ISD::SETNE), Tmp2,
1286 DAG.getConstant(0, Tmp2.getValueType()),
1287 Node->getOperand(2));
1293 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1294 // Ensure that libcalls are emitted before a branch.
1295 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1296 Tmp1 = LegalizeOp(Tmp1);
1297 LastCALLSEQ_END = DAG.getEntryNode();
1299 Tmp2 = Node->getOperand(2); // LHS
1300 Tmp3 = Node->getOperand(3); // RHS
1301 Tmp4 = Node->getOperand(1); // CC
1303 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1305 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1306 // the LHS is a legal SETCC itself. In this case, we need to compare
1307 // the result against zero to select between true and false values.
1308 if (Tmp3.Val == 0) {
1309 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1310 Tmp4 = DAG.getCondCode(ISD::SETNE);
1313 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1314 Node->getOperand(4));
1316 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1317 default: assert(0 && "Unexpected action for BR_CC!");
1318 case TargetLowering::Legal: break;
1319 case TargetLowering::Custom:
1320 Tmp4 = TLI.LowerOperation(Result, DAG);
1321 if (Tmp4.Val) Result = Tmp4;
1326 LoadSDNode *LD = cast<LoadSDNode>(Node);
1327 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1328 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1330 ISD::LoadExtType ExtType = LD->getExtensionType();
1331 if (ExtType == ISD::NON_EXTLOAD) {
1332 MVT::ValueType VT = Node->getValueType(0);
1333 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1334 Tmp3 = Result.getValue(0);
1335 Tmp4 = Result.getValue(1);
1337 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1338 default: assert(0 && "This action is not supported yet!");
1339 case TargetLowering::Legal: break;
1340 case TargetLowering::Custom:
1341 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1343 Tmp3 = LegalizeOp(Tmp1);
1344 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1347 case TargetLowering::Promote: {
1348 // Only promote a load of vector type to another.
1349 assert(MVT::isVector(VT) && "Cannot promote this load!");
1350 // Change base type to a different vector type.
1351 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1353 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1354 LD->getSrcValueOffset());
1355 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1356 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1360 // Since loads produce two values, make sure to remember that we
1361 // legalized both of them.
1362 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1363 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1364 return Op.ResNo ? Tmp4 : Tmp3;
1366 MVT::ValueType SrcVT = LD->getLoadedVT();
1367 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1368 default: assert(0 && "This action is not supported yet!");
1369 case TargetLowering::Promote:
1370 assert(SrcVT == MVT::i1 &&
1371 "Can only promote extending LOAD from i1 -> i8!");
1372 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1373 LD->getSrcValue(), LD->getSrcValueOffset(),
1375 Tmp1 = Result.getValue(0);
1376 Tmp2 = Result.getValue(1);
1378 case TargetLowering::Custom:
1381 case TargetLowering::Legal:
1382 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1383 Tmp1 = Result.getValue(0);
1384 Tmp2 = Result.getValue(1);
1387 Tmp3 = TLI.LowerOperation(Result, DAG);
1389 Tmp1 = LegalizeOp(Tmp3);
1390 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1394 case TargetLowering::Expand:
1395 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1396 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1397 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1398 LD->getSrcValueOffset());
1399 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1400 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1401 Tmp2 = LegalizeOp(Load.getValue(1));
1404 assert(ExtType != ISD::EXTLOAD && "EXTLOAD should always be supported!");
1405 // Turn the unsupported load into an EXTLOAD followed by an explicit
1406 // zero/sign extend inreg.
1407 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1408 Tmp1, Tmp2, LD->getSrcValue(),
1409 LD->getSrcValueOffset(), SrcVT);
1411 if (ExtType == ISD::SEXTLOAD)
1412 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1413 Result, DAG.getValueType(SrcVT));
1415 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1416 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1417 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1420 // Since loads produce two values, make sure to remember that we legalized
1422 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1423 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1424 return Op.ResNo ? Tmp2 : Tmp1;
1427 case ISD::EXTRACT_ELEMENT: {
1428 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1429 switch (getTypeAction(OpTy)) {
1430 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1432 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1434 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1435 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1436 TLI.getShiftAmountTy()));
1437 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1440 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1441 Node->getOperand(0));
1445 // Get both the low and high parts.
1446 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1447 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1448 Result = Tmp2; // 1 -> Hi
1450 Result = Tmp1; // 0 -> Lo
1456 case ISD::CopyToReg:
1457 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1459 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1460 "Register type must be legal!");
1461 // Legalize the incoming value (must be a legal type).
1462 Tmp2 = LegalizeOp(Node->getOperand(2));
1463 if (Node->getNumValues() == 1) {
1464 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1466 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1467 if (Node->getNumOperands() == 4) {
1468 Tmp3 = LegalizeOp(Node->getOperand(3));
1469 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1472 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1475 // Since this produces two values, make sure to remember that we legalized
1477 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1478 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1484 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1486 // Ensure that libcalls are emitted before a return.
1487 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1488 Tmp1 = LegalizeOp(Tmp1);
1489 LastCALLSEQ_END = DAG.getEntryNode();
1491 switch (Node->getNumOperands()) {
1493 Tmp2 = Node->getOperand(1);
1494 Tmp3 = Node->getOperand(2); // Signness
1495 switch (getTypeAction(Tmp2.getValueType())) {
1497 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1500 if (Tmp2.getValueType() != MVT::Vector) {
1502 ExpandOp(Tmp2, Lo, Hi);
1503 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1504 Result = LegalizeOp(Result);
1506 SDNode *InVal = Tmp2.Val;
1508 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1509 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1511 // Figure out if there is a Packed type corresponding to this Vector
1512 // type. If so, convert to the packed type.
1513 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1514 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1515 // Turn this into a return of the packed type.
1516 Tmp2 = PackVectorOp(Tmp2, TVT);
1517 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1518 } else if (NumElems == 1) {
1519 // Turn this into a return of the scalar type.
1520 Tmp2 = PackVectorOp(Tmp2, EVT);
1521 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1523 // FIXME: Returns of gcc generic vectors smaller than a legal type
1524 // should be returned in integer registers!
1526 // The scalarized value type may not be legal, e.g. it might require
1527 // promotion or expansion. Relegalize the return.
1528 Result = LegalizeOp(Result);
1530 // FIXME: Returns of gcc generic vectors larger than a legal vector
1531 // type should be returned by reference!
1533 SplitVectorOp(Tmp2, Lo, Hi);
1534 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1535 Result = LegalizeOp(Result);
1540 Tmp2 = PromoteOp(Node->getOperand(1));
1541 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1542 Result = LegalizeOp(Result);
1547 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1549 default: { // ret <values>
1550 SmallVector<SDOperand, 8> NewValues;
1551 NewValues.push_back(Tmp1);
1552 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1553 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1555 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1556 NewValues.push_back(Node->getOperand(i+1));
1560 assert(Node->getOperand(i).getValueType() != MVT::Vector &&
1561 "FIXME: TODO: implement returning non-legal vector types!");
1562 ExpandOp(Node->getOperand(i), Lo, Hi);
1563 NewValues.push_back(Lo);
1564 NewValues.push_back(Node->getOperand(i+1));
1565 NewValues.push_back(Hi);
1566 NewValues.push_back(Node->getOperand(i+1));
1570 assert(0 && "Can't promote multiple return value yet!");
1573 if (NewValues.size() == Node->getNumOperands())
1574 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1576 Result = DAG.getNode(ISD::RET, MVT::Other,
1577 &NewValues[0], NewValues.size());
1582 if (Result.getOpcode() == ISD::RET) {
1583 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1584 default: assert(0 && "This action is not supported yet!");
1585 case TargetLowering::Legal: break;
1586 case TargetLowering::Custom:
1587 Tmp1 = TLI.LowerOperation(Result, DAG);
1588 if (Tmp1.Val) Result = Tmp1;
1594 StoreSDNode *ST = cast<StoreSDNode>(Node);
1595 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1596 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1598 if (!ST->isTruncatingStore()) {
1599 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1600 // FIXME: We shouldn't do this for TargetConstantFP's.
1601 // FIXME: move this to the DAG Combiner!
1602 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(ST->getValue())) {
1603 if (CFP->getValueType(0) == MVT::f32) {
1604 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1606 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1607 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1609 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1610 ST->getSrcValueOffset());
1614 switch (getTypeAction(ST->getStoredVT())) {
1616 Tmp3 = LegalizeOp(ST->getValue());
1617 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1620 MVT::ValueType VT = Tmp3.getValueType();
1621 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1622 default: assert(0 && "This action is not supported yet!");
1623 case TargetLowering::Legal: break;
1624 case TargetLowering::Custom:
1625 Tmp1 = TLI.LowerOperation(Result, DAG);
1626 if (Tmp1.Val) Result = Tmp1;
1628 case TargetLowering::Promote:
1629 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1630 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1631 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1632 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
1633 ST->getSrcValue(), ST->getSrcValueOffset());
1639 // Truncate the value and store the result.
1640 Tmp3 = PromoteOp(ST->getValue());
1641 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1642 ST->getSrcValueOffset(), ST->getStoredVT());
1646 unsigned IncrementSize = 0;
1649 // If this is a vector type, then we have to calculate the increment as
1650 // the product of the element size in bytes, and the number of elements
1651 // in the high half of the vector.
1652 if (ST->getValue().getValueType() == MVT::Vector) {
1653 SDNode *InVal = ST->getValue().Val;
1655 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1656 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1658 // Figure out if there is a Packed type corresponding to this Vector
1659 // type. If so, convert to the packed type.
1660 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1661 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1662 // Turn this into a normal store of the packed type.
1663 Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1664 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1665 ST->getSrcValueOffset());
1666 Result = LegalizeOp(Result);
1668 } else if (NumElems == 1) {
1669 // Turn this into a normal store of the scalar type.
1670 Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1671 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1672 ST->getSrcValueOffset());
1673 // The scalarized value type may not be legal, e.g. it might require
1674 // promotion or expansion. Relegalize the scalar store.
1675 Result = LegalizeOp(Result);
1678 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1679 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1682 ExpandOp(Node->getOperand(1), Lo, Hi);
1683 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1685 if (!TLI.isLittleEndian())
1689 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
1690 ST->getSrcValueOffset());
1691 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1692 getIntPtrConstant(IncrementSize));
1693 assert(isTypeLegal(Tmp2.getValueType()) &&
1694 "Pointers must be legal!");
1695 // FIXME: This sets the srcvalue of both halves to be the same, which is
1697 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
1698 ST->getSrcValueOffset());
1699 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1704 assert(isTypeLegal(ST->getValue().getValueType()) &&
1705 "Cannot handle illegal TRUNCSTORE yet!");
1706 Tmp3 = LegalizeOp(ST->getValue());
1708 // The only promote case we handle is TRUNCSTORE:i1 X into
1709 // -> TRUNCSTORE:i8 (and X, 1)
1710 if (ST->getStoredVT() == MVT::i1 &&
1711 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
1712 // Promote the bool to a mask then store.
1713 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
1714 DAG.getConstant(1, Tmp3.getValueType()));
1715 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1716 ST->getSrcValueOffset(), MVT::i8);
1717 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1718 Tmp2 != ST->getBasePtr()) {
1719 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1723 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
1724 switch (TLI.getStoreXAction(StVT)) {
1725 default: assert(0 && "This action is not supported yet!");
1726 case TargetLowering::Legal: break;
1727 case TargetLowering::Custom:
1728 Tmp1 = TLI.LowerOperation(Result, DAG);
1729 if (Tmp1.Val) Result = Tmp1;
1736 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1737 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1739 case ISD::STACKSAVE:
1740 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1741 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1742 Tmp1 = Result.getValue(0);
1743 Tmp2 = Result.getValue(1);
1745 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1746 default: assert(0 && "This action is not supported yet!");
1747 case TargetLowering::Legal: break;
1748 case TargetLowering::Custom:
1749 Tmp3 = TLI.LowerOperation(Result, DAG);
1751 Tmp1 = LegalizeOp(Tmp3);
1752 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1755 case TargetLowering::Expand:
1756 // Expand to CopyFromReg if the target set
1757 // StackPointerRegisterToSaveRestore.
1758 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1759 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1760 Node->getValueType(0));
1761 Tmp2 = Tmp1.getValue(1);
1763 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1764 Tmp2 = Node->getOperand(0);
1769 // Since stacksave produce two values, make sure to remember that we
1770 // legalized both of them.
1771 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1772 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1773 return Op.ResNo ? Tmp2 : Tmp1;
1775 case ISD::STACKRESTORE:
1776 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1777 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1778 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1780 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1781 default: assert(0 && "This action is not supported yet!");
1782 case TargetLowering::Legal: break;
1783 case TargetLowering::Custom:
1784 Tmp1 = TLI.LowerOperation(Result, DAG);
1785 if (Tmp1.Val) Result = Tmp1;
1787 case TargetLowering::Expand:
1788 // Expand to CopyToReg if the target set
1789 // StackPointerRegisterToSaveRestore.
1790 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1791 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1799 case ISD::READCYCLECOUNTER:
1800 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1801 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1803 // Since rdcc produce two values, make sure to remember that we legalized
1805 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1806 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1810 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1811 case Expand: assert(0 && "It's impossible to expand bools");
1813 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1816 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1819 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1820 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1822 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1824 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1825 default: assert(0 && "This action is not supported yet!");
1826 case TargetLowering::Legal: break;
1827 case TargetLowering::Custom: {
1828 Tmp1 = TLI.LowerOperation(Result, DAG);
1829 if (Tmp1.Val) Result = Tmp1;
1832 case TargetLowering::Expand:
1833 if (Tmp1.getOpcode() == ISD::SETCC) {
1834 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1836 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1838 // Make sure the condition is either zero or one. It may have been
1839 // promoted from something else.
1840 unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType());
1841 if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1))
1842 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1843 Result = DAG.getSelectCC(Tmp1,
1844 DAG.getConstant(0, Tmp1.getValueType()),
1845 Tmp2, Tmp3, ISD::SETNE);
1848 case TargetLowering::Promote: {
1849 MVT::ValueType NVT =
1850 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1851 unsigned ExtOp, TruncOp;
1852 if (MVT::isVector(Tmp2.getValueType())) {
1853 ExtOp = ISD::BIT_CONVERT;
1854 TruncOp = ISD::BIT_CONVERT;
1855 } else if (MVT::isInteger(Tmp2.getValueType())) {
1856 ExtOp = ISD::ANY_EXTEND;
1857 TruncOp = ISD::TRUNCATE;
1859 ExtOp = ISD::FP_EXTEND;
1860 TruncOp = ISD::FP_ROUND;
1862 // Promote each of the values to the new type.
1863 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1864 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1865 // Perform the larger operation, then round down.
1866 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1867 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1872 case ISD::SELECT_CC: {
1873 Tmp1 = Node->getOperand(0); // LHS
1874 Tmp2 = Node->getOperand(1); // RHS
1875 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1876 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1877 SDOperand CC = Node->getOperand(4);
1879 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
1881 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1882 // the LHS is a legal SETCC itself. In this case, we need to compare
1883 // the result against zero to select between true and false values.
1884 if (Tmp2.Val == 0) {
1885 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1886 CC = DAG.getCondCode(ISD::SETNE);
1888 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
1890 // Everything is legal, see if we should expand this op or something.
1891 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
1892 default: assert(0 && "This action is not supported yet!");
1893 case TargetLowering::Legal: break;
1894 case TargetLowering::Custom:
1895 Tmp1 = TLI.LowerOperation(Result, DAG);
1896 if (Tmp1.Val) Result = Tmp1;
1902 Tmp1 = Node->getOperand(0);
1903 Tmp2 = Node->getOperand(1);
1904 Tmp3 = Node->getOperand(2);
1905 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
1907 // If we had to Expand the SetCC operands into a SELECT node, then it may
1908 // not always be possible to return a true LHS & RHS. In this case, just
1909 // return the value we legalized, returned in the LHS
1910 if (Tmp2.Val == 0) {
1915 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
1916 default: assert(0 && "Cannot handle this action for SETCC yet!");
1917 case TargetLowering::Custom:
1920 case TargetLowering::Legal:
1921 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1923 Tmp3 = TLI.LowerOperation(Result, DAG);
1924 if (Tmp3.Val) Result = Tmp3;
1927 case TargetLowering::Promote: {
1928 // First step, figure out the appropriate operation to use.
1929 // Allow SETCC to not be supported for all legal data types
1930 // Mostly this targets FP
1931 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1932 MVT::ValueType OldVT = NewInTy;
1934 // Scan for the appropriate larger type to use.
1936 NewInTy = (MVT::ValueType)(NewInTy+1);
1938 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1939 "Fell off of the edge of the integer world");
1940 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1941 "Fell off of the edge of the floating point world");
1943 // If the target supports SETCC of this type, use it.
1944 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
1947 if (MVT::isInteger(NewInTy))
1948 assert(0 && "Cannot promote Legal Integer SETCC yet");
1950 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1951 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
1953 Tmp1 = LegalizeOp(Tmp1);
1954 Tmp2 = LegalizeOp(Tmp2);
1955 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1956 Result = LegalizeOp(Result);
1959 case TargetLowering::Expand:
1960 // Expand a setcc node into a select_cc of the same condition, lhs, and
1961 // rhs that selects between const 1 (true) and const 0 (false).
1962 MVT::ValueType VT = Node->getValueType(0);
1963 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1964 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1965 Node->getOperand(2));
1971 case ISD::MEMMOVE: {
1972 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1973 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1975 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1976 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1977 case Expand: assert(0 && "Cannot expand a byte!");
1979 Tmp3 = LegalizeOp(Node->getOperand(2));
1982 Tmp3 = PromoteOp(Node->getOperand(2));
1986 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1990 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1992 // Length is too big, just take the lo-part of the length.
1994 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
1998 Tmp4 = LegalizeOp(Node->getOperand(3));
2001 Tmp4 = PromoteOp(Node->getOperand(3));
2006 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2007 case Expand: assert(0 && "Cannot expand this yet!");
2009 Tmp5 = LegalizeOp(Node->getOperand(4));
2012 Tmp5 = PromoteOp(Node->getOperand(4));
2016 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2017 default: assert(0 && "This action not implemented for this operation!");
2018 case TargetLowering::Custom:
2021 case TargetLowering::Legal:
2022 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2024 Tmp1 = TLI.LowerOperation(Result, DAG);
2025 if (Tmp1.Val) Result = Tmp1;
2028 case TargetLowering::Expand: {
2029 // Otherwise, the target does not support this operation. Lower the
2030 // operation to an explicit libcall as appropriate.
2031 MVT::ValueType IntPtr = TLI.getPointerTy();
2032 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2033 std::vector<std::pair<SDOperand, const Type*> > Args;
2035 const char *FnName = 0;
2036 if (Node->getOpcode() == ISD::MEMSET) {
2037 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2038 // Extend the (previously legalized) ubyte argument to be an int value
2040 if (Tmp3.getValueType() > MVT::i32)
2041 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2043 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2044 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
2045 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2048 } else if (Node->getOpcode() == ISD::MEMCPY ||
2049 Node->getOpcode() == ISD::MEMMOVE) {
2050 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2051 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
2052 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2053 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2055 assert(0 && "Unknown op!");
2058 std::pair<SDOperand,SDOperand> CallResult =
2059 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
2060 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2061 Result = CallResult.second;
2068 case ISD::SHL_PARTS:
2069 case ISD::SRA_PARTS:
2070 case ISD::SRL_PARTS: {
2071 SmallVector<SDOperand, 8> Ops;
2072 bool Changed = false;
2073 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2074 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2075 Changed |= Ops.back() != Node->getOperand(i);
2078 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2080 switch (TLI.getOperationAction(Node->getOpcode(),
2081 Node->getValueType(0))) {
2082 default: assert(0 && "This action is not supported yet!");
2083 case TargetLowering::Legal: break;
2084 case TargetLowering::Custom:
2085 Tmp1 = TLI.LowerOperation(Result, DAG);
2087 SDOperand Tmp2, RetVal(0, 0);
2088 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2089 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2090 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2094 assert(RetVal.Val && "Illegal result number");
2100 // Since these produce multiple values, make sure to remember that we
2101 // legalized all of them.
2102 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2103 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2104 return Result.getValue(Op.ResNo);
2125 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2126 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2127 case Expand: assert(0 && "Not possible");
2129 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2132 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2136 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2138 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2139 default: assert(0 && "BinOp legalize operation not supported");
2140 case TargetLowering::Legal: break;
2141 case TargetLowering::Custom:
2142 Tmp1 = TLI.LowerOperation(Result, DAG);
2143 if (Tmp1.Val) Result = Tmp1;
2145 case TargetLowering::Expand: {
2146 if (Node->getValueType(0) == MVT::i32) {
2147 switch (Node->getOpcode()) {
2148 default: assert(0 && "Do not know how to expand this integer BinOp!");
2151 const char *FnName = Node->getOpcode() == ISD::UDIV
2152 ? "__udivsi3" : "__divsi3";
2154 Result = ExpandLibCall(FnName, Node, Dummy);
2159 assert(MVT::isVector(Node->getValueType(0)) &&
2160 "Cannot expand this binary operator!");
2161 // Expand the operation into a bunch of nasty scalar code.
2162 SmallVector<SDOperand, 8> Ops;
2163 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
2164 MVT::ValueType PtrVT = TLI.getPointerTy();
2165 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2167 SDOperand Idx = DAG.getConstant(i, PtrVT);
2168 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2169 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2170 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2172 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2173 &Ops[0], Ops.size());
2176 case TargetLowering::Promote: {
2177 switch (Node->getOpcode()) {
2178 default: assert(0 && "Do not know how to promote this BinOp!");
2182 MVT::ValueType OVT = Node->getValueType(0);
2183 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2184 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2185 // Bit convert each of the values to the new type.
2186 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2187 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2188 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2189 // Bit convert the result back the original type.
2190 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2198 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2199 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2200 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2201 case Expand: assert(0 && "Not possible");
2203 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2206 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2210 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2212 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2213 default: assert(0 && "Operation not supported");
2214 case TargetLowering::Custom:
2215 Tmp1 = TLI.LowerOperation(Result, DAG);
2216 if (Tmp1.Val) Result = Tmp1;
2218 case TargetLowering::Legal: break;
2219 case TargetLowering::Expand:
2220 // If this target supports fabs/fneg natively, do this efficiently.
2221 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
2222 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
2223 // Get the sign bit of the RHS.
2224 MVT::ValueType IVT =
2225 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2226 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2227 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2228 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2229 // Get the absolute value of the result.
2230 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2231 // Select between the nabs and abs value based on the sign bit of
2233 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2234 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2237 Result = LegalizeOp(Result);
2241 // Otherwise, do bitwise ops!
2243 // copysign -> copysignf/copysign libcall.
2245 if (Node->getValueType(0) == MVT::f32) {
2246 FnName = "copysignf";
2247 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type.
2248 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2249 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2));
2251 FnName = "copysign";
2252 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type.
2253 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2254 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2));
2257 Result = ExpandLibCall(FnName, Node, Dummy);
2264 Tmp1 = LegalizeOp(Node->getOperand(0));
2265 Tmp2 = LegalizeOp(Node->getOperand(1));
2266 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2267 // Since this produces two values, make sure to remember that we legalized
2269 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2270 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2275 Tmp1 = LegalizeOp(Node->getOperand(0));
2276 Tmp2 = LegalizeOp(Node->getOperand(1));
2277 Tmp3 = LegalizeOp(Node->getOperand(2));
2278 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2279 // Since this produces two values, make sure to remember that we legalized
2281 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2282 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2285 case ISD::BUILD_PAIR: {
2286 MVT::ValueType PairTy = Node->getValueType(0);
2287 // TODO: handle the case where the Lo and Hi operands are not of legal type
2288 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2289 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2290 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2291 case TargetLowering::Promote:
2292 case TargetLowering::Custom:
2293 assert(0 && "Cannot promote/custom this yet!");
2294 case TargetLowering::Legal:
2295 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2296 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2298 case TargetLowering::Expand:
2299 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2300 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2301 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2302 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2303 TLI.getShiftAmountTy()));
2304 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2313 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2314 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2316 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2317 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2318 case TargetLowering::Custom:
2321 case TargetLowering::Legal:
2322 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2324 Tmp1 = TLI.LowerOperation(Result, DAG);
2325 if (Tmp1.Val) Result = Tmp1;
2328 case TargetLowering::Expand:
2329 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2330 if (MVT::isInteger(Node->getValueType(0))) {
2331 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2332 TargetLowering::Legal) {
2334 MVT::ValueType VT = Node->getValueType(0);
2335 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2336 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2337 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2339 assert(Node->getValueType(0) == MVT::i32 &&
2340 "Cannot expand this binary operator!");
2341 const char *FnName = Node->getOpcode() == ISD::UREM
2342 ? "__umodsi3" : "__modsi3";
2344 Result = ExpandLibCall(FnName, Node, Dummy);
2347 // Floating point mod -> fmod libcall.
2348 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
2350 Result = ExpandLibCall(FnName, Node, Dummy);
2356 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2357 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2359 MVT::ValueType VT = Node->getValueType(0);
2360 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2361 default: assert(0 && "This action is not supported yet!");
2362 case TargetLowering::Custom:
2365 case TargetLowering::Legal:
2366 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2367 Result = Result.getValue(0);
2368 Tmp1 = Result.getValue(1);
2371 Tmp2 = TLI.LowerOperation(Result, DAG);
2373 Result = LegalizeOp(Tmp2);
2374 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2378 case TargetLowering::Expand: {
2379 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2380 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2381 SV->getValue(), SV->getOffset());
2382 // Increment the pointer, VAList, to the next vaarg
2383 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2384 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2385 TLI.getPointerTy()));
2386 // Store the incremented VAList to the legalized pointer
2387 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
2389 // Load the actual argument out of the pointer VAList
2390 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2391 Tmp1 = LegalizeOp(Result.getValue(1));
2392 Result = LegalizeOp(Result);
2396 // Since VAARG produces two values, make sure to remember that we
2397 // legalized both of them.
2398 AddLegalizedOperand(SDOperand(Node, 0), Result);
2399 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2400 return Op.ResNo ? Tmp1 : Result;
2404 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2405 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2406 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2408 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2409 default: assert(0 && "This action is not supported yet!");
2410 case TargetLowering::Custom:
2413 case TargetLowering::Legal:
2414 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2415 Node->getOperand(3), Node->getOperand(4));
2417 Tmp1 = TLI.LowerOperation(Result, DAG);
2418 if (Tmp1.Val) Result = Tmp1;
2421 case TargetLowering::Expand:
2422 // This defaults to loading a pointer from the input and storing it to the
2423 // output, returning the chain.
2424 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
2425 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
2426 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
2428 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
2435 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2436 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2438 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2439 default: assert(0 && "This action is not supported yet!");
2440 case TargetLowering::Custom:
2443 case TargetLowering::Legal:
2444 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2446 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2447 if (Tmp1.Val) Result = Tmp1;
2450 case TargetLowering::Expand:
2451 Result = Tmp1; // Default to a no-op, return the chain
2457 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2458 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2460 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2462 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2463 default: assert(0 && "This action is not supported yet!");
2464 case TargetLowering::Legal: break;
2465 case TargetLowering::Custom:
2466 Tmp1 = TLI.LowerOperation(Result, DAG);
2467 if (Tmp1.Val) Result = Tmp1;
2474 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2475 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2477 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2478 "Cannot handle this yet!");
2479 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2483 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2484 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2485 case TargetLowering::Custom:
2486 assert(0 && "Cannot custom legalize this yet!");
2487 case TargetLowering::Legal:
2488 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2490 case TargetLowering::Promote: {
2491 MVT::ValueType OVT = Tmp1.getValueType();
2492 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2493 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2495 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2496 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2497 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2498 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2501 case TargetLowering::Expand:
2502 Result = ExpandBSWAP(Tmp1);
2510 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2511 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2512 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2513 case TargetLowering::Legal:
2514 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2516 case TargetLowering::Promote: {
2517 MVT::ValueType OVT = Tmp1.getValueType();
2518 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2520 // Zero extend the argument.
2521 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2522 // Perform the larger operation, then subtract if needed.
2523 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2524 switch (Node->getOpcode()) {
2529 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2530 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2531 DAG.getConstant(getSizeInBits(NVT), NVT),
2533 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2534 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2537 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2538 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2539 DAG.getConstant(getSizeInBits(NVT) -
2540 getSizeInBits(OVT), NVT));
2545 case TargetLowering::Expand:
2546 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2557 Tmp1 = LegalizeOp(Node->getOperand(0));
2558 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2559 case TargetLowering::Promote:
2560 case TargetLowering::Custom:
2563 case TargetLowering::Legal:
2564 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2566 Tmp1 = TLI.LowerOperation(Result, DAG);
2567 if (Tmp1.Val) Result = Tmp1;
2570 case TargetLowering::Expand:
2571 switch (Node->getOpcode()) {
2572 default: assert(0 && "Unreachable!");
2574 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2575 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2576 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2579 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2580 MVT::ValueType VT = Node->getValueType(0);
2581 Tmp2 = DAG.getConstantFP(0.0, VT);
2582 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2583 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2584 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2590 MVT::ValueType VT = Node->getValueType(0);
2591 const char *FnName = 0;
2592 switch(Node->getOpcode()) {
2593 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2594 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2595 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2596 default: assert(0 && "Unreachable!");
2599 Result = ExpandLibCall(FnName, Node, Dummy);
2607 // We always lower FPOWI into a libcall. No target support it yet.
2608 const char *FnName = Node->getValueType(0) == MVT::f32
2609 ? "__powisf2" : "__powidf2";
2611 Result = ExpandLibCall(FnName, Node, Dummy);
2614 case ISD::BIT_CONVERT:
2615 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2616 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2618 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2619 Node->getOperand(0).getValueType())) {
2620 default: assert(0 && "Unknown operation action!");
2621 case TargetLowering::Expand:
2622 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2624 case TargetLowering::Legal:
2625 Tmp1 = LegalizeOp(Node->getOperand(0));
2626 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2631 case ISD::VBIT_CONVERT: {
2632 assert(Op.getOperand(0).getValueType() == MVT::Vector &&
2633 "Can only have VBIT_CONVERT where input or output is MVT::Vector!");
2635 // The input has to be a vector type, we have to either scalarize it, pack
2636 // it, or convert it based on whether the input vector type is legal.
2637 SDNode *InVal = Node->getOperand(0).Val;
2639 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
2640 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
2642 // Figure out if there is a Packed type corresponding to this Vector
2643 // type. If so, convert to the packed type.
2644 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2645 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
2646 // Turn this into a bit convert of the packed input.
2647 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2648 PackVectorOp(Node->getOperand(0), TVT));
2650 } else if (NumElems == 1) {
2651 // Turn this into a bit convert of the scalar input.
2652 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2653 PackVectorOp(Node->getOperand(0), EVT));
2656 // FIXME: UNIMP! Store then reload
2657 assert(0 && "Cast from unsupported vector type not implemented yet!");
2661 // Conversion operators. The source and destination have different types.
2662 case ISD::SINT_TO_FP:
2663 case ISD::UINT_TO_FP: {
2664 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2665 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2667 switch (TLI.getOperationAction(Node->getOpcode(),
2668 Node->getOperand(0).getValueType())) {
2669 default: assert(0 && "Unknown operation action!");
2670 case TargetLowering::Custom:
2673 case TargetLowering::Legal:
2674 Tmp1 = LegalizeOp(Node->getOperand(0));
2675 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2677 Tmp1 = TLI.LowerOperation(Result, DAG);
2678 if (Tmp1.Val) Result = Tmp1;
2681 case TargetLowering::Expand:
2682 Result = ExpandLegalINT_TO_FP(isSigned,
2683 LegalizeOp(Node->getOperand(0)),
2684 Node->getValueType(0));
2686 case TargetLowering::Promote:
2687 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2688 Node->getValueType(0),
2694 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2695 Node->getValueType(0), Node->getOperand(0));
2698 Tmp1 = PromoteOp(Node->getOperand(0));
2700 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2701 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2703 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2704 Node->getOperand(0).getValueType());
2706 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2707 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2713 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2715 Tmp1 = LegalizeOp(Node->getOperand(0));
2716 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2719 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2721 // Since the result is legal, we should just be able to truncate the low
2722 // part of the source.
2723 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2726 Result = PromoteOp(Node->getOperand(0));
2727 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2732 case ISD::FP_TO_SINT:
2733 case ISD::FP_TO_UINT:
2734 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2736 Tmp1 = LegalizeOp(Node->getOperand(0));
2738 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2739 default: assert(0 && "Unknown operation action!");
2740 case TargetLowering::Custom:
2743 case TargetLowering::Legal:
2744 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2746 Tmp1 = TLI.LowerOperation(Result, DAG);
2747 if (Tmp1.Val) Result = Tmp1;
2750 case TargetLowering::Promote:
2751 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2752 Node->getOpcode() == ISD::FP_TO_SINT);
2754 case TargetLowering::Expand:
2755 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2756 SDOperand True, False;
2757 MVT::ValueType VT = Node->getOperand(0).getValueType();
2758 MVT::ValueType NVT = Node->getValueType(0);
2759 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2760 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2761 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2762 Node->getOperand(0), Tmp2, ISD::SETLT);
2763 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2764 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2765 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2767 False = DAG.getNode(ISD::XOR, NVT, False,
2768 DAG.getConstant(1ULL << ShiftAmt, NVT));
2769 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2772 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2778 assert(0 && "Shouldn't need to expand other operators here!");
2780 Tmp1 = PromoteOp(Node->getOperand(0));
2781 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
2782 Result = LegalizeOp(Result);
2787 case ISD::ANY_EXTEND:
2788 case ISD::ZERO_EXTEND:
2789 case ISD::SIGN_EXTEND:
2790 case ISD::FP_EXTEND:
2792 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2793 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
2795 Tmp1 = LegalizeOp(Node->getOperand(0));
2796 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2799 switch (Node->getOpcode()) {
2800 case ISD::ANY_EXTEND:
2801 Tmp1 = PromoteOp(Node->getOperand(0));
2802 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
2804 case ISD::ZERO_EXTEND:
2805 Result = PromoteOp(Node->getOperand(0));
2806 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2807 Result = DAG.getZeroExtendInReg(Result,
2808 Node->getOperand(0).getValueType());
2810 case ISD::SIGN_EXTEND:
2811 Result = PromoteOp(Node->getOperand(0));
2812 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2813 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2815 DAG.getValueType(Node->getOperand(0).getValueType()));
2817 case ISD::FP_EXTEND:
2818 Result = PromoteOp(Node->getOperand(0));
2819 if (Result.getValueType() != Op.getValueType())
2820 // Dynamically dead while we have only 2 FP types.
2821 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2824 Result = PromoteOp(Node->getOperand(0));
2825 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2830 case ISD::FP_ROUND_INREG:
2831 case ISD::SIGN_EXTEND_INREG: {
2832 Tmp1 = LegalizeOp(Node->getOperand(0));
2833 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2835 // If this operation is not supported, convert it to a shl/shr or load/store
2837 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2838 default: assert(0 && "This action not supported for this op yet!");
2839 case TargetLowering::Legal:
2840 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2842 case TargetLowering::Expand:
2843 // If this is an integer extend and shifts are supported, do that.
2844 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2845 // NOTE: we could fall back on load/store here too for targets without
2846 // SAR. However, it is doubtful that any exist.
2847 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2848 MVT::getSizeInBits(ExtraVT);
2849 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2850 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2851 Node->getOperand(0), ShiftCst);
2852 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2854 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2855 // The only way we can lower this is to turn it into a TRUNCSTORE,
2856 // EXTLOAD pair, targetting a temporary location (a stack slot).
2858 // NOTE: there is a choice here between constantly creating new stack
2859 // slots and always reusing the same one. We currently always create
2860 // new ones, as reuse may inhibit scheduling.
2861 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2862 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty);
2863 unsigned Align = TLI.getTargetData()->getTypeAlignment(Ty);
2864 MachineFunction &MF = DAG.getMachineFunction();
2866 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2867 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2868 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
2869 StackSlot, NULL, 0, ExtraVT);
2870 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2871 Result, StackSlot, NULL, 0, ExtraVT);
2873 assert(0 && "Unknown op");
2881 assert(Result.getValueType() == Op.getValueType() &&
2882 "Bad legalization!");
2884 // Make sure that the generated code is itself legal.
2886 Result = LegalizeOp(Result);
2888 // Note that LegalizeOp may be reentered even from single-use nodes, which
2889 // means that we always must cache transformed nodes.
2890 AddLegalizedOperand(Op, Result);
2894 /// PromoteOp - Given an operation that produces a value in an invalid type,
2895 /// promote it to compute the value into a larger type. The produced value will
2896 /// have the correct bits for the low portion of the register, but no guarantee
2897 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2898 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2899 MVT::ValueType VT = Op.getValueType();
2900 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2901 assert(getTypeAction(VT) == Promote &&
2902 "Caller should expand or legalize operands that are not promotable!");
2903 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2904 "Cannot promote to smaller type!");
2906 SDOperand Tmp1, Tmp2, Tmp3;
2908 SDNode *Node = Op.Val;
2910 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2911 if (I != PromotedNodes.end()) return I->second;
2913 switch (Node->getOpcode()) {
2914 case ISD::CopyFromReg:
2915 assert(0 && "CopyFromReg must be legal!");
2918 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2920 assert(0 && "Do not know how to promote this operator!");
2923 Result = DAG.getNode(ISD::UNDEF, NVT);
2927 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2929 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2930 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2932 case ISD::ConstantFP:
2933 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2934 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2938 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2939 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2940 Node->getOperand(1), Node->getOperand(2));
2944 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2946 Result = LegalizeOp(Node->getOperand(0));
2947 assert(Result.getValueType() >= NVT &&
2948 "This truncation doesn't make sense!");
2949 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2950 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2953 // The truncation is not required, because we don't guarantee anything
2954 // about high bits anyway.
2955 Result = PromoteOp(Node->getOperand(0));
2958 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2959 // Truncate the low part of the expanded value to the result type
2960 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2963 case ISD::SIGN_EXTEND:
2964 case ISD::ZERO_EXTEND:
2965 case ISD::ANY_EXTEND:
2966 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2967 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2969 // Input is legal? Just do extend all the way to the larger type.
2970 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2973 // Promote the reg if it's smaller.
2974 Result = PromoteOp(Node->getOperand(0));
2975 // The high bits are not guaranteed to be anything. Insert an extend.
2976 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2977 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2978 DAG.getValueType(Node->getOperand(0).getValueType()));
2979 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2980 Result = DAG.getZeroExtendInReg(Result,
2981 Node->getOperand(0).getValueType());
2985 case ISD::BIT_CONVERT:
2986 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2987 Result = PromoteOp(Result);
2990 case ISD::FP_EXTEND:
2991 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2993 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2994 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2995 case Promote: assert(0 && "Unreachable with 2 FP types!");
2997 // Input is legal? Do an FP_ROUND_INREG.
2998 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
2999 DAG.getValueType(VT));
3004 case ISD::SINT_TO_FP:
3005 case ISD::UINT_TO_FP:
3006 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3008 // No extra round required here.
3009 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3013 Result = PromoteOp(Node->getOperand(0));
3014 if (Node->getOpcode() == ISD::SINT_TO_FP)
3015 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3017 DAG.getValueType(Node->getOperand(0).getValueType()));
3019 Result = DAG.getZeroExtendInReg(Result,
3020 Node->getOperand(0).getValueType());
3021 // No extra round required here.
3022 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3025 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3026 Node->getOperand(0));
3027 // Round if we cannot tolerate excess precision.
3028 if (NoExcessFPPrecision)
3029 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3030 DAG.getValueType(VT));
3035 case ISD::SIGN_EXTEND_INREG:
3036 Result = PromoteOp(Node->getOperand(0));
3037 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3038 Node->getOperand(1));
3040 case ISD::FP_TO_SINT:
3041 case ISD::FP_TO_UINT:
3042 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3044 Tmp1 = Node->getOperand(0);
3047 // The input result is prerounded, so we don't have to do anything
3049 Tmp1 = PromoteOp(Node->getOperand(0));
3052 assert(0 && "not implemented");
3054 // If we're promoting a UINT to a larger size, check to see if the new node
3055 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3056 // we can use that instead. This allows us to generate better code for
3057 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3058 // legal, such as PowerPC.
3059 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3060 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3061 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3062 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3063 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3065 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3071 Tmp1 = PromoteOp(Node->getOperand(0));
3072 assert(Tmp1.getValueType() == NVT);
3073 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3074 // NOTE: we do not have to do any extra rounding here for
3075 // NoExcessFPPrecision, because we know the input will have the appropriate
3076 // precision, and these operations don't modify precision at all.
3082 Tmp1 = PromoteOp(Node->getOperand(0));
3083 assert(Tmp1.getValueType() == NVT);
3084 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3085 if (NoExcessFPPrecision)
3086 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3087 DAG.getValueType(VT));
3096 // The input may have strange things in the top bits of the registers, but
3097 // these operations don't care. They may have weird bits going out, but
3098 // that too is okay if they are integer operations.
3099 Tmp1 = PromoteOp(Node->getOperand(0));
3100 Tmp2 = PromoteOp(Node->getOperand(1));
3101 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3102 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3107 Tmp1 = PromoteOp(Node->getOperand(0));
3108 Tmp2 = PromoteOp(Node->getOperand(1));
3109 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3110 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3112 // Floating point operations will give excess precision that we may not be
3113 // able to tolerate. If we DO allow excess precision, just leave it,
3114 // otherwise excise it.
3115 // FIXME: Why would we need to round FP ops more than integer ones?
3116 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3117 if (NoExcessFPPrecision)
3118 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3119 DAG.getValueType(VT));
3124 // These operators require that their input be sign extended.
3125 Tmp1 = PromoteOp(Node->getOperand(0));
3126 Tmp2 = PromoteOp(Node->getOperand(1));
3127 if (MVT::isInteger(NVT)) {
3128 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3129 DAG.getValueType(VT));
3130 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3131 DAG.getValueType(VT));
3133 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3135 // Perform FP_ROUND: this is probably overly pessimistic.
3136 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3137 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3138 DAG.getValueType(VT));
3142 case ISD::FCOPYSIGN:
3143 // These operators require that their input be fp extended.
3144 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3146 Tmp1 = LegalizeOp(Node->getOperand(0));
3149 Tmp1 = PromoteOp(Node->getOperand(0));
3152 assert(0 && "not implemented");
3154 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3156 Tmp2 = LegalizeOp(Node->getOperand(1));
3159 Tmp2 = PromoteOp(Node->getOperand(1));
3162 assert(0 && "not implemented");
3164 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3166 // Perform FP_ROUND: this is probably overly pessimistic.
3167 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3168 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3169 DAG.getValueType(VT));
3174 // These operators require that their input be zero extended.
3175 Tmp1 = PromoteOp(Node->getOperand(0));
3176 Tmp2 = PromoteOp(Node->getOperand(1));
3177 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3178 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3179 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3180 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3184 Tmp1 = PromoteOp(Node->getOperand(0));
3185 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3188 // The input value must be properly sign extended.
3189 Tmp1 = PromoteOp(Node->getOperand(0));
3190 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3191 DAG.getValueType(VT));
3192 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3195 // The input value must be properly zero extended.
3196 Tmp1 = PromoteOp(Node->getOperand(0));
3197 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3198 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3202 Tmp1 = Node->getOperand(0); // Get the chain.
3203 Tmp2 = Node->getOperand(1); // Get the pointer.
3204 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3205 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3206 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3208 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3209 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3210 SV->getValue(), SV->getOffset());
3211 // Increment the pointer, VAList, to the next vaarg
3212 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3213 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3214 TLI.getPointerTy()));
3215 // Store the incremented VAList to the legalized pointer
3216 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3218 // Load the actual argument out of the pointer VAList
3219 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
3221 // Remember that we legalized the chain.
3222 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3226 LoadSDNode *LD = cast<LoadSDNode>(Node);
3227 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
3228 ? ISD::EXTLOAD : LD->getExtensionType();
3229 Result = DAG.getExtLoad(ExtType, NVT,
3230 LD->getChain(), LD->getBasePtr(),
3231 LD->getSrcValue(), LD->getSrcValueOffset(),
3233 // Remember that we legalized the chain.
3234 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3238 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3239 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3240 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3242 case ISD::SELECT_CC:
3243 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3244 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3245 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3246 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3249 Tmp1 = Node->getOperand(0);
3250 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3251 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3252 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3253 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
3254 TLI.getShiftAmountTy()));
3259 // Zero extend the argument
3260 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3261 // Perform the larger operation, then subtract if needed.
3262 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3263 switch(Node->getOpcode()) {
3268 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3269 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3270 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
3271 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3272 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
3275 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3276 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3277 DAG.getConstant(getSizeInBits(NVT) -
3278 getSizeInBits(VT), NVT));
3282 case ISD::VEXTRACT_VECTOR_ELT:
3283 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
3285 case ISD::EXTRACT_VECTOR_ELT:
3286 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3290 assert(Result.Val && "Didn't set a result!");
3292 // Make sure the result is itself legal.
3293 Result = LegalizeOp(Result);
3295 // Remember that we promoted this!
3296 AddPromotedOperand(Op, Result);
3300 /// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
3301 /// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
3302 /// on the vector type. The return type of this matches the element type of the
3303 /// vector, which may not be legal for the target.
3304 SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
3305 // We know that operand #0 is the Vec vector. If the index is a constant
3306 // or if the invec is a supported hardware type, we can use it. Otherwise,
3307 // lower to a store then an indexed load.
3308 SDOperand Vec = Op.getOperand(0);
3309 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3311 SDNode *InVal = Vec.Val;
3312 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
3313 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
3315 // Figure out if there is a Packed type corresponding to this Vector
3316 // type. If so, convert to the packed type.
3317 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3318 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
3319 // Turn this into a packed extract_vector_elt operation.
3320 Vec = PackVectorOp(Vec, TVT);
3321 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
3322 } else if (NumElems == 1) {
3323 // This must be an access of the only element. Return it.
3324 return PackVectorOp(Vec, EVT);
3325 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
3327 SplitVectorOp(Vec, Lo, Hi);
3328 if (CIdx->getValue() < NumElems/2) {
3332 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3335 // It's now an extract from the appropriate high or low part. Recurse.
3336 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3337 return LowerVEXTRACT_VECTOR_ELT(Op);
3339 // Variable index case for extract element.
3340 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
3341 assert(0 && "unimp!");
3346 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3348 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3349 SDOperand Vector = Op.getOperand(0);
3350 SDOperand Idx = Op.getOperand(1);
3352 // If the target doesn't support this, store the value to a temporary
3353 // stack slot, then LOAD the scalar element back out.
3354 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
3355 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vector, StackPtr, NULL, 0);
3357 // Add the offset to the index.
3358 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3359 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3360 DAG.getConstant(EltSize, Idx.getValueType()));
3361 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3363 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
3367 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3368 /// with condition CC on the current target. This usually involves legalizing
3369 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3370 /// there may be no choice but to create a new SetCC node to represent the
3371 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3372 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3373 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3376 SDOperand Tmp1, Tmp2, Result;
3378 switch (getTypeAction(LHS.getValueType())) {
3380 Tmp1 = LegalizeOp(LHS); // LHS
3381 Tmp2 = LegalizeOp(RHS); // RHS
3384 Tmp1 = PromoteOp(LHS); // LHS
3385 Tmp2 = PromoteOp(RHS); // RHS
3387 // If this is an FP compare, the operands have already been extended.
3388 if (MVT::isInteger(LHS.getValueType())) {
3389 MVT::ValueType VT = LHS.getValueType();
3390 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3392 // Otherwise, we have to insert explicit sign or zero extends. Note
3393 // that we could insert sign extends for ALL conditions, but zero extend
3394 // is cheaper on many machines (an AND instead of two shifts), so prefer
3396 switch (cast<CondCodeSDNode>(CC)->get()) {
3397 default: assert(0 && "Unknown integer comparison!");
3404 // ALL of these operations will work if we either sign or zero extend
3405 // the operands (including the unsigned comparisons!). Zero extend is
3406 // usually a simpler/cheaper operation, so prefer it.
3407 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3408 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3414 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3415 DAG.getValueType(VT));
3416 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3417 DAG.getValueType(VT));
3423 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3424 ExpandOp(LHS, LHSLo, LHSHi);
3425 ExpandOp(RHS, RHSLo, RHSHi);
3426 switch (cast<CondCodeSDNode>(CC)->get()) {
3430 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3431 if (RHSCST->isAllOnesValue()) {
3432 // Comparison to -1.
3433 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3438 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3439 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3440 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3441 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3444 // If this is a comparison of the sign bit, just look at the top part.
3446 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3447 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3448 CST->getValue() == 0) || // X < 0
3449 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3450 CST->isAllOnesValue())) { // X > -1
3456 // FIXME: This generated code sucks.
3457 ISD::CondCode LowCC;
3458 switch (cast<CondCodeSDNode>(CC)->get()) {
3459 default: assert(0 && "Unknown integer setcc!");
3461 case ISD::SETULT: LowCC = ISD::SETULT; break;
3463 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3465 case ISD::SETULE: LowCC = ISD::SETULE; break;
3467 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3470 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3471 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3472 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3474 // NOTE: on targets without efficient SELECT of bools, we can always use
3475 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3476 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3477 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3478 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3479 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3480 Result, Tmp1, Tmp2));
3489 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3490 /// The resultant code need not be legal. Note that SrcOp is the input operand
3491 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3492 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3494 // Create the stack frame object.
3495 SDOperand FIPtr = CreateStackTemporary(DestVT);
3497 // Emit a store to the stack slot.
3498 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
3499 // Result is a load from the stack slot.
3500 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
3503 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3504 // Create a vector sized/aligned stack slot, store the value to element #0,
3505 // then load the whole vector back out.
3506 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3507 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
3509 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
3513 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3514 /// support the operation, but do support the resultant packed vector type.
3515 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3517 // If the only non-undef value is the low element, turn this into a
3518 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3519 unsigned NumElems = Node->getNumOperands();
3520 bool isOnlyLowElement = true;
3521 SDOperand SplatValue = Node->getOperand(0);
3522 std::map<SDOperand, std::vector<unsigned> > Values;
3523 Values[SplatValue].push_back(0);
3524 bool isConstant = true;
3525 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3526 SplatValue.getOpcode() != ISD::UNDEF)
3529 for (unsigned i = 1; i < NumElems; ++i) {
3530 SDOperand V = Node->getOperand(i);
3531 Values[V].push_back(i);
3532 if (V.getOpcode() != ISD::UNDEF)
3533 isOnlyLowElement = false;
3534 if (SplatValue != V)
3535 SplatValue = SDOperand(0,0);
3537 // If this isn't a constant element or an undef, we can't use a constant
3539 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3540 V.getOpcode() != ISD::UNDEF)
3544 if (isOnlyLowElement) {
3545 // If the low element is an undef too, then this whole things is an undef.
3546 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3547 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3548 // Otherwise, turn this into a scalar_to_vector node.
3549 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3550 Node->getOperand(0));
3553 // If all elements are constants, create a load from the constant pool.
3555 MVT::ValueType VT = Node->getValueType(0);
3557 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3558 std::vector<Constant*> CV;
3559 for (unsigned i = 0, e = NumElems; i != e; ++i) {
3560 if (ConstantFPSDNode *V =
3561 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3562 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3563 } else if (ConstantSDNode *V =
3564 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3565 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
3567 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3568 CV.push_back(UndefValue::get(OpNTy));
3571 Constant *CP = ConstantPacked::get(CV);
3572 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3573 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
3576 if (SplatValue.Val) { // Splat of one value?
3577 // Build the shuffle constant vector: <0, 0, 0, 0>
3578 MVT::ValueType MaskVT =
3579 MVT::getIntVectorWithNumElements(NumElems);
3580 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
3581 std::vector<SDOperand> ZeroVec(NumElems, Zero);
3582 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3583 &ZeroVec[0], ZeroVec.size());
3585 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3586 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
3587 // Get the splatted value into the low element of a vector register.
3588 SDOperand LowValVec =
3589 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3591 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3592 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3593 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3598 // If there are only two unique elements, we may be able to turn this into a
3600 if (Values.size() == 2) {
3601 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
3602 MVT::ValueType MaskVT =
3603 MVT::getIntVectorWithNumElements(NumElems);
3604 std::vector<SDOperand> MaskVec(NumElems);
3606 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3607 E = Values.end(); I != E; ++I) {
3608 for (std::vector<unsigned>::iterator II = I->second.begin(),
3609 EE = I->second.end(); II != EE; ++II)
3610 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
3613 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3614 &MaskVec[0], MaskVec.size());
3616 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3617 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
3618 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
3619 SmallVector<SDOperand, 8> Ops;
3620 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3621 E = Values.end(); I != E; ++I) {
3622 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3626 Ops.push_back(ShuffleMask);
3628 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
3629 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
3630 &Ops[0], Ops.size());
3634 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
3635 // aligned object on the stack, store each element into it, then load
3636 // the result as a vector.
3637 MVT::ValueType VT = Node->getValueType(0);
3638 // Create the stack frame object.
3639 SDOperand FIPtr = CreateStackTemporary(VT);
3641 // Emit a store of each element to the stack slot.
3642 SmallVector<SDOperand, 8> Stores;
3643 unsigned TypeByteSize =
3644 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
3645 unsigned VectorSize = MVT::getSizeInBits(VT)/8;
3646 // Store (in the right endianness) the elements to memory.
3647 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3648 // Ignore undef elements.
3649 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3651 unsigned Offset = TypeByteSize*i;
3653 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
3654 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
3656 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
3660 SDOperand StoreChain;
3661 if (!Stores.empty()) // Not all undef elements?
3662 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3663 &Stores[0], Stores.size());
3665 StoreChain = DAG.getEntryNode();
3667 // Result is a load from the stack slot.
3668 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
3671 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
3672 /// specified value type.
3673 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
3674 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3675 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
3676 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
3677 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
3680 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
3681 SDOperand Op, SDOperand Amt,
3682 SDOperand &Lo, SDOperand &Hi) {
3683 // Expand the subcomponents.
3684 SDOperand LHSL, LHSH;
3685 ExpandOp(Op, LHSL, LHSH);
3687 SDOperand Ops[] = { LHSL, LHSH, Amt };
3688 MVT::ValueType VT = LHSL.getValueType();
3689 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
3690 Hi = Lo.getValue(1);
3694 /// ExpandShift - Try to find a clever way to expand this shift operation out to
3695 /// smaller elements. If we can't find a way that is more efficient than a
3696 /// libcall on this target, return false. Otherwise, return true with the
3697 /// low-parts expanded into Lo and Hi.
3698 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3699 SDOperand &Lo, SDOperand &Hi) {
3700 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3701 "This is not a shift!");
3703 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3704 SDOperand ShAmt = LegalizeOp(Amt);
3705 MVT::ValueType ShTy = ShAmt.getValueType();
3706 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3707 unsigned NVTBits = MVT::getSizeInBits(NVT);
3709 // Handle the case when Amt is an immediate. Other cases are currently broken
3710 // and are disabled.
3711 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3712 unsigned Cst = CN->getValue();
3713 // Expand the incoming operand to be shifted, so that we have its parts
3715 ExpandOp(Op, InL, InH);
3719 Lo = DAG.getConstant(0, NVT);
3720 Hi = DAG.getConstant(0, NVT);
3721 } else if (Cst > NVTBits) {
3722 Lo = DAG.getConstant(0, NVT);
3723 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
3724 } else if (Cst == NVTBits) {
3725 Lo = DAG.getConstant(0, NVT);
3728 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
3729 Hi = DAG.getNode(ISD::OR, NVT,
3730 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
3731 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
3736 Lo = DAG.getConstant(0, NVT);
3737 Hi = DAG.getConstant(0, NVT);
3738 } else if (Cst > NVTBits) {
3739 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
3740 Hi = DAG.getConstant(0, NVT);
3741 } else if (Cst == NVTBits) {
3743 Hi = DAG.getConstant(0, NVT);
3745 Lo = DAG.getNode(ISD::OR, NVT,
3746 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3747 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3748 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
3753 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
3754 DAG.getConstant(NVTBits-1, ShTy));
3755 } else if (Cst > NVTBits) {
3756 Lo = DAG.getNode(ISD::SRA, NVT, InH,
3757 DAG.getConstant(Cst-NVTBits, ShTy));
3758 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3759 DAG.getConstant(NVTBits-1, ShTy));
3760 } else if (Cst == NVTBits) {
3762 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3763 DAG.getConstant(NVTBits-1, ShTy));
3765 Lo = DAG.getNode(ISD::OR, NVT,
3766 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3767 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3768 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
3774 // Okay, the shift amount isn't constant. However, if we can tell that it is
3775 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
3776 uint64_t Mask = NVTBits, KnownZero, KnownOne;
3777 TLI.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
3779 // If we know that the high bit of the shift amount is one, then we can do
3780 // this as a couple of simple shifts.
3781 if (KnownOne & Mask) {
3782 // Mask out the high bit, which we know is set.
3783 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
3784 DAG.getConstant(NVTBits-1, Amt.getValueType()));
3786 // Expand the incoming operand to be shifted, so that we have its parts
3788 ExpandOp(Op, InL, InH);
3791 Lo = DAG.getConstant(0, NVT); // Low part is zero.
3792 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
3795 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
3796 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
3799 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
3800 DAG.getConstant(NVTBits-1, Amt.getValueType()));
3801 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
3806 // If we know that the high bit of the shift amount is zero, then we can do
3807 // this as a couple of simple shifts.
3808 if (KnownZero & Mask) {
3810 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
3811 DAG.getConstant(NVTBits, Amt.getValueType()),
3814 // Expand the incoming operand to be shifted, so that we have its parts
3816 ExpandOp(Op, InL, InH);
3819 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
3820 Hi = DAG.getNode(ISD::OR, NVT,
3821 DAG.getNode(ISD::SHL, NVT, InH, Amt),
3822 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
3825 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
3826 Lo = DAG.getNode(ISD::OR, NVT,
3827 DAG.getNode(ISD::SRL, NVT, InL, Amt),
3828 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
3831 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
3832 Lo = DAG.getNode(ISD::OR, NVT,
3833 DAG.getNode(ISD::SRL, NVT, InL, Amt),
3834 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
3843 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
3844 // does not fit into a register, return the lo part and set the hi part to the
3845 // by-reg argument. If it does fit into a single register, return the result
3846 // and leave the Hi part unset.
3847 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3849 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
3850 // The input chain to this libcall is the entry node of the function.
3851 // Legalizing the call will automatically add the previous call to the
3853 SDOperand InChain = DAG.getEntryNode();
3855 TargetLowering::ArgListTy Args;
3856 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3857 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3858 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3859 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3861 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3863 // Splice the libcall in wherever FindInputOutputChains tells us to.
3864 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3865 std::pair<SDOperand,SDOperand> CallInfo =
3866 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3869 // Legalize the call sequence, starting with the chain. This will advance
3870 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
3871 // was added by LowerCallTo (guaranteeing proper serialization of calls).
3872 LegalizeOp(CallInfo.second);
3874 switch (getTypeAction(CallInfo.first.getValueType())) {
3875 default: assert(0 && "Unknown thing");
3877 Result = CallInfo.first;
3880 ExpandOp(CallInfo.first, Result, Hi);
3887 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3888 /// destination type is legal.
3889 SDOperand SelectionDAGLegalize::
3890 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3891 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3892 assert(getTypeAction(Source.getValueType()) == Expand &&
3893 "This is not an expansion!");
3894 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3897 assert(Source.getValueType() == MVT::i64 &&
3898 "This only works for 64-bit -> FP");
3899 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3900 // incoming integer is set. To handle this, we dynamically test to see if
3901 // it is set, and, if so, add a fudge factor.
3903 ExpandOp(Source, Lo, Hi);
3905 // If this is unsigned, and not supported, first perform the conversion to
3906 // signed, then adjust the result if the sign bit is set.
3907 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3908 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3910 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3911 DAG.getConstant(0, Hi.getValueType()),
3913 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3914 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3915 SignSet, Four, Zero);
3916 uint64_t FF = 0x5f800000ULL;
3917 if (TLI.isLittleEndian()) FF <<= 32;
3918 static Constant *FudgeFactor = ConstantInt::get(Type::ULongTy, FF);
3920 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3921 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3922 SDOperand FudgeInReg;
3923 if (DestTy == MVT::f32)
3924 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
3926 assert(DestTy == MVT::f64 && "Unexpected conversion");
3927 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3928 CPIdx, NULL, 0, MVT::f32);
3930 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3933 // Check to see if the target has a custom way to lower this. If so, use it.
3934 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3935 default: assert(0 && "This action not implemented for this operation!");
3936 case TargetLowering::Legal:
3937 case TargetLowering::Expand:
3938 break; // This case is handled below.
3939 case TargetLowering::Custom: {
3940 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3943 return LegalizeOp(NV);
3944 break; // The target decided this was legal after all
3948 // Expand the source, then glue it back together for the call. We must expand
3949 // the source in case it is shared (this pass of legalize must traverse it).
3950 SDOperand SrcLo, SrcHi;
3951 ExpandOp(Source, SrcLo, SrcHi);
3952 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
3954 const char *FnName = 0;
3955 if (DestTy == MVT::f32)
3956 FnName = "__floatdisf";
3958 assert(DestTy == MVT::f64 && "Unknown fp value type!");
3959 FnName = "__floatdidf";
3962 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
3963 SDOperand UnusedHiPart;
3964 return ExpandLibCall(FnName, Source.Val, UnusedHiPart);
3967 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
3968 /// INT_TO_FP operation of the specified operand when the target requests that
3969 /// we expand it. At this point, we know that the result and operand types are
3970 /// legal for the target.
3971 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
3973 MVT::ValueType DestVT) {
3974 if (Op0.getValueType() == MVT::i32) {
3975 // simple 32-bit [signed|unsigned] integer to float/double expansion
3977 // get the stack frame index of a 8 byte buffer
3978 MachineFunction &MF = DAG.getMachineFunction();
3979 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3980 // get address of 8 byte buffer
3981 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3982 // word offset constant for Hi/Lo address computation
3983 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
3984 // set up Hi and Lo (into buffer) address based on endian
3985 SDOperand Hi = StackSlot;
3986 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
3987 if (TLI.isLittleEndian())
3990 // if signed map to unsigned space
3991 SDOperand Op0Mapped;
3993 // constant used to invert sign bit (signed to unsigned mapping)
3994 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
3995 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
3999 // store the lo of the constructed double - based on integer input
4000 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4001 Op0Mapped, Lo, NULL, 0);
4002 // initial hi portion of constructed double
4003 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4004 // store the hi of the constructed double - biased exponent
4005 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
4006 // load the constructed double
4007 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4008 // FP constant to bias correct the final result
4009 SDOperand Bias = DAG.getConstantFP(isSigned ?
4010 BitsToDouble(0x4330000080000000ULL)
4011 : BitsToDouble(0x4330000000000000ULL),
4013 // subtract the bias
4014 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4017 // handle final rounding
4018 if (DestVT == MVT::f64) {
4022 // if f32 then cast to f32
4023 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
4027 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4028 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4030 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4031 DAG.getConstant(0, Op0.getValueType()),
4033 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4034 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4035 SignSet, Four, Zero);
4037 // If the sign bit of the integer is set, the large number will be treated
4038 // as a negative number. To counteract this, the dynamic code adds an
4039 // offset depending on the data type.
4041 switch (Op0.getValueType()) {
4042 default: assert(0 && "Unsupported integer type!");
4043 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4044 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4045 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4046 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4048 if (TLI.isLittleEndian()) FF <<= 32;
4049 static Constant *FudgeFactor = ConstantInt::get(Type::ULongTy, FF);
4051 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4052 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4053 SDOperand FudgeInReg;
4054 if (DestVT == MVT::f32)
4055 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4057 assert(DestVT == MVT::f64 && "Unexpected conversion");
4058 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
4059 DAG.getEntryNode(), CPIdx,
4060 NULL, 0, MVT::f32));
4063 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4066 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4067 /// *INT_TO_FP operation of the specified operand when the target requests that
4068 /// we promote it. At this point, we know that the result and operand types are
4069 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4070 /// operation that takes a larger input.
4071 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4072 MVT::ValueType DestVT,
4074 // First step, figure out the appropriate *INT_TO_FP operation to use.
4075 MVT::ValueType NewInTy = LegalOp.getValueType();
4077 unsigned OpToUse = 0;
4079 // Scan for the appropriate larger type to use.
4081 NewInTy = (MVT::ValueType)(NewInTy+1);
4082 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4084 // If the target supports SINT_TO_FP of this type, use it.
4085 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4087 case TargetLowering::Legal:
4088 if (!TLI.isTypeLegal(NewInTy))
4089 break; // Can't use this datatype.
4091 case TargetLowering::Custom:
4092 OpToUse = ISD::SINT_TO_FP;
4096 if (isSigned) continue;
4098 // If the target supports UINT_TO_FP of this type, use it.
4099 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4101 case TargetLowering::Legal:
4102 if (!TLI.isTypeLegal(NewInTy))
4103 break; // Can't use this datatype.
4105 case TargetLowering::Custom:
4106 OpToUse = ISD::UINT_TO_FP;
4111 // Otherwise, try a larger type.
4114 // Okay, we found the operation and type to use. Zero extend our input to the
4115 // desired type then run the operation on it.
4116 return DAG.getNode(OpToUse, DestVT,
4117 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4121 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4122 /// FP_TO_*INT operation of the specified operand when the target requests that
4123 /// we promote it. At this point, we know that the result and operand types are
4124 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4125 /// operation that returns a larger result.
4126 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4127 MVT::ValueType DestVT,
4129 // First step, figure out the appropriate FP_TO*INT operation to use.
4130 MVT::ValueType NewOutTy = DestVT;
4132 unsigned OpToUse = 0;
4134 // Scan for the appropriate larger type to use.
4136 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4137 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4139 // If the target supports FP_TO_SINT returning this type, use it.
4140 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4142 case TargetLowering::Legal:
4143 if (!TLI.isTypeLegal(NewOutTy))
4144 break; // Can't use this datatype.
4146 case TargetLowering::Custom:
4147 OpToUse = ISD::FP_TO_SINT;
4152 // If the target supports FP_TO_UINT of this type, use it.
4153 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4155 case TargetLowering::Legal:
4156 if (!TLI.isTypeLegal(NewOutTy))
4157 break; // Can't use this datatype.
4159 case TargetLowering::Custom:
4160 OpToUse = ISD::FP_TO_UINT;
4165 // Otherwise, try a larger type.
4168 // Okay, we found the operation and type to use. Truncate the result of the
4169 // extended FP_TO_*INT operation to the desired size.
4170 return DAG.getNode(ISD::TRUNCATE, DestVT,
4171 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4174 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4176 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4177 MVT::ValueType VT = Op.getValueType();
4178 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4179 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4181 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4183 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4184 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4185 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4187 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4188 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4189 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4190 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4191 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4192 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4193 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4194 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4195 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4197 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4198 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4199 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4200 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4201 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4202 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4203 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4204 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4205 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4206 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4207 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4208 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4209 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4210 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4211 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4212 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4213 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4214 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4215 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4216 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4217 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4221 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4223 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4225 default: assert(0 && "Cannot expand this yet!");
4227 static const uint64_t mask[6] = {
4228 0x5555555555555555ULL, 0x3333333333333333ULL,
4229 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4230 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4232 MVT::ValueType VT = Op.getValueType();
4233 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4234 unsigned len = getSizeInBits(VT);
4235 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4236 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4237 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4238 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4239 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4240 DAG.getNode(ISD::AND, VT,
4241 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4246 // for now, we do this:
4247 // x = x | (x >> 1);
4248 // x = x | (x >> 2);
4250 // x = x | (x >>16);
4251 // x = x | (x >>32); // for 64-bit input
4252 // return popcount(~x);
4254 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4255 MVT::ValueType VT = Op.getValueType();
4256 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4257 unsigned len = getSizeInBits(VT);
4258 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4259 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4260 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4262 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4263 return DAG.getNode(ISD::CTPOP, VT, Op);
4266 // for now, we use: { return popcount(~x & (x - 1)); }
4267 // unless the target has ctlz but not ctpop, in which case we use:
4268 // { return 32 - nlz(~x & (x-1)); }
4269 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4270 MVT::ValueType VT = Op.getValueType();
4271 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4272 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4273 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4274 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4275 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4276 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4277 TLI.isOperationLegal(ISD::CTLZ, VT))
4278 return DAG.getNode(ISD::SUB, VT,
4279 DAG.getConstant(getSizeInBits(VT), VT),
4280 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4281 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4286 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4287 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4288 /// LegalizeNodes map is filled in for any results that are not expanded, the
4289 /// ExpandedNodes map is filled in for any results that are expanded, and the
4290 /// Lo/Hi values are returned.
4291 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4292 MVT::ValueType VT = Op.getValueType();
4293 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4294 SDNode *Node = Op.Val;
4295 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4296 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
4297 "Cannot expand FP values!");
4298 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
4299 "Cannot expand to FP value or to larger int value!");
4301 // See if we already expanded it.
4302 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4303 = ExpandedNodes.find(Op);
4304 if (I != ExpandedNodes.end()) {
4305 Lo = I->second.first;
4306 Hi = I->second.second;
4310 switch (Node->getOpcode()) {
4311 case ISD::CopyFromReg:
4312 assert(0 && "CopyFromReg must be legal!");
4315 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
4317 assert(0 && "Do not know how to expand this operator!");
4320 Lo = DAG.getNode(ISD::UNDEF, NVT);
4321 Hi = DAG.getNode(ISD::UNDEF, NVT);
4323 case ISD::Constant: {
4324 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4325 Lo = DAG.getConstant(Cst, NVT);
4326 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4329 case ISD::BUILD_PAIR:
4330 // Return the operands.
4331 Lo = Node->getOperand(0);
4332 Hi = Node->getOperand(1);
4335 case ISD::SIGN_EXTEND_INREG:
4336 ExpandOp(Node->getOperand(0), Lo, Hi);
4337 // sext_inreg the low part if needed.
4338 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4340 // The high part gets the sign extension from the lo-part. This handles
4341 // things like sextinreg V:i64 from i8.
4342 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4343 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4344 TLI.getShiftAmountTy()));
4348 ExpandOp(Node->getOperand(0), Lo, Hi);
4349 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4350 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4356 ExpandOp(Node->getOperand(0), Lo, Hi);
4357 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4358 DAG.getNode(ISD::CTPOP, NVT, Lo),
4359 DAG.getNode(ISD::CTPOP, NVT, Hi));
4360 Hi = DAG.getConstant(0, NVT);
4364 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4365 ExpandOp(Node->getOperand(0), Lo, Hi);
4366 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4367 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4368 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4370 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4371 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4373 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4374 Hi = DAG.getConstant(0, NVT);
4379 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4380 ExpandOp(Node->getOperand(0), Lo, Hi);
4381 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4382 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4383 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4385 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4386 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4388 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4389 Hi = DAG.getConstant(0, NVT);
4394 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4395 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4396 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4397 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4399 // Remember that we legalized the chain.
4400 Hi = LegalizeOp(Hi);
4401 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4402 if (!TLI.isLittleEndian())
4408 LoadSDNode *LD = cast<LoadSDNode>(Node);
4409 SDOperand Ch = LD->getChain(); // Legalize the chain.
4410 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
4411 ISD::LoadExtType ExtType = LD->getExtensionType();
4413 if (ExtType == ISD::NON_EXTLOAD) {
4414 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset());
4416 // Increment the pointer to the other half.
4417 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4418 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4419 getIntPtrConstant(IncrementSize));
4420 // FIXME: This creates a bogus srcvalue!
4421 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset());
4423 // Build a factor node to remember that this load is independent of the
4425 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4428 // Remember that we legalized the chain.
4429 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4430 if (!TLI.isLittleEndian())
4433 MVT::ValueType EVT = LD->getLoadedVT();
4436 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
4437 LD->getSrcValueOffset());
4439 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
4440 LD->getSrcValueOffset(), EVT);
4442 // Remember that we legalized the chain.
4443 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4445 if (ExtType == ISD::SEXTLOAD) {
4446 // The high part is obtained by SRA'ing all but one of the bits of the
4448 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4449 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4450 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4451 } else if (ExtType == ISD::ZEXTLOAD) {
4452 // The high part is just a zero.
4453 Hi = DAG.getConstant(0, NVT);
4454 } else /* if (ExtType == ISD::EXTLOAD) */ {
4455 // The high part is undefined.
4456 Hi = DAG.getNode(ISD::UNDEF, NVT);
4463 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
4464 SDOperand LL, LH, RL, RH;
4465 ExpandOp(Node->getOperand(0), LL, LH);
4466 ExpandOp(Node->getOperand(1), RL, RH);
4467 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4468 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4472 SDOperand LL, LH, RL, RH;
4473 ExpandOp(Node->getOperand(1), LL, LH);
4474 ExpandOp(Node->getOperand(2), RL, RH);
4475 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4476 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4479 case ISD::SELECT_CC: {
4480 SDOperand TL, TH, FL, FH;
4481 ExpandOp(Node->getOperand(2), TL, TH);
4482 ExpandOp(Node->getOperand(3), FL, FH);
4483 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4484 Node->getOperand(1), TL, FL, Node->getOperand(4));
4485 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4486 Node->getOperand(1), TH, FH, Node->getOperand(4));
4489 case ISD::ANY_EXTEND:
4490 // The low part is any extension of the input (which degenerates to a copy).
4491 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4492 // The high part is undefined.
4493 Hi = DAG.getNode(ISD::UNDEF, NVT);
4495 case ISD::SIGN_EXTEND: {
4496 // The low part is just a sign extension of the input (which degenerates to
4498 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4500 // The high part is obtained by SRA'ing all but one of the bits of the lo
4502 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4503 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4504 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4507 case ISD::ZERO_EXTEND:
4508 // The low part is just a zero extension of the input (which degenerates to
4510 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4512 // The high part is just a zero.
4513 Hi = DAG.getConstant(0, NVT);
4516 case ISD::BIT_CONVERT: {
4518 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
4519 // If the target wants to, allow it to lower this itself.
4520 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4521 case Expand: assert(0 && "cannot expand FP!");
4522 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
4523 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
4525 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
4528 // Turn this into a load/store pair by default.
4530 Tmp = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
4532 ExpandOp(Tmp, Lo, Hi);
4536 case ISD::READCYCLECOUNTER:
4537 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
4538 TargetLowering::Custom &&
4539 "Must custom expand ReadCycleCounter");
4540 Lo = TLI.LowerOperation(Op, DAG);
4541 assert(Lo.Val && "Node must be custom expanded!");
4542 Hi = Lo.getValue(1);
4543 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
4544 LegalizeOp(Lo.getValue(2)));
4547 // These operators cannot be expanded directly, emit them as calls to
4548 // library functions.
4549 case ISD::FP_TO_SINT:
4550 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
4552 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4553 case Expand: assert(0 && "cannot expand FP!");
4554 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4555 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4558 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
4560 // Now that the custom expander is done, expand the result, which is still
4563 ExpandOp(Op, Lo, Hi);
4568 if (Node->getOperand(0).getValueType() == MVT::f32)
4569 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
4571 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
4574 case ISD::FP_TO_UINT:
4575 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
4577 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4578 case Expand: assert(0 && "cannot expand FP!");
4579 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4580 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4583 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
4585 // Now that the custom expander is done, expand the result.
4587 ExpandOp(Op, Lo, Hi);
4592 if (Node->getOperand(0).getValueType() == MVT::f32)
4593 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
4595 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
4599 // If the target wants custom lowering, do so.
4600 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4601 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
4602 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
4603 Op = TLI.LowerOperation(Op, DAG);
4605 // Now that the custom expander is done, expand the result, which is
4607 ExpandOp(Op, Lo, Hi);
4612 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
4613 // this X << 1 as X+X.
4614 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
4615 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
4616 TLI.isOperationLegal(ISD::ADDE, NVT)) {
4617 SDOperand LoOps[2], HiOps[3];
4618 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
4619 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
4620 LoOps[1] = LoOps[0];
4621 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
4623 HiOps[1] = HiOps[0];
4624 HiOps[2] = Lo.getValue(1);
4625 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
4630 // If we can emit an efficient shift operation, do so now.
4631 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4634 // If this target supports SHL_PARTS, use it.
4635 TargetLowering::LegalizeAction Action =
4636 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
4637 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4638 Action == TargetLowering::Custom) {
4639 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4643 // Otherwise, emit a libcall.
4644 Lo = ExpandLibCall("__ashldi3", Node, Hi);
4649 // If the target wants custom lowering, do so.
4650 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4651 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
4652 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
4653 Op = TLI.LowerOperation(Op, DAG);
4655 // Now that the custom expander is done, expand the result, which is
4657 ExpandOp(Op, Lo, Hi);
4662 // If we can emit an efficient shift operation, do so now.
4663 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
4666 // If this target supports SRA_PARTS, use it.
4667 TargetLowering::LegalizeAction Action =
4668 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
4669 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4670 Action == TargetLowering::Custom) {
4671 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4675 // Otherwise, emit a libcall.
4676 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
4681 // If the target wants custom lowering, do so.
4682 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4683 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
4684 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
4685 Op = TLI.LowerOperation(Op, DAG);
4687 // Now that the custom expander is done, expand the result, which is
4689 ExpandOp(Op, Lo, Hi);
4694 // If we can emit an efficient shift operation, do so now.
4695 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4698 // If this target supports SRL_PARTS, use it.
4699 TargetLowering::LegalizeAction Action =
4700 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
4701 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4702 Action == TargetLowering::Custom) {
4703 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4707 // Otherwise, emit a libcall.
4708 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
4714 // If the target wants to custom expand this, let them.
4715 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
4716 TargetLowering::Custom) {
4717 Op = TLI.LowerOperation(Op, DAG);
4719 ExpandOp(Op, Lo, Hi);
4724 // Expand the subcomponents.
4725 SDOperand LHSL, LHSH, RHSL, RHSH;
4726 ExpandOp(Node->getOperand(0), LHSL, LHSH);
4727 ExpandOp(Node->getOperand(1), RHSL, RHSH);
4728 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
4729 SDOperand LoOps[2], HiOps[3];
4734 if (Node->getOpcode() == ISD::ADD) {
4735 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
4736 HiOps[2] = Lo.getValue(1);
4737 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
4739 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
4740 HiOps[2] = Lo.getValue(1);
4741 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
4746 // If the target wants to custom expand this, let them.
4747 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
4748 SDOperand New = TLI.LowerOperation(Op, DAG);
4750 ExpandOp(New, Lo, Hi);
4755 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
4756 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
4757 bool UseLibCall = true;
4758 if (HasMULHS || HasMULHU) {
4759 SDOperand LL, LH, RL, RH;
4760 ExpandOp(Node->getOperand(0), LL, LH);
4761 ExpandOp(Node->getOperand(1), RL, RH);
4762 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
4763 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
4764 // extended the sign bit of the low half through the upper half, and if so
4765 // emit a MULHS instead of the alternate sequence that is valid for any
4766 // i64 x i64 multiply.
4768 // is RH an extension of the sign bit of RL?
4769 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
4770 RH.getOperand(1).getOpcode() == ISD::Constant &&
4771 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
4772 // is LH an extension of the sign bit of LL?
4773 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
4774 LH.getOperand(1).getOpcode() == ISD::Constant &&
4775 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
4776 // FIXME: Move this to the dag combiner.
4779 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4781 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
4783 } else if (HasMULHU) {
4785 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4788 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
4789 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
4790 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
4791 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
4792 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
4797 Lo = ExpandLibCall("__muldi3" , Node, Hi);
4800 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
4801 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
4802 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
4803 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
4806 // Make sure the resultant values have been legalized themselves, unless this
4807 // is a type that requires multi-step expansion.
4808 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
4809 Lo = LegalizeOp(Lo);
4810 Hi = LegalizeOp(Hi);
4813 // Remember in a map if the values will be reused later.
4815 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4816 assert(isNew && "Value already expanded?!?");
4819 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
4820 /// two smaller values of MVT::Vector type.
4821 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
4823 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
4824 SDNode *Node = Op.Val;
4825 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
4826 assert(NumElements > 1 && "Cannot split a single element vector!");
4827 unsigned NewNumElts = NumElements/2;
4828 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
4829 SDOperand TypeNode = *(Node->op_end()-1);
4831 // See if we already split it.
4832 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4833 = SplitNodes.find(Op);
4834 if (I != SplitNodes.end()) {
4835 Lo = I->second.first;
4836 Hi = I->second.second;
4840 switch (Node->getOpcode()) {
4845 assert(0 && "Unhandled operation in SplitVectorOp!");
4846 case ISD::VBUILD_VECTOR: {
4847 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
4848 Node->op_begin()+NewNumElts);
4849 LoOps.push_back(NewNumEltsNode);
4850 LoOps.push_back(TypeNode);
4851 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size());
4853 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
4855 HiOps.push_back(NewNumEltsNode);
4856 HiOps.push_back(TypeNode);
4857 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size());
4868 SDOperand LL, LH, RL, RH;
4869 SplitVectorOp(Node->getOperand(0), LL, LH);
4870 SplitVectorOp(Node->getOperand(1), RL, RH);
4872 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
4873 NewNumEltsNode, TypeNode);
4874 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
4875 NewNumEltsNode, TypeNode);
4879 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4880 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4881 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4883 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4884 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
4885 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4886 getIntPtrConstant(IncrementSize));
4887 // FIXME: This creates a bogus srcvalue!
4888 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4890 // Build a factor node to remember that this load is independent of the
4892 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4895 // Remember that we legalized the chain.
4896 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4899 case ISD::VBIT_CONVERT: {
4900 // We know the result is a vector. The input may be either a vector or a
4902 if (Op.getOperand(0).getValueType() != MVT::Vector) {
4903 // Lower to a store/load. FIXME: this could be improved probably.
4904 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
4906 SDOperand St = DAG.getStore(DAG.getEntryNode(),
4907 Op.getOperand(0), Ptr, NULL, 0);
4908 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4909 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0));
4910 SplitVectorOp(St, Lo, Hi);
4912 // If the input is a vector type, we have to either scalarize it, pack it
4913 // or convert it based on whether the input vector type is legal.
4914 SDNode *InVal = Node->getOperand(0).Val;
4916 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
4917 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
4919 // If the input is from a single element vector, scalarize the vector,
4920 // then treat like a scalar.
4921 if (NumElems == 1) {
4922 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT);
4923 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar,
4924 Op.getOperand(1), Op.getOperand(2));
4925 SplitVectorOp(Scalar, Lo, Hi);
4927 // Split the input vector.
4928 SplitVectorOp(Op.getOperand(0), Lo, Hi);
4930 // Convert each of the pieces now.
4931 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo,
4932 NewNumEltsNode, TypeNode);
4933 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi,
4934 NewNumEltsNode, TypeNode);
4941 // Remember in a map if the values will be reused later.
4943 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4944 assert(isNew && "Value already expanded?!?");
4948 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
4949 /// equivalent operation that returns a scalar (e.g. F32) or packed value
4950 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
4951 /// type for the result.
4952 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
4953 MVT::ValueType NewVT) {
4954 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
4955 SDNode *Node = Op.Val;
4957 // See if we already packed it.
4958 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
4959 if (I != PackedNodes.end()) return I->second;
4962 switch (Node->getOpcode()) {
4965 Node->dump(); std::cerr << "\n";
4967 assert(0 && "Unknown vector operation in PackVectorOp!");
4976 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
4978 PackVectorOp(Node->getOperand(0), NewVT),
4979 PackVectorOp(Node->getOperand(1), NewVT));
4982 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
4983 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
4985 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
4986 Result = DAG.getLoad(NewVT, Ch, Ptr, SV->getValue(), SV->getOffset());
4988 // Remember that we legalized the chain.
4989 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4992 case ISD::VBUILD_VECTOR:
4993 if (Node->getOperand(0).getValueType() == NewVT) {
4994 // Returning a scalar?
4995 Result = Node->getOperand(0);
4997 // Returning a BUILD_VECTOR?
4999 // If all elements of the build_vector are undefs, return an undef.
5000 bool AllUndef = true;
5001 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i)
5002 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) {
5007 Result = DAG.getNode(ISD::UNDEF, NewVT);
5009 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(),
5010 Node->getNumOperands()-2);
5014 case ISD::VINSERT_VECTOR_ELT:
5015 if (!MVT::isVector(NewVT)) {
5016 // Returning a scalar? Must be the inserted element.
5017 Result = Node->getOperand(1);
5019 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
5020 PackVectorOp(Node->getOperand(0), NewVT),
5021 Node->getOperand(1), Node->getOperand(2));
5024 case ISD::VVECTOR_SHUFFLE:
5025 if (!MVT::isVector(NewVT)) {
5026 // Returning a scalar? Figure out if it is the LHS or RHS and return it.
5027 SDOperand EltNum = Node->getOperand(2).getOperand(0);
5028 if (cast<ConstantSDNode>(EltNum)->getValue())
5029 Result = PackVectorOp(Node->getOperand(1), NewVT);
5031 Result = PackVectorOp(Node->getOperand(0), NewVT);
5033 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index
5034 // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
5035 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
5036 Node->getOperand(2).Val->op_end()-2);
5037 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
5038 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT,
5039 Node->getOperand(2).Val->op_begin(),
5040 Node->getOperand(2).Val->getNumOperands()-2);
5042 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
5043 PackVectorOp(Node->getOperand(0), NewVT),
5044 PackVectorOp(Node->getOperand(1), NewVT), BV);
5047 case ISD::VBIT_CONVERT:
5048 if (Op.getOperand(0).getValueType() != MVT::Vector)
5049 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
5051 // If the input is a vector type, we have to either scalarize it, pack it
5052 // or convert it based on whether the input vector type is legal.
5053 SDNode *InVal = Node->getOperand(0).Val;
5055 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
5056 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
5058 // Figure out if there is a Packed type corresponding to this Vector
5059 // type. If so, convert to the packed type.
5060 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
5061 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
5062 // Turn this into a bit convert of the packed input.
5063 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5064 PackVectorOp(Node->getOperand(0), TVT));
5066 } else if (NumElems == 1) {
5067 // Turn this into a bit convert of the scalar input.
5068 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5069 PackVectorOp(Node->getOperand(0), EVT));
5073 assert(0 && "Cast from unsupported vector type not implemented yet!");
5078 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
5079 PackVectorOp(Op.getOperand(1), NewVT),
5080 PackVectorOp(Op.getOperand(2), NewVT));
5084 if (TLI.isTypeLegal(NewVT))
5085 Result = LegalizeOp(Result);
5086 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
5087 assert(isNew && "Value already packed?");
5092 // SelectionDAG::Legalize - This is the entry point for the file.
5094 void SelectionDAG::Legalize() {
5095 if (ViewLegalizeDAGs) viewGraph();
5097 /// run - This is the main entry point to this class.
5099 SelectionDAGLegalize(*this).LegalizeDAG();