1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/Constants.h"
27 #include "llvm/DerivedTypes.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/SmallPtrSet.h"
39 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
40 cl::desc("Pop up a window to show dags before legalize"));
42 static const bool ViewLegalizeDAGs = 0;
45 //===----------------------------------------------------------------------===//
46 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
47 /// hacks on it until the target machine can handle it. This involves
48 /// eliminating value sizes the machine cannot handle (promoting small sizes to
49 /// large sizes or splitting up large values into small values) as well as
50 /// eliminating operations the machine cannot handle.
52 /// This code also does a small amount of optimization and recognition of idioms
53 /// as part of its processing. For example, if a target does not support a
54 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
55 /// will attempt merge setcc and brc instructions into brcc's.
58 class VISIBILITY_HIDDEN SelectionDAGLegalize {
62 // Libcall insertion helpers.
64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
65 /// legalized. We use this to ensure that calls are properly serialized
66 /// against each other, including inserted libcalls.
67 SDOperand LastCALLSEQ_END;
69 /// IsLegalizingCall - This member is used *only* for purposes of providing
70 /// helpful assertions that a libcall isn't created while another call is
71 /// being legalized (which could lead to non-serialized call sequences).
72 bool IsLegalizingCall;
75 Legal, // The target natively supports this operation.
76 Promote, // This operation should be executed in a larger type.
77 Expand // Try to expand this to other ops, otherwise use a libcall.
80 /// ValueTypeActions - This is a bitvector that contains two bits for each
81 /// value type, where the two bits correspond to the LegalizeAction enum.
82 /// This can be queried with "getTypeAction(VT)".
83 TargetLowering::ValueTypeActionImpl ValueTypeActions;
85 /// LegalizedNodes - For nodes that are of legal width, and that have more
86 /// than one use, this map indicates what regularized operand to use. This
87 /// allows us to avoid legalizing the same thing more than once.
88 DenseMap<SDOperand, SDOperand> LegalizedNodes;
90 /// PromotedNodes - For nodes that are below legal width, and that have more
91 /// than one use, this map indicates what promoted value to use. This allows
92 /// us to avoid promoting the same thing more than once.
93 DenseMap<SDOperand, SDOperand> PromotedNodes;
95 /// ExpandedNodes - For nodes that need to be expanded this map indicates
96 /// which which operands are the expanded version of the input. This allows
97 /// us to avoid expanding the same node more than once.
98 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
100 /// SplitNodes - For vector nodes that need to be split, this map indicates
101 /// which which operands are the split version of the input. This allows us
102 /// to avoid splitting the same node more than once.
103 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
105 /// ScalarizedNodes - For nodes that need to be converted from vector types to
106 /// scalar types, this contains the mapping of ones we have already
107 /// processed to the result.
108 std::map<SDOperand, SDOperand> ScalarizedNodes;
110 void AddLegalizedOperand(SDOperand From, SDOperand To) {
111 LegalizedNodes.insert(std::make_pair(From, To));
112 // If someone requests legalization of the new node, return itself.
114 LegalizedNodes.insert(std::make_pair(To, To));
116 void AddPromotedOperand(SDOperand From, SDOperand To) {
117 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
118 assert(isNew && "Got into the map somehow?");
119 // If someone requests legalization of the new node, return itself.
120 LegalizedNodes.insert(std::make_pair(To, To));
125 SelectionDAGLegalize(SelectionDAG &DAG);
127 /// getTypeAction - Return how we should legalize values of this type, either
128 /// it is already legal or we need to expand it into multiple registers of
129 /// smaller integer type, or we need to promote it to a larger type.
130 LegalizeAction getTypeAction(MVT::ValueType VT) const {
131 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
134 /// isTypeLegal - Return true if this type is legal on this target.
136 bool isTypeLegal(MVT::ValueType VT) const {
137 return getTypeAction(VT) == Legal;
143 /// HandleOp - Legalize, Promote, or Expand the specified operand as
144 /// appropriate for its type.
145 void HandleOp(SDOperand Op);
147 /// LegalizeOp - We know that the specified value has a legal type.
148 /// Recursively ensure that the operands have legal types, then return the
150 SDOperand LegalizeOp(SDOperand O);
152 /// UnrollVectorOp - We know that the given vector has a legal type, however
153 /// the operation it performs is not legal and is an operation that we have
154 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
155 /// operating on each element individually.
156 SDOperand UnrollVectorOp(SDOperand O);
158 /// PromoteOp - Given an operation that produces a value in an invalid type,
159 /// promote it to compute the value into a larger type. The produced value
160 /// will have the correct bits for the low portion of the register, but no
161 /// guarantee is made about the top bits: it may be zero, sign-extended, or
163 SDOperand PromoteOp(SDOperand O);
165 /// ExpandOp - Expand the specified SDOperand into its two component pieces
166 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
167 /// the LegalizeNodes map is filled in for any results that are not expanded,
168 /// the ExpandedNodes map is filled in for any results that are expanded, and
169 /// the Lo/Hi values are returned. This applies to integer types and Vector
171 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
173 /// SplitVectorOp - Given an operand of vector type, break it down into
174 /// two smaller values.
175 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
177 /// ScalarizeVectorOp - Given an operand of single-element vector type
178 /// (e.g. v1f32), convert it into the equivalent operation that returns a
179 /// scalar (e.g. f32) value.
180 SDOperand ScalarizeVectorOp(SDOperand O);
182 /// isShuffleLegal - Return true if a vector shuffle is legal with the
183 /// specified mask and type. Targets can specify exactly which masks they
184 /// support and the code generator is tasked with not creating illegal masks.
186 /// Note that this will also return true for shuffles that are promoted to a
189 /// If this is a legal shuffle, this method returns the (possibly promoted)
190 /// build_vector Mask. If it's not a legal shuffle, it returns null.
191 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
193 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
194 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
196 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
198 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
200 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
203 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT,
204 MVT::ValueType DestVT);
205 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
206 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
207 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
209 MVT::ValueType DestVT);
210 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
212 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
215 SDOperand ExpandBSWAP(SDOperand Op);
216 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
217 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
218 SDOperand &Lo, SDOperand &Hi);
219 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
220 SDOperand &Lo, SDOperand &Hi);
222 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
223 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
227 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
228 /// specified mask and type. Targets can specify exactly which masks they
229 /// support and the code generator is tasked with not creating illegal masks.
231 /// Note that this will also return true for shuffles that are promoted to a
233 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
234 SDOperand Mask) const {
235 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
237 case TargetLowering::Legal:
238 case TargetLowering::Custom:
240 case TargetLowering::Promote: {
241 // If this is promoted to a different type, convert the shuffle mask and
242 // ask if it is legal in the promoted type!
243 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
245 // If we changed # elements, change the shuffle mask.
246 unsigned NumEltsGrowth =
247 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
248 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
249 if (NumEltsGrowth > 1) {
250 // Renumber the elements.
251 SmallVector<SDOperand, 8> Ops;
252 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
253 SDOperand InOp = Mask.getOperand(i);
254 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
255 if (InOp.getOpcode() == ISD::UNDEF)
256 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
258 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
259 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
263 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
269 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
272 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
273 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
274 ValueTypeActions(TLI.getValueTypeActions()) {
275 assert(MVT::LAST_VALUETYPE <= 32 &&
276 "Too many value types for ValueTypeActions to hold!");
279 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
280 /// contains all of a nodes operands before it contains the node.
281 static void ComputeTopDownOrdering(SelectionDAG &DAG,
282 SmallVector<SDNode*, 64> &Order) {
284 DenseMap<SDNode*, unsigned> Visited;
285 std::vector<SDNode*> Worklist;
286 Worklist.reserve(128);
288 // Compute ordering from all of the leaves in the graphs, those (like the
289 // entry node) that have no operands.
290 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
291 E = DAG.allnodes_end(); I != E; ++I) {
292 if (I->getNumOperands() == 0) {
294 Worklist.push_back(I);
298 while (!Worklist.empty()) {
299 SDNode *N = Worklist.back();
302 if (++Visited[N] != N->getNumOperands())
303 continue; // Haven't visited all operands yet
307 // Now that we have N in, add anything that uses it if all of their operands
309 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
311 Worklist.push_back(*UI);
314 assert(Order.size() == Visited.size() &&
316 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
317 "Error: DAG is cyclic!");
321 void SelectionDAGLegalize::LegalizeDAG() {
322 LastCALLSEQ_END = DAG.getEntryNode();
323 IsLegalizingCall = false;
325 // The legalize process is inherently a bottom-up recursive process (users
326 // legalize their uses before themselves). Given infinite stack space, we
327 // could just start legalizing on the root and traverse the whole graph. In
328 // practice however, this causes us to run out of stack space on large basic
329 // blocks. To avoid this problem, compute an ordering of the nodes where each
330 // node is only legalized after all of its operands are legalized.
331 SmallVector<SDNode*, 64> Order;
332 ComputeTopDownOrdering(DAG, Order);
334 for (unsigned i = 0, e = Order.size(); i != e; ++i)
335 HandleOp(SDOperand(Order[i], 0));
337 // Finally, it's possible the root changed. Get the new root.
338 SDOperand OldRoot = DAG.getRoot();
339 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
340 DAG.setRoot(LegalizedNodes[OldRoot]);
342 ExpandedNodes.clear();
343 LegalizedNodes.clear();
344 PromotedNodes.clear();
346 ScalarizedNodes.clear();
348 // Remove dead nodes now.
349 DAG.RemoveDeadNodes();
353 /// FindCallEndFromCallStart - Given a chained node that is part of a call
354 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
355 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
356 if (Node->getOpcode() == ISD::CALLSEQ_END)
358 if (Node->use_empty())
359 return 0; // No CallSeqEnd
361 // The chain is usually at the end.
362 SDOperand TheChain(Node, Node->getNumValues()-1);
363 if (TheChain.getValueType() != MVT::Other) {
364 // Sometimes it's at the beginning.
365 TheChain = SDOperand(Node, 0);
366 if (TheChain.getValueType() != MVT::Other) {
367 // Otherwise, hunt for it.
368 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
369 if (Node->getValueType(i) == MVT::Other) {
370 TheChain = SDOperand(Node, i);
374 // Otherwise, we walked into a node without a chain.
375 if (TheChain.getValueType() != MVT::Other)
380 for (SDNode::use_iterator UI = Node->use_begin(),
381 E = Node->use_end(); UI != E; ++UI) {
383 // Make sure to only follow users of our token chain.
385 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
386 if (User->getOperand(i) == TheChain)
387 if (SDNode *Result = FindCallEndFromCallStart(User))
393 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
394 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
395 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
396 assert(Node && "Didn't find callseq_start for a call??");
397 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
399 assert(Node->getOperand(0).getValueType() == MVT::Other &&
400 "Node doesn't have a token chain argument!");
401 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
404 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
405 /// see if any uses can reach Dest. If no dest operands can get to dest,
406 /// legalize them, legalize ourself, and return false, otherwise, return true.
408 /// Keep track of the nodes we fine that actually do lead to Dest in
409 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
411 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
412 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
413 if (N == Dest) return true; // N certainly leads to Dest :)
415 // If we've already processed this node and it does lead to Dest, there is no
416 // need to reprocess it.
417 if (NodesLeadingTo.count(N)) return true;
419 // If the first result of this node has been already legalized, then it cannot
421 switch (getTypeAction(N->getValueType(0))) {
423 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
426 if (PromotedNodes.count(SDOperand(N, 0))) return false;
429 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
433 // Okay, this node has not already been legalized. Check and legalize all
434 // operands. If none lead to Dest, then we can legalize this node.
435 bool OperandsLeadToDest = false;
436 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
437 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
438 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
440 if (OperandsLeadToDest) {
441 NodesLeadingTo.insert(N);
445 // Okay, this node looks safe, legalize it and return false.
446 HandleOp(SDOperand(N, 0));
450 /// HandleOp - Legalize, Promote, or Expand the specified operand as
451 /// appropriate for its type.
452 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
453 MVT::ValueType VT = Op.getValueType();
454 switch (getTypeAction(VT)) {
455 default: assert(0 && "Bad type action!");
456 case Legal: (void)LegalizeOp(Op); break;
457 case Promote: (void)PromoteOp(Op); break;
459 if (!MVT::isVector(VT)) {
460 // If this is an illegal scalar, expand it into its two component
463 if (Op.getOpcode() == ISD::TargetConstant)
464 break; // Allow illegal target nodes.
466 } else if (MVT::getVectorNumElements(VT) == 1) {
467 // If this is an illegal single element vector, convert it to a
469 (void)ScalarizeVectorOp(Op);
471 // Otherwise, this is an illegal multiple element vector.
472 // Split it in half and legalize both parts.
474 SplitVectorOp(Op, X, Y);
480 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
481 /// a load from the constant pool.
482 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
483 SelectionDAG &DAG, TargetLowering &TLI) {
486 // If a FP immediate is precise when represented as a float and if the
487 // target can do an extending load from float to double, we put it into
488 // the constant pool as a float, even if it's is statically typed as a
490 MVT::ValueType VT = CFP->getValueType(0);
491 bool isDouble = VT == MVT::f64;
492 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
495 if (VT!=MVT::f64 && VT!=MVT::f32)
496 assert(0 && "Invalid type expansion");
497 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(),
498 isDouble ? MVT::i64 : MVT::i32);
501 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) &&
502 // Only do this if the target has a native EXTLOAD instruction from f32.
503 // Do not try to be clever about long doubles (so far)
504 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
505 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
510 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
512 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
513 CPIdx, &PseudoSourceValue::CPRel, 0, MVT::f32);
515 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
516 &PseudoSourceValue::CPRel, 0);
521 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
524 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
525 SelectionDAG &DAG, TargetLowering &TLI) {
526 MVT::ValueType VT = Node->getValueType(0);
527 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
528 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
529 "fcopysign expansion only supported for f32 and f64");
530 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
532 // First get the sign bit of second operand.
533 SDOperand Mask1 = (SrcVT == MVT::f64)
534 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
535 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
536 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
537 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
538 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
539 // Shift right or sign-extend it if the two operands have different types.
540 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
542 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
543 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
544 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
545 } else if (SizeDiff < 0)
546 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
548 // Clear the sign bit of first operand.
549 SDOperand Mask2 = (VT == MVT::f64)
550 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
551 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
552 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
553 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
554 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
556 // Or the value with the sign bit.
557 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
561 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
563 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
564 TargetLowering &TLI) {
565 SDOperand Chain = ST->getChain();
566 SDOperand Ptr = ST->getBasePtr();
567 SDOperand Val = ST->getValue();
568 MVT::ValueType VT = Val.getValueType();
569 int Alignment = ST->getAlignment();
570 int SVOffset = ST->getSrcValueOffset();
571 if (MVT::isFloatingPoint(ST->getMemoryVT())) {
572 // Expand to a bitconvert of the value to the integer type of the
573 // same size, then a (misaligned) int store.
574 MVT::ValueType intVT;
577 else if (VT==MVT::f32)
580 assert(0 && "Unaligned load of unsupported floating point type");
582 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
583 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
584 SVOffset, ST->isVolatile(), Alignment);
586 assert(MVT::isInteger(ST->getMemoryVT()) &&
587 "Unaligned store of unknown type.");
588 // Get the half-size VT
589 MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1;
590 int NumBits = MVT::getSizeInBits(NewStoredVT);
591 int IncrementSize = NumBits / 8;
593 // Divide the stored value in two parts.
594 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
596 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
598 // Store the two parts
599 SDOperand Store1, Store2;
600 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
601 ST->getSrcValue(), SVOffset, NewStoredVT,
602 ST->isVolatile(), Alignment);
603 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
604 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
605 Alignment = MinAlign(Alignment, IncrementSize);
606 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
607 ST->getSrcValue(), SVOffset + IncrementSize,
608 NewStoredVT, ST->isVolatile(), Alignment);
610 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
613 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
615 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
616 TargetLowering &TLI) {
617 int SVOffset = LD->getSrcValueOffset();
618 SDOperand Chain = LD->getChain();
619 SDOperand Ptr = LD->getBasePtr();
620 MVT::ValueType VT = LD->getValueType(0);
621 MVT::ValueType LoadedVT = LD->getMemoryVT();
622 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT)) {
623 // Expand to a (misaligned) integer load of the same size,
624 // then bitconvert to floating point.
625 MVT::ValueType intVT;
626 if (LoadedVT == MVT::f64)
628 else if (LoadedVT == MVT::f32)
631 assert(0 && "Unaligned load of unsupported floating point type");
633 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
634 SVOffset, LD->isVolatile(),
636 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
638 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
640 SDOperand Ops[] = { Result, Chain };
641 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
644 assert((MVT::isInteger(LoadedVT) || MVT::isVector(LoadedVT)) &&
645 "Unaligned load of unsupported type.");
647 // Compute the new VT that is half the size of the old one. We either have an
648 // integer MVT or we have a vector MVT.
649 unsigned NumBits = MVT::getSizeInBits(LoadedVT);
650 MVT::ValueType NewLoadedVT;
651 if (!MVT::isVector(LoadedVT)) {
652 NewLoadedVT = MVT::getIntegerType(NumBits/2);
654 // FIXME: This is not right for <1 x anything> it is also not right for
655 // non-power-of-two vectors.
656 NewLoadedVT = MVT::getVectorType(MVT::getVectorElementType(LoadedVT),
657 MVT::getVectorNumElements(LoadedVT)/2);
661 unsigned Alignment = LD->getAlignment();
662 unsigned IncrementSize = NumBits / 8;
663 ISD::LoadExtType HiExtType = LD->getExtensionType();
665 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
666 if (HiExtType == ISD::NON_EXTLOAD)
667 HiExtType = ISD::ZEXTLOAD;
669 // Load the value in two parts
671 if (TLI.isLittleEndian()) {
672 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
673 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
674 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
675 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
676 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
677 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
678 MinAlign(Alignment, IncrementSize));
680 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
681 NewLoadedVT,LD->isVolatile(), Alignment);
682 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
683 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
684 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
685 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
686 MinAlign(Alignment, IncrementSize));
689 // aggregate the two parts
690 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
691 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
692 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
694 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
697 SDOperand Ops[] = { Result, TF };
698 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
701 /// UnrollVectorOp - We know that the given vector has a legal type, however
702 /// the operation it performs is not legal and is an operation that we have
703 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
704 /// operating on each element individually.
705 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
706 MVT::ValueType VT = Op.getValueType();
707 assert(isTypeLegal(VT) &&
708 "Caller should expand or promote operands that are not legal!");
709 assert(Op.Val->getNumValues() == 1 &&
710 "Can't unroll a vector with multiple results!");
711 unsigned NE = MVT::getVectorNumElements(VT);
712 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
714 SmallVector<SDOperand, 8> Scalars;
715 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
716 for (unsigned i = 0; i != NE; ++i) {
717 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
718 SDOperand Operand = Op.getOperand(j);
719 MVT::ValueType OperandVT = Operand.getValueType();
720 if (MVT::isVector(OperandVT)) {
721 // A vector operand; extract a single element.
722 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
723 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
726 DAG.getConstant(i, MVT::i32));
728 // A scalar operand; just use it as is.
729 Operands[j] = Operand;
732 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
733 &Operands[0], Operands.size()));
736 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
739 /// GetFPLibCall - Return the right libcall for the given floating point type.
740 static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
741 RTLIB::Libcall Call_F32,
742 RTLIB::Libcall Call_F64,
743 RTLIB::Libcall Call_F80,
744 RTLIB::Libcall Call_PPCF128) {
746 VT == MVT::f32 ? Call_F32 :
747 VT == MVT::f64 ? Call_F64 :
748 VT == MVT::f80 ? Call_F80 :
749 VT == MVT::ppcf128 ? Call_PPCF128 :
750 RTLIB::UNKNOWN_LIBCALL;
753 /// LegalizeOp - We know that the specified value has a legal type, and
754 /// that its operands are legal. Now ensure that the operation itself
755 /// is legal, recursively ensuring that the operands' operations remain
757 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
758 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
761 assert(isTypeLegal(Op.getValueType()) &&
762 "Caller should expand or promote operands that are not legal!");
763 SDNode *Node = Op.Val;
765 // If this operation defines any values that cannot be represented in a
766 // register on this target, make sure to expand or promote them.
767 if (Node->getNumValues() > 1) {
768 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
769 if (getTypeAction(Node->getValueType(i)) != Legal) {
770 HandleOp(Op.getValue(i));
771 assert(LegalizedNodes.count(Op) &&
772 "Handling didn't add legal operands!");
773 return LegalizedNodes[Op];
777 // Note that LegalizeOp may be reentered even from single-use nodes, which
778 // means that we always must cache transformed nodes.
779 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
780 if (I != LegalizedNodes.end()) return I->second;
782 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
783 SDOperand Result = Op;
784 bool isCustom = false;
786 switch (Node->getOpcode()) {
787 case ISD::FrameIndex:
788 case ISD::EntryToken:
790 case ISD::BasicBlock:
791 case ISD::TargetFrameIndex:
792 case ISD::TargetJumpTable:
793 case ISD::TargetConstant:
794 case ISD::TargetConstantFP:
795 case ISD::TargetConstantPool:
796 case ISD::TargetGlobalAddress:
797 case ISD::TargetGlobalTLSAddress:
798 case ISD::TargetExternalSymbol:
801 case ISD::MEMOPERAND:
804 // Primitives must all be legal.
805 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
806 "This must be legal!");
809 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
810 // If this is a target node, legalize it by legalizing the operands then
811 // passing it through.
812 SmallVector<SDOperand, 8> Ops;
813 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
814 Ops.push_back(LegalizeOp(Node->getOperand(i)));
816 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
818 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
819 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
820 return Result.getValue(Op.ResNo);
822 // Otherwise this is an unhandled builtin node. splat.
824 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
826 assert(0 && "Do not know how to legalize this operator!");
828 case ISD::GLOBAL_OFFSET_TABLE:
829 case ISD::GlobalAddress:
830 case ISD::GlobalTLSAddress:
831 case ISD::ExternalSymbol:
832 case ISD::ConstantPool:
833 case ISD::JumpTable: // Nothing to do.
834 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
835 default: assert(0 && "This action is not supported yet!");
836 case TargetLowering::Custom:
837 Tmp1 = TLI.LowerOperation(Op, DAG);
838 if (Tmp1.Val) Result = Tmp1;
839 // FALLTHROUGH if the target doesn't want to lower this op after all.
840 case TargetLowering::Legal:
845 case ISD::RETURNADDR:
846 // The only option for these nodes is to custom lower them. If the target
847 // does not custom lower them, then return zero.
848 Tmp1 = TLI.LowerOperation(Op, DAG);
852 Result = DAG.getConstant(0, TLI.getPointerTy());
854 case ISD::FRAME_TO_ARGS_OFFSET: {
855 MVT::ValueType VT = Node->getValueType(0);
856 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
857 default: assert(0 && "This action is not supported yet!");
858 case TargetLowering::Custom:
859 Result = TLI.LowerOperation(Op, DAG);
860 if (Result.Val) break;
862 case TargetLowering::Legal:
863 Result = DAG.getConstant(0, VT);
868 case ISD::EXCEPTIONADDR: {
869 Tmp1 = LegalizeOp(Node->getOperand(0));
870 MVT::ValueType VT = Node->getValueType(0);
871 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
872 default: assert(0 && "This action is not supported yet!");
873 case TargetLowering::Expand: {
874 unsigned Reg = TLI.getExceptionAddressRegister();
875 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
878 case TargetLowering::Custom:
879 Result = TLI.LowerOperation(Op, DAG);
880 if (Result.Val) break;
882 case TargetLowering::Legal: {
883 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
884 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
890 if (Result.Val->getNumValues() == 1) break;
892 assert(Result.Val->getNumValues() == 2 &&
893 "Cannot return more than two values!");
895 // Since we produced two values, make sure to remember that we
896 // legalized both of them.
897 Tmp1 = LegalizeOp(Result);
898 Tmp2 = LegalizeOp(Result.getValue(1));
899 AddLegalizedOperand(Op.getValue(0), Tmp1);
900 AddLegalizedOperand(Op.getValue(1), Tmp2);
901 return Op.ResNo ? Tmp2 : Tmp1;
902 case ISD::EHSELECTION: {
903 Tmp1 = LegalizeOp(Node->getOperand(0));
904 Tmp2 = LegalizeOp(Node->getOperand(1));
905 MVT::ValueType VT = Node->getValueType(0);
906 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
907 default: assert(0 && "This action is not supported yet!");
908 case TargetLowering::Expand: {
909 unsigned Reg = TLI.getExceptionSelectorRegister();
910 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
913 case TargetLowering::Custom:
914 Result = TLI.LowerOperation(Op, DAG);
915 if (Result.Val) break;
917 case TargetLowering::Legal: {
918 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
919 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
925 if (Result.Val->getNumValues() == 1) break;
927 assert(Result.Val->getNumValues() == 2 &&
928 "Cannot return more than two values!");
930 // Since we produced two values, make sure to remember that we
931 // legalized both of them.
932 Tmp1 = LegalizeOp(Result);
933 Tmp2 = LegalizeOp(Result.getValue(1));
934 AddLegalizedOperand(Op.getValue(0), Tmp1);
935 AddLegalizedOperand(Op.getValue(1), Tmp2);
936 return Op.ResNo ? Tmp2 : Tmp1;
937 case ISD::EH_RETURN: {
938 MVT::ValueType VT = Node->getValueType(0);
939 // The only "good" option for this node is to custom lower it.
940 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
941 default: assert(0 && "This action is not supported at all!");
942 case TargetLowering::Custom:
943 Result = TLI.LowerOperation(Op, DAG);
944 if (Result.Val) break;
946 case TargetLowering::Legal:
947 // Target does not know, how to lower this, lower to noop
948 Result = LegalizeOp(Node->getOperand(0));
953 case ISD::AssertSext:
954 case ISD::AssertZext:
955 Tmp1 = LegalizeOp(Node->getOperand(0));
956 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
958 case ISD::MERGE_VALUES:
959 // Legalize eliminates MERGE_VALUES nodes.
960 Result = Node->getOperand(Op.ResNo);
962 case ISD::CopyFromReg:
963 Tmp1 = LegalizeOp(Node->getOperand(0));
964 Result = Op.getValue(0);
965 if (Node->getNumValues() == 2) {
966 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
968 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
969 if (Node->getNumOperands() == 3) {
970 Tmp2 = LegalizeOp(Node->getOperand(2));
971 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
973 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
975 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
977 // Since CopyFromReg produces two values, make sure to remember that we
978 // legalized both of them.
979 AddLegalizedOperand(Op.getValue(0), Result);
980 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
981 return Result.getValue(Op.ResNo);
983 MVT::ValueType VT = Op.getValueType();
984 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
985 default: assert(0 && "This action is not supported yet!");
986 case TargetLowering::Expand:
987 if (MVT::isInteger(VT))
988 Result = DAG.getConstant(0, VT);
989 else if (MVT::isFloatingPoint(VT))
990 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
993 assert(0 && "Unknown value type!");
995 case TargetLowering::Legal:
1001 case ISD::INTRINSIC_W_CHAIN:
1002 case ISD::INTRINSIC_WO_CHAIN:
1003 case ISD::INTRINSIC_VOID: {
1004 SmallVector<SDOperand, 8> Ops;
1005 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1006 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1007 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1009 // Allow the target to custom lower its intrinsics if it wants to.
1010 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1011 TargetLowering::Custom) {
1012 Tmp3 = TLI.LowerOperation(Result, DAG);
1013 if (Tmp3.Val) Result = Tmp3;
1016 if (Result.Val->getNumValues() == 1) break;
1018 // Must have return value and chain result.
1019 assert(Result.Val->getNumValues() == 2 &&
1020 "Cannot return more than two values!");
1022 // Since loads produce two values, make sure to remember that we
1023 // legalized both of them.
1024 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1025 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1026 return Result.getValue(Op.ResNo);
1030 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
1031 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1033 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
1034 case TargetLowering::Promote:
1035 default: assert(0 && "This action is not supported yet!");
1036 case TargetLowering::Expand: {
1037 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1038 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1039 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
1041 if (MMI && (useDEBUG_LOC || useLABEL)) {
1042 const std::string &FName =
1043 cast<StringSDNode>(Node->getOperand(3))->getValue();
1044 const std::string &DirName =
1045 cast<StringSDNode>(Node->getOperand(4))->getValue();
1046 unsigned SrcFile = MMI->RecordSource(DirName, FName);
1048 SmallVector<SDOperand, 8> Ops;
1049 Ops.push_back(Tmp1); // chain
1050 SDOperand LineOp = Node->getOperand(1);
1051 SDOperand ColOp = Node->getOperand(2);
1054 Ops.push_back(LineOp); // line #
1055 Ops.push_back(ColOp); // col #
1056 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1057 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1059 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
1060 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
1061 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
1062 Ops.push_back(DAG.getConstant(ID, MVT::i32));
1063 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label
1064 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size());
1067 Result = Tmp1; // chain
1071 case TargetLowering::Legal:
1072 if (Tmp1 != Node->getOperand(0) ||
1073 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1074 SmallVector<SDOperand, 8> Ops;
1075 Ops.push_back(Tmp1);
1076 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1077 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1078 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1080 // Otherwise promote them.
1081 Ops.push_back(PromoteOp(Node->getOperand(1)));
1082 Ops.push_back(PromoteOp(Node->getOperand(2)));
1084 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1085 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1086 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1092 case ISD::DEBUG_LOC:
1093 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1094 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1095 default: assert(0 && "This action is not supported yet!");
1096 case TargetLowering::Legal:
1097 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1098 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1099 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1100 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1101 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1107 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!");
1108 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1109 default: assert(0 && "This action is not supported yet!");
1110 case TargetLowering::Legal:
1111 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1112 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1113 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand.
1114 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1116 case TargetLowering::Expand:
1117 Result = LegalizeOp(Node->getOperand(0));
1122 case ISD::Constant: {
1123 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1125 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1127 // We know we don't need to expand constants here, constants only have one
1128 // value and we check that it is fine above.
1130 if (opAction == TargetLowering::Custom) {
1131 Tmp1 = TLI.LowerOperation(Result, DAG);
1137 case ISD::ConstantFP: {
1138 // Spill FP immediates to the constant pool if the target cannot directly
1139 // codegen them. Targets often have some immediate values that can be
1140 // efficiently generated into an FP register without a load. We explicitly
1141 // leave these constants as ConstantFP nodes for the target to deal with.
1142 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1144 // Check to see if this FP immediate is already legal.
1145 bool isLegal = false;
1146 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1147 E = TLI.legal_fpimm_end(); I != E; ++I)
1148 if (CFP->isExactlyValue(*I)) {
1153 // If this is a legal constant, turn it into a TargetConstantFP node.
1155 Result = DAG.getTargetConstantFP(CFP->getValueAPF(),
1156 CFP->getValueType(0));
1160 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1161 default: assert(0 && "This action is not supported yet!");
1162 case TargetLowering::Custom:
1163 Tmp3 = TLI.LowerOperation(Result, DAG);
1169 case TargetLowering::Expand:
1170 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1174 case ISD::TokenFactor:
1175 if (Node->getNumOperands() == 2) {
1176 Tmp1 = LegalizeOp(Node->getOperand(0));
1177 Tmp2 = LegalizeOp(Node->getOperand(1));
1178 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1179 } else if (Node->getNumOperands() == 3) {
1180 Tmp1 = LegalizeOp(Node->getOperand(0));
1181 Tmp2 = LegalizeOp(Node->getOperand(1));
1182 Tmp3 = LegalizeOp(Node->getOperand(2));
1183 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1185 SmallVector<SDOperand, 8> Ops;
1186 // Legalize the operands.
1187 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1188 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1189 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1193 case ISD::FORMAL_ARGUMENTS:
1195 // The only option for this is to custom lower it.
1196 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1197 assert(Tmp3.Val && "Target didn't custom lower this node!");
1199 // The number of incoming and outgoing values should match; unless the final
1200 // outgoing value is a flag.
1201 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1202 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1203 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1205 "Lowering call/formal_arguments produced unexpected # results!");
1207 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1208 // remember that we legalized all of them, so it doesn't get relegalized.
1209 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1210 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1212 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1215 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1218 case ISD::EXTRACT_SUBREG: {
1219 Tmp1 = LegalizeOp(Node->getOperand(0));
1220 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1221 assert(idx && "Operand must be a constant");
1222 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1223 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1226 case ISD::INSERT_SUBREG: {
1227 Tmp1 = LegalizeOp(Node->getOperand(0));
1228 Tmp2 = LegalizeOp(Node->getOperand(1));
1229 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1230 assert(idx && "Operand must be a constant");
1231 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1232 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1235 case ISD::BUILD_VECTOR:
1236 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1237 default: assert(0 && "This action is not supported yet!");
1238 case TargetLowering::Custom:
1239 Tmp3 = TLI.LowerOperation(Result, DAG);
1245 case TargetLowering::Expand:
1246 Result = ExpandBUILD_VECTOR(Result.Val);
1250 case ISD::INSERT_VECTOR_ELT:
1251 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1252 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
1253 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1254 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1256 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1257 Node->getValueType(0))) {
1258 default: assert(0 && "This action is not supported yet!");
1259 case TargetLowering::Legal:
1261 case TargetLowering::Custom:
1262 Tmp4 = TLI.LowerOperation(Result, DAG);
1268 case TargetLowering::Expand: {
1269 // If the insert index is a constant, codegen this as a scalar_to_vector,
1270 // then a shuffle that inserts it into the right position in the vector.
1271 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1272 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1273 Tmp1.getValueType(), Tmp2);
1275 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1276 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1277 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1279 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
1280 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
1282 SmallVector<SDOperand, 8> ShufOps;
1283 for (unsigned i = 0; i != NumElts; ++i) {
1284 if (i != InsertPos->getValue())
1285 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1287 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1289 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1290 &ShufOps[0], ShufOps.size());
1292 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1293 Tmp1, ScVec, ShufMask);
1294 Result = LegalizeOp(Result);
1298 // If the target doesn't support this, we have to spill the input vector
1299 // to a temporary stack slot, update the element, then reload it. This is
1300 // badness. We could also load the value into a vector register (either
1301 // with a "move to register" or "extload into register" instruction, then
1302 // permute it into place, if the idx is a constant and if the idx is
1303 // supported by the target.
1304 MVT::ValueType VT = Tmp1.getValueType();
1305 MVT::ValueType EltVT = Tmp2.getValueType();
1306 MVT::ValueType IdxVT = Tmp3.getValueType();
1307 MVT::ValueType PtrVT = TLI.getPointerTy();
1308 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
1310 FrameIndexSDNode *StackPtrFI = dyn_cast<FrameIndexSDNode>(StackPtr.Val);
1312 int SPFI = StackPtrFI->getIndex();
1314 // Store the vector.
1315 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
1316 &PseudoSourceValue::FPRel, SPFI);
1318 // Truncate or zero extend offset to target pointer type.
1319 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1320 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1321 // Add the offset to the index.
1322 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1323 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1324 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1325 // Store the scalar value.
1326 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, &PseudoSourceValue::FPRel, SPFI);
1327 // Load the updated vector.
1328 Result = DAG.getLoad(VT, Ch, StackPtr, &PseudoSourceValue::FPRel, SPFI);
1333 case ISD::SCALAR_TO_VECTOR:
1334 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1335 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1339 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1340 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1341 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1342 Node->getValueType(0))) {
1343 default: assert(0 && "This action is not supported yet!");
1344 case TargetLowering::Legal:
1346 case TargetLowering::Custom:
1347 Tmp3 = TLI.LowerOperation(Result, DAG);
1353 case TargetLowering::Expand:
1354 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1358 case ISD::VECTOR_SHUFFLE:
1359 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1360 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1361 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1363 // Allow targets to custom lower the SHUFFLEs they support.
1364 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1365 default: assert(0 && "Unknown operation action!");
1366 case TargetLowering::Legal:
1367 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1368 "vector shuffle should not be created if not legal!");
1370 case TargetLowering::Custom:
1371 Tmp3 = TLI.LowerOperation(Result, DAG);
1377 case TargetLowering::Expand: {
1378 MVT::ValueType VT = Node->getValueType(0);
1379 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1380 MVT::ValueType PtrVT = TLI.getPointerTy();
1381 SDOperand Mask = Node->getOperand(2);
1382 unsigned NumElems = Mask.getNumOperands();
1383 SmallVector<SDOperand,8> Ops;
1384 for (unsigned i = 0; i != NumElems; ++i) {
1385 SDOperand Arg = Mask.getOperand(i);
1386 if (Arg.getOpcode() == ISD::UNDEF) {
1387 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1389 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1390 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1392 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1393 DAG.getConstant(Idx, PtrVT)));
1395 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1396 DAG.getConstant(Idx - NumElems, PtrVT)));
1399 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1402 case TargetLowering::Promote: {
1403 // Change base type to a different vector type.
1404 MVT::ValueType OVT = Node->getValueType(0);
1405 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1407 // Cast the two input vectors.
1408 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1409 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1411 // Convert the shuffle mask to the right # elements.
1412 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1413 assert(Tmp3.Val && "Shuffle not legal?");
1414 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1415 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1421 case ISD::EXTRACT_VECTOR_ELT:
1422 Tmp1 = Node->getOperand(0);
1423 Tmp2 = LegalizeOp(Node->getOperand(1));
1424 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1425 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1428 case ISD::EXTRACT_SUBVECTOR:
1429 Tmp1 = Node->getOperand(0);
1430 Tmp2 = LegalizeOp(Node->getOperand(1));
1431 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1432 Result = ExpandEXTRACT_SUBVECTOR(Result);
1435 case ISD::CALLSEQ_START: {
1436 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1438 // Recursively Legalize all of the inputs of the call end that do not lead
1439 // to this call start. This ensures that any libcalls that need be inserted
1440 // are inserted *before* the CALLSEQ_START.
1441 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1442 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1443 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1447 // Now that we legalized all of the inputs (which may have inserted
1448 // libcalls) create the new CALLSEQ_START node.
1449 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1451 // Merge in the last call, to ensure that this call start after the last
1453 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1454 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1455 Tmp1 = LegalizeOp(Tmp1);
1458 // Do not try to legalize the target-specific arguments (#1+).
1459 if (Tmp1 != Node->getOperand(0)) {
1460 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1462 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1465 // Remember that the CALLSEQ_START is legalized.
1466 AddLegalizedOperand(Op.getValue(0), Result);
1467 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1468 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1470 // Now that the callseq_start and all of the non-call nodes above this call
1471 // sequence have been legalized, legalize the call itself. During this
1472 // process, no libcalls can/will be inserted, guaranteeing that no calls
1474 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1475 SDOperand InCallSEQ = LastCALLSEQ_END;
1476 // Note that we are selecting this call!
1477 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1478 IsLegalizingCall = true;
1480 // Legalize the call, starting from the CALLSEQ_END.
1481 LegalizeOp(LastCALLSEQ_END);
1482 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1485 case ISD::CALLSEQ_END:
1486 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1487 // will cause this node to be legalized as well as handling libcalls right.
1488 if (LastCALLSEQ_END.Val != Node) {
1489 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1490 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1491 assert(I != LegalizedNodes.end() &&
1492 "Legalizing the call start should have legalized this node!");
1496 // Otherwise, the call start has been legalized and everything is going
1497 // according to plan. Just legalize ourselves normally here.
1498 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1499 // Do not try to legalize the target-specific arguments (#1+), except for
1500 // an optional flag input.
1501 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1502 if (Tmp1 != Node->getOperand(0)) {
1503 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1505 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1508 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1509 if (Tmp1 != Node->getOperand(0) ||
1510 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1511 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1514 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1517 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1518 // This finishes up call legalization.
1519 IsLegalizingCall = false;
1521 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1522 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1523 if (Node->getNumValues() == 2)
1524 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1525 return Result.getValue(Op.ResNo);
1526 case ISD::DYNAMIC_STACKALLOC: {
1527 MVT::ValueType VT = Node->getValueType(0);
1528 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1529 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1530 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1531 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1533 Tmp1 = Result.getValue(0);
1534 Tmp2 = Result.getValue(1);
1535 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1536 default: assert(0 && "This action is not supported yet!");
1537 case TargetLowering::Expand: {
1538 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1539 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1540 " not tell us which reg is the stack pointer!");
1541 SDOperand Chain = Tmp1.getOperand(0);
1543 // Chain the dynamic stack allocation so that it doesn't modify the stack
1544 // pointer when other instructions are using the stack.
1545 Chain = DAG.getCALLSEQ_START(Chain,
1546 DAG.getConstant(0, TLI.getPointerTy()));
1548 SDOperand Size = Tmp2.getOperand(1);
1549 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1550 Chain = SP.getValue(1);
1551 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1552 unsigned StackAlign =
1553 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1554 if (Align > StackAlign)
1555 SP = DAG.getNode(ISD::AND, VT, SP,
1556 DAG.getConstant(-(uint64_t)Align, VT));
1557 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1558 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1561 DAG.getCALLSEQ_END(Chain,
1562 DAG.getConstant(0, TLI.getPointerTy()),
1563 DAG.getConstant(0, TLI.getPointerTy()),
1566 Tmp1 = LegalizeOp(Tmp1);
1567 Tmp2 = LegalizeOp(Tmp2);
1570 case TargetLowering::Custom:
1571 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1573 Tmp1 = LegalizeOp(Tmp3);
1574 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1577 case TargetLowering::Legal:
1580 // Since this op produce two values, make sure to remember that we
1581 // legalized both of them.
1582 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1583 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1584 return Op.ResNo ? Tmp2 : Tmp1;
1586 case ISD::INLINEASM: {
1587 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1588 bool Changed = false;
1589 // Legalize all of the operands of the inline asm, in case they are nodes
1590 // that need to be expanded or something. Note we skip the asm string and
1591 // all of the TargetConstant flags.
1592 SDOperand Op = LegalizeOp(Ops[0]);
1593 Changed = Op != Ops[0];
1596 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1597 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1598 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1599 for (++i; NumVals; ++i, --NumVals) {
1600 SDOperand Op = LegalizeOp(Ops[i]);
1609 Op = LegalizeOp(Ops.back());
1610 Changed |= Op != Ops.back();
1615 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1617 // INLINE asm returns a chain and flag, make sure to add both to the map.
1618 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1619 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1620 return Result.getValue(Op.ResNo);
1623 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1624 // Ensure that libcalls are emitted before a branch.
1625 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1626 Tmp1 = LegalizeOp(Tmp1);
1627 LastCALLSEQ_END = DAG.getEntryNode();
1629 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1632 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1633 // Ensure that libcalls are emitted before a branch.
1634 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1635 Tmp1 = LegalizeOp(Tmp1);
1636 LastCALLSEQ_END = DAG.getEntryNode();
1638 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1639 default: assert(0 && "Indirect target must be legal type (pointer)!");
1641 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1644 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1647 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1648 // Ensure that libcalls are emitted before a branch.
1649 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1650 Tmp1 = LegalizeOp(Tmp1);
1651 LastCALLSEQ_END = DAG.getEntryNode();
1653 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1654 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1656 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1657 default: assert(0 && "This action is not supported yet!");
1658 case TargetLowering::Legal: break;
1659 case TargetLowering::Custom:
1660 Tmp1 = TLI.LowerOperation(Result, DAG);
1661 if (Tmp1.Val) Result = Tmp1;
1663 case TargetLowering::Expand: {
1664 SDOperand Chain = Result.getOperand(0);
1665 SDOperand Table = Result.getOperand(1);
1666 SDOperand Index = Result.getOperand(2);
1668 MVT::ValueType PTy = TLI.getPointerTy();
1669 MachineFunction &MF = DAG.getMachineFunction();
1670 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1671 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1672 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1675 switch (EntrySize) {
1676 default: assert(0 && "Size of jump table not supported yet."); break;
1677 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1678 &PseudoSourceValue::JTRel, 0); break;
1679 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1680 &PseudoSourceValue::JTRel, 0); break;
1684 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1685 // For PIC, the sequence is:
1686 // BRIND(load(Jumptable + index) + RelocBase)
1687 // RelocBase can be JumpTable, GOT or some sort of global base.
1688 if (PTy != MVT::i32)
1689 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1690 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1691 TLI.getPICJumpTableRelocBase(Table, DAG));
1693 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1698 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1699 // Ensure that libcalls are emitted before a return.
1700 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1701 Tmp1 = LegalizeOp(Tmp1);
1702 LastCALLSEQ_END = DAG.getEntryNode();
1704 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1705 case Expand: assert(0 && "It's impossible to expand bools");
1707 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1710 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1712 // The top bits of the promoted condition are not necessarily zero, ensure
1713 // that the value is properly zero extended.
1714 if (!DAG.MaskedValueIsZero(Tmp2,
1715 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1716 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1720 // Basic block destination (Op#2) is always legal.
1721 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1723 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1724 default: assert(0 && "This action is not supported yet!");
1725 case TargetLowering::Legal: break;
1726 case TargetLowering::Custom:
1727 Tmp1 = TLI.LowerOperation(Result, DAG);
1728 if (Tmp1.Val) Result = Tmp1;
1730 case TargetLowering::Expand:
1731 // Expand brcond's setcc into its constituent parts and create a BR_CC
1733 if (Tmp2.getOpcode() == ISD::SETCC) {
1734 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1735 Tmp2.getOperand(0), Tmp2.getOperand(1),
1736 Node->getOperand(2));
1738 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1739 DAG.getCondCode(ISD::SETNE), Tmp2,
1740 DAG.getConstant(0, Tmp2.getValueType()),
1741 Node->getOperand(2));
1747 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1748 // Ensure that libcalls are emitted before a branch.
1749 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1750 Tmp1 = LegalizeOp(Tmp1);
1751 Tmp2 = Node->getOperand(2); // LHS
1752 Tmp3 = Node->getOperand(3); // RHS
1753 Tmp4 = Node->getOperand(1); // CC
1755 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1756 LastCALLSEQ_END = DAG.getEntryNode();
1758 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1759 // the LHS is a legal SETCC itself. In this case, we need to compare
1760 // the result against zero to select between true and false values.
1761 if (Tmp3.Val == 0) {
1762 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1763 Tmp4 = DAG.getCondCode(ISD::SETNE);
1766 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1767 Node->getOperand(4));
1769 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1770 default: assert(0 && "Unexpected action for BR_CC!");
1771 case TargetLowering::Legal: break;
1772 case TargetLowering::Custom:
1773 Tmp4 = TLI.LowerOperation(Result, DAG);
1774 if (Tmp4.Val) Result = Tmp4;
1779 LoadSDNode *LD = cast<LoadSDNode>(Node);
1780 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1781 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1783 ISD::LoadExtType ExtType = LD->getExtensionType();
1784 if (ExtType == ISD::NON_EXTLOAD) {
1785 MVT::ValueType VT = Node->getValueType(0);
1786 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1787 Tmp3 = Result.getValue(0);
1788 Tmp4 = Result.getValue(1);
1790 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1791 default: assert(0 && "This action is not supported yet!");
1792 case TargetLowering::Legal:
1793 // If this is an unaligned load and the target doesn't support it,
1795 if (!TLI.allowsUnalignedMemoryAccesses()) {
1796 unsigned ABIAlignment = TLI.getTargetData()->
1797 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
1798 if (LD->getAlignment() < ABIAlignment){
1799 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1801 Tmp3 = Result.getOperand(0);
1802 Tmp4 = Result.getOperand(1);
1803 Tmp3 = LegalizeOp(Tmp3);
1804 Tmp4 = LegalizeOp(Tmp4);
1808 case TargetLowering::Custom:
1809 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1811 Tmp3 = LegalizeOp(Tmp1);
1812 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1815 case TargetLowering::Promote: {
1816 // Only promote a load of vector type to another.
1817 assert(MVT::isVector(VT) && "Cannot promote this load!");
1818 // Change base type to a different vector type.
1819 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1821 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1822 LD->getSrcValueOffset(),
1823 LD->isVolatile(), LD->getAlignment());
1824 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1825 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1829 // Since loads produce two values, make sure to remember that we
1830 // legalized both of them.
1831 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1832 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1833 return Op.ResNo ? Tmp4 : Tmp3;
1835 MVT::ValueType SrcVT = LD->getMemoryVT();
1836 unsigned SrcWidth = MVT::getSizeInBits(SrcVT);
1837 int SVOffset = LD->getSrcValueOffset();
1838 unsigned Alignment = LD->getAlignment();
1839 bool isVolatile = LD->isVolatile();
1841 if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) &&
1842 // Some targets pretend to have an i1 loading operation, and actually
1843 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1844 // bits are guaranteed to be zero; it helps the optimizers understand
1845 // that these bits are zero. It is also useful for EXTLOAD, since it
1846 // tells the optimizers that those bits are undefined. It would be
1847 // nice to have an effective generic way of getting these benefits...
1848 // Until such a way is found, don't insist on promoting i1 here.
1849 (SrcVT != MVT::i1 ||
1850 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1851 // Promote to a byte-sized load if not loading an integral number of
1852 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1853 unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT);
1854 MVT::ValueType NVT = MVT::getIntegerType(NewWidth);
1857 // The extra bits are guaranteed to be zero, since we stored them that
1858 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1860 ISD::LoadExtType NewExtType =
1861 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1863 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
1864 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1865 NVT, isVolatile, Alignment);
1867 Ch = Result.getValue(1); // The chain.
1869 if (ExtType == ISD::SEXTLOAD)
1870 // Having the top bits zero doesn't help when sign extending.
1871 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1872 Result, DAG.getValueType(SrcVT));
1873 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1874 // All the top bits are guaranteed to be zero - inform the optimizers.
1875 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
1876 DAG.getValueType(SrcVT));
1878 Tmp1 = LegalizeOp(Result);
1879 Tmp2 = LegalizeOp(Ch);
1880 } else if (SrcWidth & (SrcWidth - 1)) {
1881 // If not loading a power-of-2 number of bits, expand as two loads.
1882 assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) &&
1883 "Unsupported extload!");
1884 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1885 assert(RoundWidth < SrcWidth);
1886 unsigned ExtraWidth = SrcWidth - RoundWidth;
1887 assert(ExtraWidth < RoundWidth);
1888 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1889 "Load size not an integral number of bytes!");
1890 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
1891 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
1892 SDOperand Lo, Hi, Ch;
1893 unsigned IncrementSize;
1895 if (TLI.isLittleEndian()) {
1896 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1897 // Load the bottom RoundWidth bits.
1898 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
1899 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1902 // Load the remaining ExtraWidth bits.
1903 IncrementSize = RoundWidth / 8;
1904 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1905 DAG.getIntPtrConstant(IncrementSize));
1906 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1907 LD->getSrcValue(), SVOffset + IncrementSize,
1908 ExtraVT, isVolatile,
1909 MinAlign(Alignment, IncrementSize));
1911 // Build a factor node to remember that this load is independent of the
1913 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1916 // Move the top bits to the right place.
1917 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
1918 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1920 // Join the hi and lo parts.
1921 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
1923 // Big endian - avoid unaligned loads.
1924 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1925 // Load the top RoundWidth bits.
1926 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1927 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1930 // Load the remaining ExtraWidth bits.
1931 IncrementSize = RoundWidth / 8;
1932 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1933 DAG.getIntPtrConstant(IncrementSize));
1934 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
1935 LD->getSrcValue(), SVOffset + IncrementSize,
1936 ExtraVT, isVolatile,
1937 MinAlign(Alignment, IncrementSize));
1939 // Build a factor node to remember that this load is independent of the
1941 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1944 // Move the top bits to the right place.
1945 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
1946 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1948 // Join the hi and lo parts.
1949 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
1952 Tmp1 = LegalizeOp(Result);
1953 Tmp2 = LegalizeOp(Ch);
1955 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1956 default: assert(0 && "This action is not supported yet!");
1957 case TargetLowering::Custom:
1960 case TargetLowering::Legal:
1961 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1962 Tmp1 = Result.getValue(0);
1963 Tmp2 = Result.getValue(1);
1966 Tmp3 = TLI.LowerOperation(Result, DAG);
1968 Tmp1 = LegalizeOp(Tmp3);
1969 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1972 // If this is an unaligned load and the target doesn't support it,
1974 if (!TLI.allowsUnalignedMemoryAccesses()) {
1975 unsigned ABIAlignment = TLI.getTargetData()->
1976 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
1977 if (LD->getAlignment() < ABIAlignment){
1978 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1980 Tmp1 = Result.getOperand(0);
1981 Tmp2 = Result.getOperand(1);
1982 Tmp1 = LegalizeOp(Tmp1);
1983 Tmp2 = LegalizeOp(Tmp2);
1988 case TargetLowering::Expand:
1989 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1990 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1991 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1992 LD->getSrcValueOffset(),
1993 LD->isVolatile(), LD->getAlignment());
1994 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1995 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1996 Tmp2 = LegalizeOp(Load.getValue(1));
1999 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2000 // Turn the unsupported load into an EXTLOAD followed by an explicit
2001 // zero/sign extend inreg.
2002 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2003 Tmp1, Tmp2, LD->getSrcValue(),
2004 LD->getSrcValueOffset(), SrcVT,
2005 LD->isVolatile(), LD->getAlignment());
2007 if (ExtType == ISD::SEXTLOAD)
2008 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2009 Result, DAG.getValueType(SrcVT));
2011 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2012 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2013 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2018 // Since loads produce two values, make sure to remember that we legalized
2020 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2021 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2022 return Op.ResNo ? Tmp2 : Tmp1;
2025 case ISD::EXTRACT_ELEMENT: {
2026 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
2027 switch (getTypeAction(OpTy)) {
2028 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2030 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2032 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2033 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
2034 TLI.getShiftAmountTy()));
2035 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2038 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2039 Node->getOperand(0));
2043 // Get both the low and high parts.
2044 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2045 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2046 Result = Tmp2; // 1 -> Hi
2048 Result = Tmp1; // 0 -> Lo
2054 case ISD::CopyToReg:
2055 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2057 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2058 "Register type must be legal!");
2059 // Legalize the incoming value (must be a legal type).
2060 Tmp2 = LegalizeOp(Node->getOperand(2));
2061 if (Node->getNumValues() == 1) {
2062 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2064 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2065 if (Node->getNumOperands() == 4) {
2066 Tmp3 = LegalizeOp(Node->getOperand(3));
2067 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2070 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2073 // Since this produces two values, make sure to remember that we legalized
2075 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2076 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2082 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2084 // Ensure that libcalls are emitted before a return.
2085 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2086 Tmp1 = LegalizeOp(Tmp1);
2087 LastCALLSEQ_END = DAG.getEntryNode();
2089 switch (Node->getNumOperands()) {
2091 Tmp2 = Node->getOperand(1);
2092 Tmp3 = Node->getOperand(2); // Signness
2093 switch (getTypeAction(Tmp2.getValueType())) {
2095 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2098 if (!MVT::isVector(Tmp2.getValueType())) {
2100 ExpandOp(Tmp2, Lo, Hi);
2102 // Big endian systems want the hi reg first.
2103 if (!TLI.isLittleEndian())
2107 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2109 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2110 Result = LegalizeOp(Result);
2112 SDNode *InVal = Tmp2.Val;
2113 int InIx = Tmp2.ResNo;
2114 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
2115 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
2117 // Figure out if there is a simple type corresponding to this Vector
2118 // type. If so, convert to the vector type.
2119 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2120 if (TLI.isTypeLegal(TVT)) {
2121 // Turn this into a return of the vector type.
2122 Tmp2 = LegalizeOp(Tmp2);
2123 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2124 } else if (NumElems == 1) {
2125 // Turn this into a return of the scalar type.
2126 Tmp2 = ScalarizeVectorOp(Tmp2);
2127 Tmp2 = LegalizeOp(Tmp2);
2128 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2130 // FIXME: Returns of gcc generic vectors smaller than a legal type
2131 // should be returned in integer registers!
2133 // The scalarized value type may not be legal, e.g. it might require
2134 // promotion or expansion. Relegalize the return.
2135 Result = LegalizeOp(Result);
2137 // FIXME: Returns of gcc generic vectors larger than a legal vector
2138 // type should be returned by reference!
2140 SplitVectorOp(Tmp2, Lo, Hi);
2141 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2142 Result = LegalizeOp(Result);
2147 Tmp2 = PromoteOp(Node->getOperand(1));
2148 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2149 Result = LegalizeOp(Result);
2154 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2156 default: { // ret <values>
2157 SmallVector<SDOperand, 8> NewValues;
2158 NewValues.push_back(Tmp1);
2159 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2160 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2162 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2163 NewValues.push_back(Node->getOperand(i+1));
2167 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
2168 "FIXME: TODO: implement returning non-legal vector types!");
2169 ExpandOp(Node->getOperand(i), Lo, Hi);
2170 NewValues.push_back(Lo);
2171 NewValues.push_back(Node->getOperand(i+1));
2173 NewValues.push_back(Hi);
2174 NewValues.push_back(Node->getOperand(i+1));
2179 assert(0 && "Can't promote multiple return value yet!");
2182 if (NewValues.size() == Node->getNumOperands())
2183 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2185 Result = DAG.getNode(ISD::RET, MVT::Other,
2186 &NewValues[0], NewValues.size());
2191 if (Result.getOpcode() == ISD::RET) {
2192 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2193 default: assert(0 && "This action is not supported yet!");
2194 case TargetLowering::Legal: break;
2195 case TargetLowering::Custom:
2196 Tmp1 = TLI.LowerOperation(Result, DAG);
2197 if (Tmp1.Val) Result = Tmp1;
2203 StoreSDNode *ST = cast<StoreSDNode>(Node);
2204 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2205 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2206 int SVOffset = ST->getSrcValueOffset();
2207 unsigned Alignment = ST->getAlignment();
2208 bool isVolatile = ST->isVolatile();
2210 if (!ST->isTruncatingStore()) {
2211 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2212 // FIXME: We shouldn't do this for TargetConstantFP's.
2213 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2214 // to phase ordering between legalized code and the dag combiner. This
2215 // probably means that we need to integrate dag combiner and legalizer
2217 // We generally can't do this one for long doubles.
2218 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2219 if (CFP->getValueType(0) == MVT::f32 &&
2220 getTypeAction(MVT::i32) == Legal) {
2221 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF().
2222 convertToAPInt().getZExtValue(),
2224 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2225 SVOffset, isVolatile, Alignment);
2227 } else if (CFP->getValueType(0) == MVT::f64) {
2228 // If this target supports 64-bit registers, do a single 64-bit store.
2229 if (getTypeAction(MVT::i64) == Legal) {
2230 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2231 getZExtValue(), MVT::i64);
2232 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2233 SVOffset, isVolatile, Alignment);
2235 } else if (getTypeAction(MVT::i32) == Legal) {
2236 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2237 // stores. If the target supports neither 32- nor 64-bits, this
2238 // xform is certainly not worth it.
2239 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue();
2240 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32);
2241 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32);
2242 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
2244 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2245 SVOffset, isVolatile, Alignment);
2246 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2247 DAG.getIntPtrConstant(4));
2248 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2249 isVolatile, MinAlign(Alignment, 4U));
2251 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2257 switch (getTypeAction(ST->getMemoryVT())) {
2259 Tmp3 = LegalizeOp(ST->getValue());
2260 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2263 MVT::ValueType VT = Tmp3.getValueType();
2264 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2265 default: assert(0 && "This action is not supported yet!");
2266 case TargetLowering::Legal:
2267 // If this is an unaligned store and the target doesn't support it,
2269 if (!TLI.allowsUnalignedMemoryAccesses()) {
2270 unsigned ABIAlignment = TLI.getTargetData()->
2271 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2272 if (ST->getAlignment() < ABIAlignment)
2273 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2277 case TargetLowering::Custom:
2278 Tmp1 = TLI.LowerOperation(Result, DAG);
2279 if (Tmp1.Val) Result = Tmp1;
2281 case TargetLowering::Promote:
2282 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2283 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2284 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2285 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2286 ST->getSrcValue(), SVOffset, isVolatile,
2293 // Truncate the value and store the result.
2294 Tmp3 = PromoteOp(ST->getValue());
2295 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2296 SVOffset, ST->getMemoryVT(),
2297 isVolatile, Alignment);
2301 unsigned IncrementSize = 0;
2304 // If this is a vector type, then we have to calculate the increment as
2305 // the product of the element size in bytes, and the number of elements
2306 // in the high half of the vector.
2307 if (MVT::isVector(ST->getValue().getValueType())) {
2308 SDNode *InVal = ST->getValue().Val;
2309 int InIx = ST->getValue().ResNo;
2310 MVT::ValueType InVT = InVal->getValueType(InIx);
2311 unsigned NumElems = MVT::getVectorNumElements(InVT);
2312 MVT::ValueType EVT = MVT::getVectorElementType(InVT);
2314 // Figure out if there is a simple type corresponding to this Vector
2315 // type. If so, convert to the vector type.
2316 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2317 if (TLI.isTypeLegal(TVT)) {
2318 // Turn this into a normal store of the vector type.
2319 Tmp3 = LegalizeOp(Node->getOperand(1));
2320 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2321 SVOffset, isVolatile, Alignment);
2322 Result = LegalizeOp(Result);
2324 } else if (NumElems == 1) {
2325 // Turn this into a normal store of the scalar type.
2326 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
2327 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2328 SVOffset, isVolatile, Alignment);
2329 // The scalarized value type may not be legal, e.g. it might require
2330 // promotion or expansion. Relegalize the scalar store.
2331 Result = LegalizeOp(Result);
2334 SplitVectorOp(Node->getOperand(1), Lo, Hi);
2335 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
2336 MVT::getSizeInBits(EVT)/8;
2339 ExpandOp(Node->getOperand(1), Lo, Hi);
2340 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2342 if (!TLI.isLittleEndian())
2346 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2347 SVOffset, isVolatile, Alignment);
2349 if (Hi.Val == NULL) {
2350 // Must be int <-> float one-to-one expansion.
2355 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2356 DAG.getIntPtrConstant(IncrementSize));
2357 assert(isTypeLegal(Tmp2.getValueType()) &&
2358 "Pointers must be legal!");
2359 SVOffset += IncrementSize;
2360 Alignment = MinAlign(Alignment, IncrementSize);
2361 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2362 SVOffset, isVolatile, Alignment);
2363 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2367 switch (getTypeAction(ST->getValue().getValueType())) {
2369 Tmp3 = LegalizeOp(ST->getValue());
2372 // We can promote the value, the truncstore will still take care of it.
2373 Tmp3 = PromoteOp(ST->getValue());
2376 // Just store the low part. This may become a non-trunc store, so make
2377 // sure to use getTruncStore, not UpdateNodeOperands below.
2378 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2379 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2380 SVOffset, MVT::i8, isVolatile, Alignment);
2383 MVT::ValueType StVT = ST->getMemoryVT();
2384 unsigned StWidth = MVT::getSizeInBits(StVT);
2386 if (StWidth != MVT::getStoreSizeInBits(StVT)) {
2387 // Promote to a byte-sized store with upper bits zero if not
2388 // storing an integral number of bytes. For example, promote
2389 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2390 MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT));
2391 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2392 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2393 SVOffset, NVT, isVolatile, Alignment);
2394 } else if (StWidth & (StWidth - 1)) {
2395 // If not storing a power-of-2 number of bits, expand as two stores.
2396 assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) &&
2397 "Unsupported truncstore!");
2398 unsigned RoundWidth = 1 << Log2_32(StWidth);
2399 assert(RoundWidth < StWidth);
2400 unsigned ExtraWidth = StWidth - RoundWidth;
2401 assert(ExtraWidth < RoundWidth);
2402 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2403 "Store size not an integral number of bytes!");
2404 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
2405 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
2407 unsigned IncrementSize;
2409 if (TLI.isLittleEndian()) {
2410 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2411 // Store the bottom RoundWidth bits.
2412 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2414 isVolatile, Alignment);
2416 // Store the remaining ExtraWidth bits.
2417 IncrementSize = RoundWidth / 8;
2418 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2419 DAG.getIntPtrConstant(IncrementSize));
2420 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2421 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2422 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2423 SVOffset + IncrementSize, ExtraVT, isVolatile,
2424 MinAlign(Alignment, IncrementSize));
2426 // Big endian - avoid unaligned stores.
2427 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2428 // Store the top RoundWidth bits.
2429 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2430 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2431 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2432 RoundVT, isVolatile, Alignment);
2434 // Store the remaining ExtraWidth bits.
2435 IncrementSize = RoundWidth / 8;
2436 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2437 DAG.getIntPtrConstant(IncrementSize));
2438 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2439 SVOffset + IncrementSize, ExtraVT, isVolatile,
2440 MinAlign(Alignment, IncrementSize));
2443 // The order of the stores doesn't matter.
2444 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2446 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2447 Tmp2 != ST->getBasePtr())
2448 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2451 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2452 default: assert(0 && "This action is not supported yet!");
2453 case TargetLowering::Legal:
2454 // If this is an unaligned store and the target doesn't support it,
2456 if (!TLI.allowsUnalignedMemoryAccesses()) {
2457 unsigned ABIAlignment = TLI.getTargetData()->
2458 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2459 if (ST->getAlignment() < ABIAlignment)
2460 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2464 case TargetLowering::Custom:
2465 Result = TLI.LowerOperation(Result, DAG);
2468 // TRUNCSTORE:i16 i32 -> STORE i16
2469 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2470 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2471 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2472 isVolatile, Alignment);
2480 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2481 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2483 case ISD::STACKSAVE:
2484 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2485 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2486 Tmp1 = Result.getValue(0);
2487 Tmp2 = Result.getValue(1);
2489 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2490 default: assert(0 && "This action is not supported yet!");
2491 case TargetLowering::Legal: break;
2492 case TargetLowering::Custom:
2493 Tmp3 = TLI.LowerOperation(Result, DAG);
2495 Tmp1 = LegalizeOp(Tmp3);
2496 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2499 case TargetLowering::Expand:
2500 // Expand to CopyFromReg if the target set
2501 // StackPointerRegisterToSaveRestore.
2502 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2503 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2504 Node->getValueType(0));
2505 Tmp2 = Tmp1.getValue(1);
2507 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2508 Tmp2 = Node->getOperand(0);
2513 // Since stacksave produce two values, make sure to remember that we
2514 // legalized both of them.
2515 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2516 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2517 return Op.ResNo ? Tmp2 : Tmp1;
2519 case ISD::STACKRESTORE:
2520 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2521 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2522 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2524 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2525 default: assert(0 && "This action is not supported yet!");
2526 case TargetLowering::Legal: break;
2527 case TargetLowering::Custom:
2528 Tmp1 = TLI.LowerOperation(Result, DAG);
2529 if (Tmp1.Val) Result = Tmp1;
2531 case TargetLowering::Expand:
2532 // Expand to CopyToReg if the target set
2533 // StackPointerRegisterToSaveRestore.
2534 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2535 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2543 case ISD::READCYCLECOUNTER:
2544 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2545 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2546 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2547 Node->getValueType(0))) {
2548 default: assert(0 && "This action is not supported yet!");
2549 case TargetLowering::Legal:
2550 Tmp1 = Result.getValue(0);
2551 Tmp2 = Result.getValue(1);
2553 case TargetLowering::Custom:
2554 Result = TLI.LowerOperation(Result, DAG);
2555 Tmp1 = LegalizeOp(Result.getValue(0));
2556 Tmp2 = LegalizeOp(Result.getValue(1));
2560 // Since rdcc produce two values, make sure to remember that we legalized
2562 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2563 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2567 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2568 case Expand: assert(0 && "It's impossible to expand bools");
2570 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2573 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2574 // Make sure the condition is either zero or one.
2575 if (!DAG.MaskedValueIsZero(Tmp1,
2576 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2577 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2580 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2581 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2583 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2585 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2586 default: assert(0 && "This action is not supported yet!");
2587 case TargetLowering::Legal: break;
2588 case TargetLowering::Custom: {
2589 Tmp1 = TLI.LowerOperation(Result, DAG);
2590 if (Tmp1.Val) Result = Tmp1;
2593 case TargetLowering::Expand:
2594 if (Tmp1.getOpcode() == ISD::SETCC) {
2595 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2597 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2599 Result = DAG.getSelectCC(Tmp1,
2600 DAG.getConstant(0, Tmp1.getValueType()),
2601 Tmp2, Tmp3, ISD::SETNE);
2604 case TargetLowering::Promote: {
2605 MVT::ValueType NVT =
2606 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2607 unsigned ExtOp, TruncOp;
2608 if (MVT::isVector(Tmp2.getValueType())) {
2609 ExtOp = ISD::BIT_CONVERT;
2610 TruncOp = ISD::BIT_CONVERT;
2611 } else if (MVT::isInteger(Tmp2.getValueType())) {
2612 ExtOp = ISD::ANY_EXTEND;
2613 TruncOp = ISD::TRUNCATE;
2615 ExtOp = ISD::FP_EXTEND;
2616 TruncOp = ISD::FP_ROUND;
2618 // Promote each of the values to the new type.
2619 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2620 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2621 // Perform the larger operation, then round down.
2622 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2623 if (TruncOp != ISD::FP_ROUND)
2624 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2626 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2627 DAG.getIntPtrConstant(0));
2632 case ISD::SELECT_CC: {
2633 Tmp1 = Node->getOperand(0); // LHS
2634 Tmp2 = Node->getOperand(1); // RHS
2635 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2636 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2637 SDOperand CC = Node->getOperand(4);
2639 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2641 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2642 // the LHS is a legal SETCC itself. In this case, we need to compare
2643 // the result against zero to select between true and false values.
2644 if (Tmp2.Val == 0) {
2645 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2646 CC = DAG.getCondCode(ISD::SETNE);
2648 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2650 // Everything is legal, see if we should expand this op or something.
2651 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2652 default: assert(0 && "This action is not supported yet!");
2653 case TargetLowering::Legal: break;
2654 case TargetLowering::Custom:
2655 Tmp1 = TLI.LowerOperation(Result, DAG);
2656 if (Tmp1.Val) Result = Tmp1;
2662 Tmp1 = Node->getOperand(0);
2663 Tmp2 = Node->getOperand(1);
2664 Tmp3 = Node->getOperand(2);
2665 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2667 // If we had to Expand the SetCC operands into a SELECT node, then it may
2668 // not always be possible to return a true LHS & RHS. In this case, just
2669 // return the value we legalized, returned in the LHS
2670 if (Tmp2.Val == 0) {
2675 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2676 default: assert(0 && "Cannot handle this action for SETCC yet!");
2677 case TargetLowering::Custom:
2680 case TargetLowering::Legal:
2681 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2683 Tmp4 = TLI.LowerOperation(Result, DAG);
2684 if (Tmp4.Val) Result = Tmp4;
2687 case TargetLowering::Promote: {
2688 // First step, figure out the appropriate operation to use.
2689 // Allow SETCC to not be supported for all legal data types
2690 // Mostly this targets FP
2691 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2692 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2694 // Scan for the appropriate larger type to use.
2696 NewInTy = (MVT::ValueType)(NewInTy+1);
2698 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2699 "Fell off of the edge of the integer world");
2700 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2701 "Fell off of the edge of the floating point world");
2703 // If the target supports SETCC of this type, use it.
2704 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2707 if (MVT::isInteger(NewInTy))
2708 assert(0 && "Cannot promote Legal Integer SETCC yet");
2710 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2711 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2713 Tmp1 = LegalizeOp(Tmp1);
2714 Tmp2 = LegalizeOp(Tmp2);
2715 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2716 Result = LegalizeOp(Result);
2719 case TargetLowering::Expand:
2720 // Expand a setcc node into a select_cc of the same condition, lhs, and
2721 // rhs that selects between const 1 (true) and const 0 (false).
2722 MVT::ValueType VT = Node->getValueType(0);
2723 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2724 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2731 case ISD::MEMMOVE: {
2732 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2733 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2735 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2736 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2737 case Expand: assert(0 && "Cannot expand a byte!");
2739 Tmp3 = LegalizeOp(Node->getOperand(2));
2742 Tmp3 = PromoteOp(Node->getOperand(2));
2746 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2750 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2752 // Length is too big, just take the lo-part of the length.
2754 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2758 Tmp4 = LegalizeOp(Node->getOperand(3));
2761 Tmp4 = PromoteOp(Node->getOperand(3));
2766 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2767 case Expand: assert(0 && "Cannot expand this yet!");
2769 Tmp5 = LegalizeOp(Node->getOperand(4));
2772 Tmp5 = PromoteOp(Node->getOperand(4));
2777 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool
2778 case Expand: assert(0 && "Cannot expand this yet!");
2780 Tmp6 = LegalizeOp(Node->getOperand(5));
2783 Tmp6 = PromoteOp(Node->getOperand(5));
2787 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2788 default: assert(0 && "This action not implemented for this operation!");
2789 case TargetLowering::Custom:
2792 case TargetLowering::Legal: {
2793 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 };
2794 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
2796 Tmp1 = TLI.LowerOperation(Result, DAG);
2797 if (Tmp1.Val) Result = Tmp1;
2801 case TargetLowering::Expand: {
2802 // Otherwise, the target does not support this operation. Lower the
2803 // operation to an explicit libcall as appropriate.
2804 MVT::ValueType IntPtr = TLI.getPointerTy();
2805 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2806 TargetLowering::ArgListTy Args;
2807 TargetLowering::ArgListEntry Entry;
2809 const char *FnName = 0;
2810 if (Node->getOpcode() == ISD::MEMSET) {
2811 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2812 Args.push_back(Entry);
2813 // Extend the (previously legalized) ubyte argument to be an int value
2815 if (Tmp3.getValueType() > MVT::i32)
2816 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2818 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2819 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2820 Args.push_back(Entry);
2821 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2822 Args.push_back(Entry);
2825 } else if (Node->getOpcode() == ISD::MEMCPY ||
2826 Node->getOpcode() == ISD::MEMMOVE) {
2827 Entry.Ty = IntPtrTy;
2828 Entry.Node = Tmp2; Args.push_back(Entry);
2829 Entry.Node = Tmp3; Args.push_back(Entry);
2830 Entry.Node = Tmp4; Args.push_back(Entry);
2831 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2833 assert(0 && "Unknown op!");
2836 std::pair<SDOperand,SDOperand> CallResult =
2837 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2838 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2839 Result = CallResult.second;
2846 case ISD::SHL_PARTS:
2847 case ISD::SRA_PARTS:
2848 case ISD::SRL_PARTS: {
2849 SmallVector<SDOperand, 8> Ops;
2850 bool Changed = false;
2851 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2852 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2853 Changed |= Ops.back() != Node->getOperand(i);
2856 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2858 switch (TLI.getOperationAction(Node->getOpcode(),
2859 Node->getValueType(0))) {
2860 default: assert(0 && "This action is not supported yet!");
2861 case TargetLowering::Legal: break;
2862 case TargetLowering::Custom:
2863 Tmp1 = TLI.LowerOperation(Result, DAG);
2865 SDOperand Tmp2, RetVal(0, 0);
2866 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2867 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2868 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2872 assert(RetVal.Val && "Illegal result number");
2878 // Since these produce multiple values, make sure to remember that we
2879 // legalized all of them.
2880 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2881 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2882 return Result.getValue(Op.ResNo);
2904 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2905 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2906 case Expand: assert(0 && "Not possible");
2908 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2911 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2915 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2917 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2918 default: assert(0 && "BinOp legalize operation not supported");
2919 case TargetLowering::Legal: break;
2920 case TargetLowering::Custom:
2921 Tmp1 = TLI.LowerOperation(Result, DAG);
2922 if (Tmp1.Val) Result = Tmp1;
2924 case TargetLowering::Expand: {
2925 MVT::ValueType VT = Op.getValueType();
2927 // See if multiply or divide can be lowered using two-result operations.
2928 SDVTList VTs = DAG.getVTList(VT, VT);
2929 if (Node->getOpcode() == ISD::MUL) {
2930 // We just need the low half of the multiply; try both the signed
2931 // and unsigned forms. If the target supports both SMUL_LOHI and
2932 // UMUL_LOHI, form a preference by checking which forms of plain
2933 // MULH it supports.
2934 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2935 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2936 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2937 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2938 unsigned OpToUse = 0;
2939 if (HasSMUL_LOHI && !HasMULHS) {
2940 OpToUse = ISD::SMUL_LOHI;
2941 } else if (HasUMUL_LOHI && !HasMULHU) {
2942 OpToUse = ISD::UMUL_LOHI;
2943 } else if (HasSMUL_LOHI) {
2944 OpToUse = ISD::SMUL_LOHI;
2945 } else if (HasUMUL_LOHI) {
2946 OpToUse = ISD::UMUL_LOHI;
2949 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
2953 if (Node->getOpcode() == ISD::MULHS &&
2954 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
2955 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2958 if (Node->getOpcode() == ISD::MULHU &&
2959 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
2960 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2963 if (Node->getOpcode() == ISD::SDIV &&
2964 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
2965 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2968 if (Node->getOpcode() == ISD::UDIV &&
2969 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
2970 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2974 // Check to see if we have a libcall for this operator.
2975 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2976 bool isSigned = false;
2977 switch (Node->getOpcode()) {
2980 if (VT == MVT::i32) {
2981 LC = Node->getOpcode() == ISD::UDIV
2982 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2983 isSigned = Node->getOpcode() == ISD::SDIV;
2987 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
2988 RTLIB::POW_PPCF128);
2992 if (LC != RTLIB::UNKNOWN_LIBCALL) {
2994 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2998 assert(MVT::isVector(Node->getValueType(0)) &&
2999 "Cannot expand this binary operator!");
3000 // Expand the operation into a bunch of nasty scalar code.
3001 Result = LegalizeOp(UnrollVectorOp(Op));
3004 case TargetLowering::Promote: {
3005 switch (Node->getOpcode()) {
3006 default: assert(0 && "Do not know how to promote this BinOp!");
3010 MVT::ValueType OVT = Node->getValueType(0);
3011 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3012 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
3013 // Bit convert each of the values to the new type.
3014 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3015 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3016 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3017 // Bit convert the result back the original type.
3018 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3026 case ISD::SMUL_LOHI:
3027 case ISD::UMUL_LOHI:
3030 // These nodes will only be produced by target-specific lowering, so
3031 // they shouldn't be here if they aren't legal.
3032 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3033 "This must be legal!");
3035 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3036 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3037 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3040 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3041 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3042 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3043 case Expand: assert(0 && "Not possible");
3045 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3048 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3052 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3054 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3055 default: assert(0 && "Operation not supported");
3056 case TargetLowering::Custom:
3057 Tmp1 = TLI.LowerOperation(Result, DAG);
3058 if (Tmp1.Val) Result = Tmp1;
3060 case TargetLowering::Legal: break;
3061 case TargetLowering::Expand: {
3062 // If this target supports fabs/fneg natively and select is cheap,
3063 // do this efficiently.
3064 if (!TLI.isSelectExpensive() &&
3065 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3066 TargetLowering::Legal &&
3067 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3068 TargetLowering::Legal) {
3069 // Get the sign bit of the RHS.
3070 MVT::ValueType IVT =
3071 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3072 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3073 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
3074 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3075 // Get the absolute value of the result.
3076 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3077 // Select between the nabs and abs value based on the sign bit of
3079 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3080 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3083 Result = LegalizeOp(Result);
3087 // Otherwise, do bitwise ops!
3088 MVT::ValueType NVT =
3089 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3090 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3091 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3092 Result = LegalizeOp(Result);
3100 Tmp1 = LegalizeOp(Node->getOperand(0));
3101 Tmp2 = LegalizeOp(Node->getOperand(1));
3102 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3103 // Since this produces two values, make sure to remember that we legalized
3105 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3106 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3111 Tmp1 = LegalizeOp(Node->getOperand(0));
3112 Tmp2 = LegalizeOp(Node->getOperand(1));
3113 Tmp3 = LegalizeOp(Node->getOperand(2));
3114 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3115 // Since this produces two values, make sure to remember that we legalized
3117 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3118 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3121 case ISD::BUILD_PAIR: {
3122 MVT::ValueType PairTy = Node->getValueType(0);
3123 // TODO: handle the case where the Lo and Hi operands are not of legal type
3124 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3125 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3126 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3127 case TargetLowering::Promote:
3128 case TargetLowering::Custom:
3129 assert(0 && "Cannot promote/custom this yet!");
3130 case TargetLowering::Legal:
3131 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3132 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3134 case TargetLowering::Expand:
3135 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3136 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3137 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3138 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
3139 TLI.getShiftAmountTy()));
3140 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3149 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3150 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3152 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3153 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3154 case TargetLowering::Custom:
3157 case TargetLowering::Legal:
3158 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3160 Tmp1 = TLI.LowerOperation(Result, DAG);
3161 if (Tmp1.Val) Result = Tmp1;
3164 case TargetLowering::Expand: {
3165 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3166 bool isSigned = DivOpc == ISD::SDIV;
3167 MVT::ValueType VT = Node->getValueType(0);
3169 // See if remainder can be lowered using two-result operations.
3170 SDVTList VTs = DAG.getVTList(VT, VT);
3171 if (Node->getOpcode() == ISD::SREM &&
3172 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3173 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3176 if (Node->getOpcode() == ISD::UREM &&
3177 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3178 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3182 if (MVT::isInteger(VT)) {
3183 if (TLI.getOperationAction(DivOpc, VT) ==
3184 TargetLowering::Legal) {
3186 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3187 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3188 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3189 } else if (MVT::isVector(VT)) {
3190 Result = LegalizeOp(UnrollVectorOp(Op));
3192 assert(VT == MVT::i32 &&
3193 "Cannot expand this binary operator!");
3194 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3195 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3197 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3200 assert(MVT::isFloatingPoint(VT) &&
3201 "remainder op must have integer or floating-point type");
3202 if (MVT::isVector(VT)) {
3203 Result = LegalizeOp(UnrollVectorOp(Op));
3205 // Floating point mod -> fmod libcall.
3206 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3207 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3209 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3210 false/*sign irrelevant*/, Dummy);
3218 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3219 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3221 MVT::ValueType VT = Node->getValueType(0);
3222 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3223 default: assert(0 && "This action is not supported yet!");
3224 case TargetLowering::Custom:
3227 case TargetLowering::Legal:
3228 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3229 Result = Result.getValue(0);
3230 Tmp1 = Result.getValue(1);
3233 Tmp2 = TLI.LowerOperation(Result, DAG);
3235 Result = LegalizeOp(Tmp2);
3236 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3240 case TargetLowering::Expand: {
3241 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3242 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3243 // Increment the pointer, VAList, to the next vaarg
3244 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3245 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3246 TLI.getPointerTy()));
3247 // Store the incremented VAList to the legalized pointer
3248 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3249 // Load the actual argument out of the pointer VAList
3250 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3251 Tmp1 = LegalizeOp(Result.getValue(1));
3252 Result = LegalizeOp(Result);
3256 // Since VAARG produces two values, make sure to remember that we
3257 // legalized both of them.
3258 AddLegalizedOperand(SDOperand(Node, 0), Result);
3259 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3260 return Op.ResNo ? Tmp1 : Result;
3264 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3265 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3266 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3268 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3269 default: assert(0 && "This action is not supported yet!");
3270 case TargetLowering::Custom:
3273 case TargetLowering::Legal:
3274 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3275 Node->getOperand(3), Node->getOperand(4));
3277 Tmp1 = TLI.LowerOperation(Result, DAG);
3278 if (Tmp1.Val) Result = Tmp1;
3281 case TargetLowering::Expand:
3282 // This defaults to loading a pointer from the input and storing it to the
3283 // output, returning the chain.
3284 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3285 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3286 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VD, 0);
3287 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VS, 0);
3293 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3294 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3296 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3297 default: assert(0 && "This action is not supported yet!");
3298 case TargetLowering::Custom:
3301 case TargetLowering::Legal:
3302 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3304 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3305 if (Tmp1.Val) Result = Tmp1;
3308 case TargetLowering::Expand:
3309 Result = Tmp1; // Default to a no-op, return the chain
3315 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3316 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3318 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3320 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3321 default: assert(0 && "This action is not supported yet!");
3322 case TargetLowering::Legal: break;
3323 case TargetLowering::Custom:
3324 Tmp1 = TLI.LowerOperation(Result, DAG);
3325 if (Tmp1.Val) Result = Tmp1;
3332 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3333 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3334 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3335 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3337 assert(0 && "ROTL/ROTR legalize operation not supported");
3339 case TargetLowering::Legal:
3341 case TargetLowering::Custom:
3342 Tmp1 = TLI.LowerOperation(Result, DAG);
3343 if (Tmp1.Val) Result = Tmp1;
3345 case TargetLowering::Promote:
3346 assert(0 && "Do not know how to promote ROTL/ROTR");
3348 case TargetLowering::Expand:
3349 assert(0 && "Do not know how to expand ROTL/ROTR");
3355 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3356 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3357 case TargetLowering::Custom:
3358 assert(0 && "Cannot custom legalize this yet!");
3359 case TargetLowering::Legal:
3360 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3362 case TargetLowering::Promote: {
3363 MVT::ValueType OVT = Tmp1.getValueType();
3364 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3365 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
3367 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3368 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3369 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3370 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3373 case TargetLowering::Expand:
3374 Result = ExpandBSWAP(Tmp1);
3382 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3383 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3384 case TargetLowering::Custom:
3385 case TargetLowering::Legal:
3386 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3387 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3388 TargetLowering::Custom) {
3389 Tmp1 = TLI.LowerOperation(Result, DAG);
3395 case TargetLowering::Promote: {
3396 MVT::ValueType OVT = Tmp1.getValueType();
3397 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3399 // Zero extend the argument.
3400 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3401 // Perform the larger operation, then subtract if needed.
3402 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3403 switch (Node->getOpcode()) {
3408 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3409 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3410 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3412 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3413 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
3416 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3417 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3418 DAG.getConstant(MVT::getSizeInBits(NVT) -
3419 MVT::getSizeInBits(OVT), NVT));
3424 case TargetLowering::Expand:
3425 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3436 Tmp1 = LegalizeOp(Node->getOperand(0));
3437 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3438 case TargetLowering::Promote:
3439 case TargetLowering::Custom:
3442 case TargetLowering::Legal:
3443 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3445 Tmp1 = TLI.LowerOperation(Result, DAG);
3446 if (Tmp1.Val) Result = Tmp1;
3449 case TargetLowering::Expand:
3450 switch (Node->getOpcode()) {
3451 default: assert(0 && "Unreachable!");
3453 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3454 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3455 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3458 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3459 MVT::ValueType VT = Node->getValueType(0);
3460 Tmp2 = DAG.getConstantFP(0.0, VT);
3461 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
3462 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3463 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3469 MVT::ValueType VT = Node->getValueType(0);
3471 // Expand unsupported unary vector operators by unrolling them.
3472 if (MVT::isVector(VT)) {
3473 Result = LegalizeOp(UnrollVectorOp(Op));
3477 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3478 switch(Node->getOpcode()) {
3480 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3481 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3484 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3485 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3488 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3489 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3491 default: assert(0 && "Unreachable!");
3494 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3495 false/*sign irrelevant*/, Dummy);
3503 MVT::ValueType VT = Node->getValueType(0);
3505 // Expand unsupported unary vector operators by unrolling them.
3506 if (MVT::isVector(VT)) {
3507 Result = LegalizeOp(UnrollVectorOp(Op));
3511 // We always lower FPOWI into a libcall. No target support for it yet.
3512 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3513 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3515 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3516 false/*sign irrelevant*/, Dummy);
3519 case ISD::BIT_CONVERT:
3520 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3521 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3522 Node->getValueType(0));
3523 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3524 // The input has to be a vector type, we have to either scalarize it, pack
3525 // it, or convert it based on whether the input vector type is legal.
3526 SDNode *InVal = Node->getOperand(0).Val;
3527 int InIx = Node->getOperand(0).ResNo;
3528 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
3529 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
3531 // Figure out if there is a simple type corresponding to this Vector
3532 // type. If so, convert to the vector type.
3533 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3534 if (TLI.isTypeLegal(TVT)) {
3535 // Turn this into a bit convert of the vector input.
3536 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3537 LegalizeOp(Node->getOperand(0)));
3539 } else if (NumElems == 1) {
3540 // Turn this into a bit convert of the scalar input.
3541 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3542 ScalarizeVectorOp(Node->getOperand(0)));
3545 // FIXME: UNIMP! Store then reload
3546 assert(0 && "Cast from unsupported vector type not implemented yet!");
3549 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3550 Node->getOperand(0).getValueType())) {
3551 default: assert(0 && "Unknown operation action!");
3552 case TargetLowering::Expand:
3553 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3554 Node->getValueType(0));
3556 case TargetLowering::Legal:
3557 Tmp1 = LegalizeOp(Node->getOperand(0));
3558 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3564 // Conversion operators. The source and destination have different types.
3565 case ISD::SINT_TO_FP:
3566 case ISD::UINT_TO_FP: {
3567 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3568 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3570 switch (TLI.getOperationAction(Node->getOpcode(),
3571 Node->getOperand(0).getValueType())) {
3572 default: assert(0 && "Unknown operation action!");
3573 case TargetLowering::Custom:
3576 case TargetLowering::Legal:
3577 Tmp1 = LegalizeOp(Node->getOperand(0));
3578 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3580 Tmp1 = TLI.LowerOperation(Result, DAG);
3581 if (Tmp1.Val) Result = Tmp1;
3584 case TargetLowering::Expand:
3585 Result = ExpandLegalINT_TO_FP(isSigned,
3586 LegalizeOp(Node->getOperand(0)),
3587 Node->getValueType(0));
3589 case TargetLowering::Promote:
3590 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3591 Node->getValueType(0),
3597 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3598 Node->getValueType(0), Node->getOperand(0));
3601 Tmp1 = PromoteOp(Node->getOperand(0));
3603 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3604 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3606 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3607 Node->getOperand(0).getValueType());
3609 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3610 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3616 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3618 Tmp1 = LegalizeOp(Node->getOperand(0));
3619 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3622 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3624 // Since the result is legal, we should just be able to truncate the low
3625 // part of the source.
3626 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3629 Result = PromoteOp(Node->getOperand(0));
3630 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3635 case ISD::FP_TO_SINT:
3636 case ISD::FP_TO_UINT:
3637 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3639 Tmp1 = LegalizeOp(Node->getOperand(0));
3641 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3642 default: assert(0 && "Unknown operation action!");
3643 case TargetLowering::Custom:
3646 case TargetLowering::Legal:
3647 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3649 Tmp1 = TLI.LowerOperation(Result, DAG);
3650 if (Tmp1.Val) Result = Tmp1;
3653 case TargetLowering::Promote:
3654 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3655 Node->getOpcode() == ISD::FP_TO_SINT);
3657 case TargetLowering::Expand:
3658 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3659 SDOperand True, False;
3660 MVT::ValueType VT = Node->getOperand(0).getValueType();
3661 MVT::ValueType NVT = Node->getValueType(0);
3662 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1;
3663 const uint64_t zero[] = {0, 0};
3664 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3665 uint64_t x = 1ULL << ShiftAmt;
3666 (void)apf.convertFromZeroExtendedInteger
3667 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven);
3668 Tmp2 = DAG.getConstantFP(apf, VT);
3669 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3670 Node->getOperand(0), Tmp2, ISD::SETLT);
3671 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3672 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3673 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3675 False = DAG.getNode(ISD::XOR, NVT, False,
3676 DAG.getConstant(1ULL << ShiftAmt, NVT));
3677 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3680 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3686 MVT::ValueType VT = Op.getValueType();
3687 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3688 // Convert ppcf128 to i32
3689 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3690 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3691 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3692 Node->getOperand(0), DAG.getValueType(MVT::f64));
3693 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3694 DAG.getIntPtrConstant(1));
3695 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3697 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3698 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3699 Tmp2 = DAG.getConstantFP(apf, OVT);
3700 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3701 // FIXME: generated code sucks.
3702 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3703 DAG.getNode(ISD::ADD, MVT::i32,
3704 DAG.getNode(ISD::FP_TO_SINT, VT,
3705 DAG.getNode(ISD::FSUB, OVT,
3706 Node->getOperand(0), Tmp2)),
3707 DAG.getConstant(0x80000000, MVT::i32)),
3708 DAG.getNode(ISD::FP_TO_SINT, VT,
3709 Node->getOperand(0)),
3710 DAG.getCondCode(ISD::SETGE));
3714 // Convert f32 / f64 to i32 / i64.
3715 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3716 switch (Node->getOpcode()) {
3717 case ISD::FP_TO_SINT: {
3718 if (OVT == MVT::f32)
3719 LC = (VT == MVT::i32)
3720 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3721 else if (OVT == MVT::f64)
3722 LC = (VT == MVT::i32)
3723 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3724 else if (OVT == MVT::f80) {
3725 assert(VT == MVT::i64);
3726 LC = RTLIB::FPTOSINT_F80_I64;
3728 else if (OVT == MVT::ppcf128) {
3729 assert(VT == MVT::i64);
3730 LC = RTLIB::FPTOSINT_PPCF128_I64;
3734 case ISD::FP_TO_UINT: {
3735 if (OVT == MVT::f32)
3736 LC = (VT == MVT::i32)
3737 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3738 else if (OVT == MVT::f64)
3739 LC = (VT == MVT::i32)
3740 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3741 else if (OVT == MVT::f80) {
3742 LC = (VT == MVT::i32)
3743 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64;
3745 else if (OVT == MVT::ppcf128) {
3746 assert(VT == MVT::i64);
3747 LC = RTLIB::FPTOUINT_PPCF128_I64;
3751 default: assert(0 && "Unreachable!");
3754 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3755 false/*sign irrelevant*/, Dummy);
3759 Tmp1 = PromoteOp(Node->getOperand(0));
3760 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3761 Result = LegalizeOp(Result);
3766 case ISD::FP_EXTEND: {
3767 MVT::ValueType DstVT = Op.getValueType();
3768 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3769 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3770 // The only other way we can lower this is to turn it into a STORE,
3771 // LOAD pair, targetting a temporary location (a stack slot).
3772 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3775 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3776 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3778 Tmp1 = LegalizeOp(Node->getOperand(0));
3779 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3782 Tmp1 = PromoteOp(Node->getOperand(0));
3783 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3788 case ISD::FP_ROUND: {
3789 MVT::ValueType DstVT = Op.getValueType();
3790 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3791 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3792 if (SrcVT == MVT::ppcf128) {
3794 ExpandOp(Node->getOperand(0), Lo, Result);
3795 // Round it the rest of the way (e.g. to f32) if needed.
3796 if (DstVT!=MVT::f64)
3797 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3800 // The only other way we can lower this is to turn it into a STORE,
3801 // LOAD pair, targetting a temporary location (a stack slot).
3802 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3805 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3806 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3808 Tmp1 = LegalizeOp(Node->getOperand(0));
3809 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3812 Tmp1 = PromoteOp(Node->getOperand(0));
3813 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3814 Node->getOperand(1));
3819 case ISD::ANY_EXTEND:
3820 case ISD::ZERO_EXTEND:
3821 case ISD::SIGN_EXTEND:
3822 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3823 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3825 Tmp1 = LegalizeOp(Node->getOperand(0));
3826 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3829 switch (Node->getOpcode()) {
3830 case ISD::ANY_EXTEND:
3831 Tmp1 = PromoteOp(Node->getOperand(0));
3832 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3834 case ISD::ZERO_EXTEND:
3835 Result = PromoteOp(Node->getOperand(0));
3836 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3837 Result = DAG.getZeroExtendInReg(Result,
3838 Node->getOperand(0).getValueType());
3840 case ISD::SIGN_EXTEND:
3841 Result = PromoteOp(Node->getOperand(0));
3842 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3843 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3845 DAG.getValueType(Node->getOperand(0).getValueType()));
3850 case ISD::FP_ROUND_INREG:
3851 case ISD::SIGN_EXTEND_INREG: {
3852 Tmp1 = LegalizeOp(Node->getOperand(0));
3853 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3855 // If this operation is not supported, convert it to a shl/shr or load/store
3857 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3858 default: assert(0 && "This action not supported for this op yet!");
3859 case TargetLowering::Legal:
3860 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3862 case TargetLowering::Expand:
3863 // If this is an integer extend and shifts are supported, do that.
3864 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3865 // NOTE: we could fall back on load/store here too for targets without
3866 // SAR. However, it is doubtful that any exist.
3867 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3868 MVT::getSizeInBits(ExtraVT);
3869 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3870 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3871 Node->getOperand(0), ShiftCst);
3872 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3874 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3875 // The only way we can lower this is to turn it into a TRUNCSTORE,
3876 // EXTLOAD pair, targetting a temporary location (a stack slot).
3878 // NOTE: there is a choice here between constantly creating new stack
3879 // slots and always reusing the same one. We currently always create
3880 // new ones, as reuse may inhibit scheduling.
3881 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3882 Node->getValueType(0));
3884 assert(0 && "Unknown op");
3890 case ISD::TRAMPOLINE: {
3892 for (unsigned i = 0; i != 6; ++i)
3893 Ops[i] = LegalizeOp(Node->getOperand(i));
3894 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3895 // The only option for this node is to custom lower it.
3896 Result = TLI.LowerOperation(Result, DAG);
3897 assert(Result.Val && "Should always custom lower!");
3899 // Since trampoline produces two values, make sure to remember that we
3900 // legalized both of them.
3901 Tmp1 = LegalizeOp(Result.getValue(1));
3902 Result = LegalizeOp(Result);
3903 AddLegalizedOperand(SDOperand(Node, 0), Result);
3904 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3905 return Op.ResNo ? Tmp1 : Result;
3907 case ISD::FLT_ROUNDS_: {
3908 MVT::ValueType VT = Node->getValueType(0);
3909 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3910 default: assert(0 && "This action not supported for this op yet!");
3911 case TargetLowering::Custom:
3912 Result = TLI.LowerOperation(Op, DAG);
3913 if (Result.Val) break;
3915 case TargetLowering::Legal:
3916 // If this operation is not supported, lower it to constant 1
3917 Result = DAG.getConstant(1, VT);
3922 MVT::ValueType VT = Node->getValueType(0);
3923 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3924 default: assert(0 && "This action not supported for this op yet!");
3925 case TargetLowering::Legal:
3926 Tmp1 = LegalizeOp(Node->getOperand(0));
3927 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3929 case TargetLowering::Custom:
3930 Result = TLI.LowerOperation(Op, DAG);
3931 if (Result.Val) break;
3933 case TargetLowering::Expand:
3934 // If this operation is not supported, lower it to 'abort()' call
3935 Tmp1 = LegalizeOp(Node->getOperand(0));
3936 TargetLowering::ArgListTy Args;
3937 std::pair<SDOperand,SDOperand> CallResult =
3938 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
3939 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3941 Result = CallResult.second;
3948 assert(Result.getValueType() == Op.getValueType() &&
3949 "Bad legalization!");
3951 // Make sure that the generated code is itself legal.
3953 Result = LegalizeOp(Result);
3955 // Note that LegalizeOp may be reentered even from single-use nodes, which
3956 // means that we always must cache transformed nodes.
3957 AddLegalizedOperand(Op, Result);
3961 /// PromoteOp - Given an operation that produces a value in an invalid type,
3962 /// promote it to compute the value into a larger type. The produced value will
3963 /// have the correct bits for the low portion of the register, but no guarantee
3964 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3965 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3966 MVT::ValueType VT = Op.getValueType();
3967 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3968 assert(getTypeAction(VT) == Promote &&
3969 "Caller should expand or legalize operands that are not promotable!");
3970 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3971 "Cannot promote to smaller type!");
3973 SDOperand Tmp1, Tmp2, Tmp3;
3975 SDNode *Node = Op.Val;
3977 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3978 if (I != PromotedNodes.end()) return I->second;
3980 switch (Node->getOpcode()) {
3981 case ISD::CopyFromReg:
3982 assert(0 && "CopyFromReg must be legal!");
3985 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
3987 assert(0 && "Do not know how to promote this operator!");
3990 Result = DAG.getNode(ISD::UNDEF, NVT);
3994 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3996 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3997 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3999 case ISD::ConstantFP:
4000 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4001 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4005 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
4006 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
4007 Node->getOperand(1), Node->getOperand(2));
4011 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4013 Result = LegalizeOp(Node->getOperand(0));
4014 assert(Result.getValueType() >= NVT &&
4015 "This truncation doesn't make sense!");
4016 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
4017 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4020 // The truncation is not required, because we don't guarantee anything
4021 // about high bits anyway.
4022 Result = PromoteOp(Node->getOperand(0));
4025 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4026 // Truncate the low part of the expanded value to the result type
4027 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4030 case ISD::SIGN_EXTEND:
4031 case ISD::ZERO_EXTEND:
4032 case ISD::ANY_EXTEND:
4033 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4034 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4036 // Input is legal? Just do extend all the way to the larger type.
4037 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4040 // Promote the reg if it's smaller.
4041 Result = PromoteOp(Node->getOperand(0));
4042 // The high bits are not guaranteed to be anything. Insert an extend.
4043 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4044 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4045 DAG.getValueType(Node->getOperand(0).getValueType()));
4046 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4047 Result = DAG.getZeroExtendInReg(Result,
4048 Node->getOperand(0).getValueType());
4052 case ISD::BIT_CONVERT:
4053 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4054 Node->getValueType(0));
4055 Result = PromoteOp(Result);
4058 case ISD::FP_EXTEND:
4059 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4061 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4062 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4063 case Promote: assert(0 && "Unreachable with 2 FP types!");
4065 if (Node->getConstantOperandVal(1) == 0) {
4066 // Input is legal? Do an FP_ROUND_INREG.
4067 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4068 DAG.getValueType(VT));
4070 // Just remove the truncate, it isn't affecting the value.
4071 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4072 Node->getOperand(1));
4077 case ISD::SINT_TO_FP:
4078 case ISD::UINT_TO_FP:
4079 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4081 // No extra round required here.
4082 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4086 Result = PromoteOp(Node->getOperand(0));
4087 if (Node->getOpcode() == ISD::SINT_TO_FP)
4088 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4090 DAG.getValueType(Node->getOperand(0).getValueType()));
4092 Result = DAG.getZeroExtendInReg(Result,
4093 Node->getOperand(0).getValueType());
4094 // No extra round required here.
4095 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4098 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4099 Node->getOperand(0));
4100 // Round if we cannot tolerate excess precision.
4101 if (NoExcessFPPrecision)
4102 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4103 DAG.getValueType(VT));
4108 case ISD::SIGN_EXTEND_INREG:
4109 Result = PromoteOp(Node->getOperand(0));
4110 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4111 Node->getOperand(1));
4113 case ISD::FP_TO_SINT:
4114 case ISD::FP_TO_UINT:
4115 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4118 Tmp1 = Node->getOperand(0);
4121 // The input result is prerounded, so we don't have to do anything
4123 Tmp1 = PromoteOp(Node->getOperand(0));
4126 // If we're promoting a UINT to a larger size, check to see if the new node
4127 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4128 // we can use that instead. This allows us to generate better code for
4129 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4130 // legal, such as PowerPC.
4131 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4132 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4133 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4134 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4135 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4137 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4143 Tmp1 = PromoteOp(Node->getOperand(0));
4144 assert(Tmp1.getValueType() == NVT);
4145 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4146 // NOTE: we do not have to do any extra rounding here for
4147 // NoExcessFPPrecision, because we know the input will have the appropriate
4148 // precision, and these operations don't modify precision at all.
4154 Tmp1 = PromoteOp(Node->getOperand(0));
4155 assert(Tmp1.getValueType() == NVT);
4156 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4157 if (NoExcessFPPrecision)
4158 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4159 DAG.getValueType(VT));
4163 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4164 // directly as well, which may be better.
4165 Tmp1 = PromoteOp(Node->getOperand(0));
4166 assert(Tmp1.getValueType() == NVT);
4167 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4168 if (NoExcessFPPrecision)
4169 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4170 DAG.getValueType(VT));
4180 // The input may have strange things in the top bits of the registers, but
4181 // these operations don't care. They may have weird bits going out, but
4182 // that too is okay if they are integer operations.
4183 Tmp1 = PromoteOp(Node->getOperand(0));
4184 Tmp2 = PromoteOp(Node->getOperand(1));
4185 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4186 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4191 Tmp1 = PromoteOp(Node->getOperand(0));
4192 Tmp2 = PromoteOp(Node->getOperand(1));
4193 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4194 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4196 // Floating point operations will give excess precision that we may not be
4197 // able to tolerate. If we DO allow excess precision, just leave it,
4198 // otherwise excise it.
4199 // FIXME: Why would we need to round FP ops more than integer ones?
4200 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4201 if (NoExcessFPPrecision)
4202 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4203 DAG.getValueType(VT));
4208 // These operators require that their input be sign extended.
4209 Tmp1 = PromoteOp(Node->getOperand(0));
4210 Tmp2 = PromoteOp(Node->getOperand(1));
4211 if (MVT::isInteger(NVT)) {
4212 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4213 DAG.getValueType(VT));
4214 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4215 DAG.getValueType(VT));
4217 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4219 // Perform FP_ROUND: this is probably overly pessimistic.
4220 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
4221 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4222 DAG.getValueType(VT));
4226 case ISD::FCOPYSIGN:
4227 // These operators require that their input be fp extended.
4228 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4229 case Expand: assert(0 && "not implemented");
4230 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4231 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4233 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4234 case Expand: assert(0 && "not implemented");
4235 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4236 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4238 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4240 // Perform FP_ROUND: this is probably overly pessimistic.
4241 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4242 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4243 DAG.getValueType(VT));
4248 // These operators require that their input be zero extended.
4249 Tmp1 = PromoteOp(Node->getOperand(0));
4250 Tmp2 = PromoteOp(Node->getOperand(1));
4251 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
4252 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4253 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4254 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4258 Tmp1 = PromoteOp(Node->getOperand(0));
4259 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4262 // The input value must be properly sign extended.
4263 Tmp1 = PromoteOp(Node->getOperand(0));
4264 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4265 DAG.getValueType(VT));
4266 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4269 // The input value must be properly zero extended.
4270 Tmp1 = PromoteOp(Node->getOperand(0));
4271 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4272 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4276 Tmp1 = Node->getOperand(0); // Get the chain.
4277 Tmp2 = Node->getOperand(1); // Get the pointer.
4278 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4279 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4280 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
4282 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4283 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4284 // Increment the pointer, VAList, to the next vaarg
4285 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4286 DAG.getConstant(MVT::getSizeInBits(VT)/8,
4287 TLI.getPointerTy()));
4288 // Store the incremented VAList to the legalized pointer
4289 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4290 // Load the actual argument out of the pointer VAList
4291 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4293 // Remember that we legalized the chain.
4294 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4298 LoadSDNode *LD = cast<LoadSDNode>(Node);
4299 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4300 ? ISD::EXTLOAD : LD->getExtensionType();
4301 Result = DAG.getExtLoad(ExtType, NVT,
4302 LD->getChain(), LD->getBasePtr(),
4303 LD->getSrcValue(), LD->getSrcValueOffset(),
4306 LD->getAlignment());
4307 // Remember that we legalized the chain.
4308 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4312 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4313 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4314 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
4316 case ISD::SELECT_CC:
4317 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4318 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4319 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4320 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4323 Tmp1 = Node->getOperand(0);
4324 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4325 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4326 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4327 DAG.getConstant(MVT::getSizeInBits(NVT) -
4328 MVT::getSizeInBits(VT),
4329 TLI.getShiftAmountTy()));
4334 // Zero extend the argument
4335 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4336 // Perform the larger operation, then subtract if needed.
4337 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4338 switch(Node->getOpcode()) {
4343 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4344 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
4345 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
4347 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4348 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
4351 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4352 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4353 DAG.getConstant(MVT::getSizeInBits(NVT) -
4354 MVT::getSizeInBits(VT), NVT));
4358 case ISD::EXTRACT_SUBVECTOR:
4359 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4361 case ISD::EXTRACT_VECTOR_ELT:
4362 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4366 assert(Result.Val && "Didn't set a result!");
4368 // Make sure the result is itself legal.
4369 Result = LegalizeOp(Result);
4371 // Remember that we promoted this!
4372 AddPromotedOperand(Op, Result);
4376 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4377 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4378 /// based on the vector type. The return type of this matches the element type
4379 /// of the vector, which may not be legal for the target.
4380 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4381 // We know that operand #0 is the Vec vector. If the index is a constant
4382 // or if the invec is a supported hardware type, we can use it. Otherwise,
4383 // lower to a store then an indexed load.
4384 SDOperand Vec = Op.getOperand(0);
4385 SDOperand Idx = Op.getOperand(1);
4387 MVT::ValueType TVT = Vec.getValueType();
4388 unsigned NumElems = MVT::getVectorNumElements(TVT);
4390 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4391 default: assert(0 && "This action is not supported yet!");
4392 case TargetLowering::Custom: {
4393 Vec = LegalizeOp(Vec);
4394 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4395 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4400 case TargetLowering::Legal:
4401 if (isTypeLegal(TVT)) {
4402 Vec = LegalizeOp(Vec);
4403 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4407 case TargetLowering::Expand:
4411 if (NumElems == 1) {
4412 // This must be an access of the only element. Return it.
4413 Op = ScalarizeVectorOp(Vec);
4414 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4415 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4416 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4418 SplitVectorOp(Vec, Lo, Hi);
4419 if (CIdx->getValue() < NumLoElts) {
4423 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4424 Idx.getValueType());
4427 // It's now an extract from the appropriate high or low part. Recurse.
4428 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4429 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4431 // Store the value to a temporary stack slot, then LOAD the scalar
4432 // element back out.
4433 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4434 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4436 // Add the offset to the index.
4437 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
4438 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4439 DAG.getConstant(EltSize, Idx.getValueType()));
4441 if (MVT::getSizeInBits(Idx.getValueType()) >
4442 MVT::getSizeInBits(TLI.getPointerTy()))
4443 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4445 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4447 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4449 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4454 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4455 /// we assume the operation can be split if it is not already legal.
4456 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4457 // We know that operand #0 is the Vec vector. For now we assume the index
4458 // is a constant and that the extracted result is a supported hardware type.
4459 SDOperand Vec = Op.getOperand(0);
4460 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4462 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
4464 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
4465 // This must be an access of the desired vector length. Return it.
4469 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4471 SplitVectorOp(Vec, Lo, Hi);
4472 if (CIdx->getValue() < NumElems/2) {
4476 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4479 // It's now an extract from the appropriate high or low part. Recurse.
4480 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4481 return ExpandEXTRACT_SUBVECTOR(Op);
4484 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4485 /// with condition CC on the current target. This usually involves legalizing
4486 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4487 /// there may be no choice but to create a new SetCC node to represent the
4488 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4489 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4490 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4493 SDOperand Tmp1, Tmp2, Tmp3, Result;
4495 switch (getTypeAction(LHS.getValueType())) {
4497 Tmp1 = LegalizeOp(LHS); // LHS
4498 Tmp2 = LegalizeOp(RHS); // RHS
4501 Tmp1 = PromoteOp(LHS); // LHS
4502 Tmp2 = PromoteOp(RHS); // RHS
4504 // If this is an FP compare, the operands have already been extended.
4505 if (MVT::isInteger(LHS.getValueType())) {
4506 MVT::ValueType VT = LHS.getValueType();
4507 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4509 // Otherwise, we have to insert explicit sign or zero extends. Note
4510 // that we could insert sign extends for ALL conditions, but zero extend
4511 // is cheaper on many machines (an AND instead of two shifts), so prefer
4513 switch (cast<CondCodeSDNode>(CC)->get()) {
4514 default: assert(0 && "Unknown integer comparison!");
4521 // ALL of these operations will work if we either sign or zero extend
4522 // the operands (including the unsigned comparisons!). Zero extend is
4523 // usually a simpler/cheaper operation, so prefer it.
4524 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4525 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4531 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4532 DAG.getValueType(VT));
4533 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4534 DAG.getValueType(VT));
4540 MVT::ValueType VT = LHS.getValueType();
4541 if (VT == MVT::f32 || VT == MVT::f64) {
4542 // Expand into one or more soft-fp libcall(s).
4543 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4544 switch (cast<CondCodeSDNode>(CC)->get()) {
4547 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4551 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4555 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4559 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4563 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4567 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4570 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4573 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4576 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4577 switch (cast<CondCodeSDNode>(CC)->get()) {
4579 // SETONE = SETOLT | SETOGT
4580 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4583 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4586 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4589 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4592 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4595 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4597 default: assert(0 && "Unsupported FP setcc!");
4602 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4603 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4604 false /*sign irrelevant*/, Dummy);
4605 Tmp2 = DAG.getConstant(0, MVT::i32);
4606 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4607 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4608 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4609 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4610 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4611 false /*sign irrelevant*/, Dummy);
4612 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4613 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4614 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4622 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4623 ExpandOp(LHS, LHSLo, LHSHi);
4624 ExpandOp(RHS, RHSLo, RHSHi);
4625 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4627 if (VT==MVT::ppcf128) {
4628 // FIXME: This generated code sucks. We want to generate
4629 // FCMP crN, hi1, hi2
4631 // FCMP crN, lo1, lo2
4632 // The following can be improved, but not that much.
4633 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4634 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
4635 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4636 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
4637 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
4638 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4639 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4648 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4649 if (RHSCST->isAllOnesValue()) {
4650 // Comparison to -1.
4651 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4656 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4657 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4658 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4659 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4662 // If this is a comparison of the sign bit, just look at the top part.
4664 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4665 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4666 CST->getValue() == 0) || // X < 0
4667 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4668 CST->isAllOnesValue())) { // X > -1
4674 // FIXME: This generated code sucks.
4675 ISD::CondCode LowCC;
4677 default: assert(0 && "Unknown integer setcc!");
4679 case ISD::SETULT: LowCC = ISD::SETULT; break;
4681 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4683 case ISD::SETULE: LowCC = ISD::SETULE; break;
4685 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4688 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4689 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4690 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4692 // NOTE: on targets without efficient SELECT of bools, we can always use
4693 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4694 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4695 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4696 false, DagCombineInfo);
4698 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4699 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4700 CCCode, false, DagCombineInfo);
4702 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC);
4704 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4705 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4706 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4707 (Tmp2C && Tmp2C->getValue() == 0 &&
4708 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4709 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4710 (Tmp2C && Tmp2C->getValue() == 1 &&
4711 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4712 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4713 // low part is known false, returns high part.
4714 // For LE / GE, if high part is known false, ignore the low part.
4715 // For LT / GT, if high part is known true, ignore the low part.
4719 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4720 ISD::SETEQ, false, DagCombineInfo);
4722 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4723 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4724 Result, Tmp1, Tmp2));
4735 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4736 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4737 /// a load from the stack slot to DestVT, extending it if needed.
4738 /// The resultant code need not be legal.
4739 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4740 MVT::ValueType SlotVT,
4741 MVT::ValueType DestVT) {
4742 // Create the stack frame object.
4743 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
4745 FrameIndexSDNode *StackPtrFI = dyn_cast<FrameIndexSDNode>(FIPtr);
4747 int SPFI = StackPtrFI->getIndex();
4749 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType());
4750 unsigned SlotSize = MVT::getSizeInBits(SlotVT);
4751 unsigned DestSize = MVT::getSizeInBits(DestVT);
4753 // Emit a store to the stack slot. Use a truncstore if the input value is
4754 // later than DestVT.
4756 if (SrcSize > SlotSize)
4757 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4758 &PseudoSourceValue::FPRel, SPFI, SlotVT);
4760 assert(SrcSize == SlotSize && "Invalid store");
4761 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4762 &PseudoSourceValue::FPRel, SPFI, SlotVT);
4765 // Result is a load from the stack slot.
4766 if (SlotSize == DestSize)
4767 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4769 assert(SlotSize < DestSize && "Unknown extension!");
4770 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT);
4773 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4774 // Create a vector sized/aligned stack slot, store the value to element #0,
4775 // then load the whole vector back out.
4776 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4778 FrameIndexSDNode *StackPtrFI = dyn_cast<FrameIndexSDNode>(StackPtr);
4780 int SPFI = StackPtrFI->getIndex();
4782 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4783 &PseudoSourceValue::FPRel, SPFI);
4784 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4785 &PseudoSourceValue::FPRel, SPFI);
4789 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4790 /// support the operation, but do support the resultant vector type.
4791 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4793 // If the only non-undef value is the low element, turn this into a
4794 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4795 unsigned NumElems = Node->getNumOperands();
4796 bool isOnlyLowElement = true;
4797 SDOperand SplatValue = Node->getOperand(0);
4798 std::map<SDOperand, std::vector<unsigned> > Values;
4799 Values[SplatValue].push_back(0);
4800 bool isConstant = true;
4801 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4802 SplatValue.getOpcode() != ISD::UNDEF)
4805 for (unsigned i = 1; i < NumElems; ++i) {
4806 SDOperand V = Node->getOperand(i);
4807 Values[V].push_back(i);
4808 if (V.getOpcode() != ISD::UNDEF)
4809 isOnlyLowElement = false;
4810 if (SplatValue != V)
4811 SplatValue = SDOperand(0,0);
4813 // If this isn't a constant element or an undef, we can't use a constant
4815 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4816 V.getOpcode() != ISD::UNDEF)
4820 if (isOnlyLowElement) {
4821 // If the low element is an undef too, then this whole things is an undef.
4822 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4823 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4824 // Otherwise, turn this into a scalar_to_vector node.
4825 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4826 Node->getOperand(0));
4829 // If all elements are constants, create a load from the constant pool.
4831 MVT::ValueType VT = Node->getValueType(0);
4833 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4834 std::vector<Constant*> CV;
4835 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4836 if (ConstantFPSDNode *V =
4837 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4838 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4839 } else if (ConstantSDNode *V =
4840 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4841 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4843 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4844 CV.push_back(UndefValue::get(OpNTy));
4847 Constant *CP = ConstantVector::get(CV);
4848 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4849 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4850 &PseudoSourceValue::CPRel, 0);
4853 if (SplatValue.Val) { // Splat of one value?
4854 // Build the shuffle constant vector: <0, 0, 0, 0>
4855 MVT::ValueType MaskVT =
4856 MVT::getIntVectorWithNumElements(NumElems);
4857 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4858 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4859 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4860 &ZeroVec[0], ZeroVec.size());
4862 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4863 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4864 // Get the splatted value into the low element of a vector register.
4865 SDOperand LowValVec =
4866 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4868 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4869 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4870 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4875 // If there are only two unique elements, we may be able to turn this into a
4877 if (Values.size() == 2) {
4878 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4879 MVT::ValueType MaskVT =
4880 MVT::getIntVectorWithNumElements(NumElems);
4881 std::vector<SDOperand> MaskVec(NumElems);
4883 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4884 E = Values.end(); I != E; ++I) {
4885 for (std::vector<unsigned>::iterator II = I->second.begin(),
4886 EE = I->second.end(); II != EE; ++II)
4887 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4890 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4891 &MaskVec[0], MaskVec.size());
4893 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4894 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4895 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4896 SmallVector<SDOperand, 8> Ops;
4897 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4898 E = Values.end(); I != E; ++I) {
4899 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4903 Ops.push_back(ShuffleMask);
4905 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4906 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4907 &Ops[0], Ops.size());
4911 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4912 // aligned object on the stack, store each element into it, then load
4913 // the result as a vector.
4914 MVT::ValueType VT = Node->getValueType(0);
4915 // Create the stack frame object.
4916 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
4918 // Emit a store of each element to the stack slot.
4919 SmallVector<SDOperand, 8> Stores;
4920 unsigned TypeByteSize =
4921 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4922 // Store (in the right endianness) the elements to memory.
4923 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4924 // Ignore undef elements.
4925 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4927 unsigned Offset = TypeByteSize*i;
4929 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4930 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4932 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4936 SDOperand StoreChain;
4937 if (!Stores.empty()) // Not all undef elements?
4938 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4939 &Stores[0], Stores.size());
4941 StoreChain = DAG.getEntryNode();
4943 // Result is a load from the stack slot.
4944 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4947 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4948 SDOperand Op, SDOperand Amt,
4949 SDOperand &Lo, SDOperand &Hi) {
4950 // Expand the subcomponents.
4951 SDOperand LHSL, LHSH;
4952 ExpandOp(Op, LHSL, LHSH);
4954 SDOperand Ops[] = { LHSL, LHSH, Amt };
4955 MVT::ValueType VT = LHSL.getValueType();
4956 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4957 Hi = Lo.getValue(1);
4961 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4962 /// smaller elements. If we can't find a way that is more efficient than a
4963 /// libcall on this target, return false. Otherwise, return true with the
4964 /// low-parts expanded into Lo and Hi.
4965 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4966 SDOperand &Lo, SDOperand &Hi) {
4967 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4968 "This is not a shift!");
4970 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4971 SDOperand ShAmt = LegalizeOp(Amt);
4972 MVT::ValueType ShTy = ShAmt.getValueType();
4973 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4974 unsigned NVTBits = MVT::getSizeInBits(NVT);
4976 // Handle the case when Amt is an immediate.
4977 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4978 unsigned Cst = CN->getValue();
4979 // Expand the incoming operand to be shifted, so that we have its parts
4981 ExpandOp(Op, InL, InH);
4985 Lo = DAG.getConstant(0, NVT);
4986 Hi = DAG.getConstant(0, NVT);
4987 } else if (Cst > NVTBits) {
4988 Lo = DAG.getConstant(0, NVT);
4989 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4990 } else if (Cst == NVTBits) {
4991 Lo = DAG.getConstant(0, NVT);
4994 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4995 Hi = DAG.getNode(ISD::OR, NVT,
4996 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4997 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5002 Lo = DAG.getConstant(0, NVT);
5003 Hi = DAG.getConstant(0, NVT);
5004 } else if (Cst > NVTBits) {
5005 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5006 Hi = DAG.getConstant(0, NVT);
5007 } else if (Cst == NVTBits) {
5009 Hi = DAG.getConstant(0, NVT);
5011 Lo = DAG.getNode(ISD::OR, NVT,
5012 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5013 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5014 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5019 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5020 DAG.getConstant(NVTBits-1, ShTy));
5021 } else if (Cst > NVTBits) {
5022 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5023 DAG.getConstant(Cst-NVTBits, ShTy));
5024 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5025 DAG.getConstant(NVTBits-1, ShTy));
5026 } else if (Cst == NVTBits) {
5028 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5029 DAG.getConstant(NVTBits-1, ShTy));
5031 Lo = DAG.getNode(ISD::OR, NVT,
5032 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5033 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5034 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5040 // Okay, the shift amount isn't constant. However, if we can tell that it is
5041 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5042 uint64_t Mask = NVTBits, KnownZero, KnownOne;
5043 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5045 // If we know that the high bit of the shift amount is one, then we can do
5046 // this as a couple of simple shifts.
5047 if (KnownOne & Mask) {
5048 // Mask out the high bit, which we know is set.
5049 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5050 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5052 // Expand the incoming operand to be shifted, so that we have its parts
5054 ExpandOp(Op, InL, InH);
5057 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5058 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5061 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5062 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5065 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5066 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5067 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5072 // If we know that the high bit of the shift amount is zero, then we can do
5073 // this as a couple of simple shifts.
5074 if (KnownZero & Mask) {
5076 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5077 DAG.getConstant(NVTBits, Amt.getValueType()),
5080 // Expand the incoming operand to be shifted, so that we have its parts
5082 ExpandOp(Op, InL, InH);
5085 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5086 Hi = DAG.getNode(ISD::OR, NVT,
5087 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5088 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5091 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5092 Lo = DAG.getNode(ISD::OR, NVT,
5093 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5094 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5097 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5098 Lo = DAG.getNode(ISD::OR, NVT,
5099 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5100 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5109 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5110 // does not fit into a register, return the lo part and set the hi part to the
5111 // by-reg argument. If it does fit into a single register, return the result
5112 // and leave the Hi part unset.
5113 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
5114 bool isSigned, SDOperand &Hi) {
5115 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5116 // The input chain to this libcall is the entry node of the function.
5117 // Legalizing the call will automatically add the previous call to the
5119 SDOperand InChain = DAG.getEntryNode();
5121 TargetLowering::ArgListTy Args;
5122 TargetLowering::ArgListEntry Entry;
5123 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5124 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
5125 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
5126 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5127 Entry.isSExt = isSigned;
5128 Args.push_back(Entry);
5130 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
5132 // Splice the libcall in wherever FindInputOutputChains tells us to.
5133 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
5134 std::pair<SDOperand,SDOperand> CallInfo =
5135 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
5138 // Legalize the call sequence, starting with the chain. This will advance
5139 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5140 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5141 LegalizeOp(CallInfo.second);
5143 switch (getTypeAction(CallInfo.first.getValueType())) {
5144 default: assert(0 && "Unknown thing");
5146 Result = CallInfo.first;
5149 ExpandOp(CallInfo.first, Result, Hi);
5156 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5158 SDOperand SelectionDAGLegalize::
5159 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
5160 assert(getTypeAction(Source.getValueType()) == Expand &&
5161 "This is not an expansion!");
5162 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
5165 assert(Source.getValueType() == MVT::i64 &&
5166 "This only works for 64-bit -> FP");
5167 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
5168 // incoming integer is set. To handle this, we dynamically test to see if
5169 // it is set, and, if so, add a fudge factor.
5171 ExpandOp(Source, Lo, Hi);
5173 // If this is unsigned, and not supported, first perform the conversion to
5174 // signed, then adjust the result if the sign bit is set.
5175 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
5176 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
5178 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
5179 DAG.getConstant(0, Hi.getValueType()),
5181 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5182 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5183 SignSet, Four, Zero);
5184 uint64_t FF = 0x5f800000ULL;
5185 if (TLI.isLittleEndian()) FF <<= 32;
5186 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5188 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5189 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5190 SDOperand FudgeInReg;
5191 if (DestTy == MVT::f32)
5192 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5193 &PseudoSourceValue::CPRel, 0);
5194 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
5195 // FIXME: Avoid the extend by construction the right constantpool?
5196 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5197 CPIdx, &PseudoSourceValue::CPRel, 0,
5200 assert(0 && "Unexpected conversion");
5202 MVT::ValueType SCVT = SignedConv.getValueType();
5203 if (SCVT != DestTy) {
5204 // Destination type needs to be expanded as well. The FADD now we are
5205 // constructing will be expanded into a libcall.
5206 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
5207 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
5208 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
5209 SignedConv, SignedConv.getValue(1));
5211 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5213 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5216 // Check to see if the target has a custom way to lower this. If so, use it.
5217 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
5218 default: assert(0 && "This action not implemented for this operation!");
5219 case TargetLowering::Legal:
5220 case TargetLowering::Expand:
5221 break; // This case is handled below.
5222 case TargetLowering::Custom: {
5223 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5226 return LegalizeOp(NV);
5227 break; // The target decided this was legal after all
5231 // Expand the source, then glue it back together for the call. We must expand
5232 // the source in case it is shared (this pass of legalize must traverse it).
5233 SDOperand SrcLo, SrcHi;
5234 ExpandOp(Source, SrcLo, SrcHi);
5235 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
5238 if (DestTy == MVT::f32)
5239 LC = RTLIB::SINTTOFP_I64_F32;
5241 assert(DestTy == MVT::f64 && "Unknown fp value type!");
5242 LC = RTLIB::SINTTOFP_I64_F64;
5245 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
5246 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5247 SDOperand UnusedHiPart;
5248 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
5252 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5253 /// INT_TO_FP operation of the specified operand when the target requests that
5254 /// we expand it. At this point, we know that the result and operand types are
5255 /// legal for the target.
5256 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5258 MVT::ValueType DestVT) {
5259 if (Op0.getValueType() == MVT::i32) {
5260 // simple 32-bit [signed|unsigned] integer to float/double expansion
5262 // Get the stack frame index of a 8 byte buffer.
5263 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5265 // word offset constant for Hi/Lo address computation
5266 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5267 // set up Hi and Lo (into buffer) address based on endian
5268 SDOperand Hi = StackSlot;
5269 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5270 if (TLI.isLittleEndian())
5273 // if signed map to unsigned space
5274 SDOperand Op0Mapped;
5276 // constant used to invert sign bit (signed to unsigned mapping)
5277 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5278 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5282 // store the lo of the constructed double - based on integer input
5283 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5284 Op0Mapped, Lo, NULL, 0);
5285 // initial hi portion of constructed double
5286 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5287 // store the hi of the constructed double - biased exponent
5288 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5289 // load the constructed double
5290 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5291 // FP constant to bias correct the final result
5292 SDOperand Bias = DAG.getConstantFP(isSigned ?
5293 BitsToDouble(0x4330000080000000ULL)
5294 : BitsToDouble(0x4330000000000000ULL),
5296 // subtract the bias
5297 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5300 // handle final rounding
5301 if (DestVT == MVT::f64) {
5304 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
5305 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5306 DAG.getIntPtrConstant(0));
5307 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
5308 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5312 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5313 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5315 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
5316 DAG.getConstant(0, Op0.getValueType()),
5318 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5319 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5320 SignSet, Four, Zero);
5322 // If the sign bit of the integer is set, the large number will be treated
5323 // as a negative number. To counteract this, the dynamic code adds an
5324 // offset depending on the data type.
5326 switch (Op0.getValueType()) {
5327 default: assert(0 && "Unsupported integer type!");
5328 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5329 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5330 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5331 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5333 if (TLI.isLittleEndian()) FF <<= 32;
5334 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5336 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5337 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5338 SDOperand FudgeInReg;
5339 if (DestVT == MVT::f32)
5340 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5341 &PseudoSourceValue::CPRel, 0);
5343 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5344 DAG.getEntryNode(), CPIdx,
5345 &PseudoSourceValue::CPRel, 0,
5349 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5352 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5353 /// *INT_TO_FP operation of the specified operand when the target requests that
5354 /// we promote it. At this point, we know that the result and operand types are
5355 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5356 /// operation that takes a larger input.
5357 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5358 MVT::ValueType DestVT,
5360 // First step, figure out the appropriate *INT_TO_FP operation to use.
5361 MVT::ValueType NewInTy = LegalOp.getValueType();
5363 unsigned OpToUse = 0;
5365 // Scan for the appropriate larger type to use.
5367 NewInTy = (MVT::ValueType)(NewInTy+1);
5368 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
5370 // If the target supports SINT_TO_FP of this type, use it.
5371 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5373 case TargetLowering::Legal:
5374 if (!TLI.isTypeLegal(NewInTy))
5375 break; // Can't use this datatype.
5377 case TargetLowering::Custom:
5378 OpToUse = ISD::SINT_TO_FP;
5382 if (isSigned) continue;
5384 // If the target supports UINT_TO_FP of this type, use it.
5385 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5387 case TargetLowering::Legal:
5388 if (!TLI.isTypeLegal(NewInTy))
5389 break; // Can't use this datatype.
5391 case TargetLowering::Custom:
5392 OpToUse = ISD::UINT_TO_FP;
5397 // Otherwise, try a larger type.
5400 // Okay, we found the operation and type to use. Zero extend our input to the
5401 // desired type then run the operation on it.
5402 return DAG.getNode(OpToUse, DestVT,
5403 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5407 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5408 /// FP_TO_*INT operation of the specified operand when the target requests that
5409 /// we promote it. At this point, we know that the result and operand types are
5410 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5411 /// operation that returns a larger result.
5412 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5413 MVT::ValueType DestVT,
5415 // First step, figure out the appropriate FP_TO*INT operation to use.
5416 MVT::ValueType NewOutTy = DestVT;
5418 unsigned OpToUse = 0;
5420 // Scan for the appropriate larger type to use.
5422 NewOutTy = (MVT::ValueType)(NewOutTy+1);
5423 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
5425 // If the target supports FP_TO_SINT returning this type, use it.
5426 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5428 case TargetLowering::Legal:
5429 if (!TLI.isTypeLegal(NewOutTy))
5430 break; // Can't use this datatype.
5432 case TargetLowering::Custom:
5433 OpToUse = ISD::FP_TO_SINT;
5438 // If the target supports FP_TO_UINT of this type, use it.
5439 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5441 case TargetLowering::Legal:
5442 if (!TLI.isTypeLegal(NewOutTy))
5443 break; // Can't use this datatype.
5445 case TargetLowering::Custom:
5446 OpToUse = ISD::FP_TO_UINT;
5451 // Otherwise, try a larger type.
5455 // Okay, we found the operation and type to use.
5456 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5458 // If the operation produces an invalid type, it must be custom lowered. Use
5459 // the target lowering hooks to expand it. Just keep the low part of the
5460 // expanded operation, we know that we're truncating anyway.
5461 if (getTypeAction(NewOutTy) == Expand) {
5462 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
5463 assert(Operation.Val && "Didn't return anything");
5466 // Truncate the result of the extended FP_TO_*INT operation to the desired
5468 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5471 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5473 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5474 MVT::ValueType VT = Op.getValueType();
5475 MVT::ValueType SHVT = TLI.getShiftAmountTy();
5476 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5478 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5480 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5481 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5482 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5484 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5485 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5486 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5487 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5488 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5489 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5490 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5491 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5492 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5494 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5495 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5496 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5497 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5498 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5499 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5500 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5501 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5502 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5503 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5504 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5505 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5506 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5507 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5508 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5509 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5510 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5511 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5512 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5513 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5514 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5518 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5520 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5522 default: assert(0 && "Cannot expand this yet!");
5524 static const uint64_t mask[6] = {
5525 0x5555555555555555ULL, 0x3333333333333333ULL,
5526 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5527 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5529 MVT::ValueType VT = Op.getValueType();
5530 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5531 unsigned len = MVT::getSizeInBits(VT);
5532 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5533 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5534 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5535 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5536 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5537 DAG.getNode(ISD::AND, VT,
5538 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5543 // for now, we do this:
5544 // x = x | (x >> 1);
5545 // x = x | (x >> 2);
5547 // x = x | (x >>16);
5548 // x = x | (x >>32); // for 64-bit input
5549 // return popcount(~x);
5551 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5552 MVT::ValueType VT = Op.getValueType();
5553 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5554 unsigned len = MVT::getSizeInBits(VT);
5555 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5556 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5557 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5559 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5560 return DAG.getNode(ISD::CTPOP, VT, Op);
5563 // for now, we use: { return popcount(~x & (x - 1)); }
5564 // unless the target has ctlz but not ctpop, in which case we use:
5565 // { return 32 - nlz(~x & (x-1)); }
5566 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5567 MVT::ValueType VT = Op.getValueType();
5568 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5569 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5570 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5571 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5572 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5573 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5574 TLI.isOperationLegal(ISD::CTLZ, VT))
5575 return DAG.getNode(ISD::SUB, VT,
5576 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5577 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5578 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5583 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5584 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5585 /// LegalizeNodes map is filled in for any results that are not expanded, the
5586 /// ExpandedNodes map is filled in for any results that are expanded, and the
5587 /// Lo/Hi values are returned.
5588 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5589 MVT::ValueType VT = Op.getValueType();
5590 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5591 SDNode *Node = Op.Val;
5592 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5593 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5594 MVT::isVector(VT)) &&
5595 "Cannot expand to FP value or to larger int value!");
5597 // See if we already expanded it.
5598 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5599 = ExpandedNodes.find(Op);
5600 if (I != ExpandedNodes.end()) {
5601 Lo = I->second.first;
5602 Hi = I->second.second;
5606 switch (Node->getOpcode()) {
5607 case ISD::CopyFromReg:
5608 assert(0 && "CopyFromReg must be legal!");
5609 case ISD::FP_ROUND_INREG:
5610 if (VT == MVT::ppcf128 &&
5611 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5612 TargetLowering::Custom) {
5613 SDOperand SrcLo, SrcHi, Src;
5614 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5615 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5616 SDOperand Result = TLI.LowerOperation(
5617 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5618 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5619 Lo = Result.Val->getOperand(0);
5620 Hi = Result.Val->getOperand(1);
5626 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5628 assert(0 && "Do not know how to expand this operator!");
5630 case ISD::EXTRACT_VECTOR_ELT:
5631 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5632 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5633 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5634 return ExpandOp(Lo, Lo, Hi);
5636 NVT = TLI.getTypeToExpandTo(VT);
5637 Lo = DAG.getNode(ISD::UNDEF, NVT);
5638 Hi = DAG.getNode(ISD::UNDEF, NVT);
5640 case ISD::Constant: {
5641 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
5642 Lo = DAG.getConstant(Cst, NVT);
5643 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
5646 case ISD::ConstantFP: {
5647 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5648 if (CFP->getValueType(0) == MVT::ppcf128) {
5649 APInt api = CFP->getValueAPF().convertToAPInt();
5650 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5652 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5656 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5657 if (getTypeAction(Lo.getValueType()) == Expand)
5658 ExpandOp(Lo, Lo, Hi);
5661 case ISD::BUILD_PAIR:
5662 // Return the operands.
5663 Lo = Node->getOperand(0);
5664 Hi = Node->getOperand(1);
5667 case ISD::MERGE_VALUES:
5668 if (Node->getNumValues() == 1) {
5669 ExpandOp(Op.getOperand(0), Lo, Hi);
5672 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5673 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5674 Op.getValue(1).getValueType() == MVT::Other &&
5675 "unhandled MERGE_VALUES");
5676 ExpandOp(Op.getOperand(0), Lo, Hi);
5677 // Remember that we legalized the chain.
5678 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5681 case ISD::SIGN_EXTEND_INREG:
5682 ExpandOp(Node->getOperand(0), Lo, Hi);
5683 // sext_inreg the low part if needed.
5684 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5686 // The high part gets the sign extension from the lo-part. This handles
5687 // things like sextinreg V:i64 from i8.
5688 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5689 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5690 TLI.getShiftAmountTy()));
5694 ExpandOp(Node->getOperand(0), Lo, Hi);
5695 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5696 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5702 ExpandOp(Node->getOperand(0), Lo, Hi);
5703 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5704 DAG.getNode(ISD::CTPOP, NVT, Lo),
5705 DAG.getNode(ISD::CTPOP, NVT, Hi));
5706 Hi = DAG.getConstant(0, NVT);
5710 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5711 ExpandOp(Node->getOperand(0), Lo, Hi);
5712 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5713 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5714 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5716 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5717 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5719 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5720 Hi = DAG.getConstant(0, NVT);
5725 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5726 ExpandOp(Node->getOperand(0), Lo, Hi);
5727 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5728 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5729 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5731 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5732 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5734 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5735 Hi = DAG.getConstant(0, NVT);
5740 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5741 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5742 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5743 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5745 // Remember that we legalized the chain.
5746 Hi = LegalizeOp(Hi);
5747 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5748 if (!TLI.isLittleEndian())
5754 LoadSDNode *LD = cast<LoadSDNode>(Node);
5755 SDOperand Ch = LD->getChain(); // Legalize the chain.
5756 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5757 ISD::LoadExtType ExtType = LD->getExtensionType();
5758 int SVOffset = LD->getSrcValueOffset();
5759 unsigned Alignment = LD->getAlignment();
5760 bool isVolatile = LD->isVolatile();
5762 if (ExtType == ISD::NON_EXTLOAD) {
5763 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5764 isVolatile, Alignment);
5765 if (VT == MVT::f32 || VT == MVT::f64) {
5766 // f32->i32 or f64->i64 one to one expansion.
5767 // Remember that we legalized the chain.
5768 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5769 // Recursively expand the new load.
5770 if (getTypeAction(NVT) == Expand)
5771 ExpandOp(Lo, Lo, Hi);
5775 // Increment the pointer to the other half.
5776 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5777 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5778 DAG.getIntPtrConstant(IncrementSize));
5779 SVOffset += IncrementSize;
5780 Alignment = MinAlign(Alignment, IncrementSize);
5781 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5782 isVolatile, Alignment);
5784 // Build a factor node to remember that this load is independent of the
5786 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5789 // Remember that we legalized the chain.
5790 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5791 if (!TLI.isLittleEndian())
5794 MVT::ValueType EVT = LD->getMemoryVT();
5796 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5797 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5798 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5799 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5800 SVOffset, isVolatile, Alignment);
5801 // Remember that we legalized the chain.
5802 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5803 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5808 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5809 SVOffset, isVolatile, Alignment);
5811 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5812 SVOffset, EVT, isVolatile,
5815 // Remember that we legalized the chain.
5816 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5818 if (ExtType == ISD::SEXTLOAD) {
5819 // The high part is obtained by SRA'ing all but one of the bits of the
5821 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5822 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5823 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5824 } else if (ExtType == ISD::ZEXTLOAD) {
5825 // The high part is just a zero.
5826 Hi = DAG.getConstant(0, NVT);
5827 } else /* if (ExtType == ISD::EXTLOAD) */ {
5828 // The high part is undefined.
5829 Hi = DAG.getNode(ISD::UNDEF, NVT);
5836 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5837 SDOperand LL, LH, RL, RH;
5838 ExpandOp(Node->getOperand(0), LL, LH);
5839 ExpandOp(Node->getOperand(1), RL, RH);
5840 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5841 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5845 SDOperand LL, LH, RL, RH;
5846 ExpandOp(Node->getOperand(1), LL, LH);
5847 ExpandOp(Node->getOperand(2), RL, RH);
5848 if (getTypeAction(NVT) == Expand)
5849 NVT = TLI.getTypeToExpandTo(NVT);
5850 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5852 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5855 case ISD::SELECT_CC: {
5856 SDOperand TL, TH, FL, FH;
5857 ExpandOp(Node->getOperand(2), TL, TH);
5858 ExpandOp(Node->getOperand(3), FL, FH);
5859 if (getTypeAction(NVT) == Expand)
5860 NVT = TLI.getTypeToExpandTo(NVT);
5861 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5862 Node->getOperand(1), TL, FL, Node->getOperand(4));
5864 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5865 Node->getOperand(1), TH, FH, Node->getOperand(4));
5868 case ISD::ANY_EXTEND:
5869 // The low part is any extension of the input (which degenerates to a copy).
5870 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5871 // The high part is undefined.
5872 Hi = DAG.getNode(ISD::UNDEF, NVT);
5874 case ISD::SIGN_EXTEND: {
5875 // The low part is just a sign extension of the input (which degenerates to
5877 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5879 // The high part is obtained by SRA'ing all but one of the bits of the lo
5881 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5882 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5883 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5886 case ISD::ZERO_EXTEND:
5887 // The low part is just a zero extension of the input (which degenerates to
5889 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5891 // The high part is just a zero.
5892 Hi = DAG.getConstant(0, NVT);
5895 case ISD::TRUNCATE: {
5896 // The input value must be larger than this value. Expand *it*.
5898 ExpandOp(Node->getOperand(0), NewLo, Hi);
5900 // The low part is now either the right size, or it is closer. If not the
5901 // right size, make an illegal truncate so we recursively expand it.
5902 if (NewLo.getValueType() != Node->getValueType(0))
5903 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
5904 ExpandOp(NewLo, Lo, Hi);
5908 case ISD::BIT_CONVERT: {
5910 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
5911 // If the target wants to, allow it to lower this itself.
5912 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5913 case Expand: assert(0 && "cannot expand FP!");
5914 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
5915 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
5917 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
5920 // f32 / f64 must be expanded to i32 / i64.
5921 if (VT == MVT::f32 || VT == MVT::f64) {
5922 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5923 if (getTypeAction(NVT) == Expand)
5924 ExpandOp(Lo, Lo, Hi);
5928 // If source operand will be expanded to the same type as VT, i.e.
5929 // i64 <- f64, i32 <- f32, expand the source operand instead.
5930 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
5931 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
5932 ExpandOp(Node->getOperand(0), Lo, Hi);
5936 // Turn this into a load/store pair by default.
5938 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
5940 ExpandOp(Tmp, Lo, Hi);
5944 case ISD::READCYCLECOUNTER: {
5945 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5946 TargetLowering::Custom &&
5947 "Must custom expand ReadCycleCounter");
5948 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
5949 assert(Tmp.Val && "Node must be custom expanded!");
5950 ExpandOp(Tmp.getValue(0), Lo, Hi);
5951 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5952 LegalizeOp(Tmp.getValue(1)));
5956 // These operators cannot be expanded directly, emit them as calls to
5957 // library functions.
5958 case ISD::FP_TO_SINT: {
5959 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5961 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5962 case Expand: assert(0 && "cannot expand FP!");
5963 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5964 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5967 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5969 // Now that the custom expander is done, expand the result, which is still
5972 ExpandOp(Op, Lo, Hi);
5977 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5978 if (Node->getOperand(0).getValueType() == MVT::f32)
5979 LC = RTLIB::FPTOSINT_F32_I64;
5980 else if (Node->getOperand(0).getValueType() == MVT::f64)
5981 LC = RTLIB::FPTOSINT_F64_I64;
5982 else if (Node->getOperand(0).getValueType() == MVT::f80)
5983 LC = RTLIB::FPTOSINT_F80_I64;
5984 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
5985 LC = RTLIB::FPTOSINT_PPCF128_I64;
5986 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5987 false/*sign irrelevant*/, Hi);
5991 case ISD::FP_TO_UINT: {
5992 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
5994 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5995 case Expand: assert(0 && "cannot expand FP!");
5996 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5997 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6000 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6002 // Now that the custom expander is done, expand the result.
6004 ExpandOp(Op, Lo, Hi);
6009 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6010 if (Node->getOperand(0).getValueType() == MVT::f32)
6011 LC = RTLIB::FPTOUINT_F32_I64;
6012 else if (Node->getOperand(0).getValueType() == MVT::f64)
6013 LC = RTLIB::FPTOUINT_F64_I64;
6014 else if (Node->getOperand(0).getValueType() == MVT::f80)
6015 LC = RTLIB::FPTOUINT_F80_I64;
6016 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6017 LC = RTLIB::FPTOUINT_PPCF128_I64;
6018 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6019 false/*sign irrelevant*/, Hi);
6024 // If the target wants custom lowering, do so.
6025 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6026 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6027 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6028 Op = TLI.LowerOperation(Op, DAG);
6030 // Now that the custom expander is done, expand the result, which is
6032 ExpandOp(Op, Lo, Hi);
6037 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6038 // this X << 1 as X+X.
6039 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6040 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6041 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6042 SDOperand LoOps[2], HiOps[3];
6043 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6044 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6045 LoOps[1] = LoOps[0];
6046 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6048 HiOps[1] = HiOps[0];
6049 HiOps[2] = Lo.getValue(1);
6050 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6055 // If we can emit an efficient shift operation, do so now.
6056 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6059 // If this target supports SHL_PARTS, use it.
6060 TargetLowering::LegalizeAction Action =
6061 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6062 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6063 Action == TargetLowering::Custom) {
6064 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6068 // Otherwise, emit a libcall.
6069 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
6070 false/*left shift=unsigned*/, Hi);
6075 // If the target wants custom lowering, do so.
6076 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6077 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6078 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6079 Op = TLI.LowerOperation(Op, DAG);
6081 // Now that the custom expander is done, expand the result, which is
6083 ExpandOp(Op, Lo, Hi);
6088 // If we can emit an efficient shift operation, do so now.
6089 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6092 // If this target supports SRA_PARTS, use it.
6093 TargetLowering::LegalizeAction Action =
6094 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6095 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6096 Action == TargetLowering::Custom) {
6097 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6101 // Otherwise, emit a libcall.
6102 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
6103 true/*ashr is signed*/, Hi);
6108 // If the target wants custom lowering, do so.
6109 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6110 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6111 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6112 Op = TLI.LowerOperation(Op, DAG);
6114 // Now that the custom expander is done, expand the result, which is
6116 ExpandOp(Op, Lo, Hi);
6121 // If we can emit an efficient shift operation, do so now.
6122 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6125 // If this target supports SRL_PARTS, use it.
6126 TargetLowering::LegalizeAction Action =
6127 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6128 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6129 Action == TargetLowering::Custom) {
6130 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6134 // Otherwise, emit a libcall.
6135 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
6136 false/*lshr is unsigned*/, Hi);
6142 // If the target wants to custom expand this, let them.
6143 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6144 TargetLowering::Custom) {
6145 Op = TLI.LowerOperation(Op, DAG);
6147 ExpandOp(Op, Lo, Hi);
6152 // Expand the subcomponents.
6153 SDOperand LHSL, LHSH, RHSL, RHSH;
6154 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6155 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6156 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6157 SDOperand LoOps[2], HiOps[3];
6162 if (Node->getOpcode() == ISD::ADD) {
6163 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6164 HiOps[2] = Lo.getValue(1);
6165 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6167 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6168 HiOps[2] = Lo.getValue(1);
6169 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6176 // Expand the subcomponents.
6177 SDOperand LHSL, LHSH, RHSL, RHSH;
6178 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6179 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6180 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6181 SDOperand LoOps[2] = { LHSL, RHSL };
6182 SDOperand HiOps[3] = { LHSH, RHSH };
6184 if (Node->getOpcode() == ISD::ADDC) {
6185 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6186 HiOps[2] = Lo.getValue(1);
6187 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6189 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6190 HiOps[2] = Lo.getValue(1);
6191 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6193 // Remember that we legalized the flag.
6194 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6199 // Expand the subcomponents.
6200 SDOperand LHSL, LHSH, RHSL, RHSH;
6201 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6202 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6203 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6204 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6205 SDOperand HiOps[3] = { LHSH, RHSH };
6207 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6208 HiOps[2] = Lo.getValue(1);
6209 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6211 // Remember that we legalized the flag.
6212 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6216 // If the target wants to custom expand this, let them.
6217 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6218 SDOperand New = TLI.LowerOperation(Op, DAG);
6220 ExpandOp(New, Lo, Hi);
6225 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6226 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6227 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6228 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6229 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6230 SDOperand LL, LH, RL, RH;
6231 ExpandOp(Node->getOperand(0), LL, LH);
6232 ExpandOp(Node->getOperand(1), RL, RH);
6233 unsigned BitSize = MVT::getSizeInBits(RH.getValueType());
6234 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6235 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6236 // FIXME: generalize this to handle other bit sizes
6237 if (LHSSB == 32 && RHSSB == 32 &&
6238 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) &&
6239 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) {
6240 // The inputs are both zero-extended.
6242 // We can emit a umul_lohi.
6243 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6244 Hi = SDOperand(Lo.Val, 1);
6248 // We can emit a mulhu+mul.
6249 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6250 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6254 if (LHSSB > BitSize && RHSSB > BitSize) {
6255 // The input values are both sign-extended.
6257 // We can emit a smul_lohi.
6258 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6259 Hi = SDOperand(Lo.Val, 1);
6263 // We can emit a mulhs+mul.
6264 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6265 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6270 // Lo,Hi = umul LHS, RHS.
6271 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6272 DAG.getVTList(NVT, NVT), LL, RL);
6274 Hi = UMulLOHI.getValue(1);
6275 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6276 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6277 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6278 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6282 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6283 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6284 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6285 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6286 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6287 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6292 // If nothing else, we can make a libcall.
6293 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
6294 false/*sign irrelevant*/, Hi);
6298 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
6301 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
6304 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
6307 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
6311 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32,
6314 RTLIB::ADD_PPCF128)),
6318 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32,
6321 RTLIB::SUB_PPCF128)),
6325 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32,
6328 RTLIB::MUL_PPCF128)),
6332 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32,
6335 RTLIB::DIV_PPCF128)),
6338 case ISD::FP_EXTEND:
6339 if (VT == MVT::ppcf128) {
6340 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6341 Node->getOperand(0).getValueType()==MVT::f64);
6342 const uint64_t zero = 0;
6343 if (Node->getOperand(0).getValueType()==MVT::f32)
6344 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6346 Hi = Node->getOperand(0);
6347 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6350 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
6353 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
6356 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32,
6359 RTLIB::POWI_PPCF128)),
6365 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6366 switch(Node->getOpcode()) {
6368 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6369 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6372 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6373 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6376 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6377 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6379 default: assert(0 && "Unreachable!");
6381 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
6385 if (VT == MVT::ppcf128) {
6387 ExpandOp(Node->getOperand(0), Lo, Tmp);
6388 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6389 // lo = hi==fabs(hi) ? lo : -lo;
6390 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6391 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6392 DAG.getCondCode(ISD::SETEQ));
6395 SDOperand Mask = (VT == MVT::f64)
6396 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6397 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6398 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6399 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6400 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6401 if (getTypeAction(NVT) == Expand)
6402 ExpandOp(Lo, Lo, Hi);
6406 if (VT == MVT::ppcf128) {
6407 ExpandOp(Node->getOperand(0), Lo, Hi);
6408 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6409 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6412 SDOperand Mask = (VT == MVT::f64)
6413 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6414 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6415 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6416 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6417 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6418 if (getTypeAction(NVT) == Expand)
6419 ExpandOp(Lo, Lo, Hi);
6422 case ISD::FCOPYSIGN: {
6423 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6424 if (getTypeAction(NVT) == Expand)
6425 ExpandOp(Lo, Lo, Hi);
6428 case ISD::SINT_TO_FP:
6429 case ISD::UINT_TO_FP: {
6430 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6431 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
6432 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) {
6433 static uint64_t zero = 0;
6435 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6436 Node->getOperand(0)));
6437 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6439 static uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6440 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6441 Node->getOperand(0)));
6442 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6443 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6444 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6445 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6446 DAG.getConstant(0, MVT::i32),
6447 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6449 APFloat(APInt(128, 2, TwoE32)),
6452 DAG.getCondCode(ISD::SETLT)),
6457 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6458 // si64->ppcf128 done by libcall, below
6459 static uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6460 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6462 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6463 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6464 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6465 DAG.getConstant(0, MVT::i64),
6466 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6468 APFloat(APInt(128, 2, TwoE64)),
6471 DAG.getCondCode(ISD::SETLT)),
6475 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6476 if (Node->getOperand(0).getValueType() == MVT::i64) {
6478 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
6479 else if (VT == MVT::f64)
6480 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
6481 else if (VT == MVT::f80) {
6483 LC = RTLIB::SINTTOFP_I64_F80;
6485 else if (VT == MVT::ppcf128) {
6487 LC = RTLIB::SINTTOFP_I64_PPCF128;
6491 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
6493 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
6496 // Promote the operand if needed.
6497 if (getTypeAction(SrcVT) == Promote) {
6498 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6500 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6501 DAG.getValueType(SrcVT))
6502 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6503 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6506 const char *LibCall = TLI.getLibcallName(LC);
6508 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
6510 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6511 Node->getOperand(0));
6512 if (getTypeAction(Lo.getValueType()) == Expand)
6513 ExpandOp(Lo, Lo, Hi);
6519 // Make sure the resultant values have been legalized themselves, unless this
6520 // is a type that requires multi-step expansion.
6521 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6522 Lo = LegalizeOp(Lo);
6524 // Don't legalize the high part if it is expanded to a single node.
6525 Hi = LegalizeOp(Hi);
6528 // Remember in a map if the values will be reused later.
6529 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6530 assert(isNew && "Value already expanded?!?");
6533 /// SplitVectorOp - Given an operand of vector type, break it down into
6534 /// two smaller values, still of vector type.
6535 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6537 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
6538 SDNode *Node = Op.Val;
6539 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
6540 assert(NumElements > 1 && "Cannot split a single element vector!");
6542 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
6544 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6545 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6547 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
6548 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
6550 // See if we already split it.
6551 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6552 = SplitNodes.find(Op);
6553 if (I != SplitNodes.end()) {
6554 Lo = I->second.first;
6555 Hi = I->second.second;
6559 switch (Node->getOpcode()) {
6564 assert(0 && "Unhandled operation in SplitVectorOp!");
6566 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6567 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6569 case ISD::BUILD_PAIR:
6570 Lo = Node->getOperand(0);
6571 Hi = Node->getOperand(1);
6573 case ISD::INSERT_VECTOR_ELT: {
6574 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6575 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
6576 SDOperand ScalarOp = Node->getOperand(1);
6577 if (Index < NewNumElts_Lo)
6578 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6579 DAG.getConstant(Index, TLI.getPointerTy()));
6581 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6582 DAG.getConstant(Index - NewNumElts_Lo,
6583 TLI.getPointerTy()));
6586 case ISD::VECTOR_SHUFFLE: {
6587 // Build the low part.
6588 SDOperand Mask = Node->getOperand(2);
6589 SmallVector<SDOperand, 8> Ops;
6590 MVT::ValueType PtrVT = TLI.getPointerTy();
6592 // Insert all of the elements from the input that are needed. We use
6593 // buildvector of extractelement here because the input vectors will have
6594 // to be legalized, so this makes the code simpler.
6595 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6596 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6597 SDOperand InVec = Node->getOperand(0);
6598 if (Idx >= NumElements) {
6599 InVec = Node->getOperand(1);
6602 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6603 DAG.getConstant(Idx, PtrVT)));
6605 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6608 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6609 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6610 SDOperand InVec = Node->getOperand(0);
6611 if (Idx >= NumElements) {
6612 InVec = Node->getOperand(1);
6615 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6616 DAG.getConstant(Idx, PtrVT)));
6618 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6621 case ISD::BUILD_VECTOR: {
6622 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6623 Node->op_begin()+NewNumElts_Lo);
6624 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6626 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6628 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6631 case ISD::CONCAT_VECTORS: {
6632 // FIXME: Handle non-power-of-two vectors?
6633 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6634 if (NewNumSubvectors == 1) {
6635 Lo = Node->getOperand(0);
6636 Hi = Node->getOperand(1);
6638 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6639 Node->op_begin()+NewNumSubvectors);
6640 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6642 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6644 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6649 SDOperand Cond = Node->getOperand(0);
6651 SDOperand LL, LH, RL, RH;
6652 SplitVectorOp(Node->getOperand(1), LL, LH);
6653 SplitVectorOp(Node->getOperand(2), RL, RH);
6655 if (MVT::isVector(Cond.getValueType())) {
6656 // Handle a vector merge.
6658 SplitVectorOp(Cond, CL, CH);
6659 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6660 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6662 // Handle a simple select with vector operands.
6663 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6664 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6684 SDOperand LL, LH, RL, RH;
6685 SplitVectorOp(Node->getOperand(0), LL, LH);
6686 SplitVectorOp(Node->getOperand(1), RL, RH);
6688 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6689 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6694 SplitVectorOp(Node->getOperand(0), L, H);
6696 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6697 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6708 case ISD::FP_TO_SINT:
6709 case ISD::FP_TO_UINT:
6710 case ISD::SINT_TO_FP:
6711 case ISD::UINT_TO_FP: {
6713 SplitVectorOp(Node->getOperand(0), L, H);
6715 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6716 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6720 LoadSDNode *LD = cast<LoadSDNode>(Node);
6721 SDOperand Ch = LD->getChain();
6722 SDOperand Ptr = LD->getBasePtr();
6723 const Value *SV = LD->getSrcValue();
6724 int SVOffset = LD->getSrcValueOffset();
6725 unsigned Alignment = LD->getAlignment();
6726 bool isVolatile = LD->isVolatile();
6728 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6729 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
6730 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6731 DAG.getIntPtrConstant(IncrementSize));
6732 SVOffset += IncrementSize;
6733 Alignment = MinAlign(Alignment, IncrementSize);
6734 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6736 // Build a factor node to remember that this load is independent of the
6738 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6741 // Remember that we legalized the chain.
6742 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6745 case ISD::BIT_CONVERT: {
6746 // We know the result is a vector. The input may be either a vector or a
6748 SDOperand InOp = Node->getOperand(0);
6749 if (!MVT::isVector(InOp.getValueType()) ||
6750 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
6751 // The input is a scalar or single-element vector.
6752 // Lower to a store/load so that it can be split.
6753 // FIXME: this could be improved probably.
6754 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6755 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr.Val);
6756 assert(FI && "Expecting CreateStackTemporary to return a frame index.\n");
6758 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6760 &PseudoSourceValue::FPRel, FI->getIndex());
6761 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
6762 &PseudoSourceValue::FPRel, FI->getIndex());
6764 // Split the vector and convert each of the pieces now.
6765 SplitVectorOp(InOp, Lo, Hi);
6766 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6767 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6772 // Remember in a map if the values will be reused later.
6774 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6775 assert(isNew && "Value already split?!?");
6779 /// ScalarizeVectorOp - Given an operand of single-element vector type
6780 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6781 /// scalar (e.g. f32) value.
6782 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6783 assert(MVT::isVector(Op.getValueType()) &&
6784 "Bad ScalarizeVectorOp invocation!");
6785 SDNode *Node = Op.Val;
6786 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
6787 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
6789 // See if we already scalarized it.
6790 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
6791 if (I != ScalarizedNodes.end()) return I->second;
6794 switch (Node->getOpcode()) {
6797 Node->dump(&DAG); cerr << "\n";
6799 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
6816 Result = DAG.getNode(Node->getOpcode(),
6818 ScalarizeVectorOp(Node->getOperand(0)),
6819 ScalarizeVectorOp(Node->getOperand(1)));
6826 Result = DAG.getNode(Node->getOpcode(),
6828 ScalarizeVectorOp(Node->getOperand(0)));
6831 Result = DAG.getNode(Node->getOpcode(),
6833 ScalarizeVectorOp(Node->getOperand(0)),
6834 Node->getOperand(1));
6837 LoadSDNode *LD = cast<LoadSDNode>(Node);
6838 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
6839 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
6841 const Value *SV = LD->getSrcValue();
6842 int SVOffset = LD->getSrcValueOffset();
6843 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
6844 LD->isVolatile(), LD->getAlignment());
6846 // Remember that we legalized the chain.
6847 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
6850 case ISD::BUILD_VECTOR:
6851 Result = Node->getOperand(0);
6853 case ISD::INSERT_VECTOR_ELT:
6854 // Returning the inserted scalar element.
6855 Result = Node->getOperand(1);
6857 case ISD::CONCAT_VECTORS:
6858 assert(Node->getOperand(0).getValueType() == NewVT &&
6859 "Concat of non-legal vectors not yet supported!");
6860 Result = Node->getOperand(0);
6862 case ISD::VECTOR_SHUFFLE: {
6863 // Figure out if the scalar is the LHS or RHS and return it.
6864 SDOperand EltNum = Node->getOperand(2).getOperand(0);
6865 if (cast<ConstantSDNode>(EltNum)->getValue())
6866 Result = ScalarizeVectorOp(Node->getOperand(1));
6868 Result = ScalarizeVectorOp(Node->getOperand(0));
6871 case ISD::EXTRACT_SUBVECTOR:
6872 Result = Node->getOperand(0);
6873 assert(Result.getValueType() == NewVT);
6875 case ISD::BIT_CONVERT:
6876 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
6879 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
6880 ScalarizeVectorOp(Op.getOperand(1)),
6881 ScalarizeVectorOp(Op.getOperand(2)));
6885 if (TLI.isTypeLegal(NewVT))
6886 Result = LegalizeOp(Result);
6887 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
6888 assert(isNew && "Value already scalarized?");
6893 // SelectionDAG::Legalize - This is the entry point for the file.
6895 void SelectionDAG::Legalize() {
6896 if (ViewLegalizeDAGs) viewGraph();
6898 /// run - This is the main entry point to this class.
6900 SelectionDAGLegalize(*this).LegalizeDAG();