1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/ADT/SmallVector.h"
34 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
35 cl::desc("Pop up a window to show dags before legalize"));
37 static const bool ViewLegalizeDAGs = 0;
40 //===----------------------------------------------------------------------===//
41 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
42 /// hacks on it until the target machine can handle it. This involves
43 /// eliminating value sizes the machine cannot handle (promoting small sizes to
44 /// large sizes or splitting up large values into small values) as well as
45 /// eliminating operations the machine cannot handle.
47 /// This code also does a small amount of optimization and recognition of idioms
48 /// as part of its processing. For example, if a target does not support a
49 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
50 /// will attempt merge setcc and brc instructions into brcc's.
53 class VISIBILITY_HIDDEN SelectionDAGLegalize {
57 // Libcall insertion helpers.
59 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
60 /// legalized. We use this to ensure that calls are properly serialized
61 /// against each other, including inserted libcalls.
62 SDOperand LastCALLSEQ_END;
64 /// IsLegalizingCall - This member is used *only* for purposes of providing
65 /// helpful assertions that a libcall isn't created while another call is
66 /// being legalized (which could lead to non-serialized call sequences).
67 bool IsLegalizingCall;
70 Legal, // The target natively supports this operation.
71 Promote, // This operation should be executed in a larger type.
72 Expand // Try to expand this to other ops, otherwise use a libcall.
75 /// ValueTypeActions - This is a bitvector that contains two bits for each
76 /// value type, where the two bits correspond to the LegalizeAction enum.
77 /// This can be queried with "getTypeAction(VT)".
78 TargetLowering::ValueTypeActionImpl ValueTypeActions;
80 /// LegalizedNodes - For nodes that are of legal width, and that have more
81 /// than one use, this map indicates what regularized operand to use. This
82 /// allows us to avoid legalizing the same thing more than once.
83 std::map<SDOperand, SDOperand> LegalizedNodes;
85 /// PromotedNodes - For nodes that are below legal width, and that have more
86 /// than one use, this map indicates what promoted value to use. This allows
87 /// us to avoid promoting the same thing more than once.
88 std::map<SDOperand, SDOperand> PromotedNodes;
90 /// ExpandedNodes - For nodes that need to be expanded this map indicates
91 /// which which operands are the expanded version of the input. This allows
92 /// us to avoid expanding the same node more than once.
93 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
95 /// SplitNodes - For vector nodes that need to be split, this map indicates
96 /// which which operands are the split version of the input. This allows us
97 /// to avoid splitting the same node more than once.
98 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
100 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
101 /// concrete packed types, this contains the mapping of ones we have already
102 /// processed to the result.
103 std::map<SDOperand, SDOperand> PackedNodes;
105 void AddLegalizedOperand(SDOperand From, SDOperand To) {
106 LegalizedNodes.insert(std::make_pair(From, To));
107 // If someone requests legalization of the new node, return itself.
109 LegalizedNodes.insert(std::make_pair(To, To));
111 void AddPromotedOperand(SDOperand From, SDOperand To) {
112 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
113 assert(isNew && "Got into the map somehow?");
114 // If someone requests legalization of the new node, return itself.
115 LegalizedNodes.insert(std::make_pair(To, To));
120 SelectionDAGLegalize(SelectionDAG &DAG);
122 /// getTypeAction - Return how we should legalize values of this type, either
123 /// it is already legal or we need to expand it into multiple registers of
124 /// smaller integer type, or we need to promote it to a larger type.
125 LegalizeAction getTypeAction(MVT::ValueType VT) const {
126 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
129 /// isTypeLegal - Return true if this type is legal on this target.
131 bool isTypeLegal(MVT::ValueType VT) const {
132 return getTypeAction(VT) == Legal;
138 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
139 /// appropriate for its type.
140 void HandleOp(SDOperand Op);
142 /// LegalizeOp - We know that the specified value has a legal type.
143 /// Recursively ensure that the operands have legal types, then return the
145 SDOperand LegalizeOp(SDOperand O);
147 /// PromoteOp - Given an operation that produces a value in an invalid type,
148 /// promote it to compute the value into a larger type. The produced value
149 /// will have the correct bits for the low portion of the register, but no
150 /// guarantee is made about the top bits: it may be zero, sign-extended, or
152 SDOperand PromoteOp(SDOperand O);
154 /// ExpandOp - Expand the specified SDOperand into its two component pieces
155 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
156 /// the LegalizeNodes map is filled in for any results that are not expanded,
157 /// the ExpandedNodes map is filled in for any results that are expanded, and
158 /// the Lo/Hi values are returned. This applies to integer types and Vector
160 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
162 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
163 /// two smaller values of MVT::Vector type.
164 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
166 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
167 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
168 /// this is called, we know that PackedVT is the right type for the result and
169 /// we know that this type is legal for the target.
170 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
172 /// isShuffleLegal - Return true if a vector shuffle is legal with the
173 /// specified mask and type. Targets can specify exactly which masks they
174 /// support and the code generator is tasked with not creating illegal masks.
176 /// Note that this will also return true for shuffles that are promoted to a
179 /// If this is a legal shuffle, this method returns the (possibly promoted)
180 /// build_vector Mask. If it's not a legal shuffle, it returns null.
181 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
183 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
184 std::set<SDNode*> &NodesLeadingTo);
186 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
188 SDOperand CreateStackTemporary(MVT::ValueType VT);
190 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
192 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
195 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
196 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
197 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
198 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
200 MVT::ValueType DestVT);
201 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
203 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
206 SDOperand ExpandBSWAP(SDOperand Op);
207 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
208 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
209 SDOperand &Lo, SDOperand &Hi);
210 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
211 SDOperand &Lo, SDOperand &Hi);
213 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
214 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
216 SDOperand getIntPtrConstant(uint64_t Val) {
217 return DAG.getConstant(Val, TLI.getPointerTy());
222 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
223 /// specified mask and type. Targets can specify exactly which masks they
224 /// support and the code generator is tasked with not creating illegal masks.
226 /// Note that this will also return true for shuffles that are promoted to a
228 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
229 SDOperand Mask) const {
230 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
232 case TargetLowering::Legal:
233 case TargetLowering::Custom:
235 case TargetLowering::Promote: {
236 // If this is promoted to a different type, convert the shuffle mask and
237 // ask if it is legal in the promoted type!
238 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
240 // If we changed # elements, change the shuffle mask.
241 unsigned NumEltsGrowth =
242 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
243 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
244 if (NumEltsGrowth > 1) {
245 // Renumber the elements.
246 SmallVector<SDOperand, 8> Ops;
247 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
248 SDOperand InOp = Mask.getOperand(i);
249 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
250 if (InOp.getOpcode() == ISD::UNDEF)
251 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
253 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
254 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
258 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
264 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
267 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
268 /// specified vector opcode.
269 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
271 default: assert(0 && "Don't know how to scalarize this opcode!");
272 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
273 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
274 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
275 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
276 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
277 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
278 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
279 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
283 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
284 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
285 ValueTypeActions(TLI.getValueTypeActions()) {
286 assert(MVT::LAST_VALUETYPE <= 32 &&
287 "Too many value types for ValueTypeActions to hold!");
290 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
291 /// not been visited yet and if all of its operands have already been visited.
292 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
293 std::map<SDNode*, unsigned> &Visited) {
294 if (++Visited[N] != N->getNumOperands())
295 return; // Haven't visited all operands yet
299 if (N->hasOneUse()) { // Tail recurse in common case.
300 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
304 // Now that we have N in, add anything that uses it if all of their operands
306 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
307 ComputeTopDownOrdering(*UI, Order, Visited);
311 void SelectionDAGLegalize::LegalizeDAG() {
312 LastCALLSEQ_END = DAG.getEntryNode();
313 IsLegalizingCall = false;
315 // The legalize process is inherently a bottom-up recursive process (users
316 // legalize their uses before themselves). Given infinite stack space, we
317 // could just start legalizing on the root and traverse the whole graph. In
318 // practice however, this causes us to run out of stack space on large basic
319 // blocks. To avoid this problem, compute an ordering of the nodes where each
320 // node is only legalized after all of its operands are legalized.
321 std::map<SDNode*, unsigned> Visited;
322 std::vector<SDNode*> Order;
324 // Compute ordering from all of the leaves in the graphs, those (like the
325 // entry node) that have no operands.
326 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
327 E = DAG.allnodes_end(); I != E; ++I) {
328 if (I->getNumOperands() == 0) {
330 ComputeTopDownOrdering(I, Order, Visited);
334 assert(Order.size() == Visited.size() &&
336 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
337 "Error: DAG is cyclic!");
340 for (unsigned i = 0, e = Order.size(); i != e; ++i)
341 HandleOp(SDOperand(Order[i], 0));
343 // Finally, it's possible the root changed. Get the new root.
344 SDOperand OldRoot = DAG.getRoot();
345 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
346 DAG.setRoot(LegalizedNodes[OldRoot]);
348 ExpandedNodes.clear();
349 LegalizedNodes.clear();
350 PromotedNodes.clear();
354 // Remove dead nodes now.
355 DAG.RemoveDeadNodes();
359 /// FindCallEndFromCallStart - Given a chained node that is part of a call
360 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
361 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
362 if (Node->getOpcode() == ISD::CALLSEQ_END)
364 if (Node->use_empty())
365 return 0; // No CallSeqEnd
367 // The chain is usually at the end.
368 SDOperand TheChain(Node, Node->getNumValues()-1);
369 if (TheChain.getValueType() != MVT::Other) {
370 // Sometimes it's at the beginning.
371 TheChain = SDOperand(Node, 0);
372 if (TheChain.getValueType() != MVT::Other) {
373 // Otherwise, hunt for it.
374 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
375 if (Node->getValueType(i) == MVT::Other) {
376 TheChain = SDOperand(Node, i);
380 // Otherwise, we walked into a node without a chain.
381 if (TheChain.getValueType() != MVT::Other)
386 for (SDNode::use_iterator UI = Node->use_begin(),
387 E = Node->use_end(); UI != E; ++UI) {
389 // Make sure to only follow users of our token chain.
391 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
392 if (User->getOperand(i) == TheChain)
393 if (SDNode *Result = FindCallEndFromCallStart(User))
399 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
400 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
401 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
402 assert(Node && "Didn't find callseq_start for a call??");
403 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
405 assert(Node->getOperand(0).getValueType() == MVT::Other &&
406 "Node doesn't have a token chain argument!");
407 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
410 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
411 /// see if any uses can reach Dest. If no dest operands can get to dest,
412 /// legalize them, legalize ourself, and return false, otherwise, return true.
414 /// Keep track of the nodes we fine that actually do lead to Dest in
415 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
417 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
418 std::set<SDNode*> &NodesLeadingTo) {
419 if (N == Dest) return true; // N certainly leads to Dest :)
421 // If we've already processed this node and it does lead to Dest, there is no
422 // need to reprocess it.
423 if (NodesLeadingTo.count(N)) return true;
425 // If the first result of this node has been already legalized, then it cannot
427 switch (getTypeAction(N->getValueType(0))) {
429 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
432 if (PromotedNodes.count(SDOperand(N, 0))) return false;
435 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
439 // Okay, this node has not already been legalized. Check and legalize all
440 // operands. If none lead to Dest, then we can legalize this node.
441 bool OperandsLeadToDest = false;
442 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
443 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
444 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
446 if (OperandsLeadToDest) {
447 NodesLeadingTo.insert(N);
451 // Okay, this node looks safe, legalize it and return false.
452 HandleOp(SDOperand(N, 0));
456 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
457 /// appropriate for its type.
458 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
459 switch (getTypeAction(Op.getValueType())) {
460 default: assert(0 && "Bad type action!");
461 case Legal: LegalizeOp(Op); break;
462 case Promote: PromoteOp(Op); break;
464 if (Op.getValueType() != MVT::Vector) {
469 unsigned NumOps = N->getNumOperands();
470 unsigned NumElements =
471 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
472 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
473 MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
474 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
475 // In the common case, this is a legal vector type, convert it to the
476 // packed operation and type now.
477 PackVectorOp(Op, PackedVT);
478 } else if (NumElements == 1) {
479 // Otherwise, if this is a single element vector, convert it to a
481 PackVectorOp(Op, EVT);
483 // Otherwise, this is a multiple element vector that isn't supported.
484 // Split it in half and legalize both parts.
486 SplitVectorOp(Op, X, Y);
493 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
494 /// a load from the constant pool.
495 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
496 SelectionDAG &DAG, TargetLowering &TLI) {
499 // If a FP immediate is precise when represented as a float and if the
500 // target can do an extending load from float to double, we put it into
501 // the constant pool as a float, even if it's is statically typed as a
503 MVT::ValueType VT = CFP->getValueType(0);
504 bool isDouble = VT == MVT::f64;
505 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
506 Type::FloatTy, CFP->getValue());
508 double Val = LLVMC->getValue();
510 ? DAG.getConstant(DoubleToBits(Val), MVT::i64)
511 : DAG.getConstant(FloatToBits(Val), MVT::i32);
514 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
515 // Only do this if the target has a native EXTLOAD instruction from f32.
516 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
517 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
522 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
524 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
525 CPIdx, NULL, 0, MVT::f32);
527 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
532 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
535 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
536 SelectionDAG &DAG, TargetLowering &TLI) {
537 MVT::ValueType VT = Node->getValueType(0);
538 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
539 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
541 // First get the sign bit of second operand.
542 SDOperand Mask1 = (SrcVT == MVT::f64)
543 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
544 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
545 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
546 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
547 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
548 // Shift right or sign-extend it if the two operands have different types.
549 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
551 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
552 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
553 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
554 } else if (SizeDiff < 0)
555 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
557 // Clear the sign bit of first operand.
558 SDOperand Mask2 = (VT == MVT::f64)
559 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
560 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
561 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
562 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
563 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
565 // Or the value with the sign bit.
566 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
571 /// LegalizeOp - We know that the specified value has a legal type.
572 /// Recursively ensure that the operands have legal types, then return the
574 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
575 assert(isTypeLegal(Op.getValueType()) &&
576 "Caller should expand or promote operands that are not legal!");
577 SDNode *Node = Op.Val;
579 // If this operation defines any values that cannot be represented in a
580 // register on this target, make sure to expand or promote them.
581 if (Node->getNumValues() > 1) {
582 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
583 if (getTypeAction(Node->getValueType(i)) != Legal) {
584 HandleOp(Op.getValue(i));
585 assert(LegalizedNodes.count(Op) &&
586 "Handling didn't add legal operands!");
587 return LegalizedNodes[Op];
591 // Note that LegalizeOp may be reentered even from single-use nodes, which
592 // means that we always must cache transformed nodes.
593 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
594 if (I != LegalizedNodes.end()) return I->second;
596 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
597 SDOperand Result = Op;
598 bool isCustom = false;
600 switch (Node->getOpcode()) {
601 case ISD::FrameIndex:
602 case ISD::EntryToken:
604 case ISD::BasicBlock:
605 case ISD::TargetFrameIndex:
606 case ISD::TargetJumpTable:
607 case ISD::TargetConstant:
608 case ISD::TargetConstantFP:
609 case ISD::TargetConstantPool:
610 case ISD::TargetGlobalAddress:
611 case ISD::TargetExternalSymbol:
616 case ISD::GLOBAL_OFFSET_TABLE:
617 // Primitives must all be legal.
618 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
619 "This must be legal!");
622 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
623 // If this is a target node, legalize it by legalizing the operands then
624 // passing it through.
625 SmallVector<SDOperand, 8> Ops;
626 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
627 Ops.push_back(LegalizeOp(Node->getOperand(i)));
629 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
631 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
632 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
633 return Result.getValue(Op.ResNo);
635 // Otherwise this is an unhandled builtin node. splat.
637 cerr << "NODE: "; Node->dump(); cerr << "\n";
639 assert(0 && "Do not know how to legalize this operator!");
641 case ISD::GlobalAddress:
642 case ISD::ExternalSymbol:
643 case ISD::ConstantPool:
644 case ISD::JumpTable: // Nothing to do.
645 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
646 default: assert(0 && "This action is not supported yet!");
647 case TargetLowering::Custom:
648 Tmp1 = TLI.LowerOperation(Op, DAG);
649 if (Tmp1.Val) Result = Tmp1;
650 // FALLTHROUGH if the target doesn't want to lower this op after all.
651 case TargetLowering::Legal:
656 case ISD::RETURNADDR:
657 // The only option for these nodes is to custom lower them. If the target
658 // does not custom lower them, then return zero.
659 Tmp1 = TLI.LowerOperation(Op, DAG);
663 Result = DAG.getConstant(0, TLI.getPointerTy());
665 case ISD::AssertSext:
666 case ISD::AssertZext:
667 Tmp1 = LegalizeOp(Node->getOperand(0));
668 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
670 case ISD::MERGE_VALUES:
671 // Legalize eliminates MERGE_VALUES nodes.
672 Result = Node->getOperand(Op.ResNo);
674 case ISD::CopyFromReg:
675 Tmp1 = LegalizeOp(Node->getOperand(0));
676 Result = Op.getValue(0);
677 if (Node->getNumValues() == 2) {
678 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
680 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
681 if (Node->getNumOperands() == 3) {
682 Tmp2 = LegalizeOp(Node->getOperand(2));
683 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
685 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
687 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
689 // Since CopyFromReg produces two values, make sure to remember that we
690 // legalized both of them.
691 AddLegalizedOperand(Op.getValue(0), Result);
692 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
693 return Result.getValue(Op.ResNo);
695 MVT::ValueType VT = Op.getValueType();
696 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
697 default: assert(0 && "This action is not supported yet!");
698 case TargetLowering::Expand:
699 if (MVT::isInteger(VT))
700 Result = DAG.getConstant(0, VT);
701 else if (MVT::isFloatingPoint(VT))
702 Result = DAG.getConstantFP(0, VT);
704 assert(0 && "Unknown value type!");
706 case TargetLowering::Legal:
712 case ISD::INTRINSIC_W_CHAIN:
713 case ISD::INTRINSIC_WO_CHAIN:
714 case ISD::INTRINSIC_VOID: {
715 SmallVector<SDOperand, 8> Ops;
716 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
717 Ops.push_back(LegalizeOp(Node->getOperand(i)));
718 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
720 // Allow the target to custom lower its intrinsics if it wants to.
721 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
722 TargetLowering::Custom) {
723 Tmp3 = TLI.LowerOperation(Result, DAG);
724 if (Tmp3.Val) Result = Tmp3;
727 if (Result.Val->getNumValues() == 1) break;
729 // Must have return value and chain result.
730 assert(Result.Val->getNumValues() == 2 &&
731 "Cannot return more than two values!");
733 // Since loads produce two values, make sure to remember that we
734 // legalized both of them.
735 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
736 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
737 return Result.getValue(Op.ResNo);
741 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
742 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
744 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
745 case TargetLowering::Promote:
746 default: assert(0 && "This action is not supported yet!");
747 case TargetLowering::Expand: {
748 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
749 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
750 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
752 if (MMI && (useDEBUG_LOC || useLABEL)) {
753 const std::string &FName =
754 cast<StringSDNode>(Node->getOperand(3))->getValue();
755 const std::string &DirName =
756 cast<StringSDNode>(Node->getOperand(4))->getValue();
757 unsigned SrcFile = MMI->RecordSource(DirName, FName);
759 SmallVector<SDOperand, 8> Ops;
760 Ops.push_back(Tmp1); // chain
761 SDOperand LineOp = Node->getOperand(1);
762 SDOperand ColOp = Node->getOperand(2);
765 Ops.push_back(LineOp); // line #
766 Ops.push_back(ColOp); // col #
767 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
768 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
770 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
771 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
772 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
773 Ops.push_back(DAG.getConstant(ID, MVT::i32));
774 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
777 Result = Tmp1; // chain
781 case TargetLowering::Legal:
782 if (Tmp1 != Node->getOperand(0) ||
783 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
784 SmallVector<SDOperand, 8> Ops;
786 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
787 Ops.push_back(Node->getOperand(1)); // line # must be legal.
788 Ops.push_back(Node->getOperand(2)); // col # must be legal.
790 // Otherwise promote them.
791 Ops.push_back(PromoteOp(Node->getOperand(1)));
792 Ops.push_back(PromoteOp(Node->getOperand(2)));
794 Ops.push_back(Node->getOperand(3)); // filename must be legal.
795 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
796 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
803 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
804 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
805 default: assert(0 && "This action is not supported yet!");
806 case TargetLowering::Legal:
807 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
808 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
809 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
810 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
811 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
817 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
818 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
819 default: assert(0 && "This action is not supported yet!");
820 case TargetLowering::Legal:
821 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
822 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
823 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
829 // We know we don't need to expand constants here, constants only have one
830 // value and we check that it is fine above.
832 // FIXME: Maybe we should handle things like targets that don't support full
833 // 32-bit immediates?
835 case ISD::ConstantFP: {
836 // Spill FP immediates to the constant pool if the target cannot directly
837 // codegen them. Targets often have some immediate values that can be
838 // efficiently generated into an FP register without a load. We explicitly
839 // leave these constants as ConstantFP nodes for the target to deal with.
840 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
842 // Check to see if this FP immediate is already legal.
843 bool isLegal = false;
844 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
845 E = TLI.legal_fpimm_end(); I != E; ++I)
846 if (CFP->isExactlyValue(*I)) {
851 // If this is a legal constant, turn it into a TargetConstantFP node.
853 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
857 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
858 default: assert(0 && "This action is not supported yet!");
859 case TargetLowering::Custom:
860 Tmp3 = TLI.LowerOperation(Result, DAG);
866 case TargetLowering::Expand:
867 Result = ExpandConstantFP(CFP, true, DAG, TLI);
871 case ISD::TokenFactor:
872 if (Node->getNumOperands() == 2) {
873 Tmp1 = LegalizeOp(Node->getOperand(0));
874 Tmp2 = LegalizeOp(Node->getOperand(1));
875 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
876 } else if (Node->getNumOperands() == 3) {
877 Tmp1 = LegalizeOp(Node->getOperand(0));
878 Tmp2 = LegalizeOp(Node->getOperand(1));
879 Tmp3 = LegalizeOp(Node->getOperand(2));
880 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
882 SmallVector<SDOperand, 8> Ops;
883 // Legalize the operands.
884 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
885 Ops.push_back(LegalizeOp(Node->getOperand(i)));
886 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
890 case ISD::FORMAL_ARGUMENTS:
892 // The only option for this is to custom lower it.
893 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
894 assert(Tmp3.Val && "Target didn't custom lower this node!");
895 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
896 "Lowering call/formal_arguments produced unexpected # results!");
898 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
899 // remember that we legalized all of them, so it doesn't get relegalized.
900 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
901 Tmp1 = LegalizeOp(Tmp3.getValue(i));
904 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
908 case ISD::BUILD_VECTOR:
909 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
910 default: assert(0 && "This action is not supported yet!");
911 case TargetLowering::Custom:
912 Tmp3 = TLI.LowerOperation(Result, DAG);
918 case TargetLowering::Expand:
919 Result = ExpandBUILD_VECTOR(Result.Val);
923 case ISD::INSERT_VECTOR_ELT:
924 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
925 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
926 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
927 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
929 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
930 Node->getValueType(0))) {
931 default: assert(0 && "This action is not supported yet!");
932 case TargetLowering::Legal:
934 case TargetLowering::Custom:
935 Tmp3 = TLI.LowerOperation(Result, DAG);
941 case TargetLowering::Expand: {
942 // If the insert index is a constant, codegen this as a scalar_to_vector,
943 // then a shuffle that inserts it into the right position in the vector.
944 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
945 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
946 Tmp1.getValueType(), Tmp2);
948 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
949 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
950 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT);
952 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
953 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
955 SmallVector<SDOperand, 8> ShufOps;
956 for (unsigned i = 0; i != NumElts; ++i) {
957 if (i != InsertPos->getValue())
958 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
960 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
962 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
963 &ShufOps[0], ShufOps.size());
965 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
966 Tmp1, ScVec, ShufMask);
967 Result = LegalizeOp(Result);
971 // If the target doesn't support this, we have to spill the input vector
972 // to a temporary stack slot, update the element, then reload it. This is
973 // badness. We could also load the value into a vector register (either
974 // with a "move to register" or "extload into register" instruction, then
975 // permute it into place, if the idx is a constant and if the idx is
976 // supported by the target.
977 MVT::ValueType VT = Tmp1.getValueType();
978 MVT::ValueType EltVT = Tmp2.getValueType();
979 MVT::ValueType IdxVT = Tmp3.getValueType();
980 MVT::ValueType PtrVT = TLI.getPointerTy();
981 SDOperand StackPtr = CreateStackTemporary(VT);
983 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
985 // Truncate or zero extend offset to target pointer type.
986 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
987 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
988 // Add the offset to the index.
989 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
990 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
991 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
992 // Store the scalar value.
993 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
994 // Load the updated vector.
995 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1000 case ISD::SCALAR_TO_VECTOR:
1001 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1002 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1006 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1007 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1008 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1009 Node->getValueType(0))) {
1010 default: assert(0 && "This action is not supported yet!");
1011 case TargetLowering::Legal:
1013 case TargetLowering::Custom:
1014 Tmp3 = TLI.LowerOperation(Result, DAG);
1020 case TargetLowering::Expand:
1021 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1025 case ISD::VECTOR_SHUFFLE:
1026 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1027 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1028 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1030 // Allow targets to custom lower the SHUFFLEs they support.
1031 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1032 default: assert(0 && "Unknown operation action!");
1033 case TargetLowering::Legal:
1034 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1035 "vector shuffle should not be created if not legal!");
1037 case TargetLowering::Custom:
1038 Tmp3 = TLI.LowerOperation(Result, DAG);
1044 case TargetLowering::Expand: {
1045 MVT::ValueType VT = Node->getValueType(0);
1046 MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
1047 MVT::ValueType PtrVT = TLI.getPointerTy();
1048 SDOperand Mask = Node->getOperand(2);
1049 unsigned NumElems = Mask.getNumOperands();
1050 SmallVector<SDOperand,8> Ops;
1051 for (unsigned i = 0; i != NumElems; ++i) {
1052 SDOperand Arg = Mask.getOperand(i);
1053 if (Arg.getOpcode() == ISD::UNDEF) {
1054 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1056 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1057 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1059 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1060 DAG.getConstant(Idx, PtrVT)));
1062 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1063 DAG.getConstant(Idx - NumElems, PtrVT)));
1066 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1069 case TargetLowering::Promote: {
1070 // Change base type to a different vector type.
1071 MVT::ValueType OVT = Node->getValueType(0);
1072 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1074 // Cast the two input vectors.
1075 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1076 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1078 // Convert the shuffle mask to the right # elements.
1079 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1080 assert(Tmp3.Val && "Shuffle not legal?");
1081 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1082 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1088 case ISD::EXTRACT_VECTOR_ELT:
1089 Tmp1 = LegalizeOp(Node->getOperand(0));
1090 Tmp2 = LegalizeOp(Node->getOperand(1));
1091 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1093 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
1094 Tmp1.getValueType())) {
1095 default: assert(0 && "This action is not supported yet!");
1096 case TargetLowering::Legal:
1098 case TargetLowering::Custom:
1099 Tmp3 = TLI.LowerOperation(Result, DAG);
1105 case TargetLowering::Expand:
1106 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1111 case ISD::VEXTRACT_VECTOR_ELT:
1112 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
1115 case ISD::CALLSEQ_START: {
1116 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1118 // Recursively Legalize all of the inputs of the call end that do not lead
1119 // to this call start. This ensures that any libcalls that need be inserted
1120 // are inserted *before* the CALLSEQ_START.
1121 {std::set<SDNode*> NodesLeadingTo;
1122 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1123 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1127 // Now that we legalized all of the inputs (which may have inserted
1128 // libcalls) create the new CALLSEQ_START node.
1129 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1131 // Merge in the last call, to ensure that this call start after the last
1133 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1134 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1135 Tmp1 = LegalizeOp(Tmp1);
1138 // Do not try to legalize the target-specific arguments (#1+).
1139 if (Tmp1 != Node->getOperand(0)) {
1140 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1142 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1145 // Remember that the CALLSEQ_START is legalized.
1146 AddLegalizedOperand(Op.getValue(0), Result);
1147 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1148 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1150 // Now that the callseq_start and all of the non-call nodes above this call
1151 // sequence have been legalized, legalize the call itself. During this
1152 // process, no libcalls can/will be inserted, guaranteeing that no calls
1154 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1155 SDOperand InCallSEQ = LastCALLSEQ_END;
1156 // Note that we are selecting this call!
1157 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1158 IsLegalizingCall = true;
1160 // Legalize the call, starting from the CALLSEQ_END.
1161 LegalizeOp(LastCALLSEQ_END);
1162 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1165 case ISD::CALLSEQ_END:
1166 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1167 // will cause this node to be legalized as well as handling libcalls right.
1168 if (LastCALLSEQ_END.Val != Node) {
1169 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1170 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1171 assert(I != LegalizedNodes.end() &&
1172 "Legalizing the call start should have legalized this node!");
1176 // Otherwise, the call start has been legalized and everything is going
1177 // according to plan. Just legalize ourselves normally here.
1178 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1179 // Do not try to legalize the target-specific arguments (#1+), except for
1180 // an optional flag input.
1181 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1182 if (Tmp1 != Node->getOperand(0)) {
1183 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1185 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1188 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1189 if (Tmp1 != Node->getOperand(0) ||
1190 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1191 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1194 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1197 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1198 // This finishes up call legalization.
1199 IsLegalizingCall = false;
1201 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1202 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1203 if (Node->getNumValues() == 2)
1204 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1205 return Result.getValue(Op.ResNo);
1206 case ISD::DYNAMIC_STACKALLOC: {
1207 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1208 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1209 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1210 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1212 Tmp1 = Result.getValue(0);
1213 Tmp2 = Result.getValue(1);
1214 switch (TLI.getOperationAction(Node->getOpcode(),
1215 Node->getValueType(0))) {
1216 default: assert(0 && "This action is not supported yet!");
1217 case TargetLowering::Expand: {
1218 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1219 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1220 " not tell us which reg is the stack pointer!");
1221 SDOperand Chain = Tmp1.getOperand(0);
1222 SDOperand Size = Tmp2.getOperand(1);
1223 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1224 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1225 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1226 Tmp1 = LegalizeOp(Tmp1);
1227 Tmp2 = LegalizeOp(Tmp2);
1230 case TargetLowering::Custom:
1231 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1233 Tmp1 = LegalizeOp(Tmp3);
1234 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1237 case TargetLowering::Legal:
1240 // Since this op produce two values, make sure to remember that we
1241 // legalized both of them.
1242 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1243 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1244 return Op.ResNo ? Tmp2 : Tmp1;
1246 case ISD::INLINEASM: {
1247 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1248 bool Changed = false;
1249 // Legalize all of the operands of the inline asm, in case they are nodes
1250 // that need to be expanded or something. Note we skip the asm string and
1251 // all of the TargetConstant flags.
1252 SDOperand Op = LegalizeOp(Ops[0]);
1253 Changed = Op != Ops[0];
1256 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1257 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1258 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1259 for (++i; NumVals; ++i, --NumVals) {
1260 SDOperand Op = LegalizeOp(Ops[i]);
1269 Op = LegalizeOp(Ops.back());
1270 Changed |= Op != Ops.back();
1275 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1277 // INLINE asm returns a chain and flag, make sure to add both to the map.
1278 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1279 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1280 return Result.getValue(Op.ResNo);
1283 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1284 // Ensure that libcalls are emitted before a branch.
1285 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1286 Tmp1 = LegalizeOp(Tmp1);
1287 LastCALLSEQ_END = DAG.getEntryNode();
1289 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1292 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1293 // Ensure that libcalls are emitted before a branch.
1294 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1295 Tmp1 = LegalizeOp(Tmp1);
1296 LastCALLSEQ_END = DAG.getEntryNode();
1298 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1299 default: assert(0 && "Indirect target must be legal type (pointer)!");
1301 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1304 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1307 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1308 // Ensure that libcalls are emitted before a branch.
1309 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1310 Tmp1 = LegalizeOp(Tmp1);
1311 LastCALLSEQ_END = DAG.getEntryNode();
1313 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1314 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1316 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1317 default: assert(0 && "This action is not supported yet!");
1318 case TargetLowering::Legal: break;
1319 case TargetLowering::Custom:
1320 Tmp1 = TLI.LowerOperation(Result, DAG);
1321 if (Tmp1.Val) Result = Tmp1;
1323 case TargetLowering::Expand: {
1324 SDOperand Chain = Result.getOperand(0);
1325 SDOperand Table = Result.getOperand(1);
1326 SDOperand Index = Result.getOperand(2);
1328 MVT::ValueType PTy = TLI.getPointerTy();
1329 MachineFunction &MF = DAG.getMachineFunction();
1330 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1331 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1332 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1335 switch (EntrySize) {
1336 default: assert(0 && "Size of jump table not supported yet."); break;
1337 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1338 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1341 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1342 // For PIC, the sequence is:
1343 // BRIND(load(Jumptable + index) + RelocBase)
1344 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
1346 if (TLI.usesGlobalOffsetTable())
1347 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
1350 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
1351 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
1352 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1354 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD);
1360 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1361 // Ensure that libcalls are emitted before a return.
1362 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1363 Tmp1 = LegalizeOp(Tmp1);
1364 LastCALLSEQ_END = DAG.getEntryNode();
1366 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1367 case Expand: assert(0 && "It's impossible to expand bools");
1369 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1372 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1374 // The top bits of the promoted condition are not necessarily zero, ensure
1375 // that the value is properly zero extended.
1376 if (!TLI.MaskedValueIsZero(Tmp2,
1377 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1378 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1382 // Basic block destination (Op#2) is always legal.
1383 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1385 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1386 default: assert(0 && "This action is not supported yet!");
1387 case TargetLowering::Legal: break;
1388 case TargetLowering::Custom:
1389 Tmp1 = TLI.LowerOperation(Result, DAG);
1390 if (Tmp1.Val) Result = Tmp1;
1392 case TargetLowering::Expand:
1393 // Expand brcond's setcc into its constituent parts and create a BR_CC
1395 if (Tmp2.getOpcode() == ISD::SETCC) {
1396 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1397 Tmp2.getOperand(0), Tmp2.getOperand(1),
1398 Node->getOperand(2));
1400 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1401 DAG.getCondCode(ISD::SETNE), Tmp2,
1402 DAG.getConstant(0, Tmp2.getValueType()),
1403 Node->getOperand(2));
1409 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1410 // Ensure that libcalls are emitted before a branch.
1411 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1412 Tmp1 = LegalizeOp(Tmp1);
1413 Tmp2 = Node->getOperand(2); // LHS
1414 Tmp3 = Node->getOperand(3); // RHS
1415 Tmp4 = Node->getOperand(1); // CC
1417 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1418 LastCALLSEQ_END = DAG.getEntryNode();
1420 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1421 // the LHS is a legal SETCC itself. In this case, we need to compare
1422 // the result against zero to select between true and false values.
1423 if (Tmp3.Val == 0) {
1424 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1425 Tmp4 = DAG.getCondCode(ISD::SETNE);
1428 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1429 Node->getOperand(4));
1431 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1432 default: assert(0 && "Unexpected action for BR_CC!");
1433 case TargetLowering::Legal: break;
1434 case TargetLowering::Custom:
1435 Tmp4 = TLI.LowerOperation(Result, DAG);
1436 if (Tmp4.Val) Result = Tmp4;
1441 LoadSDNode *LD = cast<LoadSDNode>(Node);
1442 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1443 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1445 ISD::LoadExtType ExtType = LD->getExtensionType();
1446 if (ExtType == ISD::NON_EXTLOAD) {
1447 MVT::ValueType VT = Node->getValueType(0);
1448 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1449 Tmp3 = Result.getValue(0);
1450 Tmp4 = Result.getValue(1);
1452 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1453 default: assert(0 && "This action is not supported yet!");
1454 case TargetLowering::Legal: break;
1455 case TargetLowering::Custom:
1456 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1458 Tmp3 = LegalizeOp(Tmp1);
1459 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1462 case TargetLowering::Promote: {
1463 // Only promote a load of vector type to another.
1464 assert(MVT::isVector(VT) && "Cannot promote this load!");
1465 // Change base type to a different vector type.
1466 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1468 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1469 LD->getSrcValueOffset());
1470 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1471 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1475 // Since loads produce two values, make sure to remember that we
1476 // legalized both of them.
1477 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1478 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1479 return Op.ResNo ? Tmp4 : Tmp3;
1481 MVT::ValueType SrcVT = LD->getLoadedVT();
1482 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1483 default: assert(0 && "This action is not supported yet!");
1484 case TargetLowering::Promote:
1485 assert(SrcVT == MVT::i1 &&
1486 "Can only promote extending LOAD from i1 -> i8!");
1487 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1488 LD->getSrcValue(), LD->getSrcValueOffset(),
1490 Tmp1 = Result.getValue(0);
1491 Tmp2 = Result.getValue(1);
1493 case TargetLowering::Custom:
1496 case TargetLowering::Legal:
1497 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1498 Tmp1 = Result.getValue(0);
1499 Tmp2 = Result.getValue(1);
1502 Tmp3 = TLI.LowerOperation(Result, DAG);
1504 Tmp1 = LegalizeOp(Tmp3);
1505 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1509 case TargetLowering::Expand:
1510 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1511 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1512 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1513 LD->getSrcValueOffset());
1514 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1515 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1516 Tmp2 = LegalizeOp(Load.getValue(1));
1519 assert(ExtType != ISD::EXTLOAD && "EXTLOAD should always be supported!");
1520 // Turn the unsupported load into an EXTLOAD followed by an explicit
1521 // zero/sign extend inreg.
1522 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1523 Tmp1, Tmp2, LD->getSrcValue(),
1524 LD->getSrcValueOffset(), SrcVT);
1526 if (ExtType == ISD::SEXTLOAD)
1527 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1528 Result, DAG.getValueType(SrcVT));
1530 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1531 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1532 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1535 // Since loads produce two values, make sure to remember that we legalized
1537 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1538 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1539 return Op.ResNo ? Tmp2 : Tmp1;
1542 case ISD::EXTRACT_ELEMENT: {
1543 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1544 switch (getTypeAction(OpTy)) {
1545 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1547 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1549 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1550 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1551 TLI.getShiftAmountTy()));
1552 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1555 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1556 Node->getOperand(0));
1560 // Get both the low and high parts.
1561 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1562 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1563 Result = Tmp2; // 1 -> Hi
1565 Result = Tmp1; // 0 -> Lo
1571 case ISD::CopyToReg:
1572 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1574 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1575 "Register type must be legal!");
1576 // Legalize the incoming value (must be a legal type).
1577 Tmp2 = LegalizeOp(Node->getOperand(2));
1578 if (Node->getNumValues() == 1) {
1579 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1581 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1582 if (Node->getNumOperands() == 4) {
1583 Tmp3 = LegalizeOp(Node->getOperand(3));
1584 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1587 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1590 // Since this produces two values, make sure to remember that we legalized
1592 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1593 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1599 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1601 // Ensure that libcalls are emitted before a return.
1602 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1603 Tmp1 = LegalizeOp(Tmp1);
1604 LastCALLSEQ_END = DAG.getEntryNode();
1606 switch (Node->getNumOperands()) {
1608 Tmp2 = Node->getOperand(1);
1609 Tmp3 = Node->getOperand(2); // Signness
1610 switch (getTypeAction(Tmp2.getValueType())) {
1612 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1615 if (Tmp2.getValueType() != MVT::Vector) {
1617 ExpandOp(Tmp2, Lo, Hi);
1619 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1621 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1622 Result = LegalizeOp(Result);
1624 SDNode *InVal = Tmp2.Val;
1626 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1627 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1629 // Figure out if there is a Packed type corresponding to this Vector
1630 // type. If so, convert to the packed type.
1631 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1632 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1633 // Turn this into a return of the packed type.
1634 Tmp2 = PackVectorOp(Tmp2, TVT);
1635 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1636 } else if (NumElems == 1) {
1637 // Turn this into a return of the scalar type.
1638 Tmp2 = PackVectorOp(Tmp2, EVT);
1639 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1641 // FIXME: Returns of gcc generic vectors smaller than a legal type
1642 // should be returned in integer registers!
1644 // The scalarized value type may not be legal, e.g. it might require
1645 // promotion or expansion. Relegalize the return.
1646 Result = LegalizeOp(Result);
1648 // FIXME: Returns of gcc generic vectors larger than a legal vector
1649 // type should be returned by reference!
1651 SplitVectorOp(Tmp2, Lo, Hi);
1652 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1653 Result = LegalizeOp(Result);
1658 Tmp2 = PromoteOp(Node->getOperand(1));
1659 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1660 Result = LegalizeOp(Result);
1665 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1667 default: { // ret <values>
1668 SmallVector<SDOperand, 8> NewValues;
1669 NewValues.push_back(Tmp1);
1670 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1671 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1673 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1674 NewValues.push_back(Node->getOperand(i+1));
1678 assert(Node->getOperand(i).getValueType() != MVT::Vector &&
1679 "FIXME: TODO: implement returning non-legal vector types!");
1680 ExpandOp(Node->getOperand(i), Lo, Hi);
1681 NewValues.push_back(Lo);
1682 NewValues.push_back(Node->getOperand(i+1));
1684 NewValues.push_back(Hi);
1685 NewValues.push_back(Node->getOperand(i+1));
1690 assert(0 && "Can't promote multiple return value yet!");
1693 if (NewValues.size() == Node->getNumOperands())
1694 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1696 Result = DAG.getNode(ISD::RET, MVT::Other,
1697 &NewValues[0], NewValues.size());
1702 if (Result.getOpcode() == ISD::RET) {
1703 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1704 default: assert(0 && "This action is not supported yet!");
1705 case TargetLowering::Legal: break;
1706 case TargetLowering::Custom:
1707 Tmp1 = TLI.LowerOperation(Result, DAG);
1708 if (Tmp1.Val) Result = Tmp1;
1714 StoreSDNode *ST = cast<StoreSDNode>(Node);
1715 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1716 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1718 if (!ST->isTruncatingStore()) {
1719 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1720 // FIXME: We shouldn't do this for TargetConstantFP's.
1721 // FIXME: move this to the DAG Combiner! Note that we can't regress due
1722 // to phase ordering between legalized code and the dag combiner. This
1723 // probably means that we need to integrate dag combiner and legalizer
1725 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
1726 if (CFP->getValueType(0) == MVT::f32) {
1727 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1729 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1730 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1732 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1733 ST->getSrcValueOffset());
1737 switch (getTypeAction(ST->getStoredVT())) {
1739 Tmp3 = LegalizeOp(ST->getValue());
1740 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1743 MVT::ValueType VT = Tmp3.getValueType();
1744 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1745 default: assert(0 && "This action is not supported yet!");
1746 case TargetLowering::Legal: break;
1747 case TargetLowering::Custom:
1748 Tmp1 = TLI.LowerOperation(Result, DAG);
1749 if (Tmp1.Val) Result = Tmp1;
1751 case TargetLowering::Promote:
1752 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1753 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1754 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1755 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
1756 ST->getSrcValue(), ST->getSrcValueOffset());
1762 // Truncate the value and store the result.
1763 Tmp3 = PromoteOp(ST->getValue());
1764 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1765 ST->getSrcValueOffset(), ST->getStoredVT());
1769 unsigned IncrementSize = 0;
1772 // If this is a vector type, then we have to calculate the increment as
1773 // the product of the element size in bytes, and the number of elements
1774 // in the high half of the vector.
1775 if (ST->getValue().getValueType() == MVT::Vector) {
1776 SDNode *InVal = ST->getValue().Val;
1778 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1779 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1781 // Figure out if there is a Packed type corresponding to this Vector
1782 // type. If so, convert to the packed type.
1783 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1784 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1785 // Turn this into a normal store of the packed type.
1786 Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1787 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1788 ST->getSrcValueOffset());
1789 Result = LegalizeOp(Result);
1791 } else if (NumElems == 1) {
1792 // Turn this into a normal store of the scalar type.
1793 Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1794 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1795 ST->getSrcValueOffset());
1796 // The scalarized value type may not be legal, e.g. it might require
1797 // promotion or expansion. Relegalize the scalar store.
1798 Result = LegalizeOp(Result);
1801 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1802 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1805 ExpandOp(Node->getOperand(1), Lo, Hi);
1806 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
1808 if (!TLI.isLittleEndian())
1812 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
1813 ST->getSrcValueOffset());
1815 if (Hi.Val == NULL) {
1816 // Must be int <-> float one-to-one expansion.
1821 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1822 getIntPtrConstant(IncrementSize));
1823 assert(isTypeLegal(Tmp2.getValueType()) &&
1824 "Pointers must be legal!");
1825 // FIXME: This sets the srcvalue of both halves to be the same, which is
1827 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
1828 ST->getSrcValueOffset());
1829 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1834 assert(isTypeLegal(ST->getValue().getValueType()) &&
1835 "Cannot handle illegal TRUNCSTORE yet!");
1836 Tmp3 = LegalizeOp(ST->getValue());
1838 // The only promote case we handle is TRUNCSTORE:i1 X into
1839 // -> TRUNCSTORE:i8 (and X, 1)
1840 if (ST->getStoredVT() == MVT::i1 &&
1841 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
1842 // Promote the bool to a mask then store.
1843 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
1844 DAG.getConstant(1, Tmp3.getValueType()));
1845 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1846 ST->getSrcValueOffset(), MVT::i8);
1847 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1848 Tmp2 != ST->getBasePtr()) {
1849 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1853 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
1854 switch (TLI.getStoreXAction(StVT)) {
1855 default: assert(0 && "This action is not supported yet!");
1856 case TargetLowering::Legal: break;
1857 case TargetLowering::Custom:
1858 Tmp1 = TLI.LowerOperation(Result, DAG);
1859 if (Tmp1.Val) Result = Tmp1;
1866 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1867 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1869 case ISD::STACKSAVE:
1870 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1871 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1872 Tmp1 = Result.getValue(0);
1873 Tmp2 = Result.getValue(1);
1875 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1876 default: assert(0 && "This action is not supported yet!");
1877 case TargetLowering::Legal: break;
1878 case TargetLowering::Custom:
1879 Tmp3 = TLI.LowerOperation(Result, DAG);
1881 Tmp1 = LegalizeOp(Tmp3);
1882 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1885 case TargetLowering::Expand:
1886 // Expand to CopyFromReg if the target set
1887 // StackPointerRegisterToSaveRestore.
1888 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1889 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1890 Node->getValueType(0));
1891 Tmp2 = Tmp1.getValue(1);
1893 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1894 Tmp2 = Node->getOperand(0);
1899 // Since stacksave produce two values, make sure to remember that we
1900 // legalized both of them.
1901 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1902 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1903 return Op.ResNo ? Tmp2 : Tmp1;
1905 case ISD::STACKRESTORE:
1906 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1907 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1908 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1910 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1911 default: assert(0 && "This action is not supported yet!");
1912 case TargetLowering::Legal: break;
1913 case TargetLowering::Custom:
1914 Tmp1 = TLI.LowerOperation(Result, DAG);
1915 if (Tmp1.Val) Result = Tmp1;
1917 case TargetLowering::Expand:
1918 // Expand to CopyToReg if the target set
1919 // StackPointerRegisterToSaveRestore.
1920 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1921 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1929 case ISD::READCYCLECOUNTER:
1930 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1931 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1932 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
1933 Node->getValueType(0))) {
1934 default: assert(0 && "This action is not supported yet!");
1935 case TargetLowering::Legal:
1936 Tmp1 = Result.getValue(0);
1937 Tmp2 = Result.getValue(1);
1939 case TargetLowering::Custom:
1940 Result = TLI.LowerOperation(Result, DAG);
1941 Tmp1 = LegalizeOp(Result.getValue(0));
1942 Tmp2 = LegalizeOp(Result.getValue(1));
1946 // Since rdcc produce two values, make sure to remember that we legalized
1948 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1949 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1953 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1954 case Expand: assert(0 && "It's impossible to expand bools");
1956 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1959 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1960 // Make sure the condition is either zero or one.
1961 if (!TLI.MaskedValueIsZero(Tmp1,
1962 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
1963 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1966 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1967 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1969 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1971 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1972 default: assert(0 && "This action is not supported yet!");
1973 case TargetLowering::Legal: break;
1974 case TargetLowering::Custom: {
1975 Tmp1 = TLI.LowerOperation(Result, DAG);
1976 if (Tmp1.Val) Result = Tmp1;
1979 case TargetLowering::Expand:
1980 if (Tmp1.getOpcode() == ISD::SETCC) {
1981 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1983 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1985 Result = DAG.getSelectCC(Tmp1,
1986 DAG.getConstant(0, Tmp1.getValueType()),
1987 Tmp2, Tmp3, ISD::SETNE);
1990 case TargetLowering::Promote: {
1991 MVT::ValueType NVT =
1992 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1993 unsigned ExtOp, TruncOp;
1994 if (MVT::isVector(Tmp2.getValueType())) {
1995 ExtOp = ISD::BIT_CONVERT;
1996 TruncOp = ISD::BIT_CONVERT;
1997 } else if (MVT::isInteger(Tmp2.getValueType())) {
1998 ExtOp = ISD::ANY_EXTEND;
1999 TruncOp = ISD::TRUNCATE;
2001 ExtOp = ISD::FP_EXTEND;
2002 TruncOp = ISD::FP_ROUND;
2004 // Promote each of the values to the new type.
2005 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2006 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2007 // Perform the larger operation, then round down.
2008 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2009 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2014 case ISD::SELECT_CC: {
2015 Tmp1 = Node->getOperand(0); // LHS
2016 Tmp2 = Node->getOperand(1); // RHS
2017 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2018 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2019 SDOperand CC = Node->getOperand(4);
2021 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2023 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2024 // the LHS is a legal SETCC itself. In this case, we need to compare
2025 // the result against zero to select between true and false values.
2026 if (Tmp2.Val == 0) {
2027 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2028 CC = DAG.getCondCode(ISD::SETNE);
2030 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2032 // Everything is legal, see if we should expand this op or something.
2033 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2034 default: assert(0 && "This action is not supported yet!");
2035 case TargetLowering::Legal: break;
2036 case TargetLowering::Custom:
2037 Tmp1 = TLI.LowerOperation(Result, DAG);
2038 if (Tmp1.Val) Result = Tmp1;
2044 Tmp1 = Node->getOperand(0);
2045 Tmp2 = Node->getOperand(1);
2046 Tmp3 = Node->getOperand(2);
2047 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2049 // If we had to Expand the SetCC operands into a SELECT node, then it may
2050 // not always be possible to return a true LHS & RHS. In this case, just
2051 // return the value we legalized, returned in the LHS
2052 if (Tmp2.Val == 0) {
2057 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2058 default: assert(0 && "Cannot handle this action for SETCC yet!");
2059 case TargetLowering::Custom:
2062 case TargetLowering::Legal:
2063 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2065 Tmp4 = TLI.LowerOperation(Result, DAG);
2066 if (Tmp4.Val) Result = Tmp4;
2069 case TargetLowering::Promote: {
2070 // First step, figure out the appropriate operation to use.
2071 // Allow SETCC to not be supported for all legal data types
2072 // Mostly this targets FP
2073 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2074 MVT::ValueType OldVT = NewInTy;
2076 // Scan for the appropriate larger type to use.
2078 NewInTy = (MVT::ValueType)(NewInTy+1);
2080 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2081 "Fell off of the edge of the integer world");
2082 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2083 "Fell off of the edge of the floating point world");
2085 // If the target supports SETCC of this type, use it.
2086 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2089 if (MVT::isInteger(NewInTy))
2090 assert(0 && "Cannot promote Legal Integer SETCC yet");
2092 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2093 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2095 Tmp1 = LegalizeOp(Tmp1);
2096 Tmp2 = LegalizeOp(Tmp2);
2097 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2098 Result = LegalizeOp(Result);
2101 case TargetLowering::Expand:
2102 // Expand a setcc node into a select_cc of the same condition, lhs, and
2103 // rhs that selects between const 1 (true) and const 0 (false).
2104 MVT::ValueType VT = Node->getValueType(0);
2105 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2106 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2113 case ISD::MEMMOVE: {
2114 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2115 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2117 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2118 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2119 case Expand: assert(0 && "Cannot expand a byte!");
2121 Tmp3 = LegalizeOp(Node->getOperand(2));
2124 Tmp3 = PromoteOp(Node->getOperand(2));
2128 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2132 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2134 // Length is too big, just take the lo-part of the length.
2136 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2140 Tmp4 = LegalizeOp(Node->getOperand(3));
2143 Tmp4 = PromoteOp(Node->getOperand(3));
2148 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2149 case Expand: assert(0 && "Cannot expand this yet!");
2151 Tmp5 = LegalizeOp(Node->getOperand(4));
2154 Tmp5 = PromoteOp(Node->getOperand(4));
2158 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2159 default: assert(0 && "This action not implemented for this operation!");
2160 case TargetLowering::Custom:
2163 case TargetLowering::Legal:
2164 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2166 Tmp1 = TLI.LowerOperation(Result, DAG);
2167 if (Tmp1.Val) Result = Tmp1;
2170 case TargetLowering::Expand: {
2171 // Otherwise, the target does not support this operation. Lower the
2172 // operation to an explicit libcall as appropriate.
2173 MVT::ValueType IntPtr = TLI.getPointerTy();
2174 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2175 TargetLowering::ArgListTy Args;
2176 TargetLowering::ArgListEntry Entry;
2178 const char *FnName = 0;
2179 if (Node->getOpcode() == ISD::MEMSET) {
2180 Entry.Node = Tmp2; Entry.isSigned = false; Entry.Ty = IntPtrTy;
2181 Entry.isInReg = false;
2182 Args.push_back(Entry);
2183 // Extend the (previously legalized) ubyte argument to be an int value
2185 if (Tmp3.getValueType() > MVT::i32)
2186 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2188 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2189 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSigned = true;
2190 Entry.isInReg = false;
2191 Args.push_back(Entry);
2192 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSigned = false;
2193 Args.push_back(Entry);
2196 } else if (Node->getOpcode() == ISD::MEMCPY ||
2197 Node->getOpcode() == ISD::MEMMOVE) {
2198 Entry.Ty = IntPtrTy; Entry.isSigned = false; Entry.isInReg = false;
2199 Entry.Node = Tmp2; Args.push_back(Entry);
2200 Entry.Node = Tmp3; Args.push_back(Entry);
2201 Entry.Node = Tmp4; Args.push_back(Entry);
2202 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2204 assert(0 && "Unknown op!");
2207 std::pair<SDOperand,SDOperand> CallResult =
2208 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2209 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2210 Result = CallResult.second;
2217 case ISD::SHL_PARTS:
2218 case ISD::SRA_PARTS:
2219 case ISD::SRL_PARTS: {
2220 SmallVector<SDOperand, 8> Ops;
2221 bool Changed = false;
2222 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2223 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2224 Changed |= Ops.back() != Node->getOperand(i);
2227 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2229 switch (TLI.getOperationAction(Node->getOpcode(),
2230 Node->getValueType(0))) {
2231 default: assert(0 && "This action is not supported yet!");
2232 case TargetLowering::Legal: break;
2233 case TargetLowering::Custom:
2234 Tmp1 = TLI.LowerOperation(Result, DAG);
2236 SDOperand Tmp2, RetVal(0, 0);
2237 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2238 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2239 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2243 assert(RetVal.Val && "Illegal result number");
2249 // Since these produce multiple values, make sure to remember that we
2250 // legalized all of them.
2251 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2252 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2253 return Result.getValue(Op.ResNo);
2274 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2275 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2276 case Expand: assert(0 && "Not possible");
2278 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2281 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2285 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2287 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2288 default: assert(0 && "BinOp legalize operation not supported");
2289 case TargetLowering::Legal: break;
2290 case TargetLowering::Custom:
2291 Tmp1 = TLI.LowerOperation(Result, DAG);
2292 if (Tmp1.Val) Result = Tmp1;
2294 case TargetLowering::Expand: {
2295 if (Node->getValueType(0) == MVT::i32) {
2296 switch (Node->getOpcode()) {
2297 default: assert(0 && "Do not know how to expand this integer BinOp!");
2300 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV
2301 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2303 bool isSigned = Node->getOpcode() == ISD::SDIV;
2304 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2309 assert(MVT::isVector(Node->getValueType(0)) &&
2310 "Cannot expand this binary operator!");
2311 // Expand the operation into a bunch of nasty scalar code.
2312 SmallVector<SDOperand, 8> Ops;
2313 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
2314 MVT::ValueType PtrVT = TLI.getPointerTy();
2315 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2317 SDOperand Idx = DAG.getConstant(i, PtrVT);
2318 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2319 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2320 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2322 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2323 &Ops[0], Ops.size());
2326 case TargetLowering::Promote: {
2327 switch (Node->getOpcode()) {
2328 default: assert(0 && "Do not know how to promote this BinOp!");
2332 MVT::ValueType OVT = Node->getValueType(0);
2333 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2334 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2335 // Bit convert each of the values to the new type.
2336 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2337 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2338 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2339 // Bit convert the result back the original type.
2340 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2348 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2349 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2350 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2351 case Expand: assert(0 && "Not possible");
2353 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2356 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2360 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2362 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2363 default: assert(0 && "Operation not supported");
2364 case TargetLowering::Custom:
2365 Tmp1 = TLI.LowerOperation(Result, DAG);
2366 if (Tmp1.Val) Result = Tmp1;
2368 case TargetLowering::Legal: break;
2369 case TargetLowering::Expand: {
2370 // If this target supports fabs/fneg natively and select is cheap,
2371 // do this efficiently.
2372 if (!TLI.isSelectExpensive() &&
2373 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
2374 TargetLowering::Legal &&
2375 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
2376 TargetLowering::Legal) {
2377 // Get the sign bit of the RHS.
2378 MVT::ValueType IVT =
2379 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2380 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2381 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2382 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2383 // Get the absolute value of the result.
2384 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2385 // Select between the nabs and abs value based on the sign bit of
2387 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2388 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2391 Result = LegalizeOp(Result);
2395 // Otherwise, do bitwise ops!
2396 MVT::ValueType NVT =
2397 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
2398 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
2399 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
2400 Result = LegalizeOp(Result);
2408 Tmp1 = LegalizeOp(Node->getOperand(0));
2409 Tmp2 = LegalizeOp(Node->getOperand(1));
2410 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2411 // Since this produces two values, make sure to remember that we legalized
2413 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2414 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2419 Tmp1 = LegalizeOp(Node->getOperand(0));
2420 Tmp2 = LegalizeOp(Node->getOperand(1));
2421 Tmp3 = LegalizeOp(Node->getOperand(2));
2422 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2423 // Since this produces two values, make sure to remember that we legalized
2425 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2426 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2429 case ISD::BUILD_PAIR: {
2430 MVT::ValueType PairTy = Node->getValueType(0);
2431 // TODO: handle the case where the Lo and Hi operands are not of legal type
2432 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2433 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2434 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2435 case TargetLowering::Promote:
2436 case TargetLowering::Custom:
2437 assert(0 && "Cannot promote/custom this yet!");
2438 case TargetLowering::Legal:
2439 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2440 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2442 case TargetLowering::Expand:
2443 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2444 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2445 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2446 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2447 TLI.getShiftAmountTy()));
2448 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2457 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2458 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2460 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2461 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2462 case TargetLowering::Custom:
2465 case TargetLowering::Legal:
2466 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2468 Tmp1 = TLI.LowerOperation(Result, DAG);
2469 if (Tmp1.Val) Result = Tmp1;
2472 case TargetLowering::Expand:
2473 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2474 bool isSigned = DivOpc == ISD::SDIV;
2475 if (MVT::isInteger(Node->getValueType(0))) {
2476 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2477 TargetLowering::Legal) {
2479 MVT::ValueType VT = Node->getValueType(0);
2480 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2481 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2482 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2484 assert(Node->getValueType(0) == MVT::i32 &&
2485 "Cannot expand this binary operator!");
2486 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
2487 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
2489 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2492 // Floating point mod -> fmod libcall.
2493 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2494 ? RTLIB::REM_F32 : RTLIB::REM_F64;
2496 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2497 false/*sign irrelevant*/, Dummy);
2503 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2504 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2506 MVT::ValueType VT = Node->getValueType(0);
2507 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2508 default: assert(0 && "This action is not supported yet!");
2509 case TargetLowering::Custom:
2512 case TargetLowering::Legal:
2513 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2514 Result = Result.getValue(0);
2515 Tmp1 = Result.getValue(1);
2518 Tmp2 = TLI.LowerOperation(Result, DAG);
2520 Result = LegalizeOp(Tmp2);
2521 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2525 case TargetLowering::Expand: {
2526 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2527 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2528 SV->getValue(), SV->getOffset());
2529 // Increment the pointer, VAList, to the next vaarg
2530 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2531 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2532 TLI.getPointerTy()));
2533 // Store the incremented VAList to the legalized pointer
2534 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
2536 // Load the actual argument out of the pointer VAList
2537 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2538 Tmp1 = LegalizeOp(Result.getValue(1));
2539 Result = LegalizeOp(Result);
2543 // Since VAARG produces two values, make sure to remember that we
2544 // legalized both of them.
2545 AddLegalizedOperand(SDOperand(Node, 0), Result);
2546 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2547 return Op.ResNo ? Tmp1 : Result;
2551 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2552 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2553 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2555 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2556 default: assert(0 && "This action is not supported yet!");
2557 case TargetLowering::Custom:
2560 case TargetLowering::Legal:
2561 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2562 Node->getOperand(3), Node->getOperand(4));
2564 Tmp1 = TLI.LowerOperation(Result, DAG);
2565 if (Tmp1.Val) Result = Tmp1;
2568 case TargetLowering::Expand:
2569 // This defaults to loading a pointer from the input and storing it to the
2570 // output, returning the chain.
2571 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
2572 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
2573 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
2575 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
2582 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2583 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2585 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2586 default: assert(0 && "This action is not supported yet!");
2587 case TargetLowering::Custom:
2590 case TargetLowering::Legal:
2591 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2593 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2594 if (Tmp1.Val) Result = Tmp1;
2597 case TargetLowering::Expand:
2598 Result = Tmp1; // Default to a no-op, return the chain
2604 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2605 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2607 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2609 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2610 default: assert(0 && "This action is not supported yet!");
2611 case TargetLowering::Legal: break;
2612 case TargetLowering::Custom:
2613 Tmp1 = TLI.LowerOperation(Result, DAG);
2614 if (Tmp1.Val) Result = Tmp1;
2621 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2622 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2624 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2625 "Cannot handle this yet!");
2626 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2630 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2631 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2632 case TargetLowering::Custom:
2633 assert(0 && "Cannot custom legalize this yet!");
2634 case TargetLowering::Legal:
2635 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2637 case TargetLowering::Promote: {
2638 MVT::ValueType OVT = Tmp1.getValueType();
2639 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2640 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2642 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2643 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2644 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2645 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2648 case TargetLowering::Expand:
2649 Result = ExpandBSWAP(Tmp1);
2657 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2658 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2659 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2660 case TargetLowering::Legal:
2661 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2663 case TargetLowering::Promote: {
2664 MVT::ValueType OVT = Tmp1.getValueType();
2665 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2667 // Zero extend the argument.
2668 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2669 // Perform the larger operation, then subtract if needed.
2670 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2671 switch (Node->getOpcode()) {
2676 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2677 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2678 DAG.getConstant(getSizeInBits(NVT), NVT),
2680 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2681 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2684 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2685 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2686 DAG.getConstant(getSizeInBits(NVT) -
2687 getSizeInBits(OVT), NVT));
2692 case TargetLowering::Expand:
2693 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2704 Tmp1 = LegalizeOp(Node->getOperand(0));
2705 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2706 case TargetLowering::Promote:
2707 case TargetLowering::Custom:
2710 case TargetLowering::Legal:
2711 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2713 Tmp1 = TLI.LowerOperation(Result, DAG);
2714 if (Tmp1.Val) Result = Tmp1;
2717 case TargetLowering::Expand:
2718 switch (Node->getOpcode()) {
2719 default: assert(0 && "Unreachable!");
2721 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2722 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2723 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2726 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2727 MVT::ValueType VT = Node->getValueType(0);
2728 Tmp2 = DAG.getConstantFP(0.0, VT);
2729 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2730 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2731 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2737 MVT::ValueType VT = Node->getValueType(0);
2738 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2739 switch(Node->getOpcode()) {
2741 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
2744 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
2747 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64;
2749 default: assert(0 && "Unreachable!");
2752 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2753 false/*sign irrelevant*/, Dummy);
2761 // We always lower FPOWI into a libcall. No target support it yet.
2762 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2763 ? RTLIB::POWI_F32 : RTLIB::POWI_F64;
2765 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2766 false/*sign irrelevant*/, Dummy);
2769 case ISD::BIT_CONVERT:
2770 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2771 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2773 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2774 Node->getOperand(0).getValueType())) {
2775 default: assert(0 && "Unknown operation action!");
2776 case TargetLowering::Expand:
2777 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2779 case TargetLowering::Legal:
2780 Tmp1 = LegalizeOp(Node->getOperand(0));
2781 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2786 case ISD::VBIT_CONVERT: {
2787 assert(Op.getOperand(0).getValueType() == MVT::Vector &&
2788 "Can only have VBIT_CONVERT where input or output is MVT::Vector!");
2790 // The input has to be a vector type, we have to either scalarize it, pack
2791 // it, or convert it based on whether the input vector type is legal.
2792 SDNode *InVal = Node->getOperand(0).Val;
2794 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
2795 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
2797 // Figure out if there is a Packed type corresponding to this Vector
2798 // type. If so, convert to the packed type.
2799 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2800 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
2801 // Turn this into a bit convert of the packed input.
2802 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2803 PackVectorOp(Node->getOperand(0), TVT));
2805 } else if (NumElems == 1) {
2806 // Turn this into a bit convert of the scalar input.
2807 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2808 PackVectorOp(Node->getOperand(0), EVT));
2811 // FIXME: UNIMP! Store then reload
2812 assert(0 && "Cast from unsupported vector type not implemented yet!");
2816 // Conversion operators. The source and destination have different types.
2817 case ISD::SINT_TO_FP:
2818 case ISD::UINT_TO_FP: {
2819 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2820 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2822 switch (TLI.getOperationAction(Node->getOpcode(),
2823 Node->getOperand(0).getValueType())) {
2824 default: assert(0 && "Unknown operation action!");
2825 case TargetLowering::Custom:
2828 case TargetLowering::Legal:
2829 Tmp1 = LegalizeOp(Node->getOperand(0));
2830 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2832 Tmp1 = TLI.LowerOperation(Result, DAG);
2833 if (Tmp1.Val) Result = Tmp1;
2836 case TargetLowering::Expand:
2837 Result = ExpandLegalINT_TO_FP(isSigned,
2838 LegalizeOp(Node->getOperand(0)),
2839 Node->getValueType(0));
2841 case TargetLowering::Promote:
2842 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2843 Node->getValueType(0),
2849 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2850 Node->getValueType(0), Node->getOperand(0));
2853 Tmp1 = PromoteOp(Node->getOperand(0));
2855 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2856 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2858 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2859 Node->getOperand(0).getValueType());
2861 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2862 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2868 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2870 Tmp1 = LegalizeOp(Node->getOperand(0));
2871 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2874 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2876 // Since the result is legal, we should just be able to truncate the low
2877 // part of the source.
2878 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2881 Result = PromoteOp(Node->getOperand(0));
2882 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2887 case ISD::FP_TO_SINT:
2888 case ISD::FP_TO_UINT:
2889 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2891 Tmp1 = LegalizeOp(Node->getOperand(0));
2893 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2894 default: assert(0 && "Unknown operation action!");
2895 case TargetLowering::Custom:
2898 case TargetLowering::Legal:
2899 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2901 Tmp1 = TLI.LowerOperation(Result, DAG);
2902 if (Tmp1.Val) Result = Tmp1;
2905 case TargetLowering::Promote:
2906 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2907 Node->getOpcode() == ISD::FP_TO_SINT);
2909 case TargetLowering::Expand:
2910 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2911 SDOperand True, False;
2912 MVT::ValueType VT = Node->getOperand(0).getValueType();
2913 MVT::ValueType NVT = Node->getValueType(0);
2914 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2915 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2916 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2917 Node->getOperand(0), Tmp2, ISD::SETLT);
2918 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2919 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2920 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2922 False = DAG.getNode(ISD::XOR, NVT, False,
2923 DAG.getConstant(1ULL << ShiftAmt, NVT));
2924 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2927 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2933 // Convert f32 / f64 to i32 / i64.
2934 MVT::ValueType VT = Op.getValueType();
2935 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2936 switch (Node->getOpcode()) {
2937 case ISD::FP_TO_SINT:
2938 if (Node->getOperand(0).getValueType() == MVT::f32)
2939 LC = (VT == MVT::i32)
2940 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
2942 LC = (VT == MVT::i32)
2943 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
2945 case ISD::FP_TO_UINT:
2946 if (Node->getOperand(0).getValueType() == MVT::f32)
2947 LC = (VT == MVT::i32)
2948 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
2950 LC = (VT == MVT::i32)
2951 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
2953 default: assert(0 && "Unreachable!");
2956 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2957 false/*sign irrelevant*/, Dummy);
2961 Tmp1 = PromoteOp(Node->getOperand(0));
2962 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
2963 Result = LegalizeOp(Result);
2968 case ISD::ANY_EXTEND:
2969 case ISD::ZERO_EXTEND:
2970 case ISD::SIGN_EXTEND:
2971 case ISD::FP_EXTEND:
2973 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2974 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
2976 Tmp1 = LegalizeOp(Node->getOperand(0));
2977 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2980 switch (Node->getOpcode()) {
2981 case ISD::ANY_EXTEND:
2982 Tmp1 = PromoteOp(Node->getOperand(0));
2983 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
2985 case ISD::ZERO_EXTEND:
2986 Result = PromoteOp(Node->getOperand(0));
2987 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2988 Result = DAG.getZeroExtendInReg(Result,
2989 Node->getOperand(0).getValueType());
2991 case ISD::SIGN_EXTEND:
2992 Result = PromoteOp(Node->getOperand(0));
2993 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2994 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2996 DAG.getValueType(Node->getOperand(0).getValueType()));
2998 case ISD::FP_EXTEND:
2999 Result = PromoteOp(Node->getOperand(0));
3000 if (Result.getValueType() != Op.getValueType())
3001 // Dynamically dead while we have only 2 FP types.
3002 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
3005 Result = PromoteOp(Node->getOperand(0));
3006 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
3011 case ISD::FP_ROUND_INREG:
3012 case ISD::SIGN_EXTEND_INREG: {
3013 Tmp1 = LegalizeOp(Node->getOperand(0));
3014 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3016 // If this operation is not supported, convert it to a shl/shr or load/store
3018 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3019 default: assert(0 && "This action not supported for this op yet!");
3020 case TargetLowering::Legal:
3021 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3023 case TargetLowering::Expand:
3024 // If this is an integer extend and shifts are supported, do that.
3025 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3026 // NOTE: we could fall back on load/store here too for targets without
3027 // SAR. However, it is doubtful that any exist.
3028 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3029 MVT::getSizeInBits(ExtraVT);
3030 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3031 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3032 Node->getOperand(0), ShiftCst);
3033 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3035 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3036 // The only way we can lower this is to turn it into a TRUNCSTORE,
3037 // EXTLOAD pair, targetting a temporary location (a stack slot).
3039 // NOTE: there is a choice here between constantly creating new stack
3040 // slots and always reusing the same one. We currently always create
3041 // new ones, as reuse may inhibit scheduling.
3042 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
3043 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty);
3044 unsigned Align = TLI.getTargetData()->getTypeAlignmentPref(Ty);
3045 MachineFunction &MF = DAG.getMachineFunction();
3047 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
3048 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3049 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3050 StackSlot, NULL, 0, ExtraVT);
3051 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
3052 Result, StackSlot, NULL, 0, ExtraVT);
3054 assert(0 && "Unknown op");
3062 assert(Result.getValueType() == Op.getValueType() &&
3063 "Bad legalization!");
3065 // Make sure that the generated code is itself legal.
3067 Result = LegalizeOp(Result);
3069 // Note that LegalizeOp may be reentered even from single-use nodes, which
3070 // means that we always must cache transformed nodes.
3071 AddLegalizedOperand(Op, Result);
3075 /// PromoteOp - Given an operation that produces a value in an invalid type,
3076 /// promote it to compute the value into a larger type. The produced value will
3077 /// have the correct bits for the low portion of the register, but no guarantee
3078 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3079 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3080 MVT::ValueType VT = Op.getValueType();
3081 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3082 assert(getTypeAction(VT) == Promote &&
3083 "Caller should expand or legalize operands that are not promotable!");
3084 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3085 "Cannot promote to smaller type!");
3087 SDOperand Tmp1, Tmp2, Tmp3;
3089 SDNode *Node = Op.Val;
3091 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3092 if (I != PromotedNodes.end()) return I->second;
3094 switch (Node->getOpcode()) {
3095 case ISD::CopyFromReg:
3096 assert(0 && "CopyFromReg must be legal!");
3099 cerr << "NODE: "; Node->dump(); cerr << "\n";
3101 assert(0 && "Do not know how to promote this operator!");
3104 Result = DAG.getNode(ISD::UNDEF, NVT);
3108 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3110 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3111 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3113 case ISD::ConstantFP:
3114 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3115 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3119 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3120 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3121 Node->getOperand(1), Node->getOperand(2));
3125 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3127 Result = LegalizeOp(Node->getOperand(0));
3128 assert(Result.getValueType() >= NVT &&
3129 "This truncation doesn't make sense!");
3130 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3131 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3134 // The truncation is not required, because we don't guarantee anything
3135 // about high bits anyway.
3136 Result = PromoteOp(Node->getOperand(0));
3139 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3140 // Truncate the low part of the expanded value to the result type
3141 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3144 case ISD::SIGN_EXTEND:
3145 case ISD::ZERO_EXTEND:
3146 case ISD::ANY_EXTEND:
3147 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3148 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3150 // Input is legal? Just do extend all the way to the larger type.
3151 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3154 // Promote the reg if it's smaller.
3155 Result = PromoteOp(Node->getOperand(0));
3156 // The high bits are not guaranteed to be anything. Insert an extend.
3157 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3158 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3159 DAG.getValueType(Node->getOperand(0).getValueType()));
3160 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3161 Result = DAG.getZeroExtendInReg(Result,
3162 Node->getOperand(0).getValueType());
3166 case ISD::BIT_CONVERT:
3167 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3168 Result = PromoteOp(Result);
3171 case ISD::FP_EXTEND:
3172 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3174 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3175 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3176 case Promote: assert(0 && "Unreachable with 2 FP types!");
3178 // Input is legal? Do an FP_ROUND_INREG.
3179 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3180 DAG.getValueType(VT));
3185 case ISD::SINT_TO_FP:
3186 case ISD::UINT_TO_FP:
3187 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3189 // No extra round required here.
3190 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3194 Result = PromoteOp(Node->getOperand(0));
3195 if (Node->getOpcode() == ISD::SINT_TO_FP)
3196 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3198 DAG.getValueType(Node->getOperand(0).getValueType()));
3200 Result = DAG.getZeroExtendInReg(Result,
3201 Node->getOperand(0).getValueType());
3202 // No extra round required here.
3203 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3206 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3207 Node->getOperand(0));
3208 // Round if we cannot tolerate excess precision.
3209 if (NoExcessFPPrecision)
3210 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3211 DAG.getValueType(VT));
3216 case ISD::SIGN_EXTEND_INREG:
3217 Result = PromoteOp(Node->getOperand(0));
3218 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3219 Node->getOperand(1));
3221 case ISD::FP_TO_SINT:
3222 case ISD::FP_TO_UINT:
3223 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3226 Tmp1 = Node->getOperand(0);
3229 // The input result is prerounded, so we don't have to do anything
3231 Tmp1 = PromoteOp(Node->getOperand(0));
3234 // If we're promoting a UINT to a larger size, check to see if the new node
3235 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3236 // we can use that instead. This allows us to generate better code for
3237 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3238 // legal, such as PowerPC.
3239 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3240 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3241 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3242 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3243 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3245 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3251 Tmp1 = PromoteOp(Node->getOperand(0));
3252 assert(Tmp1.getValueType() == NVT);
3253 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3254 // NOTE: we do not have to do any extra rounding here for
3255 // NoExcessFPPrecision, because we know the input will have the appropriate
3256 // precision, and these operations don't modify precision at all.
3262 Tmp1 = PromoteOp(Node->getOperand(0));
3263 assert(Tmp1.getValueType() == NVT);
3264 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3265 if (NoExcessFPPrecision)
3266 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3267 DAG.getValueType(VT));
3276 // The input may have strange things in the top bits of the registers, but
3277 // these operations don't care. They may have weird bits going out, but
3278 // that too is okay if they are integer operations.
3279 Tmp1 = PromoteOp(Node->getOperand(0));
3280 Tmp2 = PromoteOp(Node->getOperand(1));
3281 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3282 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3287 Tmp1 = PromoteOp(Node->getOperand(0));
3288 Tmp2 = PromoteOp(Node->getOperand(1));
3289 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3290 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3292 // Floating point operations will give excess precision that we may not be
3293 // able to tolerate. If we DO allow excess precision, just leave it,
3294 // otherwise excise it.
3295 // FIXME: Why would we need to round FP ops more than integer ones?
3296 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3297 if (NoExcessFPPrecision)
3298 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3299 DAG.getValueType(VT));
3304 // These operators require that their input be sign extended.
3305 Tmp1 = PromoteOp(Node->getOperand(0));
3306 Tmp2 = PromoteOp(Node->getOperand(1));
3307 if (MVT::isInteger(NVT)) {
3308 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3309 DAG.getValueType(VT));
3310 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3311 DAG.getValueType(VT));
3313 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3315 // Perform FP_ROUND: this is probably overly pessimistic.
3316 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3317 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3318 DAG.getValueType(VT));
3322 case ISD::FCOPYSIGN:
3323 // These operators require that their input be fp extended.
3324 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3326 Tmp1 = LegalizeOp(Node->getOperand(0));
3329 Tmp1 = PromoteOp(Node->getOperand(0));
3332 assert(0 && "not implemented");
3334 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3336 Tmp2 = LegalizeOp(Node->getOperand(1));
3339 Tmp2 = PromoteOp(Node->getOperand(1));
3342 assert(0 && "not implemented");
3344 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3346 // Perform FP_ROUND: this is probably overly pessimistic.
3347 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3348 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3349 DAG.getValueType(VT));
3354 // These operators require that their input be zero extended.
3355 Tmp1 = PromoteOp(Node->getOperand(0));
3356 Tmp2 = PromoteOp(Node->getOperand(1));
3357 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3358 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3359 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3360 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3364 Tmp1 = PromoteOp(Node->getOperand(0));
3365 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3368 // The input value must be properly sign extended.
3369 Tmp1 = PromoteOp(Node->getOperand(0));
3370 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3371 DAG.getValueType(VT));
3372 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3375 // The input value must be properly zero extended.
3376 Tmp1 = PromoteOp(Node->getOperand(0));
3377 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3378 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3382 Tmp1 = Node->getOperand(0); // Get the chain.
3383 Tmp2 = Node->getOperand(1); // Get the pointer.
3384 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3385 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3386 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3388 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3389 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3390 SV->getValue(), SV->getOffset());
3391 // Increment the pointer, VAList, to the next vaarg
3392 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3393 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3394 TLI.getPointerTy()));
3395 // Store the incremented VAList to the legalized pointer
3396 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3398 // Load the actual argument out of the pointer VAList
3399 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
3401 // Remember that we legalized the chain.
3402 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3406 LoadSDNode *LD = cast<LoadSDNode>(Node);
3407 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
3408 ? ISD::EXTLOAD : LD->getExtensionType();
3409 Result = DAG.getExtLoad(ExtType, NVT,
3410 LD->getChain(), LD->getBasePtr(),
3411 LD->getSrcValue(), LD->getSrcValueOffset(),
3413 // Remember that we legalized the chain.
3414 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3418 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3419 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3420 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3422 case ISD::SELECT_CC:
3423 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3424 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3425 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3426 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3429 Tmp1 = Node->getOperand(0);
3430 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3431 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3432 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3433 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
3434 TLI.getShiftAmountTy()));
3439 // Zero extend the argument
3440 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3441 // Perform the larger operation, then subtract if needed.
3442 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3443 switch(Node->getOpcode()) {
3448 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3449 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3450 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
3451 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3452 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
3455 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3456 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3457 DAG.getConstant(getSizeInBits(NVT) -
3458 getSizeInBits(VT), NVT));
3462 case ISD::VEXTRACT_VECTOR_ELT:
3463 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
3465 case ISD::EXTRACT_VECTOR_ELT:
3466 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3470 assert(Result.Val && "Didn't set a result!");
3472 // Make sure the result is itself legal.
3473 Result = LegalizeOp(Result);
3475 // Remember that we promoted this!
3476 AddPromotedOperand(Op, Result);
3480 /// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
3481 /// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
3482 /// on the vector type. The return type of this matches the element type of the
3483 /// vector, which may not be legal for the target.
3484 SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
3485 // We know that operand #0 is the Vec vector. If the index is a constant
3486 // or if the invec is a supported hardware type, we can use it. Otherwise,
3487 // lower to a store then an indexed load.
3488 SDOperand Vec = Op.getOperand(0);
3489 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3491 SDNode *InVal = Vec.Val;
3492 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
3493 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
3495 // Figure out if there is a Packed type corresponding to this Vector
3496 // type. If so, convert to the packed type.
3497 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3498 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
3499 // Turn this into a packed extract_vector_elt operation.
3500 Vec = PackVectorOp(Vec, TVT);
3501 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
3502 } else if (NumElems == 1) {
3503 // This must be an access of the only element. Return it.
3504 return PackVectorOp(Vec, EVT);
3505 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
3507 SplitVectorOp(Vec, Lo, Hi);
3508 if (CIdx->getValue() < NumElems/2) {
3512 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3515 // It's now an extract from the appropriate high or low part. Recurse.
3516 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3517 return LowerVEXTRACT_VECTOR_ELT(Op);
3519 // Variable index case for extract element.
3520 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
3521 assert(0 && "unimp!");
3526 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3528 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3529 SDOperand Vector = Op.getOperand(0);
3530 SDOperand Idx = Op.getOperand(1);
3532 // If the target doesn't support this, store the value to a temporary
3533 // stack slot, then LOAD the scalar element back out.
3534 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
3535 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vector, StackPtr, NULL, 0);
3537 // Add the offset to the index.
3538 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3539 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3540 DAG.getConstant(EltSize, Idx.getValueType()));
3541 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3543 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
3547 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3548 /// with condition CC on the current target. This usually involves legalizing
3549 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3550 /// there may be no choice but to create a new SetCC node to represent the
3551 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3552 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3553 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3556 SDOperand Tmp1, Tmp2, Result;
3558 switch (getTypeAction(LHS.getValueType())) {
3560 Tmp1 = LegalizeOp(LHS); // LHS
3561 Tmp2 = LegalizeOp(RHS); // RHS
3564 Tmp1 = PromoteOp(LHS); // LHS
3565 Tmp2 = PromoteOp(RHS); // RHS
3567 // If this is an FP compare, the operands have already been extended.
3568 if (MVT::isInteger(LHS.getValueType())) {
3569 MVT::ValueType VT = LHS.getValueType();
3570 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3572 // Otherwise, we have to insert explicit sign or zero extends. Note
3573 // that we could insert sign extends for ALL conditions, but zero extend
3574 // is cheaper on many machines (an AND instead of two shifts), so prefer
3576 switch (cast<CondCodeSDNode>(CC)->get()) {
3577 default: assert(0 && "Unknown integer comparison!");
3584 // ALL of these operations will work if we either sign or zero extend
3585 // the operands (including the unsigned comparisons!). Zero extend is
3586 // usually a simpler/cheaper operation, so prefer it.
3587 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3588 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3594 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3595 DAG.getValueType(VT));
3596 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3597 DAG.getValueType(VT));
3603 MVT::ValueType VT = LHS.getValueType();
3604 if (VT == MVT::f32 || VT == MVT::f64) {
3605 // Expand into one or more soft-fp libcall(s).
3606 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
3607 ISD::CondCode CC1, CC2 = ISD::SETCC_INVALID;
3608 switch (cast<CondCodeSDNode>(CC)->get()) {
3611 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
3616 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
3621 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
3626 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3631 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
3636 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
3641 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
3642 CC1 = cast<CondCodeSDNode>(CC)->get() == ISD::SETO
3643 ? ISD::SETEQ : ISD::SETNE;
3646 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
3648 switch (cast<CondCodeSDNode>(CC)->get()) {
3650 // SETONE = SETOLT | SETOGT
3651 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3655 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
3659 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
3663 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3667 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
3671 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
3674 default: assert(0 && "Unsupported FP setcc!");
3679 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
3680 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
3681 false /*sign irrelevant*/, Dummy);
3682 Tmp2 = DAG.getConstant(0, MVT::i32);
3683 CC = DAG.getCondCode(CC1);
3684 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
3685 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
3686 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
3687 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
3688 false /*sign irrelevant*/, Dummy);
3689 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
3690 DAG.getCondCode(CC2));
3691 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3699 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3700 ExpandOp(LHS, LHSLo, LHSHi);
3701 ExpandOp(RHS, RHSLo, RHSHi);
3702 switch (cast<CondCodeSDNode>(CC)->get()) {
3706 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3707 if (RHSCST->isAllOnesValue()) {
3708 // Comparison to -1.
3709 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3714 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3715 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3716 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3717 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3720 // If this is a comparison of the sign bit, just look at the top part.
3722 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3723 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3724 CST->getValue() == 0) || // X < 0
3725 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3726 CST->isAllOnesValue())) { // X > -1
3732 // FIXME: This generated code sucks.
3733 ISD::CondCode LowCC;
3734 switch (cast<CondCodeSDNode>(CC)->get()) {
3735 default: assert(0 && "Unknown integer setcc!");
3737 case ISD::SETULT: LowCC = ISD::SETULT; break;
3739 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3741 case ISD::SETULE: LowCC = ISD::SETULE; break;
3743 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3746 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3747 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3748 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3750 // NOTE: on targets without efficient SELECT of bools, we can always use
3751 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3752 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3753 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3754 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3755 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3756 Result, Tmp1, Tmp2));
3766 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3767 /// The resultant code need not be legal. Note that SrcOp is the input operand
3768 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3769 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3771 // Create the stack frame object.
3772 SDOperand FIPtr = CreateStackTemporary(DestVT);
3774 // Emit a store to the stack slot.
3775 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
3776 // Result is a load from the stack slot.
3777 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
3780 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3781 // Create a vector sized/aligned stack slot, store the value to element #0,
3782 // then load the whole vector back out.
3783 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3784 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
3786 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
3790 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3791 /// support the operation, but do support the resultant packed vector type.
3792 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3794 // If the only non-undef value is the low element, turn this into a
3795 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3796 unsigned NumElems = Node->getNumOperands();
3797 bool isOnlyLowElement = true;
3798 SDOperand SplatValue = Node->getOperand(0);
3799 std::map<SDOperand, std::vector<unsigned> > Values;
3800 Values[SplatValue].push_back(0);
3801 bool isConstant = true;
3802 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3803 SplatValue.getOpcode() != ISD::UNDEF)
3806 for (unsigned i = 1; i < NumElems; ++i) {
3807 SDOperand V = Node->getOperand(i);
3808 Values[V].push_back(i);
3809 if (V.getOpcode() != ISD::UNDEF)
3810 isOnlyLowElement = false;
3811 if (SplatValue != V)
3812 SplatValue = SDOperand(0,0);
3814 // If this isn't a constant element or an undef, we can't use a constant
3816 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3817 V.getOpcode() != ISD::UNDEF)
3821 if (isOnlyLowElement) {
3822 // If the low element is an undef too, then this whole things is an undef.
3823 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3824 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3825 // Otherwise, turn this into a scalar_to_vector node.
3826 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3827 Node->getOperand(0));
3830 // If all elements are constants, create a load from the constant pool.
3832 MVT::ValueType VT = Node->getValueType(0);
3834 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3835 std::vector<Constant*> CV;
3836 for (unsigned i = 0, e = NumElems; i != e; ++i) {
3837 if (ConstantFPSDNode *V =
3838 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3839 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3840 } else if (ConstantSDNode *V =
3841 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3842 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
3844 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3845 CV.push_back(UndefValue::get(OpNTy));
3848 Constant *CP = ConstantPacked::get(CV);
3849 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3850 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
3853 if (SplatValue.Val) { // Splat of one value?
3854 // Build the shuffle constant vector: <0, 0, 0, 0>
3855 MVT::ValueType MaskVT =
3856 MVT::getIntVectorWithNumElements(NumElems);
3857 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
3858 std::vector<SDOperand> ZeroVec(NumElems, Zero);
3859 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3860 &ZeroVec[0], ZeroVec.size());
3862 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3863 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
3864 // Get the splatted value into the low element of a vector register.
3865 SDOperand LowValVec =
3866 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3868 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3869 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3870 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3875 // If there are only two unique elements, we may be able to turn this into a
3877 if (Values.size() == 2) {
3878 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
3879 MVT::ValueType MaskVT =
3880 MVT::getIntVectorWithNumElements(NumElems);
3881 std::vector<SDOperand> MaskVec(NumElems);
3883 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3884 E = Values.end(); I != E; ++I) {
3885 for (std::vector<unsigned>::iterator II = I->second.begin(),
3886 EE = I->second.end(); II != EE; ++II)
3887 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
3890 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3891 &MaskVec[0], MaskVec.size());
3893 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3894 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
3895 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
3896 SmallVector<SDOperand, 8> Ops;
3897 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3898 E = Values.end(); I != E; ++I) {
3899 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3903 Ops.push_back(ShuffleMask);
3905 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
3906 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
3907 &Ops[0], Ops.size());
3911 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
3912 // aligned object on the stack, store each element into it, then load
3913 // the result as a vector.
3914 MVT::ValueType VT = Node->getValueType(0);
3915 // Create the stack frame object.
3916 SDOperand FIPtr = CreateStackTemporary(VT);
3918 // Emit a store of each element to the stack slot.
3919 SmallVector<SDOperand, 8> Stores;
3920 unsigned TypeByteSize =
3921 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
3922 // Store (in the right endianness) the elements to memory.
3923 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3924 // Ignore undef elements.
3925 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3927 unsigned Offset = TypeByteSize*i;
3929 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
3930 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
3932 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
3936 SDOperand StoreChain;
3937 if (!Stores.empty()) // Not all undef elements?
3938 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3939 &Stores[0], Stores.size());
3941 StoreChain = DAG.getEntryNode();
3943 // Result is a load from the stack slot.
3944 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
3947 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
3948 /// specified value type.
3949 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
3950 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3951 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
3952 const Type *Ty = MVT::getTypeForValueType(VT);
3953 unsigned StackAlign = (unsigned)TLI.getTargetData()->getTypeAlignmentPref(Ty);
3954 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign);
3955 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
3958 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
3959 SDOperand Op, SDOperand Amt,
3960 SDOperand &Lo, SDOperand &Hi) {
3961 // Expand the subcomponents.
3962 SDOperand LHSL, LHSH;
3963 ExpandOp(Op, LHSL, LHSH);
3965 SDOperand Ops[] = { LHSL, LHSH, Amt };
3966 MVT::ValueType VT = LHSL.getValueType();
3967 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
3968 Hi = Lo.getValue(1);
3972 /// ExpandShift - Try to find a clever way to expand this shift operation out to
3973 /// smaller elements. If we can't find a way that is more efficient than a
3974 /// libcall on this target, return false. Otherwise, return true with the
3975 /// low-parts expanded into Lo and Hi.
3976 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3977 SDOperand &Lo, SDOperand &Hi) {
3978 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3979 "This is not a shift!");
3981 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3982 SDOperand ShAmt = LegalizeOp(Amt);
3983 MVT::ValueType ShTy = ShAmt.getValueType();
3984 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3985 unsigned NVTBits = MVT::getSizeInBits(NVT);
3987 // Handle the case when Amt is an immediate. Other cases are currently broken
3988 // and are disabled.
3989 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3990 unsigned Cst = CN->getValue();
3991 // Expand the incoming operand to be shifted, so that we have its parts
3993 ExpandOp(Op, InL, InH);
3997 Lo = DAG.getConstant(0, NVT);
3998 Hi = DAG.getConstant(0, NVT);
3999 } else if (Cst > NVTBits) {
4000 Lo = DAG.getConstant(0, NVT);
4001 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4002 } else if (Cst == NVTBits) {
4003 Lo = DAG.getConstant(0, NVT);
4006 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4007 Hi = DAG.getNode(ISD::OR, NVT,
4008 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4009 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4014 Lo = DAG.getConstant(0, NVT);
4015 Hi = DAG.getConstant(0, NVT);
4016 } else if (Cst > NVTBits) {
4017 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
4018 Hi = DAG.getConstant(0, NVT);
4019 } else if (Cst == NVTBits) {
4021 Hi = DAG.getConstant(0, NVT);
4023 Lo = DAG.getNode(ISD::OR, NVT,
4024 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4025 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4026 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
4031 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
4032 DAG.getConstant(NVTBits-1, ShTy));
4033 } else if (Cst > NVTBits) {
4034 Lo = DAG.getNode(ISD::SRA, NVT, InH,
4035 DAG.getConstant(Cst-NVTBits, ShTy));
4036 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4037 DAG.getConstant(NVTBits-1, ShTy));
4038 } else if (Cst == NVTBits) {
4040 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4041 DAG.getConstant(NVTBits-1, ShTy));
4043 Lo = DAG.getNode(ISD::OR, NVT,
4044 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4045 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4046 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
4052 // Okay, the shift amount isn't constant. However, if we can tell that it is
4053 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
4054 uint64_t Mask = NVTBits, KnownZero, KnownOne;
4055 TLI.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
4057 // If we know that the high bit of the shift amount is one, then we can do
4058 // this as a couple of simple shifts.
4059 if (KnownOne & Mask) {
4060 // Mask out the high bit, which we know is set.
4061 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
4062 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4064 // Expand the incoming operand to be shifted, so that we have its parts
4066 ExpandOp(Op, InL, InH);
4069 Lo = DAG.getConstant(0, NVT); // Low part is zero.
4070 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
4073 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
4074 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
4077 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
4078 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4079 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
4084 // If we know that the high bit of the shift amount is zero, then we can do
4085 // this as a couple of simple shifts.
4086 if (KnownZero & Mask) {
4088 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
4089 DAG.getConstant(NVTBits, Amt.getValueType()),
4092 // Expand the incoming operand to be shifted, so that we have its parts
4094 ExpandOp(Op, InL, InH);
4097 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
4098 Hi = DAG.getNode(ISD::OR, NVT,
4099 DAG.getNode(ISD::SHL, NVT, InH, Amt),
4100 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
4103 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
4104 Lo = DAG.getNode(ISD::OR, NVT,
4105 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4106 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4109 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
4110 Lo = DAG.getNode(ISD::OR, NVT,
4111 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4112 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4121 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
4122 // does not fit into a register, return the lo part and set the hi part to the
4123 // by-reg argument. If it does fit into a single register, return the result
4124 // and leave the Hi part unset.
4125 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
4126 bool isSigned, SDOperand &Hi) {
4127 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
4128 // The input chain to this libcall is the entry node of the function.
4129 // Legalizing the call will automatically add the previous call to the
4131 SDOperand InChain = DAG.getEntryNode();
4133 TargetLowering::ArgListTy Args;
4134 TargetLowering::ArgListEntry Entry;
4135 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4136 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
4137 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
4138 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
4139 Entry.isSigned = isSigned; Entry.isInReg = false;
4140 Args.push_back(Entry);
4142 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
4144 // Splice the libcall in wherever FindInputOutputChains tells us to.
4145 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
4146 std::pair<SDOperand,SDOperand> CallInfo =
4147 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
4150 // Legalize the call sequence, starting with the chain. This will advance
4151 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
4152 // was added by LowerCallTo (guaranteeing proper serialization of calls).
4153 LegalizeOp(CallInfo.second);
4155 switch (getTypeAction(CallInfo.first.getValueType())) {
4156 default: assert(0 && "Unknown thing");
4158 Result = CallInfo.first;
4161 ExpandOp(CallInfo.first, Result, Hi);
4168 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
4169 /// destination type is legal.
4170 SDOperand SelectionDAGLegalize::
4171 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
4172 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
4173 assert(getTypeAction(Source.getValueType()) == Expand &&
4174 "This is not an expansion!");
4175 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
4178 assert(Source.getValueType() == MVT::i64 &&
4179 "This only works for 64-bit -> FP");
4180 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
4181 // incoming integer is set. To handle this, we dynamically test to see if
4182 // it is set, and, if so, add a fudge factor.
4184 ExpandOp(Source, Lo, Hi);
4186 // If this is unsigned, and not supported, first perform the conversion to
4187 // signed, then adjust the result if the sign bit is set.
4188 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
4189 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
4191 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
4192 DAG.getConstant(0, Hi.getValueType()),
4194 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4195 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4196 SignSet, Four, Zero);
4197 uint64_t FF = 0x5f800000ULL;
4198 if (TLI.isLittleEndian()) FF <<= 32;
4199 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4201 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4202 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4203 SDOperand FudgeInReg;
4204 if (DestTy == MVT::f32)
4205 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4207 assert(DestTy == MVT::f64 && "Unexpected conversion");
4208 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
4209 CPIdx, NULL, 0, MVT::f32);
4211 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
4214 // Check to see if the target has a custom way to lower this. If so, use it.
4215 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
4216 default: assert(0 && "This action not implemented for this operation!");
4217 case TargetLowering::Legal:
4218 case TargetLowering::Expand:
4219 break; // This case is handled below.
4220 case TargetLowering::Custom: {
4221 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
4224 return LegalizeOp(NV);
4225 break; // The target decided this was legal after all
4229 // Expand the source, then glue it back together for the call. We must expand
4230 // the source in case it is shared (this pass of legalize must traverse it).
4231 SDOperand SrcLo, SrcHi;
4232 ExpandOp(Source, SrcLo, SrcHi);
4233 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
4236 if (DestTy == MVT::f32)
4237 LC = RTLIB::SINTTOFP_I64_F32;
4239 assert(DestTy == MVT::f64 && "Unknown fp value type!");
4240 LC = RTLIB::SINTTOFP_I64_F64;
4243 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
4244 SDOperand UnusedHiPart;
4245 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
4249 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
4250 /// INT_TO_FP operation of the specified operand when the target requests that
4251 /// we expand it. At this point, we know that the result and operand types are
4252 /// legal for the target.
4253 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
4255 MVT::ValueType DestVT) {
4256 if (Op0.getValueType() == MVT::i32) {
4257 // simple 32-bit [signed|unsigned] integer to float/double expansion
4259 // get the stack frame index of a 8 byte buffer, pessimistically aligned
4260 MachineFunction &MF = DAG.getMachineFunction();
4261 const Type *F64Type = MVT::getTypeForValueType(MVT::f64);
4262 unsigned StackAlign =
4263 (unsigned)TLI.getTargetData()->getTypeAlignmentPref(F64Type);
4264 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign);
4265 // get address of 8 byte buffer
4266 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4267 // word offset constant for Hi/Lo address computation
4268 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
4269 // set up Hi and Lo (into buffer) address based on endian
4270 SDOperand Hi = StackSlot;
4271 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4272 if (TLI.isLittleEndian())
4275 // if signed map to unsigned space
4276 SDOperand Op0Mapped;
4278 // constant used to invert sign bit (signed to unsigned mapping)
4279 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4280 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4284 // store the lo of the constructed double - based on integer input
4285 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4286 Op0Mapped, Lo, NULL, 0);
4287 // initial hi portion of constructed double
4288 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4289 // store the hi of the constructed double - biased exponent
4290 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
4291 // load the constructed double
4292 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4293 // FP constant to bias correct the final result
4294 SDOperand Bias = DAG.getConstantFP(isSigned ?
4295 BitsToDouble(0x4330000080000000ULL)
4296 : BitsToDouble(0x4330000000000000ULL),
4298 // subtract the bias
4299 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4302 // handle final rounding
4303 if (DestVT == MVT::f64) {
4307 // if f32 then cast to f32
4308 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
4312 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4313 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4315 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4316 DAG.getConstant(0, Op0.getValueType()),
4318 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4319 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4320 SignSet, Four, Zero);
4322 // If the sign bit of the integer is set, the large number will be treated
4323 // as a negative number. To counteract this, the dynamic code adds an
4324 // offset depending on the data type.
4326 switch (Op0.getValueType()) {
4327 default: assert(0 && "Unsupported integer type!");
4328 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4329 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4330 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4331 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4333 if (TLI.isLittleEndian()) FF <<= 32;
4334 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4336 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4337 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4338 SDOperand FudgeInReg;
4339 if (DestVT == MVT::f32)
4340 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4342 assert(DestVT == MVT::f64 && "Unexpected conversion");
4343 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
4344 DAG.getEntryNode(), CPIdx,
4345 NULL, 0, MVT::f32));
4348 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4351 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4352 /// *INT_TO_FP operation of the specified operand when the target requests that
4353 /// we promote it. At this point, we know that the result and operand types are
4354 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4355 /// operation that takes a larger input.
4356 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4357 MVT::ValueType DestVT,
4359 // First step, figure out the appropriate *INT_TO_FP operation to use.
4360 MVT::ValueType NewInTy = LegalOp.getValueType();
4362 unsigned OpToUse = 0;
4364 // Scan for the appropriate larger type to use.
4366 NewInTy = (MVT::ValueType)(NewInTy+1);
4367 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4369 // If the target supports SINT_TO_FP of this type, use it.
4370 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4372 case TargetLowering::Legal:
4373 if (!TLI.isTypeLegal(NewInTy))
4374 break; // Can't use this datatype.
4376 case TargetLowering::Custom:
4377 OpToUse = ISD::SINT_TO_FP;
4381 if (isSigned) continue;
4383 // If the target supports UINT_TO_FP of this type, use it.
4384 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4386 case TargetLowering::Legal:
4387 if (!TLI.isTypeLegal(NewInTy))
4388 break; // Can't use this datatype.
4390 case TargetLowering::Custom:
4391 OpToUse = ISD::UINT_TO_FP;
4396 // Otherwise, try a larger type.
4399 // Okay, we found the operation and type to use. Zero extend our input to the
4400 // desired type then run the operation on it.
4401 return DAG.getNode(OpToUse, DestVT,
4402 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4406 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4407 /// FP_TO_*INT operation of the specified operand when the target requests that
4408 /// we promote it. At this point, we know that the result and operand types are
4409 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4410 /// operation that returns a larger result.
4411 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4412 MVT::ValueType DestVT,
4414 // First step, figure out the appropriate FP_TO*INT operation to use.
4415 MVT::ValueType NewOutTy = DestVT;
4417 unsigned OpToUse = 0;
4419 // Scan for the appropriate larger type to use.
4421 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4422 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4424 // If the target supports FP_TO_SINT returning this type, use it.
4425 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4427 case TargetLowering::Legal:
4428 if (!TLI.isTypeLegal(NewOutTy))
4429 break; // Can't use this datatype.
4431 case TargetLowering::Custom:
4432 OpToUse = ISD::FP_TO_SINT;
4437 // If the target supports FP_TO_UINT of this type, use it.
4438 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4440 case TargetLowering::Legal:
4441 if (!TLI.isTypeLegal(NewOutTy))
4442 break; // Can't use this datatype.
4444 case TargetLowering::Custom:
4445 OpToUse = ISD::FP_TO_UINT;
4450 // Otherwise, try a larger type.
4453 // Okay, we found the operation and type to use. Truncate the result of the
4454 // extended FP_TO_*INT operation to the desired size.
4455 return DAG.getNode(ISD::TRUNCATE, DestVT,
4456 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4459 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4461 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4462 MVT::ValueType VT = Op.getValueType();
4463 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4464 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4466 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4468 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4469 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4470 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4472 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4473 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4474 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4475 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4476 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4477 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4478 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4479 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4480 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4482 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4483 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4484 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4485 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4486 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4487 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4488 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4489 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4490 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4491 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4492 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4493 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4494 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4495 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4496 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4497 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4498 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4499 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4500 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4501 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4502 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4506 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4508 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4510 default: assert(0 && "Cannot expand this yet!");
4512 static const uint64_t mask[6] = {
4513 0x5555555555555555ULL, 0x3333333333333333ULL,
4514 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4515 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4517 MVT::ValueType VT = Op.getValueType();
4518 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4519 unsigned len = getSizeInBits(VT);
4520 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4521 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4522 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4523 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4524 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4525 DAG.getNode(ISD::AND, VT,
4526 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4531 // for now, we do this:
4532 // x = x | (x >> 1);
4533 // x = x | (x >> 2);
4535 // x = x | (x >>16);
4536 // x = x | (x >>32); // for 64-bit input
4537 // return popcount(~x);
4539 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4540 MVT::ValueType VT = Op.getValueType();
4541 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4542 unsigned len = getSizeInBits(VT);
4543 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4544 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4545 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4547 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4548 return DAG.getNode(ISD::CTPOP, VT, Op);
4551 // for now, we use: { return popcount(~x & (x - 1)); }
4552 // unless the target has ctlz but not ctpop, in which case we use:
4553 // { return 32 - nlz(~x & (x-1)); }
4554 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4555 MVT::ValueType VT = Op.getValueType();
4556 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4557 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4558 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4559 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4560 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4561 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4562 TLI.isOperationLegal(ISD::CTLZ, VT))
4563 return DAG.getNode(ISD::SUB, VT,
4564 DAG.getConstant(getSizeInBits(VT), VT),
4565 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4566 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4571 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4572 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4573 /// LegalizeNodes map is filled in for any results that are not expanded, the
4574 /// ExpandedNodes map is filled in for any results that are expanded, and the
4575 /// Lo/Hi values are returned.
4576 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4577 MVT::ValueType VT = Op.getValueType();
4578 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4579 SDNode *Node = Op.Val;
4580 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4581 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
4582 VT == MVT::Vector) &&
4583 "Cannot expand to FP value or to larger int value!");
4585 // See if we already expanded it.
4586 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4587 = ExpandedNodes.find(Op);
4588 if (I != ExpandedNodes.end()) {
4589 Lo = I->second.first;
4590 Hi = I->second.second;
4594 switch (Node->getOpcode()) {
4595 case ISD::CopyFromReg:
4596 assert(0 && "CopyFromReg must be legal!");
4599 cerr << "NODE: "; Node->dump(); cerr << "\n";
4601 assert(0 && "Do not know how to expand this operator!");
4604 NVT = TLI.getTypeToExpandTo(VT);
4605 Lo = DAG.getNode(ISD::UNDEF, NVT);
4606 Hi = DAG.getNode(ISD::UNDEF, NVT);
4608 case ISD::Constant: {
4609 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4610 Lo = DAG.getConstant(Cst, NVT);
4611 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4614 case ISD::ConstantFP: {
4615 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
4616 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
4617 if (getTypeAction(Lo.getValueType()) == Expand)
4618 ExpandOp(Lo, Lo, Hi);
4621 case ISD::BUILD_PAIR:
4622 // Return the operands.
4623 Lo = Node->getOperand(0);
4624 Hi = Node->getOperand(1);
4627 case ISD::SIGN_EXTEND_INREG:
4628 ExpandOp(Node->getOperand(0), Lo, Hi);
4629 // sext_inreg the low part if needed.
4630 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4632 // The high part gets the sign extension from the lo-part. This handles
4633 // things like sextinreg V:i64 from i8.
4634 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4635 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4636 TLI.getShiftAmountTy()));
4640 ExpandOp(Node->getOperand(0), Lo, Hi);
4641 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4642 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4648 ExpandOp(Node->getOperand(0), Lo, Hi);
4649 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4650 DAG.getNode(ISD::CTPOP, NVT, Lo),
4651 DAG.getNode(ISD::CTPOP, NVT, Hi));
4652 Hi = DAG.getConstant(0, NVT);
4656 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4657 ExpandOp(Node->getOperand(0), Lo, Hi);
4658 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4659 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4660 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4662 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4663 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4665 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4666 Hi = DAG.getConstant(0, NVT);
4671 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4672 ExpandOp(Node->getOperand(0), Lo, Hi);
4673 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4674 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4675 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4677 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4678 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4680 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4681 Hi = DAG.getConstant(0, NVT);
4686 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4687 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4688 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4689 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4691 // Remember that we legalized the chain.
4692 Hi = LegalizeOp(Hi);
4693 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4694 if (!TLI.isLittleEndian())
4700 LoadSDNode *LD = cast<LoadSDNode>(Node);
4701 SDOperand Ch = LD->getChain(); // Legalize the chain.
4702 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
4703 ISD::LoadExtType ExtType = LD->getExtensionType();
4705 if (ExtType == ISD::NON_EXTLOAD) {
4706 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset());
4707 if (VT == MVT::f32 || VT == MVT::f64) {
4708 // f32->i32 or f64->i64 one to one expansion.
4709 // Remember that we legalized the chain.
4710 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4711 // Recursively expand the new load.
4712 if (getTypeAction(NVT) == Expand)
4713 ExpandOp(Lo, Lo, Hi);
4717 // Increment the pointer to the other half.
4718 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4719 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4720 getIntPtrConstant(IncrementSize));
4721 // FIXME: This creates a bogus srcvalue!
4722 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset());
4724 // Build a factor node to remember that this load is independent of the
4726 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4729 // Remember that we legalized the chain.
4730 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4731 if (!TLI.isLittleEndian())
4734 MVT::ValueType EVT = LD->getLoadedVT();
4736 if (VT == MVT::f64 && EVT == MVT::f32) {
4737 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
4738 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
4739 LD->getSrcValueOffset());
4740 // Remember that we legalized the chain.
4741 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
4742 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
4747 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
4748 LD->getSrcValueOffset());
4750 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
4751 LD->getSrcValueOffset(), EVT);
4753 // Remember that we legalized the chain.
4754 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4756 if (ExtType == ISD::SEXTLOAD) {
4757 // The high part is obtained by SRA'ing all but one of the bits of the
4759 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4760 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4761 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4762 } else if (ExtType == ISD::ZEXTLOAD) {
4763 // The high part is just a zero.
4764 Hi = DAG.getConstant(0, NVT);
4765 } else /* if (ExtType == ISD::EXTLOAD) */ {
4766 // The high part is undefined.
4767 Hi = DAG.getNode(ISD::UNDEF, NVT);
4774 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
4775 SDOperand LL, LH, RL, RH;
4776 ExpandOp(Node->getOperand(0), LL, LH);
4777 ExpandOp(Node->getOperand(1), RL, RH);
4778 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4779 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4783 SDOperand LL, LH, RL, RH;
4784 ExpandOp(Node->getOperand(1), LL, LH);
4785 ExpandOp(Node->getOperand(2), RL, RH);
4786 if (getTypeAction(NVT) == Expand)
4787 NVT = TLI.getTypeToExpandTo(NVT);
4788 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4790 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4793 case ISD::SELECT_CC: {
4794 SDOperand TL, TH, FL, FH;
4795 ExpandOp(Node->getOperand(2), TL, TH);
4796 ExpandOp(Node->getOperand(3), FL, FH);
4797 if (getTypeAction(NVT) == Expand)
4798 NVT = TLI.getTypeToExpandTo(NVT);
4799 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4800 Node->getOperand(1), TL, FL, Node->getOperand(4));
4802 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4803 Node->getOperand(1), TH, FH, Node->getOperand(4));
4806 case ISD::ANY_EXTEND:
4807 // The low part is any extension of the input (which degenerates to a copy).
4808 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4809 // The high part is undefined.
4810 Hi = DAG.getNode(ISD::UNDEF, NVT);
4812 case ISD::SIGN_EXTEND: {
4813 // The low part is just a sign extension of the input (which degenerates to
4815 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4817 // The high part is obtained by SRA'ing all but one of the bits of the lo
4819 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4820 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4821 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4824 case ISD::ZERO_EXTEND:
4825 // The low part is just a zero extension of the input (which degenerates to
4827 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4829 // The high part is just a zero.
4830 Hi = DAG.getConstant(0, NVT);
4833 case ISD::BIT_CONVERT: {
4835 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
4836 // If the target wants to, allow it to lower this itself.
4837 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4838 case Expand: assert(0 && "cannot expand FP!");
4839 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
4840 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
4842 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
4845 // f32 / f64 must be expanded to i32 / i64.
4846 if (VT == MVT::f32 || VT == MVT::f64) {
4847 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
4848 if (getTypeAction(NVT) == Expand)
4849 ExpandOp(Lo, Lo, Hi);
4853 // If source operand will be expanded to the same type as VT, i.e.
4854 // i64 <- f64, i32 <- f32, expand the source operand instead.
4855 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
4856 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
4857 ExpandOp(Node->getOperand(0), Lo, Hi);
4861 // Turn this into a load/store pair by default.
4863 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0));
4865 ExpandOp(Tmp, Lo, Hi);
4869 case ISD::READCYCLECOUNTER:
4870 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
4871 TargetLowering::Custom &&
4872 "Must custom expand ReadCycleCounter");
4873 Lo = TLI.LowerOperation(Op, DAG);
4874 assert(Lo.Val && "Node must be custom expanded!");
4875 Hi = Lo.getValue(1);
4876 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
4877 LegalizeOp(Lo.getValue(2)));
4880 // These operators cannot be expanded directly, emit them as calls to
4881 // library functions.
4882 case ISD::FP_TO_SINT: {
4883 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
4885 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4886 case Expand: assert(0 && "cannot expand FP!");
4887 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4888 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4891 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
4893 // Now that the custom expander is done, expand the result, which is still
4896 ExpandOp(Op, Lo, Hi);
4902 if (Node->getOperand(0).getValueType() == MVT::f32)
4903 LC = RTLIB::FPTOSINT_F32_I64;
4905 LC = RTLIB::FPTOSINT_F64_I64;
4906 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
4907 false/*sign irrelevant*/, Hi);
4911 case ISD::FP_TO_UINT: {
4912 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
4914 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4915 case Expand: assert(0 && "cannot expand FP!");
4916 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4917 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4920 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
4922 // Now that the custom expander is done, expand the result.
4924 ExpandOp(Op, Lo, Hi);
4930 if (Node->getOperand(0).getValueType() == MVT::f32)
4931 LC = RTLIB::FPTOUINT_F32_I64;
4933 LC = RTLIB::FPTOUINT_F64_I64;
4934 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
4935 false/*sign irrelevant*/, Hi);
4940 // If the target wants custom lowering, do so.
4941 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4942 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
4943 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
4944 Op = TLI.LowerOperation(Op, DAG);
4946 // Now that the custom expander is done, expand the result, which is
4948 ExpandOp(Op, Lo, Hi);
4953 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
4954 // this X << 1 as X+X.
4955 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
4956 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
4957 TLI.isOperationLegal(ISD::ADDE, NVT)) {
4958 SDOperand LoOps[2], HiOps[3];
4959 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
4960 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
4961 LoOps[1] = LoOps[0];
4962 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
4964 HiOps[1] = HiOps[0];
4965 HiOps[2] = Lo.getValue(1);
4966 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
4971 // If we can emit an efficient shift operation, do so now.
4972 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4975 // If this target supports SHL_PARTS, use it.
4976 TargetLowering::LegalizeAction Action =
4977 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
4978 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4979 Action == TargetLowering::Custom) {
4980 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4984 // Otherwise, emit a libcall.
4985 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
4986 false/*left shift=unsigned*/, Hi);
4991 // If the target wants custom lowering, do so.
4992 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4993 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
4994 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
4995 Op = TLI.LowerOperation(Op, DAG);
4997 // Now that the custom expander is done, expand the result, which is
4999 ExpandOp(Op, Lo, Hi);
5004 // If we can emit an efficient shift operation, do so now.
5005 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
5008 // If this target supports SRA_PARTS, use it.
5009 TargetLowering::LegalizeAction Action =
5010 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
5011 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5012 Action == TargetLowering::Custom) {
5013 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5017 // Otherwise, emit a libcall.
5018 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
5019 true/*ashr is signed*/, Hi);
5024 // If the target wants custom lowering, do so.
5025 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5026 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
5027 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
5028 Op = TLI.LowerOperation(Op, DAG);
5030 // Now that the custom expander is done, expand the result, which is
5032 ExpandOp(Op, Lo, Hi);
5037 // If we can emit an efficient shift operation, do so now.
5038 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5041 // If this target supports SRL_PARTS, use it.
5042 TargetLowering::LegalizeAction Action =
5043 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
5044 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5045 Action == TargetLowering::Custom) {
5046 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5050 // Otherwise, emit a libcall.
5051 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
5052 false/*lshr is unsigned*/, Hi);
5058 // If the target wants to custom expand this, let them.
5059 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
5060 TargetLowering::Custom) {
5061 Op = TLI.LowerOperation(Op, DAG);
5063 ExpandOp(Op, Lo, Hi);
5068 // Expand the subcomponents.
5069 SDOperand LHSL, LHSH, RHSL, RHSH;
5070 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5071 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5072 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5073 SDOperand LoOps[2], HiOps[3];
5078 if (Node->getOpcode() == ISD::ADD) {
5079 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5080 HiOps[2] = Lo.getValue(1);
5081 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5083 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5084 HiOps[2] = Lo.getValue(1);
5085 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5090 // If the target wants to custom expand this, let them.
5091 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
5092 SDOperand New = TLI.LowerOperation(Op, DAG);
5094 ExpandOp(New, Lo, Hi);
5099 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
5100 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
5101 if (HasMULHS || HasMULHU) {
5102 SDOperand LL, LH, RL, RH;
5103 ExpandOp(Node->getOperand(0), LL, LH);
5104 ExpandOp(Node->getOperand(1), RL, RH);
5105 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
5106 // FIXME: Move this to the dag combiner.
5107 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
5108 // extended the sign bit of the low half through the upper half, and if so
5109 // emit a MULHS instead of the alternate sequence that is valid for any
5110 // i64 x i64 multiply.
5112 // is RH an extension of the sign bit of RL?
5113 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
5114 RH.getOperand(1).getOpcode() == ISD::Constant &&
5115 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
5116 // is LH an extension of the sign bit of LL?
5117 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
5118 LH.getOperand(1).getOpcode() == ISD::Constant &&
5119 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
5121 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5123 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
5125 } else if (HasMULHU) {
5127 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5130 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
5131 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
5132 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
5133 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
5134 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
5139 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
5140 false/*sign irrelevant*/, Hi);
5144 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
5147 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
5150 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
5153 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
5157 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5158 ? RTLIB::ADD_F32 : RTLIB::ADD_F64),
5162 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5163 ? RTLIB::SUB_F32 : RTLIB::SUB_F64),
5167 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5168 ? RTLIB::MUL_F32 : RTLIB::MUL_F64),
5172 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5173 ? RTLIB::DIV_F32 : RTLIB::DIV_F64),
5176 case ISD::FP_EXTEND:
5177 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
5180 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
5185 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5186 switch(Node->getOpcode()) {
5188 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
5191 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
5194 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64;
5196 default: assert(0 && "Unreachable!");
5198 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
5202 SDOperand Mask = (VT == MVT::f64)
5203 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
5204 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
5205 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5206 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5207 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
5208 if (getTypeAction(NVT) == Expand)
5209 ExpandOp(Lo, Lo, Hi);
5213 SDOperand Mask = (VT == MVT::f64)
5214 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
5215 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
5216 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5217 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5218 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
5219 if (getTypeAction(NVT) == Expand)
5220 ExpandOp(Lo, Lo, Hi);
5223 case ISD::FCOPYSIGN: {
5224 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
5225 if (getTypeAction(NVT) == Expand)
5226 ExpandOp(Lo, Lo, Hi);
5229 case ISD::SINT_TO_FP:
5230 case ISD::UINT_TO_FP: {
5231 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
5232 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
5234 if (Node->getOperand(0).getValueType() == MVT::i64) {
5236 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
5238 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
5241 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
5243 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
5246 // Promote the operand if needed.
5247 if (getTypeAction(SrcVT) == Promote) {
5248 SDOperand Tmp = PromoteOp(Node->getOperand(0));
5250 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
5251 DAG.getValueType(SrcVT))
5252 : DAG.getZeroExtendInReg(Tmp, SrcVT);
5253 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
5255 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
5260 // Make sure the resultant values have been legalized themselves, unless this
5261 // is a type that requires multi-step expansion.
5262 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
5263 Lo = LegalizeOp(Lo);
5265 // Don't legalize the high part if it is expanded to a single node.
5266 Hi = LegalizeOp(Hi);
5269 // Remember in a map if the values will be reused later.
5271 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
5272 assert(isNew && "Value already expanded?!?");
5275 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
5276 /// two smaller values of MVT::Vector type.
5277 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
5279 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
5280 SDNode *Node = Op.Val;
5281 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
5282 assert(NumElements > 1 && "Cannot split a single element vector!");
5283 unsigned NewNumElts = NumElements/2;
5284 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
5285 SDOperand TypeNode = *(Node->op_end()-1);
5287 // See if we already split it.
5288 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5289 = SplitNodes.find(Op);
5290 if (I != SplitNodes.end()) {
5291 Lo = I->second.first;
5292 Hi = I->second.second;
5296 switch (Node->getOpcode()) {
5301 assert(0 && "Unhandled operation in SplitVectorOp!");
5302 case ISD::VBUILD_VECTOR: {
5303 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5304 Node->op_begin()+NewNumElts);
5305 LoOps.push_back(NewNumEltsNode);
5306 LoOps.push_back(TypeNode);
5307 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size());
5309 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
5311 HiOps.push_back(NewNumEltsNode);
5312 HiOps.push_back(TypeNode);
5313 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size());
5324 SDOperand LL, LH, RL, RH;
5325 SplitVectorOp(Node->getOperand(0), LL, LH);
5326 SplitVectorOp(Node->getOperand(1), RL, RH);
5328 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
5329 NewNumEltsNode, TypeNode);
5330 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
5331 NewNumEltsNode, TypeNode);
5335 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5336 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5337 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
5339 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
5340 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
5341 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5342 getIntPtrConstant(IncrementSize));
5343 // FIXME: This creates a bogus srcvalue!
5344 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
5346 // Build a factor node to remember that this load is independent of the
5348 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5351 // Remember that we legalized the chain.
5352 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5355 case ISD::VBIT_CONVERT: {
5356 // We know the result is a vector. The input may be either a vector or a
5358 if (Op.getOperand(0).getValueType() != MVT::Vector) {
5359 // Lower to a store/load. FIXME: this could be improved probably.
5360 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
5362 SDOperand St = DAG.getStore(DAG.getEntryNode(),
5363 Op.getOperand(0), Ptr, NULL, 0);
5364 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
5365 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0));
5366 SplitVectorOp(St, Lo, Hi);
5368 // If the input is a vector type, we have to either scalarize it, pack it
5369 // or convert it based on whether the input vector type is legal.
5370 SDNode *InVal = Node->getOperand(0).Val;
5372 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
5373 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
5375 // If the input is from a single element vector, scalarize the vector,
5376 // then treat like a scalar.
5377 if (NumElems == 1) {
5378 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT);
5379 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar,
5380 Op.getOperand(1), Op.getOperand(2));
5381 SplitVectorOp(Scalar, Lo, Hi);
5383 // Split the input vector.
5384 SplitVectorOp(Op.getOperand(0), Lo, Hi);
5386 // Convert each of the pieces now.
5387 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo,
5388 NewNumEltsNode, TypeNode);
5389 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi,
5390 NewNumEltsNode, TypeNode);
5397 // Remember in a map if the values will be reused later.
5399 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
5400 assert(isNew && "Value already expanded?!?");
5404 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
5405 /// equivalent operation that returns a scalar (e.g. F32) or packed value
5406 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
5407 /// type for the result.
5408 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
5409 MVT::ValueType NewVT) {
5410 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
5411 SDNode *Node = Op.Val;
5413 // See if we already packed it.
5414 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
5415 if (I != PackedNodes.end()) return I->second;
5418 switch (Node->getOpcode()) {
5421 Node->dump(); cerr << "\n";
5423 assert(0 && "Unknown vector operation in PackVectorOp!");
5432 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
5434 PackVectorOp(Node->getOperand(0), NewVT),
5435 PackVectorOp(Node->getOperand(1), NewVT));
5438 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
5439 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
5441 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
5442 Result = DAG.getLoad(NewVT, Ch, Ptr, SV->getValue(), SV->getOffset());
5444 // Remember that we legalized the chain.
5445 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
5448 case ISD::VBUILD_VECTOR:
5449 if (Node->getOperand(0).getValueType() == NewVT) {
5450 // Returning a scalar?
5451 Result = Node->getOperand(0);
5453 // Returning a BUILD_VECTOR?
5455 // If all elements of the build_vector are undefs, return an undef.
5456 bool AllUndef = true;
5457 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i)
5458 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) {
5463 Result = DAG.getNode(ISD::UNDEF, NewVT);
5465 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(),
5466 Node->getNumOperands()-2);
5470 case ISD::VINSERT_VECTOR_ELT:
5471 if (!MVT::isVector(NewVT)) {
5472 // Returning a scalar? Must be the inserted element.
5473 Result = Node->getOperand(1);
5475 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
5476 PackVectorOp(Node->getOperand(0), NewVT),
5477 Node->getOperand(1), Node->getOperand(2));
5480 case ISD::VVECTOR_SHUFFLE:
5481 if (!MVT::isVector(NewVT)) {
5482 // Returning a scalar? Figure out if it is the LHS or RHS and return it.
5483 SDOperand EltNum = Node->getOperand(2).getOperand(0);
5484 if (cast<ConstantSDNode>(EltNum)->getValue())
5485 Result = PackVectorOp(Node->getOperand(1), NewVT);
5487 Result = PackVectorOp(Node->getOperand(0), NewVT);
5489 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index
5490 // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
5491 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
5492 Node->getOperand(2).Val->op_end()-2);
5493 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
5494 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT,
5495 Node->getOperand(2).Val->op_begin(),
5496 Node->getOperand(2).Val->getNumOperands()-2);
5498 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
5499 PackVectorOp(Node->getOperand(0), NewVT),
5500 PackVectorOp(Node->getOperand(1), NewVT), BV);
5503 case ISD::VBIT_CONVERT:
5504 if (Op.getOperand(0).getValueType() != MVT::Vector)
5505 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
5507 // If the input is a vector type, we have to either scalarize it, pack it
5508 // or convert it based on whether the input vector type is legal.
5509 SDNode *InVal = Node->getOperand(0).Val;
5511 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
5512 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
5514 // Figure out if there is a Packed type corresponding to this Vector
5515 // type. If so, convert to the packed type.
5516 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
5517 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
5518 // Turn this into a bit convert of the packed input.
5519 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5520 PackVectorOp(Node->getOperand(0), TVT));
5522 } else if (NumElems == 1) {
5523 // Turn this into a bit convert of the scalar input.
5524 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5525 PackVectorOp(Node->getOperand(0), EVT));
5529 assert(0 && "Cast from unsupported vector type not implemented yet!");
5534 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
5535 PackVectorOp(Op.getOperand(1), NewVT),
5536 PackVectorOp(Op.getOperand(2), NewVT));
5540 if (TLI.isTypeLegal(NewVT))
5541 Result = LegalizeOp(Result);
5542 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
5543 assert(isNew && "Value already packed?");
5548 // SelectionDAG::Legalize - This is the entry point for the file.
5550 void SelectionDAG::Legalize() {
5551 if (ViewLegalizeDAGs) viewGraph();
5553 /// run - This is the main entry point to this class.
5555 SelectionDAGLegalize(*this).LegalizeDAG();