1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Support/MathExtras.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
27 //===----------------------------------------------------------------------===//
28 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
29 /// hacks on it until the target machine can handle it. This involves
30 /// eliminating value sizes the machine cannot handle (promoting small sizes to
31 /// large sizes or splitting up large values into small values) as well as
32 /// eliminating operations the machine cannot handle.
34 /// This code also does a small amount of optimization and recognition of idioms
35 /// as part of its processing. For example, if a target does not support a
36 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
37 /// will attempt merge setcc and brc instructions into brcc's.
40 class SelectionDAGLegalize {
44 /// LegalizeAction - This enum indicates what action we should take for each
45 /// value type the can occur in the program.
47 Legal, // The target natively supports this value type.
48 Promote, // This should be promoted to the next larger type.
49 Expand, // This integer type should be broken into smaller pieces.
52 /// ValueTypeActions - This is a bitvector that contains two bits for each
53 /// value type, where the two bits correspond to the LegalizeAction enum.
54 /// This can be queried with "getTypeAction(VT)".
55 unsigned long long ValueTypeActions;
57 /// NeedsAnotherIteration - This is set when we expand a large integer
58 /// operation into smaller integer operations, but the smaller operations are
59 /// not set. This occurs only rarely in practice, for targets that don't have
60 /// 32-bit or larger integer registers.
61 bool NeedsAnotherIteration;
63 /// LegalizedNodes - For nodes that are of legal width, and that have more
64 /// than one use, this map indicates what regularized operand to use. This
65 /// allows us to avoid legalizing the same thing more than once.
66 std::map<SDOperand, SDOperand> LegalizedNodes;
68 /// PromotedNodes - For nodes that are below legal width, and that have more
69 /// than one use, this map indicates what promoted value to use. This allows
70 /// us to avoid promoting the same thing more than once.
71 std::map<SDOperand, SDOperand> PromotedNodes;
73 /// ExpandedNodes - For nodes that need to be expanded, and which have more
74 /// than one use, this map indicates which which operands are the expanded
75 /// version of the input. This allows us to avoid expanding the same node
77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
79 void AddLegalizedOperand(SDOperand From, SDOperand To) {
80 LegalizedNodes.insert(std::make_pair(From, To));
81 // If someone requests legalization of the new node, return itself.
83 LegalizedNodes.insert(std::make_pair(To, To));
85 void AddPromotedOperand(SDOperand From, SDOperand To) {
86 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
87 assert(isNew && "Got into the map somehow?");
88 // If someone requests legalization of the new node, return itself.
89 LegalizedNodes.insert(std::make_pair(To, To));
94 SelectionDAGLegalize(SelectionDAG &DAG);
96 /// Run - While there is still lowering to do, perform a pass over the DAG.
97 /// Most regularization can be done in a single pass, but targets that require
98 /// large values to be split into registers multiple times (e.g. i64 -> 4x
99 /// i16) require iteration for these values (the first iteration will demote
100 /// to i32, the second will demote to i16).
103 NeedsAnotherIteration = false;
105 } while (NeedsAnotherIteration);
108 /// getTypeAction - Return how we should legalize values of this type, either
109 /// it is already legal or we need to expand it into multiple registers of
110 /// smaller integer type, or we need to promote it to a larger type.
111 LegalizeAction getTypeAction(MVT::ValueType VT) const {
112 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3);
115 /// isTypeLegal - Return true if this type is legal on this target.
117 bool isTypeLegal(MVT::ValueType VT) const {
118 return getTypeAction(VT) == Legal;
124 SDOperand LegalizeOp(SDOperand O);
125 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
126 SDOperand PromoteOp(SDOperand O);
128 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
130 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
133 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
134 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
136 MVT::ValueType DestVT);
137 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
139 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
142 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
143 SDOperand &Lo, SDOperand &Hi);
144 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
145 SDOperand &Lo, SDOperand &Hi);
146 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
147 SDOperand &Lo, SDOperand &Hi);
149 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain);
151 SDOperand getIntPtrConstant(uint64_t Val) {
152 return DAG.getConstant(Val, TLI.getPointerTy());
157 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
159 default: assert(0 && "Don't know how to scalarize this opcode!");
160 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
161 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
162 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
166 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
167 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
168 ValueTypeActions(TLI.getValueTypeActions()) {
169 assert(MVT::LAST_VALUETYPE <= 32 &&
170 "Too many value types for ValueTypeActions to hold!");
173 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
174 /// INT_TO_FP operation of the specified operand when the target requests that
175 /// we expand it. At this point, we know that the result and operand types are
176 /// legal for the target.
177 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
179 MVT::ValueType DestVT) {
180 if (Op0.getValueType() == MVT::i32) {
181 // simple 32-bit [signed|unsigned] integer to float/double expansion
183 // get the stack frame index of a 8 byte buffer
184 MachineFunction &MF = DAG.getMachineFunction();
185 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
186 // get address of 8 byte buffer
187 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
188 // word offset constant for Hi/Lo address computation
189 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
190 // set up Hi and Lo (into buffer) address based on endian
192 if (TLI.isLittleEndian()) {
193 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
197 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
199 // if signed map to unsigned space
202 // constant used to invert sign bit (signed to unsigned mapping)
203 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
204 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
208 // store the lo of the constructed double - based on integer input
209 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
210 Op0Mapped, Lo, DAG.getSrcValue(NULL));
211 // initial hi portion of constructed double
212 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
213 // store the hi of the constructed double - biased exponent
214 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
215 InitialHi, Hi, DAG.getSrcValue(NULL));
216 // load the constructed double
217 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
218 DAG.getSrcValue(NULL));
219 // FP constant to bias correct the final result
220 SDOperand Bias = DAG.getConstantFP(isSigned ?
221 BitsToDouble(0x4330000080000000ULL)
222 : BitsToDouble(0x4330000000000000ULL),
225 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
228 // handle final rounding
229 if (DestVT == MVT::f64) {
233 // if f32 then cast to f32
234 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
236 return LegalizeOp(Result);
238 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
239 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
241 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
242 DAG.getConstant(0, Op0.getValueType()),
244 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
245 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
246 SignSet, Four, Zero);
248 // If the sign bit of the integer is set, the large number will be treated
249 // as a negative number. To counteract this, the dynamic code adds an
250 // offset depending on the data type.
252 switch (Op0.getValueType()) {
253 default: assert(0 && "Unsupported integer type!");
254 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
255 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
256 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
257 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
259 if (TLI.isLittleEndian()) FF <<= 32;
260 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
262 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
263 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
264 SDOperand FudgeInReg;
265 if (DestVT == MVT::f32)
266 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
267 DAG.getSrcValue(NULL));
269 assert(DestVT == MVT::f64 && "Unexpected conversion");
270 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
271 DAG.getEntryNode(), CPIdx,
272 DAG.getSrcValue(NULL), MVT::f32));
275 return LegalizeOp(DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg));
278 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
279 /// *INT_TO_FP operation of the specified operand when the target requests that
280 /// we promote it. At this point, we know that the result and operand types are
281 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
282 /// operation that takes a larger input.
283 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
284 MVT::ValueType DestVT,
286 // First step, figure out the appropriate *INT_TO_FP operation to use.
287 MVT::ValueType NewInTy = LegalOp.getValueType();
289 unsigned OpToUse = 0;
291 // Scan for the appropriate larger type to use.
293 NewInTy = (MVT::ValueType)(NewInTy+1);
294 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
296 // If the target supports SINT_TO_FP of this type, use it.
297 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
299 case TargetLowering::Legal:
300 if (!TLI.isTypeLegal(NewInTy))
301 break; // Can't use this datatype.
303 case TargetLowering::Custom:
304 OpToUse = ISD::SINT_TO_FP;
308 if (isSigned) continue;
310 // If the target supports UINT_TO_FP of this type, use it.
311 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
313 case TargetLowering::Legal:
314 if (!TLI.isTypeLegal(NewInTy))
315 break; // Can't use this datatype.
317 case TargetLowering::Custom:
318 OpToUse = ISD::UINT_TO_FP;
323 // Otherwise, try a larger type.
326 // Okay, we found the operation and type to use. Zero extend our input to the
327 // desired type then run the operation on it.
328 SDOperand N = DAG.getNode(OpToUse, DestVT,
329 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
331 // Make sure to legalize any nodes we create here.
332 return LegalizeOp(N);
335 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
336 /// FP_TO_*INT operation of the specified operand when the target requests that
337 /// we promote it. At this point, we know that the result and operand types are
338 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
339 /// operation that returns a larger result.
340 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
341 MVT::ValueType DestVT,
343 // First step, figure out the appropriate FP_TO*INT operation to use.
344 MVT::ValueType NewOutTy = DestVT;
346 unsigned OpToUse = 0;
348 // Scan for the appropriate larger type to use.
350 NewOutTy = (MVT::ValueType)(NewOutTy+1);
351 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
353 // If the target supports FP_TO_SINT returning this type, use it.
354 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
356 case TargetLowering::Legal:
357 if (!TLI.isTypeLegal(NewOutTy))
358 break; // Can't use this datatype.
360 case TargetLowering::Custom:
361 OpToUse = ISD::FP_TO_SINT;
366 // If the target supports FP_TO_UINT of this type, use it.
367 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
369 case TargetLowering::Legal:
370 if (!TLI.isTypeLegal(NewOutTy))
371 break; // Can't use this datatype.
373 case TargetLowering::Custom:
374 OpToUse = ISD::FP_TO_UINT;
379 // Otherwise, try a larger type.
382 // Okay, we found the operation and type to use. Truncate the result of the
383 // extended FP_TO_*INT operation to the desired size.
384 SDOperand N = DAG.getNode(ISD::TRUNCATE, DestVT,
385 DAG.getNode(OpToUse, NewOutTy, LegalOp));
386 // Make sure to legalize any nodes we create here in the next pass.
387 return LegalizeOp(N);
390 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
391 /// not been visited yet and if all of its operands have already been visited.
392 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
393 std::map<SDNode*, unsigned> &Visited) {
394 if (++Visited[N] != N->getNumOperands())
395 return; // Haven't visited all operands yet
399 if (N->hasOneUse()) { // Tail recurse in common case.
400 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
404 // Now that we have N in, add anything that uses it if all of their operands
406 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
407 ComputeTopDownOrdering(*UI, Order, Visited);
411 void SelectionDAGLegalize::LegalizeDAG() {
412 // The legalize process is inherently a bottom-up recursive process (users
413 // legalize their uses before themselves). Given infinite stack space, we
414 // could just start legalizing on the root and traverse the whole graph. In
415 // practice however, this causes us to run out of stack space on large basic
416 // blocks. To avoid this problem, compute an ordering of the nodes where each
417 // node is only legalized after all of its operands are legalized.
418 std::map<SDNode*, unsigned> Visited;
419 std::vector<SDNode*> Order;
421 // Compute ordering from all of the leaves in the graphs, those (like the
422 // entry node) that have no operands.
423 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
424 E = DAG.allnodes_end(); I != E; ++I) {
425 if (I->getNumOperands() == 0) {
427 ComputeTopDownOrdering(I, Order, Visited);
431 assert(Order.size() == Visited.size() &&
433 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
434 "Error: DAG is cyclic!");
437 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
438 SDNode *N = Order[i];
439 switch (getTypeAction(N->getValueType(0))) {
440 default: assert(0 && "Bad type action!");
442 LegalizeOp(SDOperand(N, 0));
445 PromoteOp(SDOperand(N, 0));
449 ExpandOp(SDOperand(N, 0), X, Y);
455 // Finally, it's possible the root changed. Get the new root.
456 SDOperand OldRoot = DAG.getRoot();
457 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
458 DAG.setRoot(LegalizedNodes[OldRoot]);
460 ExpandedNodes.clear();
461 LegalizedNodes.clear();
462 PromotedNodes.clear();
464 // Remove dead nodes now.
465 DAG.RemoveDeadNodes(OldRoot.Val);
468 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
469 assert(isTypeLegal(Op.getValueType()) &&
470 "Caller should expand or promote operands that are not legal!");
471 SDNode *Node = Op.Val;
473 // If this operation defines any values that cannot be represented in a
474 // register on this target, make sure to expand or promote them.
475 if (Node->getNumValues() > 1) {
476 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
477 switch (getTypeAction(Node->getValueType(i))) {
478 case Legal: break; // Nothing to do.
481 ExpandOp(Op.getValue(i), T1, T2);
482 assert(LegalizedNodes.count(Op) &&
483 "Expansion didn't add legal operands!");
484 return LegalizedNodes[Op];
487 PromoteOp(Op.getValue(i));
488 assert(LegalizedNodes.count(Op) &&
489 "Expansion didn't add legal operands!");
490 return LegalizedNodes[Op];
494 // Note that LegalizeOp may be reentered even from single-use nodes, which
495 // means that we always must cache transformed nodes.
496 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
497 if (I != LegalizedNodes.end()) return I->second;
499 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
501 SDOperand Result = Op;
503 switch (Node->getOpcode()) {
505 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
506 // If this is a target node, legalize it by legalizing the operands then
507 // passing it through.
508 std::vector<SDOperand> Ops;
509 bool Changed = false;
510 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
511 Ops.push_back(LegalizeOp(Node->getOperand(i)));
512 Changed = Changed || Node->getOperand(i) != Ops.back();
515 if (Node->getNumValues() == 1)
516 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops);
518 std::vector<MVT::ValueType> VTs(Node->value_begin(),
520 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
523 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
524 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
525 return Result.getValue(Op.ResNo);
527 // Otherwise this is an unhandled builtin node. splat.
528 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
529 assert(0 && "Do not know how to legalize this operator!");
531 case ISD::EntryToken:
532 case ISD::FrameIndex:
533 case ISD::TargetFrameIndex:
535 case ISD::TargetConstant:
536 case ISD::TargetConstantPool:
537 case ISD::GlobalAddress:
538 case ISD::TargetGlobalAddress:
539 case ISD::ExternalSymbol:
540 case ISD::ConstantPool: // Nothing to do.
541 case ISD::BasicBlock:
546 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
547 default: assert(0 && "This action is not supported yet!");
548 case TargetLowering::Custom: {
549 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
551 Result = LegalizeOp(Tmp);
554 } // FALLTHROUGH if the target doesn't want to lower this op after all.
555 case TargetLowering::Legal:
556 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!");
560 case ISD::AssertSext:
561 case ISD::AssertZext:
562 Tmp1 = LegalizeOp(Node->getOperand(0));
563 if (Tmp1 != Node->getOperand(0))
564 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
565 Node->getOperand(1));
567 case ISD::MERGE_VALUES:
568 return LegalizeOp(Node->getOperand(Op.ResNo));
569 case ISD::CopyFromReg:
570 Tmp1 = LegalizeOp(Node->getOperand(0));
571 Result = Op.getValue(0);
572 if (Node->getNumValues() == 2) {
573 if (Tmp1 != Node->getOperand(0))
574 Result = DAG.getCopyFromReg(Tmp1,
575 cast<RegisterSDNode>(Node->getOperand(1))->getReg(),
576 Node->getValueType(0));
578 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
579 if (Node->getNumOperands() == 3)
580 Tmp2 = LegalizeOp(Node->getOperand(2));
581 if (Tmp1 != Node->getOperand(0) ||
582 (Node->getNumOperands() == 3 && Tmp2 != Node->getOperand(2)))
583 Result = DAG.getCopyFromReg(Tmp1,
584 cast<RegisterSDNode>(Node->getOperand(1))->getReg(),
585 Node->getValueType(0), Tmp2);
586 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
588 // Since CopyFromReg produces two values, make sure to remember that we
589 // legalized both of them.
590 AddLegalizedOperand(Op.getValue(0), Result);
591 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
592 return Result.getValue(Op.ResNo);
594 MVT::ValueType VT = Op.getValueType();
595 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
596 default: assert(0 && "This action is not supported yet!");
597 case TargetLowering::Expand:
598 case TargetLowering::Promote:
599 if (MVT::isInteger(VT))
600 Result = DAG.getConstant(0, VT);
601 else if (MVT::isFloatingPoint(VT))
602 Result = DAG.getConstantFP(0, VT);
604 assert(0 && "Unknown value type!");
606 case TargetLowering::Legal:
613 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
614 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
616 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
617 case TargetLowering::Promote:
618 default: assert(0 && "This action is not supported yet!");
619 case TargetLowering::Expand: {
620 if (TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other)) {
621 MachineDebugInfo &DebugInfo = DAG.getMachineFunction().getDebugInfo();
622 std::vector<SDOperand> Ops;
623 Ops.push_back(Tmp1); // chain
624 Ops.push_back(Node->getOperand(1)); // line #
625 Ops.push_back(Node->getOperand(2)); // col #
626 const std::string &fname =
627 cast<StringSDNode>(Node->getOperand(3))->getValue();
628 const std::string &dirname =
629 cast<StringSDNode>(Node->getOperand(4))->getValue();
630 unsigned id = DebugInfo.RecordSource(fname, dirname);
631 Ops.push_back(DAG.getConstant(id, MVT::i32)); // source file id
632 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
634 Result = Tmp1; // chain
636 Result = LegalizeOp(Result); // Relegalize new nodes.
639 case TargetLowering::Legal:
640 if (Tmp1 != Node->getOperand(0) ||
641 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
642 std::vector<SDOperand> Ops;
644 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
645 Ops.push_back(Node->getOperand(1)); // line # must be legal.
646 Ops.push_back(Node->getOperand(2)); // col # must be legal.
648 // Otherwise promote them.
649 Ops.push_back(PromoteOp(Node->getOperand(1)));
650 Ops.push_back(PromoteOp(Node->getOperand(2)));
652 Ops.push_back(Node->getOperand(3)); // filename must be legal.
653 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
654 Result = DAG.getNode(ISD::LOCATION, MVT::Other, Ops);
661 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
662 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
663 case TargetLowering::Promote:
664 case TargetLowering::Expand:
665 default: assert(0 && "This action is not supported yet!");
666 case TargetLowering::Legal:
667 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
668 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
669 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
670 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
672 if (Tmp1 != Node->getOperand(0) ||
673 Tmp2 != Node->getOperand(1) ||
674 Tmp3 != Node->getOperand(2) ||
675 Tmp4 != Node->getOperand(3)) {
676 Result = DAG.getNode(ISD::DEBUG_LOC,MVT::Other, Tmp1, Tmp2, Tmp3, Tmp4);
683 // We know we don't need to expand constants here, constants only have one
684 // value and we check that it is fine above.
686 // FIXME: Maybe we should handle things like targets that don't support full
687 // 32-bit immediates?
689 case ISD::ConstantFP: {
690 // Spill FP immediates to the constant pool if the target cannot directly
691 // codegen them. Targets often have some immediate values that can be
692 // efficiently generated into an FP register without a load. We explicitly
693 // leave these constants as ConstantFP nodes for the target to deal with.
695 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
697 // Check to see if this FP immediate is already legal.
698 bool isLegal = false;
699 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
700 E = TLI.legal_fpimm_end(); I != E; ++I)
701 if (CFP->isExactlyValue(*I)) {
707 // Otherwise we need to spill the constant to memory.
710 // If a FP immediate is precise when represented as a float, we put it
711 // into the constant pool as a float, even if it's is statically typed
713 MVT::ValueType VT = CFP->getValueType(0);
714 bool isDouble = VT == MVT::f64;
715 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
716 Type::FloatTy, CFP->getValue());
717 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
718 // Only do this if the target has a native EXTLOAD instruction from
720 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
721 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
727 LegalizeOp(DAG.getConstantPool(LLVMC, TLI.getPointerTy()));
729 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
730 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
732 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
733 DAG.getSrcValue(NULL));
738 case ISD::ConstantVec: {
739 // We assume that vector constants are not legal, and will be immediately
740 // spilled to the constant pool.
742 // FIXME: revisit this when we have some kind of mechanism by which targets
743 // can decided legality of vector constants, of which there may be very
746 // Create a ConstantPacked, and put it in the constant pool.
747 std::vector<Constant*> CV;
748 MVT::ValueType VT = Node->getValueType(0);
749 for (unsigned I = 0, E = Node->getNumOperands(); I < E; ++I) {
750 SDOperand OpN = Node->getOperand(I);
751 const Type* OpNTy = MVT::getTypeForValueType(OpN.getValueType());
752 if (MVT::isFloatingPoint(VT))
753 CV.push_back(ConstantFP::get(OpNTy,
754 cast<ConstantFPSDNode>(OpN)->getValue()));
756 CV.push_back(ConstantUInt::get(OpNTy,
757 cast<ConstantSDNode>(OpN)->getValue()));
759 Constant *CP = ConstantPacked::get(CV);
760 SDOperand CPIdx = LegalizeOp(DAG.getConstantPool(CP, TLI.getPointerTy()));
761 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
764 case ISD::TokenFactor:
765 if (Node->getNumOperands() == 2) {
766 bool Changed = false;
767 SDOperand Op0 = LegalizeOp(Node->getOperand(0));
768 SDOperand Op1 = LegalizeOp(Node->getOperand(1));
769 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1))
770 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
772 std::vector<SDOperand> Ops;
773 bool Changed = false;
774 // Legalize the operands.
775 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
776 SDOperand Op = Node->getOperand(i);
777 Ops.push_back(LegalizeOp(Op));
778 Changed |= Ops[i] != Op;
781 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
785 case ISD::CALLSEQ_START:
786 case ISD::CALLSEQ_END:
787 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
788 // Do not try to legalize the target-specific arguments (#1+)
789 Tmp2 = Node->getOperand(0);
791 Node->setAdjCallChain(Tmp1);
793 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These
794 // nodes are treated specially and are mutated in place. This makes the dag
795 // legalization process more efficient and also makes libcall insertion
798 case ISD::DYNAMIC_STACKALLOC:
799 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
800 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
801 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
802 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
803 Tmp3 != Node->getOperand(2)) {
804 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
805 std::vector<SDOperand> Ops;
806 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
807 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
809 Result = Op.getValue(0);
811 // Since this op produces two values, make sure to remember that we
812 // legalized both of them.
813 AddLegalizedOperand(SDOperand(Node, 0), Result);
814 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
815 return Result.getValue(Op.ResNo);
819 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
820 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
822 bool Changed = false;
823 std::vector<SDOperand> Ops;
824 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
825 Ops.push_back(LegalizeOp(Node->getOperand(i)));
826 Changed |= Ops.back() != Node->getOperand(i);
829 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) {
830 std::vector<MVT::ValueType> RetTyVTs;
831 RetTyVTs.reserve(Node->getNumValues());
832 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
833 RetTyVTs.push_back(Node->getValueType(i));
834 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
835 Node->getOpcode() == ISD::TAILCALL), 0);
837 Result = Result.getValue(0);
839 // Since calls produce multiple values, make sure to remember that we
840 // legalized all of them.
841 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
842 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
843 return Result.getValue(Op.ResNo);
846 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
847 if (Tmp1 != Node->getOperand(0))
848 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1));
852 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
854 switch (getTypeAction(Node->getOperand(1).getValueType())) {
855 case Expand: assert(0 && "It's impossible to expand bools");
857 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
860 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
864 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
865 default: assert(0 && "This action is not supported yet!");
866 case TargetLowering::Expand:
867 // Expand brcond's setcc into its constituent parts and create a BR_CC
869 if (Tmp2.getOpcode() == ISD::SETCC) {
870 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
871 Tmp2.getOperand(0), Tmp2.getOperand(1),
872 Node->getOperand(2));
874 // Make sure the condition is either zero or one. It may have been
875 // promoted from something else.
876 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
878 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
879 DAG.getCondCode(ISD::SETNE), Tmp2,
880 DAG.getConstant(0, Tmp2.getValueType()),
881 Node->getOperand(2));
883 Result = LegalizeOp(Result); // Relegalize new nodes.
885 case TargetLowering::Custom: {
887 TLI.LowerOperation(DAG.getNode(ISD::BRCOND, Node->getValueType(0),
888 Tmp1, Tmp2, Node->getOperand(2)), DAG);
890 Result = LegalizeOp(Tmp);
893 // FALLTHROUGH if the target thinks it is legal.
895 case TargetLowering::Legal:
896 // Basic block destination (Op#2) is always legal.
897 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
898 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
899 Node->getOperand(2));
904 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
905 if (!isTypeLegal(Node->getOperand(2).getValueType())) {
906 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
907 Node->getOperand(2), // LHS
908 Node->getOperand(3), // RHS
909 Node->getOperand(1)));
910 // If we get a SETCC back from legalizing the SETCC node we just
911 // created, then use its LHS, RHS, and CC directly in creating a new
912 // node. Otherwise, select between the true and false value based on
913 // comparing the result of the legalized with zero.
914 if (Tmp2.getOpcode() == ISD::SETCC) {
915 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
916 Tmp2.getOperand(0), Tmp2.getOperand(1),
917 Node->getOperand(4));
919 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
920 DAG.getCondCode(ISD::SETNE),
921 Tmp2, DAG.getConstant(0, Tmp2.getValueType()),
922 Node->getOperand(4));
927 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
928 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
930 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
931 default: assert(0 && "Unexpected action for BR_CC!");
932 case TargetLowering::Custom: {
933 Tmp4 = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1),
934 Tmp2, Tmp3, Node->getOperand(4));
935 Tmp4 = TLI.LowerOperation(Tmp4, DAG);
937 Result = LegalizeOp(Tmp4);
940 } // FALLTHROUGH if the target doesn't want to lower this op after all.
941 case TargetLowering::Legal:
942 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
943 Tmp3 != Node->getOperand(3)) {
944 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1),
945 Tmp2, Tmp3, Node->getOperand(4));
950 case ISD::BRCONDTWOWAY:
951 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
952 switch (getTypeAction(Node->getOperand(1).getValueType())) {
953 case Expand: assert(0 && "It's impossible to expand bools");
955 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
958 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
961 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR
963 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) {
964 case TargetLowering::Promote:
965 default: assert(0 && "This action is not supported yet!");
966 case TargetLowering::Legal:
967 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
968 std::vector<SDOperand> Ops;
971 Ops.push_back(Node->getOperand(2));
972 Ops.push_back(Node->getOperand(3));
973 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops);
976 case TargetLowering::Expand:
977 // If BRTWOWAY_CC is legal for this target, then simply expand this node
978 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a
980 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
981 if (Tmp2.getOpcode() == ISD::SETCC) {
982 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
983 Tmp2.getOperand(0), Tmp2.getOperand(1),
984 Node->getOperand(2), Node->getOperand(3));
986 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
987 DAG.getConstant(0, Tmp2.getValueType()),
988 Node->getOperand(2), Node->getOperand(3));
991 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
992 Node->getOperand(2));
993 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3));
995 Result = LegalizeOp(Result); // Relegalize new nodes.
999 case ISD::BRTWOWAY_CC:
1000 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1001 if (isTypeLegal(Node->getOperand(2).getValueType())) {
1002 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
1003 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
1004 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
1005 Tmp3 != Node->getOperand(3)) {
1006 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3,
1007 Node->getOperand(4), Node->getOperand(5));
1011 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
1012 Node->getOperand(2), // LHS
1013 Node->getOperand(3), // RHS
1014 Node->getOperand(1)));
1015 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR
1017 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) {
1018 default: assert(0 && "This action is not supported yet!");
1019 case TargetLowering::Legal:
1020 // If we get a SETCC back from legalizing the SETCC node we just
1021 // created, then use its LHS, RHS, and CC directly in creating a new
1022 // node. Otherwise, select between the true and false value based on
1023 // comparing the result of the legalized with zero.
1024 if (Tmp2.getOpcode() == ISD::SETCC) {
1025 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
1026 Tmp2.getOperand(0), Tmp2.getOperand(1),
1027 Node->getOperand(4), Node->getOperand(5));
1029 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
1030 DAG.getConstant(0, Tmp2.getValueType()),
1031 Node->getOperand(4), Node->getOperand(5));
1034 case TargetLowering::Expand:
1035 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
1036 Node->getOperand(4));
1037 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5));
1040 Result = LegalizeOp(Result); // Relegalize new nodes.
1044 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1045 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1047 MVT::ValueType VT = Node->getValueType(0);
1048 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1049 default: assert(0 && "This action is not supported yet!");
1050 case TargetLowering::Custom: {
1051 SDOperand Op = DAG.getLoad(Node->getValueType(0),
1052 Tmp1, Tmp2, Node->getOperand(2));
1053 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
1055 Result = LegalizeOp(Tmp);
1056 // Since loads produce two values, make sure to remember that we legalized
1058 AddLegalizedOperand(SDOperand(Node, 0), Result);
1059 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1060 return Result.getValue(Op.ResNo);
1062 // FALLTHROUGH if the target thinks it is legal.
1064 case TargetLowering::Legal:
1065 if (Tmp1 != Node->getOperand(0) ||
1066 Tmp2 != Node->getOperand(1))
1067 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2,
1068 Node->getOperand(2));
1070 Result = SDOperand(Node, 0);
1072 // Since loads produce two values, make sure to remember that we legalized
1074 AddLegalizedOperand(SDOperand(Node, 0), Result);
1075 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1076 return Result.getValue(Op.ResNo);
1078 assert(0 && "Unreachable");
1082 case ISD::ZEXTLOAD: {
1083 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1084 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1086 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
1087 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
1088 default: assert(0 && "This action is not supported yet!");
1089 case TargetLowering::Promote:
1090 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
1091 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
1092 Tmp1, Tmp2, Node->getOperand(2), MVT::i8);
1093 // Since loads produce two values, make sure to remember that we legalized
1095 AddLegalizedOperand(SDOperand(Node, 0), Result);
1096 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1097 return Result.getValue(Op.ResNo);
1099 case TargetLowering::Custom: {
1100 SDOperand Op = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
1101 Tmp1, Tmp2, Node->getOperand(2),
1103 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
1105 Result = LegalizeOp(Tmp);
1106 // Since loads produce two values, make sure to remember that we legalized
1108 AddLegalizedOperand(SDOperand(Node, 0), Result);
1109 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1110 return Result.getValue(Op.ResNo);
1112 // FALLTHROUGH if the target thinks it is legal.
1114 case TargetLowering::Legal:
1115 if (Tmp1 != Node->getOperand(0) ||
1116 Tmp2 != Node->getOperand(1))
1117 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
1118 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1120 Result = SDOperand(Node, 0);
1122 // Since loads produce two values, make sure to remember that we legalized
1124 AddLegalizedOperand(SDOperand(Node, 0), Result);
1125 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1126 return Result.getValue(Op.ResNo);
1127 case TargetLowering::Expand:
1128 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1129 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1130 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
1131 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1132 Result = LegalizeOp(Result); // Relegalize new nodes.
1133 Load = LegalizeOp(Load);
1134 AddLegalizedOperand(SDOperand(Node, 0), Result);
1135 AddLegalizedOperand(SDOperand(Node, 1), Load.getValue(1));
1137 return Load.getValue(1);
1140 assert(Node->getOpcode() != ISD::EXTLOAD &&
1141 "EXTLOAD should always be supported!");
1142 // Turn the unsupported load into an EXTLOAD followed by an explicit
1143 // zero/sign extend inreg.
1144 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1145 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1147 if (Node->getOpcode() == ISD::SEXTLOAD)
1148 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1149 Result, DAG.getValueType(SrcVT));
1151 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1152 Result = LegalizeOp(Result); // Relegalize new nodes.
1153 ValRes = LegalizeOp(ValRes); // Relegalize new nodes.
1154 AddLegalizedOperand(SDOperand(Node, 0), ValRes);
1155 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1157 return Result.getValue(1);
1160 assert(0 && "Unreachable");
1162 case ISD::EXTRACT_ELEMENT: {
1163 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1164 switch (getTypeAction(OpTy)) {
1166 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1169 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1171 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1172 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1173 TLI.getShiftAmountTy()));
1174 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1177 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1178 Node->getOperand(0));
1180 Result = LegalizeOp(Result);
1183 // Get both the low and high parts.
1184 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1185 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1186 Result = Tmp2; // 1 -> Hi
1188 Result = Tmp1; // 0 -> Lo
1194 case ISD::CopyToReg:
1195 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1197 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1198 "Register type must be legal!");
1199 // Legalize the incoming value (must be a legal type).
1200 Tmp2 = LegalizeOp(Node->getOperand(2));
1201 if (Node->getNumValues() == 1) {
1202 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2))
1203 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1,
1204 Node->getOperand(1), Tmp2);
1206 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1207 if (Node->getNumOperands() == 4)
1208 Tmp3 = LegalizeOp(Node->getOperand(3));
1209 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
1210 (Node->getNumOperands() == 4 && Tmp3 != Node->getOperand(3))) {
1211 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1212 Result = DAG.getCopyToReg(Tmp1, Reg, Tmp2, Tmp3);
1215 // Since this produces two values, make sure to remember that we legalized
1217 AddLegalizedOperand(SDOperand(Node, 0), Result);
1218 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1219 return Result.getValue(Op.ResNo);
1224 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1225 switch (Node->getNumOperands()) {
1227 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1229 Tmp2 = LegalizeOp(Node->getOperand(1));
1230 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1231 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
1235 ExpandOp(Node->getOperand(1), Lo, Hi);
1236 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
1240 Tmp2 = PromoteOp(Node->getOperand(1));
1241 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
1246 if (Tmp1 != Node->getOperand(0))
1247 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1);
1249 default: { // ret <values>
1250 std::vector<SDOperand> NewValues;
1251 NewValues.push_back(Tmp1);
1252 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1253 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1255 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1259 ExpandOp(Node->getOperand(i), Lo, Hi);
1260 NewValues.push_back(Lo);
1261 NewValues.push_back(Hi);
1265 assert(0 && "Can't promote multiple return value yet!");
1267 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
1273 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1274 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1276 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1277 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1278 if (CFP->getValueType(0) == MVT::f32) {
1279 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
1280 DAG.getConstant(FloatToBits(CFP->getValue()),
1283 Node->getOperand(3));
1285 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1286 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
1287 DAG.getConstant(DoubleToBits(CFP->getValue()),
1290 Node->getOperand(3));
1295 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1297 SDOperand Val = LegalizeOp(Node->getOperand(1));
1298 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) ||
1299 Tmp2 != Node->getOperand(2))
1300 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2,
1301 Node->getOperand(3));
1303 MVT::ValueType VT = Result.Val->getOperand(1).getValueType();
1304 switch (TLI.getOperationAction(Result.Val->getOpcode(), VT)) {
1305 default: assert(0 && "This action is not supported yet!");
1306 case TargetLowering::Custom: {
1307 SDOperand Tmp = TLI.LowerOperation(Result, DAG);
1309 Result = LegalizeOp(Tmp);
1312 // FALLTHROUGH if the target thinks it is legal.
1314 case TargetLowering::Legal:
1321 // Truncate the value and store the result.
1322 Tmp3 = PromoteOp(Node->getOperand(1));
1323 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1324 Node->getOperand(3),
1325 DAG.getValueType(Node->getOperand(1).getValueType()));
1330 unsigned IncrementSize;
1331 ExpandOp(Node->getOperand(1), Lo, Hi);
1333 if (!TLI.isLittleEndian())
1336 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1337 Node->getOperand(3));
1338 // If this is a vector type, then we have to calculate the increment as
1339 // the product of the element size in bytes, and the number of elements
1340 // in the high half of the vector.
1341 if (MVT::Vector == Hi.getValueType()) {
1342 unsigned NumElems = cast<ConstantSDNode>(Hi.getOperand(2))->getValue();
1343 MVT::ValueType EVT = cast<VTSDNode>(Hi.getOperand(3))->getVT();
1344 IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8;
1346 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1348 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1349 getIntPtrConstant(IncrementSize));
1350 assert(isTypeLegal(Tmp2.getValueType()) &&
1351 "Pointers must be legal!");
1352 //Again, claiming both parts of the store came form the same Instr
1353 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1354 Node->getOperand(3));
1355 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1361 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1362 if (Tmp1 != Node->getOperand(0))
1363 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1));
1365 case ISD::READCYCLECOUNTER:
1366 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1367 if (Tmp1 != Node->getOperand(0)) {
1368 std::vector<MVT::ValueType> rtypes;
1369 std::vector<SDOperand> rvals;
1370 rtypes.push_back(MVT::i64);
1371 rtypes.push_back(MVT::Other);
1372 rvals.push_back(Tmp1);
1373 Result = DAG.getNode(ISD::READCYCLECOUNTER, rtypes, rvals);
1376 // Since rdcc produce two values, make sure to remember that we legalized
1378 AddLegalizedOperand(SDOperand(Node, 0), Result);
1379 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1380 return Result.getValue(Op.ResNo);
1382 case ISD::TRUNCSTORE: {
1383 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1384 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1386 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1389 assert(0 && "Cannot handle illegal TRUNCSTORE yet!");
1391 Tmp2 = LegalizeOp(Node->getOperand(1));
1393 // The only promote case we handle is TRUNCSTORE:i1 X into
1394 // -> TRUNCSTORE:i8 (and X, 1)
1395 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1396 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1397 TargetLowering::Promote) {
1398 // Promote the bool to a mask then store.
1399 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1400 DAG.getConstant(1, Tmp2.getValueType()));
1401 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1402 Node->getOperand(3), DAG.getValueType(MVT::i8));
1404 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1405 Tmp3 != Node->getOperand(2)) {
1406 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1407 Node->getOperand(3), Node->getOperand(4));
1410 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT();
1411 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) {
1412 default: assert(0 && "This action is not supported yet!");
1413 case TargetLowering::Custom: {
1414 SDOperand Tmp = TLI.LowerOperation(Result, DAG);
1416 Result = LegalizeOp(Tmp);
1419 // FALLTHROUGH if the target thinks it is legal.
1421 case TargetLowering::Legal:
1430 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1431 case Expand: assert(0 && "It's impossible to expand bools");
1433 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1436 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1439 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1440 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1442 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1443 default: assert(0 && "This action is not supported yet!");
1444 case TargetLowering::Expand:
1445 if (Tmp1.getOpcode() == ISD::SETCC) {
1446 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1448 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1450 // Make sure the condition is either zero or one. It may have been
1451 // promoted from something else.
1452 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1453 Result = DAG.getSelectCC(Tmp1,
1454 DAG.getConstant(0, Tmp1.getValueType()),
1455 Tmp2, Tmp3, ISD::SETNE);
1457 Result = LegalizeOp(Result); // Relegalize new nodes.
1459 case TargetLowering::Custom: {
1461 TLI.LowerOperation(DAG.getNode(ISD::SELECT, Node->getValueType(0),
1462 Tmp1, Tmp2, Tmp3), DAG);
1464 Result = LegalizeOp(Tmp);
1467 // FALLTHROUGH if the target thinks it is legal.
1469 case TargetLowering::Legal:
1470 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1471 Tmp3 != Node->getOperand(2))
1472 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0),
1475 case TargetLowering::Promote: {
1476 MVT::ValueType NVT =
1477 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1478 unsigned ExtOp, TruncOp;
1479 if (MVT::isInteger(Tmp2.getValueType())) {
1480 ExtOp = ISD::ANY_EXTEND;
1481 TruncOp = ISD::TRUNCATE;
1483 ExtOp = ISD::FP_EXTEND;
1484 TruncOp = ISD::FP_ROUND;
1486 // Promote each of the values to the new type.
1487 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1488 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1489 // Perform the larger operation, then round down.
1490 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1491 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1496 case ISD::SELECT_CC:
1497 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1498 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1500 if (isTypeLegal(Node->getOperand(0).getValueType())) {
1501 // Everything is legal, see if we should expand this op or something.
1502 switch (TLI.getOperationAction(ISD::SELECT_CC,
1503 Node->getOperand(0).getValueType())) {
1504 default: assert(0 && "This action is not supported yet!");
1505 case TargetLowering::Custom: {
1507 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0),
1508 Node->getOperand(0),
1509 Node->getOperand(1), Tmp3, Tmp4,
1510 Node->getOperand(4)), DAG);
1512 Result = LegalizeOp(Tmp);
1515 } // FALLTHROUGH if the target can't lower this operation after all.
1516 case TargetLowering::Legal:
1517 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1518 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1519 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1520 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) {
1521 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1,Tmp2,
1522 Tmp3, Tmp4, Node->getOperand(4));
1528 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
1529 Node->getOperand(0), // LHS
1530 Node->getOperand(1), // RHS
1531 Node->getOperand(4)));
1532 // If we get a SETCC back from legalizing the SETCC node we just
1533 // created, then use its LHS, RHS, and CC directly in creating a new
1534 // node. Otherwise, select between the true and false value based on
1535 // comparing the result of the legalized with zero.
1536 if (Tmp1.getOpcode() == ISD::SETCC) {
1537 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(),
1538 Tmp1.getOperand(0), Tmp1.getOperand(1),
1539 Tmp3, Tmp4, Tmp1.getOperand(2));
1541 Result = DAG.getSelectCC(Tmp1,
1542 DAG.getConstant(0, Tmp1.getValueType()),
1543 Tmp3, Tmp4, ISD::SETNE);
1548 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1550 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1551 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1554 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS
1555 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS
1557 // If this is an FP compare, the operands have already been extended.
1558 if (MVT::isInteger(Node->getOperand(0).getValueType())) {
1559 MVT::ValueType VT = Node->getOperand(0).getValueType();
1560 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
1562 // Otherwise, we have to insert explicit sign or zero extends. Note
1563 // that we could insert sign extends for ALL conditions, but zero extend
1564 // is cheaper on many machines (an AND instead of two shifts), so prefer
1566 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1567 default: assert(0 && "Unknown integer comparison!");
1574 // ALL of these operations will work if we either sign or zero extend
1575 // the operands (including the unsigned comparisons!). Zero extend is
1576 // usually a simpler/cheaper operation, so prefer it.
1577 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
1578 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
1584 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
1585 DAG.getValueType(VT));
1586 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
1587 DAG.getValueType(VT));
1593 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
1594 ExpandOp(Node->getOperand(0), LHSLo, LHSHi);
1595 ExpandOp(Node->getOperand(1), RHSLo, RHSHi);
1596 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1600 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
1601 if (RHSCST->isAllOnesValue()) {
1602 // Comparison to -1.
1603 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1608 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1609 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1610 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
1611 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1614 // If this is a comparison of the sign bit, just look at the top part.
1616 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
1617 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT &&
1618 CST->getValue() == 0) || // X < 0
1619 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT &&
1620 (CST->isAllOnesValue()))) { // X > -1
1626 // FIXME: This generated code sucks.
1627 ISD::CondCode LowCC;
1628 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1629 default: assert(0 && "Unknown integer setcc!");
1631 case ISD::SETULT: LowCC = ISD::SETULT; break;
1633 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1635 case ISD::SETULE: LowCC = ISD::SETULE; break;
1637 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1640 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1641 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1642 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1644 // NOTE: on targets without efficient SELECT of bools, we can always use
1645 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1646 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC);
1647 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi,
1648 Node->getOperand(2));
1649 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ);
1650 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1651 Result, Tmp1, Tmp2));
1652 AddLegalizedOperand(SDOperand(Node, 0), Result);
1657 switch(TLI.getOperationAction(ISD::SETCC,
1658 Node->getOperand(0).getValueType())) {
1660 assert(0 && "Cannot handle this action for SETCC yet!");
1662 case TargetLowering::Promote: {
1663 // First step, figure out the appropriate operation to use.
1664 // Allow SETCC to not be supported for all legal data types
1665 // Mostly this targets FP
1666 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1667 MVT::ValueType OldVT = NewInTy;
1669 // Scan for the appropriate larger type to use.
1671 NewInTy = (MVT::ValueType)(NewInTy+1);
1673 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1674 "Fell off of the edge of the integer world");
1675 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1676 "Fell off of the edge of the floating point world");
1678 // If the target supports SETCC of this type, use it.
1679 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
1682 if (MVT::isInteger(NewInTy))
1683 assert(0 && "Cannot promote Legal Integer SETCC yet");
1685 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1686 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
1689 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1690 Node->getOperand(2));
1693 case TargetLowering::Custom: {
1695 TLI.LowerOperation(DAG.getNode(ISD::SETCC, Node->getValueType(0),
1696 Tmp1, Tmp2, Node->getOperand(2)), DAG);
1698 Result = LegalizeOp(Tmp);
1701 // FALLTHROUGH if the target thinks it is legal.
1703 case TargetLowering::Legal:
1704 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1705 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1706 Node->getOperand(2));
1708 case TargetLowering::Expand:
1709 // Expand a setcc node into a select_cc of the same condition, lhs, and
1710 // rhs that selects between const 1 (true) and const 0 (false).
1711 MVT::ValueType VT = Node->getValueType(0);
1712 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1713 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1714 Node->getOperand(2));
1715 Result = LegalizeOp(Result);
1722 case ISD::MEMMOVE: {
1723 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1724 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1726 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1727 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1728 case Expand: assert(0 && "Cannot expand a byte!");
1730 Tmp3 = LegalizeOp(Node->getOperand(2));
1733 Tmp3 = PromoteOp(Node->getOperand(2));
1737 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1741 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1743 // Length is too big, just take the lo-part of the length.
1745 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
1749 Tmp4 = LegalizeOp(Node->getOperand(3));
1752 Tmp4 = PromoteOp(Node->getOperand(3));
1757 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
1758 case Expand: assert(0 && "Cannot expand this yet!");
1760 Tmp5 = LegalizeOp(Node->getOperand(4));
1763 Tmp5 = PromoteOp(Node->getOperand(4));
1767 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1768 default: assert(0 && "This action not implemented for this operation!");
1769 case TargetLowering::Custom: {
1771 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1,
1772 Tmp2, Tmp3, Tmp4, Tmp5), DAG);
1774 Result = LegalizeOp(Tmp);
1777 // FALLTHROUGH if the target thinks it is legal.
1779 case TargetLowering::Legal:
1780 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1781 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) ||
1782 Tmp5 != Node->getOperand(4)) {
1783 std::vector<SDOperand> Ops;
1784 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
1785 Ops.push_back(Tmp4); Ops.push_back(Tmp5);
1786 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops);
1789 case TargetLowering::Expand: {
1790 // Otherwise, the target does not support this operation. Lower the
1791 // operation to an explicit libcall as appropriate.
1792 MVT::ValueType IntPtr = TLI.getPointerTy();
1793 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType();
1794 std::vector<std::pair<SDOperand, const Type*> > Args;
1796 const char *FnName = 0;
1797 if (Node->getOpcode() == ISD::MEMSET) {
1798 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1799 // Extend the ubyte argument to be an int value for the call.
1800 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
1801 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
1802 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1805 } else if (Node->getOpcode() == ISD::MEMCPY ||
1806 Node->getOpcode() == ISD::MEMMOVE) {
1807 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1808 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
1809 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1810 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
1812 assert(0 && "Unknown op!");
1815 std::pair<SDOperand,SDOperand> CallResult =
1816 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
1817 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
1818 Result = LegalizeOp(CallResult.second);
1826 Tmp1 = LegalizeOp(Node->getOperand(0));
1827 Tmp2 = LegalizeOp(Node->getOperand(1));
1829 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1830 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1831 std::vector<SDOperand> Ops;
1832 Ops.push_back(Tmp1);
1833 Ops.push_back(Tmp2);
1834 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1836 Result = SDOperand(Node, 0);
1837 // Since these produce two values, make sure to remember that we legalized
1839 AddLegalizedOperand(SDOperand(Node, 0), Result);
1840 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1841 return Result.getValue(Op.ResNo);
1842 case ISD::WRITEPORT:
1843 Tmp1 = LegalizeOp(Node->getOperand(0));
1844 Tmp2 = LegalizeOp(Node->getOperand(1));
1845 Tmp3 = LegalizeOp(Node->getOperand(2));
1846 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1847 Tmp3 != Node->getOperand(2))
1848 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1852 Tmp1 = LegalizeOp(Node->getOperand(0));
1853 Tmp2 = LegalizeOp(Node->getOperand(1));
1855 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1856 case TargetLowering::Custom:
1857 default: assert(0 && "This action not implemented for this operation!");
1858 case TargetLowering::Legal:
1859 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1860 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1861 std::vector<SDOperand> Ops;
1862 Ops.push_back(Tmp1);
1863 Ops.push_back(Tmp2);
1864 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1866 Result = SDOperand(Node, 0);
1868 case TargetLowering::Expand:
1869 // Replace this with a load from memory.
1870 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0),
1871 Node->getOperand(1), DAG.getSrcValue(NULL));
1872 Result = LegalizeOp(Result);
1876 // Since these produce two values, make sure to remember that we legalized
1878 AddLegalizedOperand(SDOperand(Node, 0), Result);
1879 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1880 return Result.getValue(Op.ResNo);
1883 Tmp1 = LegalizeOp(Node->getOperand(0));
1884 Tmp2 = LegalizeOp(Node->getOperand(1));
1885 Tmp3 = LegalizeOp(Node->getOperand(2));
1887 switch (TLI.getOperationAction(Node->getOpcode(),
1888 Node->getOperand(1).getValueType())) {
1889 case TargetLowering::Custom:
1890 default: assert(0 && "This action not implemented for this operation!");
1891 case TargetLowering::Legal:
1892 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1893 Tmp3 != Node->getOperand(2))
1894 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1896 case TargetLowering::Expand:
1897 // Replace this with a store to memory.
1898 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0),
1899 Node->getOperand(1), Node->getOperand(2),
1900 DAG.getSrcValue(NULL));
1901 Result = LegalizeOp(Result);
1906 case ISD::ADD_PARTS:
1907 case ISD::SUB_PARTS:
1908 case ISD::SHL_PARTS:
1909 case ISD::SRA_PARTS:
1910 case ISD::SRL_PARTS: {
1911 std::vector<SDOperand> Ops;
1912 bool Changed = false;
1913 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1914 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1915 Changed |= Ops.back() != Node->getOperand(i);
1918 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1919 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
1922 // Since these produce multiple values, make sure to remember that we
1923 // legalized all of them.
1924 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1925 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
1926 return Result.getValue(Op.ResNo);
1947 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1948 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1949 case Expand: assert(0 && "Not possible");
1951 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
1954 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
1957 if (Tmp1 != Node->getOperand(0) ||
1958 Tmp2 != Node->getOperand(1))
1959 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
1962 case ISD::BUILD_PAIR: {
1963 MVT::ValueType PairTy = Node->getValueType(0);
1964 // TODO: handle the case where the Lo and Hi operands are not of legal type
1965 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
1966 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
1967 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
1968 case TargetLowering::Legal:
1969 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1970 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
1972 case TargetLowering::Promote:
1973 case TargetLowering::Custom:
1974 assert(0 && "Cannot promote/custom this yet!");
1975 case TargetLowering::Expand:
1976 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
1977 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
1978 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
1979 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
1980 TLI.getShiftAmountTy()));
1981 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2));
1990 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1991 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1992 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1993 case TargetLowering::Legal:
1994 if (Tmp1 != Node->getOperand(0) ||
1995 Tmp2 != Node->getOperand(1))
1996 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
1999 case TargetLowering::Promote:
2000 case TargetLowering::Custom:
2001 assert(0 && "Cannot promote/custom handle this yet!");
2002 case TargetLowering::Expand:
2003 if (MVT::isInteger(Node->getValueType(0))) {
2004 MVT::ValueType VT = Node->getValueType(0);
2005 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2006 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
2007 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2008 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2010 // Floating point mod -> fmod libcall.
2011 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
2013 Result = ExpandLibCall(FnName, Node, Dummy);
2022 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2023 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2024 case TargetLowering::Legal:
2025 if (Tmp1 != Node->getOperand(0))
2026 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2028 case TargetLowering::Promote: {
2029 MVT::ValueType OVT = Tmp1.getValueType();
2030 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2032 // Zero extend the argument.
2033 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2034 // Perform the larger operation, then subtract if needed.
2035 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2036 switch(Node->getOpcode())
2042 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2043 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2044 DAG.getConstant(getSizeInBits(NVT), NVT),
2046 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2047 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2050 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2051 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2052 DAG.getConstant(getSizeInBits(NVT) -
2053 getSizeInBits(OVT), NVT));
2058 case TargetLowering::Custom:
2059 assert(0 && "Cannot custom handle this yet!");
2060 case TargetLowering::Expand:
2061 switch(Node->getOpcode())
2064 static const uint64_t mask[6] = {
2065 0x5555555555555555ULL, 0x3333333333333333ULL,
2066 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
2067 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
2069 MVT::ValueType VT = Tmp1.getValueType();
2070 MVT::ValueType ShVT = TLI.getShiftAmountTy();
2071 unsigned len = getSizeInBits(VT);
2072 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2073 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
2074 Tmp2 = DAG.getConstant(mask[i], VT);
2075 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2076 Tmp1 = DAG.getNode(ISD::ADD, VT,
2077 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2),
2078 DAG.getNode(ISD::AND, VT,
2079 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3),
2086 /* for now, we do this:
2091 x = x | (x >>32); // for 64-bit input
2092 return popcount(~x);
2094 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */
2095 MVT::ValueType VT = Tmp1.getValueType();
2096 MVT::ValueType ShVT = TLI.getShiftAmountTy();
2097 unsigned len = getSizeInBits(VT);
2098 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2099 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2100 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1,
2101 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3));
2103 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT));
2104 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
2108 // for now, we use: { return popcount(~x & (x - 1)); }
2109 // unless the target has ctlz but not ctpop, in which case we use:
2110 // { return 32 - nlz(~x & (x-1)); }
2111 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2112 MVT::ValueType VT = Tmp1.getValueType();
2113 Tmp2 = DAG.getConstant(~0ULL, VT);
2114 Tmp3 = DAG.getNode(ISD::AND, VT,
2115 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2),
2116 DAG.getNode(ISD::SUB, VT, Tmp1,
2117 DAG.getConstant(1, VT)));
2118 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead
2119 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
2120 TLI.isOperationLegal(ISD::CTLZ, VT)) {
2121 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT,
2122 DAG.getConstant(getSizeInBits(VT), VT),
2123 DAG.getNode(ISD::CTLZ, VT, Tmp3)));
2125 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
2130 assert(0 && "Cannot expand this yet!");
2143 Tmp1 = LegalizeOp(Node->getOperand(0));
2144 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2145 case TargetLowering::Legal:
2146 if (Tmp1 != Node->getOperand(0))
2147 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2149 case TargetLowering::Promote:
2150 case TargetLowering::Custom:
2151 assert(0 && "Cannot promote/custom handle this yet!");
2152 case TargetLowering::Expand:
2153 switch(Node->getOpcode()) {
2155 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2156 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2157 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0),
2162 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2163 MVT::ValueType VT = Node->getValueType(0);
2164 Tmp2 = DAG.getConstantFP(0.0, VT);
2165 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2166 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2167 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2168 Result = LegalizeOp(Result);
2174 MVT::ValueType VT = Node->getValueType(0);
2175 const char *FnName = 0;
2176 switch(Node->getOpcode()) {
2177 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2178 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2179 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2180 default: assert(0 && "Unreachable!");
2183 Result = ExpandLibCall(FnName, Node, Dummy);
2187 assert(0 && "Unreachable!");
2193 case ISD::BIT_CONVERT:
2194 if (!isTypeLegal(Node->getOperand(0).getValueType()))
2195 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2197 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2198 Node->getOperand(0).getValueType())) {
2199 default: assert(0 && "Unknown operation action!");
2200 case TargetLowering::Expand:
2201 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2203 case TargetLowering::Legal:
2204 Tmp1 = LegalizeOp(Node->getOperand(0));
2205 if (Tmp1 != Node->getOperand(0))
2206 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Tmp1);
2211 // Conversion operators. The source and destination have different types.
2212 case ISD::SINT_TO_FP:
2213 case ISD::UINT_TO_FP: {
2214 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2215 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2217 switch (TLI.getOperationAction(Node->getOpcode(),
2218 Node->getOperand(0).getValueType())) {
2219 default: assert(0 && "Unknown operation action!");
2220 case TargetLowering::Expand:
2221 Result = ExpandLegalINT_TO_FP(isSigned,
2222 LegalizeOp(Node->getOperand(0)),
2223 Node->getValueType(0));
2224 AddLegalizedOperand(Op, Result);
2226 case TargetLowering::Promote:
2227 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2228 Node->getValueType(0),
2230 AddLegalizedOperand(Op, Result);
2232 case TargetLowering::Legal:
2234 case TargetLowering::Custom: {
2235 Tmp1 = LegalizeOp(Node->getOperand(0));
2237 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2238 Tmp = TLI.LowerOperation(Tmp, DAG);
2240 Tmp = LegalizeOp(Tmp); // Relegalize input.
2241 AddLegalizedOperand(Op, Tmp);
2244 assert(0 && "Target Must Lower this");
2249 Tmp1 = LegalizeOp(Node->getOperand(0));
2250 if (Tmp1 != Node->getOperand(0))
2251 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2254 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2255 Node->getValueType(0), Node->getOperand(0));
2259 Result = PromoteOp(Node->getOperand(0));
2260 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2261 Result, DAG.getValueType(Node->getOperand(0).getValueType()));
2262 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result);
2264 Result = PromoteOp(Node->getOperand(0));
2265 Result = DAG.getZeroExtendInReg(Result,
2266 Node->getOperand(0).getValueType());
2267 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result);
2274 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2276 Tmp1 = LegalizeOp(Node->getOperand(0));
2277 if (Tmp1 != Node->getOperand(0))
2278 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2281 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2283 // Since the result is legal, we should just be able to truncate the low
2284 // part of the source.
2285 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2288 Result = PromoteOp(Node->getOperand(0));
2289 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2294 case ISD::FP_TO_SINT:
2295 case ISD::FP_TO_UINT:
2296 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2298 Tmp1 = LegalizeOp(Node->getOperand(0));
2300 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2301 default: assert(0 && "Unknown operation action!");
2302 case TargetLowering::Expand:
2303 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2304 SDOperand True, False;
2305 MVT::ValueType VT = Node->getOperand(0).getValueType();
2306 MVT::ValueType NVT = Node->getValueType(0);
2307 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2308 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2309 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2310 Node->getOperand(0), Tmp2, ISD::SETLT);
2311 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2312 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2313 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2315 False = DAG.getNode(ISD::XOR, NVT, False,
2316 DAG.getConstant(1ULL << ShiftAmt, NVT));
2317 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False));
2318 AddLegalizedOperand(SDOperand(Node, 0), Result);
2321 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2324 case TargetLowering::Promote:
2325 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2326 Node->getOpcode() == ISD::FP_TO_SINT);
2327 AddLegalizedOperand(Op, Result);
2329 case TargetLowering::Custom: {
2331 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2332 Tmp = TLI.LowerOperation(Tmp, DAG);
2334 Tmp = LegalizeOp(Tmp);
2335 AddLegalizedOperand(Op, Tmp);
2338 // The target thinks this is legal afterall.
2342 case TargetLowering::Legal:
2346 if (Tmp1 != Node->getOperand(0))
2347 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2350 assert(0 && "Shouldn't need to expand other operators here!");
2352 Result = PromoteOp(Node->getOperand(0));
2353 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2358 case ISD::ANY_EXTEND:
2359 case ISD::ZERO_EXTEND:
2360 case ISD::SIGN_EXTEND:
2361 case ISD::FP_EXTEND:
2363 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2365 Tmp1 = LegalizeOp(Node->getOperand(0));
2366 if (Tmp1 != Node->getOperand(0))
2367 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2370 assert(0 && "Shouldn't need to expand other operators here!");
2373 switch (Node->getOpcode()) {
2374 case ISD::ANY_EXTEND:
2375 Result = PromoteOp(Node->getOperand(0));
2376 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2378 case ISD::ZERO_EXTEND:
2379 Result = PromoteOp(Node->getOperand(0));
2380 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2381 Result = DAG.getZeroExtendInReg(Result,
2382 Node->getOperand(0).getValueType());
2384 case ISD::SIGN_EXTEND:
2385 Result = PromoteOp(Node->getOperand(0));
2386 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2387 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2389 DAG.getValueType(Node->getOperand(0).getValueType()));
2391 case ISD::FP_EXTEND:
2392 Result = PromoteOp(Node->getOperand(0));
2393 if (Result.getValueType() != Op.getValueType())
2394 // Dynamically dead while we have only 2 FP types.
2395 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2398 Result = PromoteOp(Node->getOperand(0));
2399 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2404 case ISD::FP_ROUND_INREG:
2405 case ISD::SIGN_EXTEND_INREG: {
2406 Tmp1 = LegalizeOp(Node->getOperand(0));
2407 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2409 // If this operation is not supported, convert it to a shl/shr or load/store
2411 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2412 default: assert(0 && "This action not supported for this op yet!");
2413 case TargetLowering::Legal:
2414 if (Tmp1 != Node->getOperand(0))
2415 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
2416 DAG.getValueType(ExtraVT));
2418 case TargetLowering::Expand:
2419 // If this is an integer extend and shifts are supported, do that.
2420 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2421 // NOTE: we could fall back on load/store here too for targets without
2422 // SAR. However, it is doubtful that any exist.
2423 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2424 MVT::getSizeInBits(ExtraVT);
2425 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2426 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2427 Node->getOperand(0), ShiftCst);
2428 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2430 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2431 // The only way we can lower this is to turn it into a STORETRUNC,
2432 // EXTLOAD pair, targetting a temporary location (a stack slot).
2434 // NOTE: there is a choice here between constantly creating new stack
2435 // slots and always reusing the same one. We currently always create
2436 // new ones, as reuse may inhibit scheduling.
2437 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2438 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
2439 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
2440 MachineFunction &MF = DAG.getMachineFunction();
2442 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2443 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2444 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2445 Node->getOperand(0), StackSlot,
2446 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2447 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2448 Result, StackSlot, DAG.getSrcValue(NULL),
2451 assert(0 && "Unknown op");
2453 Result = LegalizeOp(Result);
2460 // Note that LegalizeOp may be reentered even from single-use nodes, which
2461 // means that we always must cache transformed nodes.
2462 AddLegalizedOperand(Op, Result);
2466 /// PromoteOp - Given an operation that produces a value in an invalid type,
2467 /// promote it to compute the value into a larger type. The produced value will
2468 /// have the correct bits for the low portion of the register, but no guarantee
2469 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2470 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2471 MVT::ValueType VT = Op.getValueType();
2472 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2473 assert(getTypeAction(VT) == Promote &&
2474 "Caller should expand or legalize operands that are not promotable!");
2475 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2476 "Cannot promote to smaller type!");
2478 SDOperand Tmp1, Tmp2, Tmp3;
2481 SDNode *Node = Op.Val;
2483 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2484 if (I != PromotedNodes.end()) return I->second;
2486 // Promotion needs an optimization step to clean up after it, and is not
2487 // careful to avoid operations the target does not support. Make sure that
2488 // all generated operations are legalized in the next iteration.
2489 NeedsAnotherIteration = true;
2491 switch (Node->getOpcode()) {
2492 case ISD::CopyFromReg:
2493 assert(0 && "CopyFromReg must be legal!");
2495 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2496 assert(0 && "Do not know how to promote this operator!");
2499 Result = DAG.getNode(ISD::UNDEF, NVT);
2503 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2505 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2506 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2508 case ISD::ConstantFP:
2509 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2510 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2514 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2515 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2516 Node->getOperand(1), Node->getOperand(2));
2517 Result = LegalizeOp(Result);
2521 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2523 Result = LegalizeOp(Node->getOperand(0));
2524 assert(Result.getValueType() >= NVT &&
2525 "This truncation doesn't make sense!");
2526 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2527 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2530 // The truncation is not required, because we don't guarantee anything
2531 // about high bits anyway.
2532 Result = PromoteOp(Node->getOperand(0));
2535 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2536 // Truncate the low part of the expanded value to the result type
2537 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2540 case ISD::SIGN_EXTEND:
2541 case ISD::ZERO_EXTEND:
2542 case ISD::ANY_EXTEND:
2543 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2544 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2546 // Input is legal? Just do extend all the way to the larger type.
2547 Result = LegalizeOp(Node->getOperand(0));
2548 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2551 // Promote the reg if it's smaller.
2552 Result = PromoteOp(Node->getOperand(0));
2553 // The high bits are not guaranteed to be anything. Insert an extend.
2554 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2555 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2556 DAG.getValueType(Node->getOperand(0).getValueType()));
2557 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2558 Result = DAG.getZeroExtendInReg(Result,
2559 Node->getOperand(0).getValueType());
2563 case ISD::BIT_CONVERT:
2564 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2565 Result = PromoteOp(Result);
2568 case ISD::FP_EXTEND:
2569 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2571 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2572 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2573 case Promote: assert(0 && "Unreachable with 2 FP types!");
2575 // Input is legal? Do an FP_ROUND_INREG.
2576 Result = LegalizeOp(Node->getOperand(0));
2577 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2578 DAG.getValueType(VT));
2583 case ISD::SINT_TO_FP:
2584 case ISD::UINT_TO_FP:
2585 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2587 Result = LegalizeOp(Node->getOperand(0));
2588 // No extra round required here.
2589 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2593 Result = PromoteOp(Node->getOperand(0));
2594 if (Node->getOpcode() == ISD::SINT_TO_FP)
2595 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2597 DAG.getValueType(Node->getOperand(0).getValueType()));
2599 Result = DAG.getZeroExtendInReg(Result,
2600 Node->getOperand(0).getValueType());
2601 // No extra round required here.
2602 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2605 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
2606 Node->getOperand(0));
2607 // Round if we cannot tolerate excess precision.
2608 if (NoExcessFPPrecision)
2609 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2610 DAG.getValueType(VT));
2615 case ISD::SIGN_EXTEND_INREG:
2616 Result = PromoteOp(Node->getOperand(0));
2617 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2618 Node->getOperand(1));
2620 case ISD::FP_TO_SINT:
2621 case ISD::FP_TO_UINT:
2622 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2624 Tmp1 = LegalizeOp(Node->getOperand(0));
2627 // The input result is prerounded, so we don't have to do anything
2629 Tmp1 = PromoteOp(Node->getOperand(0));
2632 assert(0 && "not implemented");
2634 // If we're promoting a UINT to a larger size, check to see if the new node
2635 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
2636 // we can use that instead. This allows us to generate better code for
2637 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
2638 // legal, such as PowerPC.
2639 if (Node->getOpcode() == ISD::FP_TO_UINT &&
2640 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
2641 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
2642 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
2643 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
2645 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2651 Tmp1 = PromoteOp(Node->getOperand(0));
2652 assert(Tmp1.getValueType() == NVT);
2653 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2654 // NOTE: we do not have to do any extra rounding here for
2655 // NoExcessFPPrecision, because we know the input will have the appropriate
2656 // precision, and these operations don't modify precision at all.
2662 Tmp1 = PromoteOp(Node->getOperand(0));
2663 assert(Tmp1.getValueType() == NVT);
2664 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2665 if(NoExcessFPPrecision)
2666 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2667 DAG.getValueType(VT));
2676 // The input may have strange things in the top bits of the registers, but
2677 // these operations don't care. They may have weird bits going out, but
2678 // that too is okay if they are integer operations.
2679 Tmp1 = PromoteOp(Node->getOperand(0));
2680 Tmp2 = PromoteOp(Node->getOperand(1));
2681 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2682 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2687 // The input may have strange things in the top bits of the registers, but
2688 // these operations don't care.
2689 Tmp1 = PromoteOp(Node->getOperand(0));
2690 Tmp2 = PromoteOp(Node->getOperand(1));
2691 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2692 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2694 // Floating point operations will give excess precision that we may not be
2695 // able to tolerate. If we DO allow excess precision, just leave it,
2696 // otherwise excise it.
2697 // FIXME: Why would we need to round FP ops more than integer ones?
2698 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
2699 if (NoExcessFPPrecision)
2700 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2701 DAG.getValueType(VT));
2706 // These operators require that their input be sign extended.
2707 Tmp1 = PromoteOp(Node->getOperand(0));
2708 Tmp2 = PromoteOp(Node->getOperand(1));
2709 if (MVT::isInteger(NVT)) {
2710 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2711 DAG.getValueType(VT));
2712 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
2713 DAG.getValueType(VT));
2715 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2717 // Perform FP_ROUND: this is probably overly pessimistic.
2718 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
2719 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2720 DAG.getValueType(VT));
2724 // These operators require that their input be fp extended.
2725 Tmp1 = PromoteOp(Node->getOperand(0));
2726 Tmp2 = PromoteOp(Node->getOperand(1));
2727 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2729 // Perform FP_ROUND: this is probably overly pessimistic.
2730 if (NoExcessFPPrecision)
2731 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2732 DAG.getValueType(VT));
2737 // These operators require that their input be zero extended.
2738 Tmp1 = PromoteOp(Node->getOperand(0));
2739 Tmp2 = PromoteOp(Node->getOperand(1));
2740 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
2741 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2742 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
2743 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2747 Tmp1 = PromoteOp(Node->getOperand(0));
2748 Tmp2 = LegalizeOp(Node->getOperand(1));
2749 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2);
2752 // The input value must be properly sign extended.
2753 Tmp1 = PromoteOp(Node->getOperand(0));
2754 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2755 DAG.getValueType(VT));
2756 Tmp2 = LegalizeOp(Node->getOperand(1));
2757 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2);
2760 // The input value must be properly zero extended.
2761 Tmp1 = PromoteOp(Node->getOperand(0));
2762 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2763 Tmp2 = LegalizeOp(Node->getOperand(1));
2764 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2);
2767 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2768 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2769 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2,
2770 Node->getOperand(2), VT);
2771 // Remember that we legalized the chain.
2772 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2777 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2778 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2779 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2,
2780 Node->getOperand(2),
2781 cast<VTSDNode>(Node->getOperand(3))->getVT());
2782 // Remember that we legalized the chain.
2783 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2786 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2787 case Expand: assert(0 && "It's impossible to expand bools");
2789 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition.
2792 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2795 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
2796 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
2797 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3);
2799 case ISD::SELECT_CC:
2800 Tmp2 = PromoteOp(Node->getOperand(2)); // True
2801 Tmp3 = PromoteOp(Node->getOperand(3)); // False
2802 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
2803 Node->getOperand(1), Tmp2, Tmp3,
2804 Node->getOperand(4));
2808 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2809 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
2811 std::vector<SDOperand> Ops;
2812 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i)
2813 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2815 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
2816 "Can only promote single result calls");
2817 std::vector<MVT::ValueType> RetTyVTs;
2818 RetTyVTs.reserve(2);
2819 RetTyVTs.push_back(NVT);
2820 RetTyVTs.push_back(MVT::Other);
2821 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
2822 Node->getOpcode() == ISD::TAILCALL);
2823 Result = SDOperand(NC, 0);
2825 // Insert the new chain mapping.
2826 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2832 Tmp1 = Node->getOperand(0);
2833 //Zero extend the argument
2834 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2835 // Perform the larger operation, then subtract if needed.
2836 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2837 switch(Node->getOpcode())
2843 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2844 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2845 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
2846 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2847 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1);
2850 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2851 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2852 DAG.getConstant(getSizeInBits(NVT) -
2853 getSizeInBits(VT), NVT));
2859 assert(Result.Val && "Didn't set a result!");
2860 AddPromotedOperand(Op, Result);
2864 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
2865 /// The resultant code need not be legal. Note that SrcOp is the input operand
2866 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
2867 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
2869 // Create the stack frame object.
2870 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2871 unsigned ByteSize = MVT::getSizeInBits(DestVT)/8;
2872 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
2873 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
2875 // Emit a store to the stack slot.
2876 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
2877 SrcOp, FIPtr, DAG.getSrcValue(NULL));
2878 // Result is a load from the stack slot.
2879 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0));
2882 /// ExpandAddSub - Find a clever way to expand this add operation into
2884 void SelectionDAGLegalize::
2885 ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
2886 SDOperand &Lo, SDOperand &Hi) {
2887 // Expand the subcomponents.
2888 SDOperand LHSL, LHSH, RHSL, RHSH;
2889 ExpandOp(LHS, LHSL, LHSH);
2890 ExpandOp(RHS, RHSL, RHSH);
2892 std::vector<SDOperand> Ops;
2893 Ops.push_back(LHSL);
2894 Ops.push_back(LHSH);
2895 Ops.push_back(RHSL);
2896 Ops.push_back(RHSH);
2897 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
2898 Lo = DAG.getNode(NodeOp, VTs, Ops);
2899 Hi = Lo.getValue(1);
2902 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
2903 SDOperand Op, SDOperand Amt,
2904 SDOperand &Lo, SDOperand &Hi) {
2905 // Expand the subcomponents.
2906 SDOperand LHSL, LHSH;
2907 ExpandOp(Op, LHSL, LHSH);
2909 std::vector<SDOperand> Ops;
2910 Ops.push_back(LHSL);
2911 Ops.push_back(LHSH);
2913 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
2914 Lo = DAG.getNode(NodeOp, VTs, Ops);
2915 Hi = Lo.getValue(1);
2919 /// ExpandShift - Try to find a clever way to expand this shift operation out to
2920 /// smaller elements. If we can't find a way that is more efficient than a
2921 /// libcall on this target, return false. Otherwise, return true with the
2922 /// low-parts expanded into Lo and Hi.
2923 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
2924 SDOperand &Lo, SDOperand &Hi) {
2925 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
2926 "This is not a shift!");
2928 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
2929 SDOperand ShAmt = LegalizeOp(Amt);
2930 MVT::ValueType ShTy = ShAmt.getValueType();
2931 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
2932 unsigned NVTBits = MVT::getSizeInBits(NVT);
2934 // Handle the case when Amt is an immediate. Other cases are currently broken
2935 // and are disabled.
2936 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
2937 unsigned Cst = CN->getValue();
2938 // Expand the incoming operand to be shifted, so that we have its parts
2940 ExpandOp(Op, InL, InH);
2944 Lo = DAG.getConstant(0, NVT);
2945 Hi = DAG.getConstant(0, NVT);
2946 } else if (Cst > NVTBits) {
2947 Lo = DAG.getConstant(0, NVT);
2948 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
2949 } else if (Cst == NVTBits) {
2950 Lo = DAG.getConstant(0, NVT);
2953 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
2954 Hi = DAG.getNode(ISD::OR, NVT,
2955 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
2956 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
2961 Lo = DAG.getConstant(0, NVT);
2962 Hi = DAG.getConstant(0, NVT);
2963 } else if (Cst > NVTBits) {
2964 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
2965 Hi = DAG.getConstant(0, NVT);
2966 } else if (Cst == NVTBits) {
2968 Hi = DAG.getConstant(0, NVT);
2970 Lo = DAG.getNode(ISD::OR, NVT,
2971 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
2972 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
2973 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
2978 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
2979 DAG.getConstant(NVTBits-1, ShTy));
2980 } else if (Cst > NVTBits) {
2981 Lo = DAG.getNode(ISD::SRA, NVT, InH,
2982 DAG.getConstant(Cst-NVTBits, ShTy));
2983 Hi = DAG.getNode(ISD::SRA, NVT, InH,
2984 DAG.getConstant(NVTBits-1, ShTy));
2985 } else if (Cst == NVTBits) {
2987 Hi = DAG.getNode(ISD::SRA, NVT, InH,
2988 DAG.getConstant(NVTBits-1, ShTy));
2990 Lo = DAG.getNode(ISD::OR, NVT,
2991 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
2992 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
2993 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
2998 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy,
2999 // so disable it for now. Currently targets are handling this via SHL_PARTS
3003 // If we have an efficient select operation (or if the selects will all fold
3004 // away), lower to some complex code, otherwise just emit the libcall.
3005 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt))
3009 ExpandOp(Op, InL, InH);
3010 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt
3011 DAG.getConstant(NVTBits, ShTy), ShAmt);
3013 // Compare the unmasked shift amount against 32.
3014 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt,
3015 DAG.getConstant(NVTBits, ShTy), ISD::SETGE);
3017 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) {
3018 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31
3019 DAG.getConstant(NVTBits-1, ShTy));
3020 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31
3021 DAG.getConstant(NVTBits-1, ShTy));
3024 if (Opc == ISD::SHL) {
3025 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt)
3026 DAG.getNode(ISD::SHL, NVT, InH, ShAmt),
3027 DAG.getNode(ISD::SRL, NVT, InL, NAmt));
3028 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31
3030 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
3031 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2);
3033 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT,
3034 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt,
3035 DAG.getConstant(32, ShTy),
3037 DAG.getConstant(0, NVT),
3038 DAG.getNode(ISD::SHL, NVT, InH, NAmt));
3039 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt)
3041 DAG.getNode(ISD::SRL, NVT, InL, ShAmt));
3042 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31
3045 if (Opc == ISD::SRA)
3046 HiPart = DAG.getNode(ISD::SRA, NVT, InH,
3047 DAG.getConstant(NVTBits-1, ShTy));
3049 HiPart = DAG.getConstant(0, NVT);
3050 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
3051 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2);
3056 /// FindLatestCallSeqStart - Scan up the dag to find the latest (highest
3057 /// NodeDepth) node that is an CallSeqStart operation and occurs later than
3059 static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found) {
3060 if (Node->getNodeDepth() <= Found->getNodeDepth()) return;
3062 // If we found an CALLSEQ_START, we already know this node occurs later
3063 // than the Found node. Just remember this node and return.
3064 if (Node->getOpcode() == ISD::CALLSEQ_START) {
3069 // Otherwise, scan the operands of Node to see if any of them is a call.
3070 assert(Node->getNumOperands() != 0 &&
3071 "All leaves should have depth equal to the entry node!");
3072 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i)
3073 FindLatestCallSeqStart(Node->getOperand(i).Val, Found);
3075 // Tail recurse for the last iteration.
3076 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val,
3081 /// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest
3082 /// NodeDepth) node that is an CallSeqEnd operation and occurs more recent
3084 static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found,
3085 std::set<SDNode*> &Visited) {
3086 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) ||
3087 !Visited.insert(Node).second) return;
3089 // If we found an CALLSEQ_END, we already know this node occurs earlier
3090 // than the Found node. Just remember this node and return.
3091 if (Node->getOpcode() == ISD::CALLSEQ_END) {
3096 // Otherwise, scan the operands of Node to see if any of them is a call.
3097 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
3098 if (UI == E) return;
3099 for (--E; UI != E; ++UI)
3100 FindEarliestCallSeqEnd(*UI, Found, Visited);
3102 // Tail recurse for the last iteration.
3103 FindEarliestCallSeqEnd(*UI, Found, Visited);
3106 /// FindCallSeqEnd - Given a chained node that is part of a call sequence,
3107 /// find the CALLSEQ_END node that terminates the call sequence.
3108 static SDNode *FindCallSeqEnd(SDNode *Node) {
3109 if (Node->getOpcode() == ISD::CALLSEQ_END)
3111 if (Node->use_empty())
3112 return 0; // No CallSeqEnd
3114 SDOperand TheChain(Node, Node->getNumValues()-1);
3115 if (TheChain.getValueType() != MVT::Other)
3116 TheChain = SDOperand(Node, 0);
3117 if (TheChain.getValueType() != MVT::Other)
3120 for (SDNode::use_iterator UI = Node->use_begin(),
3121 E = Node->use_end(); UI != E; ++UI) {
3123 // Make sure to only follow users of our token chain.
3125 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
3126 if (User->getOperand(i) == TheChain)
3127 if (SDNode *Result = FindCallSeqEnd(User))
3133 /// FindCallSeqStart - Given a chained node that is part of a call sequence,
3134 /// find the CALLSEQ_START node that initiates the call sequence.
3135 static SDNode *FindCallSeqStart(SDNode *Node) {
3136 assert(Node && "Didn't find callseq_start for a call??");
3137 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
3139 assert(Node->getOperand(0).getValueType() == MVT::Other &&
3140 "Node doesn't have a token chain argument!");
3141 return FindCallSeqStart(Node->getOperand(0).Val);
3145 /// FindInputOutputChains - If we are replacing an operation with a call we need
3146 /// to find the call that occurs before and the call that occurs after it to
3147 /// properly serialize the calls in the block. The returned operand is the
3148 /// input chain value for the new call (e.g. the entry node or the previous
3149 /// call), and OutChain is set to be the chain node to update to point to the
3150 /// end of the call chain.
3151 static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain,
3153 SDNode *LatestCallSeqStart = Entry.Val;
3154 SDNode *LatestCallSeqEnd = 0;
3155 FindLatestCallSeqStart(OpNode, LatestCallSeqStart);
3156 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n";
3158 // It is possible that no ISD::CALLSEQ_START was found because there is no
3159 // previous call in the function. LatestCallStackDown may in that case be
3160 // the entry node itself. Do not attempt to find a matching CALLSEQ_END
3161 // unless LatestCallStackDown is an CALLSEQ_START.
3162 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) {
3163 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart);
3164 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n";
3166 LatestCallSeqEnd = Entry.Val;
3168 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd");
3170 // Finally, find the first call that this must come before, first we find the
3171 // CallSeqEnd that ends the call.
3173 std::set<SDNode*> Visited;
3174 FindEarliestCallSeqEnd(OpNode, OutChain, Visited);
3176 // If we found one, translate from the adj up to the callseq_start.
3178 OutChain = FindCallSeqStart(OutChain);
3180 return SDOperand(LatestCallSeqEnd, 0);
3183 /// SpliceCallInto - Given the result chain of a libcall (CallResult), and a
3184 void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult,
3186 // Nothing to splice it into?
3187 if (OutChain == 0) return;
3189 assert(OutChain->getOperand(0).getValueType() == MVT::Other);
3192 // Form a token factor node merging the old inval and the new inval.
3193 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult,
3194 OutChain->getOperand(0));
3195 // Change the node to refer to the new token.
3196 OutChain->setAdjCallChain(InToken);
3200 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
3201 // does not fit into a register, return the lo part and set the hi part to the
3202 // by-reg argument. If it does fit into a single register, return the result
3203 // and leave the Hi part unset.
3204 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3207 SDOperand InChain = FindInputOutputChains(Node, OutChain,
3208 DAG.getEntryNode());
3209 if (InChain.Val == 0)
3210 InChain = DAG.getEntryNode();
3212 TargetLowering::ArgListTy Args;
3213 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3214 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3215 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3216 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3218 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3220 // Splice the libcall in wherever FindInputOutputChains tells us to.
3221 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3222 std::pair<SDOperand,SDOperand> CallInfo =
3223 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3227 switch (getTypeAction(CallInfo.first.getValueType())) {
3228 default: assert(0 && "Unknown thing");
3230 Result = CallInfo.first;
3233 assert(0 && "Cannot promote this yet!");
3235 ExpandOp(CallInfo.first, Result, Hi);
3236 CallInfo.second = LegalizeOp(CallInfo.second);
3240 SpliceCallInto(CallInfo.second, OutChain);
3241 NeedsAnotherIteration = true;
3246 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3247 /// destination type is legal.
3248 SDOperand SelectionDAGLegalize::
3249 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3250 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3251 assert(getTypeAction(Source.getValueType()) == Expand &&
3252 "This is not an expansion!");
3253 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3256 assert(Source.getValueType() == MVT::i64 &&
3257 "This only works for 64-bit -> FP");
3258 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3259 // incoming integer is set. To handle this, we dynamically test to see if
3260 // it is set, and, if so, add a fudge factor.
3262 ExpandOp(Source, Lo, Hi);
3264 // If this is unsigned, and not supported, first perform the conversion to
3265 // signed, then adjust the result if the sign bit is set.
3266 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3267 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3269 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3270 DAG.getConstant(0, Hi.getValueType()),
3272 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3273 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3274 SignSet, Four, Zero);
3275 uint64_t FF = 0x5f800000ULL;
3276 if (TLI.isLittleEndian()) FF <<= 32;
3277 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3279 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3280 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3281 SDOperand FudgeInReg;
3282 if (DestTy == MVT::f32)
3283 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3284 DAG.getSrcValue(NULL));
3286 assert(DestTy == MVT::f64 && "Unexpected conversion");
3287 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3288 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
3290 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3293 // Check to see if the target has a custom way to lower this. If so, use it.
3294 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3295 default: assert(0 && "This action not implemented for this operation!");
3296 case TargetLowering::Legal:
3297 case TargetLowering::Expand:
3298 break; // This case is handled below.
3299 case TargetLowering::Custom: {
3300 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3303 return LegalizeOp(NV);
3304 break; // The target decided this was legal after all
3308 // Expand the source, then glue it back together for the call. We must expand
3309 // the source in case it is shared (this pass of legalize must traverse it).
3310 SDOperand SrcLo, SrcHi;
3311 ExpandOp(Source, SrcLo, SrcHi);
3312 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
3314 SDNode *OutChain = 0;
3315 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain,
3316 DAG.getEntryNode());
3317 const char *FnName = 0;
3318 if (DestTy == MVT::f32)
3319 FnName = "__floatdisf";
3321 assert(DestTy == MVT::f64 && "Unknown fp value type!");
3322 FnName = "__floatdidf";
3325 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy());
3327 TargetLowering::ArgListTy Args;
3328 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType());
3330 Args.push_back(std::make_pair(Source, ArgTy));
3332 // We don't care about token chains for libcalls. We just use the entry
3333 // node as our input and ignore the output chain. This allows us to place
3334 // calls wherever we need them to satisfy data dependences.
3335 const Type *RetTy = MVT::getTypeForValueType(DestTy);
3337 std::pair<SDOperand,SDOperand> CallResult =
3338 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true,
3341 SpliceCallInto(CallResult.second, OutChain);
3342 return CallResult.first;
3347 /// ExpandOp - Expand the specified SDOperand into its two component pieces
3348 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
3349 /// LegalizeNodes map is filled in for any results that are not expanded, the
3350 /// ExpandedNodes map is filled in for any results that are expanded, and the
3351 /// Lo/Hi values are returned.
3352 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
3353 MVT::ValueType VT = Op.getValueType();
3354 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3355 SDNode *Node = Op.Val;
3356 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
3357 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
3358 "Cannot expand FP values!");
3359 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
3360 "Cannot expand to FP value or to larger int value!");
3362 // See if we already expanded it.
3363 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
3364 = ExpandedNodes.find(Op);
3365 if (I != ExpandedNodes.end()) {
3366 Lo = I->second.first;
3367 Hi = I->second.second;
3371 // Expanding to multiple registers needs to perform an optimization step, and
3372 // is not careful to avoid operations the target does not support. Make sure
3373 // that all generated operations are legalized in the next iteration.
3374 NeedsAnotherIteration = true;
3376 switch (Node->getOpcode()) {
3377 case ISD::CopyFromReg:
3378 assert(0 && "CopyFromReg must be legal!");
3380 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
3381 assert(0 && "Do not know how to expand this operator!");
3384 Lo = DAG.getNode(ISD::UNDEF, NVT);
3385 Hi = DAG.getNode(ISD::UNDEF, NVT);
3387 case ISD::Constant: {
3388 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
3389 Lo = DAG.getConstant(Cst, NVT);
3390 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
3393 case ISD::ConstantVec: {
3394 unsigned NumElements = Node->getNumOperands();
3395 // If we only have two elements left in the constant vector, just break it
3396 // apart into the two scalar constants it contains. Otherwise, bisect the
3397 // ConstantVec, and return each half as a new ConstantVec.
3398 // FIXME: this is hard coded as big endian, it may have to change to support
3399 // SSE and Alpha MVI
3400 if (NumElements == 2) {
3401 Hi = Node->getOperand(0);
3402 Lo = Node->getOperand(1);
3405 std::vector<SDOperand> LoOps, HiOps;
3406 for (unsigned I = 0, E = NumElements; I < E; ++I) {
3407 HiOps.push_back(Node->getOperand(I));
3408 LoOps.push_back(Node->getOperand(I+NumElements));
3410 Lo = DAG.getNode(ISD::ConstantVec, MVT::Vector, LoOps);
3411 Hi = DAG.getNode(ISD::ConstantVec, MVT::Vector, HiOps);
3416 case ISD::BUILD_PAIR:
3417 // Legalize both operands. FIXME: in the future we should handle the case
3418 // where the two elements are not legal.
3419 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
3420 Lo = LegalizeOp(Node->getOperand(0));
3421 Hi = LegalizeOp(Node->getOperand(1));
3424 case ISD::SIGN_EXTEND_INREG:
3425 ExpandOp(Node->getOperand(0), Lo, Hi);
3426 // Sign extend the lo-part.
3427 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
3428 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
3429 TLI.getShiftAmountTy()));
3430 // sext_inreg the low part if needed.
3431 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
3435 ExpandOp(Node->getOperand(0), Lo, Hi);
3436 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
3437 DAG.getNode(ISD::CTPOP, NVT, Lo),
3438 DAG.getNode(ISD::CTPOP, NVT, Hi));
3439 Hi = DAG.getConstant(0, NVT);
3443 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
3444 ExpandOp(Node->getOperand(0), Lo, Hi);
3445 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3446 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
3447 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
3449 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
3450 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
3452 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
3453 Hi = DAG.getConstant(0, NVT);
3458 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
3459 ExpandOp(Node->getOperand(0), Lo, Hi);
3460 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3461 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
3462 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
3464 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
3465 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
3467 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
3468 Hi = DAG.getConstant(0, NVT);
3473 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3474 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3475 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3477 // Increment the pointer to the other half.
3478 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
3479 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3480 getIntPtrConstant(IncrementSize));
3481 //Is this safe? declaring that the two parts of the split load
3482 //are from the same instruction?
3483 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3485 // Build a factor node to remember that this load is independent of the
3487 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3490 // Remember that we legalized the chain.
3491 AddLegalizedOperand(Op.getValue(1), TF);
3492 if (!TLI.isLittleEndian())
3497 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3498 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3499 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue();
3500 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3502 // If we only have two elements, turn into a pair of scalar loads.
3503 // FIXME: handle case where a vector of two elements is fine, such as
3504 // 2 x double on SSE2.
3505 if (NumElements == 2) {
3506 Lo = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4));
3507 // Increment the pointer to the other half.
3508 unsigned IncrementSize = MVT::getSizeInBits(EVT)/8;
3509 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3510 getIntPtrConstant(IncrementSize));
3511 //Is this safe? declaring that the two parts of the split load
3512 //are from the same instruction?
3513 Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4));
3515 NumElements /= 2; // Split the vector in half
3516 Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4));
3517 unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8;
3518 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3519 getIntPtrConstant(IncrementSize));
3520 //Is this safe? declaring that the two parts of the split load
3521 //are from the same instruction?
3522 Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4));
3525 // Build a factor node to remember that this load is independent of the
3527 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3530 // Remember that we legalized the chain.
3531 AddLegalizedOperand(Op.getValue(1), TF);
3532 if (!TLI.isLittleEndian())
3539 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue();
3540 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3541 SDOperand LL, LH, RL, RH;
3543 ExpandOp(Node->getOperand(0), LL, LH);
3544 ExpandOp(Node->getOperand(1), RL, RH);
3546 // If we only have two elements, turn into a pair of scalar loads.
3547 // FIXME: handle case where a vector of two elements is fine, such as
3548 // 2 x double on SSE2.
3549 if (NumElements == 2) {
3550 unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT);
3551 Lo = DAG.getNode(Opc, EVT, LL, RL);
3552 Hi = DAG.getNode(Opc, EVT, LH, RH);
3554 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, LL.getOperand(2),
3556 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, LH.getOperand(2),
3563 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3564 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
3566 bool Changed = false;
3567 std::vector<SDOperand> Ops;
3568 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
3569 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3570 Changed |= Ops.back() != Node->getOperand(i);
3573 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
3574 "Can only expand a call once so far, not i64 -> i16!");
3576 std::vector<MVT::ValueType> RetTyVTs;
3577 RetTyVTs.reserve(3);
3578 RetTyVTs.push_back(NVT);
3579 RetTyVTs.push_back(NVT);
3580 RetTyVTs.push_back(MVT::Other);
3581 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops,
3582 Node->getOpcode() == ISD::TAILCALL);
3583 Lo = SDOperand(NC, 0);
3584 Hi = SDOperand(NC, 1);
3586 // Insert the new chain mapping.
3587 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2));
3592 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
3593 SDOperand LL, LH, RL, RH;
3594 ExpandOp(Node->getOperand(0), LL, LH);
3595 ExpandOp(Node->getOperand(1), RL, RH);
3596 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
3597 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
3601 SDOperand C, LL, LH, RL, RH;
3603 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3604 case Expand: assert(0 && "It's impossible to expand bools");
3606 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
3609 C = PromoteOp(Node->getOperand(0)); // Promote the condition.
3612 ExpandOp(Node->getOperand(1), LL, LH);
3613 ExpandOp(Node->getOperand(2), RL, RH);
3614 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL);
3615 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH);
3618 case ISD::SELECT_CC: {
3619 SDOperand TL, TH, FL, FH;
3620 ExpandOp(Node->getOperand(2), TL, TH);
3621 ExpandOp(Node->getOperand(3), FL, FH);
3622 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3623 Node->getOperand(1), TL, FL, Node->getOperand(4));
3624 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3625 Node->getOperand(1), TH, FH, Node->getOperand(4));
3626 Lo = LegalizeOp(Lo);
3627 Hi = LegalizeOp(Hi);
3630 case ISD::SEXTLOAD: {
3631 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3632 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3633 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3636 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3638 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3641 // Remember that we legalized the chain.
3642 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3644 // The high part is obtained by SRA'ing all but one of the bits of the lo
3646 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3647 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3648 TLI.getShiftAmountTy()));
3649 Lo = LegalizeOp(Lo);
3650 Hi = LegalizeOp(Hi);
3653 case ISD::ZEXTLOAD: {
3654 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3655 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3656 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3659 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3661 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3664 // Remember that we legalized the chain.
3665 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3667 // The high part is just a zero.
3668 Hi = LegalizeOp(DAG.getConstant(0, NVT));
3669 Lo = LegalizeOp(Lo);
3672 case ISD::EXTLOAD: {
3673 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3674 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3675 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3678 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3680 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3683 // Remember that we legalized the chain.
3684 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3686 // The high part is undefined.
3687 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT));
3688 Lo = LegalizeOp(Lo);
3691 case ISD::ANY_EXTEND: {
3693 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3694 case Expand: assert(0 && "expand-expand not implemented yet!");
3695 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3697 In = PromoteOp(Node->getOperand(0));
3701 // The low part is any extension of the input (which degenerates to a copy).
3702 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In);
3703 // The high part is undefined.
3704 Hi = DAG.getNode(ISD::UNDEF, NVT);
3707 case ISD::SIGN_EXTEND: {
3709 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3710 case Expand: assert(0 && "expand-expand not implemented yet!");
3711 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3713 In = PromoteOp(Node->getOperand(0));
3714 // Emit the appropriate sign_extend_inreg to get the value we want.
3715 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In,
3716 DAG.getValueType(Node->getOperand(0).getValueType()));
3720 // The low part is just a sign extension of the input (which degenerates to
3722 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In);
3724 // The high part is obtained by SRA'ing all but one of the bits of the lo
3726 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3727 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3728 TLI.getShiftAmountTy()));
3731 case ISD::ZERO_EXTEND: {
3733 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3734 case Expand: assert(0 && "expand-expand not implemented yet!");
3735 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3737 In = PromoteOp(Node->getOperand(0));
3738 // Emit the appropriate zero_extend_inreg to get the value we want.
3739 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType());
3743 // The low part is just a zero extension of the input (which degenerates to
3745 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In);
3747 // The high part is just a zero.
3748 Hi = DAG.getConstant(0, NVT);
3752 case ISD::BIT_CONVERT: {
3753 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0),
3754 Node->getOperand(0));
3755 ExpandOp(Tmp, Lo, Hi);
3759 case ISD::READCYCLECOUNTER: {
3760 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
3761 TargetLowering::Custom &&
3762 "Must custom expand ReadCycleCounter");
3763 SDOperand T = TLI.LowerOperation(Op, DAG);
3764 assert(T.Val && "Node must be custom expanded!");
3765 Lo = LegalizeOp(T.getValue(0));
3766 Hi = LegalizeOp(T.getValue(1));
3767 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
3768 LegalizeOp(T.getValue(2)));
3772 // These operators cannot be expanded directly, emit them as calls to
3773 // library functions.
3774 case ISD::FP_TO_SINT:
3775 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
3777 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3778 case Expand: assert(0 && "cannot expand FP!");
3779 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
3780 case Promote: Op = PromoteOp(Node->getOperand(0)); break;
3783 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
3785 // Now that the custom expander is done, expand the result, which is still
3788 ExpandOp(Op, Lo, Hi);
3793 if (Node->getOperand(0).getValueType() == MVT::f32)
3794 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
3796 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
3799 case ISD::FP_TO_UINT:
3800 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
3801 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT,
3802 LegalizeOp(Node->getOperand(0)));
3803 // Now that the custom expander is done, expand the result, which is still
3805 Op = TLI.LowerOperation(Op, DAG);
3807 ExpandOp(Op, Lo, Hi);
3812 if (Node->getOperand(0).getValueType() == MVT::f32)
3813 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
3815 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
3819 // If the target wants custom lowering, do so.
3820 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
3821 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0),
3822 LegalizeOp(Node->getOperand(1)));
3823 Op = TLI.LowerOperation(Op, DAG);
3825 // Now that the custom expander is done, expand the result, which is
3827 ExpandOp(Op, Lo, Hi);
3832 // If we can emit an efficient shift operation, do so now.
3833 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3836 // If this target supports SHL_PARTS, use it.
3837 if (TLI.isOperationLegal(ISD::SHL_PARTS, NVT)) {
3838 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1),
3843 // Otherwise, emit a libcall.
3844 Lo = ExpandLibCall("__ashldi3", Node, Hi);
3848 // If the target wants custom lowering, do so.
3849 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
3850 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0),
3851 LegalizeOp(Node->getOperand(1)));
3852 Op = TLI.LowerOperation(Op, DAG);
3854 // Now that the custom expander is done, expand the result, which is
3856 ExpandOp(Op, Lo, Hi);
3861 // If we can emit an efficient shift operation, do so now.
3862 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3865 // If this target supports SRA_PARTS, use it.
3866 if (TLI.isOperationLegal(ISD::SRA_PARTS, NVT)) {
3867 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1),
3872 // Otherwise, emit a libcall.
3873 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
3876 // If the target wants custom lowering, do so.
3877 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
3878 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0),
3879 LegalizeOp(Node->getOperand(1)));
3880 Op = TLI.LowerOperation(Op, DAG);
3882 // Now that the custom expander is done, expand the result, which is
3884 ExpandOp(Op, Lo, Hi);
3889 // If we can emit an efficient shift operation, do so now.
3890 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3893 // If this target supports SRL_PARTS, use it.
3894 if (TLI.isOperationLegal(ISD::SRL_PARTS, NVT)) {
3895 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1),
3900 // Otherwise, emit a libcall.
3901 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
3905 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1),
3909 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1),
3913 if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
3914 SDOperand LL, LH, RL, RH;
3915 ExpandOp(Node->getOperand(0), LL, LH);
3916 ExpandOp(Node->getOperand(1), RL, RH);
3917 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
3918 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
3919 // extended the sign bit of the low half through the upper half, and if so
3920 // emit a MULHS instead of the alternate sequence that is valid for any
3921 // i64 x i64 multiply.
3922 if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
3923 // is RH an extension of the sign bit of RL?
3924 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
3925 RH.getOperand(1).getOpcode() == ISD::Constant &&
3926 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
3927 // is LH an extension of the sign bit of LL?
3928 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
3929 LH.getOperand(1).getOpcode() == ISD::Constant &&
3930 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
3931 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
3933 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
3934 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
3935 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
3936 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
3937 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
3939 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
3941 Lo = ExpandLibCall("__muldi3" , Node, Hi); break;
3945 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
3946 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
3947 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
3948 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
3951 // Remember in a map if the values will be reused later.
3952 bool isNew = ExpandedNodes.insert(std::make_pair(Op,
3953 std::make_pair(Lo, Hi))).second;
3954 assert(isNew && "Value already expanded?!?");
3956 // Make sure the resultant values have been legalized themselves, unless this
3957 // is a type that requires multi-step expansion.
3958 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
3959 Lo = LegalizeOp(Lo);
3960 Hi = LegalizeOp(Hi);
3965 // SelectionDAG::Legalize - This is the entry point for the file.
3967 void SelectionDAG::Legalize() {
3968 /// run - This is the main entry point to this class.
3970 SelectionDAGLegalize(*this).Run();