1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/DwarfWriter.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetSubtarget.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/DerivedTypes.h"
31 #include "llvm/GlobalVariable.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/ADT/DenseMap.h"
36 #include "llvm/ADT/SmallVector.h"
37 #include "llvm/ADT/SmallPtrSet.h"
41 //===----------------------------------------------------------------------===//
42 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
43 /// hacks on it until the target machine can handle it. This involves
44 /// eliminating value sizes the machine cannot handle (promoting small sizes to
45 /// large sizes or splitting up large values into small values) as well as
46 /// eliminating operations the machine cannot handle.
48 /// This code also does a small amount of optimization and recognition of idioms
49 /// as part of its processing. For example, if a target does not support a
50 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
51 /// will attempt merge setcc and brc instructions into brcc's.
54 class VISIBILITY_HIDDEN SelectionDAGLegalize {
57 bool TypesNeedLegalizing;
59 // Libcall insertion helpers.
61 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
62 /// legalized. We use this to ensure that calls are properly serialized
63 /// against each other, including inserted libcalls.
64 SDValue LastCALLSEQ_END;
66 /// IsLegalizingCall - This member is used *only* for purposes of providing
67 /// helpful assertions that a libcall isn't created while another call is
68 /// being legalized (which could lead to non-serialized call sequences).
69 bool IsLegalizingCall;
72 Legal, // The target natively supports this operation.
73 Promote, // This operation should be executed in a larger type.
74 Expand // Try to expand this to other ops, otherwise use a libcall.
77 /// ValueTypeActions - This is a bitvector that contains two bits for each
78 /// value type, where the two bits correspond to the LegalizeAction enum.
79 /// This can be queried with "getTypeAction(VT)".
80 TargetLowering::ValueTypeActionImpl ValueTypeActions;
82 /// LegalizedNodes - For nodes that are of legal width, and that have more
83 /// than one use, this map indicates what regularized operand to use. This
84 /// allows us to avoid legalizing the same thing more than once.
85 DenseMap<SDValue, SDValue> LegalizedNodes;
87 /// PromotedNodes - For nodes that are below legal width, and that have more
88 /// than one use, this map indicates what promoted value to use. This allows
89 /// us to avoid promoting the same thing more than once.
90 DenseMap<SDValue, SDValue> PromotedNodes;
92 /// ExpandedNodes - For nodes that need to be expanded this map indicates
93 /// which operands are the expanded version of the input. This allows
94 /// us to avoid expanding the same node more than once.
95 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
97 /// SplitNodes - For vector nodes that need to be split, this map indicates
98 /// which operands are the split version of the input. This allows us
99 /// to avoid splitting the same node more than once.
100 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
102 /// ScalarizedNodes - For nodes that need to be converted from vector types to
103 /// scalar types, this contains the mapping of ones we have already
104 /// processed to the result.
105 std::map<SDValue, SDValue> ScalarizedNodes;
107 /// WidenNodes - For nodes that need to be widened from one vector type to
108 /// another, this contains the mapping of those that we have already widen.
109 /// This allows us to avoid widening more than once.
110 std::map<SDValue, SDValue> WidenNodes;
112 void AddLegalizedOperand(SDValue From, SDValue To) {
113 LegalizedNodes.insert(std::make_pair(From, To));
114 // If someone requests legalization of the new node, return itself.
116 LegalizedNodes.insert(std::make_pair(To, To));
118 void AddPromotedOperand(SDValue From, SDValue To) {
119 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
120 assert(isNew && "Got into the map somehow?");
122 // If someone requests legalization of the new node, return itself.
123 LegalizedNodes.insert(std::make_pair(To, To));
125 void AddWidenedOperand(SDValue From, SDValue To) {
126 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second;
127 assert(isNew && "Got into the map somehow?");
129 // If someone requests legalization of the new node, return itself.
130 LegalizedNodes.insert(std::make_pair(To, To));
134 explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing);
136 /// getTypeAction - Return how we should legalize values of this type, either
137 /// it is already legal or we need to expand it into multiple registers of
138 /// smaller integer type, or we need to promote it to a larger type.
139 LegalizeAction getTypeAction(MVT VT) const {
140 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
143 /// isTypeLegal - Return true if this type is legal on this target.
145 bool isTypeLegal(MVT VT) const {
146 return getTypeAction(VT) == Legal;
152 /// HandleOp - Legalize, Promote, or Expand the specified operand as
153 /// appropriate for its type.
154 void HandleOp(SDValue Op);
156 /// LegalizeOp - We know that the specified value has a legal type.
157 /// Recursively ensure that the operands have legal types, then return the
159 SDValue LegalizeOp(SDValue O);
161 /// UnrollVectorOp - We know that the given vector has a legal type, however
162 /// the operation it performs is not legal and is an operation that we have
163 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
164 /// operating on each element individually.
165 SDValue UnrollVectorOp(SDValue O);
167 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
168 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
169 /// is necessary to spill the vector being inserted into to memory, perform
170 /// the insert there, and then read the result back.
171 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
174 /// PromoteOp - Given an operation that produces a value in an invalid type,
175 /// promote it to compute the value into a larger type. The produced value
176 /// will have the correct bits for the low portion of the register, but no
177 /// guarantee is made about the top bits: it may be zero, sign-extended, or
179 SDValue PromoteOp(SDValue O);
181 /// ExpandOp - Expand the specified SDValue into its two component pieces
182 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
183 /// the LegalizedNodes map is filled in for any results that are not expanded,
184 /// the ExpandedNodes map is filled in for any results that are expanded, and
185 /// the Lo/Hi values are returned. This applies to integer types and Vector
187 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
189 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
190 /// (e.g., v3i32 to v4i32). The produced value will have the correct value
191 /// for the existing elements but no guarantee is made about the new elements
192 /// at the end of the vector: it may be zero, ones, or garbage. This is useful
193 /// when we have an instruction operating on an illegal vector type and we
194 /// want to widen it to do the computation on a legal wider vector type.
195 SDValue WidenVectorOp(SDValue Op, MVT WidenVT);
197 /// SplitVectorOp - Given an operand of vector type, break it down into
198 /// two smaller values.
199 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
201 /// ScalarizeVectorOp - Given an operand of single-element vector type
202 /// (e.g. v1f32), convert it into the equivalent operation that returns a
203 /// scalar (e.g. f32) value.
204 SDValue ScalarizeVectorOp(SDValue O);
206 /// Useful 16 element vector type that is used to pass operands for widening.
207 typedef SmallVector<SDValue, 16> SDValueVector;
209 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if
210 /// the LdChain contains a single load and false if it contains a token
211 /// factor for multiple loads. It takes
212 /// Result: location to return the result
213 /// LdChain: location to return the load chain
214 /// Op: load operation to widen
215 /// NVT: widen vector result type we want for the load
216 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
217 SDValue Op, MVT NVT);
219 /// Helper genWidenVectorLoads - Helper function to generate a set of
220 /// loads to load a vector with a resulting wider type. It takes
221 /// LdChain: list of chains for the load we have generated
222 /// Chain: incoming chain for the ld vector
223 /// BasePtr: base pointer to load from
224 /// SV: memory disambiguation source value
225 /// SVOffset: memory disambiugation offset
226 /// Alignment: alignment of the memory
227 /// isVolatile: volatile load
228 /// LdWidth: width of memory that we want to load
229 /// ResType: the wider result result type for the resulting loaded vector
230 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain,
231 SDValue BasePtr, const Value *SV,
232 int SVOffset, unsigned Alignment,
233 bool isVolatile, unsigned LdWidth,
236 /// StoreWidenVectorOp - Stores a widen vector into non widen memory
237 /// location. It takes
238 /// ST: store node that we want to replace
239 /// Chain: incoming store chain
240 /// BasePtr: base address of where we want to store into
241 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
244 /// Helper genWidenVectorStores - Helper function to generate a set of
245 /// stores to store a widen vector into non widen memory
247 // StChain: list of chains for the stores we have generated
248 // Chain: incoming chain for the ld vector
249 // BasePtr: base pointer to load from
250 // SV: memory disambiguation source value
251 // SVOffset: memory disambiugation offset
252 // Alignment: alignment of the memory
253 // isVolatile: volatile lod
254 // ValOp: value to store
255 // StWidth: width of memory that we want to store
256 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain,
257 SDValue BasePtr, const Value *SV,
258 int SVOffset, unsigned Alignment,
259 bool isVolatile, SDValue ValOp,
262 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
263 /// specified mask and type. Targets can specify exactly which masks they
264 /// support and the code generator is tasked with not creating illegal masks.
266 /// Note that this will also return true for shuffles that are promoted to a
269 /// If this is a legal shuffle, this method returns the (possibly promoted)
270 /// build_vector Mask. If it's not a legal shuffle, it returns null.
271 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
273 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
274 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
276 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC);
277 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC);
278 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC) {
279 LegalizeSetCCOperands(LHS, RHS, CC);
280 LegalizeSetCCCondCode(VT, LHS, RHS, CC);
283 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
285 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source);
287 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT);
288 SDValue ExpandBUILD_VECTOR(SDNode *Node);
289 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
290 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op);
291 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT);
292 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned);
293 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned);
295 SDValue ExpandBSWAP(SDValue Op);
296 SDValue ExpandBitCount(unsigned Opc, SDValue Op);
297 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
298 SDValue &Lo, SDValue &Hi);
299 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
300 SDValue &Lo, SDValue &Hi);
302 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
303 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
305 // Returns the legalized (truncated or extended) shift amount.
306 SDValue LegalizeShiftAmount(SDValue ShiftAmt);
310 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
311 /// specified mask and type. Targets can specify exactly which masks they
312 /// support and the code generator is tasked with not creating illegal masks.
314 /// Note that this will also return true for shuffles that are promoted to a
316 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
317 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
319 case TargetLowering::Legal:
320 case TargetLowering::Custom:
322 case TargetLowering::Promote: {
323 // If this is promoted to a different type, convert the shuffle mask and
324 // ask if it is legal in the promoted type!
325 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
326 MVT EltVT = NVT.getVectorElementType();
328 // If we changed # elements, change the shuffle mask.
329 unsigned NumEltsGrowth =
330 NVT.getVectorNumElements() / VT.getVectorNumElements();
331 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
332 if (NumEltsGrowth > 1) {
333 // Renumber the elements.
334 SmallVector<SDValue, 8> Ops;
335 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
336 SDValue InOp = Mask.getOperand(i);
337 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
338 if (InOp.getOpcode() == ISD::UNDEF)
339 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
341 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
342 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
346 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
352 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
355 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, bool types)
356 : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types),
357 ValueTypeActions(TLI.getValueTypeActions()) {
358 assert(MVT::LAST_VALUETYPE <= 32 &&
359 "Too many value types for ValueTypeActions to hold!");
362 void SelectionDAGLegalize::LegalizeDAG() {
363 LastCALLSEQ_END = DAG.getEntryNode();
364 IsLegalizingCall = false;
366 // The legalize process is inherently a bottom-up recursive process (users
367 // legalize their uses before themselves). Given infinite stack space, we
368 // could just start legalizing on the root and traverse the whole graph. In
369 // practice however, this causes us to run out of stack space on large basic
370 // blocks. To avoid this problem, compute an ordering of the nodes where each
371 // node is only legalized after all of its operands are legalized.
372 DAG.AssignTopologicalOrder();
373 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
374 E = prior(DAG.allnodes_end()); I != next(E); ++I)
375 HandleOp(SDValue(I, 0));
377 // Finally, it's possible the root changed. Get the new root.
378 SDValue OldRoot = DAG.getRoot();
379 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
380 DAG.setRoot(LegalizedNodes[OldRoot]);
382 ExpandedNodes.clear();
383 LegalizedNodes.clear();
384 PromotedNodes.clear();
386 ScalarizedNodes.clear();
389 // Remove dead nodes now.
390 DAG.RemoveDeadNodes();
394 /// FindCallEndFromCallStart - Given a chained node that is part of a call
395 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
396 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
397 if (Node->getOpcode() == ISD::CALLSEQ_END)
399 if (Node->use_empty())
400 return 0; // No CallSeqEnd
402 // The chain is usually at the end.
403 SDValue TheChain(Node, Node->getNumValues()-1);
404 if (TheChain.getValueType() != MVT::Other) {
405 // Sometimes it's at the beginning.
406 TheChain = SDValue(Node, 0);
407 if (TheChain.getValueType() != MVT::Other) {
408 // Otherwise, hunt for it.
409 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
410 if (Node->getValueType(i) == MVT::Other) {
411 TheChain = SDValue(Node, i);
415 // Otherwise, we walked into a node without a chain.
416 if (TheChain.getValueType() != MVT::Other)
421 for (SDNode::use_iterator UI = Node->use_begin(),
422 E = Node->use_end(); UI != E; ++UI) {
424 // Make sure to only follow users of our token chain.
426 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
427 if (User->getOperand(i) == TheChain)
428 if (SDNode *Result = FindCallEndFromCallStart(User))
434 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
435 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
436 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
437 assert(Node && "Didn't find callseq_start for a call??");
438 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
440 assert(Node->getOperand(0).getValueType() == MVT::Other &&
441 "Node doesn't have a token chain argument!");
442 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
445 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
446 /// see if any uses can reach Dest. If no dest operands can get to dest,
447 /// legalize them, legalize ourself, and return false, otherwise, return true.
449 /// Keep track of the nodes we fine that actually do lead to Dest in
450 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
452 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
453 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
454 if (N == Dest) return true; // N certainly leads to Dest :)
456 // If we've already processed this node and it does lead to Dest, there is no
457 // need to reprocess it.
458 if (NodesLeadingTo.count(N)) return true;
460 // If the first result of this node has been already legalized, then it cannot
462 switch (getTypeAction(N->getValueType(0))) {
464 if (LegalizedNodes.count(SDValue(N, 0))) return false;
467 if (PromotedNodes.count(SDValue(N, 0))) return false;
470 if (ExpandedNodes.count(SDValue(N, 0))) return false;
474 // Okay, this node has not already been legalized. Check and legalize all
475 // operands. If none lead to Dest, then we can legalize this node.
476 bool OperandsLeadToDest = false;
477 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
478 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
479 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
481 if (OperandsLeadToDest) {
482 NodesLeadingTo.insert(N);
486 // Okay, this node looks safe, legalize it and return false.
487 HandleOp(SDValue(N, 0));
491 /// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as
492 /// appropriate for its type.
493 void SelectionDAGLegalize::HandleOp(SDValue Op) {
494 MVT VT = Op.getValueType();
495 // If the type legalizer was run then we should never see any illegal result
496 // types here except for target constants (the type legalizer does not touch
497 // those) or for build vector used as a mask for a vector shuffle.
498 // FIXME: We can removed the BUILD_VECTOR case when we fix PR2957.
499 assert((TypesNeedLegalizing || getTypeAction(VT) == Legal ||
500 Op.getOpcode() == ISD::TargetConstant ||
501 Op.getOpcode() == ISD::BUILD_VECTOR) &&
502 "Illegal type introduced after type legalization?");
503 switch (getTypeAction(VT)) {
504 default: assert(0 && "Bad type action!");
505 case Legal: (void)LegalizeOp(Op); break;
507 if (!VT.isVector()) {
512 // See if we can widen otherwise use Expand to either scalarize or split
513 MVT WidenVT = TLI.getWidenVectorType(VT);
514 if (WidenVT != MVT::Other) {
515 (void) WidenVectorOp(Op, WidenVT);
518 // else fall thru to expand since we can't widen the vector
521 if (!VT.isVector()) {
522 // If this is an illegal scalar, expand it into its two component
525 if (Op.getOpcode() == ISD::TargetConstant)
526 break; // Allow illegal target nodes.
528 } else if (VT.getVectorNumElements() == 1) {
529 // If this is an illegal single element vector, convert it to a
531 (void)ScalarizeVectorOp(Op);
533 // This is an illegal multiple element vector.
534 // Split it in half and legalize both parts.
536 SplitVectorOp(Op, X, Y);
542 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
543 /// a load from the constant pool.
544 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
545 SelectionDAG &DAG, const TargetLowering &TLI) {
548 // If a FP immediate is precise when represented as a float and if the
549 // target can do an extending load from float to double, we put it into
550 // the constant pool as a float, even if it's is statically typed as a
551 // double. This shrinks FP constants and canonicalizes them for targets where
552 // an FP extending load is the same cost as a normal load (such as on the x87
553 // fp stack or PPC FP unit).
554 MVT VT = CFP->getValueType(0);
555 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
557 if (VT!=MVT::f64 && VT!=MVT::f32)
558 assert(0 && "Invalid type expansion");
559 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
560 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
565 while (SVT != MVT::f32) {
566 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
567 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
568 // Only do this if the target has a native EXTLOAD instruction from
570 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
571 TLI.ShouldShrinkFPConstant(OrigVT)) {
572 const Type *SType = SVT.getTypeForMVT();
573 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
579 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
580 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
582 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
583 CPIdx, PseudoSourceValue::getConstantPool(),
584 0, VT, false, Alignment);
585 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
586 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
590 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
593 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
595 const TargetLowering &TLI) {
596 MVT VT = Node->getValueType(0);
597 MVT SrcVT = Node->getOperand(1).getValueType();
598 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
599 "fcopysign expansion only supported for f32 and f64");
600 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
602 // First get the sign bit of second operand.
603 SDValue Mask1 = (SrcVT == MVT::f64)
604 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
605 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
606 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
607 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
608 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
609 // Shift right or sign-extend it if the two operands have different types.
610 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
612 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
613 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
614 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
615 } else if (SizeDiff < 0) {
616 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
617 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
618 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
621 // Clear the sign bit of first operand.
622 SDValue Mask2 = (VT == MVT::f64)
623 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
624 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
625 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
626 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
627 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
629 // Or the value with the sign bit.
630 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
634 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
636 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
637 const TargetLowering &TLI) {
638 SDValue Chain = ST->getChain();
639 SDValue Ptr = ST->getBasePtr();
640 SDValue Val = ST->getValue();
641 MVT VT = Val.getValueType();
642 int Alignment = ST->getAlignment();
643 int SVOffset = ST->getSrcValueOffset();
644 if (ST->getMemoryVT().isFloatingPoint() ||
645 ST->getMemoryVT().isVector()) {
646 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
647 if (TLI.isTypeLegal(intVT)) {
648 // Expand to a bitconvert of the value to the integer type of the
649 // same size, then a (misaligned) int store.
650 // FIXME: Does not handle truncating floating point stores!
651 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
652 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
653 SVOffset, ST->isVolatile(), Alignment);
655 // Do a (aligned) store to a stack slot, then copy from the stack slot
656 // to the final destination using (unaligned) integer loads and stores.
657 MVT StoredVT = ST->getMemoryVT();
659 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
660 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
661 unsigned RegBytes = RegVT.getSizeInBits() / 8;
662 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
664 // Make sure the stack slot is also aligned for the register type.
665 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
667 // Perform the original store, only redirected to the stack slot.
668 SDValue Store = DAG.getTruncStore(Chain, Val, StackPtr, NULL, 0,StoredVT);
669 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
670 SmallVector<SDValue, 8> Stores;
673 // Do all but one copies using the full register width.
674 for (unsigned i = 1; i < NumRegs; i++) {
675 // Load one integer register's worth from the stack slot.
676 SDValue Load = DAG.getLoad(RegVT, Store, StackPtr, NULL, 0);
677 // Store it to the final location. Remember the store.
678 Stores.push_back(DAG.getStore(Load.getValue(1), Load, Ptr,
679 ST->getSrcValue(), SVOffset + Offset,
681 MinAlign(ST->getAlignment(), Offset)));
682 // Increment the pointers.
684 StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr,
686 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, Increment);
689 // The last store may be partial. Do a truncating store. On big-endian
690 // machines this requires an extending load from the stack slot to ensure
691 // that the bits are in the right place.
692 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
694 // Load from the stack slot.
695 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, Store, StackPtr,
698 Stores.push_back(DAG.getTruncStore(Load.getValue(1), Load, Ptr,
699 ST->getSrcValue(), SVOffset + Offset,
700 MemVT, ST->isVolatile(),
701 MinAlign(ST->getAlignment(), Offset)));
702 // The order of the stores doesn't matter - say it with a TokenFactor.
703 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],
707 assert(ST->getMemoryVT().isInteger() &&
708 !ST->getMemoryVT().isVector() &&
709 "Unaligned store of unknown type.");
710 // Get the half-size VT
712 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
713 int NumBits = NewStoredVT.getSizeInBits();
714 int IncrementSize = NumBits / 8;
716 // Divide the stored value in two parts.
717 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
719 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
721 // Store the two parts
722 SDValue Store1, Store2;
723 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
724 ST->getSrcValue(), SVOffset, NewStoredVT,
725 ST->isVolatile(), Alignment);
726 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
727 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
728 Alignment = MinAlign(Alignment, IncrementSize);
729 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
730 ST->getSrcValue(), SVOffset + IncrementSize,
731 NewStoredVT, ST->isVolatile(), Alignment);
733 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
736 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
738 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
739 const TargetLowering &TLI) {
740 int SVOffset = LD->getSrcValueOffset();
741 SDValue Chain = LD->getChain();
742 SDValue Ptr = LD->getBasePtr();
743 MVT VT = LD->getValueType(0);
744 MVT LoadedVT = LD->getMemoryVT();
745 if (VT.isFloatingPoint() || VT.isVector()) {
746 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
747 if (TLI.isTypeLegal(intVT)) {
748 // Expand to a (misaligned) integer load of the same size,
749 // then bitconvert to floating point or vector.
750 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
751 SVOffset, LD->isVolatile(),
753 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
754 if (VT.isFloatingPoint() && LoadedVT != VT)
755 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
757 SDValue Ops[] = { Result, Chain };
758 return DAG.getMergeValues(Ops, 2);
760 // Copy the value to a (aligned) stack slot using (unaligned) integer
761 // loads and stores, then do a (aligned) load from the stack slot.
762 MVT RegVT = TLI.getRegisterType(intVT);
763 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
764 unsigned RegBytes = RegVT.getSizeInBits() / 8;
765 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
767 // Make sure the stack slot is also aligned for the register type.
768 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
770 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
771 SmallVector<SDValue, 8> Stores;
772 SDValue StackPtr = StackBase;
775 // Do all but one copies using the full register width.
776 for (unsigned i = 1; i < NumRegs; i++) {
777 // Load one integer register's worth from the original location.
778 SDValue Load = DAG.getLoad(RegVT, Chain, Ptr, LD->getSrcValue(),
779 SVOffset + Offset, LD->isVolatile(),
780 MinAlign(LD->getAlignment(), Offset));
781 // Follow the load with a store to the stack slot. Remember the store.
782 Stores.push_back(DAG.getStore(Load.getValue(1), Load, StackPtr,
784 // Increment the pointers.
786 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, Increment);
787 StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr,
791 // The last copy may be partial. Do an extending load.
792 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
793 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, Chain, Ptr,
794 LD->getSrcValue(), SVOffset + Offset,
795 MemVT, LD->isVolatile(),
796 MinAlign(LD->getAlignment(), Offset));
797 // Follow the load with a store to the stack slot. Remember the store.
798 // On big-endian machines this requires a truncating store to ensure
799 // that the bits end up in the right place.
800 Stores.push_back(DAG.getTruncStore(Load.getValue(1), Load, StackPtr,
803 // The order of the stores doesn't matter - say it with a TokenFactor.
804 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],
807 // Finally, perform the original load only redirected to the stack slot.
808 Load = DAG.getExtLoad(LD->getExtensionType(), VT, TF, StackBase,
811 // Callers expect a MERGE_VALUES node.
812 SDValue Ops[] = { Load, TF };
813 return DAG.getMergeValues(Ops, 2);
816 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
817 "Unaligned load of unsupported type.");
819 // Compute the new VT that is half the size of the old one. This is an
821 unsigned NumBits = LoadedVT.getSizeInBits();
823 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
826 unsigned Alignment = LD->getAlignment();
827 unsigned IncrementSize = NumBits / 8;
828 ISD::LoadExtType HiExtType = LD->getExtensionType();
830 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
831 if (HiExtType == ISD::NON_EXTLOAD)
832 HiExtType = ISD::ZEXTLOAD;
834 // Load the value in two parts
836 if (TLI.isLittleEndian()) {
837 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
838 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
839 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
840 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
841 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
842 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
843 MinAlign(Alignment, IncrementSize));
845 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
846 NewLoadedVT,LD->isVolatile(), Alignment);
847 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
848 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
849 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
850 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
851 MinAlign(Alignment, IncrementSize));
854 // aggregate the two parts
855 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
856 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
857 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
859 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
862 SDValue Ops[] = { Result, TF };
863 return DAG.getMergeValues(Ops, 2);
866 /// UnrollVectorOp - We know that the given vector has a legal type, however
867 /// the operation it performs is not legal and is an operation that we have
868 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
869 /// operating on each element individually.
870 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
871 MVT VT = Op.getValueType();
872 assert(isTypeLegal(VT) &&
873 "Caller should expand or promote operands that are not legal!");
874 assert(Op.getNode()->getNumValues() == 1 &&
875 "Can't unroll a vector with multiple results!");
876 unsigned NE = VT.getVectorNumElements();
877 MVT EltVT = VT.getVectorElementType();
879 SmallVector<SDValue, 8> Scalars;
880 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
881 for (unsigned i = 0; i != NE; ++i) {
882 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
883 SDValue Operand = Op.getOperand(j);
884 MVT OperandVT = Operand.getValueType();
885 if (OperandVT.isVector()) {
886 // A vector operand; extract a single element.
887 MVT OperandEltVT = OperandVT.getVectorElementType();
888 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
891 DAG.getConstant(i, MVT::i32));
893 // A scalar operand; just use it as is.
894 Operands[j] = Operand;
898 switch (Op.getOpcode()) {
900 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
901 &Operands[0], Operands.size()));
906 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, Operands[0],
907 LegalizeShiftAmount(Operands[1])));
912 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
915 /// GetFPLibCall - Return the right libcall for the given floating point type.
916 static RTLIB::Libcall GetFPLibCall(MVT VT,
917 RTLIB::Libcall Call_F32,
918 RTLIB::Libcall Call_F64,
919 RTLIB::Libcall Call_F80,
920 RTLIB::Libcall Call_PPCF128) {
922 VT == MVT::f32 ? Call_F32 :
923 VT == MVT::f64 ? Call_F64 :
924 VT == MVT::f80 ? Call_F80 :
925 VT == MVT::ppcf128 ? Call_PPCF128 :
926 RTLIB::UNKNOWN_LIBCALL;
929 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
930 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
931 /// is necessary to spill the vector being inserted into to memory, perform
932 /// the insert there, and then read the result back.
933 SDValue SelectionDAGLegalize::
934 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) {
939 // If the target doesn't support this, we have to spill the input vector
940 // to a temporary stack slot, update the element, then reload it. This is
941 // badness. We could also load the value into a vector register (either
942 // with a "move to register" or "extload into register" instruction, then
943 // permute it into place, if the idx is a constant and if the idx is
944 // supported by the target.
945 MVT VT = Tmp1.getValueType();
946 MVT EltVT = VT.getVectorElementType();
947 MVT IdxVT = Tmp3.getValueType();
948 MVT PtrVT = TLI.getPointerTy();
949 SDValue StackPtr = DAG.CreateStackTemporary(VT);
951 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
954 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
955 PseudoSourceValue::getFixedStack(SPFI), 0);
957 // Truncate or zero extend offset to target pointer type.
958 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
959 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
960 // Add the offset to the index.
961 unsigned EltSize = EltVT.getSizeInBits()/8;
962 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
963 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
964 // Store the scalar value.
965 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
966 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
967 // Load the updated vector.
968 return DAG.getLoad(VT, Ch, StackPtr,
969 PseudoSourceValue::getFixedStack(SPFI), 0);
972 SDValue SelectionDAGLegalize::LegalizeShiftAmount(SDValue ShiftAmt) {
973 if (TLI.getShiftAmountTy().bitsLT(ShiftAmt.getValueType()))
974 return DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt);
976 if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType()))
977 return DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt);
983 /// LegalizeOp - We know that the specified value has a legal type, and
984 /// that its operands are legal. Now ensure that the operation itself
985 /// is legal, recursively ensuring that the operands' operations remain
987 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
988 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
991 assert(isTypeLegal(Op.getValueType()) &&
992 "Caller should expand or promote operands that are not legal!");
993 SDNode *Node = Op.getNode();
995 // If this operation defines any values that cannot be represented in a
996 // register on this target, make sure to expand or promote them.
997 if (Node->getNumValues() > 1) {
998 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
999 if (getTypeAction(Node->getValueType(i)) != Legal) {
1000 HandleOp(Op.getValue(i));
1001 assert(LegalizedNodes.count(Op) &&
1002 "Handling didn't add legal operands!");
1003 return LegalizedNodes[Op];
1007 // Note that LegalizeOp may be reentered even from single-use nodes, which
1008 // means that we always must cache transformed nodes.
1009 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1010 if (I != LegalizedNodes.end()) return I->second;
1012 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
1013 SDValue Result = Op;
1014 bool isCustom = false;
1016 switch (Node->getOpcode()) {
1017 case ISD::FrameIndex:
1018 case ISD::EntryToken:
1020 case ISD::BasicBlock:
1021 case ISD::TargetFrameIndex:
1022 case ISD::TargetJumpTable:
1023 case ISD::TargetConstant:
1024 case ISD::TargetConstantFP:
1025 case ISD::TargetConstantPool:
1026 case ISD::TargetGlobalAddress:
1027 case ISD::TargetGlobalTLSAddress:
1028 case ISD::TargetExternalSymbol:
1029 case ISD::VALUETYPE:
1031 case ISD::MEMOPERAND:
1033 case ISD::ARG_FLAGS:
1034 // Primitives must all be legal.
1035 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
1036 "This must be legal!");
1039 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1040 // If this is a target node, legalize it by legalizing the operands then
1041 // passing it through.
1042 SmallVector<SDValue, 8> Ops;
1043 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1044 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1046 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
1048 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1049 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
1050 return Result.getValue(Op.getResNo());
1052 // Otherwise this is an unhandled builtin node. splat.
1054 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
1056 assert(0 && "Do not know how to legalize this operator!");
1058 case ISD::GLOBAL_OFFSET_TABLE:
1059 case ISD::GlobalAddress:
1060 case ISD::GlobalTLSAddress:
1061 case ISD::ExternalSymbol:
1062 case ISD::ConstantPool:
1063 case ISD::JumpTable: // Nothing to do.
1064 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1065 default: assert(0 && "This action is not supported yet!");
1066 case TargetLowering::Custom:
1067 Tmp1 = TLI.LowerOperation(Op, DAG);
1068 if (Tmp1.getNode()) Result = Tmp1;
1069 // FALLTHROUGH if the target doesn't want to lower this op after all.
1070 case TargetLowering::Legal:
1074 case ISD::FRAMEADDR:
1075 case ISD::RETURNADDR:
1076 // The only option for these nodes is to custom lower them. If the target
1077 // does not custom lower them, then return zero.
1078 Tmp1 = TLI.LowerOperation(Op, DAG);
1082 Result = DAG.getConstant(0, TLI.getPointerTy());
1084 case ISD::FRAME_TO_ARGS_OFFSET: {
1085 MVT VT = Node->getValueType(0);
1086 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1087 default: assert(0 && "This action is not supported yet!");
1088 case TargetLowering::Custom:
1089 Result = TLI.LowerOperation(Op, DAG);
1090 if (Result.getNode()) break;
1092 case TargetLowering::Legal:
1093 Result = DAG.getConstant(0, VT);
1098 case ISD::EXCEPTIONADDR: {
1099 Tmp1 = LegalizeOp(Node->getOperand(0));
1100 MVT VT = Node->getValueType(0);
1101 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1102 default: assert(0 && "This action is not supported yet!");
1103 case TargetLowering::Expand: {
1104 unsigned Reg = TLI.getExceptionAddressRegister();
1105 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
1108 case TargetLowering::Custom:
1109 Result = TLI.LowerOperation(Op, DAG);
1110 if (Result.getNode()) break;
1112 case TargetLowering::Legal: {
1113 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
1114 Result = DAG.getMergeValues(Ops, 2);
1119 if (Result.getNode()->getNumValues() == 1) break;
1121 assert(Result.getNode()->getNumValues() == 2 &&
1122 "Cannot return more than two values!");
1124 // Since we produced two values, make sure to remember that we
1125 // legalized both of them.
1126 Tmp1 = LegalizeOp(Result);
1127 Tmp2 = LegalizeOp(Result.getValue(1));
1128 AddLegalizedOperand(Op.getValue(0), Tmp1);
1129 AddLegalizedOperand(Op.getValue(1), Tmp2);
1130 return Op.getResNo() ? Tmp2 : Tmp1;
1131 case ISD::EHSELECTION: {
1132 Tmp1 = LegalizeOp(Node->getOperand(0));
1133 Tmp2 = LegalizeOp(Node->getOperand(1));
1134 MVT VT = Node->getValueType(0);
1135 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1136 default: assert(0 && "This action is not supported yet!");
1137 case TargetLowering::Expand: {
1138 unsigned Reg = TLI.getExceptionSelectorRegister();
1139 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
1142 case TargetLowering::Custom:
1143 Result = TLI.LowerOperation(Op, DAG);
1144 if (Result.getNode()) break;
1146 case TargetLowering::Legal: {
1147 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
1148 Result = DAG.getMergeValues(Ops, 2);
1153 if (Result.getNode()->getNumValues() == 1) break;
1155 assert(Result.getNode()->getNumValues() == 2 &&
1156 "Cannot return more than two values!");
1158 // Since we produced two values, make sure to remember that we
1159 // legalized both of them.
1160 Tmp1 = LegalizeOp(Result);
1161 Tmp2 = LegalizeOp(Result.getValue(1));
1162 AddLegalizedOperand(Op.getValue(0), Tmp1);
1163 AddLegalizedOperand(Op.getValue(1), Tmp2);
1164 return Op.getResNo() ? Tmp2 : Tmp1;
1165 case ISD::EH_RETURN: {
1166 MVT VT = Node->getValueType(0);
1167 // The only "good" option for this node is to custom lower it.
1168 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1169 default: assert(0 && "This action is not supported at all!");
1170 case TargetLowering::Custom:
1171 Result = TLI.LowerOperation(Op, DAG);
1172 if (Result.getNode()) break;
1174 case TargetLowering::Legal:
1175 // Target does not know, how to lower this, lower to noop
1176 Result = LegalizeOp(Node->getOperand(0));
1181 case ISD::AssertSext:
1182 case ISD::AssertZext:
1183 Tmp1 = LegalizeOp(Node->getOperand(0));
1184 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1186 case ISD::MERGE_VALUES:
1187 // Legalize eliminates MERGE_VALUES nodes.
1188 Result = Node->getOperand(Op.getResNo());
1190 case ISD::CopyFromReg:
1191 Tmp1 = LegalizeOp(Node->getOperand(0));
1192 Result = Op.getValue(0);
1193 if (Node->getNumValues() == 2) {
1194 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1196 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1197 if (Node->getNumOperands() == 3) {
1198 Tmp2 = LegalizeOp(Node->getOperand(2));
1199 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1201 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1203 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1205 // Since CopyFromReg produces two values, make sure to remember that we
1206 // legalized both of them.
1207 AddLegalizedOperand(Op.getValue(0), Result);
1208 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1209 return Result.getValue(Op.getResNo());
1211 MVT VT = Op.getValueType();
1212 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1213 default: assert(0 && "This action is not supported yet!");
1214 case TargetLowering::Expand:
1216 Result = DAG.getConstant(0, VT);
1217 else if (VT.isFloatingPoint())
1218 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1221 assert(0 && "Unknown value type!");
1223 case TargetLowering::Legal:
1229 case ISD::INTRINSIC_W_CHAIN:
1230 case ISD::INTRINSIC_WO_CHAIN:
1231 case ISD::INTRINSIC_VOID: {
1232 SmallVector<SDValue, 8> Ops;
1233 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1234 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1235 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1237 // Allow the target to custom lower its intrinsics if it wants to.
1238 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1239 TargetLowering::Custom) {
1240 Tmp3 = TLI.LowerOperation(Result, DAG);
1241 if (Tmp3.getNode()) Result = Tmp3;
1244 if (Result.getNode()->getNumValues() == 1) break;
1246 // Must have return value and chain result.
1247 assert(Result.getNode()->getNumValues() == 2 &&
1248 "Cannot return more than two values!");
1250 // Since loads produce two values, make sure to remember that we
1251 // legalized both of them.
1252 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1253 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1254 return Result.getValue(Op.getResNo());
1257 case ISD::DBG_STOPPOINT:
1258 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1259 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1261 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1262 case TargetLowering::Promote:
1263 default: assert(0 && "This action is not supported yet!");
1264 case TargetLowering::Expand: {
1265 DwarfWriter *DW = DAG.getDwarfWriter();
1266 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1267 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
1269 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1270 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
1271 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) {
1272 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit()));
1273 unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
1276 unsigned Line = DSP->getLine();
1277 unsigned Col = DSP->getColumn();
1280 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1281 DAG.getConstant(Col, MVT::i32),
1282 DAG.getConstant(SrcFile, MVT::i32) };
1283 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
1285 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile);
1286 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1289 Result = Tmp1; // chain
1293 case TargetLowering::Legal: {
1294 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1295 if (Action == Legal && Tmp1 == Node->getOperand(0))
1298 SmallVector<SDValue, 8> Ops;
1299 Ops.push_back(Tmp1);
1300 if (Action == Legal) {
1301 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1302 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1304 // Otherwise promote them.
1305 Ops.push_back(PromoteOp(Node->getOperand(1)));
1306 Ops.push_back(PromoteOp(Node->getOperand(2)));
1308 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1309 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1310 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1317 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1318 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1319 default: assert(0 && "This action is not supported yet!");
1320 case TargetLowering::Legal:
1321 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1322 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1323 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1324 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1326 case TargetLowering::Expand:
1327 Result = LegalizeOp(Node->getOperand(0));
1332 case ISD::DEBUG_LOC:
1333 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1334 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1335 default: assert(0 && "This action is not supported yet!");
1336 case TargetLowering::Legal: {
1337 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1338 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1339 if (Action == Legal && Tmp1 == Node->getOperand(0))
1341 if (Action == Legal) {
1342 Tmp2 = Node->getOperand(1);
1343 Tmp3 = Node->getOperand(2);
1344 Tmp4 = Node->getOperand(3);
1346 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1347 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1348 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1350 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1356 case ISD::DBG_LABEL:
1358 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1359 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1360 default: assert(0 && "This action is not supported yet!");
1361 case TargetLowering::Legal:
1362 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1363 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1365 case TargetLowering::Expand:
1366 Result = LegalizeOp(Node->getOperand(0));
1372 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1373 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1374 default: assert(0 && "This action is not supported yet!");
1375 case TargetLowering::Legal:
1376 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1377 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1378 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1379 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1380 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1382 case TargetLowering::Expand:
1384 Result = LegalizeOp(Node->getOperand(0));
1389 case ISD::MEMBARRIER: {
1390 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1391 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1392 default: assert(0 && "This action is not supported yet!");
1393 case TargetLowering::Legal: {
1395 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1396 for (int x = 1; x < 6; ++x) {
1397 Ops[x] = Node->getOperand(x);
1398 if (!isTypeLegal(Ops[x].getValueType()))
1399 Ops[x] = PromoteOp(Ops[x]);
1401 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1404 case TargetLowering::Expand:
1405 //There is no libgcc call for this op
1406 Result = Node->getOperand(0); // Noop
1412 case ISD::ATOMIC_CMP_SWAP: {
1413 unsigned int num_operands = 4;
1414 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1416 for (unsigned int x = 0; x < num_operands; ++x)
1417 Ops[x] = LegalizeOp(Node->getOperand(x));
1418 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1420 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1421 default: assert(0 && "This action is not supported yet!");
1422 case TargetLowering::Custom:
1423 Result = TLI.LowerOperation(Result, DAG);
1425 case TargetLowering::Legal:
1428 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1429 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1430 return Result.getValue(Op.getResNo());
1432 case ISD::ATOMIC_LOAD_ADD:
1433 case ISD::ATOMIC_LOAD_SUB:
1434 case ISD::ATOMIC_LOAD_AND:
1435 case ISD::ATOMIC_LOAD_OR:
1436 case ISD::ATOMIC_LOAD_XOR:
1437 case ISD::ATOMIC_LOAD_NAND:
1438 case ISD::ATOMIC_LOAD_MIN:
1439 case ISD::ATOMIC_LOAD_MAX:
1440 case ISD::ATOMIC_LOAD_UMIN:
1441 case ISD::ATOMIC_LOAD_UMAX:
1442 case ISD::ATOMIC_SWAP: {
1443 unsigned int num_operands = 3;
1444 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1446 for (unsigned int x = 0; x < num_operands; ++x)
1447 Ops[x] = LegalizeOp(Node->getOperand(x));
1448 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1450 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1451 default: assert(0 && "This action is not supported yet!");
1452 case TargetLowering::Custom:
1453 Result = TLI.LowerOperation(Result, DAG);
1455 case TargetLowering::Legal:
1458 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1459 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1460 return Result.getValue(Op.getResNo());
1462 case ISD::Constant: {
1463 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1465 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1467 // We know we don't need to expand constants here, constants only have one
1468 // value and we check that it is fine above.
1470 if (opAction == TargetLowering::Custom) {
1471 Tmp1 = TLI.LowerOperation(Result, DAG);
1477 case ISD::ConstantFP: {
1478 // Spill FP immediates to the constant pool if the target cannot directly
1479 // codegen them. Targets often have some immediate values that can be
1480 // efficiently generated into an FP register without a load. We explicitly
1481 // leave these constants as ConstantFP nodes for the target to deal with.
1482 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1484 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1485 default: assert(0 && "This action is not supported yet!");
1486 case TargetLowering::Legal:
1488 case TargetLowering::Custom:
1489 Tmp3 = TLI.LowerOperation(Result, DAG);
1490 if (Tmp3.getNode()) {
1495 case TargetLowering::Expand: {
1496 // Check to see if this FP immediate is already legal.
1497 bool isLegal = false;
1498 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1499 E = TLI.legal_fpimm_end(); I != E; ++I) {
1500 if (CFP->isExactlyValue(*I)) {
1505 // If this is a legal constant, turn it into a TargetConstantFP node.
1508 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1513 case ISD::TokenFactor:
1514 if (Node->getNumOperands() == 2) {
1515 Tmp1 = LegalizeOp(Node->getOperand(0));
1516 Tmp2 = LegalizeOp(Node->getOperand(1));
1517 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1518 } else if (Node->getNumOperands() == 3) {
1519 Tmp1 = LegalizeOp(Node->getOperand(0));
1520 Tmp2 = LegalizeOp(Node->getOperand(1));
1521 Tmp3 = LegalizeOp(Node->getOperand(2));
1522 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1524 SmallVector<SDValue, 8> Ops;
1525 // Legalize the operands.
1526 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1527 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1528 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1532 case ISD::FORMAL_ARGUMENTS:
1534 // The only option for this is to custom lower it.
1535 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1536 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1537 // A call within a calling sequence must be legalized to something
1538 // other than the normal CALLSEQ_END. Violating this gets Legalize
1539 // into an infinite loop.
1540 assert ((!IsLegalizingCall ||
1541 Node->getOpcode() != ISD::CALL ||
1542 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1543 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1545 // The number of incoming and outgoing values should match; unless the final
1546 // outgoing value is a flag.
1547 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1548 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1549 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1551 "Lowering call/formal_arguments produced unexpected # results!");
1553 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1554 // remember that we legalized all of them, so it doesn't get relegalized.
1555 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1556 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1558 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1559 if (Op.getResNo() == i)
1561 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1564 case ISD::EXTRACT_SUBREG: {
1565 Tmp1 = LegalizeOp(Node->getOperand(0));
1566 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1567 assert(idx && "Operand must be a constant");
1568 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1569 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1572 case ISD::INSERT_SUBREG: {
1573 Tmp1 = LegalizeOp(Node->getOperand(0));
1574 Tmp2 = LegalizeOp(Node->getOperand(1));
1575 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1576 assert(idx && "Operand must be a constant");
1577 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1578 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1581 case ISD::BUILD_VECTOR:
1582 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1583 default: assert(0 && "This action is not supported yet!");
1584 case TargetLowering::Custom:
1585 Tmp3 = TLI.LowerOperation(Result, DAG);
1586 if (Tmp3.getNode()) {
1591 case TargetLowering::Expand:
1592 Result = ExpandBUILD_VECTOR(Result.getNode());
1596 case ISD::INSERT_VECTOR_ELT:
1597 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1598 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1600 // The type of the value to insert may not be legal, even though the vector
1601 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1603 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1604 default: assert(0 && "Cannot expand insert element operand");
1605 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1606 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1608 // FIXME: An alternative would be to check to see if the target is not
1609 // going to custom lower this operation, we could bitcast to half elt
1610 // width and perform two inserts at that width, if that is legal.
1611 Tmp2 = Node->getOperand(1);
1614 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1616 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1617 Node->getValueType(0))) {
1618 default: assert(0 && "This action is not supported yet!");
1619 case TargetLowering::Legal:
1621 case TargetLowering::Custom:
1622 Tmp4 = TLI.LowerOperation(Result, DAG);
1623 if (Tmp4.getNode()) {
1628 case TargetLowering::Promote:
1629 // Fall thru for vector case
1630 case TargetLowering::Expand: {
1631 // If the insert index is a constant, codegen this as a scalar_to_vector,
1632 // then a shuffle that inserts it into the right position in the vector.
1633 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1634 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1635 // match the element type of the vector being created.
1636 if (Tmp2.getValueType() ==
1637 Op.getValueType().getVectorElementType()) {
1638 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1639 Tmp1.getValueType(), Tmp2);
1641 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1643 MVT::getIntVectorWithNumElements(NumElts);
1644 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1646 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1647 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1648 // elt 0 of the RHS.
1649 SmallVector<SDValue, 8> ShufOps;
1650 for (unsigned i = 0; i != NumElts; ++i) {
1651 if (i != InsertPos->getZExtValue())
1652 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1654 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1656 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1657 &ShufOps[0], ShufOps.size());
1659 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1660 Tmp1, ScVec, ShufMask);
1661 Result = LegalizeOp(Result);
1665 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1670 case ISD::SCALAR_TO_VECTOR:
1671 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1672 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1676 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1677 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1678 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1679 Node->getValueType(0))) {
1680 default: assert(0 && "This action is not supported yet!");
1681 case TargetLowering::Legal:
1683 case TargetLowering::Custom:
1684 Tmp3 = TLI.LowerOperation(Result, DAG);
1685 if (Tmp3.getNode()) {
1690 case TargetLowering::Expand:
1691 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1695 case ISD::VECTOR_SHUFFLE:
1696 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1697 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1698 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1700 // Allow targets to custom lower the SHUFFLEs they support.
1701 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1702 default: assert(0 && "Unknown operation action!");
1703 case TargetLowering::Legal:
1704 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1705 "vector shuffle should not be created if not legal!");
1707 case TargetLowering::Custom:
1708 Tmp3 = TLI.LowerOperation(Result, DAG);
1709 if (Tmp3.getNode()) {
1714 case TargetLowering::Expand: {
1715 MVT VT = Node->getValueType(0);
1716 MVT EltVT = VT.getVectorElementType();
1717 MVT PtrVT = TLI.getPointerTy();
1718 SDValue Mask = Node->getOperand(2);
1719 unsigned NumElems = Mask.getNumOperands();
1720 SmallVector<SDValue,8> Ops;
1721 for (unsigned i = 0; i != NumElems; ++i) {
1722 SDValue Arg = Mask.getOperand(i);
1723 if (Arg.getOpcode() == ISD::UNDEF) {
1724 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1726 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1727 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1729 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1730 DAG.getConstant(Idx, PtrVT)));
1732 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1733 DAG.getConstant(Idx - NumElems, PtrVT)));
1736 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1739 case TargetLowering::Promote: {
1740 // Change base type to a different vector type.
1741 MVT OVT = Node->getValueType(0);
1742 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1744 // Cast the two input vectors.
1745 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1746 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1748 // Convert the shuffle mask to the right # elements.
1749 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1750 assert(Tmp3.getNode() && "Shuffle not legal?");
1751 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1752 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1758 case ISD::EXTRACT_VECTOR_ELT:
1759 Tmp1 = Node->getOperand(0);
1760 Tmp2 = LegalizeOp(Node->getOperand(1));
1761 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1762 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1765 case ISD::EXTRACT_SUBVECTOR:
1766 Tmp1 = Node->getOperand(0);
1767 Tmp2 = LegalizeOp(Node->getOperand(1));
1768 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1769 Result = ExpandEXTRACT_SUBVECTOR(Result);
1772 case ISD::CONCAT_VECTORS: {
1773 // Use extract/insert/build vector for now. We might try to be
1774 // more clever later.
1775 MVT PtrVT = TLI.getPointerTy();
1776 SmallVector<SDValue, 8> Ops;
1777 unsigned NumOperands = Node->getNumOperands();
1778 for (unsigned i=0; i < NumOperands; ++i) {
1779 SDValue SubOp = Node->getOperand(i);
1780 MVT VVT = SubOp.getNode()->getValueType(0);
1781 MVT EltVT = VVT.getVectorElementType();
1782 unsigned NumSubElem = VVT.getVectorNumElements();
1783 for (unsigned j=0; j < NumSubElem; ++j) {
1784 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, SubOp,
1785 DAG.getConstant(j, PtrVT)));
1788 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
1789 &Ops[0], Ops.size()));
1792 case ISD::CALLSEQ_START: {
1793 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1795 // Recursively Legalize all of the inputs of the call end that do not lead
1796 // to this call start. This ensures that any libcalls that need be inserted
1797 // are inserted *before* the CALLSEQ_START.
1798 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1799 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1800 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1804 // Now that we legalized all of the inputs (which may have inserted
1805 // libcalls) create the new CALLSEQ_START node.
1806 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1808 // Merge in the last call, to ensure that this call start after the last
1810 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1811 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1812 Tmp1 = LegalizeOp(Tmp1);
1815 // Do not try to legalize the target-specific arguments (#1+).
1816 if (Tmp1 != Node->getOperand(0)) {
1817 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1819 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1822 // Remember that the CALLSEQ_START is legalized.
1823 AddLegalizedOperand(Op.getValue(0), Result);
1824 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1825 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1827 // Now that the callseq_start and all of the non-call nodes above this call
1828 // sequence have been legalized, legalize the call itself. During this
1829 // process, no libcalls can/will be inserted, guaranteeing that no calls
1831 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1832 // Note that we are selecting this call!
1833 LastCALLSEQ_END = SDValue(CallEnd, 0);
1834 IsLegalizingCall = true;
1836 // Legalize the call, starting from the CALLSEQ_END.
1837 LegalizeOp(LastCALLSEQ_END);
1838 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1841 case ISD::CALLSEQ_END:
1842 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1843 // will cause this node to be legalized as well as handling libcalls right.
1844 if (LastCALLSEQ_END.getNode() != Node) {
1845 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1846 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1847 assert(I != LegalizedNodes.end() &&
1848 "Legalizing the call start should have legalized this node!");
1852 // Otherwise, the call start has been legalized and everything is going
1853 // according to plan. Just legalize ourselves normally here.
1854 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1855 // Do not try to legalize the target-specific arguments (#1+), except for
1856 // an optional flag input.
1857 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1858 if (Tmp1 != Node->getOperand(0)) {
1859 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1861 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1864 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1865 if (Tmp1 != Node->getOperand(0) ||
1866 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1867 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1870 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1873 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1874 // This finishes up call legalization.
1875 IsLegalizingCall = false;
1877 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1878 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1879 if (Node->getNumValues() == 2)
1880 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1881 return Result.getValue(Op.getResNo());
1882 case ISD::DYNAMIC_STACKALLOC: {
1883 MVT VT = Node->getValueType(0);
1884 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1885 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1886 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1887 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1889 Tmp1 = Result.getValue(0);
1890 Tmp2 = Result.getValue(1);
1891 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1892 default: assert(0 && "This action is not supported yet!");
1893 case TargetLowering::Expand: {
1894 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1895 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1896 " not tell us which reg is the stack pointer!");
1897 SDValue Chain = Tmp1.getOperand(0);
1899 // Chain the dynamic stack allocation so that it doesn't modify the stack
1900 // pointer when other instructions are using the stack.
1901 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1903 SDValue Size = Tmp2.getOperand(1);
1904 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1905 Chain = SP.getValue(1);
1906 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1907 unsigned StackAlign =
1908 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1909 if (Align > StackAlign)
1910 SP = DAG.getNode(ISD::AND, VT, SP,
1911 DAG.getConstant(-(uint64_t)Align, VT));
1912 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1913 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1915 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1916 DAG.getIntPtrConstant(0, true), SDValue());
1918 Tmp1 = LegalizeOp(Tmp1);
1919 Tmp2 = LegalizeOp(Tmp2);
1922 case TargetLowering::Custom:
1923 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1924 if (Tmp3.getNode()) {
1925 Tmp1 = LegalizeOp(Tmp3);
1926 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1929 case TargetLowering::Legal:
1932 // Since this op produce two values, make sure to remember that we
1933 // legalized both of them.
1934 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1935 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1936 return Op.getResNo() ? Tmp2 : Tmp1;
1938 case ISD::INLINEASM: {
1939 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1940 bool Changed = false;
1941 // Legalize all of the operands of the inline asm, in case they are nodes
1942 // that need to be expanded or something. Note we skip the asm string and
1943 // all of the TargetConstant flags.
1944 SDValue Op = LegalizeOp(Ops[0]);
1945 Changed = Op != Ops[0];
1948 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1949 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1950 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3;
1951 for (++i; NumVals; ++i, --NumVals) {
1952 SDValue Op = LegalizeOp(Ops[i]);
1961 Op = LegalizeOp(Ops.back());
1962 Changed |= Op != Ops.back();
1967 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1969 // INLINE asm returns a chain and flag, make sure to add both to the map.
1970 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1971 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1972 return Result.getValue(Op.getResNo());
1975 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1976 // Ensure that libcalls are emitted before a branch.
1977 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1978 Tmp1 = LegalizeOp(Tmp1);
1979 LastCALLSEQ_END = DAG.getEntryNode();
1981 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1984 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1985 // Ensure that libcalls are emitted before a branch.
1986 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1987 Tmp1 = LegalizeOp(Tmp1);
1988 LastCALLSEQ_END = DAG.getEntryNode();
1990 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1991 default: assert(0 && "Indirect target must be legal type (pointer)!");
1993 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1996 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1999 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2000 // Ensure that libcalls are emitted before a branch.
2001 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2002 Tmp1 = LegalizeOp(Tmp1);
2003 LastCALLSEQ_END = DAG.getEntryNode();
2005 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
2006 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2008 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
2009 default: assert(0 && "This action is not supported yet!");
2010 case TargetLowering::Legal: break;
2011 case TargetLowering::Custom:
2012 Tmp1 = TLI.LowerOperation(Result, DAG);
2013 if (Tmp1.getNode()) Result = Tmp1;
2015 case TargetLowering::Expand: {
2016 SDValue Chain = Result.getOperand(0);
2017 SDValue Table = Result.getOperand(1);
2018 SDValue Index = Result.getOperand(2);
2020 MVT PTy = TLI.getPointerTy();
2021 MachineFunction &MF = DAG.getMachineFunction();
2022 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
2023 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
2024 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
2026 MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
2027 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, Chain, Addr,
2028 PseudoSourceValue::getJumpTable(), 0, MemVT);
2030 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2031 // For PIC, the sequence is:
2032 // BRIND(load(Jumptable + index) + RelocBase)
2033 // RelocBase can be JumpTable, GOT or some sort of global base.
2034 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
2035 TLI.getPICJumpTableRelocBase(Table, DAG));
2037 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
2042 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2043 // Ensure that libcalls are emitted before a return.
2044 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2045 Tmp1 = LegalizeOp(Tmp1);
2046 LastCALLSEQ_END = DAG.getEntryNode();
2048 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2049 case Expand: assert(0 && "It's impossible to expand bools");
2051 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2054 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
2056 // The top bits of the promoted condition are not necessarily zero, ensure
2057 // that the value is properly zero extended.
2058 unsigned BitWidth = Tmp2.getValueSizeInBits();
2059 if (!DAG.MaskedValueIsZero(Tmp2,
2060 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2061 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
2066 // Basic block destination (Op#2) is always legal.
2067 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2069 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
2070 default: assert(0 && "This action is not supported yet!");
2071 case TargetLowering::Legal: break;
2072 case TargetLowering::Custom:
2073 Tmp1 = TLI.LowerOperation(Result, DAG);
2074 if (Tmp1.getNode()) Result = Tmp1;
2076 case TargetLowering::Expand:
2077 // Expand brcond's setcc into its constituent parts and create a BR_CC
2079 if (Tmp2.getOpcode() == ISD::SETCC) {
2080 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
2081 Tmp2.getOperand(0), Tmp2.getOperand(1),
2082 Node->getOperand(2));
2084 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
2085 DAG.getCondCode(ISD::SETNE), Tmp2,
2086 DAG.getConstant(0, Tmp2.getValueType()),
2087 Node->getOperand(2));
2093 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2094 // Ensure that libcalls are emitted before a branch.
2095 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2096 Tmp1 = LegalizeOp(Tmp1);
2097 Tmp2 = Node->getOperand(2); // LHS
2098 Tmp3 = Node->getOperand(3); // RHS
2099 Tmp4 = Node->getOperand(1); // CC
2101 LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()), Tmp2, Tmp3,Tmp4);
2102 LastCALLSEQ_END = DAG.getEntryNode();
2104 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2105 // the LHS is a legal SETCC itself. In this case, we need to compare
2106 // the result against zero to select between true and false values.
2107 if (Tmp3.getNode() == 0) {
2108 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2109 Tmp4 = DAG.getCondCode(ISD::SETNE);
2112 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
2113 Node->getOperand(4));
2115 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
2116 default: assert(0 && "Unexpected action for BR_CC!");
2117 case TargetLowering::Legal: break;
2118 case TargetLowering::Custom:
2119 Tmp4 = TLI.LowerOperation(Result, DAG);
2120 if (Tmp4.getNode()) Result = Tmp4;
2125 LoadSDNode *LD = cast<LoadSDNode>(Node);
2126 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
2127 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
2129 ISD::LoadExtType ExtType = LD->getExtensionType();
2130 if (ExtType == ISD::NON_EXTLOAD) {
2131 MVT VT = Node->getValueType(0);
2132 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2133 Tmp3 = Result.getValue(0);
2134 Tmp4 = Result.getValue(1);
2136 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
2137 default: assert(0 && "This action is not supported yet!");
2138 case TargetLowering::Legal:
2139 // If this is an unaligned load and the target doesn't support it,
2141 if (!TLI.allowsUnalignedMemoryAccesses()) {
2142 unsigned ABIAlignment = TLI.getTargetData()->
2143 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2144 if (LD->getAlignment() < ABIAlignment){
2145 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2147 Tmp3 = Result.getOperand(0);
2148 Tmp4 = Result.getOperand(1);
2149 Tmp3 = LegalizeOp(Tmp3);
2150 Tmp4 = LegalizeOp(Tmp4);
2154 case TargetLowering::Custom:
2155 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
2156 if (Tmp1.getNode()) {
2157 Tmp3 = LegalizeOp(Tmp1);
2158 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2161 case TargetLowering::Promote: {
2162 // Only promote a load of vector type to another.
2163 assert(VT.isVector() && "Cannot promote this load!");
2164 // Change base type to a different vector type.
2165 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
2167 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
2168 LD->getSrcValueOffset(),
2169 LD->isVolatile(), LD->getAlignment());
2170 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
2171 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2175 // Since loads produce two values, make sure to remember that we
2176 // legalized both of them.
2177 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
2178 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
2179 return Op.getResNo() ? Tmp4 : Tmp3;
2181 MVT SrcVT = LD->getMemoryVT();
2182 unsigned SrcWidth = SrcVT.getSizeInBits();
2183 int SVOffset = LD->getSrcValueOffset();
2184 unsigned Alignment = LD->getAlignment();
2185 bool isVolatile = LD->isVolatile();
2187 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
2188 // Some targets pretend to have an i1 loading operation, and actually
2189 // load an i8. This trick is correct for ZEXTLOAD because the top 7
2190 // bits are guaranteed to be zero; it helps the optimizers understand
2191 // that these bits are zero. It is also useful for EXTLOAD, since it
2192 // tells the optimizers that those bits are undefined. It would be
2193 // nice to have an effective generic way of getting these benefits...
2194 // Until such a way is found, don't insist on promoting i1 here.
2195 (SrcVT != MVT::i1 ||
2196 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2197 // Promote to a byte-sized load if not loading an integral number of
2198 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2199 unsigned NewWidth = SrcVT.getStoreSizeInBits();
2200 MVT NVT = MVT::getIntegerVT(NewWidth);
2203 // The extra bits are guaranteed to be zero, since we stored them that
2204 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2206 ISD::LoadExtType NewExtType =
2207 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2209 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2210 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2211 NVT, isVolatile, Alignment);
2213 Ch = Result.getValue(1); // The chain.
2215 if (ExtType == ISD::SEXTLOAD)
2216 // Having the top bits zero doesn't help when sign extending.
2217 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2218 Result, DAG.getValueType(SrcVT));
2219 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2220 // All the top bits are guaranteed to be zero - inform the optimizers.
2221 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2222 DAG.getValueType(SrcVT));
2224 Tmp1 = LegalizeOp(Result);
2225 Tmp2 = LegalizeOp(Ch);
2226 } else if (SrcWidth & (SrcWidth - 1)) {
2227 // If not loading a power-of-2 number of bits, expand as two loads.
2228 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2229 "Unsupported extload!");
2230 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2231 assert(RoundWidth < SrcWidth);
2232 unsigned ExtraWidth = SrcWidth - RoundWidth;
2233 assert(ExtraWidth < RoundWidth);
2234 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2235 "Load size not an integral number of bytes!");
2236 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2237 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2239 unsigned IncrementSize;
2241 if (TLI.isLittleEndian()) {
2242 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2243 // Load the bottom RoundWidth bits.
2244 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2245 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2248 // Load the remaining ExtraWidth bits.
2249 IncrementSize = RoundWidth / 8;
2250 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2251 DAG.getIntPtrConstant(IncrementSize));
2252 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2253 LD->getSrcValue(), SVOffset + IncrementSize,
2254 ExtraVT, isVolatile,
2255 MinAlign(Alignment, IncrementSize));
2257 // Build a factor node to remember that this load is independent of the
2259 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2262 // Move the top bits to the right place.
2263 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2264 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2266 // Join the hi and lo parts.
2267 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2269 // Big endian - avoid unaligned loads.
2270 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2271 // Load the top RoundWidth bits.
2272 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2273 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2276 // Load the remaining ExtraWidth bits.
2277 IncrementSize = RoundWidth / 8;
2278 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2279 DAG.getIntPtrConstant(IncrementSize));
2280 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2281 LD->getSrcValue(), SVOffset + IncrementSize,
2282 ExtraVT, isVolatile,
2283 MinAlign(Alignment, IncrementSize));
2285 // Build a factor node to remember that this load is independent of the
2287 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2290 // Move the top bits to the right place.
2291 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2292 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2294 // Join the hi and lo parts.
2295 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2298 Tmp1 = LegalizeOp(Result);
2299 Tmp2 = LegalizeOp(Ch);
2301 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
2302 default: assert(0 && "This action is not supported yet!");
2303 case TargetLowering::Custom:
2306 case TargetLowering::Legal:
2307 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2308 Tmp1 = Result.getValue(0);
2309 Tmp2 = Result.getValue(1);
2312 Tmp3 = TLI.LowerOperation(Result, DAG);
2313 if (Tmp3.getNode()) {
2314 Tmp1 = LegalizeOp(Tmp3);
2315 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2318 // If this is an unaligned load and the target doesn't support it,
2320 if (!TLI.allowsUnalignedMemoryAccesses()) {
2321 unsigned ABIAlignment = TLI.getTargetData()->
2322 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2323 if (LD->getAlignment() < ABIAlignment){
2324 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2326 Tmp1 = Result.getOperand(0);
2327 Tmp2 = Result.getOperand(1);
2328 Tmp1 = LegalizeOp(Tmp1);
2329 Tmp2 = LegalizeOp(Tmp2);
2334 case TargetLowering::Expand:
2335 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2336 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2337 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2338 LD->getSrcValueOffset(),
2339 LD->isVolatile(), LD->getAlignment());
2340 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2341 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2342 Tmp2 = LegalizeOp(Load.getValue(1));
2345 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2346 // Turn the unsupported load into an EXTLOAD followed by an explicit
2347 // zero/sign extend inreg.
2348 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2349 Tmp1, Tmp2, LD->getSrcValue(),
2350 LD->getSrcValueOffset(), SrcVT,
2351 LD->isVolatile(), LD->getAlignment());
2353 if (ExtType == ISD::SEXTLOAD)
2354 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2355 Result, DAG.getValueType(SrcVT));
2357 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2358 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2359 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2364 // Since loads produce two values, make sure to remember that we legalized
2366 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2367 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2368 return Op.getResNo() ? Tmp2 : Tmp1;
2371 case ISD::EXTRACT_ELEMENT: {
2372 MVT OpTy = Node->getOperand(0).getValueType();
2373 switch (getTypeAction(OpTy)) {
2374 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2376 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2378 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2379 DAG.getConstant(OpTy.getSizeInBits()/2,
2380 TLI.getShiftAmountTy()));
2381 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2384 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2385 Node->getOperand(0));
2389 // Get both the low and high parts.
2390 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2391 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2392 Result = Tmp2; // 1 -> Hi
2394 Result = Tmp1; // 0 -> Lo
2400 case ISD::CopyToReg:
2401 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2403 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2404 "Register type must be legal!");
2405 // Legalize the incoming value (must be a legal type).
2406 Tmp2 = LegalizeOp(Node->getOperand(2));
2407 if (Node->getNumValues() == 1) {
2408 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2410 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2411 if (Node->getNumOperands() == 4) {
2412 Tmp3 = LegalizeOp(Node->getOperand(3));
2413 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2416 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2419 // Since this produces two values, make sure to remember that we legalized
2421 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2422 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2428 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2430 // Ensure that libcalls are emitted before a return.
2431 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2432 Tmp1 = LegalizeOp(Tmp1);
2433 LastCALLSEQ_END = DAG.getEntryNode();
2435 switch (Node->getNumOperands()) {
2437 Tmp2 = Node->getOperand(1);
2438 Tmp3 = Node->getOperand(2); // Signness
2439 switch (getTypeAction(Tmp2.getValueType())) {
2441 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2444 if (!Tmp2.getValueType().isVector()) {
2446 ExpandOp(Tmp2, Lo, Hi);
2448 // Big endian systems want the hi reg first.
2449 if (TLI.isBigEndian())
2453 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2455 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2456 Result = LegalizeOp(Result);
2458 SDNode *InVal = Tmp2.getNode();
2459 int InIx = Tmp2.getResNo();
2460 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2461 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2463 // Figure out if there is a simple type corresponding to this Vector
2464 // type. If so, convert to the vector type.
2465 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2466 if (TLI.isTypeLegal(TVT)) {
2467 // Turn this into a return of the vector type.
2468 Tmp2 = LegalizeOp(Tmp2);
2469 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2470 } else if (NumElems == 1) {
2471 // Turn this into a return of the scalar type.
2472 Tmp2 = ScalarizeVectorOp(Tmp2);
2473 Tmp2 = LegalizeOp(Tmp2);
2474 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2476 // FIXME: Returns of gcc generic vectors smaller than a legal type
2477 // should be returned in integer registers!
2479 // The scalarized value type may not be legal, e.g. it might require
2480 // promotion or expansion. Relegalize the return.
2481 Result = LegalizeOp(Result);
2483 // FIXME: Returns of gcc generic vectors larger than a legal vector
2484 // type should be returned by reference!
2486 SplitVectorOp(Tmp2, Lo, Hi);
2487 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2488 Result = LegalizeOp(Result);
2493 Tmp2 = PromoteOp(Node->getOperand(1));
2494 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2495 Result = LegalizeOp(Result);
2500 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2502 default: { // ret <values>
2503 SmallVector<SDValue, 8> NewValues;
2504 NewValues.push_back(Tmp1);
2505 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2506 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2508 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2509 NewValues.push_back(Node->getOperand(i+1));
2513 assert(!Node->getOperand(i).getValueType().isExtended() &&
2514 "FIXME: TODO: implement returning non-legal vector types!");
2515 ExpandOp(Node->getOperand(i), Lo, Hi);
2516 NewValues.push_back(Lo);
2517 NewValues.push_back(Node->getOperand(i+1));
2519 NewValues.push_back(Hi);
2520 NewValues.push_back(Node->getOperand(i+1));
2525 assert(0 && "Can't promote multiple return value yet!");
2528 if (NewValues.size() == Node->getNumOperands())
2529 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2531 Result = DAG.getNode(ISD::RET, MVT::Other,
2532 &NewValues[0], NewValues.size());
2537 if (Result.getOpcode() == ISD::RET) {
2538 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2539 default: assert(0 && "This action is not supported yet!");
2540 case TargetLowering::Legal: break;
2541 case TargetLowering::Custom:
2542 Tmp1 = TLI.LowerOperation(Result, DAG);
2543 if (Tmp1.getNode()) Result = Tmp1;
2549 StoreSDNode *ST = cast<StoreSDNode>(Node);
2550 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2551 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2552 int SVOffset = ST->getSrcValueOffset();
2553 unsigned Alignment = ST->getAlignment();
2554 bool isVolatile = ST->isVolatile();
2556 if (!ST->isTruncatingStore()) {
2557 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2558 // FIXME: We shouldn't do this for TargetConstantFP's.
2559 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2560 // to phase ordering between legalized code and the dag combiner. This
2561 // probably means that we need to integrate dag combiner and legalizer
2563 // We generally can't do this one for long doubles.
2564 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2565 if (CFP->getValueType(0) == MVT::f32 &&
2566 getTypeAction(MVT::i32) == Legal) {
2567 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2568 bitcastToAPInt().zextOrTrunc(32),
2570 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2571 SVOffset, isVolatile, Alignment);
2573 } else if (CFP->getValueType(0) == MVT::f64) {
2574 // If this target supports 64-bit registers, do a single 64-bit store.
2575 if (getTypeAction(MVT::i64) == Legal) {
2576 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
2577 zextOrTrunc(64), MVT::i64);
2578 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2579 SVOffset, isVolatile, Alignment);
2581 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2582 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2583 // stores. If the target supports neither 32- nor 64-bits, this
2584 // xform is certainly not worth it.
2585 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
2586 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2587 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2588 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2590 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2591 SVOffset, isVolatile, Alignment);
2592 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2593 DAG.getIntPtrConstant(4));
2594 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2595 isVolatile, MinAlign(Alignment, 4U));
2597 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2603 switch (getTypeAction(ST->getMemoryVT())) {
2605 Tmp3 = LegalizeOp(ST->getValue());
2606 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2609 MVT VT = Tmp3.getValueType();
2610 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2611 default: assert(0 && "This action is not supported yet!");
2612 case TargetLowering::Legal:
2613 // If this is an unaligned store and the target doesn't support it,
2615 if (!TLI.allowsUnalignedMemoryAccesses()) {
2616 unsigned ABIAlignment = TLI.getTargetData()->
2617 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2618 if (ST->getAlignment() < ABIAlignment)
2619 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2623 case TargetLowering::Custom:
2624 Tmp1 = TLI.LowerOperation(Result, DAG);
2625 if (Tmp1.getNode()) Result = Tmp1;
2627 case TargetLowering::Promote:
2628 assert(VT.isVector() && "Unknown legal promote case!");
2629 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2630 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2631 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2632 ST->getSrcValue(), SVOffset, isVolatile,
2639 if (!ST->getMemoryVT().isVector()) {
2640 // Truncate the value and store the result.
2641 Tmp3 = PromoteOp(ST->getValue());
2642 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2643 SVOffset, ST->getMemoryVT(),
2644 isVolatile, Alignment);
2647 // Fall thru to expand for vector
2649 unsigned IncrementSize = 0;
2652 // If this is a vector type, then we have to calculate the increment as
2653 // the product of the element size in bytes, and the number of elements
2654 // in the high half of the vector.
2655 if (ST->getValue().getValueType().isVector()) {
2656 SDNode *InVal = ST->getValue().getNode();
2657 int InIx = ST->getValue().getResNo();
2658 MVT InVT = InVal->getValueType(InIx);
2659 unsigned NumElems = InVT.getVectorNumElements();
2660 MVT EVT = InVT.getVectorElementType();
2662 // Figure out if there is a simple type corresponding to this Vector
2663 // type. If so, convert to the vector type.
2664 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2665 if (TLI.isTypeLegal(TVT)) {
2666 // Turn this into a normal store of the vector type.
2667 Tmp3 = LegalizeOp(ST->getValue());
2668 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2669 SVOffset, isVolatile, Alignment);
2670 Result = LegalizeOp(Result);
2672 } else if (NumElems == 1) {
2673 // Turn this into a normal store of the scalar type.
2674 Tmp3 = ScalarizeVectorOp(ST->getValue());
2675 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2676 SVOffset, isVolatile, Alignment);
2677 // The scalarized value type may not be legal, e.g. it might require
2678 // promotion or expansion. Relegalize the scalar store.
2679 Result = LegalizeOp(Result);
2682 // Check if we have widen this node with another value
2683 std::map<SDValue, SDValue>::iterator I =
2684 WidenNodes.find(ST->getValue());
2685 if (I != WidenNodes.end()) {
2686 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2);
2690 SplitVectorOp(ST->getValue(), Lo, Hi);
2691 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2692 EVT.getSizeInBits()/8;
2696 ExpandOp(ST->getValue(), Lo, Hi);
2697 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2699 if (Hi.getNode() && TLI.isBigEndian())
2703 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2704 SVOffset, isVolatile, Alignment);
2706 if (Hi.getNode() == NULL) {
2707 // Must be int <-> float one-to-one expansion.
2712 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2713 DAG.getIntPtrConstant(IncrementSize));
2714 assert(isTypeLegal(Tmp2.getValueType()) &&
2715 "Pointers must be legal!");
2716 SVOffset += IncrementSize;
2717 Alignment = MinAlign(Alignment, IncrementSize);
2718 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2719 SVOffset, isVolatile, Alignment);
2720 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2725 switch (getTypeAction(ST->getValue().getValueType())) {
2727 Tmp3 = LegalizeOp(ST->getValue());
2730 if (!ST->getValue().getValueType().isVector()) {
2731 // We can promote the value, the truncstore will still take care of it.
2732 Tmp3 = PromoteOp(ST->getValue());
2735 // Vector case falls through to expand
2737 // Just store the low part. This may become a non-trunc store, so make
2738 // sure to use getTruncStore, not UpdateNodeOperands below.
2739 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2740 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2741 SVOffset, MVT::i8, isVolatile, Alignment);
2744 MVT StVT = ST->getMemoryVT();
2745 unsigned StWidth = StVT.getSizeInBits();
2747 if (StWidth != StVT.getStoreSizeInBits()) {
2748 // Promote to a byte-sized store with upper bits zero if not
2749 // storing an integral number of bytes. For example, promote
2750 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2751 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2752 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2753 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2754 SVOffset, NVT, isVolatile, Alignment);
2755 } else if (StWidth & (StWidth - 1)) {
2756 // If not storing a power-of-2 number of bits, expand as two stores.
2757 assert(StVT.isExtended() && !StVT.isVector() &&
2758 "Unsupported truncstore!");
2759 unsigned RoundWidth = 1 << Log2_32(StWidth);
2760 assert(RoundWidth < StWidth);
2761 unsigned ExtraWidth = StWidth - RoundWidth;
2762 assert(ExtraWidth < RoundWidth);
2763 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2764 "Store size not an integral number of bytes!");
2765 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2766 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2768 unsigned IncrementSize;
2770 if (TLI.isLittleEndian()) {
2771 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2772 // Store the bottom RoundWidth bits.
2773 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2775 isVolatile, Alignment);
2777 // Store the remaining ExtraWidth bits.
2778 IncrementSize = RoundWidth / 8;
2779 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2780 DAG.getIntPtrConstant(IncrementSize));
2781 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2782 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2783 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2784 SVOffset + IncrementSize, ExtraVT, isVolatile,
2785 MinAlign(Alignment, IncrementSize));
2787 // Big endian - avoid unaligned stores.
2788 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2789 // Store the top RoundWidth bits.
2790 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2791 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2792 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2793 RoundVT, isVolatile, Alignment);
2795 // Store the remaining ExtraWidth bits.
2796 IncrementSize = RoundWidth / 8;
2797 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2798 DAG.getIntPtrConstant(IncrementSize));
2799 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2800 SVOffset + IncrementSize, ExtraVT, isVolatile,
2801 MinAlign(Alignment, IncrementSize));
2804 // The order of the stores doesn't matter.
2805 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2807 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2808 Tmp2 != ST->getBasePtr())
2809 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2812 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2813 default: assert(0 && "This action is not supported yet!");
2814 case TargetLowering::Legal:
2815 // If this is an unaligned store and the target doesn't support it,
2817 if (!TLI.allowsUnalignedMemoryAccesses()) {
2818 unsigned ABIAlignment = TLI.getTargetData()->
2819 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2820 if (ST->getAlignment() < ABIAlignment)
2821 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2825 case TargetLowering::Custom:
2826 Result = TLI.LowerOperation(Result, DAG);
2829 // TRUNCSTORE:i16 i32 -> STORE i16
2830 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2831 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2832 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2833 isVolatile, Alignment);
2841 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2842 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2844 case ISD::STACKSAVE:
2845 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2846 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2847 Tmp1 = Result.getValue(0);
2848 Tmp2 = Result.getValue(1);
2850 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2851 default: assert(0 && "This action is not supported yet!");
2852 case TargetLowering::Legal: break;
2853 case TargetLowering::Custom:
2854 Tmp3 = TLI.LowerOperation(Result, DAG);
2855 if (Tmp3.getNode()) {
2856 Tmp1 = LegalizeOp(Tmp3);
2857 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2860 case TargetLowering::Expand:
2861 // Expand to CopyFromReg if the target set
2862 // StackPointerRegisterToSaveRestore.
2863 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2864 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2865 Node->getValueType(0));
2866 Tmp2 = Tmp1.getValue(1);
2868 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2869 Tmp2 = Node->getOperand(0);
2874 // Since stacksave produce two values, make sure to remember that we
2875 // legalized both of them.
2876 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2877 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2878 return Op.getResNo() ? Tmp2 : Tmp1;
2880 case ISD::STACKRESTORE:
2881 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2882 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2883 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2885 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2886 default: assert(0 && "This action is not supported yet!");
2887 case TargetLowering::Legal: break;
2888 case TargetLowering::Custom:
2889 Tmp1 = TLI.LowerOperation(Result, DAG);
2890 if (Tmp1.getNode()) Result = Tmp1;
2892 case TargetLowering::Expand:
2893 // Expand to CopyToReg if the target set
2894 // StackPointerRegisterToSaveRestore.
2895 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2896 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2904 case ISD::READCYCLECOUNTER:
2905 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2906 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2907 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2908 Node->getValueType(0))) {
2909 default: assert(0 && "This action is not supported yet!");
2910 case TargetLowering::Legal:
2911 Tmp1 = Result.getValue(0);
2912 Tmp2 = Result.getValue(1);
2914 case TargetLowering::Custom:
2915 Result = TLI.LowerOperation(Result, DAG);
2916 Tmp1 = LegalizeOp(Result.getValue(0));
2917 Tmp2 = LegalizeOp(Result.getValue(1));
2921 // Since rdcc produce two values, make sure to remember that we legalized
2923 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2924 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2928 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2929 case Expand: assert(0 && "It's impossible to expand bools");
2931 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2934 assert(!Node->getOperand(0).getValueType().isVector() && "not possible");
2935 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2936 // Make sure the condition is either zero or one.
2937 unsigned BitWidth = Tmp1.getValueSizeInBits();
2938 if (!DAG.MaskedValueIsZero(Tmp1,
2939 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2940 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2944 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2945 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2947 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2949 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2950 default: assert(0 && "This action is not supported yet!");
2951 case TargetLowering::Legal: break;
2952 case TargetLowering::Custom: {
2953 Tmp1 = TLI.LowerOperation(Result, DAG);
2954 if (Tmp1.getNode()) Result = Tmp1;
2957 case TargetLowering::Expand:
2958 if (Tmp1.getOpcode() == ISD::SETCC) {
2959 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2961 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2963 Result = DAG.getSelectCC(Tmp1,
2964 DAG.getConstant(0, Tmp1.getValueType()),
2965 Tmp2, Tmp3, ISD::SETNE);
2968 case TargetLowering::Promote: {
2970 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2971 unsigned ExtOp, TruncOp;
2972 if (Tmp2.getValueType().isVector()) {
2973 ExtOp = ISD::BIT_CONVERT;
2974 TruncOp = ISD::BIT_CONVERT;
2975 } else if (Tmp2.getValueType().isInteger()) {
2976 ExtOp = ISD::ANY_EXTEND;
2977 TruncOp = ISD::TRUNCATE;
2979 ExtOp = ISD::FP_EXTEND;
2980 TruncOp = ISD::FP_ROUND;
2982 // Promote each of the values to the new type.
2983 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2984 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2985 // Perform the larger operation, then round down.
2986 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2987 if (TruncOp != ISD::FP_ROUND)
2988 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2990 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2991 DAG.getIntPtrConstant(0));
2996 case ISD::SELECT_CC: {
2997 Tmp1 = Node->getOperand(0); // LHS
2998 Tmp2 = Node->getOperand(1); // RHS
2999 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
3000 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
3001 SDValue CC = Node->getOperand(4);
3003 LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC);
3005 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
3006 // the LHS is a legal SETCC itself. In this case, we need to compare
3007 // the result against zero to select between true and false values.
3008 if (Tmp2.getNode() == 0) {
3009 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3010 CC = DAG.getCondCode(ISD::SETNE);
3012 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
3014 // Everything is legal, see if we should expand this op or something.
3015 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
3016 default: assert(0 && "This action is not supported yet!");
3017 case TargetLowering::Legal: break;
3018 case TargetLowering::Custom:
3019 Tmp1 = TLI.LowerOperation(Result, DAG);
3020 if (Tmp1.getNode()) Result = Tmp1;
3026 Tmp1 = Node->getOperand(0);
3027 Tmp2 = Node->getOperand(1);
3028 Tmp3 = Node->getOperand(2);
3029 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3);
3031 // If we had to Expand the SetCC operands into a SELECT node, then it may
3032 // not always be possible to return a true LHS & RHS. In this case, just
3033 // return the value we legalized, returned in the LHS
3034 if (Tmp2.getNode() == 0) {
3039 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
3040 default: assert(0 && "Cannot handle this action for SETCC yet!");
3041 case TargetLowering::Custom:
3044 case TargetLowering::Legal:
3045 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3047 Tmp4 = TLI.LowerOperation(Result, DAG);
3048 if (Tmp4.getNode()) Result = Tmp4;
3051 case TargetLowering::Promote: {
3052 // First step, figure out the appropriate operation to use.
3053 // Allow SETCC to not be supported for all legal data types
3054 // Mostly this targets FP
3055 MVT NewInTy = Node->getOperand(0).getValueType();
3056 MVT OldVT = NewInTy; OldVT = OldVT;
3058 // Scan for the appropriate larger type to use.
3060 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
3062 assert(NewInTy.isInteger() == OldVT.isInteger() &&
3063 "Fell off of the edge of the integer world");
3064 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
3065 "Fell off of the edge of the floating point world");
3067 // If the target supports SETCC of this type, use it.
3068 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
3071 if (NewInTy.isInteger())
3072 assert(0 && "Cannot promote Legal Integer SETCC yet");
3074 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
3075 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
3077 Tmp1 = LegalizeOp(Tmp1);
3078 Tmp2 = LegalizeOp(Tmp2);
3079 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3080 Result = LegalizeOp(Result);
3083 case TargetLowering::Expand:
3084 // Expand a setcc node into a select_cc of the same condition, lhs, and
3085 // rhs that selects between const 1 (true) and const 0 (false).
3086 MVT VT = Node->getValueType(0);
3087 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
3088 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3094 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3095 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3096 SDValue CC = Node->getOperand(2);
3098 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
3100 // Everything is legal, see if we should expand this op or something.
3101 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
3102 default: assert(0 && "This action is not supported yet!");
3103 case TargetLowering::Legal: break;
3104 case TargetLowering::Custom:
3105 Tmp1 = TLI.LowerOperation(Result, DAG);
3106 if (Tmp1.getNode()) Result = Tmp1;
3108 case TargetLowering::Expand: {
3109 // Unroll into a nasty set of scalar code for now.
3110 MVT VT = Node->getValueType(0);
3111 unsigned NumElems = VT.getVectorNumElements();
3112 MVT EltVT = VT.getVectorElementType();
3113 MVT TmpEltVT = Tmp1.getValueType().getVectorElementType();
3114 SmallVector<SDValue, 8> Ops(NumElems);
3115 for (unsigned i = 0; i < NumElems; ++i) {
3116 SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
3117 Tmp1, DAG.getIntPtrConstant(i));
3118 Ops[i] = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(TmpEltVT), In1,
3119 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
3120 Tmp2, DAG.getIntPtrConstant(i)),
3122 Ops[i] = DAG.getNode(ISD::SELECT, EltVT, Ops[i],
3123 DAG.getConstant(EltVT.getIntegerVTBitMask(),EltVT),
3124 DAG.getConstant(0, EltVT));
3126 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], NumElems);
3133 case ISD::SHL_PARTS:
3134 case ISD::SRA_PARTS:
3135 case ISD::SRL_PARTS: {
3136 SmallVector<SDValue, 8> Ops;
3137 bool Changed = false;
3138 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3139 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3140 Changed |= Ops.back() != Node->getOperand(i);
3143 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
3145 switch (TLI.getOperationAction(Node->getOpcode(),
3146 Node->getValueType(0))) {
3147 default: assert(0 && "This action is not supported yet!");
3148 case TargetLowering::Legal: break;
3149 case TargetLowering::Custom:
3150 Tmp1 = TLI.LowerOperation(Result, DAG);
3151 if (Tmp1.getNode()) {
3152 SDValue Tmp2, RetVal(0, 0);
3153 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
3154 Tmp2 = LegalizeOp(Tmp1.getValue(i));
3155 AddLegalizedOperand(SDValue(Node, i), Tmp2);
3156 if (i == Op.getResNo())
3159 assert(RetVal.getNode() && "Illegal result number");
3165 // Since these produce multiple values, make sure to remember that we
3166 // legalized all of them.
3167 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3168 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
3169 return Result.getValue(Op.getResNo());
3191 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3192 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3193 case Expand: assert(0 && "Not possible");
3195 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3198 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3202 if ((Node->getOpcode() == ISD::SHL ||
3203 Node->getOpcode() == ISD::SRL ||
3204 Node->getOpcode() == ISD::SRA) &&
3205 !Node->getValueType(0).isVector()) {
3206 Tmp2 = LegalizeShiftAmount(Tmp2);
3209 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3211 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3212 default: assert(0 && "BinOp legalize operation not supported");
3213 case TargetLowering::Legal: break;
3214 case TargetLowering::Custom:
3215 Tmp1 = TLI.LowerOperation(Result, DAG);
3216 if (Tmp1.getNode()) {
3220 // Fall through if the custom lower can't deal with the operation
3221 case TargetLowering::Expand: {
3222 MVT VT = Op.getValueType();
3224 // See if multiply or divide can be lowered using two-result operations.
3225 SDVTList VTs = DAG.getVTList(VT, VT);
3226 if (Node->getOpcode() == ISD::MUL) {
3227 // We just need the low half of the multiply; try both the signed
3228 // and unsigned forms. If the target supports both SMUL_LOHI and
3229 // UMUL_LOHI, form a preference by checking which forms of plain
3230 // MULH it supports.
3231 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
3232 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
3233 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
3234 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
3235 unsigned OpToUse = 0;
3236 if (HasSMUL_LOHI && !HasMULHS) {
3237 OpToUse = ISD::SMUL_LOHI;
3238 } else if (HasUMUL_LOHI && !HasMULHU) {
3239 OpToUse = ISD::UMUL_LOHI;
3240 } else if (HasSMUL_LOHI) {
3241 OpToUse = ISD::SMUL_LOHI;
3242 } else if (HasUMUL_LOHI) {
3243 OpToUse = ISD::UMUL_LOHI;
3246 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0);
3250 if (Node->getOpcode() == ISD::MULHS &&
3251 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3252 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3256 if (Node->getOpcode() == ISD::MULHU &&
3257 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3258 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3262 if (Node->getOpcode() == ISD::SDIV &&
3263 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3264 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(),
3268 if (Node->getOpcode() == ISD::UDIV &&
3269 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3270 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(),
3275 // Check to see if we have a libcall for this operator.
3276 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3277 bool isSigned = false;
3278 switch (Node->getOpcode()) {
3281 if (VT == MVT::i32) {
3282 LC = Node->getOpcode() == ISD::UDIV
3283 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3284 isSigned = Node->getOpcode() == ISD::SDIV;
3289 LC = RTLIB::MUL_I32;
3290 else if (VT == MVT::i64)
3291 LC = RTLIB::MUL_I64;
3294 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3295 RTLIB::POW_PPCF128);
3298 LC = GetFPLibCall(VT, RTLIB::DIV_F32, RTLIB::DIV_F64, RTLIB::DIV_F80,
3299 RTLIB::DIV_PPCF128);
3303 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3305 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3309 assert(Node->getValueType(0).isVector() &&
3310 "Cannot expand this binary operator!");
3311 // Expand the operation into a bunch of nasty scalar code.
3312 Result = LegalizeOp(UnrollVectorOp(Op));
3315 case TargetLowering::Promote: {
3316 switch (Node->getOpcode()) {
3317 default: assert(0 && "Do not know how to promote this BinOp!");
3321 MVT OVT = Node->getValueType(0);
3322 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3323 assert(OVT.isVector() && "Cannot promote this BinOp!");
3324 // Bit convert each of the values to the new type.
3325 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3326 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3327 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3328 // Bit convert the result back the original type.
3329 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3337 case ISD::SMUL_LOHI:
3338 case ISD::UMUL_LOHI:
3341 // These nodes will only be produced by target-specific lowering, so
3342 // they shouldn't be here if they aren't legal.
3343 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3344 "This must be legal!");
3346 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3347 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3348 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3351 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3352 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3353 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3354 case Expand: assert(0 && "Not possible");
3356 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3359 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3363 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3365 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3366 default: assert(0 && "Operation not supported");
3367 case TargetLowering::Custom:
3368 Tmp1 = TLI.LowerOperation(Result, DAG);
3369 if (Tmp1.getNode()) Result = Tmp1;
3371 case TargetLowering::Legal: break;
3372 case TargetLowering::Expand: {
3373 // If this target supports fabs/fneg natively and select is cheap,
3374 // do this efficiently.
3375 if (!TLI.isSelectExpensive() &&
3376 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3377 TargetLowering::Legal &&
3378 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3379 TargetLowering::Legal) {
3380 // Get the sign bit of the RHS.
3382 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3383 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3384 SignBit = DAG.getSetCC(TLI.getSetCCResultType(IVT),
3385 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3386 // Get the absolute value of the result.
3387 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3388 // Select between the nabs and abs value based on the sign bit of
3390 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3391 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3394 Result = LegalizeOp(Result);
3398 // Otherwise, do bitwise ops!
3400 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3401 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3402 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3403 Result = LegalizeOp(Result);
3411 Tmp1 = LegalizeOp(Node->getOperand(0));
3412 Tmp2 = LegalizeOp(Node->getOperand(1));
3413 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3414 Tmp3 = Result.getValue(0);
3415 Tmp4 = Result.getValue(1);
3417 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3418 default: assert(0 && "This action is not supported yet!");
3419 case TargetLowering::Legal:
3421 case TargetLowering::Custom:
3422 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3423 if (Tmp1.getNode() != NULL) {
3424 Tmp3 = LegalizeOp(Tmp1);
3425 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3429 // Since this produces two values, make sure to remember that we legalized
3431 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3432 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3433 return Op.getResNo() ? Tmp4 : Tmp3;
3437 Tmp1 = LegalizeOp(Node->getOperand(0));
3438 Tmp2 = LegalizeOp(Node->getOperand(1));
3439 Tmp3 = LegalizeOp(Node->getOperand(2));
3440 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3441 Tmp3 = Result.getValue(0);
3442 Tmp4 = Result.getValue(1);
3444 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3445 default: assert(0 && "This action is not supported yet!");
3446 case TargetLowering::Legal:
3448 case TargetLowering::Custom:
3449 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3450 if (Tmp1.getNode() != NULL) {
3451 Tmp3 = LegalizeOp(Tmp1);
3452 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3456 // Since this produces two values, make sure to remember that we legalized
3458 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3459 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3460 return Op.getResNo() ? Tmp4 : Tmp3;
3462 case ISD::BUILD_PAIR: {
3463 MVT PairTy = Node->getValueType(0);
3464 // TODO: handle the case where the Lo and Hi operands are not of legal type
3465 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3466 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3467 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3468 case TargetLowering::Promote:
3469 case TargetLowering::Custom:
3470 assert(0 && "Cannot promote/custom this yet!");
3471 case TargetLowering::Legal:
3472 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3473 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3475 case TargetLowering::Expand:
3476 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3477 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3478 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3479 DAG.getConstant(PairTy.getSizeInBits()/2,
3480 TLI.getShiftAmountTy()));
3481 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3490 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3491 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3493 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3494 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3495 case TargetLowering::Custom:
3498 case TargetLowering::Legal:
3499 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3501 Tmp1 = TLI.LowerOperation(Result, DAG);
3502 if (Tmp1.getNode()) Result = Tmp1;
3505 case TargetLowering::Expand: {
3506 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3507 bool isSigned = DivOpc == ISD::SDIV;
3508 MVT VT = Node->getValueType(0);
3510 // See if remainder can be lowered using two-result operations.
3511 SDVTList VTs = DAG.getVTList(VT, VT);
3512 if (Node->getOpcode() == ISD::SREM &&
3513 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3514 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3517 if (Node->getOpcode() == ISD::UREM &&
3518 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3519 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3523 if (VT.isInteger()) {
3524 if (TLI.getOperationAction(DivOpc, VT) ==
3525 TargetLowering::Legal) {
3527 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3528 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3529 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3530 } else if (VT.isVector()) {
3531 Result = LegalizeOp(UnrollVectorOp(Op));
3533 assert(VT == MVT::i32 &&
3534 "Cannot expand this binary operator!");
3535 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3536 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3538 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3541 assert(VT.isFloatingPoint() &&
3542 "remainder op must have integer or floating-point type");
3543 if (VT.isVector()) {
3544 Result = LegalizeOp(UnrollVectorOp(Op));
3546 // Floating point mod -> fmod libcall.
3547 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3548 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3550 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3558 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3559 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3561 MVT VT = Node->getValueType(0);
3562 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3563 default: assert(0 && "This action is not supported yet!");
3564 case TargetLowering::Custom:
3567 case TargetLowering::Legal:
3568 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3569 Result = Result.getValue(0);
3570 Tmp1 = Result.getValue(1);
3573 Tmp2 = TLI.LowerOperation(Result, DAG);
3574 if (Tmp2.getNode()) {
3575 Result = LegalizeOp(Tmp2);
3576 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3580 case TargetLowering::Expand: {
3581 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3582 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3583 // Increment the pointer, VAList, to the next vaarg
3584 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3585 DAG.getConstant(TLI.getTargetData()->
3586 getTypePaddedSize(VT.getTypeForMVT()),
3587 TLI.getPointerTy()));
3588 // Store the incremented VAList to the legalized pointer
3589 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3590 // Load the actual argument out of the pointer VAList
3591 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3592 Tmp1 = LegalizeOp(Result.getValue(1));
3593 Result = LegalizeOp(Result);
3597 // Since VAARG produces two values, make sure to remember that we
3598 // legalized both of them.
3599 AddLegalizedOperand(SDValue(Node, 0), Result);
3600 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3601 return Op.getResNo() ? Tmp1 : Result;
3605 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3606 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3607 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3609 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3610 default: assert(0 && "This action is not supported yet!");
3611 case TargetLowering::Custom:
3614 case TargetLowering::Legal:
3615 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3616 Node->getOperand(3), Node->getOperand(4));
3618 Tmp1 = TLI.LowerOperation(Result, DAG);
3619 if (Tmp1.getNode()) Result = Tmp1;
3622 case TargetLowering::Expand:
3623 // This defaults to loading a pointer from the input and storing it to the
3624 // output, returning the chain.
3625 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3626 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3627 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3628 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3634 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3635 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3637 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3638 default: assert(0 && "This action is not supported yet!");
3639 case TargetLowering::Custom:
3642 case TargetLowering::Legal:
3643 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3645 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3646 if (Tmp1.getNode()) Result = Tmp1;
3649 case TargetLowering::Expand:
3650 Result = Tmp1; // Default to a no-op, return the chain
3656 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3657 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3659 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3661 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3662 default: assert(0 && "This action is not supported yet!");
3663 case TargetLowering::Legal: break;
3664 case TargetLowering::Custom:
3665 Tmp1 = TLI.LowerOperation(Result, DAG);
3666 if (Tmp1.getNode()) Result = Tmp1;
3673 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3674 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3675 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3676 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3678 assert(0 && "ROTL/ROTR legalize operation not supported");
3680 case TargetLowering::Legal:
3682 case TargetLowering::Custom:
3683 Tmp1 = TLI.LowerOperation(Result, DAG);
3684 if (Tmp1.getNode()) Result = Tmp1;
3686 case TargetLowering::Promote:
3687 assert(0 && "Do not know how to promote ROTL/ROTR");
3689 case TargetLowering::Expand:
3690 assert(0 && "Do not know how to expand ROTL/ROTR");
3696 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3697 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3698 case TargetLowering::Custom:
3699 assert(0 && "Cannot custom legalize this yet!");
3700 case TargetLowering::Legal:
3701 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3703 case TargetLowering::Promote: {
3704 MVT OVT = Tmp1.getValueType();
3705 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3706 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3708 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3709 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3710 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3711 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3714 case TargetLowering::Expand:
3715 Result = ExpandBSWAP(Tmp1);
3723 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3724 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3725 case TargetLowering::Custom:
3726 case TargetLowering::Legal:
3727 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3728 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3729 TargetLowering::Custom) {
3730 Tmp1 = TLI.LowerOperation(Result, DAG);
3731 if (Tmp1.getNode()) {
3736 case TargetLowering::Promote: {
3737 MVT OVT = Tmp1.getValueType();
3738 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3740 // Zero extend the argument.
3741 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3742 // Perform the larger operation, then subtract if needed.
3743 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3744 switch (Node->getOpcode()) {
3749 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3750 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
3751 DAG.getConstant(NVT.getSizeInBits(), NVT),
3753 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3754 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3757 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3758 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3759 DAG.getConstant(NVT.getSizeInBits() -
3760 OVT.getSizeInBits(), NVT));
3765 case TargetLowering::Expand:
3766 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3786 case ISD::FNEARBYINT:
3787 Tmp1 = LegalizeOp(Node->getOperand(0));
3788 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3789 case TargetLowering::Promote:
3790 case TargetLowering::Custom:
3793 case TargetLowering::Legal:
3794 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3796 Tmp1 = TLI.LowerOperation(Result, DAG);
3797 if (Tmp1.getNode()) Result = Tmp1;
3800 case TargetLowering::Expand:
3801 switch (Node->getOpcode()) {
3802 default: assert(0 && "Unreachable!");
3804 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3805 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3806 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3809 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3810 MVT VT = Node->getValueType(0);
3811 Tmp2 = DAG.getConstantFP(0.0, VT);
3812 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()),
3813 Tmp1, Tmp2, ISD::SETUGT);
3814 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3815 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3830 case ISD::FNEARBYINT: {
3831 MVT VT = Node->getValueType(0);
3833 // Expand unsupported unary vector operators by unrolling them.
3834 if (VT.isVector()) {
3835 Result = LegalizeOp(UnrollVectorOp(Op));
3839 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3840 switch(Node->getOpcode()) {
3842 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3843 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3846 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3847 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3850 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3851 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3854 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3855 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3858 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3859 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3862 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3863 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3866 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3867 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3870 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3871 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3874 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3875 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3878 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3879 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3882 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3883 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3886 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3887 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3889 case ISD::FNEARBYINT:
3890 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3891 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3894 default: assert(0 && "Unreachable!");
3897 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3905 MVT VT = Node->getValueType(0);
3907 // Expand unsupported unary vector operators by unrolling them.
3908 if (VT.isVector()) {
3909 Result = LegalizeOp(UnrollVectorOp(Op));
3913 // We always lower FPOWI into a libcall. No target support for it yet.
3914 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3915 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3917 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3920 case ISD::BIT_CONVERT:
3921 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3922 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3923 Node->getValueType(0));
3924 } else if (Op.getOperand(0).getValueType().isVector()) {
3925 // The input has to be a vector type, we have to either scalarize it, pack
3926 // it, or convert it based on whether the input vector type is legal.
3927 SDNode *InVal = Node->getOperand(0).getNode();
3928 int InIx = Node->getOperand(0).getResNo();
3929 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3930 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3932 // Figure out if there is a simple type corresponding to this Vector
3933 // type. If so, convert to the vector type.
3934 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3935 if (TLI.isTypeLegal(TVT)) {
3936 // Turn this into a bit convert of the vector input.
3937 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3938 LegalizeOp(Node->getOperand(0)));
3940 } else if (NumElems == 1) {
3941 // Turn this into a bit convert of the scalar input.
3942 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3943 ScalarizeVectorOp(Node->getOperand(0)));
3946 // FIXME: UNIMP! Store then reload
3947 assert(0 && "Cast from unsupported vector type not implemented yet!");
3950 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3951 Node->getOperand(0).getValueType())) {
3952 default: assert(0 && "Unknown operation action!");
3953 case TargetLowering::Expand:
3954 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3955 Node->getValueType(0));
3957 case TargetLowering::Legal:
3958 Tmp1 = LegalizeOp(Node->getOperand(0));
3959 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3964 case ISD::CONVERT_RNDSAT: {
3965 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
3967 default: assert(0 && "Unknown cvt code!");
3978 SDValue DTyOp = Node->getOperand(1);
3979 SDValue STyOp = Node->getOperand(2);
3980 SDValue RndOp = Node->getOperand(3);
3981 SDValue SatOp = Node->getOperand(4);
3982 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3983 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3985 Tmp1 = LegalizeOp(Node->getOperand(0));
3986 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp,
3988 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3989 TargetLowering::Custom) {
3990 Tmp1 = TLI.LowerOperation(Result, DAG);
3991 if (Tmp1.getNode()) Result = Tmp1;
3995 Result = PromoteOp(Node->getOperand(0));
3996 // For FP, make Op1 a i32
3998 Result = DAG.getConvertRndSat(Op.getValueType(), Result,
3999 DTyOp, STyOp, RndOp, SatOp, CvtCode);
4004 } // end switch CvtCode
4007 // Conversion operators. The source and destination have different types.
4008 case ISD::SINT_TO_FP:
4009 case ISD::UINT_TO_FP: {
4010 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
4011 Result = LegalizeINT_TO_FP(Result, isSigned,
4012 Node->getValueType(0), Node->getOperand(0));
4016 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4018 Tmp1 = LegalizeOp(Node->getOperand(0));
4019 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
4020 default: assert(0 && "Unknown TRUNCATE legalization operation action!");
4021 case TargetLowering::Custom:
4024 case TargetLowering::Legal:
4025 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4027 Tmp1 = TLI.LowerOperation(Result, DAG);
4028 if (Tmp1.getNode()) Result = Tmp1;
4031 case TargetLowering::Expand:
4032 assert(Result.getValueType().isVector() && "must be vector type");
4033 // Unroll the truncate. We should do better.
4034 Result = LegalizeOp(UnrollVectorOp(Result));
4038 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4040 // Since the result is legal, we should just be able to truncate the low
4041 // part of the source.
4042 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
4045 Result = PromoteOp(Node->getOperand(0));
4046 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
4051 case ISD::FP_TO_SINT:
4052 case ISD::FP_TO_UINT:
4053 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4055 Tmp1 = LegalizeOp(Node->getOperand(0));
4057 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
4058 default: assert(0 && "Unknown operation action!");
4059 case TargetLowering::Custom:
4062 case TargetLowering::Legal:
4063 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4065 Tmp1 = TLI.LowerOperation(Result, DAG);
4066 if (Tmp1.getNode()) Result = Tmp1;
4069 case TargetLowering::Promote:
4070 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
4071 Node->getOpcode() == ISD::FP_TO_SINT);
4073 case TargetLowering::Expand:
4074 if (Node->getOpcode() == ISD::FP_TO_UINT) {
4075 SDValue True, False;
4076 MVT VT = Node->getOperand(0).getValueType();
4077 MVT NVT = Node->getValueType(0);
4078 const uint64_t zero[] = {0, 0};
4079 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
4080 APInt x = APInt::getSignBit(NVT.getSizeInBits());
4081 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
4082 Tmp2 = DAG.getConstantFP(apf, VT);
4083 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(VT), Node->getOperand(0),
4085 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
4086 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
4087 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
4089 False = DAG.getNode(ISD::XOR, NVT, False,
4090 DAG.getConstant(x, NVT));
4091 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
4094 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
4100 MVT VT = Op.getValueType();
4101 MVT OVT = Node->getOperand(0).getValueType();
4102 // Convert ppcf128 to i32
4103 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
4104 if (Node->getOpcode() == ISD::FP_TO_SINT) {
4105 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
4106 Node->getOperand(0), DAG.getValueType(MVT::f64));
4107 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
4108 DAG.getIntPtrConstant(1));
4109 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
4111 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
4112 APFloat apf = APFloat(APInt(128, 2, TwoE31));
4113 Tmp2 = DAG.getConstantFP(apf, OVT);
4114 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
4115 // FIXME: generated code sucks.
4116 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
4117 DAG.getNode(ISD::ADD, MVT::i32,
4118 DAG.getNode(ISD::FP_TO_SINT, VT,
4119 DAG.getNode(ISD::FSUB, OVT,
4120 Node->getOperand(0), Tmp2)),
4121 DAG.getConstant(0x80000000, MVT::i32)),
4122 DAG.getNode(ISD::FP_TO_SINT, VT,
4123 Node->getOperand(0)),
4124 DAG.getCondCode(ISD::SETGE));
4128 // Convert f32 / f64 to i32 / i64 / i128.
4129 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
4130 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
4131 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
4133 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
4137 Tmp1 = PromoteOp(Node->getOperand(0));
4138 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
4139 Result = LegalizeOp(Result);
4144 case ISD::FP_EXTEND: {
4145 MVT DstVT = Op.getValueType();
4146 MVT SrcVT = Op.getOperand(0).getValueType();
4147 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4148 // The only other way we can lower this is to turn it into a STORE,
4149 // LOAD pair, targetting a temporary location (a stack slot).
4150 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
4153 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4154 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4156 Tmp1 = LegalizeOp(Node->getOperand(0));
4157 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4160 Tmp1 = PromoteOp(Node->getOperand(0));
4161 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
4166 case ISD::FP_ROUND: {
4167 MVT DstVT = Op.getValueType();
4168 MVT SrcVT = Op.getOperand(0).getValueType();
4169 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4170 if (SrcVT == MVT::ppcf128) {
4172 ExpandOp(Node->getOperand(0), Lo, Result);
4173 // Round it the rest of the way (e.g. to f32) if needed.
4174 if (DstVT!=MVT::f64)
4175 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
4178 // The only other way we can lower this is to turn it into a STORE,
4179 // LOAD pair, targetting a temporary location (a stack slot).
4180 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
4183 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4184 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4186 Tmp1 = LegalizeOp(Node->getOperand(0));
4187 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4190 Tmp1 = PromoteOp(Node->getOperand(0));
4191 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
4192 Node->getOperand(1));
4197 case ISD::ANY_EXTEND:
4198 case ISD::ZERO_EXTEND:
4199 case ISD::SIGN_EXTEND:
4200 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4201 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4203 Tmp1 = LegalizeOp(Node->getOperand(0));
4204 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4205 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4206 TargetLowering::Custom) {
4207 Tmp1 = TLI.LowerOperation(Result, DAG);
4208 if (Tmp1.getNode()) Result = Tmp1;
4212 switch (Node->getOpcode()) {
4213 case ISD::ANY_EXTEND:
4214 Tmp1 = PromoteOp(Node->getOperand(0));
4215 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
4217 case ISD::ZERO_EXTEND:
4218 Result = PromoteOp(Node->getOperand(0));
4219 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
4220 Result = DAG.getZeroExtendInReg(Result,
4221 Node->getOperand(0).getValueType());
4223 case ISD::SIGN_EXTEND:
4224 Result = PromoteOp(Node->getOperand(0));
4225 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
4226 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4228 DAG.getValueType(Node->getOperand(0).getValueType()));
4233 case ISD::FP_ROUND_INREG:
4234 case ISD::SIGN_EXTEND_INREG: {
4235 Tmp1 = LegalizeOp(Node->getOperand(0));
4236 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
4238 // If this operation is not supported, convert it to a shl/shr or load/store
4240 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
4241 default: assert(0 && "This action not supported for this op yet!");
4242 case TargetLowering::Legal:
4243 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4245 case TargetLowering::Expand:
4246 // If this is an integer extend and shifts are supported, do that.
4247 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
4248 // NOTE: we could fall back on load/store here too for targets without
4249 // SAR. However, it is doubtful that any exist.
4250 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
4251 ExtraVT.getSizeInBits();
4252 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
4253 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
4254 Node->getOperand(0), ShiftCst);
4255 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
4257 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
4258 // The only way we can lower this is to turn it into a TRUNCSTORE,
4259 // EXTLOAD pair, targetting a temporary location (a stack slot).
4261 // NOTE: there is a choice here between constantly creating new stack
4262 // slots and always reusing the same one. We currently always create
4263 // new ones, as reuse may inhibit scheduling.
4264 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
4265 Node->getValueType(0));
4267 assert(0 && "Unknown op");
4273 case ISD::TRAMPOLINE: {
4275 for (unsigned i = 0; i != 6; ++i)
4276 Ops[i] = LegalizeOp(Node->getOperand(i));
4277 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
4278 // The only option for this node is to custom lower it.
4279 Result = TLI.LowerOperation(Result, DAG);
4280 assert(Result.getNode() && "Should always custom lower!");
4282 // Since trampoline produces two values, make sure to remember that we
4283 // legalized both of them.
4284 Tmp1 = LegalizeOp(Result.getValue(1));
4285 Result = LegalizeOp(Result);
4286 AddLegalizedOperand(SDValue(Node, 0), Result);
4287 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
4288 return Op.getResNo() ? Tmp1 : Result;
4290 case ISD::FLT_ROUNDS_: {
4291 MVT VT = Node->getValueType(0);
4292 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4293 default: assert(0 && "This action not supported for this op yet!");
4294 case TargetLowering::Custom:
4295 Result = TLI.LowerOperation(Op, DAG);
4296 if (Result.getNode()) break;
4298 case TargetLowering::Legal:
4299 // If this operation is not supported, lower it to constant 1
4300 Result = DAG.getConstant(1, VT);
4306 MVT VT = Node->getValueType(0);
4307 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4308 default: assert(0 && "This action not supported for this op yet!");
4309 case TargetLowering::Legal:
4310 Tmp1 = LegalizeOp(Node->getOperand(0));
4311 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4313 case TargetLowering::Custom:
4314 Result = TLI.LowerOperation(Op, DAG);
4315 if (Result.getNode()) break;
4317 case TargetLowering::Expand:
4318 // If this operation is not supported, lower it to 'abort()' call
4319 Tmp1 = LegalizeOp(Node->getOperand(0));
4320 TargetLowering::ArgListTy Args;
4321 std::pair<SDValue,SDValue> CallResult =
4322 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4323 false, false, false, false, CallingConv::C, false,
4324 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4326 Result = CallResult.second;
4334 MVT VT = Node->getValueType(0);
4335 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4336 default: assert(0 && "This action not supported for this op yet!");
4337 case TargetLowering::Custom:
4338 Result = TLI.LowerOperation(Op, DAG);
4339 if (Result.getNode()) break;
4341 case TargetLowering::Legal: {
4342 SDValue LHS = LegalizeOp(Node->getOperand(0));
4343 SDValue RHS = LegalizeOp(Node->getOperand(1));
4345 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
4346 ISD::ADD : ISD::SUB, LHS.getValueType(),
4348 MVT OType = Node->getValueType(1);
4350 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
4352 // LHSSign -> LHS >= 0
4353 // RHSSign -> RHS >= 0
4354 // SumSign -> Sum >= 0
4357 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4359 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
4361 SDValue LHSSign = DAG.getSetCC(OType, LHS, Zero, ISD::SETGE);
4362 SDValue RHSSign = DAG.getSetCC(OType, RHS, Zero, ISD::SETGE);
4363 SDValue SignsMatch = DAG.getSetCC(OType, LHSSign, RHSSign,
4364 Node->getOpcode() == ISD::SADDO ?
4365 ISD::SETEQ : ISD::SETNE);
4367 SDValue SumSign = DAG.getSetCC(OType, Sum, Zero, ISD::SETGE);
4368 SDValue SumSignNE = DAG.getSetCC(OType, LHSSign, SumSign, ISD::SETNE);
4370 SDValue Cmp = DAG.getNode(ISD::AND, OType, SignsMatch, SumSignNE);
4372 MVT ValueVTs[] = { LHS.getValueType(), OType };
4373 SDValue Ops[] = { Sum, Cmp };
4375 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2),
4377 SDNode *RNode = Result.getNode();
4378 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4379 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4388 MVT VT = Node->getValueType(0);
4389 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4390 default: assert(0 && "This action not supported for this op yet!");
4391 case TargetLowering::Custom:
4392 Result = TLI.LowerOperation(Op, DAG);
4393 if (Result.getNode()) break;
4395 case TargetLowering::Legal: {
4396 SDValue LHS = LegalizeOp(Node->getOperand(0));
4397 SDValue RHS = LegalizeOp(Node->getOperand(1));
4399 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
4400 ISD::ADD : ISD::SUB, LHS.getValueType(),
4402 MVT OType = Node->getValueType(1);
4403 SDValue Cmp = DAG.getSetCC(OType, Sum, LHS,
4404 Node->getOpcode () == ISD::UADDO ?
4405 ISD::SETULT : ISD::SETUGT);
4407 MVT ValueVTs[] = { LHS.getValueType(), OType };
4408 SDValue Ops[] = { Sum, Cmp };
4410 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2),
4412 SDNode *RNode = Result.getNode();
4413 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4414 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4423 MVT VT = Node->getValueType(0);
4424 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4425 default: assert(0 && "This action is not supported at all!");
4426 case TargetLowering::Custom:
4427 Result = TLI.LowerOperation(Op, DAG);
4428 if (Result.getNode()) break;
4430 case TargetLowering::Legal:
4431 // FIXME: According to Hacker's Delight, this can be implemented in
4432 // target independent lowering, but it would be inefficient, since it
4433 // requires a division + a branch.
4434 assert(0 && "Target independent lowering is not supported for SMULO/UMULO!");
4442 assert(Result.getValueType() == Op.getValueType() &&
4443 "Bad legalization!");
4445 // Make sure that the generated code is itself legal.
4447 Result = LegalizeOp(Result);
4449 // Note that LegalizeOp may be reentered even from single-use nodes, which
4450 // means that we always must cache transformed nodes.
4451 AddLegalizedOperand(Op, Result);
4455 /// PromoteOp - Given an operation that produces a value in an invalid type,
4456 /// promote it to compute the value into a larger type. The produced value will
4457 /// have the correct bits for the low portion of the register, but no guarantee
4458 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4459 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4460 MVT VT = Op.getValueType();
4461 MVT NVT = TLI.getTypeToTransformTo(VT);
4462 assert(getTypeAction(VT) == Promote &&
4463 "Caller should expand or legalize operands that are not promotable!");
4464 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4465 "Cannot promote to smaller type!");
4467 SDValue Tmp1, Tmp2, Tmp3;
4469 SDNode *Node = Op.getNode();
4471 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4472 if (I != PromotedNodes.end()) return I->second;
4474 switch (Node->getOpcode()) {
4475 case ISD::CopyFromReg:
4476 assert(0 && "CopyFromReg must be legal!");
4479 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4481 assert(0 && "Do not know how to promote this operator!");
4484 Result = DAG.getNode(ISD::UNDEF, NVT);
4488 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4490 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4491 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4493 case ISD::ConstantFP:
4494 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4495 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4499 MVT VT0 = Node->getOperand(0).getValueType();
4500 assert(isTypeLegal(TLI.getSetCCResultType(VT0))
4501 && "SetCC type is not legal??");
4502 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(VT0),
4503 Node->getOperand(0), Node->getOperand(1),
4504 Node->getOperand(2));
4508 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4510 Result = LegalizeOp(Node->getOperand(0));
4511 assert(Result.getValueType().bitsGE(NVT) &&
4512 "This truncation doesn't make sense!");
4513 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4514 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4517 // The truncation is not required, because we don't guarantee anything
4518 // about high bits anyway.
4519 Result = PromoteOp(Node->getOperand(0));
4522 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4523 // Truncate the low part of the expanded value to the result type
4524 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4527 case ISD::SIGN_EXTEND:
4528 case ISD::ZERO_EXTEND:
4529 case ISD::ANY_EXTEND:
4530 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4531 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4533 // Input is legal? Just do extend all the way to the larger type.
4534 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4537 // Promote the reg if it's smaller.
4538 Result = PromoteOp(Node->getOperand(0));
4539 // The high bits are not guaranteed to be anything. Insert an extend.
4540 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4541 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4542 DAG.getValueType(Node->getOperand(0).getValueType()));
4543 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4544 Result = DAG.getZeroExtendInReg(Result,
4545 Node->getOperand(0).getValueType());
4549 case ISD::CONVERT_RNDSAT: {
4550 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4551 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
4552 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
4553 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
4554 "can only promote integers");
4555 Result = DAG.getConvertRndSat(NVT, Node->getOperand(0),
4556 Node->getOperand(1), Node->getOperand(2),
4557 Node->getOperand(3), Node->getOperand(4),
4562 case ISD::BIT_CONVERT:
4563 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4564 Node->getValueType(0));
4565 Result = PromoteOp(Result);
4568 case ISD::FP_EXTEND:
4569 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4571 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4572 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4573 case Promote: assert(0 && "Unreachable with 2 FP types!");
4575 if (Node->getConstantOperandVal(1) == 0) {
4576 // Input is legal? Do an FP_ROUND_INREG.
4577 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4578 DAG.getValueType(VT));
4580 // Just remove the truncate, it isn't affecting the value.
4581 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4582 Node->getOperand(1));
4587 case ISD::SINT_TO_FP:
4588 case ISD::UINT_TO_FP:
4589 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4591 // No extra round required here.
4592 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4596 Result = PromoteOp(Node->getOperand(0));
4597 if (Node->getOpcode() == ISD::SINT_TO_FP)
4598 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4600 DAG.getValueType(Node->getOperand(0).getValueType()));
4602 Result = DAG.getZeroExtendInReg(Result,
4603 Node->getOperand(0).getValueType());
4604 // No extra round required here.
4605 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4608 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4609 Node->getOperand(0));
4610 // Round if we cannot tolerate excess precision.
4611 if (NoExcessFPPrecision)
4612 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4613 DAG.getValueType(VT));
4618 case ISD::SIGN_EXTEND_INREG:
4619 Result = PromoteOp(Node->getOperand(0));
4620 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4621 Node->getOperand(1));
4623 case ISD::FP_TO_SINT:
4624 case ISD::FP_TO_UINT:
4625 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4628 Tmp1 = Node->getOperand(0);
4631 // The input result is prerounded, so we don't have to do anything
4633 Tmp1 = PromoteOp(Node->getOperand(0));
4636 // If we're promoting a UINT to a larger size, check to see if the new node
4637 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4638 // we can use that instead. This allows us to generate better code for
4639 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4640 // legal, such as PowerPC.
4641 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4642 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4643 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4644 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4645 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4647 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4653 Tmp1 = PromoteOp(Node->getOperand(0));
4654 assert(Tmp1.getValueType() == NVT);
4655 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4656 // NOTE: we do not have to do any extra rounding here for
4657 // NoExcessFPPrecision, because we know the input will have the appropriate
4658 // precision, and these operations don't modify precision at all.
4673 case ISD::FNEARBYINT:
4674 Tmp1 = PromoteOp(Node->getOperand(0));
4675 assert(Tmp1.getValueType() == NVT);
4676 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4677 if (NoExcessFPPrecision)
4678 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4679 DAG.getValueType(VT));
4684 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4685 // directly as well, which may be better.
4686 Tmp1 = PromoteOp(Node->getOperand(0));
4687 Tmp2 = Node->getOperand(1);
4688 if (Node->getOpcode() == ISD::FPOW)
4689 Tmp2 = PromoteOp(Tmp2);
4690 assert(Tmp1.getValueType() == NVT);
4691 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4692 if (NoExcessFPPrecision)
4693 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4694 DAG.getValueType(VT));
4698 case ISD::ATOMIC_CMP_SWAP: {
4699 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4700 Tmp2 = PromoteOp(Node->getOperand(2));
4701 Tmp3 = PromoteOp(Node->getOperand(3));
4702 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getMemoryVT(),
4703 AtomNode->getChain(),
4704 AtomNode->getBasePtr(), Tmp2, Tmp3,
4705 AtomNode->getSrcValue(),
4706 AtomNode->getAlignment());
4707 // Remember that we legalized the chain.
4708 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4711 case ISD::ATOMIC_LOAD_ADD:
4712 case ISD::ATOMIC_LOAD_SUB:
4713 case ISD::ATOMIC_LOAD_AND:
4714 case ISD::ATOMIC_LOAD_OR:
4715 case ISD::ATOMIC_LOAD_XOR:
4716 case ISD::ATOMIC_LOAD_NAND:
4717 case ISD::ATOMIC_LOAD_MIN:
4718 case ISD::ATOMIC_LOAD_MAX:
4719 case ISD::ATOMIC_LOAD_UMIN:
4720 case ISD::ATOMIC_LOAD_UMAX:
4721 case ISD::ATOMIC_SWAP: {
4722 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4723 Tmp2 = PromoteOp(Node->getOperand(2));
4724 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getMemoryVT(),
4725 AtomNode->getChain(),
4726 AtomNode->getBasePtr(), Tmp2,
4727 AtomNode->getSrcValue(),
4728 AtomNode->getAlignment());
4729 // Remember that we legalized the chain.
4730 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4740 // The input may have strange things in the top bits of the registers, but
4741 // these operations don't care. They may have weird bits going out, but
4742 // that too is okay if they are integer operations.
4743 Tmp1 = PromoteOp(Node->getOperand(0));
4744 Tmp2 = PromoteOp(Node->getOperand(1));
4745 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4746 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4751 Tmp1 = PromoteOp(Node->getOperand(0));
4752 Tmp2 = PromoteOp(Node->getOperand(1));
4753 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4754 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4756 // Floating point operations will give excess precision that we may not be
4757 // able to tolerate. If we DO allow excess precision, just leave it,
4758 // otherwise excise it.
4759 // FIXME: Why would we need to round FP ops more than integer ones?
4760 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4761 if (NoExcessFPPrecision)
4762 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4763 DAG.getValueType(VT));
4768 // These operators require that their input be sign extended.
4769 Tmp1 = PromoteOp(Node->getOperand(0));
4770 Tmp2 = PromoteOp(Node->getOperand(1));
4771 if (NVT.isInteger()) {
4772 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4773 DAG.getValueType(VT));
4774 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4775 DAG.getValueType(VT));
4777 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4779 // Perform FP_ROUND: this is probably overly pessimistic.
4780 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4781 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4782 DAG.getValueType(VT));
4786 case ISD::FCOPYSIGN:
4787 // These operators require that their input be fp extended.
4788 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4789 case Expand: assert(0 && "not implemented");
4790 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4791 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4793 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4794 case Expand: assert(0 && "not implemented");
4795 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4796 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4798 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4800 // Perform FP_ROUND: this is probably overly pessimistic.
4801 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4802 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4803 DAG.getValueType(VT));
4808 // These operators require that their input be zero extended.
4809 Tmp1 = PromoteOp(Node->getOperand(0));
4810 Tmp2 = PromoteOp(Node->getOperand(1));
4811 assert(NVT.isInteger() && "Operators don't apply to FP!");
4812 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4813 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4814 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4818 Tmp1 = PromoteOp(Node->getOperand(0));
4819 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4822 // The input value must be properly sign extended.
4823 Tmp1 = PromoteOp(Node->getOperand(0));
4824 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4825 DAG.getValueType(VT));
4826 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4829 // The input value must be properly zero extended.
4830 Tmp1 = PromoteOp(Node->getOperand(0));
4831 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4832 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4836 Tmp1 = Node->getOperand(0); // Get the chain.
4837 Tmp2 = Node->getOperand(1); // Get the pointer.
4838 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4839 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4840 Result = TLI.LowerOperation(Tmp3, DAG);
4842 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4843 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4844 // Increment the pointer, VAList, to the next vaarg
4845 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4846 DAG.getConstant(VT.getSizeInBits()/8,
4847 TLI.getPointerTy()));
4848 // Store the incremented VAList to the legalized pointer
4849 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4850 // Load the actual argument out of the pointer VAList
4851 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4853 // Remember that we legalized the chain.
4854 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4858 LoadSDNode *LD = cast<LoadSDNode>(Node);
4859 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4860 ? ISD::EXTLOAD : LD->getExtensionType();
4861 Result = DAG.getExtLoad(ExtType, NVT,
4862 LD->getChain(), LD->getBasePtr(),
4863 LD->getSrcValue(), LD->getSrcValueOffset(),
4866 LD->getAlignment());
4867 // Remember that we legalized the chain.
4868 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4872 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4873 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4875 MVT VT2 = Tmp2.getValueType();
4876 assert(VT2 == Tmp3.getValueType()
4877 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4878 // Ensure that the resulting node is at least the same size as the operands'
4879 // value types, because we cannot assume that TLI.getSetCCValueType() is
4881 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4884 case ISD::SELECT_CC:
4885 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4886 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4887 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4888 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4891 Tmp1 = Node->getOperand(0);
4892 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4893 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4894 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4895 DAG.getConstant(NVT.getSizeInBits() -
4897 TLI.getShiftAmountTy()));
4902 // Zero extend the argument
4903 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4904 // Perform the larger operation, then subtract if needed.
4905 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4906 switch(Node->getOpcode()) {
4911 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4912 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
4913 DAG.getConstant(NVT.getSizeInBits(), NVT),
4915 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4916 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4919 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4920 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4921 DAG.getConstant(NVT.getSizeInBits() -
4922 VT.getSizeInBits(), NVT));
4926 case ISD::EXTRACT_SUBVECTOR:
4927 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4929 case ISD::EXTRACT_VECTOR_ELT:
4930 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4934 assert(Result.getNode() && "Didn't set a result!");
4936 // Make sure the result is itself legal.
4937 Result = LegalizeOp(Result);
4939 // Remember that we promoted this!
4940 AddPromotedOperand(Op, Result);
4944 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4945 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4946 /// based on the vector type. The return type of this matches the element type
4947 /// of the vector, which may not be legal for the target.
4948 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
4949 // We know that operand #0 is the Vec vector. If the index is a constant
4950 // or if the invec is a supported hardware type, we can use it. Otherwise,
4951 // lower to a store then an indexed load.
4952 SDValue Vec = Op.getOperand(0);
4953 SDValue Idx = Op.getOperand(1);
4955 MVT TVT = Vec.getValueType();
4956 unsigned NumElems = TVT.getVectorNumElements();
4958 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4959 default: assert(0 && "This action is not supported yet!");
4960 case TargetLowering::Custom: {
4961 Vec = LegalizeOp(Vec);
4962 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4963 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
4968 case TargetLowering::Legal:
4969 if (isTypeLegal(TVT)) {
4970 Vec = LegalizeOp(Vec);
4971 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4975 case TargetLowering::Promote:
4976 assert(TVT.isVector() && "not vector type");
4977 // fall thru to expand since vectors are by default are promote
4978 case TargetLowering::Expand:
4982 if (NumElems == 1) {
4983 // This must be an access of the only element. Return it.
4984 Op = ScalarizeVectorOp(Vec);
4985 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4986 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4987 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4989 SplitVectorOp(Vec, Lo, Hi);
4990 if (CIdx->getZExtValue() < NumLoElts) {
4994 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
4995 Idx.getValueType());
4998 // It's now an extract from the appropriate high or low part. Recurse.
4999 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5000 Op = ExpandEXTRACT_VECTOR_ELT(Op);
5002 // Store the value to a temporary stack slot, then LOAD the scalar
5003 // element back out.
5004 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
5005 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
5007 // Add the offset to the index.
5008 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
5009 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
5010 DAG.getConstant(EltSize, Idx.getValueType()));
5012 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
5013 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
5015 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
5017 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
5019 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
5024 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
5025 /// we assume the operation can be split if it is not already legal.
5026 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
5027 // We know that operand #0 is the Vec vector. For now we assume the index
5028 // is a constant and that the extracted result is a supported hardware type.
5029 SDValue Vec = Op.getOperand(0);
5030 SDValue Idx = LegalizeOp(Op.getOperand(1));
5032 unsigned NumElems = Vec.getValueType().getVectorNumElements();
5034 if (NumElems == Op.getValueType().getVectorNumElements()) {
5035 // This must be an access of the desired vector length. Return it.
5039 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5041 SplitVectorOp(Vec, Lo, Hi);
5042 if (CIdx->getZExtValue() < NumElems/2) {
5046 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
5047 Idx.getValueType());
5050 // It's now an extract from the appropriate high or low part. Recurse.
5051 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5052 return ExpandEXTRACT_SUBVECTOR(Op);
5055 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
5056 /// with condition CC on the current target. This usually involves legalizing
5057 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
5058 /// there may be no choice but to create a new SetCC node to represent the
5059 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
5060 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
5061 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
5064 SDValue Tmp1, Tmp2, Tmp3, Result;
5066 switch (getTypeAction(LHS.getValueType())) {
5068 Tmp1 = LegalizeOp(LHS); // LHS
5069 Tmp2 = LegalizeOp(RHS); // RHS
5072 Tmp1 = PromoteOp(LHS); // LHS
5073 Tmp2 = PromoteOp(RHS); // RHS
5075 // If this is an FP compare, the operands have already been extended.
5076 if (LHS.getValueType().isInteger()) {
5077 MVT VT = LHS.getValueType();
5078 MVT NVT = TLI.getTypeToTransformTo(VT);
5080 // Otherwise, we have to insert explicit sign or zero extends. Note
5081 // that we could insert sign extends for ALL conditions, but zero extend
5082 // is cheaper on many machines (an AND instead of two shifts), so prefer
5084 switch (cast<CondCodeSDNode>(CC)->get()) {
5085 default: assert(0 && "Unknown integer comparison!");
5092 // ALL of these operations will work if we either sign or zero extend
5093 // the operands (including the unsigned comparisons!). Zero extend is
5094 // usually a simpler/cheaper operation, so prefer it.
5095 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
5096 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
5102 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
5103 DAG.getValueType(VT));
5104 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
5105 DAG.getValueType(VT));
5106 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
5107 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
5113 MVT VT = LHS.getValueType();
5114 if (VT == MVT::f32 || VT == MVT::f64) {
5115 // Expand into one or more soft-fp libcall(s).
5116 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
5117 switch (cast<CondCodeSDNode>(CC)->get()) {
5120 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5124 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
5128 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5132 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5136 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5140 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5143 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5146 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
5149 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5150 switch (cast<CondCodeSDNode>(CC)->get()) {
5152 // SETONE = SETOLT | SETOGT
5153 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5156 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5159 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5162 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5165 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5168 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5170 default: assert(0 && "Unsupported FP setcc!");
5175 SDValue Ops[2] = { LHS, RHS };
5176 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(),
5177 false /*sign irrelevant*/, Dummy);
5178 Tmp2 = DAG.getConstant(0, MVT::i32);
5179 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
5180 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
5181 Tmp1 = DAG.getNode(ISD::SETCC,
5182 TLI.getSetCCResultType(Tmp1.getValueType()),
5184 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(),
5185 false /*sign irrelevant*/, Dummy);
5186 Tmp2 = DAG.getNode(ISD::SETCC,
5187 TLI.getSetCCResultType(LHS.getValueType()), LHS,
5188 Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
5189 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
5192 LHS = LegalizeOp(Tmp1);
5197 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5198 ExpandOp(LHS, LHSLo, LHSHi);
5199 ExpandOp(RHS, RHSLo, RHSHi);
5200 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5202 if (VT==MVT::ppcf128) {
5203 // FIXME: This generated code sucks. We want to generate
5204 // FCMPU crN, hi1, hi2
5206 // FCMPU crN, lo1, lo2
5207 // The following can be improved, but not that much.
5208 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5209 LHSHi, RHSHi, ISD::SETOEQ);
5210 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
5211 LHSLo, RHSLo, CCCode);
5212 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
5213 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5214 LHSHi, RHSHi, ISD::SETUNE);
5215 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5216 LHSHi, RHSHi, CCCode);
5217 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
5218 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
5227 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
5228 if (RHSCST->isAllOnesValue()) {
5229 // Comparison to -1.
5230 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
5235 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
5236 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
5237 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
5238 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
5241 // If this is a comparison of the sign bit, just look at the top part.
5243 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
5244 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
5245 CST->isNullValue()) || // X < 0
5246 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
5247 CST->isAllOnesValue())) { // X > -1
5253 // FIXME: This generated code sucks.
5254 ISD::CondCode LowCC;
5256 default: assert(0 && "Unknown integer setcc!");
5258 case ISD::SETULT: LowCC = ISD::SETULT; break;
5260 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5262 case ISD::SETULE: LowCC = ISD::SETULE; break;
5264 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5267 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
5268 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
5269 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
5271 // NOTE: on targets without efficient SELECT of bools, we can always use
5272 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5273 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
5274 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
5275 LHSLo, RHSLo, LowCC, false, DagCombineInfo);
5276 if (!Tmp1.getNode())
5277 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
5278 LHSLo, RHSLo, LowCC);
5279 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5280 LHSHi, RHSHi, CCCode, false, DagCombineInfo);
5281 if (!Tmp2.getNode())
5282 Tmp2 = DAG.getNode(ISD::SETCC,
5283 TLI.getSetCCResultType(LHSHi.getValueType()),
5286 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
5287 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
5288 if ((Tmp1C && Tmp1C->isNullValue()) ||
5289 (Tmp2C && Tmp2C->isNullValue() &&
5290 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
5291 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
5292 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
5293 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
5294 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
5295 // low part is known false, returns high part.
5296 // For LE / GE, if high part is known false, ignore the low part.
5297 // For LT / GT, if high part is known true, ignore the low part.
5301 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5302 LHSHi, RHSHi, ISD::SETEQ, false,
5304 if (!Result.getNode())
5305 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5306 LHSHi, RHSHi, ISD::SETEQ);
5307 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
5308 Result, Tmp1, Tmp2));
5319 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
5320 /// condition code CC on the current target. This routine assumes LHS and rHS
5321 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
5322 /// illegal condition code into AND / OR of multiple SETCC values.
5323 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
5324 SDValue &LHS, SDValue &RHS,
5326 MVT OpVT = LHS.getValueType();
5327 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5328 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
5329 default: assert(0 && "Unknown condition code action!");
5330 case TargetLowering::Legal:
5333 case TargetLowering::Expand: {
5334 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
5337 default: assert(0 && "Don't know how to expand this condition!"); abort();
5338 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
5339 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5340 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5341 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5342 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5343 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5344 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5345 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5346 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5347 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5348 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5349 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5350 // FIXME: Implement more expansions.
5353 SDValue SetCC1 = DAG.getSetCC(VT, LHS, RHS, CC1);
5354 SDValue SetCC2 = DAG.getSetCC(VT, LHS, RHS, CC2);
5355 LHS = DAG.getNode(Opc, VT, SetCC1, SetCC2);
5363 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
5364 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
5365 /// a load from the stack slot to DestVT, extending it if needed.
5366 /// The resultant code need not be legal.
5367 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
5370 // Create the stack frame object.
5371 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
5372 SrcOp.getValueType().getTypeForMVT());
5373 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
5375 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
5376 int SPFI = StackPtrFI->getIndex();
5378 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
5379 unsigned SlotSize = SlotVT.getSizeInBits();
5380 unsigned DestSize = DestVT.getSizeInBits();
5381 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
5382 DestVT.getTypeForMVT());
5384 // Emit a store to the stack slot. Use a truncstore if the input value is
5385 // later than DestVT.
5388 if (SrcSize > SlotSize)
5389 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
5390 PseudoSourceValue::getFixedStack(SPFI), 0,
5391 SlotVT, false, SrcAlign);
5393 assert(SrcSize == SlotSize && "Invalid store");
5394 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
5395 PseudoSourceValue::getFixedStack(SPFI), 0,
5399 // Result is a load from the stack slot.
5400 if (SlotSize == DestSize)
5401 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
5403 assert(SlotSize < DestSize && "Unknown extension!");
5404 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
5408 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
5409 // Create a vector sized/aligned stack slot, store the value to element #0,
5410 // then load the whole vector back out.
5411 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
5413 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
5414 int SPFI = StackPtrFI->getIndex();
5416 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
5417 PseudoSourceValue::getFixedStack(SPFI), 0);
5418 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
5419 PseudoSourceValue::getFixedStack(SPFI), 0);
5423 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
5424 /// support the operation, but do support the resultant vector type.
5425 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
5427 // If the only non-undef value is the low element, turn this into a
5428 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
5429 unsigned NumElems = Node->getNumOperands();
5430 bool isOnlyLowElement = true;
5431 SDValue SplatValue = Node->getOperand(0);
5433 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
5434 // and use a bitmask instead of a list of elements.
5435 std::map<SDValue, std::vector<unsigned> > Values;
5436 Values[SplatValue].push_back(0);
5437 bool isConstant = true;
5438 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
5439 SplatValue.getOpcode() != ISD::UNDEF)
5442 for (unsigned i = 1; i < NumElems; ++i) {
5443 SDValue V = Node->getOperand(i);
5444 Values[V].push_back(i);
5445 if (V.getOpcode() != ISD::UNDEF)
5446 isOnlyLowElement = false;
5447 if (SplatValue != V)
5448 SplatValue = SDValue(0,0);
5450 // If this isn't a constant element or an undef, we can't use a constant
5452 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
5453 V.getOpcode() != ISD::UNDEF)
5457 if (isOnlyLowElement) {
5458 // If the low element is an undef too, then this whole things is an undef.
5459 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
5460 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
5461 // Otherwise, turn this into a scalar_to_vector node.
5462 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
5463 Node->getOperand(0));
5466 // If all elements are constants, create a load from the constant pool.
5468 MVT VT = Node->getValueType(0);
5469 std::vector<Constant*> CV;
5470 for (unsigned i = 0, e = NumElems; i != e; ++i) {
5471 if (ConstantFPSDNode *V =
5472 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
5473 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
5474 } else if (ConstantSDNode *V =
5475 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
5476 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
5478 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
5480 Node->getOperand(0).getValueType().getTypeForMVT();
5481 CV.push_back(UndefValue::get(OpNTy));
5484 Constant *CP = ConstantVector::get(CV);
5485 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5486 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5487 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
5488 PseudoSourceValue::getConstantPool(), 0,
5492 if (SplatValue.getNode()) { // Splat of one value?
5493 // Build the shuffle constant vector: <0, 0, 0, 0>
5494 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5495 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5496 std::vector<SDValue> ZeroVec(NumElems, Zero);
5497 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5498 &ZeroVec[0], ZeroVec.size());
5500 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5501 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5502 // Get the splatted value into the low element of a vector register.
5504 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
5506 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5507 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
5508 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
5513 // If there are only two unique elements, we may be able to turn this into a
5515 if (Values.size() == 2) {
5516 // Get the two values in deterministic order.
5517 SDValue Val1 = Node->getOperand(1);
5519 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5520 if (MI->first != Val1)
5523 Val2 = (++MI)->first;
5525 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5526 // vector shuffle has the undef vector on the RHS.
5527 if (Val1.getOpcode() == ISD::UNDEF)
5528 std::swap(Val1, Val2);
5530 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5531 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5532 MVT MaskEltVT = MaskVT.getVectorElementType();
5533 std::vector<SDValue> MaskVec(NumElems);
5535 // Set elements of the shuffle mask for Val1.
5536 std::vector<unsigned> &Val1Elts = Values[Val1];
5537 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5538 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5540 // Set elements of the shuffle mask for Val2.
5541 std::vector<unsigned> &Val2Elts = Values[Val2];
5542 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5543 if (Val2.getOpcode() != ISD::UNDEF)
5544 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5546 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
5548 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5549 &MaskVec[0], MaskVec.size());
5551 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5552 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5553 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5554 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
5555 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
5556 SDValue Ops[] = { Val1, Val2, ShuffleMask };
5558 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5559 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5563 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5564 // aligned object on the stack, store each element into it, then load
5565 // the result as a vector.
5566 MVT VT = Node->getValueType(0);
5567 // Create the stack frame object.
5568 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5570 // Emit a store of each element to the stack slot.
5571 SmallVector<SDValue, 8> Stores;
5572 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5573 // Store (in the right endianness) the elements to memory.
5574 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5575 // Ignore undef elements.
5576 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5578 unsigned Offset = TypeByteSize*i;
5580 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5581 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5583 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5588 if (!Stores.empty()) // Not all undef elements?
5589 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5590 &Stores[0], Stores.size());
5592 StoreChain = DAG.getEntryNode();
5594 // Result is a load from the stack slot.
5595 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5598 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5599 SDValue Op, SDValue Amt,
5600 SDValue &Lo, SDValue &Hi) {
5601 // Expand the subcomponents.
5603 ExpandOp(Op, LHSL, LHSH);
5605 SDValue Ops[] = { LHSL, LHSH, Amt };
5606 MVT VT = LHSL.getValueType();
5607 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5608 Hi = Lo.getValue(1);
5612 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5613 /// smaller elements. If we can't find a way that is more efficient than a
5614 /// libcall on this target, return false. Otherwise, return true with the
5615 /// low-parts expanded into Lo and Hi.
5616 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5617 SDValue &Lo, SDValue &Hi) {
5618 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5619 "This is not a shift!");
5621 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5622 SDValue ShAmt = LegalizeOp(Amt);
5623 MVT ShTy = ShAmt.getValueType();
5624 unsigned ShBits = ShTy.getSizeInBits();
5625 unsigned VTBits = Op.getValueType().getSizeInBits();
5626 unsigned NVTBits = NVT.getSizeInBits();
5628 // Handle the case when Amt is an immediate.
5629 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5630 unsigned Cst = CN->getZExtValue();
5631 // Expand the incoming operand to be shifted, so that we have its parts
5633 ExpandOp(Op, InL, InH);
5637 Lo = DAG.getConstant(0, NVT);
5638 Hi = DAG.getConstant(0, NVT);
5639 } else if (Cst > NVTBits) {
5640 Lo = DAG.getConstant(0, NVT);
5641 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5642 } else if (Cst == NVTBits) {
5643 Lo = DAG.getConstant(0, NVT);
5646 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5647 Hi = DAG.getNode(ISD::OR, NVT,
5648 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5649 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5654 Lo = DAG.getConstant(0, NVT);
5655 Hi = DAG.getConstant(0, NVT);
5656 } else if (Cst > NVTBits) {
5657 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5658 Hi = DAG.getConstant(0, NVT);
5659 } else if (Cst == NVTBits) {
5661 Hi = DAG.getConstant(0, NVT);
5663 Lo = DAG.getNode(ISD::OR, NVT,
5664 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5665 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5666 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5671 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5672 DAG.getConstant(NVTBits-1, ShTy));
5673 } else if (Cst > NVTBits) {
5674 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5675 DAG.getConstant(Cst-NVTBits, ShTy));
5676 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5677 DAG.getConstant(NVTBits-1, ShTy));
5678 } else if (Cst == NVTBits) {
5680 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5681 DAG.getConstant(NVTBits-1, ShTy));
5683 Lo = DAG.getNode(ISD::OR, NVT,
5684 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5685 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5686 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5692 // Okay, the shift amount isn't constant. However, if we can tell that it is
5693 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5694 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5695 APInt KnownZero, KnownOne;
5696 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5698 // If we know that if any of the high bits of the shift amount are one, then
5699 // we can do this as a couple of simple shifts.
5700 if (KnownOne.intersects(Mask)) {
5701 // Mask out the high bit, which we know is set.
5702 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5703 DAG.getConstant(~Mask, Amt.getValueType()));
5705 // Expand the incoming operand to be shifted, so that we have its parts
5707 ExpandOp(Op, InL, InH);
5710 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5711 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5714 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5715 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5718 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5719 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5720 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5725 // If we know that the high bits of the shift amount are all zero, then we can
5726 // do this as a couple of simple shifts.
5727 if ((KnownZero & Mask) == Mask) {
5729 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5730 DAG.getConstant(NVTBits, Amt.getValueType()),
5733 // Expand the incoming operand to be shifted, so that we have its parts
5735 ExpandOp(Op, InL, InH);
5738 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5739 Hi = DAG.getNode(ISD::OR, NVT,
5740 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5741 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5744 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5745 Lo = DAG.getNode(ISD::OR, NVT,
5746 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5747 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5750 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5751 Lo = DAG.getNode(ISD::OR, NVT,
5752 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5753 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5762 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5763 // does not fit into a register, return the lo part and set the hi part to the
5764 // by-reg argument. If it does fit into a single register, return the result
5765 // and leave the Hi part unset.
5766 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5767 bool isSigned, SDValue &Hi) {
5768 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5769 // The input chain to this libcall is the entry node of the function.
5770 // Legalizing the call will automatically add the previous call to the
5772 SDValue InChain = DAG.getEntryNode();
5774 TargetLowering::ArgListTy Args;
5775 TargetLowering::ArgListEntry Entry;
5776 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5777 MVT ArgVT = Node->getOperand(i).getValueType();
5778 const Type *ArgTy = ArgVT.getTypeForMVT();
5779 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5780 Entry.isSExt = isSigned;
5781 Entry.isZExt = !isSigned;
5782 Args.push_back(Entry);
5784 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5785 TLI.getPointerTy());
5787 // Splice the libcall in wherever FindInputOutputChains tells us to.
5788 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5789 std::pair<SDValue,SDValue> CallInfo =
5790 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5791 CallingConv::C, false, Callee, Args, DAG);
5793 // Legalize the call sequence, starting with the chain. This will advance
5794 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5795 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5796 LegalizeOp(CallInfo.second);
5798 switch (getTypeAction(CallInfo.first.getValueType())) {
5799 default: assert(0 && "Unknown thing");
5801 Result = CallInfo.first;
5804 ExpandOp(CallInfo.first, Result, Hi);
5810 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5812 SDValue SelectionDAGLegalize::
5813 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) {
5814 bool isCustom = false;
5816 switch (getTypeAction(Op.getValueType())) {
5818 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5819 Op.getValueType())) {
5820 default: assert(0 && "Unknown operation action!");
5821 case TargetLowering::Custom:
5824 case TargetLowering::Legal:
5825 Tmp1 = LegalizeOp(Op);
5826 if (Result.getNode())
5827 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5829 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5832 Tmp1 = TLI.LowerOperation(Result, DAG);
5833 if (Tmp1.getNode()) Result = Tmp1;
5836 case TargetLowering::Expand:
5837 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy);
5839 case TargetLowering::Promote:
5840 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned);
5845 Result = ExpandIntToFP(isSigned, DestTy, Op);
5848 Tmp1 = PromoteOp(Op);
5850 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
5851 Tmp1, DAG.getValueType(Op.getValueType()));
5853 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
5856 if (Result.getNode())
5857 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5859 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5861 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5867 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5869 SDValue SelectionDAGLegalize::
5870 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
5871 MVT SourceVT = Source.getValueType();
5872 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5874 // Expand unsupported int-to-fp vector casts by unrolling them.
5875 if (DestTy.isVector()) {
5877 return LegalizeOp(UnrollVectorOp(Source));
5878 MVT DestEltTy = DestTy.getVectorElementType();
5879 if (DestTy.getVectorNumElements() == 1) {
5880 SDValue Scalar = ScalarizeVectorOp(Source);
5881 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5883 return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result);
5886 SplitVectorOp(Source, Lo, Hi);
5887 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5888 DestTy.getVectorNumElements() / 2);
5889 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo);
5890 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi);
5891 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult,
5895 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5896 if (!isSigned && SourceVT != MVT::i32) {
5897 // The integer value loaded will be incorrectly if the 'sign bit' of the
5898 // incoming integer is set. To handle this, we dynamically test to see if
5899 // it is set, and, if so, add a fudge factor.
5903 ExpandOp(Source, Lo, Hi);
5904 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5906 // The comparison for the sign bit will use the entire operand.
5910 // Check to see if the target has a custom way to lower this. If so, use
5911 // it. (Note we've already expanded the operand in this case.)
5912 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) {
5913 default: assert(0 && "This action not implemented for this operation!");
5914 case TargetLowering::Legal:
5915 case TargetLowering::Expand:
5916 break; // This case is handled below.
5917 case TargetLowering::Custom: {
5918 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, DestTy,
5921 return LegalizeOp(NV);
5922 break; // The target decided this was legal after all
5926 // If this is unsigned, and not supported, first perform the conversion to
5927 // signed, then adjust the result if the sign bit is set.
5928 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
5930 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi.getValueType()),
5931 Hi, DAG.getConstant(0, Hi.getValueType()),
5933 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5934 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5935 SignSet, Four, Zero);
5936 uint64_t FF = 0x5f800000ULL;
5937 if (TLI.isLittleEndian()) FF <<= 32;
5938 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5940 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5941 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5942 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5943 Alignment = std::min(Alignment, 4u);
5945 if (DestTy == MVT::f32)
5946 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5947 PseudoSourceValue::getConstantPool(), 0,
5949 else if (DestTy.bitsGT(MVT::f32))
5950 // FIXME: Avoid the extend by construction the right constantpool?
5951 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5953 PseudoSourceValue::getConstantPool(), 0,
5954 MVT::f32, false, Alignment);
5956 assert(0 && "Unexpected conversion");
5958 MVT SCVT = SignedConv.getValueType();
5959 if (SCVT != DestTy) {
5960 // Destination type needs to be expanded as well. The FADD now we are
5961 // constructing will be expanded into a libcall.
5962 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5963 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5964 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5965 SignedConv, SignedConv.getValue(1));
5967 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5969 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5972 // Check to see if the target has a custom way to lower this. If so, use it.
5973 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5974 default: assert(0 && "This action not implemented for this operation!");
5975 case TargetLowering::Legal:
5976 case TargetLowering::Expand:
5977 break; // This case is handled below.
5978 case TargetLowering::Custom: {
5979 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5982 return LegalizeOp(NV);
5983 break; // The target decided this was legal after all
5987 // Expand the source, then glue it back together for the call. We must expand
5988 // the source in case it is shared (this pass of legalize must traverse it).
5990 SDValue SrcLo, SrcHi;
5991 ExpandOp(Source, SrcLo, SrcHi);
5992 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5995 RTLIB::Libcall LC = isSigned ?
5996 RTLIB::getSINTTOFP(SourceVT, DestTy) :
5997 RTLIB::getUINTTOFP(SourceVT, DestTy);
5998 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
6000 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
6002 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
6003 if (Result.getValueType() != DestTy && HiPart.getNode())
6004 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
6008 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
6009 /// INT_TO_FP operation of the specified operand when the target requests that
6010 /// we expand it. At this point, we know that the result and operand types are
6011 /// legal for the target.
6012 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
6015 if (Op0.getValueType() == MVT::i32) {
6016 // simple 32-bit [signed|unsigned] integer to float/double expansion
6018 // Get the stack frame index of a 8 byte buffer.
6019 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
6021 // word offset constant for Hi/Lo address computation
6022 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
6023 // set up Hi and Lo (into buffer) address based on endian
6024 SDValue Hi = StackSlot;
6025 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
6026 if (TLI.isLittleEndian())
6029 // if signed map to unsigned space
6032 // constant used to invert sign bit (signed to unsigned mapping)
6033 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
6034 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
6038 // store the lo of the constructed double - based on integer input
6039 SDValue Store1 = DAG.getStore(DAG.getEntryNode(),
6040 Op0Mapped, Lo, NULL, 0);
6041 // initial hi portion of constructed double
6042 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
6043 // store the hi of the constructed double - biased exponent
6044 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
6045 // load the constructed double
6046 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
6047 // FP constant to bias correct the final result
6048 SDValue Bias = DAG.getConstantFP(isSigned ?
6049 BitsToDouble(0x4330000080000000ULL)
6050 : BitsToDouble(0x4330000000000000ULL),
6052 // subtract the bias
6053 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
6056 // handle final rounding
6057 if (DestVT == MVT::f64) {
6060 } else if (DestVT.bitsLT(MVT::f64)) {
6061 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
6062 DAG.getIntPtrConstant(0));
6063 } else if (DestVT.bitsGT(MVT::f64)) {
6064 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
6068 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
6069 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
6071 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0.getValueType()),
6072 Op0, DAG.getConstant(0, Op0.getValueType()),
6074 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
6075 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
6076 SignSet, Four, Zero);
6078 // If the sign bit of the integer is set, the large number will be treated
6079 // as a negative number. To counteract this, the dynamic code adds an
6080 // offset depending on the data type.
6082 switch (Op0.getValueType().getSimpleVT()) {
6083 default: assert(0 && "Unsupported integer type!");
6084 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
6085 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
6086 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
6087 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
6089 if (TLI.isLittleEndian()) FF <<= 32;
6090 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
6092 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
6093 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6094 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
6095 Alignment = std::min(Alignment, 4u);
6097 if (DestVT == MVT::f32)
6098 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
6099 PseudoSourceValue::getConstantPool(), 0,
6103 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
6104 DAG.getEntryNode(), CPIdx,
6105 PseudoSourceValue::getConstantPool(), 0,
6106 MVT::f32, false, Alignment));
6109 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
6112 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
6113 /// *INT_TO_FP operation of the specified operand when the target requests that
6114 /// we promote it. At this point, we know that the result and operand types are
6115 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
6116 /// operation that takes a larger input.
6117 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
6120 // First step, figure out the appropriate *INT_TO_FP operation to use.
6121 MVT NewInTy = LegalOp.getValueType();
6123 unsigned OpToUse = 0;
6125 // Scan for the appropriate larger type to use.
6127 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
6128 assert(NewInTy.isInteger() && "Ran out of possibilities!");
6130 // If the target supports SINT_TO_FP of this type, use it.
6131 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
6133 case TargetLowering::Legal:
6134 if (!TLI.isTypeLegal(NewInTy))
6135 break; // Can't use this datatype.
6137 case TargetLowering::Custom:
6138 OpToUse = ISD::SINT_TO_FP;
6142 if (isSigned) continue;
6144 // If the target supports UINT_TO_FP of this type, use it.
6145 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
6147 case TargetLowering::Legal:
6148 if (!TLI.isTypeLegal(NewInTy))
6149 break; // Can't use this datatype.
6151 case TargetLowering::Custom:
6152 OpToUse = ISD::UINT_TO_FP;
6157 // Otherwise, try a larger type.
6160 // Okay, we found the operation and type to use. Zero extend our input to the
6161 // desired type then run the operation on it.
6162 return DAG.getNode(OpToUse, DestVT,
6163 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
6167 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
6168 /// FP_TO_*INT operation of the specified operand when the target requests that
6169 /// we promote it. At this point, we know that the result and operand types are
6170 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
6171 /// operation that returns a larger result.
6172 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
6175 // First step, figure out the appropriate FP_TO*INT operation to use.
6176 MVT NewOutTy = DestVT;
6178 unsigned OpToUse = 0;
6180 // Scan for the appropriate larger type to use.
6182 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
6183 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
6185 // If the target supports FP_TO_SINT returning this type, use it.
6186 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
6188 case TargetLowering::Legal:
6189 if (!TLI.isTypeLegal(NewOutTy))
6190 break; // Can't use this datatype.
6192 case TargetLowering::Custom:
6193 OpToUse = ISD::FP_TO_SINT;
6198 // If the target supports FP_TO_UINT of this type, use it.
6199 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
6201 case TargetLowering::Legal:
6202 if (!TLI.isTypeLegal(NewOutTy))
6203 break; // Can't use this datatype.
6205 case TargetLowering::Custom:
6206 OpToUse = ISD::FP_TO_UINT;
6211 // Otherwise, try a larger type.
6215 // Okay, we found the operation and type to use.
6216 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
6218 // If the operation produces an invalid type, it must be custom lowered. Use
6219 // the target lowering hooks to expand it. Just keep the low part of the
6220 // expanded operation, we know that we're truncating anyway.
6221 if (getTypeAction(NewOutTy) == Expand) {
6222 SmallVector<SDValue, 2> Results;
6223 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG);
6224 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!");
6225 Operation = Results[0];
6228 // Truncate the result of the extended FP_TO_*INT operation to the desired
6230 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
6233 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
6235 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) {
6236 MVT VT = Op.getValueType();
6237 MVT SHVT = TLI.getShiftAmountTy();
6238 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
6239 switch (VT.getSimpleVT()) {
6240 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
6242 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6243 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6244 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
6246 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
6247 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6248 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6249 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
6250 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
6251 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
6252 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
6253 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
6254 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
6256 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
6257 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
6258 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
6259 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6260 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6261 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
6262 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
6263 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
6264 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
6265 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
6266 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
6267 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
6268 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
6269 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
6270 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
6271 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
6272 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
6273 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
6274 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
6275 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
6276 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
6280 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
6282 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
6284 default: assert(0 && "Cannot expand this yet!");
6286 static const uint64_t mask[6] = {
6287 0x5555555555555555ULL, 0x3333333333333333ULL,
6288 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
6289 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
6291 MVT VT = Op.getValueType();
6292 MVT ShVT = TLI.getShiftAmountTy();
6293 unsigned len = VT.getSizeInBits();
6294 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6295 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
6296 SDValue Tmp2 = DAG.getConstant(VT.getIntegerVTBitMask() & mask[i], VT);
6297 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6298 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
6299 DAG.getNode(ISD::AND, VT,
6300 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
6305 // for now, we do this:
6306 // x = x | (x >> 1);
6307 // x = x | (x >> 2);
6309 // x = x | (x >>16);
6310 // x = x | (x >>32); // for 64-bit input
6311 // return popcount(~x);
6313 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
6314 MVT VT = Op.getValueType();
6315 MVT ShVT = TLI.getShiftAmountTy();
6316 unsigned len = VT.getSizeInBits();
6317 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6318 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6319 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
6321 Op = DAG.getNOT(Op, VT);
6322 return DAG.getNode(ISD::CTPOP, VT, Op);
6325 // for now, we use: { return popcount(~x & (x - 1)); }
6326 // unless the target has ctlz but not ctpop, in which case we use:
6327 // { return 32 - nlz(~x & (x-1)); }
6328 // see also http://www.hackersdelight.org/HDcode/ntz.cc
6329 MVT VT = Op.getValueType();
6330 SDValue Tmp3 = DAG.getNode(ISD::AND, VT, DAG.getNOT(Op, VT),
6331 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
6332 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6333 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
6334 TLI.isOperationLegal(ISD::CTLZ, VT))
6335 return DAG.getNode(ISD::SUB, VT,
6336 DAG.getConstant(VT.getSizeInBits(), VT),
6337 DAG.getNode(ISD::CTLZ, VT, Tmp3));
6338 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
6343 /// ExpandOp - Expand the specified SDValue into its two component pieces
6344 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
6345 /// LegalizedNodes map is filled in for any results that are not expanded, the
6346 /// ExpandedNodes map is filled in for any results that are expanded, and the
6347 /// Lo/Hi values are returned.
6348 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
6349 MVT VT = Op.getValueType();
6350 MVT NVT = TLI.getTypeToTransformTo(VT);
6351 SDNode *Node = Op.getNode();
6352 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
6353 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
6354 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
6356 // See if we already expanded it.
6357 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
6358 = ExpandedNodes.find(Op);
6359 if (I != ExpandedNodes.end()) {
6360 Lo = I->second.first;
6361 Hi = I->second.second;
6365 switch (Node->getOpcode()) {
6366 case ISD::CopyFromReg:
6367 assert(0 && "CopyFromReg must be legal!");
6368 case ISD::FP_ROUND_INREG:
6369 if (VT == MVT::ppcf128 &&
6370 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
6371 TargetLowering::Custom) {
6372 SDValue SrcLo, SrcHi, Src;
6373 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
6374 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
6375 SDValue Result = TLI.LowerOperation(
6376 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
6377 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
6378 Lo = Result.getNode()->getOperand(0);
6379 Hi = Result.getNode()->getOperand(1);
6385 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
6387 assert(0 && "Do not know how to expand this operator!");
6389 case ISD::EXTRACT_ELEMENT:
6390 ExpandOp(Node->getOperand(0), Lo, Hi);
6391 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
6392 return ExpandOp(Hi, Lo, Hi);
6393 return ExpandOp(Lo, Lo, Hi);
6394 case ISD::EXTRACT_VECTOR_ELT:
6395 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
6396 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
6397 return ExpandOp(Lo, Lo, Hi);
6399 Lo = DAG.getNode(ISD::UNDEF, NVT);
6400 Hi = DAG.getNode(ISD::UNDEF, NVT);
6402 case ISD::Constant: {
6403 unsigned NVTBits = NVT.getSizeInBits();
6404 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
6405 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
6406 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
6409 case ISD::ConstantFP: {
6410 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
6411 if (CFP->getValueType(0) == MVT::ppcf128) {
6412 APInt api = CFP->getValueAPF().bitcastToAPInt();
6413 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
6415 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
6419 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
6420 if (getTypeAction(Lo.getValueType()) == Expand)
6421 ExpandOp(Lo, Lo, Hi);
6424 case ISD::BUILD_PAIR:
6425 // Return the operands.
6426 Lo = Node->getOperand(0);
6427 Hi = Node->getOperand(1);
6430 case ISD::MERGE_VALUES:
6431 if (Node->getNumValues() == 1) {
6432 ExpandOp(Op.getOperand(0), Lo, Hi);
6435 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
6436 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
6437 Op.getValue(1).getValueType() == MVT::Other &&
6438 "unhandled MERGE_VALUES");
6439 ExpandOp(Op.getOperand(0), Lo, Hi);
6440 // Remember that we legalized the chain.
6441 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
6444 case ISD::SIGN_EXTEND_INREG:
6445 ExpandOp(Node->getOperand(0), Lo, Hi);
6446 // sext_inreg the low part if needed.
6447 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
6449 // The high part gets the sign extension from the lo-part. This handles
6450 // things like sextinreg V:i64 from i8.
6451 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6452 DAG.getConstant(NVT.getSizeInBits()-1,
6453 TLI.getShiftAmountTy()));
6457 ExpandOp(Node->getOperand(0), Lo, Hi);
6458 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
6459 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
6465 ExpandOp(Node->getOperand(0), Lo, Hi);
6466 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
6467 DAG.getNode(ISD::CTPOP, NVT, Lo),
6468 DAG.getNode(ISD::CTPOP, NVT, Hi));
6469 Hi = DAG.getConstant(0, NVT);
6473 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
6474 ExpandOp(Node->getOperand(0), Lo, Hi);
6475 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6476 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
6477 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), HLZ, BitsC,
6479 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
6480 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
6482 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
6483 Hi = DAG.getConstant(0, NVT);
6488 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
6489 ExpandOp(Node->getOperand(0), Lo, Hi);
6490 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6491 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
6492 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), LTZ, BitsC,
6494 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
6495 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
6497 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
6498 Hi = DAG.getConstant(0, NVT);
6503 SDValue Ch = Node->getOperand(0); // Legalize the chain.
6504 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6505 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
6506 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
6508 // Remember that we legalized the chain.
6509 Hi = LegalizeOp(Hi);
6510 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6511 if (TLI.isBigEndian())
6517 LoadSDNode *LD = cast<LoadSDNode>(Node);
6518 SDValue Ch = LD->getChain(); // Legalize the chain.
6519 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6520 ISD::LoadExtType ExtType = LD->getExtensionType();
6521 const Value *SV = LD->getSrcValue();
6522 int SVOffset = LD->getSrcValueOffset();
6523 unsigned Alignment = LD->getAlignment();
6524 bool isVolatile = LD->isVolatile();
6526 if (ExtType == ISD::NON_EXTLOAD) {
6527 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6528 isVolatile, Alignment);
6529 if (VT == MVT::f32 || VT == MVT::f64) {
6530 // f32->i32 or f64->i64 one to one expansion.
6531 // Remember that we legalized the chain.
6532 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6533 // Recursively expand the new load.
6534 if (getTypeAction(NVT) == Expand)
6535 ExpandOp(Lo, Lo, Hi);
6539 // Increment the pointer to the other half.
6540 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6541 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6542 DAG.getIntPtrConstant(IncrementSize));
6543 SVOffset += IncrementSize;
6544 Alignment = MinAlign(Alignment, IncrementSize);
6545 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6546 isVolatile, Alignment);
6548 // Build a factor node to remember that this load is independent of the
6550 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6553 // Remember that we legalized the chain.
6554 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6555 if (TLI.isBigEndian())
6558 MVT EVT = LD->getMemoryVT();
6560 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6561 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6562 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6563 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV,
6564 SVOffset, isVolatile, Alignment);
6565 // Remember that we legalized the chain.
6566 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6567 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
6572 Lo = DAG.getLoad(NVT, Ch, Ptr, SV,
6573 SVOffset, isVolatile, Alignment);
6575 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV,
6576 SVOffset, EVT, isVolatile,
6579 // Remember that we legalized the chain.
6580 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6582 if (ExtType == ISD::SEXTLOAD) {
6583 // The high part is obtained by SRA'ing all but one of the bits of the
6585 unsigned LoSize = Lo.getValueType().getSizeInBits();
6586 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6587 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6588 } else if (ExtType == ISD::ZEXTLOAD) {
6589 // The high part is just a zero.
6590 Hi = DAG.getConstant(0, NVT);
6591 } else /* if (ExtType == ISD::EXTLOAD) */ {
6592 // The high part is undefined.
6593 Hi = DAG.getNode(ISD::UNDEF, NVT);
6600 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6601 SDValue LL, LH, RL, RH;
6602 ExpandOp(Node->getOperand(0), LL, LH);
6603 ExpandOp(Node->getOperand(1), RL, RH);
6604 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
6605 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
6609 SDValue LL, LH, RL, RH;
6610 ExpandOp(Node->getOperand(1), LL, LH);
6611 ExpandOp(Node->getOperand(2), RL, RH);
6612 if (getTypeAction(NVT) == Expand)
6613 NVT = TLI.getTypeToExpandTo(NVT);
6614 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
6616 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
6619 case ISD::SELECT_CC: {
6620 SDValue TL, TH, FL, FH;
6621 ExpandOp(Node->getOperand(2), TL, TH);
6622 ExpandOp(Node->getOperand(3), FL, FH);
6623 if (getTypeAction(NVT) == Expand)
6624 NVT = TLI.getTypeToExpandTo(NVT);
6625 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6626 Node->getOperand(1), TL, FL, Node->getOperand(4));
6628 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6629 Node->getOperand(1), TH, FH, Node->getOperand(4));
6632 case ISD::ANY_EXTEND:
6633 // The low part is any extension of the input (which degenerates to a copy).
6634 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6635 // The high part is undefined.
6636 Hi = DAG.getNode(ISD::UNDEF, NVT);
6638 case ISD::SIGN_EXTEND: {
6639 // The low part is just a sign extension of the input (which degenerates to
6641 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6643 // The high part is obtained by SRA'ing all but one of the bits of the lo
6645 unsigned LoSize = Lo.getValueType().getSizeInBits();
6646 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6647 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6650 case ISD::ZERO_EXTEND:
6651 // The low part is just a zero extension of the input (which degenerates to
6653 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6655 // The high part is just a zero.
6656 Hi = DAG.getConstant(0, NVT);
6659 case ISD::TRUNCATE: {
6660 // The input value must be larger than this value. Expand *it*.
6662 ExpandOp(Node->getOperand(0), NewLo, Hi);
6664 // The low part is now either the right size, or it is closer. If not the
6665 // right size, make an illegal truncate so we recursively expand it.
6666 if (NewLo.getValueType() != Node->getValueType(0))
6667 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6668 ExpandOp(NewLo, Lo, Hi);
6672 case ISD::BIT_CONVERT: {
6674 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6675 // If the target wants to, allow it to lower this itself.
6676 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6677 case Expand: assert(0 && "cannot expand FP!");
6678 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6679 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6681 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6684 // f32 / f64 must be expanded to i32 / i64.
6685 if (VT == MVT::f32 || VT == MVT::f64) {
6686 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6687 if (getTypeAction(NVT) == Expand)
6688 ExpandOp(Lo, Lo, Hi);
6692 // If source operand will be expanded to the same type as VT, i.e.
6693 // i64 <- f64, i32 <- f32, expand the source operand instead.
6694 MVT VT0 = Node->getOperand(0).getValueType();
6695 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6696 ExpandOp(Node->getOperand(0), Lo, Hi);
6700 // Turn this into a load/store pair by default.
6701 if (Tmp.getNode() == 0)
6702 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6704 ExpandOp(Tmp, Lo, Hi);
6708 case ISD::READCYCLECOUNTER: {
6709 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6710 TargetLowering::Custom &&
6711 "Must custom expand ReadCycleCounter");
6712 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6713 assert(Tmp.getNode() && "Node must be custom expanded!");
6714 ExpandOp(Tmp.getValue(0), Lo, Hi);
6715 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6716 LegalizeOp(Tmp.getValue(1)));
6720 case ISD::ATOMIC_CMP_SWAP: {
6721 // This operation does not need a loop.
6722 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6723 assert(Tmp.getNode() && "Node must be custom expanded!");
6724 ExpandOp(Tmp.getValue(0), Lo, Hi);
6725 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6726 LegalizeOp(Tmp.getValue(1)));
6730 case ISD::ATOMIC_LOAD_ADD:
6731 case ISD::ATOMIC_LOAD_SUB:
6732 case ISD::ATOMIC_LOAD_AND:
6733 case ISD::ATOMIC_LOAD_OR:
6734 case ISD::ATOMIC_LOAD_XOR:
6735 case ISD::ATOMIC_LOAD_NAND:
6736 case ISD::ATOMIC_SWAP: {
6737 // These operations require a loop to be generated. We can't do that yet,
6738 // so substitute a target-dependent pseudo and expand that later.
6739 SDValue In2Lo, In2Hi, In2;
6740 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6741 In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi);
6742 AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
6744 DAG.getAtomic(Op.getOpcode(), Anode->getMemoryVT(),
6745 Op.getOperand(0), Op.getOperand(1), In2,
6746 Anode->getSrcValue(), Anode->getAlignment());
6747 SDValue Result = TLI.LowerOperation(Replace, DAG);
6748 ExpandOp(Result.getValue(0), Lo, Hi);
6749 // Remember that we legalized the chain.
6750 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
6754 // These operators cannot be expanded directly, emit them as calls to
6755 // library functions.
6756 case ISD::FP_TO_SINT: {
6757 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6759 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6760 case Expand: assert(0 && "cannot expand FP!");
6761 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6762 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6765 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6767 // Now that the custom expander is done, expand the result, which is still
6770 ExpandOp(Op, Lo, Hi);
6775 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6777 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6778 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6782 case ISD::FP_TO_UINT: {
6783 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6785 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6786 case Expand: assert(0 && "cannot expand FP!");
6787 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6788 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6791 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6793 // Now that the custom expander is done, expand the result.
6795 ExpandOp(Op, Lo, Hi);
6800 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6802 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6803 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6808 // If the target wants custom lowering, do so.
6809 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6810 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6811 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6812 Op = TLI.LowerOperation(Op, DAG);
6814 // Now that the custom expander is done, expand the result, which is
6816 ExpandOp(Op, Lo, Hi);
6821 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6822 // this X << 1 as X+X.
6823 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6824 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6825 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6826 SDValue LoOps[2], HiOps[3];
6827 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6828 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6829 LoOps[1] = LoOps[0];
6830 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6832 HiOps[1] = HiOps[0];
6833 HiOps[2] = Lo.getValue(1);
6834 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6839 // If we can emit an efficient shift operation, do so now.
6840 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6843 // If this target supports SHL_PARTS, use it.
6844 TargetLowering::LegalizeAction Action =
6845 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6846 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6847 Action == TargetLowering::Custom) {
6848 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6852 // Otherwise, emit a libcall.
6853 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6858 // If the target wants custom lowering, do so.
6859 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6860 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6861 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6862 Op = TLI.LowerOperation(Op, DAG);
6864 // Now that the custom expander is done, expand the result, which is
6866 ExpandOp(Op, Lo, Hi);
6871 // If we can emit an efficient shift operation, do so now.
6872 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6875 // If this target supports SRA_PARTS, use it.
6876 TargetLowering::LegalizeAction Action =
6877 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6878 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6879 Action == TargetLowering::Custom) {
6880 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6884 // Otherwise, emit a libcall.
6885 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6890 // If the target wants custom lowering, do so.
6891 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6892 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6893 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6894 Op = TLI.LowerOperation(Op, DAG);
6896 // Now that the custom expander is done, expand the result, which is
6898 ExpandOp(Op, Lo, Hi);
6903 // If we can emit an efficient shift operation, do so now.
6904 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6907 // If this target supports SRL_PARTS, use it.
6908 TargetLowering::LegalizeAction Action =
6909 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6910 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6911 Action == TargetLowering::Custom) {
6912 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6916 // Otherwise, emit a libcall.
6917 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6923 // If the target wants to custom expand this, let them.
6924 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6925 TargetLowering::Custom) {
6926 SDValue Result = TLI.LowerOperation(Op, DAG);
6927 if (Result.getNode()) {
6928 ExpandOp(Result, Lo, Hi);
6932 // Expand the subcomponents.
6933 SDValue LHSL, LHSH, RHSL, RHSH;
6934 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6935 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6936 SDValue LoOps[2], HiOps[3];
6942 //cascaded check to see if any smaller size has a a carry flag.
6943 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
6944 bool hasCarry = false;
6945 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
6946 MVT AVT = MVT::getIntegerVT(BitSize);
6947 if (TLI.isOperationLegal(OpV, AVT)) {
6954 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6955 if (Node->getOpcode() == ISD::ADD) {
6956 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6957 HiOps[2] = Lo.getValue(1);
6958 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6960 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6961 HiOps[2] = Lo.getValue(1);
6962 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6966 if (Node->getOpcode() == ISD::ADD) {
6967 Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2);
6968 Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2);
6969 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(NVT),
6970 Lo, LoOps[0], ISD::SETULT);
6971 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
6972 DAG.getConstant(1, NVT),
6973 DAG.getConstant(0, NVT));
6974 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(NVT),
6975 Lo, LoOps[1], ISD::SETULT);
6976 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
6977 DAG.getConstant(1, NVT),
6979 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
6981 Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2);
6982 Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2);
6983 SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT);
6984 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
6985 DAG.getConstant(1, NVT),
6986 DAG.getConstant(0, NVT));
6987 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow);
6995 // Expand the subcomponents.
6996 SDValue LHSL, LHSH, RHSL, RHSH;
6997 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6998 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6999 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7000 SDValue LoOps[2] = { LHSL, RHSL };
7001 SDValue HiOps[3] = { LHSH, RHSH };
7003 if (Node->getOpcode() == ISD::ADDC) {
7004 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
7005 HiOps[2] = Lo.getValue(1);
7006 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
7008 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
7009 HiOps[2] = Lo.getValue(1);
7010 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
7012 // Remember that we legalized the flag.
7013 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7018 // Expand the subcomponents.
7019 SDValue LHSL, LHSH, RHSL, RHSH;
7020 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7021 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7022 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7023 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
7024 SDValue HiOps[3] = { LHSH, RHSH };
7026 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
7027 HiOps[2] = Lo.getValue(1);
7028 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
7030 // Remember that we legalized the flag.
7031 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7035 // If the target wants to custom expand this, let them.
7036 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
7037 SDValue New = TLI.LowerOperation(Op, DAG);
7038 if (New.getNode()) {
7039 ExpandOp(New, Lo, Hi);
7044 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
7045 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
7046 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
7047 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
7048 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
7049 SDValue LL, LH, RL, RH;
7050 ExpandOp(Node->getOperand(0), LL, LH);
7051 ExpandOp(Node->getOperand(1), RL, RH);
7052 unsigned OuterBitSize = Op.getValueSizeInBits();
7053 unsigned InnerBitSize = RH.getValueSizeInBits();
7054 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
7055 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
7056 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
7057 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
7058 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
7059 // The inputs are both zero-extended.
7061 // We can emit a umul_lohi.
7062 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
7063 Hi = SDValue(Lo.getNode(), 1);
7067 // We can emit a mulhu+mul.
7068 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
7069 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
7073 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
7074 // The input values are both sign-extended.
7076 // We can emit a smul_lohi.
7077 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
7078 Hi = SDValue(Lo.getNode(), 1);
7082 // We can emit a mulhs+mul.
7083 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
7084 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
7089 // Lo,Hi = umul LHS, RHS.
7090 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
7091 DAG.getVTList(NVT, NVT), LL, RL);
7093 Hi = UMulLOHI.getValue(1);
7094 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
7095 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
7096 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
7097 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
7101 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
7102 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
7103 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
7104 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
7105 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
7106 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
7111 // If nothing else, we can make a libcall.
7112 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
7116 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
7119 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
7122 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
7125 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
7129 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
7132 RTLIB::ADD_PPCF128),
7136 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
7139 RTLIB::SUB_PPCF128),
7143 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
7146 RTLIB::MUL_PPCF128),
7150 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
7153 RTLIB::DIV_PPCF128),
7156 case ISD::FP_EXTEND: {
7157 if (VT == MVT::ppcf128) {
7158 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
7159 Node->getOperand(0).getValueType()==MVT::f64);
7160 const uint64_t zero = 0;
7161 if (Node->getOperand(0).getValueType()==MVT::f32)
7162 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
7164 Hi = Node->getOperand(0);
7165 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7168 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
7169 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
7170 Lo = ExpandLibCall(LC, Node, true, Hi);
7173 case ISD::FP_ROUND: {
7174 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
7176 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
7177 Lo = ExpandLibCall(LC, Node, true, Hi);
7192 case ISD::FNEARBYINT:
7195 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
7196 switch(Node->getOpcode()) {
7198 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
7199 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
7202 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
7203 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
7206 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
7207 RTLIB::COS_F80, RTLIB::COS_PPCF128);
7210 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
7211 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
7214 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
7215 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
7218 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
7219 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
7222 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
7223 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
7226 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
7227 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
7230 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
7231 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
7234 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
7235 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
7238 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
7239 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
7242 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
7243 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
7245 case ISD::FNEARBYINT:
7246 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
7247 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
7250 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
7251 RTLIB::POW_PPCF128);
7254 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
7255 RTLIB::POWI_PPCF128);
7257 default: assert(0 && "Unreachable!");
7259 Lo = ExpandLibCall(LC, Node, false, Hi);
7263 if (VT == MVT::ppcf128) {
7265 ExpandOp(Node->getOperand(0), Lo, Tmp);
7266 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
7267 // lo = hi==fabs(hi) ? lo : -lo;
7268 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
7269 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
7270 DAG.getCondCode(ISD::SETEQ));
7273 SDValue Mask = (VT == MVT::f64)
7274 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
7275 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
7276 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
7277 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
7278 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
7279 if (getTypeAction(NVT) == Expand)
7280 ExpandOp(Lo, Lo, Hi);
7284 if (VT == MVT::ppcf128) {
7285 ExpandOp(Node->getOperand(0), Lo, Hi);
7286 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
7287 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
7290 SDValue Mask = (VT == MVT::f64)
7291 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
7292 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
7293 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
7294 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
7295 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
7296 if (getTypeAction(NVT) == Expand)
7297 ExpandOp(Lo, Lo, Hi);
7300 case ISD::FCOPYSIGN: {
7301 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
7302 if (getTypeAction(NVT) == Expand)
7303 ExpandOp(Lo, Lo, Hi);
7306 case ISD::SINT_TO_FP:
7307 case ISD::UINT_TO_FP: {
7308 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
7309 MVT SrcVT = Node->getOperand(0).getValueType();
7311 // Promote the operand if needed. Do this before checking for
7312 // ppcf128 so conversions of i16 and i8 work.
7313 if (getTypeAction(SrcVT) == Promote) {
7314 SDValue Tmp = PromoteOp(Node->getOperand(0));
7316 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
7317 DAG.getValueType(SrcVT))
7318 : DAG.getZeroExtendInReg(Tmp, SrcVT);
7319 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
7320 SrcVT = Node->getOperand(0).getValueType();
7323 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
7324 static const uint64_t zero = 0;
7326 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
7327 Node->getOperand(0)));
7328 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7330 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
7331 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
7332 Node->getOperand(0)));
7333 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7334 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
7335 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
7336 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
7337 DAG.getConstant(0, MVT::i32),
7338 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
7340 APFloat(APInt(128, 2, TwoE32)),
7343 DAG.getCondCode(ISD::SETLT)),
7348 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
7349 // si64->ppcf128 done by libcall, below
7350 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
7351 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
7353 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
7354 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
7355 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
7356 DAG.getConstant(0, MVT::i64),
7357 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
7359 APFloat(APInt(128, 2, TwoE64)),
7362 DAG.getCondCode(ISD::SETLT)),
7367 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
7368 Node->getOperand(0));
7369 if (getTypeAction(Lo.getValueType()) == Expand)
7370 // float to i32 etc. can be 'expanded' to a single node.
7371 ExpandOp(Lo, Lo, Hi);
7376 // Make sure the resultant values have been legalized themselves, unless this
7377 // is a type that requires multi-step expansion.
7378 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
7379 Lo = LegalizeOp(Lo);
7381 // Don't legalize the high part if it is expanded to a single node.
7382 Hi = LegalizeOp(Hi);
7385 // Remember in a map if the values will be reused later.
7387 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7388 assert(isNew && "Value already expanded?!?");
7392 /// SplitVectorOp - Given an operand of vector type, break it down into
7393 /// two smaller values, still of vector type.
7394 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
7396 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
7397 SDNode *Node = Op.getNode();
7398 unsigned NumElements = Op.getValueType().getVectorNumElements();
7399 assert(NumElements > 1 && "Cannot split a single element vector!");
7401 MVT NewEltVT = Op.getValueType().getVectorElementType();
7403 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
7404 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
7406 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
7407 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
7409 // See if we already split it.
7410 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
7411 = SplitNodes.find(Op);
7412 if (I != SplitNodes.end()) {
7413 Lo = I->second.first;
7414 Hi = I->second.second;
7418 switch (Node->getOpcode()) {
7423 assert(0 && "Unhandled operation in SplitVectorOp!");
7425 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
7426 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
7428 case ISD::BUILD_PAIR:
7429 Lo = Node->getOperand(0);
7430 Hi = Node->getOperand(1);
7432 case ISD::INSERT_VECTOR_ELT: {
7433 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
7434 SplitVectorOp(Node->getOperand(0), Lo, Hi);
7435 unsigned Index = Idx->getZExtValue();
7436 SDValue ScalarOp = Node->getOperand(1);
7437 if (Index < NewNumElts_Lo)
7438 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
7439 DAG.getIntPtrConstant(Index));
7441 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
7442 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
7445 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
7446 Node->getOperand(1),
7447 Node->getOperand(2));
7448 SplitVectorOp(Tmp, Lo, Hi);
7451 case ISD::VECTOR_SHUFFLE: {
7452 // Build the low part.
7453 SDValue Mask = Node->getOperand(2);
7454 SmallVector<SDValue, 8> Ops;
7455 MVT PtrVT = TLI.getPointerTy();
7457 // Insert all of the elements from the input that are needed. We use
7458 // buildvector of extractelement here because the input vectors will have
7459 // to be legalized, so this makes the code simpler.
7460 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
7461 SDValue IdxNode = Mask.getOperand(i);
7462 if (IdxNode.getOpcode() == ISD::UNDEF) {
7463 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
7466 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7467 SDValue InVec = Node->getOperand(0);
7468 if (Idx >= NumElements) {
7469 InVec = Node->getOperand(1);
7472 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
7473 DAG.getConstant(Idx, PtrVT)));
7475 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
7478 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
7479 SDValue IdxNode = Mask.getOperand(i);
7480 if (IdxNode.getOpcode() == ISD::UNDEF) {
7481 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
7484 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7485 SDValue InVec = Node->getOperand(0);
7486 if (Idx >= NumElements) {
7487 InVec = Node->getOperand(1);
7490 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
7491 DAG.getConstant(Idx, PtrVT)));
7493 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size());
7496 case ISD::BUILD_VECTOR: {
7497 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7498 Node->op_begin()+NewNumElts_Lo);
7499 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
7501 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
7503 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
7506 case ISD::CONCAT_VECTORS: {
7507 // FIXME: Handle non-power-of-two vectors?
7508 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
7509 if (NewNumSubvectors == 1) {
7510 Lo = Node->getOperand(0);
7511 Hi = Node->getOperand(1);
7513 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7514 Node->op_begin()+NewNumSubvectors);
7515 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
7517 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
7519 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
7523 case ISD::EXTRACT_SUBVECTOR: {
7524 SDValue Vec = Op.getOperand(0);
7525 SDValue Idx = Op.getOperand(1);
7526 MVT IdxVT = Idx.getValueType();
7528 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Lo, Vec, Idx);
7529 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
7531 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec,
7532 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo,
7535 Idx = DAG.getNode(ISD::ADD, IdxVT, Idx,
7536 DAG.getConstant(NewNumElts_Lo, IdxVT));
7537 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec, Idx);
7542 SDValue Cond = Node->getOperand(0);
7544 SDValue LL, LH, RL, RH;
7545 SplitVectorOp(Node->getOperand(1), LL, LH);
7546 SplitVectorOp(Node->getOperand(2), RL, RH);
7548 if (Cond.getValueType().isVector()) {
7549 // Handle a vector merge.
7551 SplitVectorOp(Cond, CL, CH);
7552 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
7553 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
7555 // Handle a simple select with vector operands.
7556 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
7557 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
7561 case ISD::SELECT_CC: {
7562 SDValue CondLHS = Node->getOperand(0);
7563 SDValue CondRHS = Node->getOperand(1);
7564 SDValue CondCode = Node->getOperand(4);
7566 SDValue LL, LH, RL, RH;
7567 SplitVectorOp(Node->getOperand(2), LL, LH);
7568 SplitVectorOp(Node->getOperand(3), RL, RH);
7570 // Handle a simple select with vector operands.
7571 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
7573 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
7578 SDValue LL, LH, RL, RH;
7579 SplitVectorOp(Node->getOperand(0), LL, LH);
7580 SplitVectorOp(Node->getOperand(1), RL, RH);
7581 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
7582 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
7604 SDValue LL, LH, RL, RH;
7605 SplitVectorOp(Node->getOperand(0), LL, LH);
7606 SplitVectorOp(Node->getOperand(1), RL, RH);
7608 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
7609 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
7615 SplitVectorOp(Node->getOperand(0), L, H);
7617 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
7618 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
7634 case ISD::FP_TO_SINT:
7635 case ISD::FP_TO_UINT:
7636 case ISD::SINT_TO_FP:
7637 case ISD::UINT_TO_FP:
7639 case ISD::ANY_EXTEND:
7640 case ISD::SIGN_EXTEND:
7641 case ISD::ZERO_EXTEND:
7642 case ISD::FP_EXTEND: {
7644 SplitVectorOp(Node->getOperand(0), L, H);
7646 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
7647 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
7650 case ISD::CONVERT_RNDSAT: {
7651 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
7653 SplitVectorOp(Node->getOperand(0), L, H);
7654 SDValue DTyOpL = DAG.getValueType(NewVT_Lo);
7655 SDValue DTyOpH = DAG.getValueType(NewVT_Hi);
7656 SDValue STyOpL = DAG.getValueType(L.getValueType());
7657 SDValue STyOpH = DAG.getValueType(H.getValueType());
7659 SDValue RndOp = Node->getOperand(3);
7660 SDValue SatOp = Node->getOperand(4);
7662 Lo = DAG.getConvertRndSat(NewVT_Lo, L, DTyOpL, STyOpL,
7663 RndOp, SatOp, CvtCode);
7664 Hi = DAG.getConvertRndSat(NewVT_Hi, H, DTyOpH, STyOpH,
7665 RndOp, SatOp, CvtCode);
7669 LoadSDNode *LD = cast<LoadSDNode>(Node);
7670 SDValue Ch = LD->getChain();
7671 SDValue Ptr = LD->getBasePtr();
7672 ISD::LoadExtType ExtType = LD->getExtensionType();
7673 const Value *SV = LD->getSrcValue();
7674 int SVOffset = LD->getSrcValueOffset();
7675 MVT MemoryVT = LD->getMemoryVT();
7676 unsigned Alignment = LD->getAlignment();
7677 bool isVolatile = LD->isVolatile();
7679 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7680 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7682 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7683 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7684 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7686 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType,
7687 NewVT_Lo, Ch, Ptr, Offset,
7688 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7689 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7690 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
7691 DAG.getIntPtrConstant(IncrementSize));
7692 SVOffset += IncrementSize;
7693 Alignment = MinAlign(Alignment, IncrementSize);
7694 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType,
7695 NewVT_Hi, Ch, Ptr, Offset,
7696 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7698 // Build a factor node to remember that this load is independent of the
7700 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
7703 // Remember that we legalized the chain.
7704 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7707 case ISD::BIT_CONVERT: {
7708 // We know the result is a vector. The input may be either a vector or a
7710 SDValue InOp = Node->getOperand(0);
7711 if (!InOp.getValueType().isVector() ||
7712 InOp.getValueType().getVectorNumElements() == 1) {
7713 // The input is a scalar or single-element vector.
7714 // Lower to a store/load so that it can be split.
7715 // FIXME: this could be improved probably.
7716 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
7717 Op.getValueType().getTypeForMVT());
7718 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7719 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7721 SDValue St = DAG.getStore(DAG.getEntryNode(),
7723 PseudoSourceValue::getFixedStack(FI), 0);
7724 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
7725 PseudoSourceValue::getFixedStack(FI), 0);
7727 // Split the vector and convert each of the pieces now.
7728 SplitVectorOp(InOp, Lo, Hi);
7729 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
7730 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
7735 // Remember in a map if the values will be reused later.
7737 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7738 assert(isNew && "Value already split?!?");
7743 /// ScalarizeVectorOp - Given an operand of single-element vector type
7744 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7745 /// scalar (e.g. f32) value.
7746 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7747 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7748 SDNode *Node = Op.getNode();
7749 MVT NewVT = Op.getValueType().getVectorElementType();
7750 assert(Op.getValueType().getVectorNumElements() == 1);
7752 // See if we already scalarized it.
7753 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7754 if (I != ScalarizedNodes.end()) return I->second;
7757 switch (Node->getOpcode()) {
7760 Node->dump(&DAG); cerr << "\n";
7762 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7779 Result = DAG.getNode(Node->getOpcode(),
7781 ScalarizeVectorOp(Node->getOperand(0)),
7782 ScalarizeVectorOp(Node->getOperand(1)));
7794 case ISD::FP_TO_SINT:
7795 case ISD::FP_TO_UINT:
7796 case ISD::SINT_TO_FP:
7797 case ISD::UINT_TO_FP:
7798 case ISD::SIGN_EXTEND:
7799 case ISD::ZERO_EXTEND:
7800 case ISD::ANY_EXTEND:
7802 case ISD::FP_EXTEND:
7803 Result = DAG.getNode(Node->getOpcode(),
7805 ScalarizeVectorOp(Node->getOperand(0)));
7807 case ISD::CONVERT_RNDSAT: {
7808 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
7809 Result = DAG.getConvertRndSat(NewVT, Op0,
7810 DAG.getValueType(NewVT),
7811 DAG.getValueType(Op0.getValueType()),
7812 Node->getOperand(3),
7813 Node->getOperand(4),
7814 cast<CvtRndSatSDNode>(Node)->getCvtCode());
7819 Result = DAG.getNode(Node->getOpcode(),
7821 ScalarizeVectorOp(Node->getOperand(0)),
7822 Node->getOperand(1));
7825 LoadSDNode *LD = cast<LoadSDNode>(Node);
7826 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7827 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7828 ISD::LoadExtType ExtType = LD->getExtensionType();
7829 const Value *SV = LD->getSrcValue();
7830 int SVOffset = LD->getSrcValueOffset();
7831 MVT MemoryVT = LD->getMemoryVT();
7832 unsigned Alignment = LD->getAlignment();
7833 bool isVolatile = LD->isVolatile();
7835 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7836 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7838 Result = DAG.getLoad(ISD::UNINDEXED, ExtType,
7839 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7840 MemoryVT.getVectorElementType(),
7841 isVolatile, Alignment);
7843 // Remember that we legalized the chain.
7844 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7847 case ISD::BUILD_VECTOR:
7848 Result = Node->getOperand(0);
7850 case ISD::INSERT_VECTOR_ELT:
7851 // Returning the inserted scalar element.
7852 Result = Node->getOperand(1);
7854 case ISD::CONCAT_VECTORS:
7855 assert(Node->getOperand(0).getValueType() == NewVT &&
7856 "Concat of non-legal vectors not yet supported!");
7857 Result = Node->getOperand(0);
7859 case ISD::VECTOR_SHUFFLE: {
7860 // Figure out if the scalar is the LHS or RHS and return it.
7861 SDValue EltNum = Node->getOperand(2).getOperand(0);
7862 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7863 Result = ScalarizeVectorOp(Node->getOperand(1));
7865 Result = ScalarizeVectorOp(Node->getOperand(0));
7868 case ISD::EXTRACT_SUBVECTOR:
7869 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, Node->getOperand(0),
7870 Node->getOperand(1));
7872 case ISD::BIT_CONVERT: {
7873 SDValue Op0 = Op.getOperand(0);
7874 if (Op0.getValueType().getVectorNumElements() == 1)
7875 Op0 = ScalarizeVectorOp(Op0);
7876 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7880 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7881 ScalarizeVectorOp(Op.getOperand(1)),
7882 ScalarizeVectorOp(Op.getOperand(2)));
7884 case ISD::SELECT_CC:
7885 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
7886 Node->getOperand(1),
7887 ScalarizeVectorOp(Op.getOperand(2)),
7888 ScalarizeVectorOp(Op.getOperand(3)),
7889 Node->getOperand(4));
7892 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7893 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7894 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0.getValueType()),
7895 Op0, Op1, Op.getOperand(2));
7896 Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7897 DAG.getConstant(-1ULL, NewVT),
7898 DAG.getConstant(0ULL, NewVT));
7903 if (TLI.isTypeLegal(NewVT))
7904 Result = LegalizeOp(Result);
7905 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7906 assert(isNew && "Value already scalarized?");
7912 SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
7913 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op);
7914 if (I != WidenNodes.end()) return I->second;
7916 MVT VT = Op.getValueType();
7917 assert(VT.isVector() && "Cannot widen non-vector type!");
7920 SDNode *Node = Op.getNode();
7921 MVT EVT = VT.getVectorElementType();
7923 unsigned NumElts = VT.getVectorNumElements();
7924 unsigned NewNumElts = WidenVT.getVectorNumElements();
7925 assert(NewNumElts > NumElts && "Cannot widen to smaller type!");
7926 assert(NewNumElts < 17);
7928 // When widen is called, it is assumed that it is more efficient to use a
7929 // wide type. The default action is to widen to operation to a wider legal
7930 // vector type and then do the operation if it is legal by calling LegalizeOp
7931 // again. If there is no vector equivalent, we will unroll the operation, do
7932 // it, and rebuild the vector. If most of the operations are vectorizible to
7933 // the legal type, the resulting code will be more efficient. If this is not
7934 // the case, the resulting code will preform badly as we end up generating
7935 // code to pack/unpack the results. It is the function that calls widen
7936 // that is responsible for seeing this doesn't happen.
7937 switch (Node->getOpcode()) {
7942 assert(0 && "Unexpected operation in WidenVectorOp!");
7944 case ISD::CopyFromReg:
7945 assert(0 && "CopyFromReg doesn't need widening!");
7947 case ISD::ConstantFP:
7948 // To build a vector of these elements, clients should call BuildVector
7949 // and with each element instead of creating a node with a vector type
7950 assert(0 && "Unexpected operation in WidenVectorOp!");
7952 // Variable Arguments with vector types doesn't make any sense to me
7953 assert(0 && "Unexpected operation in WidenVectorOp!");
7956 Result = DAG.getNode(ISD::UNDEF, WidenVT);
7958 case ISD::BUILD_VECTOR: {
7959 // Build a vector with undefined for the new nodes
7960 SDValueVector NewOps(Node->op_begin(), Node->op_end());
7961 for (unsigned i = NumElts; i < NewNumElts; ++i) {
7962 NewOps.push_back(DAG.getNode(ISD::UNDEF,EVT));
7964 Result = DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &NewOps[0], NewOps.size());
7967 case ISD::INSERT_VECTOR_ELT: {
7968 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7969 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, WidenVT, Tmp1,
7970 Node->getOperand(1), Node->getOperand(2));
7973 case ISD::VECTOR_SHUFFLE: {
7974 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7975 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
7976 // VECTOR_SHUFFLE 3rd operand must be a constant build vector that is
7977 // used as permutation array. We build the vector here instead of widening
7978 // because we don't want to legalize and have it turned to something else.
7979 SDValue PermOp = Node->getOperand(2);
7980 SDValueVector NewOps;
7981 MVT PVT = PermOp.getValueType().getVectorElementType();
7982 for (unsigned i = 0; i < NumElts; ++i) {
7983 if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) {
7984 NewOps.push_back(PermOp.getOperand(i));
7987 cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue();
7988 if (Idx < NumElts) {
7989 NewOps.push_back(PermOp.getOperand(i));
7992 NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts,
7993 PermOp.getOperand(i).getValueType()));
7997 for (unsigned i = NumElts; i < NewNumElts; ++i) {
7998 NewOps.push_back(DAG.getNode(ISD::UNDEF,PVT));
8001 SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR,
8002 MVT::getVectorVT(PVT, NewOps.size()),
8003 &NewOps[0], NewOps.size());
8005 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, WidenVT, Tmp1, Tmp2, Tmp3);
8009 // If the load widen returns true, we can use a single load for the
8010 // vector. Otherwise, it is returning a token factor for multiple
8013 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT))
8014 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1)));
8016 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0)));
8020 case ISD::BIT_CONVERT: {
8021 SDValue Tmp1 = Node->getOperand(0);
8022 // Converts between two different types so we need to determine
8023 // the correct widen type for the input operand.
8024 MVT InVT = Tmp1.getValueType();
8025 unsigned WidenSize = WidenVT.getSizeInBits();
8026 if (InVT.isVector()) {
8027 MVT InEltVT = InVT.getVectorElementType();
8028 unsigned InEltSize = InEltVT.getSizeInBits();
8029 assert(WidenSize % InEltSize == 0 &&
8030 "can not widen bit convert that are not multiple of element type");
8031 MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize);
8032 Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT);
8033 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
8034 Result = DAG.getNode(ISD::BIT_CONVERT, WidenVT, Tmp1);
8036 // If the result size is a multiple of the input size, widen the input
8037 // and then convert.
8038 unsigned InSize = InVT.getSizeInBits();
8039 assert(WidenSize % InSize == 0 &&
8040 "can not widen bit convert that are not multiple of element type");
8041 unsigned NewNumElts = WidenSize / InSize;
8042 SmallVector<SDValue, 16> Ops(NewNumElts);
8043 SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT);
8045 for (unsigned i = 1; i < NewNumElts; ++i)
8048 MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts);
8049 Result = DAG.getNode(ISD::BUILD_VECTOR, NewInVT, &Ops[0], NewNumElts);
8050 Result = DAG.getNode(ISD::BIT_CONVERT, WidenVT, Result);
8055 case ISD::SINT_TO_FP:
8056 case ISD::UINT_TO_FP:
8057 case ISD::FP_TO_SINT:
8058 case ISD::FP_TO_UINT:
8059 case ISD::FP_ROUND: {
8060 SDValue Tmp1 = Node->getOperand(0);
8061 // Converts between two different types so we need to determine
8062 // the correct widen type for the input operand.
8063 MVT TVT = Tmp1.getValueType();
8064 assert(TVT.isVector() && "can not widen non vector type");
8065 MVT TEVT = TVT.getVectorElementType();
8066 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts);
8067 Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
8068 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts);
8069 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
8073 case ISD::FP_EXTEND:
8074 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
8076 case ISD::SIGN_EXTEND:
8077 case ISD::ZERO_EXTEND:
8078 case ISD::ANY_EXTEND:
8079 case ISD::SIGN_EXTEND_INREG:
8088 // Unary op widening
8090 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8091 assert(Tmp1.getValueType() == WidenVT);
8092 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
8095 case ISD::CONVERT_RNDSAT: {
8096 SDValue RndOp = Node->getOperand(3);
8097 SDValue SatOp = Node->getOperand(4);
8098 SDValue SrcOp = Node->getOperand(0);
8100 // Converts between two different types so we need to determine
8101 // the correct widen type for the input operand.
8102 MVT SVT = SrcOp.getValueType();
8103 assert(SVT.isVector() && "can not widen non vector type");
8104 MVT SEVT = SVT.getVectorElementType();
8105 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts);
8107 SrcOp = WidenVectorOp(SrcOp, SWidenVT);
8108 assert(SrcOp.getValueType() == WidenVT);
8109 SDValue DTyOp = DAG.getValueType(WidenVT);
8110 SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
8111 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
8113 Result = DAG.getConvertRndSat(WidenVT, SrcOp, DTyOp, STyOp,
8114 RndOp, SatOp, CvtCode);
8134 case ISD::FCOPYSIGN:
8138 // Binary op widening
8139 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8140 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8141 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8142 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2);
8149 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8150 assert(Tmp1.getValueType() == WidenVT);
8151 SDValue ShOp = Node->getOperand(1);
8152 MVT ShVT = ShOp.getValueType();
8153 MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(),
8154 WidenVT.getVectorNumElements());
8155 ShOp = WidenVectorOp(ShOp, NewShVT);
8156 assert(ShOp.getValueType() == NewShVT);
8157 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, ShOp);
8161 case ISD::EXTRACT_VECTOR_ELT: {
8162 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8163 assert(Tmp1.getValueType() == WidenVT);
8164 Result = DAG.getNode(Node->getOpcode(), EVT, Tmp1, Node->getOperand(1));
8167 case ISD::CONCAT_VECTORS: {
8168 // We concurrently support only widen on a multiple of the incoming vector.
8169 // We could widen on a multiple of the incoming operand if necessary.
8170 unsigned NumConcat = NewNumElts / NumElts;
8171 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
8172 SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT);
8173 SmallVector<SDValue, 8> MOps;
8175 for (unsigned i = 1; i != NumConcat; ++i) {
8176 MOps.push_back(UndefVal);
8178 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
8179 &MOps[0], MOps.size()));
8182 case ISD::EXTRACT_SUBVECTOR: {
8183 SDValue Tmp1 = Node->getOperand(0);
8184 SDValue Idx = Node->getOperand(1);
8185 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
8186 if (CIdx && CIdx->getZExtValue() == 0) {
8187 // Since we are access the start of the vector, the incoming
8188 // vector type might be the proper.
8189 MVT Tmp1VT = Tmp1.getValueType();
8190 if (Tmp1VT == WidenVT)
8193 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements();
8194 if (Tmp1VTNumElts < NewNumElts)
8195 Result = WidenVectorOp(Tmp1, WidenVT);
8197 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, WidenVT, Tmp1, Idx);
8199 } else if (NewNumElts % NumElts == 0) {
8200 // Widen the extracted subvector.
8201 unsigned NumConcat = NewNumElts / NumElts;
8202 SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT);
8203 SmallVector<SDValue, 8> MOps;
8205 for (unsigned i = 1; i != NumConcat; ++i) {
8206 MOps.push_back(UndefVal);
8208 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
8209 &MOps[0], MOps.size()));
8211 assert(0 && "can not widen extract subvector");
8212 // This could be implemented using insert and build vector but I would
8213 // like to see when this happens.
8219 // Determine new condition widen type and widen
8220 SDValue Cond1 = Node->getOperand(0);
8221 MVT CondVT = Cond1.getValueType();
8222 assert(CondVT.isVector() && "can not widen non vector type");
8223 MVT CondEVT = CondVT.getVectorElementType();
8224 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8225 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8226 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen");
8228 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT);
8229 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT);
8230 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8231 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Tmp1, Tmp2);
8235 case ISD::SELECT_CC: {
8236 // Determine new condition widen type and widen
8237 SDValue Cond1 = Node->getOperand(0);
8238 SDValue Cond2 = Node->getOperand(1);
8239 MVT CondVT = Cond1.getValueType();
8240 assert(CondVT.isVector() && "can not widen non vector type");
8241 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs");
8242 MVT CondEVT = CondVT.getVectorElementType();
8243 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8244 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8245 Cond2 = WidenVectorOp(Cond2, CondWidenVT);
8246 assert(Cond1.getValueType() == CondWidenVT &&
8247 Cond2.getValueType() == CondWidenVT && "condition not widen");
8249 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT);
8250 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT);
8251 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT &&
8252 "operands not widen");
8253 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Cond2, Tmp1,
8254 Tmp2, Node->getOperand(4));
8258 // Determine widen for the operand
8259 SDValue Tmp1 = Node->getOperand(0);
8260 MVT TmpVT = Tmp1.getValueType();
8261 assert(TmpVT.isVector() && "can not widen non vector type");
8262 MVT TmpEVT = TmpVT.getVectorElementType();
8263 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts);
8264 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT);
8265 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT);
8266 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2,
8267 Node->getOperand(2));
8270 case ISD::ATOMIC_CMP_SWAP:
8271 case ISD::ATOMIC_LOAD_ADD:
8272 case ISD::ATOMIC_LOAD_SUB:
8273 case ISD::ATOMIC_LOAD_AND:
8274 case ISD::ATOMIC_LOAD_OR:
8275 case ISD::ATOMIC_LOAD_XOR:
8276 case ISD::ATOMIC_LOAD_NAND:
8277 case ISD::ATOMIC_LOAD_MIN:
8278 case ISD::ATOMIC_LOAD_MAX:
8279 case ISD::ATOMIC_LOAD_UMIN:
8280 case ISD::ATOMIC_LOAD_UMAX:
8281 case ISD::ATOMIC_SWAP: {
8282 // For now, we assume that using vectors for these operations don't make
8283 // much sense so we just split it. We return an empty result
8285 SplitVectorOp(Op, X, Y);
8290 } // end switch (Node->getOpcode())
8292 assert(Result.getNode() && "Didn't set a result!");
8294 Result = LegalizeOp(Result);
8296 AddWidenedOperand(Op, Result);
8300 // Utility function to find a legal vector type and its associated element
8301 // type from a preferred width and whose vector type must be the same size
8303 // TLI: Target lowering used to determine legal types
8304 // Width: Preferred width of element type
8305 // VVT: Vector value type whose size we must match.
8306 // Returns VecEVT and EVT - the vector type and its associated element type
8307 static void FindWidenVecType(const TargetLowering &TLI, unsigned Width, MVT VVT,
8308 MVT& EVT, MVT& VecEVT) {
8309 // We start with the preferred width, make it a power of 2 and see if
8310 // we can find a vector type of that width. If not, we reduce it by
8311 // another power of 2. If we have widen the type, a vector of bytes should
8313 assert(TLI.isTypeLegal(VVT));
8314 unsigned EWidth = Width + 1;
8317 EWidth = (1 << Log2_32(EWidth-1));
8318 EVT = MVT::getIntegerVT(EWidth);
8319 unsigned NumEVT = VVT.getSizeInBits()/EWidth;
8320 VecEVT = MVT::getVectorVT(EVT, NumEVT);
8321 } while (!TLI.isTypeLegal(VecEVT) ||
8322 VVT.getSizeInBits() != VecEVT.getSizeInBits());
8325 SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
8334 // We assume that we have good rules to handle loading power of two loads so
8335 // we break down the operations to power of 2 loads. The strategy is to
8336 // load the largest power of 2 that we can easily transform to a legal vector
8337 // and then insert into that vector, and the cast the result into the legal
8338 // vector that we want. This avoids unnecessary stack converts.
8339 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
8340 // the load is nonvolatile, we an use a wider load for the value.
8341 // Find a vector length we can load a large chunk
8344 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8345 EVTWidth = EVT.getSizeInBits();
8347 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV, SVOffset,
8348 isVolatile, Alignment);
8349 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecEVT, LdOp);
8350 LdChain.push_back(LdOp.getValue(1));
8352 // Check if we can load the element with one instruction
8353 if (LdWidth == EVTWidth) {
8354 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
8357 // The vector element order is endianness dependent.
8359 LdWidth -= EVTWidth;
8360 unsigned Offset = 0;
8362 while (LdWidth > 0) {
8363 unsigned Increment = EVTWidth / 8;
8364 Offset += Increment;
8365 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
8366 DAG.getIntPtrConstant(Increment));
8368 if (LdWidth < EVTWidth) {
8369 // Our current type we are using is too large, use a smaller size by
8370 // using a smaller power of 2
8371 unsigned oEVTWidth = EVTWidth;
8372 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8373 EVTWidth = EVT.getSizeInBits();
8374 // Readjust position and vector position based on new load type
8375 Idx = Idx * (oEVTWidth/EVTWidth);
8376 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
8379 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV,
8380 SVOffset+Offset, isVolatile,
8381 MinAlign(Alignment, Offset));
8382 LdChain.push_back(LdOp.getValue(1));
8383 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, VecEVT, VecOp, LdOp,
8384 DAG.getIntPtrConstant(Idx++));
8386 LdWidth -= EVTWidth;
8389 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
8392 bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
8396 // TODO: Add support for ConcatVec and the ability to load many vector
8397 // types (e.g., v4i8). This will not work when a vector register
8398 // to memory mapping is strange (e.g., vector elements are not
8399 // stored in some sequential order).
8401 // It must be true that the widen vector type is bigger than where
8402 // we need to load from.
8403 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
8404 MVT LdVT = LD->getMemoryVT();
8405 assert(LdVT.isVector() && NVT.isVector());
8406 assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
8409 SDValue Chain = LD->getChain();
8410 SDValue BasePtr = LD->getBasePtr();
8411 int SVOffset = LD->getSrcValueOffset();
8412 unsigned Alignment = LD->getAlignment();
8413 bool isVolatile = LD->isVolatile();
8414 const Value *SV = LD->getSrcValue();
8415 unsigned int LdWidth = LdVT.getSizeInBits();
8417 // Load value as a large register
8418 SDValueVector LdChain;
8419 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
8420 Alignment, isVolatile, LdWidth, NVT);
8422 if (LdChain.size() == 1) {
8427 TFOp=DAG.getNode(ISD::TokenFactor, MVT::Other, &LdChain[0], LdChain.size());
8433 void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
8442 // Breaks the stores into a series of power of 2 width stores. For any
8443 // width, we convert the vector to the vector of element size that we
8444 // want to store. This avoids requiring a stack convert.
8446 // Find a width of the element type we can store with
8447 MVT VVT = ValOp.getValueType();
8450 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8451 EVTWidth = EVT.getSizeInBits();
8453 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, ValOp);
8454 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
8455 DAG.getIntPtrConstant(0));
8456 SDValue StOp = DAG.getStore(Chain, EOp, BasePtr, SV, SVOffset,
8457 isVolatile, Alignment);
8458 StChain.push_back(StOp);
8460 // Check if we are done
8461 if (StWidth == EVTWidth) {
8466 StWidth -= EVTWidth;
8467 unsigned Offset = 0;
8469 while (StWidth > 0) {
8470 unsigned Increment = EVTWidth / 8;
8471 Offset += Increment;
8472 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
8473 DAG.getIntPtrConstant(Increment));
8475 if (StWidth < EVTWidth) {
8476 // Our current type we are using is too large, use a smaller size by
8477 // using a smaller power of 2
8478 unsigned oEVTWidth = EVTWidth;
8479 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8480 EVTWidth = EVT.getSizeInBits();
8481 // Readjust position and vector position based on new load type
8482 Idx = Idx * (oEVTWidth/EVTWidth);
8483 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
8486 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
8487 DAG.getIntPtrConstant(Idx++));
8488 StChain.push_back(DAG.getStore(Chain, EOp, BasePtr, SV,
8489 SVOffset + Offset, isVolatile,
8490 MinAlign(Alignment, Offset)));
8491 StWidth -= EVTWidth;
8496 SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
8499 // TODO: It might be cleaner if we can use SplitVector and have more legal
8500 // vector types that can be stored into memory (e.g., v4xi8 can
8501 // be stored as a word). This will not work when a vector register
8502 // to memory mapping is strange (e.g., vector elements are not
8503 // stored in some sequential order).
8505 MVT StVT = ST->getMemoryVT();
8506 SDValue ValOp = ST->getValue();
8508 // Check if we have widen this node with another value
8509 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
8510 if (I != WidenNodes.end())
8513 MVT VVT = ValOp.getValueType();
8515 // It must be true that we the widen vector type is bigger than where
8516 // we need to store.
8517 assert(StVT.isVector() && VVT.isVector());
8518 assert(StVT.getSizeInBits() < VVT.getSizeInBits());
8519 assert(StVT.getVectorElementType() == VVT.getVectorElementType());
8522 SDValueVector StChain;
8523 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(),
8524 ST->getSrcValueOffset(), ST->getAlignment(),
8525 ST->isVolatile(), ValOp, StVT.getSizeInBits());
8526 if (StChain.size() == 1)
8529 return DAG.getNode(ISD::TokenFactor, MVT::Other,&StChain[0],StChain.size());
8533 // SelectionDAG::Legalize - This is the entry point for the file.
8535 void SelectionDAG::Legalize(bool TypesNeedLegalizing) {
8536 /// run - This is the main entry point to this class.
8538 SelectionDAGLegalize(*this, TypesNeedLegalizing).LegalizeDAG();