1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class VISIBILITY_HIDDEN SelectionDAGLegalize {
54 bool TypesNeedLegalizing;
56 // Libcall insertion helpers.
58 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
59 /// legalized. We use this to ensure that calls are properly serialized
60 /// against each other, including inserted libcalls.
61 SDValue LastCALLSEQ_END;
63 /// IsLegalizingCall - This member is used *only* for purposes of providing
64 /// helpful assertions that a libcall isn't created while another call is
65 /// being legalized (which could lead to non-serialized call sequences).
66 bool IsLegalizingCall;
69 Legal, // The target natively supports this operation.
70 Promote, // This operation should be executed in a larger type.
71 Expand // Try to expand this to other ops, otherwise use a libcall.
74 /// ValueTypeActions - This is a bitvector that contains two bits for each
75 /// value type, where the two bits correspond to the LegalizeAction enum.
76 /// This can be queried with "getTypeAction(VT)".
77 TargetLowering::ValueTypeActionImpl ValueTypeActions;
79 /// LegalizedNodes - For nodes that are of legal width, and that have more
80 /// than one use, this map indicates what regularized operand to use. This
81 /// allows us to avoid legalizing the same thing more than once.
82 DenseMap<SDValue, SDValue> LegalizedNodes;
84 /// PromotedNodes - For nodes that are below legal width, and that have more
85 /// than one use, this map indicates what promoted value to use. This allows
86 /// us to avoid promoting the same thing more than once.
87 DenseMap<SDValue, SDValue> PromotedNodes;
89 /// ExpandedNodes - For nodes that need to be expanded this map indicates
90 /// which operands are the expanded version of the input. This allows
91 /// us to avoid expanding the same node more than once.
92 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
94 /// SplitNodes - For vector nodes that need to be split, this map indicates
95 /// which operands are the split version of the input. This allows us
96 /// to avoid splitting the same node more than once.
97 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
99 /// ScalarizedNodes - For nodes that need to be converted from vector types to
100 /// scalar types, this contains the mapping of ones we have already
101 /// processed to the result.
102 std::map<SDValue, SDValue> ScalarizedNodes;
104 /// WidenNodes - For nodes that need to be widened from one vector type to
105 /// another, this contains the mapping of those that we have already widen.
106 /// This allows us to avoid widening more than once.
107 std::map<SDValue, SDValue> WidenNodes;
109 void AddLegalizedOperand(SDValue From, SDValue To) {
110 LegalizedNodes.insert(std::make_pair(From, To));
111 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
115 void AddPromotedOperand(SDValue From, SDValue To) {
116 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
117 assert(isNew && "Got into the map somehow?");
119 // If someone requests legalization of the new node, return itself.
120 LegalizedNodes.insert(std::make_pair(To, To));
122 void AddWidenedOperand(SDValue From, SDValue To) {
123 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second;
124 assert(isNew && "Got into the map somehow?");
126 // If someone requests legalization of the new node, return itself.
127 LegalizedNodes.insert(std::make_pair(To, To));
131 explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing);
133 /// getTypeAction - Return how we should legalize values of this type, either
134 /// it is already legal or we need to expand it into multiple registers of
135 /// smaller integer type, or we need to promote it to a larger type.
136 LegalizeAction getTypeAction(MVT VT) const {
137 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
140 /// isTypeLegal - Return true if this type is legal on this target.
142 bool isTypeLegal(MVT VT) const {
143 return getTypeAction(VT) == Legal;
149 /// HandleOp - Legalize, Promote, or Expand the specified operand as
150 /// appropriate for its type.
151 void HandleOp(SDValue Op);
153 /// LegalizeOp - We know that the specified value has a legal type.
154 /// Recursively ensure that the operands have legal types, then return the
156 SDValue LegalizeOp(SDValue O);
158 /// UnrollVectorOp - We know that the given vector has a legal type, however
159 /// the operation it performs is not legal and is an operation that we have
160 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
161 /// operating on each element individually.
162 SDValue UnrollVectorOp(SDValue O);
164 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
165 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
166 /// is necessary to spill the vector being inserted into to memory, perform
167 /// the insert there, and then read the result back.
168 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
171 /// PromoteOp - Given an operation that produces a value in an invalid type,
172 /// promote it to compute the value into a larger type. The produced value
173 /// will have the correct bits for the low portion of the register, but no
174 /// guarantee is made about the top bits: it may be zero, sign-extended, or
176 SDValue PromoteOp(SDValue O);
178 /// ExpandOp - Expand the specified SDValue into its two component pieces
179 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
180 /// the LegalizedNodes map is filled in for any results that are not expanded,
181 /// the ExpandedNodes map is filled in for any results that are expanded, and
182 /// the Lo/Hi values are returned. This applies to integer types and Vector
184 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
186 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
187 /// (e.g., v3i32 to v4i32). The produced value will have the correct value
188 /// for the existing elements but no guarantee is made about the new elements
189 /// at the end of the vector: it may be zero, ones, or garbage. This is useful
190 /// when we have an instruction operating on an illegal vector type and we
191 /// want to widen it to do the computation on a legal wider vector type.
192 SDValue WidenVectorOp(SDValue Op, MVT WidenVT);
194 /// SplitVectorOp - Given an operand of vector type, break it down into
195 /// two smaller values.
196 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
198 /// ScalarizeVectorOp - Given an operand of single-element vector type
199 /// (e.g. v1f32), convert it into the equivalent operation that returns a
200 /// scalar (e.g. f32) value.
201 SDValue ScalarizeVectorOp(SDValue O);
203 /// Useful 16 element vector type that is used to pass operands for widening.
204 typedef SmallVector<SDValue, 16> SDValueVector;
206 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if
207 /// the LdChain contains a single load and false if it contains a token
208 /// factor for multiple loads. It takes
209 /// Result: location to return the result
210 /// LdChain: location to return the load chain
211 /// Op: load operation to widen
212 /// NVT: widen vector result type we want for the load
213 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
214 SDValue Op, MVT NVT);
216 /// Helper genWidenVectorLoads - Helper function to generate a set of
217 /// loads to load a vector with a resulting wider type. It takes
218 /// LdChain: list of chains for the load we have generated
219 /// Chain: incoming chain for the ld vector
220 /// BasePtr: base pointer to load from
221 /// SV: memory disambiguation source value
222 /// SVOffset: memory disambiugation offset
223 /// Alignment: alignment of the memory
224 /// isVolatile: volatile load
225 /// LdWidth: width of memory that we want to load
226 /// ResType: the wider result result type for the resulting loaded vector
227 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain,
228 SDValue BasePtr, const Value *SV,
229 int SVOffset, unsigned Alignment,
230 bool isVolatile, unsigned LdWidth,
233 /// StoreWidenVectorOp - Stores a widen vector into non widen memory
234 /// location. It takes
235 /// ST: store node that we want to replace
236 /// Chain: incoming store chain
237 /// BasePtr: base address of where we want to store into
238 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
241 /// Helper genWidenVectorStores - Helper function to generate a set of
242 /// stores to store a widen vector into non widen memory
244 // StChain: list of chains for the stores we have generated
245 // Chain: incoming chain for the ld vector
246 // BasePtr: base pointer to load from
247 // SV: memory disambiguation source value
248 // SVOffset: memory disambiugation offset
249 // Alignment: alignment of the memory
250 // isVolatile: volatile lod
251 // ValOp: value to store
252 // StWidth: width of memory that we want to store
253 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain,
254 SDValue BasePtr, const Value *SV,
255 int SVOffset, unsigned Alignment,
256 bool isVolatile, SDValue ValOp,
259 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
260 /// specified mask and type. Targets can specify exactly which masks they
261 /// support and the code generator is tasked with not creating illegal masks.
263 /// Note that this will also return true for shuffles that are promoted to a
266 /// If this is a legal shuffle, this method returns the (possibly promoted)
267 /// build_vector Mask. If it's not a legal shuffle, it returns null.
268 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
270 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
271 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
273 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC);
274 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC);
275 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC) {
276 LegalizeSetCCOperands(LHS, RHS, CC);
277 LegalizeSetCCCondCode(VT, LHS, RHS, CC);
280 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
282 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source);
284 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT);
285 SDValue ExpandBUILD_VECTOR(SDNode *Node);
286 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
287 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op);
288 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT);
289 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned);
290 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned);
292 SDValue ExpandBSWAP(SDValue Op);
293 SDValue ExpandBitCount(unsigned Opc, SDValue Op);
294 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
295 SDValue &Lo, SDValue &Hi);
296 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
297 SDValue &Lo, SDValue &Hi);
299 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
300 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
302 // Returns the legalized (truncated or extended) shift amount.
303 SDValue LegalizeShiftAmount(SDValue ShiftAmt);
307 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
308 /// specified mask and type. Targets can specify exactly which masks they
309 /// support and the code generator is tasked with not creating illegal masks.
311 /// Note that this will also return true for shuffles that are promoted to a
313 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
314 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
316 case TargetLowering::Legal:
317 case TargetLowering::Custom:
319 case TargetLowering::Promote: {
320 // If this is promoted to a different type, convert the shuffle mask and
321 // ask if it is legal in the promoted type!
322 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
323 MVT EltVT = NVT.getVectorElementType();
325 // If we changed # elements, change the shuffle mask.
326 unsigned NumEltsGrowth =
327 NVT.getVectorNumElements() / VT.getVectorNumElements();
328 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
329 if (NumEltsGrowth > 1) {
330 // Renumber the elements.
331 SmallVector<SDValue, 8> Ops;
332 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
333 SDValue InOp = Mask.getOperand(i);
334 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
335 if (InOp.getOpcode() == ISD::UNDEF)
336 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
338 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
339 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
343 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
349 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
352 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, bool types)
353 : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types),
354 ValueTypeActions(TLI.getValueTypeActions()) {
355 assert(MVT::LAST_VALUETYPE <= 32 &&
356 "Too many value types for ValueTypeActions to hold!");
359 void SelectionDAGLegalize::LegalizeDAG() {
360 LastCALLSEQ_END = DAG.getEntryNode();
361 IsLegalizingCall = false;
363 // The legalize process is inherently a bottom-up recursive process (users
364 // legalize their uses before themselves). Given infinite stack space, we
365 // could just start legalizing on the root and traverse the whole graph. In
366 // practice however, this causes us to run out of stack space on large basic
367 // blocks. To avoid this problem, compute an ordering of the nodes where each
368 // node is only legalized after all of its operands are legalized.
369 DAG.AssignTopologicalOrder();
370 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
371 E = prior(DAG.allnodes_end()); I != next(E); ++I)
372 HandleOp(SDValue(I, 0));
374 // Finally, it's possible the root changed. Get the new root.
375 SDValue OldRoot = DAG.getRoot();
376 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
377 DAG.setRoot(LegalizedNodes[OldRoot]);
379 ExpandedNodes.clear();
380 LegalizedNodes.clear();
381 PromotedNodes.clear();
383 ScalarizedNodes.clear();
386 // Remove dead nodes now.
387 DAG.RemoveDeadNodes();
391 /// FindCallEndFromCallStart - Given a chained node that is part of a call
392 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
393 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
394 if (Node->getOpcode() == ISD::CALLSEQ_END)
396 if (Node->use_empty())
397 return 0; // No CallSeqEnd
399 // The chain is usually at the end.
400 SDValue TheChain(Node, Node->getNumValues()-1);
401 if (TheChain.getValueType() != MVT::Other) {
402 // Sometimes it's at the beginning.
403 TheChain = SDValue(Node, 0);
404 if (TheChain.getValueType() != MVT::Other) {
405 // Otherwise, hunt for it.
406 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
407 if (Node->getValueType(i) == MVT::Other) {
408 TheChain = SDValue(Node, i);
412 // Otherwise, we walked into a node without a chain.
413 if (TheChain.getValueType() != MVT::Other)
418 for (SDNode::use_iterator UI = Node->use_begin(),
419 E = Node->use_end(); UI != E; ++UI) {
421 // Make sure to only follow users of our token chain.
423 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
424 if (User->getOperand(i) == TheChain)
425 if (SDNode *Result = FindCallEndFromCallStart(User))
431 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
432 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
433 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
434 assert(Node && "Didn't find callseq_start for a call??");
435 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
437 assert(Node->getOperand(0).getValueType() == MVT::Other &&
438 "Node doesn't have a token chain argument!");
439 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
442 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
443 /// see if any uses can reach Dest. If no dest operands can get to dest,
444 /// legalize them, legalize ourself, and return false, otherwise, return true.
446 /// Keep track of the nodes we fine that actually do lead to Dest in
447 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
449 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
450 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
451 if (N == Dest) return true; // N certainly leads to Dest :)
453 // If we've already processed this node and it does lead to Dest, there is no
454 // need to reprocess it.
455 if (NodesLeadingTo.count(N)) return true;
457 // If the first result of this node has been already legalized, then it cannot
459 switch (getTypeAction(N->getValueType(0))) {
461 if (LegalizedNodes.count(SDValue(N, 0))) return false;
464 if (PromotedNodes.count(SDValue(N, 0))) return false;
467 if (ExpandedNodes.count(SDValue(N, 0))) return false;
471 // Okay, this node has not already been legalized. Check and legalize all
472 // operands. If none lead to Dest, then we can legalize this node.
473 bool OperandsLeadToDest = false;
474 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
475 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
476 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
478 if (OperandsLeadToDest) {
479 NodesLeadingTo.insert(N);
483 // Okay, this node looks safe, legalize it and return false.
484 HandleOp(SDValue(N, 0));
488 /// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as
489 /// appropriate for its type.
490 void SelectionDAGLegalize::HandleOp(SDValue Op) {
491 MVT VT = Op.getValueType();
492 // If the type legalizer was run then we should never see any illegal result
493 // types here except for target constants (the type legalizer does not touch
494 // those) or for build vector used as a mask for a vector shuffle.
495 // FIXME: We can removed the BUILD_VECTOR case when we fix PR2957.
496 assert((TypesNeedLegalizing || getTypeAction(VT) == Legal ||
497 Op.getOpcode() == ISD::TargetConstant ||
498 Op.getOpcode() == ISD::BUILD_VECTOR) &&
499 "Illegal type introduced after type legalization?");
500 switch (getTypeAction(VT)) {
501 default: assert(0 && "Bad type action!");
502 case Legal: (void)LegalizeOp(Op); break;
504 if (!VT.isVector()) {
509 // See if we can widen otherwise use Expand to either scalarize or split
510 MVT WidenVT = TLI.getWidenVectorType(VT);
511 if (WidenVT != MVT::Other) {
512 (void) WidenVectorOp(Op, WidenVT);
515 // else fall thru to expand since we can't widen the vector
518 if (!VT.isVector()) {
519 // If this is an illegal scalar, expand it into its two component
522 if (Op.getOpcode() == ISD::TargetConstant)
523 break; // Allow illegal target nodes.
525 } else if (VT.getVectorNumElements() == 1) {
526 // If this is an illegal single element vector, convert it to a
528 (void)ScalarizeVectorOp(Op);
530 // This is an illegal multiple element vector.
531 // Split it in half and legalize both parts.
533 SplitVectorOp(Op, X, Y);
539 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
540 /// a load from the constant pool.
541 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
542 SelectionDAG &DAG, TargetLowering &TLI) {
545 // If a FP immediate is precise when represented as a float and if the
546 // target can do an extending load from float to double, we put it into
547 // the constant pool as a float, even if it's is statically typed as a
548 // double. This shrinks FP constants and canonicalizes them for targets where
549 // an FP extending load is the same cost as a normal load (such as on the x87
550 // fp stack or PPC FP unit).
551 MVT VT = CFP->getValueType(0);
552 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
554 if (VT!=MVT::f64 && VT!=MVT::f32)
555 assert(0 && "Invalid type expansion");
556 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
557 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
562 while (SVT != MVT::f32) {
563 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
564 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
565 // Only do this if the target has a native EXTLOAD instruction from
567 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
568 TLI.ShouldShrinkFPConstant(OrigVT)) {
569 const Type *SType = SVT.getTypeForMVT();
570 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
576 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
577 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
579 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
580 CPIdx, PseudoSourceValue::getConstantPool(),
581 0, VT, false, Alignment);
582 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
583 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
587 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
590 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
591 SelectionDAG &DAG, TargetLowering &TLI) {
592 MVT VT = Node->getValueType(0);
593 MVT SrcVT = Node->getOperand(1).getValueType();
594 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
595 "fcopysign expansion only supported for f32 and f64");
596 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
598 // First get the sign bit of second operand.
599 SDValue Mask1 = (SrcVT == MVT::f64)
600 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
601 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
602 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
603 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
604 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
605 // Shift right or sign-extend it if the two operands have different types.
606 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
608 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
609 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
610 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
611 } else if (SizeDiff < 0) {
612 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
613 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
614 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
617 // Clear the sign bit of first operand.
618 SDValue Mask2 = (VT == MVT::f64)
619 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
620 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
621 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
622 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
623 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
625 // Or the value with the sign bit.
626 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
630 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
632 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
633 TargetLowering &TLI) {
634 SDValue Chain = ST->getChain();
635 SDValue Ptr = ST->getBasePtr();
636 SDValue Val = ST->getValue();
637 MVT VT = Val.getValueType();
638 int Alignment = ST->getAlignment();
639 int SVOffset = ST->getSrcValueOffset();
640 if (ST->getMemoryVT().isFloatingPoint() ||
641 ST->getMemoryVT().isVector()) {
642 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
643 if (TLI.isTypeLegal(intVT)) {
644 // Expand to a bitconvert of the value to the integer type of the
645 // same size, then a (misaligned) int store.
646 // FIXME: Does not handle truncating floating point stores!
647 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
648 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
649 SVOffset, ST->isVolatile(), Alignment);
651 // Do a (aligned) store to a stack slot, then copy from the stack slot
652 // to the final destination using (unaligned) integer loads and stores.
653 MVT StoredVT = ST->getMemoryVT();
655 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
656 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
657 unsigned RegBytes = RegVT.getSizeInBits() / 8;
658 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
660 // Make sure the stack slot is also aligned for the register type.
661 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
663 // Perform the original store, only redirected to the stack slot.
664 SDValue Store = DAG.getTruncStore(Chain, Val, StackPtr, NULL, 0,StoredVT);
665 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
666 SmallVector<SDValue, 8> Stores;
669 // Do all but one copies using the full register width.
670 for (unsigned i = 1; i < NumRegs; i++) {
671 // Load one integer register's worth from the stack slot.
672 SDValue Load = DAG.getLoad(RegVT, Store, StackPtr, NULL, 0);
673 // Store it to the final location. Remember the store.
674 Stores.push_back(DAG.getStore(Load.getValue(1), Load, Ptr,
675 ST->getSrcValue(), SVOffset + Offset,
677 MinAlign(ST->getAlignment(), Offset)));
678 // Increment the pointers.
680 StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr,
682 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, Increment);
685 // The last store may be partial. Do a truncating store. On big-endian
686 // machines this requires an extending load from the stack slot to ensure
687 // that the bits are in the right place.
688 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
690 // Load from the stack slot.
691 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, Store, StackPtr,
694 Stores.push_back(DAG.getTruncStore(Load.getValue(1), Load, Ptr,
695 ST->getSrcValue(), SVOffset + Offset,
696 MemVT, ST->isVolatile(),
697 MinAlign(ST->getAlignment(), Offset)));
698 // The order of the stores doesn't matter - say it with a TokenFactor.
699 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],
703 assert(ST->getMemoryVT().isInteger() &&
704 !ST->getMemoryVT().isVector() &&
705 "Unaligned store of unknown type.");
706 // Get the half-size VT
708 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
709 int NumBits = NewStoredVT.getSizeInBits();
710 int IncrementSize = NumBits / 8;
712 // Divide the stored value in two parts.
713 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
715 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
717 // Store the two parts
718 SDValue Store1, Store2;
719 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
720 ST->getSrcValue(), SVOffset, NewStoredVT,
721 ST->isVolatile(), Alignment);
722 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
723 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
724 Alignment = MinAlign(Alignment, IncrementSize);
725 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
726 ST->getSrcValue(), SVOffset + IncrementSize,
727 NewStoredVT, ST->isVolatile(), Alignment);
729 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
732 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
734 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
735 TargetLowering &TLI) {
736 int SVOffset = LD->getSrcValueOffset();
737 SDValue Chain = LD->getChain();
738 SDValue Ptr = LD->getBasePtr();
739 MVT VT = LD->getValueType(0);
740 MVT LoadedVT = LD->getMemoryVT();
741 if (VT.isFloatingPoint() || VT.isVector()) {
742 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
743 if (TLI.isTypeLegal(intVT)) {
744 // Expand to a (misaligned) integer load of the same size,
745 // then bitconvert to floating point or vector.
746 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
747 SVOffset, LD->isVolatile(),
749 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
750 if (VT.isFloatingPoint() && LoadedVT != VT)
751 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
753 SDValue Ops[] = { Result, Chain };
754 return DAG.getMergeValues(Ops, 2);
756 // Copy the value to a (aligned) stack slot using (unaligned) integer
757 // loads and stores, then do a (aligned) load from the stack slot.
758 MVT RegVT = TLI.getRegisterType(intVT);
759 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
760 unsigned RegBytes = RegVT.getSizeInBits() / 8;
761 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
763 // Make sure the stack slot is also aligned for the register type.
764 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
766 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
767 SmallVector<SDValue, 8> Stores;
768 SDValue StackPtr = StackBase;
771 // Do all but one copies using the full register width.
772 for (unsigned i = 1; i < NumRegs; i++) {
773 // Load one integer register's worth from the original location.
774 SDValue Load = DAG.getLoad(RegVT, Chain, Ptr, LD->getSrcValue(),
775 SVOffset + Offset, LD->isVolatile(),
776 MinAlign(LD->getAlignment(), Offset));
777 // Follow the load with a store to the stack slot. Remember the store.
778 Stores.push_back(DAG.getStore(Load.getValue(1), Load, StackPtr,
780 // Increment the pointers.
782 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, Increment);
783 StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr,
787 // The last copy may be partial. Do an extending load.
788 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
789 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, Chain, Ptr,
790 LD->getSrcValue(), SVOffset + Offset,
791 MemVT, LD->isVolatile(),
792 MinAlign(LD->getAlignment(), Offset));
793 // Follow the load with a store to the stack slot. Remember the store.
794 // On big-endian machines this requires a truncating store to ensure
795 // that the bits end up in the right place.
796 Stores.push_back(DAG.getTruncStore(Load.getValue(1), Load, StackPtr,
799 // The order of the stores doesn't matter - say it with a TokenFactor.
800 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],
803 // Finally, perform the original load only redirected to the stack slot.
804 Load = DAG.getExtLoad(LD->getExtensionType(), VT, TF, StackBase,
807 // Callers expect a MERGE_VALUES node.
808 SDValue Ops[] = { Load, TF };
809 return DAG.getMergeValues(Ops, 2);
812 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
813 "Unaligned load of unsupported type.");
815 // Compute the new VT that is half the size of the old one. This is an
817 unsigned NumBits = LoadedVT.getSizeInBits();
819 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
822 unsigned Alignment = LD->getAlignment();
823 unsigned IncrementSize = NumBits / 8;
824 ISD::LoadExtType HiExtType = LD->getExtensionType();
826 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
827 if (HiExtType == ISD::NON_EXTLOAD)
828 HiExtType = ISD::ZEXTLOAD;
830 // Load the value in two parts
832 if (TLI.isLittleEndian()) {
833 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
834 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
835 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
836 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
837 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
838 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
839 MinAlign(Alignment, IncrementSize));
841 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
842 NewLoadedVT,LD->isVolatile(), Alignment);
843 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
844 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
845 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
846 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
847 MinAlign(Alignment, IncrementSize));
850 // aggregate the two parts
851 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
852 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
853 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
855 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
858 SDValue Ops[] = { Result, TF };
859 return DAG.getMergeValues(Ops, 2);
862 /// UnrollVectorOp - We know that the given vector has a legal type, however
863 /// the operation it performs is not legal and is an operation that we have
864 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
865 /// operating on each element individually.
866 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
867 MVT VT = Op.getValueType();
868 assert(isTypeLegal(VT) &&
869 "Caller should expand or promote operands that are not legal!");
870 assert(Op.getNode()->getNumValues() == 1 &&
871 "Can't unroll a vector with multiple results!");
872 unsigned NE = VT.getVectorNumElements();
873 MVT EltVT = VT.getVectorElementType();
875 SmallVector<SDValue, 8> Scalars;
876 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
877 for (unsigned i = 0; i != NE; ++i) {
878 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
879 SDValue Operand = Op.getOperand(j);
880 MVT OperandVT = Operand.getValueType();
881 if (OperandVT.isVector()) {
882 // A vector operand; extract a single element.
883 MVT OperandEltVT = OperandVT.getVectorElementType();
884 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
887 DAG.getConstant(i, MVT::i32));
889 // A scalar operand; just use it as is.
890 Operands[j] = Operand;
894 switch (Op.getOpcode()) {
896 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
897 &Operands[0], Operands.size()));
902 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, Operands[0],
903 LegalizeShiftAmount(Operands[1])));
908 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
911 /// GetFPLibCall - Return the right libcall for the given floating point type.
912 static RTLIB::Libcall GetFPLibCall(MVT VT,
913 RTLIB::Libcall Call_F32,
914 RTLIB::Libcall Call_F64,
915 RTLIB::Libcall Call_F80,
916 RTLIB::Libcall Call_PPCF128) {
918 VT == MVT::f32 ? Call_F32 :
919 VT == MVT::f64 ? Call_F64 :
920 VT == MVT::f80 ? Call_F80 :
921 VT == MVT::ppcf128 ? Call_PPCF128 :
922 RTLIB::UNKNOWN_LIBCALL;
925 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
926 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
927 /// is necessary to spill the vector being inserted into to memory, perform
928 /// the insert there, and then read the result back.
929 SDValue SelectionDAGLegalize::
930 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) {
935 // If the target doesn't support this, we have to spill the input vector
936 // to a temporary stack slot, update the element, then reload it. This is
937 // badness. We could also load the value into a vector register (either
938 // with a "move to register" or "extload into register" instruction, then
939 // permute it into place, if the idx is a constant and if the idx is
940 // supported by the target.
941 MVT VT = Tmp1.getValueType();
942 MVT EltVT = VT.getVectorElementType();
943 MVT IdxVT = Tmp3.getValueType();
944 MVT PtrVT = TLI.getPointerTy();
945 SDValue StackPtr = DAG.CreateStackTemporary(VT);
947 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
950 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
951 PseudoSourceValue::getFixedStack(SPFI), 0);
953 // Truncate or zero extend offset to target pointer type.
954 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
955 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
956 // Add the offset to the index.
957 unsigned EltSize = EltVT.getSizeInBits()/8;
958 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
959 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
960 // Store the scalar value.
961 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
962 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
963 // Load the updated vector.
964 return DAG.getLoad(VT, Ch, StackPtr,
965 PseudoSourceValue::getFixedStack(SPFI), 0);
968 SDValue SelectionDAGLegalize::LegalizeShiftAmount(SDValue ShiftAmt) {
969 if (TLI.getShiftAmountTy().bitsLT(ShiftAmt.getValueType()))
970 return DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt);
972 if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType()))
973 return DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt);
979 /// LegalizeOp - We know that the specified value has a legal type, and
980 /// that its operands are legal. Now ensure that the operation itself
981 /// is legal, recursively ensuring that the operands' operations remain
983 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
984 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
987 assert(isTypeLegal(Op.getValueType()) &&
988 "Caller should expand or promote operands that are not legal!");
989 SDNode *Node = Op.getNode();
991 // If this operation defines any values that cannot be represented in a
992 // register on this target, make sure to expand or promote them.
993 if (Node->getNumValues() > 1) {
994 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
995 if (getTypeAction(Node->getValueType(i)) != Legal) {
996 HandleOp(Op.getValue(i));
997 assert(LegalizedNodes.count(Op) &&
998 "Handling didn't add legal operands!");
999 return LegalizedNodes[Op];
1003 // Note that LegalizeOp may be reentered even from single-use nodes, which
1004 // means that we always must cache transformed nodes.
1005 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1006 if (I != LegalizedNodes.end()) return I->second;
1008 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
1009 SDValue Result = Op;
1010 bool isCustom = false;
1012 switch (Node->getOpcode()) {
1013 case ISD::FrameIndex:
1014 case ISD::EntryToken:
1016 case ISD::BasicBlock:
1017 case ISD::TargetFrameIndex:
1018 case ISD::TargetJumpTable:
1019 case ISD::TargetConstant:
1020 case ISD::TargetConstantFP:
1021 case ISD::TargetConstantPool:
1022 case ISD::TargetGlobalAddress:
1023 case ISD::TargetGlobalTLSAddress:
1024 case ISD::TargetExternalSymbol:
1025 case ISD::VALUETYPE:
1027 case ISD::MEMOPERAND:
1029 case ISD::ARG_FLAGS:
1030 // Primitives must all be legal.
1031 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
1032 "This must be legal!");
1035 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1036 // If this is a target node, legalize it by legalizing the operands then
1037 // passing it through.
1038 SmallVector<SDValue, 8> Ops;
1039 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1040 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1042 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
1044 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1045 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
1046 return Result.getValue(Op.getResNo());
1048 // Otherwise this is an unhandled builtin node. splat.
1050 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
1052 assert(0 && "Do not know how to legalize this operator!");
1054 case ISD::GLOBAL_OFFSET_TABLE:
1055 case ISD::GlobalAddress:
1056 case ISD::GlobalTLSAddress:
1057 case ISD::ExternalSymbol:
1058 case ISD::ConstantPool:
1059 case ISD::JumpTable: // Nothing to do.
1060 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1061 default: assert(0 && "This action is not supported yet!");
1062 case TargetLowering::Custom:
1063 Tmp1 = TLI.LowerOperation(Op, DAG);
1064 if (Tmp1.getNode()) Result = Tmp1;
1065 // FALLTHROUGH if the target doesn't want to lower this op after all.
1066 case TargetLowering::Legal:
1070 case ISD::FRAMEADDR:
1071 case ISD::RETURNADDR:
1072 // The only option for these nodes is to custom lower them. If the target
1073 // does not custom lower them, then return zero.
1074 Tmp1 = TLI.LowerOperation(Op, DAG);
1078 Result = DAG.getConstant(0, TLI.getPointerTy());
1080 case ISD::FRAME_TO_ARGS_OFFSET: {
1081 MVT VT = Node->getValueType(0);
1082 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1083 default: assert(0 && "This action is not supported yet!");
1084 case TargetLowering::Custom:
1085 Result = TLI.LowerOperation(Op, DAG);
1086 if (Result.getNode()) break;
1088 case TargetLowering::Legal:
1089 Result = DAG.getConstant(0, VT);
1094 case ISD::EXCEPTIONADDR: {
1095 Tmp1 = LegalizeOp(Node->getOperand(0));
1096 MVT VT = Node->getValueType(0);
1097 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1098 default: assert(0 && "This action is not supported yet!");
1099 case TargetLowering::Expand: {
1100 unsigned Reg = TLI.getExceptionAddressRegister();
1101 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
1104 case TargetLowering::Custom:
1105 Result = TLI.LowerOperation(Op, DAG);
1106 if (Result.getNode()) break;
1108 case TargetLowering::Legal: {
1109 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
1110 Result = DAG.getMergeValues(Ops, 2);
1115 if (Result.getNode()->getNumValues() == 1) break;
1117 assert(Result.getNode()->getNumValues() == 2 &&
1118 "Cannot return more than two values!");
1120 // Since we produced two values, make sure to remember that we
1121 // legalized both of them.
1122 Tmp1 = LegalizeOp(Result);
1123 Tmp2 = LegalizeOp(Result.getValue(1));
1124 AddLegalizedOperand(Op.getValue(0), Tmp1);
1125 AddLegalizedOperand(Op.getValue(1), Tmp2);
1126 return Op.getResNo() ? Tmp2 : Tmp1;
1127 case ISD::EHSELECTION: {
1128 Tmp1 = LegalizeOp(Node->getOperand(0));
1129 Tmp2 = LegalizeOp(Node->getOperand(1));
1130 MVT VT = Node->getValueType(0);
1131 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1132 default: assert(0 && "This action is not supported yet!");
1133 case TargetLowering::Expand: {
1134 unsigned Reg = TLI.getExceptionSelectorRegister();
1135 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
1138 case TargetLowering::Custom:
1139 Result = TLI.LowerOperation(Op, DAG);
1140 if (Result.getNode()) break;
1142 case TargetLowering::Legal: {
1143 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
1144 Result = DAG.getMergeValues(Ops, 2);
1149 if (Result.getNode()->getNumValues() == 1) break;
1151 assert(Result.getNode()->getNumValues() == 2 &&
1152 "Cannot return more than two values!");
1154 // Since we produced two values, make sure to remember that we
1155 // legalized both of them.
1156 Tmp1 = LegalizeOp(Result);
1157 Tmp2 = LegalizeOp(Result.getValue(1));
1158 AddLegalizedOperand(Op.getValue(0), Tmp1);
1159 AddLegalizedOperand(Op.getValue(1), Tmp2);
1160 return Op.getResNo() ? Tmp2 : Tmp1;
1161 case ISD::EH_RETURN: {
1162 MVT VT = Node->getValueType(0);
1163 // The only "good" option for this node is to custom lower it.
1164 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1165 default: assert(0 && "This action is not supported at all!");
1166 case TargetLowering::Custom:
1167 Result = TLI.LowerOperation(Op, DAG);
1168 if (Result.getNode()) break;
1170 case TargetLowering::Legal:
1171 // Target does not know, how to lower this, lower to noop
1172 Result = LegalizeOp(Node->getOperand(0));
1177 case ISD::AssertSext:
1178 case ISD::AssertZext:
1179 Tmp1 = LegalizeOp(Node->getOperand(0));
1180 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1182 case ISD::MERGE_VALUES:
1183 // Legalize eliminates MERGE_VALUES nodes.
1184 Result = Node->getOperand(Op.getResNo());
1186 case ISD::CopyFromReg:
1187 Tmp1 = LegalizeOp(Node->getOperand(0));
1188 Result = Op.getValue(0);
1189 if (Node->getNumValues() == 2) {
1190 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1192 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1193 if (Node->getNumOperands() == 3) {
1194 Tmp2 = LegalizeOp(Node->getOperand(2));
1195 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1197 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1199 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1201 // Since CopyFromReg produces two values, make sure to remember that we
1202 // legalized both of them.
1203 AddLegalizedOperand(Op.getValue(0), Result);
1204 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1205 return Result.getValue(Op.getResNo());
1207 MVT VT = Op.getValueType();
1208 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1209 default: assert(0 && "This action is not supported yet!");
1210 case TargetLowering::Expand:
1212 Result = DAG.getConstant(0, VT);
1213 else if (VT.isFloatingPoint())
1214 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1217 assert(0 && "Unknown value type!");
1219 case TargetLowering::Legal:
1225 case ISD::INTRINSIC_W_CHAIN:
1226 case ISD::INTRINSIC_WO_CHAIN:
1227 case ISD::INTRINSIC_VOID: {
1228 SmallVector<SDValue, 8> Ops;
1229 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1230 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1231 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1233 // Allow the target to custom lower its intrinsics if it wants to.
1234 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1235 TargetLowering::Custom) {
1236 Tmp3 = TLI.LowerOperation(Result, DAG);
1237 if (Tmp3.getNode()) Result = Tmp3;
1240 if (Result.getNode()->getNumValues() == 1) break;
1242 // Must have return value and chain result.
1243 assert(Result.getNode()->getNumValues() == 2 &&
1244 "Cannot return more than two values!");
1246 // Since loads produce two values, make sure to remember that we
1247 // legalized both of them.
1248 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1249 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1250 return Result.getValue(Op.getResNo());
1253 case ISD::DBG_STOPPOINT:
1254 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1255 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1257 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1258 case TargetLowering::Promote:
1259 default: assert(0 && "This action is not supported yet!");
1260 case TargetLowering::Expand: {
1261 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1262 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1263 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
1265 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1266 if (MMI && (useDEBUG_LOC || useLABEL)) {
1267 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
1268 unsigned SrcFile = MMI->RecordSource(CompileUnit);
1270 unsigned Line = DSP->getLine();
1271 unsigned Col = DSP->getColumn();
1274 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1275 DAG.getConstant(Col, MVT::i32),
1276 DAG.getConstant(SrcFile, MVT::i32) };
1277 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
1279 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1280 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1283 Result = Tmp1; // chain
1287 case TargetLowering::Legal: {
1288 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1289 if (Action == Legal && Tmp1 == Node->getOperand(0))
1292 SmallVector<SDValue, 8> Ops;
1293 Ops.push_back(Tmp1);
1294 if (Action == Legal) {
1295 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1296 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1298 // Otherwise promote them.
1299 Ops.push_back(PromoteOp(Node->getOperand(1)));
1300 Ops.push_back(PromoteOp(Node->getOperand(2)));
1302 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1303 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1304 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1311 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1312 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1313 default: assert(0 && "This action is not supported yet!");
1314 case TargetLowering::Legal:
1315 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1316 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1317 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1318 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1320 case TargetLowering::Expand:
1321 Result = LegalizeOp(Node->getOperand(0));
1326 case ISD::DEBUG_LOC:
1327 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1328 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1329 default: assert(0 && "This action is not supported yet!");
1330 case TargetLowering::Legal: {
1331 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1332 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1333 if (Action == Legal && Tmp1 == Node->getOperand(0))
1335 if (Action == Legal) {
1336 Tmp2 = Node->getOperand(1);
1337 Tmp3 = Node->getOperand(2);
1338 Tmp4 = Node->getOperand(3);
1340 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1341 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1342 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1344 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1350 case ISD::DBG_LABEL:
1352 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1353 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1354 default: assert(0 && "This action is not supported yet!");
1355 case TargetLowering::Legal:
1356 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1357 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1359 case TargetLowering::Expand:
1360 Result = LegalizeOp(Node->getOperand(0));
1366 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1367 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1368 default: assert(0 && "This action is not supported yet!");
1369 case TargetLowering::Legal:
1370 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1371 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1372 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1373 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1374 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1376 case TargetLowering::Expand:
1378 Result = LegalizeOp(Node->getOperand(0));
1383 case ISD::MEMBARRIER: {
1384 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1385 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1386 default: assert(0 && "This action is not supported yet!");
1387 case TargetLowering::Legal: {
1389 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1390 for (int x = 1; x < 6; ++x) {
1391 Ops[x] = Node->getOperand(x);
1392 if (!isTypeLegal(Ops[x].getValueType()))
1393 Ops[x] = PromoteOp(Ops[x]);
1395 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1398 case TargetLowering::Expand:
1399 //There is no libgcc call for this op
1400 Result = Node->getOperand(0); // Noop
1406 case ISD::ATOMIC_CMP_SWAP: {
1407 unsigned int num_operands = 4;
1408 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1410 for (unsigned int x = 0; x < num_operands; ++x)
1411 Ops[x] = LegalizeOp(Node->getOperand(x));
1412 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1414 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1415 default: assert(0 && "This action is not supported yet!");
1416 case TargetLowering::Custom:
1417 Result = TLI.LowerOperation(Result, DAG);
1419 case TargetLowering::Legal:
1422 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1423 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1424 return Result.getValue(Op.getResNo());
1426 case ISD::ATOMIC_LOAD_ADD:
1427 case ISD::ATOMIC_LOAD_SUB:
1428 case ISD::ATOMIC_LOAD_AND:
1429 case ISD::ATOMIC_LOAD_OR:
1430 case ISD::ATOMIC_LOAD_XOR:
1431 case ISD::ATOMIC_LOAD_NAND:
1432 case ISD::ATOMIC_LOAD_MIN:
1433 case ISD::ATOMIC_LOAD_MAX:
1434 case ISD::ATOMIC_LOAD_UMIN:
1435 case ISD::ATOMIC_LOAD_UMAX:
1436 case ISD::ATOMIC_SWAP: {
1437 unsigned int num_operands = 3;
1438 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1440 for (unsigned int x = 0; x < num_operands; ++x)
1441 Ops[x] = LegalizeOp(Node->getOperand(x));
1442 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1444 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1445 default: assert(0 && "This action is not supported yet!");
1446 case TargetLowering::Custom:
1447 Result = TLI.LowerOperation(Result, DAG);
1449 case TargetLowering::Legal:
1452 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1453 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1454 return Result.getValue(Op.getResNo());
1456 case ISD::Constant: {
1457 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1459 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1461 // We know we don't need to expand constants here, constants only have one
1462 // value and we check that it is fine above.
1464 if (opAction == TargetLowering::Custom) {
1465 Tmp1 = TLI.LowerOperation(Result, DAG);
1471 case ISD::ConstantFP: {
1472 // Spill FP immediates to the constant pool if the target cannot directly
1473 // codegen them. Targets often have some immediate values that can be
1474 // efficiently generated into an FP register without a load. We explicitly
1475 // leave these constants as ConstantFP nodes for the target to deal with.
1476 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1478 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1479 default: assert(0 && "This action is not supported yet!");
1480 case TargetLowering::Legal:
1482 case TargetLowering::Custom:
1483 Tmp3 = TLI.LowerOperation(Result, DAG);
1484 if (Tmp3.getNode()) {
1489 case TargetLowering::Expand: {
1490 // Check to see if this FP immediate is already legal.
1491 bool isLegal = false;
1492 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1493 E = TLI.legal_fpimm_end(); I != E; ++I) {
1494 if (CFP->isExactlyValue(*I)) {
1499 // If this is a legal constant, turn it into a TargetConstantFP node.
1502 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1507 case ISD::TokenFactor:
1508 if (Node->getNumOperands() == 2) {
1509 Tmp1 = LegalizeOp(Node->getOperand(0));
1510 Tmp2 = LegalizeOp(Node->getOperand(1));
1511 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1512 } else if (Node->getNumOperands() == 3) {
1513 Tmp1 = LegalizeOp(Node->getOperand(0));
1514 Tmp2 = LegalizeOp(Node->getOperand(1));
1515 Tmp3 = LegalizeOp(Node->getOperand(2));
1516 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1518 SmallVector<SDValue, 8> Ops;
1519 // Legalize the operands.
1520 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1521 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1522 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1526 case ISD::FORMAL_ARGUMENTS:
1528 // The only option for this is to custom lower it.
1529 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1530 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1531 // A call within a calling sequence must be legalized to something
1532 // other than the normal CALLSEQ_END. Violating this gets Legalize
1533 // into an infinite loop.
1534 assert ((!IsLegalizingCall ||
1535 Node->getOpcode() != ISD::CALL ||
1536 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1537 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1539 // The number of incoming and outgoing values should match; unless the final
1540 // outgoing value is a flag.
1541 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1542 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1543 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1545 "Lowering call/formal_arguments produced unexpected # results!");
1547 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1548 // remember that we legalized all of them, so it doesn't get relegalized.
1549 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1550 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1552 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1553 if (Op.getResNo() == i)
1555 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1558 case ISD::EXTRACT_SUBREG: {
1559 Tmp1 = LegalizeOp(Node->getOperand(0));
1560 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1561 assert(idx && "Operand must be a constant");
1562 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1563 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1566 case ISD::INSERT_SUBREG: {
1567 Tmp1 = LegalizeOp(Node->getOperand(0));
1568 Tmp2 = LegalizeOp(Node->getOperand(1));
1569 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1570 assert(idx && "Operand must be a constant");
1571 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1572 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1575 case ISD::BUILD_VECTOR:
1576 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1577 default: assert(0 && "This action is not supported yet!");
1578 case TargetLowering::Custom:
1579 Tmp3 = TLI.LowerOperation(Result, DAG);
1580 if (Tmp3.getNode()) {
1585 case TargetLowering::Expand:
1586 Result = ExpandBUILD_VECTOR(Result.getNode());
1590 case ISD::INSERT_VECTOR_ELT:
1591 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1592 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1594 // The type of the value to insert may not be legal, even though the vector
1595 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1597 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1598 default: assert(0 && "Cannot expand insert element operand");
1599 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1600 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1602 // FIXME: An alternative would be to check to see if the target is not
1603 // going to custom lower this operation, we could bitcast to half elt
1604 // width and perform two inserts at that width, if that is legal.
1605 Tmp2 = Node->getOperand(1);
1608 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1610 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1611 Node->getValueType(0))) {
1612 default: assert(0 && "This action is not supported yet!");
1613 case TargetLowering::Legal:
1615 case TargetLowering::Custom:
1616 Tmp4 = TLI.LowerOperation(Result, DAG);
1617 if (Tmp4.getNode()) {
1622 case TargetLowering::Promote:
1623 // Fall thru for vector case
1624 case TargetLowering::Expand: {
1625 // If the insert index is a constant, codegen this as a scalar_to_vector,
1626 // then a shuffle that inserts it into the right position in the vector.
1627 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1628 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1629 // match the element type of the vector being created.
1630 if (Tmp2.getValueType() ==
1631 Op.getValueType().getVectorElementType()) {
1632 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1633 Tmp1.getValueType(), Tmp2);
1635 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1637 MVT::getIntVectorWithNumElements(NumElts);
1638 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1640 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1641 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1642 // elt 0 of the RHS.
1643 SmallVector<SDValue, 8> ShufOps;
1644 for (unsigned i = 0; i != NumElts; ++i) {
1645 if (i != InsertPos->getZExtValue())
1646 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1648 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1650 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1651 &ShufOps[0], ShufOps.size());
1653 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1654 Tmp1, ScVec, ShufMask);
1655 Result = LegalizeOp(Result);
1659 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1664 case ISD::SCALAR_TO_VECTOR:
1665 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1666 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1670 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1671 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1672 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1673 Node->getValueType(0))) {
1674 default: assert(0 && "This action is not supported yet!");
1675 case TargetLowering::Legal:
1677 case TargetLowering::Custom:
1678 Tmp3 = TLI.LowerOperation(Result, DAG);
1679 if (Tmp3.getNode()) {
1684 case TargetLowering::Expand:
1685 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1689 case ISD::VECTOR_SHUFFLE:
1690 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1691 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1692 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1694 // Allow targets to custom lower the SHUFFLEs they support.
1695 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1696 default: assert(0 && "Unknown operation action!");
1697 case TargetLowering::Legal:
1698 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1699 "vector shuffle should not be created if not legal!");
1701 case TargetLowering::Custom:
1702 Tmp3 = TLI.LowerOperation(Result, DAG);
1703 if (Tmp3.getNode()) {
1708 case TargetLowering::Expand: {
1709 MVT VT = Node->getValueType(0);
1710 MVT EltVT = VT.getVectorElementType();
1711 MVT PtrVT = TLI.getPointerTy();
1712 SDValue Mask = Node->getOperand(2);
1713 unsigned NumElems = Mask.getNumOperands();
1714 SmallVector<SDValue,8> Ops;
1715 for (unsigned i = 0; i != NumElems; ++i) {
1716 SDValue Arg = Mask.getOperand(i);
1717 if (Arg.getOpcode() == ISD::UNDEF) {
1718 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1720 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1721 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1723 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1724 DAG.getConstant(Idx, PtrVT)));
1726 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1727 DAG.getConstant(Idx - NumElems, PtrVT)));
1730 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1733 case TargetLowering::Promote: {
1734 // Change base type to a different vector type.
1735 MVT OVT = Node->getValueType(0);
1736 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1738 // Cast the two input vectors.
1739 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1740 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1742 // Convert the shuffle mask to the right # elements.
1743 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1744 assert(Tmp3.getNode() && "Shuffle not legal?");
1745 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1746 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1752 case ISD::EXTRACT_VECTOR_ELT:
1753 Tmp1 = Node->getOperand(0);
1754 Tmp2 = LegalizeOp(Node->getOperand(1));
1755 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1756 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1759 case ISD::EXTRACT_SUBVECTOR:
1760 Tmp1 = Node->getOperand(0);
1761 Tmp2 = LegalizeOp(Node->getOperand(1));
1762 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1763 Result = ExpandEXTRACT_SUBVECTOR(Result);
1766 case ISD::CONCAT_VECTORS: {
1767 // Use extract/insert/build vector for now. We might try to be
1768 // more clever later.
1769 MVT PtrVT = TLI.getPointerTy();
1770 SmallVector<SDValue, 8> Ops;
1771 unsigned NumOperands = Node->getNumOperands();
1772 for (unsigned i=0; i < NumOperands; ++i) {
1773 SDValue SubOp = Node->getOperand(i);
1774 MVT VVT = SubOp.getNode()->getValueType(0);
1775 MVT EltVT = VVT.getVectorElementType();
1776 unsigned NumSubElem = VVT.getVectorNumElements();
1777 for (unsigned j=0; j < NumSubElem; ++j) {
1778 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, SubOp,
1779 DAG.getConstant(j, PtrVT)));
1782 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
1783 &Ops[0], Ops.size()));
1786 case ISD::CALLSEQ_START: {
1787 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1789 // Recursively Legalize all of the inputs of the call end that do not lead
1790 // to this call start. This ensures that any libcalls that need be inserted
1791 // are inserted *before* the CALLSEQ_START.
1792 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1793 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1794 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1798 // Now that we legalized all of the inputs (which may have inserted
1799 // libcalls) create the new CALLSEQ_START node.
1800 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1802 // Merge in the last call, to ensure that this call start after the last
1804 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1805 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1806 Tmp1 = LegalizeOp(Tmp1);
1809 // Do not try to legalize the target-specific arguments (#1+).
1810 if (Tmp1 != Node->getOperand(0)) {
1811 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1813 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1816 // Remember that the CALLSEQ_START is legalized.
1817 AddLegalizedOperand(Op.getValue(0), Result);
1818 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1819 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1821 // Now that the callseq_start and all of the non-call nodes above this call
1822 // sequence have been legalized, legalize the call itself. During this
1823 // process, no libcalls can/will be inserted, guaranteeing that no calls
1825 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1826 // Note that we are selecting this call!
1827 LastCALLSEQ_END = SDValue(CallEnd, 0);
1828 IsLegalizingCall = true;
1830 // Legalize the call, starting from the CALLSEQ_END.
1831 LegalizeOp(LastCALLSEQ_END);
1832 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1835 case ISD::CALLSEQ_END:
1836 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1837 // will cause this node to be legalized as well as handling libcalls right.
1838 if (LastCALLSEQ_END.getNode() != Node) {
1839 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1840 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1841 assert(I != LegalizedNodes.end() &&
1842 "Legalizing the call start should have legalized this node!");
1846 // Otherwise, the call start has been legalized and everything is going
1847 // according to plan. Just legalize ourselves normally here.
1848 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1849 // Do not try to legalize the target-specific arguments (#1+), except for
1850 // an optional flag input.
1851 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1852 if (Tmp1 != Node->getOperand(0)) {
1853 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1855 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1858 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1859 if (Tmp1 != Node->getOperand(0) ||
1860 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1861 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1864 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1867 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1868 // This finishes up call legalization.
1869 IsLegalizingCall = false;
1871 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1872 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1873 if (Node->getNumValues() == 2)
1874 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1875 return Result.getValue(Op.getResNo());
1876 case ISD::DYNAMIC_STACKALLOC: {
1877 MVT VT = Node->getValueType(0);
1878 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1879 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1880 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1881 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1883 Tmp1 = Result.getValue(0);
1884 Tmp2 = Result.getValue(1);
1885 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1886 default: assert(0 && "This action is not supported yet!");
1887 case TargetLowering::Expand: {
1888 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1889 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1890 " not tell us which reg is the stack pointer!");
1891 SDValue Chain = Tmp1.getOperand(0);
1893 // Chain the dynamic stack allocation so that it doesn't modify the stack
1894 // pointer when other instructions are using the stack.
1895 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1897 SDValue Size = Tmp2.getOperand(1);
1898 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1899 Chain = SP.getValue(1);
1900 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1901 unsigned StackAlign =
1902 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1903 if (Align > StackAlign)
1904 SP = DAG.getNode(ISD::AND, VT, SP,
1905 DAG.getConstant(-(uint64_t)Align, VT));
1906 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1907 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1909 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1910 DAG.getIntPtrConstant(0, true), SDValue());
1912 Tmp1 = LegalizeOp(Tmp1);
1913 Tmp2 = LegalizeOp(Tmp2);
1916 case TargetLowering::Custom:
1917 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1918 if (Tmp3.getNode()) {
1919 Tmp1 = LegalizeOp(Tmp3);
1920 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1923 case TargetLowering::Legal:
1926 // Since this op produce two values, make sure to remember that we
1927 // legalized both of them.
1928 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1929 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1930 return Op.getResNo() ? Tmp2 : Tmp1;
1932 case ISD::INLINEASM: {
1933 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1934 bool Changed = false;
1935 // Legalize all of the operands of the inline asm, in case they are nodes
1936 // that need to be expanded or something. Note we skip the asm string and
1937 // all of the TargetConstant flags.
1938 SDValue Op = LegalizeOp(Ops[0]);
1939 Changed = Op != Ops[0];
1942 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1943 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1944 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3;
1945 for (++i; NumVals; ++i, --NumVals) {
1946 SDValue Op = LegalizeOp(Ops[i]);
1955 Op = LegalizeOp(Ops.back());
1956 Changed |= Op != Ops.back();
1961 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1963 // INLINE asm returns a chain and flag, make sure to add both to the map.
1964 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1965 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1966 return Result.getValue(Op.getResNo());
1969 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1970 // Ensure that libcalls are emitted before a branch.
1971 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1972 Tmp1 = LegalizeOp(Tmp1);
1973 LastCALLSEQ_END = DAG.getEntryNode();
1975 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1978 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1979 // Ensure that libcalls are emitted before a branch.
1980 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1981 Tmp1 = LegalizeOp(Tmp1);
1982 LastCALLSEQ_END = DAG.getEntryNode();
1984 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1985 default: assert(0 && "Indirect target must be legal type (pointer)!");
1987 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1990 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1993 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1994 // Ensure that libcalls are emitted before a branch.
1995 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1996 Tmp1 = LegalizeOp(Tmp1);
1997 LastCALLSEQ_END = DAG.getEntryNode();
1999 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
2000 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2002 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
2003 default: assert(0 && "This action is not supported yet!");
2004 case TargetLowering::Legal: break;
2005 case TargetLowering::Custom:
2006 Tmp1 = TLI.LowerOperation(Result, DAG);
2007 if (Tmp1.getNode()) Result = Tmp1;
2009 case TargetLowering::Expand: {
2010 SDValue Chain = Result.getOperand(0);
2011 SDValue Table = Result.getOperand(1);
2012 SDValue Index = Result.getOperand(2);
2014 MVT PTy = TLI.getPointerTy();
2015 MachineFunction &MF = DAG.getMachineFunction();
2016 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
2017 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
2018 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
2020 MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
2021 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, Chain, Addr,
2022 PseudoSourceValue::getJumpTable(), 0, MemVT);
2024 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2025 // For PIC, the sequence is:
2026 // BRIND(load(Jumptable + index) + RelocBase)
2027 // RelocBase can be JumpTable, GOT or some sort of global base.
2028 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
2029 TLI.getPICJumpTableRelocBase(Table, DAG));
2031 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
2036 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2037 // Ensure that libcalls are emitted before a return.
2038 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2039 Tmp1 = LegalizeOp(Tmp1);
2040 LastCALLSEQ_END = DAG.getEntryNode();
2042 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2043 case Expand: assert(0 && "It's impossible to expand bools");
2045 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2048 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
2050 // The top bits of the promoted condition are not necessarily zero, ensure
2051 // that the value is properly zero extended.
2052 unsigned BitWidth = Tmp2.getValueSizeInBits();
2053 if (!DAG.MaskedValueIsZero(Tmp2,
2054 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2055 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
2060 // Basic block destination (Op#2) is always legal.
2061 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2063 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
2064 default: assert(0 && "This action is not supported yet!");
2065 case TargetLowering::Legal: break;
2066 case TargetLowering::Custom:
2067 Tmp1 = TLI.LowerOperation(Result, DAG);
2068 if (Tmp1.getNode()) Result = Tmp1;
2070 case TargetLowering::Expand:
2071 // Expand brcond's setcc into its constituent parts and create a BR_CC
2073 if (Tmp2.getOpcode() == ISD::SETCC) {
2074 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
2075 Tmp2.getOperand(0), Tmp2.getOperand(1),
2076 Node->getOperand(2));
2078 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
2079 DAG.getCondCode(ISD::SETNE), Tmp2,
2080 DAG.getConstant(0, Tmp2.getValueType()),
2081 Node->getOperand(2));
2087 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2088 // Ensure that libcalls are emitted before a branch.
2089 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2090 Tmp1 = LegalizeOp(Tmp1);
2091 Tmp2 = Node->getOperand(2); // LHS
2092 Tmp3 = Node->getOperand(3); // RHS
2093 Tmp4 = Node->getOperand(1); // CC
2095 LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()), Tmp2, Tmp3,Tmp4);
2096 LastCALLSEQ_END = DAG.getEntryNode();
2098 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2099 // the LHS is a legal SETCC itself. In this case, we need to compare
2100 // the result against zero to select between true and false values.
2101 if (Tmp3.getNode() == 0) {
2102 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2103 Tmp4 = DAG.getCondCode(ISD::SETNE);
2106 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
2107 Node->getOperand(4));
2109 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
2110 default: assert(0 && "Unexpected action for BR_CC!");
2111 case TargetLowering::Legal: break;
2112 case TargetLowering::Custom:
2113 Tmp4 = TLI.LowerOperation(Result, DAG);
2114 if (Tmp4.getNode()) Result = Tmp4;
2119 LoadSDNode *LD = cast<LoadSDNode>(Node);
2120 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
2121 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
2123 ISD::LoadExtType ExtType = LD->getExtensionType();
2124 if (ExtType == ISD::NON_EXTLOAD) {
2125 MVT VT = Node->getValueType(0);
2126 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2127 Tmp3 = Result.getValue(0);
2128 Tmp4 = Result.getValue(1);
2130 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
2131 default: assert(0 && "This action is not supported yet!");
2132 case TargetLowering::Legal:
2133 // If this is an unaligned load and the target doesn't support it,
2135 if (!TLI.allowsUnalignedMemoryAccesses()) {
2136 unsigned ABIAlignment = TLI.getTargetData()->
2137 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2138 if (LD->getAlignment() < ABIAlignment){
2139 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2141 Tmp3 = Result.getOperand(0);
2142 Tmp4 = Result.getOperand(1);
2143 Tmp3 = LegalizeOp(Tmp3);
2144 Tmp4 = LegalizeOp(Tmp4);
2148 case TargetLowering::Custom:
2149 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
2150 if (Tmp1.getNode()) {
2151 Tmp3 = LegalizeOp(Tmp1);
2152 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2155 case TargetLowering::Promote: {
2156 // Only promote a load of vector type to another.
2157 assert(VT.isVector() && "Cannot promote this load!");
2158 // Change base type to a different vector type.
2159 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
2161 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
2162 LD->getSrcValueOffset(),
2163 LD->isVolatile(), LD->getAlignment());
2164 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
2165 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2169 // Since loads produce two values, make sure to remember that we
2170 // legalized both of them.
2171 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
2172 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
2173 return Op.getResNo() ? Tmp4 : Tmp3;
2175 MVT SrcVT = LD->getMemoryVT();
2176 unsigned SrcWidth = SrcVT.getSizeInBits();
2177 int SVOffset = LD->getSrcValueOffset();
2178 unsigned Alignment = LD->getAlignment();
2179 bool isVolatile = LD->isVolatile();
2181 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
2182 // Some targets pretend to have an i1 loading operation, and actually
2183 // load an i8. This trick is correct for ZEXTLOAD because the top 7
2184 // bits are guaranteed to be zero; it helps the optimizers understand
2185 // that these bits are zero. It is also useful for EXTLOAD, since it
2186 // tells the optimizers that those bits are undefined. It would be
2187 // nice to have an effective generic way of getting these benefits...
2188 // Until such a way is found, don't insist on promoting i1 here.
2189 (SrcVT != MVT::i1 ||
2190 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2191 // Promote to a byte-sized load if not loading an integral number of
2192 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2193 unsigned NewWidth = SrcVT.getStoreSizeInBits();
2194 MVT NVT = MVT::getIntegerVT(NewWidth);
2197 // The extra bits are guaranteed to be zero, since we stored them that
2198 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2200 ISD::LoadExtType NewExtType =
2201 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2203 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2204 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2205 NVT, isVolatile, Alignment);
2207 Ch = Result.getValue(1); // The chain.
2209 if (ExtType == ISD::SEXTLOAD)
2210 // Having the top bits zero doesn't help when sign extending.
2211 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2212 Result, DAG.getValueType(SrcVT));
2213 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2214 // All the top bits are guaranteed to be zero - inform the optimizers.
2215 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2216 DAG.getValueType(SrcVT));
2218 Tmp1 = LegalizeOp(Result);
2219 Tmp2 = LegalizeOp(Ch);
2220 } else if (SrcWidth & (SrcWidth - 1)) {
2221 // If not loading a power-of-2 number of bits, expand as two loads.
2222 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2223 "Unsupported extload!");
2224 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2225 assert(RoundWidth < SrcWidth);
2226 unsigned ExtraWidth = SrcWidth - RoundWidth;
2227 assert(ExtraWidth < RoundWidth);
2228 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2229 "Load size not an integral number of bytes!");
2230 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2231 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2233 unsigned IncrementSize;
2235 if (TLI.isLittleEndian()) {
2236 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2237 // Load the bottom RoundWidth bits.
2238 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2239 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2242 // Load the remaining ExtraWidth bits.
2243 IncrementSize = RoundWidth / 8;
2244 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2245 DAG.getIntPtrConstant(IncrementSize));
2246 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2247 LD->getSrcValue(), SVOffset + IncrementSize,
2248 ExtraVT, isVolatile,
2249 MinAlign(Alignment, IncrementSize));
2251 // Build a factor node to remember that this load is independent of the
2253 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2256 // Move the top bits to the right place.
2257 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2258 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2260 // Join the hi and lo parts.
2261 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2263 // Big endian - avoid unaligned loads.
2264 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2265 // Load the top RoundWidth bits.
2266 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2267 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2270 // Load the remaining ExtraWidth bits.
2271 IncrementSize = RoundWidth / 8;
2272 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2273 DAG.getIntPtrConstant(IncrementSize));
2274 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2275 LD->getSrcValue(), SVOffset + IncrementSize,
2276 ExtraVT, isVolatile,
2277 MinAlign(Alignment, IncrementSize));
2279 // Build a factor node to remember that this load is independent of the
2281 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2284 // Move the top bits to the right place.
2285 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2286 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2288 // Join the hi and lo parts.
2289 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2292 Tmp1 = LegalizeOp(Result);
2293 Tmp2 = LegalizeOp(Ch);
2295 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
2296 default: assert(0 && "This action is not supported yet!");
2297 case TargetLowering::Custom:
2300 case TargetLowering::Legal:
2301 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2302 Tmp1 = Result.getValue(0);
2303 Tmp2 = Result.getValue(1);
2306 Tmp3 = TLI.LowerOperation(Result, DAG);
2307 if (Tmp3.getNode()) {
2308 Tmp1 = LegalizeOp(Tmp3);
2309 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2312 // If this is an unaligned load and the target doesn't support it,
2314 if (!TLI.allowsUnalignedMemoryAccesses()) {
2315 unsigned ABIAlignment = TLI.getTargetData()->
2316 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2317 if (LD->getAlignment() < ABIAlignment){
2318 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2320 Tmp1 = Result.getOperand(0);
2321 Tmp2 = Result.getOperand(1);
2322 Tmp1 = LegalizeOp(Tmp1);
2323 Tmp2 = LegalizeOp(Tmp2);
2328 case TargetLowering::Expand:
2329 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2330 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2331 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2332 LD->getSrcValueOffset(),
2333 LD->isVolatile(), LD->getAlignment());
2334 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2335 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2336 Tmp2 = LegalizeOp(Load.getValue(1));
2339 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2340 // Turn the unsupported load into an EXTLOAD followed by an explicit
2341 // zero/sign extend inreg.
2342 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2343 Tmp1, Tmp2, LD->getSrcValue(),
2344 LD->getSrcValueOffset(), SrcVT,
2345 LD->isVolatile(), LD->getAlignment());
2347 if (ExtType == ISD::SEXTLOAD)
2348 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2349 Result, DAG.getValueType(SrcVT));
2351 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2352 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2353 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2358 // Since loads produce two values, make sure to remember that we legalized
2360 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2361 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2362 return Op.getResNo() ? Tmp2 : Tmp1;
2365 case ISD::EXTRACT_ELEMENT: {
2366 MVT OpTy = Node->getOperand(0).getValueType();
2367 switch (getTypeAction(OpTy)) {
2368 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2370 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2372 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2373 DAG.getConstant(OpTy.getSizeInBits()/2,
2374 TLI.getShiftAmountTy()));
2375 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2378 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2379 Node->getOperand(0));
2383 // Get both the low and high parts.
2384 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2385 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2386 Result = Tmp2; // 1 -> Hi
2388 Result = Tmp1; // 0 -> Lo
2394 case ISD::CopyToReg:
2395 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2397 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2398 "Register type must be legal!");
2399 // Legalize the incoming value (must be a legal type).
2400 Tmp2 = LegalizeOp(Node->getOperand(2));
2401 if (Node->getNumValues() == 1) {
2402 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2404 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2405 if (Node->getNumOperands() == 4) {
2406 Tmp3 = LegalizeOp(Node->getOperand(3));
2407 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2410 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2413 // Since this produces two values, make sure to remember that we legalized
2415 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2416 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2422 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2424 // Ensure that libcalls are emitted before a return.
2425 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2426 Tmp1 = LegalizeOp(Tmp1);
2427 LastCALLSEQ_END = DAG.getEntryNode();
2429 switch (Node->getNumOperands()) {
2431 Tmp2 = Node->getOperand(1);
2432 Tmp3 = Node->getOperand(2); // Signness
2433 switch (getTypeAction(Tmp2.getValueType())) {
2435 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2438 if (!Tmp2.getValueType().isVector()) {
2440 ExpandOp(Tmp2, Lo, Hi);
2442 // Big endian systems want the hi reg first.
2443 if (TLI.isBigEndian())
2447 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2449 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2450 Result = LegalizeOp(Result);
2452 SDNode *InVal = Tmp2.getNode();
2453 int InIx = Tmp2.getResNo();
2454 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2455 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2457 // Figure out if there is a simple type corresponding to this Vector
2458 // type. If so, convert to the vector type.
2459 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2460 if (TLI.isTypeLegal(TVT)) {
2461 // Turn this into a return of the vector type.
2462 Tmp2 = LegalizeOp(Tmp2);
2463 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2464 } else if (NumElems == 1) {
2465 // Turn this into a return of the scalar type.
2466 Tmp2 = ScalarizeVectorOp(Tmp2);
2467 Tmp2 = LegalizeOp(Tmp2);
2468 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2470 // FIXME: Returns of gcc generic vectors smaller than a legal type
2471 // should be returned in integer registers!
2473 // The scalarized value type may not be legal, e.g. it might require
2474 // promotion or expansion. Relegalize the return.
2475 Result = LegalizeOp(Result);
2477 // FIXME: Returns of gcc generic vectors larger than a legal vector
2478 // type should be returned by reference!
2480 SplitVectorOp(Tmp2, Lo, Hi);
2481 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2482 Result = LegalizeOp(Result);
2487 Tmp2 = PromoteOp(Node->getOperand(1));
2488 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2489 Result = LegalizeOp(Result);
2494 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2496 default: { // ret <values>
2497 SmallVector<SDValue, 8> NewValues;
2498 NewValues.push_back(Tmp1);
2499 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2500 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2502 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2503 NewValues.push_back(Node->getOperand(i+1));
2507 assert(!Node->getOperand(i).getValueType().isExtended() &&
2508 "FIXME: TODO: implement returning non-legal vector types!");
2509 ExpandOp(Node->getOperand(i), Lo, Hi);
2510 NewValues.push_back(Lo);
2511 NewValues.push_back(Node->getOperand(i+1));
2513 NewValues.push_back(Hi);
2514 NewValues.push_back(Node->getOperand(i+1));
2519 assert(0 && "Can't promote multiple return value yet!");
2522 if (NewValues.size() == Node->getNumOperands())
2523 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2525 Result = DAG.getNode(ISD::RET, MVT::Other,
2526 &NewValues[0], NewValues.size());
2531 if (Result.getOpcode() == ISD::RET) {
2532 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2533 default: assert(0 && "This action is not supported yet!");
2534 case TargetLowering::Legal: break;
2535 case TargetLowering::Custom:
2536 Tmp1 = TLI.LowerOperation(Result, DAG);
2537 if (Tmp1.getNode()) Result = Tmp1;
2543 StoreSDNode *ST = cast<StoreSDNode>(Node);
2544 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2545 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2546 int SVOffset = ST->getSrcValueOffset();
2547 unsigned Alignment = ST->getAlignment();
2548 bool isVolatile = ST->isVolatile();
2550 if (!ST->isTruncatingStore()) {
2551 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2552 // FIXME: We shouldn't do this for TargetConstantFP's.
2553 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2554 // to phase ordering between legalized code and the dag combiner. This
2555 // probably means that we need to integrate dag combiner and legalizer
2557 // We generally can't do this one for long doubles.
2558 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2559 if (CFP->getValueType(0) == MVT::f32 &&
2560 getTypeAction(MVT::i32) == Legal) {
2561 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2562 bitcastToAPInt().zextOrTrunc(32),
2564 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2565 SVOffset, isVolatile, Alignment);
2567 } else if (CFP->getValueType(0) == MVT::f64) {
2568 // If this target supports 64-bit registers, do a single 64-bit store.
2569 if (getTypeAction(MVT::i64) == Legal) {
2570 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
2571 zextOrTrunc(64), MVT::i64);
2572 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2573 SVOffset, isVolatile, Alignment);
2575 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2576 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2577 // stores. If the target supports neither 32- nor 64-bits, this
2578 // xform is certainly not worth it.
2579 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
2580 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2581 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2582 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2584 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2585 SVOffset, isVolatile, Alignment);
2586 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2587 DAG.getIntPtrConstant(4));
2588 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2589 isVolatile, MinAlign(Alignment, 4U));
2591 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2597 switch (getTypeAction(ST->getMemoryVT())) {
2599 Tmp3 = LegalizeOp(ST->getValue());
2600 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2603 MVT VT = Tmp3.getValueType();
2604 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2605 default: assert(0 && "This action is not supported yet!");
2606 case TargetLowering::Legal:
2607 // If this is an unaligned store and the target doesn't support it,
2609 if (!TLI.allowsUnalignedMemoryAccesses()) {
2610 unsigned ABIAlignment = TLI.getTargetData()->
2611 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2612 if (ST->getAlignment() < ABIAlignment)
2613 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2617 case TargetLowering::Custom:
2618 Tmp1 = TLI.LowerOperation(Result, DAG);
2619 if (Tmp1.getNode()) Result = Tmp1;
2621 case TargetLowering::Promote:
2622 assert(VT.isVector() && "Unknown legal promote case!");
2623 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2624 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2625 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2626 ST->getSrcValue(), SVOffset, isVolatile,
2633 if (!ST->getMemoryVT().isVector()) {
2634 // Truncate the value and store the result.
2635 Tmp3 = PromoteOp(ST->getValue());
2636 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2637 SVOffset, ST->getMemoryVT(),
2638 isVolatile, Alignment);
2641 // Fall thru to expand for vector
2643 unsigned IncrementSize = 0;
2646 // If this is a vector type, then we have to calculate the increment as
2647 // the product of the element size in bytes, and the number of elements
2648 // in the high half of the vector.
2649 if (ST->getValue().getValueType().isVector()) {
2650 SDNode *InVal = ST->getValue().getNode();
2651 int InIx = ST->getValue().getResNo();
2652 MVT InVT = InVal->getValueType(InIx);
2653 unsigned NumElems = InVT.getVectorNumElements();
2654 MVT EVT = InVT.getVectorElementType();
2656 // Figure out if there is a simple type corresponding to this Vector
2657 // type. If so, convert to the vector type.
2658 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2659 if (TLI.isTypeLegal(TVT)) {
2660 // Turn this into a normal store of the vector type.
2661 Tmp3 = LegalizeOp(ST->getValue());
2662 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2663 SVOffset, isVolatile, Alignment);
2664 Result = LegalizeOp(Result);
2666 } else if (NumElems == 1) {
2667 // Turn this into a normal store of the scalar type.
2668 Tmp3 = ScalarizeVectorOp(ST->getValue());
2669 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2670 SVOffset, isVolatile, Alignment);
2671 // The scalarized value type may not be legal, e.g. it might require
2672 // promotion or expansion. Relegalize the scalar store.
2673 Result = LegalizeOp(Result);
2676 // Check if we have widen this node with another value
2677 std::map<SDValue, SDValue>::iterator I =
2678 WidenNodes.find(ST->getValue());
2679 if (I != WidenNodes.end()) {
2680 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2);
2684 SplitVectorOp(ST->getValue(), Lo, Hi);
2685 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2686 EVT.getSizeInBits()/8;
2690 ExpandOp(ST->getValue(), Lo, Hi);
2691 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2693 if (Hi.getNode() && TLI.isBigEndian())
2697 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2698 SVOffset, isVolatile, Alignment);
2700 if (Hi.getNode() == NULL) {
2701 // Must be int <-> float one-to-one expansion.
2706 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2707 DAG.getIntPtrConstant(IncrementSize));
2708 assert(isTypeLegal(Tmp2.getValueType()) &&
2709 "Pointers must be legal!");
2710 SVOffset += IncrementSize;
2711 Alignment = MinAlign(Alignment, IncrementSize);
2712 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2713 SVOffset, isVolatile, Alignment);
2714 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2719 switch (getTypeAction(ST->getValue().getValueType())) {
2721 Tmp3 = LegalizeOp(ST->getValue());
2724 if (!ST->getValue().getValueType().isVector()) {
2725 // We can promote the value, the truncstore will still take care of it.
2726 Tmp3 = PromoteOp(ST->getValue());
2729 // Vector case falls through to expand
2731 // Just store the low part. This may become a non-trunc store, so make
2732 // sure to use getTruncStore, not UpdateNodeOperands below.
2733 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2734 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2735 SVOffset, MVT::i8, isVolatile, Alignment);
2738 MVT StVT = ST->getMemoryVT();
2739 unsigned StWidth = StVT.getSizeInBits();
2741 if (StWidth != StVT.getStoreSizeInBits()) {
2742 // Promote to a byte-sized store with upper bits zero if not
2743 // storing an integral number of bytes. For example, promote
2744 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2745 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2746 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2747 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2748 SVOffset, NVT, isVolatile, Alignment);
2749 } else if (StWidth & (StWidth - 1)) {
2750 // If not storing a power-of-2 number of bits, expand as two stores.
2751 assert(StVT.isExtended() && !StVT.isVector() &&
2752 "Unsupported truncstore!");
2753 unsigned RoundWidth = 1 << Log2_32(StWidth);
2754 assert(RoundWidth < StWidth);
2755 unsigned ExtraWidth = StWidth - RoundWidth;
2756 assert(ExtraWidth < RoundWidth);
2757 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2758 "Store size not an integral number of bytes!");
2759 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2760 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2762 unsigned IncrementSize;
2764 if (TLI.isLittleEndian()) {
2765 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2766 // Store the bottom RoundWidth bits.
2767 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2769 isVolatile, Alignment);
2771 // Store the remaining ExtraWidth bits.
2772 IncrementSize = RoundWidth / 8;
2773 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2774 DAG.getIntPtrConstant(IncrementSize));
2775 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2776 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2777 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2778 SVOffset + IncrementSize, ExtraVT, isVolatile,
2779 MinAlign(Alignment, IncrementSize));
2781 // Big endian - avoid unaligned stores.
2782 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2783 // Store the top RoundWidth bits.
2784 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2785 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2786 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2787 RoundVT, isVolatile, Alignment);
2789 // Store the remaining ExtraWidth bits.
2790 IncrementSize = RoundWidth / 8;
2791 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2792 DAG.getIntPtrConstant(IncrementSize));
2793 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2794 SVOffset + IncrementSize, ExtraVT, isVolatile,
2795 MinAlign(Alignment, IncrementSize));
2798 // The order of the stores doesn't matter.
2799 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2801 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2802 Tmp2 != ST->getBasePtr())
2803 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2806 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2807 default: assert(0 && "This action is not supported yet!");
2808 case TargetLowering::Legal:
2809 // If this is an unaligned store and the target doesn't support it,
2811 if (!TLI.allowsUnalignedMemoryAccesses()) {
2812 unsigned ABIAlignment = TLI.getTargetData()->
2813 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2814 if (ST->getAlignment() < ABIAlignment)
2815 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2819 case TargetLowering::Custom:
2820 Result = TLI.LowerOperation(Result, DAG);
2823 // TRUNCSTORE:i16 i32 -> STORE i16
2824 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2825 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2826 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2827 isVolatile, Alignment);
2835 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2836 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2838 case ISD::STACKSAVE:
2839 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2840 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2841 Tmp1 = Result.getValue(0);
2842 Tmp2 = Result.getValue(1);
2844 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2845 default: assert(0 && "This action is not supported yet!");
2846 case TargetLowering::Legal: break;
2847 case TargetLowering::Custom:
2848 Tmp3 = TLI.LowerOperation(Result, DAG);
2849 if (Tmp3.getNode()) {
2850 Tmp1 = LegalizeOp(Tmp3);
2851 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2854 case TargetLowering::Expand:
2855 // Expand to CopyFromReg if the target set
2856 // StackPointerRegisterToSaveRestore.
2857 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2858 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2859 Node->getValueType(0));
2860 Tmp2 = Tmp1.getValue(1);
2862 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2863 Tmp2 = Node->getOperand(0);
2868 // Since stacksave produce two values, make sure to remember that we
2869 // legalized both of them.
2870 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2871 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2872 return Op.getResNo() ? Tmp2 : Tmp1;
2874 case ISD::STACKRESTORE:
2875 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2876 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2877 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2879 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2880 default: assert(0 && "This action is not supported yet!");
2881 case TargetLowering::Legal: break;
2882 case TargetLowering::Custom:
2883 Tmp1 = TLI.LowerOperation(Result, DAG);
2884 if (Tmp1.getNode()) Result = Tmp1;
2886 case TargetLowering::Expand:
2887 // Expand to CopyToReg if the target set
2888 // StackPointerRegisterToSaveRestore.
2889 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2890 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2898 case ISD::READCYCLECOUNTER:
2899 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2900 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2901 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2902 Node->getValueType(0))) {
2903 default: assert(0 && "This action is not supported yet!");
2904 case TargetLowering::Legal:
2905 Tmp1 = Result.getValue(0);
2906 Tmp2 = Result.getValue(1);
2908 case TargetLowering::Custom:
2909 Result = TLI.LowerOperation(Result, DAG);
2910 Tmp1 = LegalizeOp(Result.getValue(0));
2911 Tmp2 = LegalizeOp(Result.getValue(1));
2915 // Since rdcc produce two values, make sure to remember that we legalized
2917 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2918 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2922 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2923 case Expand: assert(0 && "It's impossible to expand bools");
2925 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2928 assert(!Node->getOperand(0).getValueType().isVector() && "not possible");
2929 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2930 // Make sure the condition is either zero or one.
2931 unsigned BitWidth = Tmp1.getValueSizeInBits();
2932 if (!DAG.MaskedValueIsZero(Tmp1,
2933 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2934 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2938 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2939 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2941 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2943 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2944 default: assert(0 && "This action is not supported yet!");
2945 case TargetLowering::Legal: break;
2946 case TargetLowering::Custom: {
2947 Tmp1 = TLI.LowerOperation(Result, DAG);
2948 if (Tmp1.getNode()) Result = Tmp1;
2951 case TargetLowering::Expand:
2952 if (Tmp1.getOpcode() == ISD::SETCC) {
2953 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2955 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2957 Result = DAG.getSelectCC(Tmp1,
2958 DAG.getConstant(0, Tmp1.getValueType()),
2959 Tmp2, Tmp3, ISD::SETNE);
2962 case TargetLowering::Promote: {
2964 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2965 unsigned ExtOp, TruncOp;
2966 if (Tmp2.getValueType().isVector()) {
2967 ExtOp = ISD::BIT_CONVERT;
2968 TruncOp = ISD::BIT_CONVERT;
2969 } else if (Tmp2.getValueType().isInteger()) {
2970 ExtOp = ISD::ANY_EXTEND;
2971 TruncOp = ISD::TRUNCATE;
2973 ExtOp = ISD::FP_EXTEND;
2974 TruncOp = ISD::FP_ROUND;
2976 // Promote each of the values to the new type.
2977 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2978 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2979 // Perform the larger operation, then round down.
2980 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2981 if (TruncOp != ISD::FP_ROUND)
2982 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2984 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2985 DAG.getIntPtrConstant(0));
2990 case ISD::SELECT_CC: {
2991 Tmp1 = Node->getOperand(0); // LHS
2992 Tmp2 = Node->getOperand(1); // RHS
2993 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2994 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2995 SDValue CC = Node->getOperand(4);
2997 LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC);
2999 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
3000 // the LHS is a legal SETCC itself. In this case, we need to compare
3001 // the result against zero to select between true and false values.
3002 if (Tmp2.getNode() == 0) {
3003 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3004 CC = DAG.getCondCode(ISD::SETNE);
3006 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
3008 // Everything is legal, see if we should expand this op or something.
3009 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
3010 default: assert(0 && "This action is not supported yet!");
3011 case TargetLowering::Legal: break;
3012 case TargetLowering::Custom:
3013 Tmp1 = TLI.LowerOperation(Result, DAG);
3014 if (Tmp1.getNode()) Result = Tmp1;
3020 Tmp1 = Node->getOperand(0);
3021 Tmp2 = Node->getOperand(1);
3022 Tmp3 = Node->getOperand(2);
3023 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3);
3025 // If we had to Expand the SetCC operands into a SELECT node, then it may
3026 // not always be possible to return a true LHS & RHS. In this case, just
3027 // return the value we legalized, returned in the LHS
3028 if (Tmp2.getNode() == 0) {
3033 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
3034 default: assert(0 && "Cannot handle this action for SETCC yet!");
3035 case TargetLowering::Custom:
3038 case TargetLowering::Legal:
3039 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3041 Tmp4 = TLI.LowerOperation(Result, DAG);
3042 if (Tmp4.getNode()) Result = Tmp4;
3045 case TargetLowering::Promote: {
3046 // First step, figure out the appropriate operation to use.
3047 // Allow SETCC to not be supported for all legal data types
3048 // Mostly this targets FP
3049 MVT NewInTy = Node->getOperand(0).getValueType();
3050 MVT OldVT = NewInTy; OldVT = OldVT;
3052 // Scan for the appropriate larger type to use.
3054 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
3056 assert(NewInTy.isInteger() == OldVT.isInteger() &&
3057 "Fell off of the edge of the integer world");
3058 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
3059 "Fell off of the edge of the floating point world");
3061 // If the target supports SETCC of this type, use it.
3062 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
3065 if (NewInTy.isInteger())
3066 assert(0 && "Cannot promote Legal Integer SETCC yet");
3068 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
3069 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
3071 Tmp1 = LegalizeOp(Tmp1);
3072 Tmp2 = LegalizeOp(Tmp2);
3073 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3074 Result = LegalizeOp(Result);
3077 case TargetLowering::Expand:
3078 // Expand a setcc node into a select_cc of the same condition, lhs, and
3079 // rhs that selects between const 1 (true) and const 0 (false).
3080 MVT VT = Node->getValueType(0);
3081 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
3082 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3088 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3089 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3090 SDValue CC = Node->getOperand(2);
3092 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
3094 // Everything is legal, see if we should expand this op or something.
3095 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
3096 default: assert(0 && "This action is not supported yet!");
3097 case TargetLowering::Legal: break;
3098 case TargetLowering::Custom:
3099 Tmp1 = TLI.LowerOperation(Result, DAG);
3100 if (Tmp1.getNode()) Result = Tmp1;
3102 case TargetLowering::Expand: {
3103 // Unroll into a nasty set of scalar code for now.
3104 MVT VT = Node->getValueType(0);
3105 unsigned NumElems = VT.getVectorNumElements();
3106 MVT EltVT = VT.getVectorElementType();
3107 MVT TmpEltVT = Tmp1.getValueType().getVectorElementType();
3108 SmallVector<SDValue, 8> Ops(NumElems);
3109 for (unsigned i = 0; i < NumElems; ++i) {
3110 SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
3111 Tmp1, DAG.getIntPtrConstant(i));
3112 Ops[i] = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(TmpEltVT), In1,
3113 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
3114 Tmp2, DAG.getIntPtrConstant(i)),
3116 Ops[i] = DAG.getNode(ISD::SELECT, EltVT, Ops[i],
3117 DAG.getConstant(EltVT.getIntegerVTBitMask(),EltVT),
3118 DAG.getConstant(0, EltVT));
3120 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], NumElems);
3127 case ISD::SHL_PARTS:
3128 case ISD::SRA_PARTS:
3129 case ISD::SRL_PARTS: {
3130 SmallVector<SDValue, 8> Ops;
3131 bool Changed = false;
3132 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3133 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3134 Changed |= Ops.back() != Node->getOperand(i);
3137 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
3139 switch (TLI.getOperationAction(Node->getOpcode(),
3140 Node->getValueType(0))) {
3141 default: assert(0 && "This action is not supported yet!");
3142 case TargetLowering::Legal: break;
3143 case TargetLowering::Custom:
3144 Tmp1 = TLI.LowerOperation(Result, DAG);
3145 if (Tmp1.getNode()) {
3146 SDValue Tmp2, RetVal(0, 0);
3147 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
3148 Tmp2 = LegalizeOp(Tmp1.getValue(i));
3149 AddLegalizedOperand(SDValue(Node, i), Tmp2);
3150 if (i == Op.getResNo())
3153 assert(RetVal.getNode() && "Illegal result number");
3159 // Since these produce multiple values, make sure to remember that we
3160 // legalized all of them.
3161 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3162 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
3163 return Result.getValue(Op.getResNo());
3185 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3186 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3187 case Expand: assert(0 && "Not possible");
3189 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3192 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3196 if ((Node->getOpcode() == ISD::SHL ||
3197 Node->getOpcode() == ISD::SRL ||
3198 Node->getOpcode() == ISD::SRA) &&
3199 !Node->getValueType(0).isVector()) {
3200 Tmp2 = LegalizeShiftAmount(Tmp2);
3203 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3205 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3206 default: assert(0 && "BinOp legalize operation not supported");
3207 case TargetLowering::Legal: break;
3208 case TargetLowering::Custom:
3209 Tmp1 = TLI.LowerOperation(Result, DAG);
3210 if (Tmp1.getNode()) {
3214 // Fall through if the custom lower can't deal with the operation
3215 case TargetLowering::Expand: {
3216 MVT VT = Op.getValueType();
3218 // See if multiply or divide can be lowered using two-result operations.
3219 SDVTList VTs = DAG.getVTList(VT, VT);
3220 if (Node->getOpcode() == ISD::MUL) {
3221 // We just need the low half of the multiply; try both the signed
3222 // and unsigned forms. If the target supports both SMUL_LOHI and
3223 // UMUL_LOHI, form a preference by checking which forms of plain
3224 // MULH it supports.
3225 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
3226 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
3227 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
3228 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
3229 unsigned OpToUse = 0;
3230 if (HasSMUL_LOHI && !HasMULHS) {
3231 OpToUse = ISD::SMUL_LOHI;
3232 } else if (HasUMUL_LOHI && !HasMULHU) {
3233 OpToUse = ISD::UMUL_LOHI;
3234 } else if (HasSMUL_LOHI) {
3235 OpToUse = ISD::SMUL_LOHI;
3236 } else if (HasUMUL_LOHI) {
3237 OpToUse = ISD::UMUL_LOHI;
3240 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0);
3244 if (Node->getOpcode() == ISD::MULHS &&
3245 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3246 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3250 if (Node->getOpcode() == ISD::MULHU &&
3251 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3252 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3256 if (Node->getOpcode() == ISD::SDIV &&
3257 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3258 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(),
3262 if (Node->getOpcode() == ISD::UDIV &&
3263 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3264 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(),
3269 // Check to see if we have a libcall for this operator.
3270 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3271 bool isSigned = false;
3272 switch (Node->getOpcode()) {
3275 if (VT == MVT::i32) {
3276 LC = Node->getOpcode() == ISD::UDIV
3277 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3278 isSigned = Node->getOpcode() == ISD::SDIV;
3283 LC = RTLIB::MUL_I32;
3284 else if (VT == MVT::i64)
3285 LC = RTLIB::MUL_I64;
3288 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3289 RTLIB::POW_PPCF128);
3293 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3295 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3299 assert(Node->getValueType(0).isVector() &&
3300 "Cannot expand this binary operator!");
3301 // Expand the operation into a bunch of nasty scalar code.
3302 Result = LegalizeOp(UnrollVectorOp(Op));
3305 case TargetLowering::Promote: {
3306 switch (Node->getOpcode()) {
3307 default: assert(0 && "Do not know how to promote this BinOp!");
3311 MVT OVT = Node->getValueType(0);
3312 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3313 assert(OVT.isVector() && "Cannot promote this BinOp!");
3314 // Bit convert each of the values to the new type.
3315 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3316 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3317 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3318 // Bit convert the result back the original type.
3319 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3327 case ISD::SMUL_LOHI:
3328 case ISD::UMUL_LOHI:
3331 // These nodes will only be produced by target-specific lowering, so
3332 // they shouldn't be here if they aren't legal.
3333 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3334 "This must be legal!");
3336 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3337 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3338 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3341 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3342 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3343 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3344 case Expand: assert(0 && "Not possible");
3346 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3349 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3353 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3355 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3356 default: assert(0 && "Operation not supported");
3357 case TargetLowering::Custom:
3358 Tmp1 = TLI.LowerOperation(Result, DAG);
3359 if (Tmp1.getNode()) Result = Tmp1;
3361 case TargetLowering::Legal: break;
3362 case TargetLowering::Expand: {
3363 // If this target supports fabs/fneg natively and select is cheap,
3364 // do this efficiently.
3365 if (!TLI.isSelectExpensive() &&
3366 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3367 TargetLowering::Legal &&
3368 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3369 TargetLowering::Legal) {
3370 // Get the sign bit of the RHS.
3372 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3373 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3374 SignBit = DAG.getSetCC(TLI.getSetCCResultType(IVT),
3375 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3376 // Get the absolute value of the result.
3377 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3378 // Select between the nabs and abs value based on the sign bit of
3380 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3381 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3384 Result = LegalizeOp(Result);
3388 // Otherwise, do bitwise ops!
3390 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3391 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3392 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3393 Result = LegalizeOp(Result);
3401 Tmp1 = LegalizeOp(Node->getOperand(0));
3402 Tmp2 = LegalizeOp(Node->getOperand(1));
3403 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3404 Tmp3 = Result.getValue(0);
3405 Tmp4 = Result.getValue(1);
3407 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3408 default: assert(0 && "This action is not supported yet!");
3409 case TargetLowering::Legal:
3411 case TargetLowering::Custom:
3412 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3413 if (Tmp1.getNode() != NULL) {
3414 Tmp3 = LegalizeOp(Tmp1);
3415 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3419 // Since this produces two values, make sure to remember that we legalized
3421 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3422 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3423 return Op.getResNo() ? Tmp4 : Tmp3;
3427 Tmp1 = LegalizeOp(Node->getOperand(0));
3428 Tmp2 = LegalizeOp(Node->getOperand(1));
3429 Tmp3 = LegalizeOp(Node->getOperand(2));
3430 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3431 Tmp3 = Result.getValue(0);
3432 Tmp4 = Result.getValue(1);
3434 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3435 default: assert(0 && "This action is not supported yet!");
3436 case TargetLowering::Legal:
3438 case TargetLowering::Custom:
3439 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3440 if (Tmp1.getNode() != NULL) {
3441 Tmp3 = LegalizeOp(Tmp1);
3442 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3446 // Since this produces two values, make sure to remember that we legalized
3448 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3449 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3450 return Op.getResNo() ? Tmp4 : Tmp3;
3452 case ISD::BUILD_PAIR: {
3453 MVT PairTy = Node->getValueType(0);
3454 // TODO: handle the case where the Lo and Hi operands are not of legal type
3455 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3456 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3457 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3458 case TargetLowering::Promote:
3459 case TargetLowering::Custom:
3460 assert(0 && "Cannot promote/custom this yet!");
3461 case TargetLowering::Legal:
3462 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3463 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3465 case TargetLowering::Expand:
3466 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3467 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3468 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3469 DAG.getConstant(PairTy.getSizeInBits()/2,
3470 TLI.getShiftAmountTy()));
3471 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3480 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3481 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3483 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3484 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3485 case TargetLowering::Custom:
3488 case TargetLowering::Legal:
3489 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3491 Tmp1 = TLI.LowerOperation(Result, DAG);
3492 if (Tmp1.getNode()) Result = Tmp1;
3495 case TargetLowering::Expand: {
3496 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3497 bool isSigned = DivOpc == ISD::SDIV;
3498 MVT VT = Node->getValueType(0);
3500 // See if remainder can be lowered using two-result operations.
3501 SDVTList VTs = DAG.getVTList(VT, VT);
3502 if (Node->getOpcode() == ISD::SREM &&
3503 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3504 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3507 if (Node->getOpcode() == ISD::UREM &&
3508 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3509 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3513 if (VT.isInteger()) {
3514 if (TLI.getOperationAction(DivOpc, VT) ==
3515 TargetLowering::Legal) {
3517 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3518 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3519 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3520 } else if (VT.isVector()) {
3521 Result = LegalizeOp(UnrollVectorOp(Op));
3523 assert(VT == MVT::i32 &&
3524 "Cannot expand this binary operator!");
3525 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3526 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3528 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3531 assert(VT.isFloatingPoint() &&
3532 "remainder op must have integer or floating-point type");
3533 if (VT.isVector()) {
3534 Result = LegalizeOp(UnrollVectorOp(Op));
3536 // Floating point mod -> fmod libcall.
3537 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3538 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3540 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3548 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3549 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3551 MVT VT = Node->getValueType(0);
3552 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3553 default: assert(0 && "This action is not supported yet!");
3554 case TargetLowering::Custom:
3557 case TargetLowering::Legal:
3558 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3559 Result = Result.getValue(0);
3560 Tmp1 = Result.getValue(1);
3563 Tmp2 = TLI.LowerOperation(Result, DAG);
3564 if (Tmp2.getNode()) {
3565 Result = LegalizeOp(Tmp2);
3566 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3570 case TargetLowering::Expand: {
3571 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3572 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3573 // Increment the pointer, VAList, to the next vaarg
3574 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3575 DAG.getConstant(TLI.getTargetData()->
3576 getTypePaddedSize(VT.getTypeForMVT()),
3577 TLI.getPointerTy()));
3578 // Store the incremented VAList to the legalized pointer
3579 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3580 // Load the actual argument out of the pointer VAList
3581 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3582 Tmp1 = LegalizeOp(Result.getValue(1));
3583 Result = LegalizeOp(Result);
3587 // Since VAARG produces two values, make sure to remember that we
3588 // legalized both of them.
3589 AddLegalizedOperand(SDValue(Node, 0), Result);
3590 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3591 return Op.getResNo() ? Tmp1 : Result;
3595 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3596 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3597 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3599 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3600 default: assert(0 && "This action is not supported yet!");
3601 case TargetLowering::Custom:
3604 case TargetLowering::Legal:
3605 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3606 Node->getOperand(3), Node->getOperand(4));
3608 Tmp1 = TLI.LowerOperation(Result, DAG);
3609 if (Tmp1.getNode()) Result = Tmp1;
3612 case TargetLowering::Expand:
3613 // This defaults to loading a pointer from the input and storing it to the
3614 // output, returning the chain.
3615 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3616 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3617 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3618 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3624 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3625 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3627 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3628 default: assert(0 && "This action is not supported yet!");
3629 case TargetLowering::Custom:
3632 case TargetLowering::Legal:
3633 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3635 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3636 if (Tmp1.getNode()) Result = Tmp1;
3639 case TargetLowering::Expand:
3640 Result = Tmp1; // Default to a no-op, return the chain
3646 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3647 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3649 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3651 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3652 default: assert(0 && "This action is not supported yet!");
3653 case TargetLowering::Legal: break;
3654 case TargetLowering::Custom:
3655 Tmp1 = TLI.LowerOperation(Result, DAG);
3656 if (Tmp1.getNode()) Result = Tmp1;
3663 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3664 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3665 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3666 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3668 assert(0 && "ROTL/ROTR legalize operation not supported");
3670 case TargetLowering::Legal:
3672 case TargetLowering::Custom:
3673 Tmp1 = TLI.LowerOperation(Result, DAG);
3674 if (Tmp1.getNode()) Result = Tmp1;
3676 case TargetLowering::Promote:
3677 assert(0 && "Do not know how to promote ROTL/ROTR");
3679 case TargetLowering::Expand:
3680 assert(0 && "Do not know how to expand ROTL/ROTR");
3686 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3687 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3688 case TargetLowering::Custom:
3689 assert(0 && "Cannot custom legalize this yet!");
3690 case TargetLowering::Legal:
3691 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3693 case TargetLowering::Promote: {
3694 MVT OVT = Tmp1.getValueType();
3695 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3696 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3698 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3699 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3700 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3701 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3704 case TargetLowering::Expand:
3705 Result = ExpandBSWAP(Tmp1);
3713 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3714 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3715 case TargetLowering::Custom:
3716 case TargetLowering::Legal:
3717 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3718 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3719 TargetLowering::Custom) {
3720 Tmp1 = TLI.LowerOperation(Result, DAG);
3721 if (Tmp1.getNode()) {
3726 case TargetLowering::Promote: {
3727 MVT OVT = Tmp1.getValueType();
3728 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3730 // Zero extend the argument.
3731 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3732 // Perform the larger operation, then subtract if needed.
3733 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3734 switch (Node->getOpcode()) {
3739 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3740 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
3741 DAG.getConstant(NVT.getSizeInBits(), NVT),
3743 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3744 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3747 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3748 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3749 DAG.getConstant(NVT.getSizeInBits() -
3750 OVT.getSizeInBits(), NVT));
3755 case TargetLowering::Expand:
3756 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3776 case ISD::FNEARBYINT:
3777 Tmp1 = LegalizeOp(Node->getOperand(0));
3778 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3779 case TargetLowering::Promote:
3780 case TargetLowering::Custom:
3783 case TargetLowering::Legal:
3784 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3786 Tmp1 = TLI.LowerOperation(Result, DAG);
3787 if (Tmp1.getNode()) Result = Tmp1;
3790 case TargetLowering::Expand:
3791 switch (Node->getOpcode()) {
3792 default: assert(0 && "Unreachable!");
3794 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3795 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3796 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3799 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3800 MVT VT = Node->getValueType(0);
3801 Tmp2 = DAG.getConstantFP(0.0, VT);
3802 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()),
3803 Tmp1, Tmp2, ISD::SETUGT);
3804 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3805 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3820 case ISD::FNEARBYINT: {
3821 MVT VT = Node->getValueType(0);
3823 // Expand unsupported unary vector operators by unrolling them.
3824 if (VT.isVector()) {
3825 Result = LegalizeOp(UnrollVectorOp(Op));
3829 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3830 switch(Node->getOpcode()) {
3832 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3833 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3836 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3837 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3840 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3841 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3844 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3845 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3848 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3849 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3852 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3853 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3856 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3857 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3860 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3861 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3864 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3865 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3868 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3869 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3872 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3873 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3876 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3877 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3879 case ISD::FNEARBYINT:
3880 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3881 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3884 default: assert(0 && "Unreachable!");
3887 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3895 MVT VT = Node->getValueType(0);
3897 // Expand unsupported unary vector operators by unrolling them.
3898 if (VT.isVector()) {
3899 Result = LegalizeOp(UnrollVectorOp(Op));
3903 // We always lower FPOWI into a libcall. No target support for it yet.
3904 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3905 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3907 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3910 case ISD::BIT_CONVERT:
3911 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3912 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3913 Node->getValueType(0));
3914 } else if (Op.getOperand(0).getValueType().isVector()) {
3915 // The input has to be a vector type, we have to either scalarize it, pack
3916 // it, or convert it based on whether the input vector type is legal.
3917 SDNode *InVal = Node->getOperand(0).getNode();
3918 int InIx = Node->getOperand(0).getResNo();
3919 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3920 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3922 // Figure out if there is a simple type corresponding to this Vector
3923 // type. If so, convert to the vector type.
3924 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3925 if (TLI.isTypeLegal(TVT)) {
3926 // Turn this into a bit convert of the vector input.
3927 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3928 LegalizeOp(Node->getOperand(0)));
3930 } else if (NumElems == 1) {
3931 // Turn this into a bit convert of the scalar input.
3932 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3933 ScalarizeVectorOp(Node->getOperand(0)));
3936 // FIXME: UNIMP! Store then reload
3937 assert(0 && "Cast from unsupported vector type not implemented yet!");
3940 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3941 Node->getOperand(0).getValueType())) {
3942 default: assert(0 && "Unknown operation action!");
3943 case TargetLowering::Expand:
3944 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3945 Node->getValueType(0));
3947 case TargetLowering::Legal:
3948 Tmp1 = LegalizeOp(Node->getOperand(0));
3949 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3954 case ISD::CONVERT_RNDSAT: {
3955 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
3957 default: assert(0 && "Unknown cvt code!");
3968 SDValue DTyOp = Node->getOperand(1);
3969 SDValue STyOp = Node->getOperand(2);
3970 SDValue RndOp = Node->getOperand(3);
3971 SDValue SatOp = Node->getOperand(4);
3972 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3973 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3975 Tmp1 = LegalizeOp(Node->getOperand(0));
3976 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp,
3978 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3979 TargetLowering::Custom) {
3980 Tmp1 = TLI.LowerOperation(Result, DAG);
3981 if (Tmp1.getNode()) Result = Tmp1;
3985 Result = PromoteOp(Node->getOperand(0));
3986 // For FP, make Op1 a i32
3988 Result = DAG.getConvertRndSat(Op.getValueType(), Result,
3989 DTyOp, STyOp, RndOp, SatOp, CvtCode);
3994 } // end switch CvtCode
3997 // Conversion operators. The source and destination have different types.
3998 case ISD::SINT_TO_FP:
3999 case ISD::UINT_TO_FP: {
4000 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
4001 Result = LegalizeINT_TO_FP(Result, isSigned,
4002 Node->getValueType(0), Node->getOperand(0));
4006 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4008 Tmp1 = LegalizeOp(Node->getOperand(0));
4009 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
4010 default: assert(0 && "Unknown TRUNCATE legalization operation action!");
4011 case TargetLowering::Custom:
4014 case TargetLowering::Legal:
4015 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4017 Tmp1 = TLI.LowerOperation(Result, DAG);
4018 if (Tmp1.getNode()) Result = Tmp1;
4021 case TargetLowering::Expand:
4022 assert(Result.getValueType().isVector() && "must be vector type");
4023 // Unroll the truncate. We should do better.
4024 Result = LegalizeOp(UnrollVectorOp(Result));
4028 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4030 // Since the result is legal, we should just be able to truncate the low
4031 // part of the source.
4032 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
4035 Result = PromoteOp(Node->getOperand(0));
4036 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
4041 case ISD::FP_TO_SINT:
4042 case ISD::FP_TO_UINT:
4043 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4045 Tmp1 = LegalizeOp(Node->getOperand(0));
4047 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
4048 default: assert(0 && "Unknown operation action!");
4049 case TargetLowering::Custom:
4052 case TargetLowering::Legal:
4053 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4055 Tmp1 = TLI.LowerOperation(Result, DAG);
4056 if (Tmp1.getNode()) Result = Tmp1;
4059 case TargetLowering::Promote:
4060 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
4061 Node->getOpcode() == ISD::FP_TO_SINT);
4063 case TargetLowering::Expand:
4064 if (Node->getOpcode() == ISD::FP_TO_UINT) {
4065 SDValue True, False;
4066 MVT VT = Node->getOperand(0).getValueType();
4067 MVT NVT = Node->getValueType(0);
4068 const uint64_t zero[] = {0, 0};
4069 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
4070 APInt x = APInt::getSignBit(NVT.getSizeInBits());
4071 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
4072 Tmp2 = DAG.getConstantFP(apf, VT);
4073 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(VT), Node->getOperand(0),
4075 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
4076 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
4077 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
4079 False = DAG.getNode(ISD::XOR, NVT, False,
4080 DAG.getConstant(x, NVT));
4081 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
4084 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
4090 MVT VT = Op.getValueType();
4091 MVT OVT = Node->getOperand(0).getValueType();
4092 // Convert ppcf128 to i32
4093 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
4094 if (Node->getOpcode() == ISD::FP_TO_SINT) {
4095 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
4096 Node->getOperand(0), DAG.getValueType(MVT::f64));
4097 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
4098 DAG.getIntPtrConstant(1));
4099 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
4101 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
4102 APFloat apf = APFloat(APInt(128, 2, TwoE31));
4103 Tmp2 = DAG.getConstantFP(apf, OVT);
4104 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
4105 // FIXME: generated code sucks.
4106 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
4107 DAG.getNode(ISD::ADD, MVT::i32,
4108 DAG.getNode(ISD::FP_TO_SINT, VT,
4109 DAG.getNode(ISD::FSUB, OVT,
4110 Node->getOperand(0), Tmp2)),
4111 DAG.getConstant(0x80000000, MVT::i32)),
4112 DAG.getNode(ISD::FP_TO_SINT, VT,
4113 Node->getOperand(0)),
4114 DAG.getCondCode(ISD::SETGE));
4118 // Convert f32 / f64 to i32 / i64 / i128.
4119 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
4120 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
4121 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
4123 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
4127 Tmp1 = PromoteOp(Node->getOperand(0));
4128 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
4129 Result = LegalizeOp(Result);
4134 case ISD::FP_EXTEND: {
4135 MVT DstVT = Op.getValueType();
4136 MVT SrcVT = Op.getOperand(0).getValueType();
4137 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4138 // The only other way we can lower this is to turn it into a STORE,
4139 // LOAD pair, targetting a temporary location (a stack slot).
4140 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
4143 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4144 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4146 Tmp1 = LegalizeOp(Node->getOperand(0));
4147 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4150 Tmp1 = PromoteOp(Node->getOperand(0));
4151 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
4156 case ISD::FP_ROUND: {
4157 MVT DstVT = Op.getValueType();
4158 MVT SrcVT = Op.getOperand(0).getValueType();
4159 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4160 if (SrcVT == MVT::ppcf128) {
4162 ExpandOp(Node->getOperand(0), Lo, Result);
4163 // Round it the rest of the way (e.g. to f32) if needed.
4164 if (DstVT!=MVT::f64)
4165 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
4168 // The only other way we can lower this is to turn it into a STORE,
4169 // LOAD pair, targetting a temporary location (a stack slot).
4170 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
4173 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4174 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4176 Tmp1 = LegalizeOp(Node->getOperand(0));
4177 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4180 Tmp1 = PromoteOp(Node->getOperand(0));
4181 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
4182 Node->getOperand(1));
4187 case ISD::ANY_EXTEND:
4188 case ISD::ZERO_EXTEND:
4189 case ISD::SIGN_EXTEND:
4190 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4191 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4193 Tmp1 = LegalizeOp(Node->getOperand(0));
4194 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4195 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4196 TargetLowering::Custom) {
4197 Tmp1 = TLI.LowerOperation(Result, DAG);
4198 if (Tmp1.getNode()) Result = Tmp1;
4202 switch (Node->getOpcode()) {
4203 case ISD::ANY_EXTEND:
4204 Tmp1 = PromoteOp(Node->getOperand(0));
4205 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
4207 case ISD::ZERO_EXTEND:
4208 Result = PromoteOp(Node->getOperand(0));
4209 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
4210 Result = DAG.getZeroExtendInReg(Result,
4211 Node->getOperand(0).getValueType());
4213 case ISD::SIGN_EXTEND:
4214 Result = PromoteOp(Node->getOperand(0));
4215 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
4216 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4218 DAG.getValueType(Node->getOperand(0).getValueType()));
4223 case ISD::FP_ROUND_INREG:
4224 case ISD::SIGN_EXTEND_INREG: {
4225 Tmp1 = LegalizeOp(Node->getOperand(0));
4226 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
4228 // If this operation is not supported, convert it to a shl/shr or load/store
4230 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
4231 default: assert(0 && "This action not supported for this op yet!");
4232 case TargetLowering::Legal:
4233 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4235 case TargetLowering::Expand:
4236 // If this is an integer extend and shifts are supported, do that.
4237 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
4238 // NOTE: we could fall back on load/store here too for targets without
4239 // SAR. However, it is doubtful that any exist.
4240 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
4241 ExtraVT.getSizeInBits();
4242 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
4243 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
4244 Node->getOperand(0), ShiftCst);
4245 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
4247 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
4248 // The only way we can lower this is to turn it into a TRUNCSTORE,
4249 // EXTLOAD pair, targetting a temporary location (a stack slot).
4251 // NOTE: there is a choice here between constantly creating new stack
4252 // slots and always reusing the same one. We currently always create
4253 // new ones, as reuse may inhibit scheduling.
4254 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
4255 Node->getValueType(0));
4257 assert(0 && "Unknown op");
4263 case ISD::TRAMPOLINE: {
4265 for (unsigned i = 0; i != 6; ++i)
4266 Ops[i] = LegalizeOp(Node->getOperand(i));
4267 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
4268 // The only option for this node is to custom lower it.
4269 Result = TLI.LowerOperation(Result, DAG);
4270 assert(Result.getNode() && "Should always custom lower!");
4272 // Since trampoline produces two values, make sure to remember that we
4273 // legalized both of them.
4274 Tmp1 = LegalizeOp(Result.getValue(1));
4275 Result = LegalizeOp(Result);
4276 AddLegalizedOperand(SDValue(Node, 0), Result);
4277 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
4278 return Op.getResNo() ? Tmp1 : Result;
4280 case ISD::FLT_ROUNDS_: {
4281 MVT VT = Node->getValueType(0);
4282 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4283 default: assert(0 && "This action not supported for this op yet!");
4284 case TargetLowering::Custom:
4285 Result = TLI.LowerOperation(Op, DAG);
4286 if (Result.getNode()) break;
4288 case TargetLowering::Legal:
4289 // If this operation is not supported, lower it to constant 1
4290 Result = DAG.getConstant(1, VT);
4296 MVT VT = Node->getValueType(0);
4297 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4298 default: assert(0 && "This action not supported for this op yet!");
4299 case TargetLowering::Legal:
4300 Tmp1 = LegalizeOp(Node->getOperand(0));
4301 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4303 case TargetLowering::Custom:
4304 Result = TLI.LowerOperation(Op, DAG);
4305 if (Result.getNode()) break;
4307 case TargetLowering::Expand:
4308 // If this operation is not supported, lower it to 'abort()' call
4309 Tmp1 = LegalizeOp(Node->getOperand(0));
4310 TargetLowering::ArgListTy Args;
4311 std::pair<SDValue,SDValue> CallResult =
4312 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4313 false, false, false, false, CallingConv::C, false,
4314 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4316 Result = CallResult.second;
4324 MVT VT = Node->getValueType(0);
4325 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4326 default: assert(0 && "This action not supported for this op yet!");
4327 case TargetLowering::Custom:
4328 Result = TLI.LowerOperation(Op, DAG);
4329 if (Result.getNode()) break;
4331 case TargetLowering::Legal: {
4332 SDValue LHS = LegalizeOp(Node->getOperand(0));
4333 SDValue RHS = LegalizeOp(Node->getOperand(1));
4335 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
4336 ISD::ADD : ISD::SUB, LHS.getValueType(),
4338 MVT OType = Node->getValueType(1);
4340 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
4342 // LHSSign -> LHS >= 0
4343 // RHSSign -> RHS >= 0
4344 // SumSign -> Sum >= 0
4347 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4349 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
4351 SDValue LHSSign = DAG.getSetCC(OType, LHS, Zero, ISD::SETGE);
4352 SDValue RHSSign = DAG.getSetCC(OType, RHS, Zero, ISD::SETGE);
4353 SDValue SignsMatch = DAG.getSetCC(OType, LHSSign, RHSSign,
4354 Node->getOpcode() == ISD::SADDO ?
4355 ISD::SETEQ : ISD::SETNE);
4357 SDValue SumSign = DAG.getSetCC(OType, Sum, Zero, ISD::SETGE);
4358 SDValue SumSignNE = DAG.getSetCC(OType, LHSSign, SumSign, ISD::SETNE);
4360 SDValue Cmp = DAG.getNode(ISD::AND, OType, SignsMatch, SumSignNE);
4362 MVT ValueVTs[] = { LHS.getValueType(), OType };
4363 SDValue Ops[] = { Sum, Cmp };
4365 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2),
4367 SDNode *RNode = Result.getNode();
4368 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4369 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4378 MVT VT = Node->getValueType(0);
4379 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4380 default: assert(0 && "This action not supported for this op yet!");
4381 case TargetLowering::Custom:
4382 Result = TLI.LowerOperation(Op, DAG);
4383 if (Result.getNode()) break;
4385 case TargetLowering::Legal: {
4386 SDValue LHS = LegalizeOp(Node->getOperand(0));
4387 SDValue RHS = LegalizeOp(Node->getOperand(1));
4389 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
4390 ISD::ADD : ISD::SUB, LHS.getValueType(),
4392 MVT OType = Node->getValueType(1);
4393 SDValue Cmp = DAG.getSetCC(OType, Sum, LHS,
4394 Node->getOpcode () == ISD::UADDO ?
4395 ISD::SETULT : ISD::SETUGT);
4397 MVT ValueVTs[] = { LHS.getValueType(), OType };
4398 SDValue Ops[] = { Sum, Cmp };
4400 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2),
4402 SDNode *RNode = Result.getNode();
4403 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4404 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4413 MVT VT = Node->getValueType(0);
4414 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4415 default: assert(0 && "This action is not supported at all!");
4416 case TargetLowering::Custom:
4417 Result = TLI.LowerOperation(Op, DAG);
4418 if (Result.getNode()) break;
4420 case TargetLowering::Legal:
4421 // FIXME: According to Hacker's Delight, this can be implemented in
4422 // target independent lowering, but it would be inefficient, since it
4423 // requires a division + a branch.
4424 assert(0 && "Target independent lowering is not supported for SMULO/UMULO!");
4432 assert(Result.getValueType() == Op.getValueType() &&
4433 "Bad legalization!");
4435 // Make sure that the generated code is itself legal.
4437 Result = LegalizeOp(Result);
4439 // Note that LegalizeOp may be reentered even from single-use nodes, which
4440 // means that we always must cache transformed nodes.
4441 AddLegalizedOperand(Op, Result);
4445 /// PromoteOp - Given an operation that produces a value in an invalid type,
4446 /// promote it to compute the value into a larger type. The produced value will
4447 /// have the correct bits for the low portion of the register, but no guarantee
4448 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4449 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4450 MVT VT = Op.getValueType();
4451 MVT NVT = TLI.getTypeToTransformTo(VT);
4452 assert(getTypeAction(VT) == Promote &&
4453 "Caller should expand or legalize operands that are not promotable!");
4454 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4455 "Cannot promote to smaller type!");
4457 SDValue Tmp1, Tmp2, Tmp3;
4459 SDNode *Node = Op.getNode();
4461 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4462 if (I != PromotedNodes.end()) return I->second;
4464 switch (Node->getOpcode()) {
4465 case ISD::CopyFromReg:
4466 assert(0 && "CopyFromReg must be legal!");
4469 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4471 assert(0 && "Do not know how to promote this operator!");
4474 Result = DAG.getNode(ISD::UNDEF, NVT);
4478 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4480 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4481 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4483 case ISD::ConstantFP:
4484 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4485 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4489 MVT VT0 = Node->getOperand(0).getValueType();
4490 assert(isTypeLegal(TLI.getSetCCResultType(VT0))
4491 && "SetCC type is not legal??");
4492 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(VT0),
4493 Node->getOperand(0), Node->getOperand(1),
4494 Node->getOperand(2));
4498 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4500 Result = LegalizeOp(Node->getOperand(0));
4501 assert(Result.getValueType().bitsGE(NVT) &&
4502 "This truncation doesn't make sense!");
4503 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4504 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4507 // The truncation is not required, because we don't guarantee anything
4508 // about high bits anyway.
4509 Result = PromoteOp(Node->getOperand(0));
4512 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4513 // Truncate the low part of the expanded value to the result type
4514 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4517 case ISD::SIGN_EXTEND:
4518 case ISD::ZERO_EXTEND:
4519 case ISD::ANY_EXTEND:
4520 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4521 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4523 // Input is legal? Just do extend all the way to the larger type.
4524 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4527 // Promote the reg if it's smaller.
4528 Result = PromoteOp(Node->getOperand(0));
4529 // The high bits are not guaranteed to be anything. Insert an extend.
4530 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4531 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4532 DAG.getValueType(Node->getOperand(0).getValueType()));
4533 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4534 Result = DAG.getZeroExtendInReg(Result,
4535 Node->getOperand(0).getValueType());
4539 case ISD::CONVERT_RNDSAT: {
4540 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4541 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
4542 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
4543 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
4544 "can only promote integers");
4545 Result = DAG.getConvertRndSat(NVT, Node->getOperand(0),
4546 Node->getOperand(1), Node->getOperand(2),
4547 Node->getOperand(3), Node->getOperand(4),
4552 case ISD::BIT_CONVERT:
4553 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4554 Node->getValueType(0));
4555 Result = PromoteOp(Result);
4558 case ISD::FP_EXTEND:
4559 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4561 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4562 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4563 case Promote: assert(0 && "Unreachable with 2 FP types!");
4565 if (Node->getConstantOperandVal(1) == 0) {
4566 // Input is legal? Do an FP_ROUND_INREG.
4567 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4568 DAG.getValueType(VT));
4570 // Just remove the truncate, it isn't affecting the value.
4571 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4572 Node->getOperand(1));
4577 case ISD::SINT_TO_FP:
4578 case ISD::UINT_TO_FP:
4579 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4581 // No extra round required here.
4582 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4586 Result = PromoteOp(Node->getOperand(0));
4587 if (Node->getOpcode() == ISD::SINT_TO_FP)
4588 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4590 DAG.getValueType(Node->getOperand(0).getValueType()));
4592 Result = DAG.getZeroExtendInReg(Result,
4593 Node->getOperand(0).getValueType());
4594 // No extra round required here.
4595 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4598 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4599 Node->getOperand(0));
4600 // Round if we cannot tolerate excess precision.
4601 if (NoExcessFPPrecision)
4602 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4603 DAG.getValueType(VT));
4608 case ISD::SIGN_EXTEND_INREG:
4609 Result = PromoteOp(Node->getOperand(0));
4610 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4611 Node->getOperand(1));
4613 case ISD::FP_TO_SINT:
4614 case ISD::FP_TO_UINT:
4615 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4618 Tmp1 = Node->getOperand(0);
4621 // The input result is prerounded, so we don't have to do anything
4623 Tmp1 = PromoteOp(Node->getOperand(0));
4626 // If we're promoting a UINT to a larger size, check to see if the new node
4627 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4628 // we can use that instead. This allows us to generate better code for
4629 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4630 // legal, such as PowerPC.
4631 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4632 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4633 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4634 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4635 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4637 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4643 Tmp1 = PromoteOp(Node->getOperand(0));
4644 assert(Tmp1.getValueType() == NVT);
4645 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4646 // NOTE: we do not have to do any extra rounding here for
4647 // NoExcessFPPrecision, because we know the input will have the appropriate
4648 // precision, and these operations don't modify precision at all.
4663 case ISD::FNEARBYINT:
4664 Tmp1 = PromoteOp(Node->getOperand(0));
4665 assert(Tmp1.getValueType() == NVT);
4666 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4667 if (NoExcessFPPrecision)
4668 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4669 DAG.getValueType(VT));
4674 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4675 // directly as well, which may be better.
4676 Tmp1 = PromoteOp(Node->getOperand(0));
4677 Tmp2 = Node->getOperand(1);
4678 if (Node->getOpcode() == ISD::FPOW)
4679 Tmp2 = PromoteOp(Tmp2);
4680 assert(Tmp1.getValueType() == NVT);
4681 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4682 if (NoExcessFPPrecision)
4683 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4684 DAG.getValueType(VT));
4688 case ISD::ATOMIC_CMP_SWAP: {
4689 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4690 Tmp2 = PromoteOp(Node->getOperand(2));
4691 Tmp3 = PromoteOp(Node->getOperand(3));
4692 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getMemoryVT(),
4693 AtomNode->getChain(),
4694 AtomNode->getBasePtr(), Tmp2, Tmp3,
4695 AtomNode->getSrcValue(),
4696 AtomNode->getAlignment());
4697 // Remember that we legalized the chain.
4698 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4701 case ISD::ATOMIC_LOAD_ADD:
4702 case ISD::ATOMIC_LOAD_SUB:
4703 case ISD::ATOMIC_LOAD_AND:
4704 case ISD::ATOMIC_LOAD_OR:
4705 case ISD::ATOMIC_LOAD_XOR:
4706 case ISD::ATOMIC_LOAD_NAND:
4707 case ISD::ATOMIC_LOAD_MIN:
4708 case ISD::ATOMIC_LOAD_MAX:
4709 case ISD::ATOMIC_LOAD_UMIN:
4710 case ISD::ATOMIC_LOAD_UMAX:
4711 case ISD::ATOMIC_SWAP: {
4712 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4713 Tmp2 = PromoteOp(Node->getOperand(2));
4714 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getMemoryVT(),
4715 AtomNode->getChain(),
4716 AtomNode->getBasePtr(), Tmp2,
4717 AtomNode->getSrcValue(),
4718 AtomNode->getAlignment());
4719 // Remember that we legalized the chain.
4720 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4730 // The input may have strange things in the top bits of the registers, but
4731 // these operations don't care. They may have weird bits going out, but
4732 // that too is okay if they are integer operations.
4733 Tmp1 = PromoteOp(Node->getOperand(0));
4734 Tmp2 = PromoteOp(Node->getOperand(1));
4735 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4736 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4741 Tmp1 = PromoteOp(Node->getOperand(0));
4742 Tmp2 = PromoteOp(Node->getOperand(1));
4743 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4744 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4746 // Floating point operations will give excess precision that we may not be
4747 // able to tolerate. If we DO allow excess precision, just leave it,
4748 // otherwise excise it.
4749 // FIXME: Why would we need to round FP ops more than integer ones?
4750 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4751 if (NoExcessFPPrecision)
4752 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4753 DAG.getValueType(VT));
4758 // These operators require that their input be sign extended.
4759 Tmp1 = PromoteOp(Node->getOperand(0));
4760 Tmp2 = PromoteOp(Node->getOperand(1));
4761 if (NVT.isInteger()) {
4762 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4763 DAG.getValueType(VT));
4764 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4765 DAG.getValueType(VT));
4767 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4769 // Perform FP_ROUND: this is probably overly pessimistic.
4770 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4771 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4772 DAG.getValueType(VT));
4776 case ISD::FCOPYSIGN:
4777 // These operators require that their input be fp extended.
4778 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4779 case Expand: assert(0 && "not implemented");
4780 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4781 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4783 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4784 case Expand: assert(0 && "not implemented");
4785 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4786 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4788 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4790 // Perform FP_ROUND: this is probably overly pessimistic.
4791 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4792 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4793 DAG.getValueType(VT));
4798 // These operators require that their input be zero extended.
4799 Tmp1 = PromoteOp(Node->getOperand(0));
4800 Tmp2 = PromoteOp(Node->getOperand(1));
4801 assert(NVT.isInteger() && "Operators don't apply to FP!");
4802 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4803 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4804 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4808 Tmp1 = PromoteOp(Node->getOperand(0));
4809 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4812 // The input value must be properly sign extended.
4813 Tmp1 = PromoteOp(Node->getOperand(0));
4814 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4815 DAG.getValueType(VT));
4816 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4819 // The input value must be properly zero extended.
4820 Tmp1 = PromoteOp(Node->getOperand(0));
4821 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4822 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4826 Tmp1 = Node->getOperand(0); // Get the chain.
4827 Tmp2 = Node->getOperand(1); // Get the pointer.
4828 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4829 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4830 Result = TLI.LowerOperation(Tmp3, DAG);
4832 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4833 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4834 // Increment the pointer, VAList, to the next vaarg
4835 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4836 DAG.getConstant(VT.getSizeInBits()/8,
4837 TLI.getPointerTy()));
4838 // Store the incremented VAList to the legalized pointer
4839 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4840 // Load the actual argument out of the pointer VAList
4841 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4843 // Remember that we legalized the chain.
4844 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4848 LoadSDNode *LD = cast<LoadSDNode>(Node);
4849 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4850 ? ISD::EXTLOAD : LD->getExtensionType();
4851 Result = DAG.getExtLoad(ExtType, NVT,
4852 LD->getChain(), LD->getBasePtr(),
4853 LD->getSrcValue(), LD->getSrcValueOffset(),
4856 LD->getAlignment());
4857 // Remember that we legalized the chain.
4858 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4862 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4863 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4865 MVT VT2 = Tmp2.getValueType();
4866 assert(VT2 == Tmp3.getValueType()
4867 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4868 // Ensure that the resulting node is at least the same size as the operands'
4869 // value types, because we cannot assume that TLI.getSetCCValueType() is
4871 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4874 case ISD::SELECT_CC:
4875 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4876 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4877 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4878 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4881 Tmp1 = Node->getOperand(0);
4882 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4883 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4884 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4885 DAG.getConstant(NVT.getSizeInBits() -
4887 TLI.getShiftAmountTy()));
4892 // Zero extend the argument
4893 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4894 // Perform the larger operation, then subtract if needed.
4895 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4896 switch(Node->getOpcode()) {
4901 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4902 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
4903 DAG.getConstant(NVT.getSizeInBits(), NVT),
4905 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4906 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4909 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4910 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4911 DAG.getConstant(NVT.getSizeInBits() -
4912 VT.getSizeInBits(), NVT));
4916 case ISD::EXTRACT_SUBVECTOR:
4917 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4919 case ISD::EXTRACT_VECTOR_ELT:
4920 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4924 assert(Result.getNode() && "Didn't set a result!");
4926 // Make sure the result is itself legal.
4927 Result = LegalizeOp(Result);
4929 // Remember that we promoted this!
4930 AddPromotedOperand(Op, Result);
4934 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4935 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4936 /// based on the vector type. The return type of this matches the element type
4937 /// of the vector, which may not be legal for the target.
4938 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
4939 // We know that operand #0 is the Vec vector. If the index is a constant
4940 // or if the invec is a supported hardware type, we can use it. Otherwise,
4941 // lower to a store then an indexed load.
4942 SDValue Vec = Op.getOperand(0);
4943 SDValue Idx = Op.getOperand(1);
4945 MVT TVT = Vec.getValueType();
4946 unsigned NumElems = TVT.getVectorNumElements();
4948 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4949 default: assert(0 && "This action is not supported yet!");
4950 case TargetLowering::Custom: {
4951 Vec = LegalizeOp(Vec);
4952 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4953 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
4958 case TargetLowering::Legal:
4959 if (isTypeLegal(TVT)) {
4960 Vec = LegalizeOp(Vec);
4961 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4965 case TargetLowering::Promote:
4966 assert(TVT.isVector() && "not vector type");
4967 // fall thru to expand since vectors are by default are promote
4968 case TargetLowering::Expand:
4972 if (NumElems == 1) {
4973 // This must be an access of the only element. Return it.
4974 Op = ScalarizeVectorOp(Vec);
4975 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4976 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4977 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4979 SplitVectorOp(Vec, Lo, Hi);
4980 if (CIdx->getZExtValue() < NumLoElts) {
4984 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
4985 Idx.getValueType());
4988 // It's now an extract from the appropriate high or low part. Recurse.
4989 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4990 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4992 // Store the value to a temporary stack slot, then LOAD the scalar
4993 // element back out.
4994 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4995 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4997 // Add the offset to the index.
4998 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
4999 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
5000 DAG.getConstant(EltSize, Idx.getValueType()));
5002 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
5003 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
5005 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
5007 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
5009 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
5014 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
5015 /// we assume the operation can be split if it is not already legal.
5016 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
5017 // We know that operand #0 is the Vec vector. For now we assume the index
5018 // is a constant and that the extracted result is a supported hardware type.
5019 SDValue Vec = Op.getOperand(0);
5020 SDValue Idx = LegalizeOp(Op.getOperand(1));
5022 unsigned NumElems = Vec.getValueType().getVectorNumElements();
5024 if (NumElems == Op.getValueType().getVectorNumElements()) {
5025 // This must be an access of the desired vector length. Return it.
5029 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5031 SplitVectorOp(Vec, Lo, Hi);
5032 if (CIdx->getZExtValue() < NumElems/2) {
5036 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
5037 Idx.getValueType());
5040 // It's now an extract from the appropriate high or low part. Recurse.
5041 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5042 return ExpandEXTRACT_SUBVECTOR(Op);
5045 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
5046 /// with condition CC on the current target. This usually involves legalizing
5047 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
5048 /// there may be no choice but to create a new SetCC node to represent the
5049 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
5050 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
5051 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
5054 SDValue Tmp1, Tmp2, Tmp3, Result;
5056 switch (getTypeAction(LHS.getValueType())) {
5058 Tmp1 = LegalizeOp(LHS); // LHS
5059 Tmp2 = LegalizeOp(RHS); // RHS
5062 Tmp1 = PromoteOp(LHS); // LHS
5063 Tmp2 = PromoteOp(RHS); // RHS
5065 // If this is an FP compare, the operands have already been extended.
5066 if (LHS.getValueType().isInteger()) {
5067 MVT VT = LHS.getValueType();
5068 MVT NVT = TLI.getTypeToTransformTo(VT);
5070 // Otherwise, we have to insert explicit sign or zero extends. Note
5071 // that we could insert sign extends for ALL conditions, but zero extend
5072 // is cheaper on many machines (an AND instead of two shifts), so prefer
5074 switch (cast<CondCodeSDNode>(CC)->get()) {
5075 default: assert(0 && "Unknown integer comparison!");
5082 // ALL of these operations will work if we either sign or zero extend
5083 // the operands (including the unsigned comparisons!). Zero extend is
5084 // usually a simpler/cheaper operation, so prefer it.
5085 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
5086 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
5092 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
5093 DAG.getValueType(VT));
5094 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
5095 DAG.getValueType(VT));
5096 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
5097 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
5103 MVT VT = LHS.getValueType();
5104 if (VT == MVT::f32 || VT == MVT::f64) {
5105 // Expand into one or more soft-fp libcall(s).
5106 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
5107 switch (cast<CondCodeSDNode>(CC)->get()) {
5110 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5114 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
5118 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5122 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5126 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5130 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5133 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5136 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
5139 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5140 switch (cast<CondCodeSDNode>(CC)->get()) {
5142 // SETONE = SETOLT | SETOGT
5143 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5146 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5149 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5152 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5155 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5158 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5160 default: assert(0 && "Unsupported FP setcc!");
5165 SDValue Ops[2] = { LHS, RHS };
5166 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(),
5167 false /*sign irrelevant*/, Dummy);
5168 Tmp2 = DAG.getConstant(0, MVT::i32);
5169 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
5170 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
5171 Tmp1 = DAG.getNode(ISD::SETCC,
5172 TLI.getSetCCResultType(Tmp1.getValueType()),
5174 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(),
5175 false /*sign irrelevant*/, Dummy);
5176 Tmp2 = DAG.getNode(ISD::SETCC,
5177 TLI.getSetCCResultType(LHS.getValueType()), LHS,
5178 Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
5179 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
5182 LHS = LegalizeOp(Tmp1);
5187 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5188 ExpandOp(LHS, LHSLo, LHSHi);
5189 ExpandOp(RHS, RHSLo, RHSHi);
5190 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5192 if (VT==MVT::ppcf128) {
5193 // FIXME: This generated code sucks. We want to generate
5194 // FCMPU crN, hi1, hi2
5196 // FCMPU crN, lo1, lo2
5197 // The following can be improved, but not that much.
5198 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5199 LHSHi, RHSHi, ISD::SETOEQ);
5200 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
5201 LHSLo, RHSLo, CCCode);
5202 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
5203 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5204 LHSHi, RHSHi, ISD::SETUNE);
5205 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5206 LHSHi, RHSHi, CCCode);
5207 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
5208 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
5217 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
5218 if (RHSCST->isAllOnesValue()) {
5219 // Comparison to -1.
5220 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
5225 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
5226 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
5227 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
5228 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
5231 // If this is a comparison of the sign bit, just look at the top part.
5233 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
5234 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
5235 CST->isNullValue()) || // X < 0
5236 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
5237 CST->isAllOnesValue())) { // X > -1
5243 // FIXME: This generated code sucks.
5244 ISD::CondCode LowCC;
5246 default: assert(0 && "Unknown integer setcc!");
5248 case ISD::SETULT: LowCC = ISD::SETULT; break;
5250 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5252 case ISD::SETULE: LowCC = ISD::SETULE; break;
5254 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5257 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
5258 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
5259 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
5261 // NOTE: on targets without efficient SELECT of bools, we can always use
5262 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5263 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
5264 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
5265 LHSLo, RHSLo, LowCC, false, DagCombineInfo);
5266 if (!Tmp1.getNode())
5267 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
5268 LHSLo, RHSLo, LowCC);
5269 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5270 LHSHi, RHSHi, CCCode, false, DagCombineInfo);
5271 if (!Tmp2.getNode())
5272 Tmp2 = DAG.getNode(ISD::SETCC,
5273 TLI.getSetCCResultType(LHSHi.getValueType()),
5276 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
5277 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
5278 if ((Tmp1C && Tmp1C->isNullValue()) ||
5279 (Tmp2C && Tmp2C->isNullValue() &&
5280 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
5281 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
5282 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
5283 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
5284 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
5285 // low part is known false, returns high part.
5286 // For LE / GE, if high part is known false, ignore the low part.
5287 // For LT / GT, if high part is known true, ignore the low part.
5291 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5292 LHSHi, RHSHi, ISD::SETEQ, false,
5294 if (!Result.getNode())
5295 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5296 LHSHi, RHSHi, ISD::SETEQ);
5297 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
5298 Result, Tmp1, Tmp2));
5309 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
5310 /// condition code CC on the current target. This routine assumes LHS and rHS
5311 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
5312 /// illegal condition code into AND / OR of multiple SETCC values.
5313 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
5314 SDValue &LHS, SDValue &RHS,
5316 MVT OpVT = LHS.getValueType();
5317 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5318 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
5319 default: assert(0 && "Unknown condition code action!");
5320 case TargetLowering::Legal:
5323 case TargetLowering::Expand: {
5324 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
5327 default: assert(0 && "Don't know how to expand this condition!"); abort();
5328 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
5329 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5330 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5331 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5332 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5333 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5334 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5335 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5336 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5337 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5338 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5339 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5340 // FIXME: Implement more expansions.
5343 SDValue SetCC1 = DAG.getSetCC(VT, LHS, RHS, CC1);
5344 SDValue SetCC2 = DAG.getSetCC(VT, LHS, RHS, CC2);
5345 LHS = DAG.getNode(Opc, VT, SetCC1, SetCC2);
5353 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
5354 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
5355 /// a load from the stack slot to DestVT, extending it if needed.
5356 /// The resultant code need not be legal.
5357 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
5360 // Create the stack frame object.
5361 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
5362 SrcOp.getValueType().getTypeForMVT());
5363 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
5365 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
5366 int SPFI = StackPtrFI->getIndex();
5368 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
5369 unsigned SlotSize = SlotVT.getSizeInBits();
5370 unsigned DestSize = DestVT.getSizeInBits();
5371 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
5372 DestVT.getTypeForMVT());
5374 // Emit a store to the stack slot. Use a truncstore if the input value is
5375 // later than DestVT.
5378 if (SrcSize > SlotSize)
5379 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
5380 PseudoSourceValue::getFixedStack(SPFI), 0,
5381 SlotVT, false, SrcAlign);
5383 assert(SrcSize == SlotSize && "Invalid store");
5384 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
5385 PseudoSourceValue::getFixedStack(SPFI), 0,
5389 // Result is a load from the stack slot.
5390 if (SlotSize == DestSize)
5391 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
5393 assert(SlotSize < DestSize && "Unknown extension!");
5394 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
5398 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
5399 // Create a vector sized/aligned stack slot, store the value to element #0,
5400 // then load the whole vector back out.
5401 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
5403 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
5404 int SPFI = StackPtrFI->getIndex();
5406 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
5407 PseudoSourceValue::getFixedStack(SPFI), 0);
5408 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
5409 PseudoSourceValue::getFixedStack(SPFI), 0);
5413 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
5414 /// support the operation, but do support the resultant vector type.
5415 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
5417 // If the only non-undef value is the low element, turn this into a
5418 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
5419 unsigned NumElems = Node->getNumOperands();
5420 bool isOnlyLowElement = true;
5421 SDValue SplatValue = Node->getOperand(0);
5423 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
5424 // and use a bitmask instead of a list of elements.
5425 std::map<SDValue, std::vector<unsigned> > Values;
5426 Values[SplatValue].push_back(0);
5427 bool isConstant = true;
5428 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
5429 SplatValue.getOpcode() != ISD::UNDEF)
5432 for (unsigned i = 1; i < NumElems; ++i) {
5433 SDValue V = Node->getOperand(i);
5434 Values[V].push_back(i);
5435 if (V.getOpcode() != ISD::UNDEF)
5436 isOnlyLowElement = false;
5437 if (SplatValue != V)
5438 SplatValue = SDValue(0,0);
5440 // If this isn't a constant element or an undef, we can't use a constant
5442 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
5443 V.getOpcode() != ISD::UNDEF)
5447 if (isOnlyLowElement) {
5448 // If the low element is an undef too, then this whole things is an undef.
5449 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
5450 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
5451 // Otherwise, turn this into a scalar_to_vector node.
5452 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
5453 Node->getOperand(0));
5456 // If all elements are constants, create a load from the constant pool.
5458 MVT VT = Node->getValueType(0);
5459 std::vector<Constant*> CV;
5460 for (unsigned i = 0, e = NumElems; i != e; ++i) {
5461 if (ConstantFPSDNode *V =
5462 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
5463 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
5464 } else if (ConstantSDNode *V =
5465 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
5466 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
5468 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
5470 Node->getOperand(0).getValueType().getTypeForMVT();
5471 CV.push_back(UndefValue::get(OpNTy));
5474 Constant *CP = ConstantVector::get(CV);
5475 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5476 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5477 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
5478 PseudoSourceValue::getConstantPool(), 0,
5482 if (SplatValue.getNode()) { // Splat of one value?
5483 // Build the shuffle constant vector: <0, 0, 0, 0>
5484 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5485 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5486 std::vector<SDValue> ZeroVec(NumElems, Zero);
5487 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5488 &ZeroVec[0], ZeroVec.size());
5490 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5491 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5492 // Get the splatted value into the low element of a vector register.
5494 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
5496 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5497 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
5498 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
5503 // If there are only two unique elements, we may be able to turn this into a
5505 if (Values.size() == 2) {
5506 // Get the two values in deterministic order.
5507 SDValue Val1 = Node->getOperand(1);
5509 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5510 if (MI->first != Val1)
5513 Val2 = (++MI)->first;
5515 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5516 // vector shuffle has the undef vector on the RHS.
5517 if (Val1.getOpcode() == ISD::UNDEF)
5518 std::swap(Val1, Val2);
5520 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5521 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5522 MVT MaskEltVT = MaskVT.getVectorElementType();
5523 std::vector<SDValue> MaskVec(NumElems);
5525 // Set elements of the shuffle mask for Val1.
5526 std::vector<unsigned> &Val1Elts = Values[Val1];
5527 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5528 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5530 // Set elements of the shuffle mask for Val2.
5531 std::vector<unsigned> &Val2Elts = Values[Val2];
5532 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5533 if (Val2.getOpcode() != ISD::UNDEF)
5534 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5536 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
5538 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5539 &MaskVec[0], MaskVec.size());
5541 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5542 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5543 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5544 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
5545 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
5546 SDValue Ops[] = { Val1, Val2, ShuffleMask };
5548 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5549 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5553 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5554 // aligned object on the stack, store each element into it, then load
5555 // the result as a vector.
5556 MVT VT = Node->getValueType(0);
5557 // Create the stack frame object.
5558 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5560 // Emit a store of each element to the stack slot.
5561 SmallVector<SDValue, 8> Stores;
5562 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5563 // Store (in the right endianness) the elements to memory.
5564 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5565 // Ignore undef elements.
5566 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5568 unsigned Offset = TypeByteSize*i;
5570 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5571 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5573 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5578 if (!Stores.empty()) // Not all undef elements?
5579 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5580 &Stores[0], Stores.size());
5582 StoreChain = DAG.getEntryNode();
5584 // Result is a load from the stack slot.
5585 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5588 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5589 SDValue Op, SDValue Amt,
5590 SDValue &Lo, SDValue &Hi) {
5591 // Expand the subcomponents.
5593 ExpandOp(Op, LHSL, LHSH);
5595 SDValue Ops[] = { LHSL, LHSH, Amt };
5596 MVT VT = LHSL.getValueType();
5597 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5598 Hi = Lo.getValue(1);
5602 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5603 /// smaller elements. If we can't find a way that is more efficient than a
5604 /// libcall on this target, return false. Otherwise, return true with the
5605 /// low-parts expanded into Lo and Hi.
5606 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5607 SDValue &Lo, SDValue &Hi) {
5608 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5609 "This is not a shift!");
5611 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5612 SDValue ShAmt = LegalizeOp(Amt);
5613 MVT ShTy = ShAmt.getValueType();
5614 unsigned ShBits = ShTy.getSizeInBits();
5615 unsigned VTBits = Op.getValueType().getSizeInBits();
5616 unsigned NVTBits = NVT.getSizeInBits();
5618 // Handle the case when Amt is an immediate.
5619 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5620 unsigned Cst = CN->getZExtValue();
5621 // Expand the incoming operand to be shifted, so that we have its parts
5623 ExpandOp(Op, InL, InH);
5627 Lo = DAG.getConstant(0, NVT);
5628 Hi = DAG.getConstant(0, NVT);
5629 } else if (Cst > NVTBits) {
5630 Lo = DAG.getConstant(0, NVT);
5631 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5632 } else if (Cst == NVTBits) {
5633 Lo = DAG.getConstant(0, NVT);
5636 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5637 Hi = DAG.getNode(ISD::OR, NVT,
5638 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5639 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5644 Lo = DAG.getConstant(0, NVT);
5645 Hi = DAG.getConstant(0, NVT);
5646 } else if (Cst > NVTBits) {
5647 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5648 Hi = DAG.getConstant(0, NVT);
5649 } else if (Cst == NVTBits) {
5651 Hi = DAG.getConstant(0, NVT);
5653 Lo = DAG.getNode(ISD::OR, NVT,
5654 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5655 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5656 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5661 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5662 DAG.getConstant(NVTBits-1, ShTy));
5663 } else if (Cst > NVTBits) {
5664 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5665 DAG.getConstant(Cst-NVTBits, ShTy));
5666 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5667 DAG.getConstant(NVTBits-1, ShTy));
5668 } else if (Cst == NVTBits) {
5670 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5671 DAG.getConstant(NVTBits-1, ShTy));
5673 Lo = DAG.getNode(ISD::OR, NVT,
5674 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5675 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5676 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5682 // Okay, the shift amount isn't constant. However, if we can tell that it is
5683 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5684 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5685 APInt KnownZero, KnownOne;
5686 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5688 // If we know that if any of the high bits of the shift amount are one, then
5689 // we can do this as a couple of simple shifts.
5690 if (KnownOne.intersects(Mask)) {
5691 // Mask out the high bit, which we know is set.
5692 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5693 DAG.getConstant(~Mask, Amt.getValueType()));
5695 // Expand the incoming operand to be shifted, so that we have its parts
5697 ExpandOp(Op, InL, InH);
5700 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5701 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5704 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5705 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5708 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5709 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5710 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5715 // If we know that the high bits of the shift amount are all zero, then we can
5716 // do this as a couple of simple shifts.
5717 if ((KnownZero & Mask) == Mask) {
5719 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5720 DAG.getConstant(NVTBits, Amt.getValueType()),
5723 // Expand the incoming operand to be shifted, so that we have its parts
5725 ExpandOp(Op, InL, InH);
5728 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5729 Hi = DAG.getNode(ISD::OR, NVT,
5730 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5731 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5734 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5735 Lo = DAG.getNode(ISD::OR, NVT,
5736 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5737 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5740 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5741 Lo = DAG.getNode(ISD::OR, NVT,
5742 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5743 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5752 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5753 // does not fit into a register, return the lo part and set the hi part to the
5754 // by-reg argument. If it does fit into a single register, return the result
5755 // and leave the Hi part unset.
5756 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5757 bool isSigned, SDValue &Hi) {
5758 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5759 // The input chain to this libcall is the entry node of the function.
5760 // Legalizing the call will automatically add the previous call to the
5762 SDValue InChain = DAG.getEntryNode();
5764 TargetLowering::ArgListTy Args;
5765 TargetLowering::ArgListEntry Entry;
5766 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5767 MVT ArgVT = Node->getOperand(i).getValueType();
5768 const Type *ArgTy = ArgVT.getTypeForMVT();
5769 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5770 Entry.isSExt = isSigned;
5771 Entry.isZExt = !isSigned;
5772 Args.push_back(Entry);
5774 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5775 TLI.getPointerTy());
5777 // Splice the libcall in wherever FindInputOutputChains tells us to.
5778 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5779 std::pair<SDValue,SDValue> CallInfo =
5780 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5781 CallingConv::C, false, Callee, Args, DAG);
5783 // Legalize the call sequence, starting with the chain. This will advance
5784 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5785 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5786 LegalizeOp(CallInfo.second);
5788 switch (getTypeAction(CallInfo.first.getValueType())) {
5789 default: assert(0 && "Unknown thing");
5791 Result = CallInfo.first;
5794 ExpandOp(CallInfo.first, Result, Hi);
5800 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5802 SDValue SelectionDAGLegalize::
5803 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) {
5804 bool isCustom = false;
5806 switch (getTypeAction(Op.getValueType())) {
5808 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5809 Op.getValueType())) {
5810 default: assert(0 && "Unknown operation action!");
5811 case TargetLowering::Custom:
5814 case TargetLowering::Legal:
5815 Tmp1 = LegalizeOp(Op);
5816 if (Result.getNode())
5817 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5819 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5822 Tmp1 = TLI.LowerOperation(Result, DAG);
5823 if (Tmp1.getNode()) Result = Tmp1;
5826 case TargetLowering::Expand:
5827 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy);
5829 case TargetLowering::Promote:
5830 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned);
5835 Result = ExpandIntToFP(isSigned, DestTy, Op);
5838 Tmp1 = PromoteOp(Op);
5840 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
5841 Tmp1, DAG.getValueType(Op.getValueType()));
5843 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
5846 if (Result.getNode())
5847 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5849 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5851 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5857 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5859 SDValue SelectionDAGLegalize::
5860 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
5861 MVT SourceVT = Source.getValueType();
5862 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5864 // Expand unsupported int-to-fp vector casts by unrolling them.
5865 if (DestTy.isVector()) {
5867 return LegalizeOp(UnrollVectorOp(Source));
5868 MVT DestEltTy = DestTy.getVectorElementType();
5869 if (DestTy.getVectorNumElements() == 1) {
5870 SDValue Scalar = ScalarizeVectorOp(Source);
5871 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5873 return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result);
5876 SplitVectorOp(Source, Lo, Hi);
5877 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5878 DestTy.getVectorNumElements() / 2);
5879 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo);
5880 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi);
5881 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult,
5885 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5886 if (!isSigned && SourceVT != MVT::i32) {
5887 // The integer value loaded will be incorrectly if the 'sign bit' of the
5888 // incoming integer is set. To handle this, we dynamically test to see if
5889 // it is set, and, if so, add a fudge factor.
5893 ExpandOp(Source, Lo, Hi);
5894 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5896 // The comparison for the sign bit will use the entire operand.
5900 // Check to see if the target has a custom way to lower this. If so, use
5901 // it. (Note we've already expanded the operand in this case.)
5902 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) {
5903 default: assert(0 && "This action not implemented for this operation!");
5904 case TargetLowering::Legal:
5905 case TargetLowering::Expand:
5906 break; // This case is handled below.
5907 case TargetLowering::Custom: {
5908 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, DestTy,
5911 return LegalizeOp(NV);
5912 break; // The target decided this was legal after all
5916 // If this is unsigned, and not supported, first perform the conversion to
5917 // signed, then adjust the result if the sign bit is set.
5918 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
5920 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi.getValueType()),
5921 Hi, DAG.getConstant(0, Hi.getValueType()),
5923 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5924 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5925 SignSet, Four, Zero);
5926 uint64_t FF = 0x5f800000ULL;
5927 if (TLI.isLittleEndian()) FF <<= 32;
5928 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5930 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5931 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5932 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5933 Alignment = std::min(Alignment, 4u);
5935 if (DestTy == MVT::f32)
5936 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5937 PseudoSourceValue::getConstantPool(), 0,
5939 else if (DestTy.bitsGT(MVT::f32))
5940 // FIXME: Avoid the extend by construction the right constantpool?
5941 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5943 PseudoSourceValue::getConstantPool(), 0,
5944 MVT::f32, false, Alignment);
5946 assert(0 && "Unexpected conversion");
5948 MVT SCVT = SignedConv.getValueType();
5949 if (SCVT != DestTy) {
5950 // Destination type needs to be expanded as well. The FADD now we are
5951 // constructing will be expanded into a libcall.
5952 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5953 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5954 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5955 SignedConv, SignedConv.getValue(1));
5957 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5959 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5962 // Check to see if the target has a custom way to lower this. If so, use it.
5963 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5964 default: assert(0 && "This action not implemented for this operation!");
5965 case TargetLowering::Legal:
5966 case TargetLowering::Expand:
5967 break; // This case is handled below.
5968 case TargetLowering::Custom: {
5969 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5972 return LegalizeOp(NV);
5973 break; // The target decided this was legal after all
5977 // Expand the source, then glue it back together for the call. We must expand
5978 // the source in case it is shared (this pass of legalize must traverse it).
5980 SDValue SrcLo, SrcHi;
5981 ExpandOp(Source, SrcLo, SrcHi);
5982 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5985 RTLIB::Libcall LC = isSigned ?
5986 RTLIB::getSINTTOFP(SourceVT, DestTy) :
5987 RTLIB::getUINTTOFP(SourceVT, DestTy);
5988 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
5990 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5992 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
5993 if (Result.getValueType() != DestTy && HiPart.getNode())
5994 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5998 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5999 /// INT_TO_FP operation of the specified operand when the target requests that
6000 /// we expand it. At this point, we know that the result and operand types are
6001 /// legal for the target.
6002 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
6005 if (Op0.getValueType() == MVT::i32) {
6006 // simple 32-bit [signed|unsigned] integer to float/double expansion
6008 // Get the stack frame index of a 8 byte buffer.
6009 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
6011 // word offset constant for Hi/Lo address computation
6012 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
6013 // set up Hi and Lo (into buffer) address based on endian
6014 SDValue Hi = StackSlot;
6015 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
6016 if (TLI.isLittleEndian())
6019 // if signed map to unsigned space
6022 // constant used to invert sign bit (signed to unsigned mapping)
6023 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
6024 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
6028 // store the lo of the constructed double - based on integer input
6029 SDValue Store1 = DAG.getStore(DAG.getEntryNode(),
6030 Op0Mapped, Lo, NULL, 0);
6031 // initial hi portion of constructed double
6032 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
6033 // store the hi of the constructed double - biased exponent
6034 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
6035 // load the constructed double
6036 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
6037 // FP constant to bias correct the final result
6038 SDValue Bias = DAG.getConstantFP(isSigned ?
6039 BitsToDouble(0x4330000080000000ULL)
6040 : BitsToDouble(0x4330000000000000ULL),
6042 // subtract the bias
6043 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
6046 // handle final rounding
6047 if (DestVT == MVT::f64) {
6050 } else if (DestVT.bitsLT(MVT::f64)) {
6051 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
6052 DAG.getIntPtrConstant(0));
6053 } else if (DestVT.bitsGT(MVT::f64)) {
6054 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
6058 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
6059 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
6061 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0.getValueType()),
6062 Op0, DAG.getConstant(0, Op0.getValueType()),
6064 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
6065 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
6066 SignSet, Four, Zero);
6068 // If the sign bit of the integer is set, the large number will be treated
6069 // as a negative number. To counteract this, the dynamic code adds an
6070 // offset depending on the data type.
6072 switch (Op0.getValueType().getSimpleVT()) {
6073 default: assert(0 && "Unsupported integer type!");
6074 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
6075 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
6076 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
6077 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
6079 if (TLI.isLittleEndian()) FF <<= 32;
6080 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
6082 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
6083 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6084 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
6085 Alignment = std::min(Alignment, 4u);
6087 if (DestVT == MVT::f32)
6088 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
6089 PseudoSourceValue::getConstantPool(), 0,
6093 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
6094 DAG.getEntryNode(), CPIdx,
6095 PseudoSourceValue::getConstantPool(), 0,
6096 MVT::f32, false, Alignment));
6099 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
6102 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
6103 /// *INT_TO_FP operation of the specified operand when the target requests that
6104 /// we promote it. At this point, we know that the result and operand types are
6105 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
6106 /// operation that takes a larger input.
6107 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
6110 // First step, figure out the appropriate *INT_TO_FP operation to use.
6111 MVT NewInTy = LegalOp.getValueType();
6113 unsigned OpToUse = 0;
6115 // Scan for the appropriate larger type to use.
6117 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
6118 assert(NewInTy.isInteger() && "Ran out of possibilities!");
6120 // If the target supports SINT_TO_FP of this type, use it.
6121 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
6123 case TargetLowering::Legal:
6124 if (!TLI.isTypeLegal(NewInTy))
6125 break; // Can't use this datatype.
6127 case TargetLowering::Custom:
6128 OpToUse = ISD::SINT_TO_FP;
6132 if (isSigned) continue;
6134 // If the target supports UINT_TO_FP of this type, use it.
6135 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
6137 case TargetLowering::Legal:
6138 if (!TLI.isTypeLegal(NewInTy))
6139 break; // Can't use this datatype.
6141 case TargetLowering::Custom:
6142 OpToUse = ISD::UINT_TO_FP;
6147 // Otherwise, try a larger type.
6150 // Okay, we found the operation and type to use. Zero extend our input to the
6151 // desired type then run the operation on it.
6152 return DAG.getNode(OpToUse, DestVT,
6153 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
6157 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
6158 /// FP_TO_*INT operation of the specified operand when the target requests that
6159 /// we promote it. At this point, we know that the result and operand types are
6160 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
6161 /// operation that returns a larger result.
6162 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
6165 // First step, figure out the appropriate FP_TO*INT operation to use.
6166 MVT NewOutTy = DestVT;
6168 unsigned OpToUse = 0;
6170 // Scan for the appropriate larger type to use.
6172 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
6173 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
6175 // If the target supports FP_TO_SINT returning this type, use it.
6176 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
6178 case TargetLowering::Legal:
6179 if (!TLI.isTypeLegal(NewOutTy))
6180 break; // Can't use this datatype.
6182 case TargetLowering::Custom:
6183 OpToUse = ISD::FP_TO_SINT;
6188 // If the target supports FP_TO_UINT of this type, use it.
6189 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
6191 case TargetLowering::Legal:
6192 if (!TLI.isTypeLegal(NewOutTy))
6193 break; // Can't use this datatype.
6195 case TargetLowering::Custom:
6196 OpToUse = ISD::FP_TO_UINT;
6201 // Otherwise, try a larger type.
6205 // Okay, we found the operation and type to use.
6206 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
6208 // If the operation produces an invalid type, it must be custom lowered. Use
6209 // the target lowering hooks to expand it. Just keep the low part of the
6210 // expanded operation, we know that we're truncating anyway.
6211 if (getTypeAction(NewOutTy) == Expand) {
6212 SmallVector<SDValue, 2> Results;
6213 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG);
6214 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!");
6215 Operation = Results[0];
6218 // Truncate the result of the extended FP_TO_*INT operation to the desired
6220 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
6223 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
6225 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) {
6226 MVT VT = Op.getValueType();
6227 MVT SHVT = TLI.getShiftAmountTy();
6228 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
6229 switch (VT.getSimpleVT()) {
6230 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
6232 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6233 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6234 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
6236 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
6237 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6238 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6239 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
6240 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
6241 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
6242 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
6243 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
6244 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
6246 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
6247 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
6248 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
6249 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6250 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6251 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
6252 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
6253 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
6254 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
6255 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
6256 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
6257 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
6258 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
6259 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
6260 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
6261 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
6262 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
6263 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
6264 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
6265 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
6266 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
6270 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
6272 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
6274 default: assert(0 && "Cannot expand this yet!");
6276 static const uint64_t mask[6] = {
6277 0x5555555555555555ULL, 0x3333333333333333ULL,
6278 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
6279 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
6281 MVT VT = Op.getValueType();
6282 MVT ShVT = TLI.getShiftAmountTy();
6283 unsigned len = VT.getSizeInBits();
6284 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6285 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
6286 SDValue Tmp2 = DAG.getConstant(mask[i], VT);
6287 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6288 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
6289 DAG.getNode(ISD::AND, VT,
6290 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
6295 // for now, we do this:
6296 // x = x | (x >> 1);
6297 // x = x | (x >> 2);
6299 // x = x | (x >>16);
6300 // x = x | (x >>32); // for 64-bit input
6301 // return popcount(~x);
6303 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
6304 MVT VT = Op.getValueType();
6305 MVT ShVT = TLI.getShiftAmountTy();
6306 unsigned len = VT.getSizeInBits();
6307 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6308 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6309 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
6311 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
6312 return DAG.getNode(ISD::CTPOP, VT, Op);
6315 // for now, we use: { return popcount(~x & (x - 1)); }
6316 // unless the target has ctlz but not ctpop, in which case we use:
6317 // { return 32 - nlz(~x & (x-1)); }
6318 // see also http://www.hackersdelight.org/HDcode/ntz.cc
6319 MVT VT = Op.getValueType();
6320 SDValue Tmp2 = DAG.getConstant(~0ULL, VT);
6321 SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
6322 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
6323 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
6324 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6325 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
6326 TLI.isOperationLegal(ISD::CTLZ, VT))
6327 return DAG.getNode(ISD::SUB, VT,
6328 DAG.getConstant(VT.getSizeInBits(), VT),
6329 DAG.getNode(ISD::CTLZ, VT, Tmp3));
6330 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
6335 /// ExpandOp - Expand the specified SDValue into its two component pieces
6336 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
6337 /// LegalizedNodes map is filled in for any results that are not expanded, the
6338 /// ExpandedNodes map is filled in for any results that are expanded, and the
6339 /// Lo/Hi values are returned.
6340 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
6341 MVT VT = Op.getValueType();
6342 MVT NVT = TLI.getTypeToTransformTo(VT);
6343 SDNode *Node = Op.getNode();
6344 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
6345 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
6346 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
6348 // See if we already expanded it.
6349 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
6350 = ExpandedNodes.find(Op);
6351 if (I != ExpandedNodes.end()) {
6352 Lo = I->second.first;
6353 Hi = I->second.second;
6357 switch (Node->getOpcode()) {
6358 case ISD::CopyFromReg:
6359 assert(0 && "CopyFromReg must be legal!");
6360 case ISD::FP_ROUND_INREG:
6361 if (VT == MVT::ppcf128 &&
6362 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
6363 TargetLowering::Custom) {
6364 SDValue SrcLo, SrcHi, Src;
6365 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
6366 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
6367 SDValue Result = TLI.LowerOperation(
6368 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
6369 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
6370 Lo = Result.getNode()->getOperand(0);
6371 Hi = Result.getNode()->getOperand(1);
6377 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
6379 assert(0 && "Do not know how to expand this operator!");
6381 case ISD::EXTRACT_ELEMENT:
6382 ExpandOp(Node->getOperand(0), Lo, Hi);
6383 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
6384 return ExpandOp(Hi, Lo, Hi);
6385 return ExpandOp(Lo, Lo, Hi);
6386 case ISD::EXTRACT_VECTOR_ELT:
6387 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
6388 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
6389 return ExpandOp(Lo, Lo, Hi);
6391 Lo = DAG.getNode(ISD::UNDEF, NVT);
6392 Hi = DAG.getNode(ISD::UNDEF, NVT);
6394 case ISD::Constant: {
6395 unsigned NVTBits = NVT.getSizeInBits();
6396 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
6397 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
6398 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
6401 case ISD::ConstantFP: {
6402 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
6403 if (CFP->getValueType(0) == MVT::ppcf128) {
6404 APInt api = CFP->getValueAPF().bitcastToAPInt();
6405 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
6407 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
6411 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
6412 if (getTypeAction(Lo.getValueType()) == Expand)
6413 ExpandOp(Lo, Lo, Hi);
6416 case ISD::BUILD_PAIR:
6417 // Return the operands.
6418 Lo = Node->getOperand(0);
6419 Hi = Node->getOperand(1);
6422 case ISD::MERGE_VALUES:
6423 if (Node->getNumValues() == 1) {
6424 ExpandOp(Op.getOperand(0), Lo, Hi);
6427 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
6428 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
6429 Op.getValue(1).getValueType() == MVT::Other &&
6430 "unhandled MERGE_VALUES");
6431 ExpandOp(Op.getOperand(0), Lo, Hi);
6432 // Remember that we legalized the chain.
6433 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
6436 case ISD::SIGN_EXTEND_INREG:
6437 ExpandOp(Node->getOperand(0), Lo, Hi);
6438 // sext_inreg the low part if needed.
6439 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
6441 // The high part gets the sign extension from the lo-part. This handles
6442 // things like sextinreg V:i64 from i8.
6443 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6444 DAG.getConstant(NVT.getSizeInBits()-1,
6445 TLI.getShiftAmountTy()));
6449 ExpandOp(Node->getOperand(0), Lo, Hi);
6450 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
6451 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
6457 ExpandOp(Node->getOperand(0), Lo, Hi);
6458 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
6459 DAG.getNode(ISD::CTPOP, NVT, Lo),
6460 DAG.getNode(ISD::CTPOP, NVT, Hi));
6461 Hi = DAG.getConstant(0, NVT);
6465 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
6466 ExpandOp(Node->getOperand(0), Lo, Hi);
6467 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6468 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
6469 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), HLZ, BitsC,
6471 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
6472 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
6474 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
6475 Hi = DAG.getConstant(0, NVT);
6480 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
6481 ExpandOp(Node->getOperand(0), Lo, Hi);
6482 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6483 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
6484 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), LTZ, BitsC,
6486 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
6487 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
6489 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
6490 Hi = DAG.getConstant(0, NVT);
6495 SDValue Ch = Node->getOperand(0); // Legalize the chain.
6496 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6497 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
6498 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
6500 // Remember that we legalized the chain.
6501 Hi = LegalizeOp(Hi);
6502 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6503 if (TLI.isBigEndian())
6509 LoadSDNode *LD = cast<LoadSDNode>(Node);
6510 SDValue Ch = LD->getChain(); // Legalize the chain.
6511 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6512 ISD::LoadExtType ExtType = LD->getExtensionType();
6513 const Value *SV = LD->getSrcValue();
6514 int SVOffset = LD->getSrcValueOffset();
6515 unsigned Alignment = LD->getAlignment();
6516 bool isVolatile = LD->isVolatile();
6518 if (ExtType == ISD::NON_EXTLOAD) {
6519 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6520 isVolatile, Alignment);
6521 if (VT == MVT::f32 || VT == MVT::f64) {
6522 // f32->i32 or f64->i64 one to one expansion.
6523 // Remember that we legalized the chain.
6524 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6525 // Recursively expand the new load.
6526 if (getTypeAction(NVT) == Expand)
6527 ExpandOp(Lo, Lo, Hi);
6531 // Increment the pointer to the other half.
6532 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6533 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6534 DAG.getIntPtrConstant(IncrementSize));
6535 SVOffset += IncrementSize;
6536 Alignment = MinAlign(Alignment, IncrementSize);
6537 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6538 isVolatile, Alignment);
6540 // Build a factor node to remember that this load is independent of the
6542 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6545 // Remember that we legalized the chain.
6546 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6547 if (TLI.isBigEndian())
6550 MVT EVT = LD->getMemoryVT();
6552 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6553 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6554 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6555 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV,
6556 SVOffset, isVolatile, Alignment);
6557 // Remember that we legalized the chain.
6558 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6559 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
6564 Lo = DAG.getLoad(NVT, Ch, Ptr, SV,
6565 SVOffset, isVolatile, Alignment);
6567 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV,
6568 SVOffset, EVT, isVolatile,
6571 // Remember that we legalized the chain.
6572 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6574 if (ExtType == ISD::SEXTLOAD) {
6575 // The high part is obtained by SRA'ing all but one of the bits of the
6577 unsigned LoSize = Lo.getValueType().getSizeInBits();
6578 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6579 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6580 } else if (ExtType == ISD::ZEXTLOAD) {
6581 // The high part is just a zero.
6582 Hi = DAG.getConstant(0, NVT);
6583 } else /* if (ExtType == ISD::EXTLOAD) */ {
6584 // The high part is undefined.
6585 Hi = DAG.getNode(ISD::UNDEF, NVT);
6592 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6593 SDValue LL, LH, RL, RH;
6594 ExpandOp(Node->getOperand(0), LL, LH);
6595 ExpandOp(Node->getOperand(1), RL, RH);
6596 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
6597 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
6601 SDValue LL, LH, RL, RH;
6602 ExpandOp(Node->getOperand(1), LL, LH);
6603 ExpandOp(Node->getOperand(2), RL, RH);
6604 if (getTypeAction(NVT) == Expand)
6605 NVT = TLI.getTypeToExpandTo(NVT);
6606 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
6608 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
6611 case ISD::SELECT_CC: {
6612 SDValue TL, TH, FL, FH;
6613 ExpandOp(Node->getOperand(2), TL, TH);
6614 ExpandOp(Node->getOperand(3), FL, FH);
6615 if (getTypeAction(NVT) == Expand)
6616 NVT = TLI.getTypeToExpandTo(NVT);
6617 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6618 Node->getOperand(1), TL, FL, Node->getOperand(4));
6620 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6621 Node->getOperand(1), TH, FH, Node->getOperand(4));
6624 case ISD::ANY_EXTEND:
6625 // The low part is any extension of the input (which degenerates to a copy).
6626 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6627 // The high part is undefined.
6628 Hi = DAG.getNode(ISD::UNDEF, NVT);
6630 case ISD::SIGN_EXTEND: {
6631 // The low part is just a sign extension of the input (which degenerates to
6633 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6635 // The high part is obtained by SRA'ing all but one of the bits of the lo
6637 unsigned LoSize = Lo.getValueType().getSizeInBits();
6638 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6639 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6642 case ISD::ZERO_EXTEND:
6643 // The low part is just a zero extension of the input (which degenerates to
6645 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6647 // The high part is just a zero.
6648 Hi = DAG.getConstant(0, NVT);
6651 case ISD::TRUNCATE: {
6652 // The input value must be larger than this value. Expand *it*.
6654 ExpandOp(Node->getOperand(0), NewLo, Hi);
6656 // The low part is now either the right size, or it is closer. If not the
6657 // right size, make an illegal truncate so we recursively expand it.
6658 if (NewLo.getValueType() != Node->getValueType(0))
6659 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6660 ExpandOp(NewLo, Lo, Hi);
6664 case ISD::BIT_CONVERT: {
6666 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6667 // If the target wants to, allow it to lower this itself.
6668 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6669 case Expand: assert(0 && "cannot expand FP!");
6670 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6671 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6673 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6676 // f32 / f64 must be expanded to i32 / i64.
6677 if (VT == MVT::f32 || VT == MVT::f64) {
6678 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6679 if (getTypeAction(NVT) == Expand)
6680 ExpandOp(Lo, Lo, Hi);
6684 // If source operand will be expanded to the same type as VT, i.e.
6685 // i64 <- f64, i32 <- f32, expand the source operand instead.
6686 MVT VT0 = Node->getOperand(0).getValueType();
6687 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6688 ExpandOp(Node->getOperand(0), Lo, Hi);
6692 // Turn this into a load/store pair by default.
6693 if (Tmp.getNode() == 0)
6694 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6696 ExpandOp(Tmp, Lo, Hi);
6700 case ISD::READCYCLECOUNTER: {
6701 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6702 TargetLowering::Custom &&
6703 "Must custom expand ReadCycleCounter");
6704 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6705 assert(Tmp.getNode() && "Node must be custom expanded!");
6706 ExpandOp(Tmp.getValue(0), Lo, Hi);
6707 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6708 LegalizeOp(Tmp.getValue(1)));
6712 case ISD::ATOMIC_CMP_SWAP: {
6713 // This operation does not need a loop.
6714 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6715 assert(Tmp.getNode() && "Node must be custom expanded!");
6716 ExpandOp(Tmp.getValue(0), Lo, Hi);
6717 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6718 LegalizeOp(Tmp.getValue(1)));
6722 case ISD::ATOMIC_LOAD_ADD:
6723 case ISD::ATOMIC_LOAD_SUB:
6724 case ISD::ATOMIC_LOAD_AND:
6725 case ISD::ATOMIC_LOAD_OR:
6726 case ISD::ATOMIC_LOAD_XOR:
6727 case ISD::ATOMIC_LOAD_NAND:
6728 case ISD::ATOMIC_SWAP: {
6729 // These operations require a loop to be generated. We can't do that yet,
6730 // so substitute a target-dependent pseudo and expand that later.
6731 SDValue In2Lo, In2Hi, In2;
6732 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6733 In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi);
6734 AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
6736 DAG.getAtomic(Op.getOpcode(), Anode->getMemoryVT(),
6737 Op.getOperand(0), Op.getOperand(1), In2,
6738 Anode->getSrcValue(), Anode->getAlignment());
6739 SDValue Result = TLI.LowerOperation(Replace, DAG);
6740 ExpandOp(Result.getValue(0), Lo, Hi);
6741 // Remember that we legalized the chain.
6742 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
6746 // These operators cannot be expanded directly, emit them as calls to
6747 // library functions.
6748 case ISD::FP_TO_SINT: {
6749 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6751 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6752 case Expand: assert(0 && "cannot expand FP!");
6753 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6754 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6757 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6759 // Now that the custom expander is done, expand the result, which is still
6762 ExpandOp(Op, Lo, Hi);
6767 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6769 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6770 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6774 case ISD::FP_TO_UINT: {
6775 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6777 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6778 case Expand: assert(0 && "cannot expand FP!");
6779 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6780 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6783 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6785 // Now that the custom expander is done, expand the result.
6787 ExpandOp(Op, Lo, Hi);
6792 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6794 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6795 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6800 // If the target wants custom lowering, do so.
6801 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6802 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6803 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6804 Op = TLI.LowerOperation(Op, DAG);
6806 // Now that the custom expander is done, expand the result, which is
6808 ExpandOp(Op, Lo, Hi);
6813 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6814 // this X << 1 as X+X.
6815 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6816 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6817 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6818 SDValue LoOps[2], HiOps[3];
6819 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6820 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6821 LoOps[1] = LoOps[0];
6822 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6824 HiOps[1] = HiOps[0];
6825 HiOps[2] = Lo.getValue(1);
6826 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6831 // If we can emit an efficient shift operation, do so now.
6832 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6835 // If this target supports SHL_PARTS, use it.
6836 TargetLowering::LegalizeAction Action =
6837 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6838 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6839 Action == TargetLowering::Custom) {
6840 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6844 // Otherwise, emit a libcall.
6845 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6850 // If the target wants custom lowering, do so.
6851 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6852 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6853 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6854 Op = TLI.LowerOperation(Op, DAG);
6856 // Now that the custom expander is done, expand the result, which is
6858 ExpandOp(Op, Lo, Hi);
6863 // If we can emit an efficient shift operation, do so now.
6864 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6867 // If this target supports SRA_PARTS, use it.
6868 TargetLowering::LegalizeAction Action =
6869 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6870 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6871 Action == TargetLowering::Custom) {
6872 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6876 // Otherwise, emit a libcall.
6877 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6882 // If the target wants custom lowering, do so.
6883 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6884 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6885 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6886 Op = TLI.LowerOperation(Op, DAG);
6888 // Now that the custom expander is done, expand the result, which is
6890 ExpandOp(Op, Lo, Hi);
6895 // If we can emit an efficient shift operation, do so now.
6896 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6899 // If this target supports SRL_PARTS, use it.
6900 TargetLowering::LegalizeAction Action =
6901 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6902 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6903 Action == TargetLowering::Custom) {
6904 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6908 // Otherwise, emit a libcall.
6909 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6915 // If the target wants to custom expand this, let them.
6916 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6917 TargetLowering::Custom) {
6918 SDValue Result = TLI.LowerOperation(Op, DAG);
6919 if (Result.getNode()) {
6920 ExpandOp(Result, Lo, Hi);
6924 // Expand the subcomponents.
6925 SDValue LHSL, LHSH, RHSL, RHSH;
6926 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6927 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6928 SDValue LoOps[2], HiOps[3];
6934 //cascaded check to see if any smaller size has a a carry flag.
6935 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
6936 bool hasCarry = false;
6937 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
6938 MVT AVT = MVT::getIntegerVT(BitSize);
6939 if (TLI.isOperationLegal(OpV, AVT)) {
6946 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6947 if (Node->getOpcode() == ISD::ADD) {
6948 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6949 HiOps[2] = Lo.getValue(1);
6950 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6952 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6953 HiOps[2] = Lo.getValue(1);
6954 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6958 if (Node->getOpcode() == ISD::ADD) {
6959 Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2);
6960 Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2);
6961 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(NVT),
6962 Lo, LoOps[0], ISD::SETULT);
6963 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
6964 DAG.getConstant(1, NVT),
6965 DAG.getConstant(0, NVT));
6966 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(NVT),
6967 Lo, LoOps[1], ISD::SETULT);
6968 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
6969 DAG.getConstant(1, NVT),
6971 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
6973 Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2);
6974 Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2);
6975 SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT);
6976 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
6977 DAG.getConstant(1, NVT),
6978 DAG.getConstant(0, NVT));
6979 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow);
6987 // Expand the subcomponents.
6988 SDValue LHSL, LHSH, RHSL, RHSH;
6989 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6990 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6991 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6992 SDValue LoOps[2] = { LHSL, RHSL };
6993 SDValue HiOps[3] = { LHSH, RHSH };
6995 if (Node->getOpcode() == ISD::ADDC) {
6996 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6997 HiOps[2] = Lo.getValue(1);
6998 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
7000 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
7001 HiOps[2] = Lo.getValue(1);
7002 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
7004 // Remember that we legalized the flag.
7005 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7010 // Expand the subcomponents.
7011 SDValue LHSL, LHSH, RHSL, RHSH;
7012 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7013 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7014 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7015 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
7016 SDValue HiOps[3] = { LHSH, RHSH };
7018 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
7019 HiOps[2] = Lo.getValue(1);
7020 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
7022 // Remember that we legalized the flag.
7023 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7027 // If the target wants to custom expand this, let them.
7028 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
7029 SDValue New = TLI.LowerOperation(Op, DAG);
7030 if (New.getNode()) {
7031 ExpandOp(New, Lo, Hi);
7036 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
7037 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
7038 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
7039 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
7040 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
7041 SDValue LL, LH, RL, RH;
7042 ExpandOp(Node->getOperand(0), LL, LH);
7043 ExpandOp(Node->getOperand(1), RL, RH);
7044 unsigned OuterBitSize = Op.getValueSizeInBits();
7045 unsigned InnerBitSize = RH.getValueSizeInBits();
7046 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
7047 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
7048 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
7049 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
7050 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
7051 // The inputs are both zero-extended.
7053 // We can emit a umul_lohi.
7054 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
7055 Hi = SDValue(Lo.getNode(), 1);
7059 // We can emit a mulhu+mul.
7060 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
7061 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
7065 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
7066 // The input values are both sign-extended.
7068 // We can emit a smul_lohi.
7069 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
7070 Hi = SDValue(Lo.getNode(), 1);
7074 // We can emit a mulhs+mul.
7075 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
7076 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
7081 // Lo,Hi = umul LHS, RHS.
7082 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
7083 DAG.getVTList(NVT, NVT), LL, RL);
7085 Hi = UMulLOHI.getValue(1);
7086 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
7087 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
7088 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
7089 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
7093 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
7094 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
7095 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
7096 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
7097 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
7098 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
7103 // If nothing else, we can make a libcall.
7104 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
7108 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
7111 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
7114 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
7117 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
7121 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
7124 RTLIB::ADD_PPCF128),
7128 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
7131 RTLIB::SUB_PPCF128),
7135 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
7138 RTLIB::MUL_PPCF128),
7142 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
7145 RTLIB::DIV_PPCF128),
7148 case ISD::FP_EXTEND: {
7149 if (VT == MVT::ppcf128) {
7150 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
7151 Node->getOperand(0).getValueType()==MVT::f64);
7152 const uint64_t zero = 0;
7153 if (Node->getOperand(0).getValueType()==MVT::f32)
7154 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
7156 Hi = Node->getOperand(0);
7157 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7160 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
7161 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
7162 Lo = ExpandLibCall(LC, Node, true, Hi);
7165 case ISD::FP_ROUND: {
7166 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
7168 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
7169 Lo = ExpandLibCall(LC, Node, true, Hi);
7184 case ISD::FNEARBYINT:
7187 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
7188 switch(Node->getOpcode()) {
7190 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
7191 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
7194 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
7195 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
7198 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
7199 RTLIB::COS_F80, RTLIB::COS_PPCF128);
7202 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
7203 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
7206 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
7207 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
7210 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
7211 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
7214 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
7215 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
7218 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
7219 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
7222 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
7223 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
7226 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
7227 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
7230 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
7231 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
7234 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
7235 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
7237 case ISD::FNEARBYINT:
7238 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
7239 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
7242 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
7243 RTLIB::POW_PPCF128);
7246 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
7247 RTLIB::POWI_PPCF128);
7249 default: assert(0 && "Unreachable!");
7251 Lo = ExpandLibCall(LC, Node, false, Hi);
7255 if (VT == MVT::ppcf128) {
7257 ExpandOp(Node->getOperand(0), Lo, Tmp);
7258 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
7259 // lo = hi==fabs(hi) ? lo : -lo;
7260 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
7261 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
7262 DAG.getCondCode(ISD::SETEQ));
7265 SDValue Mask = (VT == MVT::f64)
7266 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
7267 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
7268 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
7269 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
7270 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
7271 if (getTypeAction(NVT) == Expand)
7272 ExpandOp(Lo, Lo, Hi);
7276 if (VT == MVT::ppcf128) {
7277 ExpandOp(Node->getOperand(0), Lo, Hi);
7278 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
7279 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
7282 SDValue Mask = (VT == MVT::f64)
7283 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
7284 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
7285 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
7286 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
7287 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
7288 if (getTypeAction(NVT) == Expand)
7289 ExpandOp(Lo, Lo, Hi);
7292 case ISD::FCOPYSIGN: {
7293 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
7294 if (getTypeAction(NVT) == Expand)
7295 ExpandOp(Lo, Lo, Hi);
7298 case ISD::SINT_TO_FP:
7299 case ISD::UINT_TO_FP: {
7300 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
7301 MVT SrcVT = Node->getOperand(0).getValueType();
7303 // Promote the operand if needed. Do this before checking for
7304 // ppcf128 so conversions of i16 and i8 work.
7305 if (getTypeAction(SrcVT) == Promote) {
7306 SDValue Tmp = PromoteOp(Node->getOperand(0));
7308 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
7309 DAG.getValueType(SrcVT))
7310 : DAG.getZeroExtendInReg(Tmp, SrcVT);
7311 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
7312 SrcVT = Node->getOperand(0).getValueType();
7315 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
7316 static const uint64_t zero = 0;
7318 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
7319 Node->getOperand(0)));
7320 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7322 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
7323 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
7324 Node->getOperand(0)));
7325 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7326 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
7327 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
7328 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
7329 DAG.getConstant(0, MVT::i32),
7330 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
7332 APFloat(APInt(128, 2, TwoE32)),
7335 DAG.getCondCode(ISD::SETLT)),
7340 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
7341 // si64->ppcf128 done by libcall, below
7342 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
7343 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
7345 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
7346 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
7347 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
7348 DAG.getConstant(0, MVT::i64),
7349 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
7351 APFloat(APInt(128, 2, TwoE64)),
7354 DAG.getCondCode(ISD::SETLT)),
7359 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
7360 Node->getOperand(0));
7361 if (getTypeAction(Lo.getValueType()) == Expand)
7362 // float to i32 etc. can be 'expanded' to a single node.
7363 ExpandOp(Lo, Lo, Hi);
7368 // Make sure the resultant values have been legalized themselves, unless this
7369 // is a type that requires multi-step expansion.
7370 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
7371 Lo = LegalizeOp(Lo);
7373 // Don't legalize the high part if it is expanded to a single node.
7374 Hi = LegalizeOp(Hi);
7377 // Remember in a map if the values will be reused later.
7379 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7380 assert(isNew && "Value already expanded?!?");
7384 /// SplitVectorOp - Given an operand of vector type, break it down into
7385 /// two smaller values, still of vector type.
7386 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
7388 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
7389 SDNode *Node = Op.getNode();
7390 unsigned NumElements = Op.getValueType().getVectorNumElements();
7391 assert(NumElements > 1 && "Cannot split a single element vector!");
7393 MVT NewEltVT = Op.getValueType().getVectorElementType();
7395 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
7396 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
7398 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
7399 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
7401 // See if we already split it.
7402 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
7403 = SplitNodes.find(Op);
7404 if (I != SplitNodes.end()) {
7405 Lo = I->second.first;
7406 Hi = I->second.second;
7410 switch (Node->getOpcode()) {
7415 assert(0 && "Unhandled operation in SplitVectorOp!");
7417 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
7418 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
7420 case ISD::BUILD_PAIR:
7421 Lo = Node->getOperand(0);
7422 Hi = Node->getOperand(1);
7424 case ISD::INSERT_VECTOR_ELT: {
7425 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
7426 SplitVectorOp(Node->getOperand(0), Lo, Hi);
7427 unsigned Index = Idx->getZExtValue();
7428 SDValue ScalarOp = Node->getOperand(1);
7429 if (Index < NewNumElts_Lo)
7430 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
7431 DAG.getIntPtrConstant(Index));
7433 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
7434 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
7437 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
7438 Node->getOperand(1),
7439 Node->getOperand(2));
7440 SplitVectorOp(Tmp, Lo, Hi);
7443 case ISD::VECTOR_SHUFFLE: {
7444 // Build the low part.
7445 SDValue Mask = Node->getOperand(2);
7446 SmallVector<SDValue, 8> Ops;
7447 MVT PtrVT = TLI.getPointerTy();
7449 // Insert all of the elements from the input that are needed. We use
7450 // buildvector of extractelement here because the input vectors will have
7451 // to be legalized, so this makes the code simpler.
7452 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
7453 SDValue IdxNode = Mask.getOperand(i);
7454 if (IdxNode.getOpcode() == ISD::UNDEF) {
7455 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
7458 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7459 SDValue InVec = Node->getOperand(0);
7460 if (Idx >= NumElements) {
7461 InVec = Node->getOperand(1);
7464 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
7465 DAG.getConstant(Idx, PtrVT)));
7467 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
7470 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
7471 SDValue IdxNode = Mask.getOperand(i);
7472 if (IdxNode.getOpcode() == ISD::UNDEF) {
7473 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
7476 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7477 SDValue InVec = Node->getOperand(0);
7478 if (Idx >= NumElements) {
7479 InVec = Node->getOperand(1);
7482 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
7483 DAG.getConstant(Idx, PtrVT)));
7485 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size());
7488 case ISD::BUILD_VECTOR: {
7489 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7490 Node->op_begin()+NewNumElts_Lo);
7491 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
7493 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
7495 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
7498 case ISD::CONCAT_VECTORS: {
7499 // FIXME: Handle non-power-of-two vectors?
7500 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
7501 if (NewNumSubvectors == 1) {
7502 Lo = Node->getOperand(0);
7503 Hi = Node->getOperand(1);
7505 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7506 Node->op_begin()+NewNumSubvectors);
7507 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
7509 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
7511 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
7515 case ISD::EXTRACT_SUBVECTOR: {
7516 SDValue Vec = Op.getOperand(0);
7517 SDValue Idx = Op.getOperand(1);
7518 MVT IdxVT = Idx.getValueType();
7520 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Lo, Vec, Idx);
7521 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
7523 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec,
7524 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo,
7527 Idx = DAG.getNode(ISD::ADD, IdxVT, Idx,
7528 DAG.getConstant(NewNumElts_Lo, IdxVT));
7529 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec, Idx);
7534 SDValue Cond = Node->getOperand(0);
7536 SDValue LL, LH, RL, RH;
7537 SplitVectorOp(Node->getOperand(1), LL, LH);
7538 SplitVectorOp(Node->getOperand(2), RL, RH);
7540 if (Cond.getValueType().isVector()) {
7541 // Handle a vector merge.
7543 SplitVectorOp(Cond, CL, CH);
7544 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
7545 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
7547 // Handle a simple select with vector operands.
7548 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
7549 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
7553 case ISD::SELECT_CC: {
7554 SDValue CondLHS = Node->getOperand(0);
7555 SDValue CondRHS = Node->getOperand(1);
7556 SDValue CondCode = Node->getOperand(4);
7558 SDValue LL, LH, RL, RH;
7559 SplitVectorOp(Node->getOperand(2), LL, LH);
7560 SplitVectorOp(Node->getOperand(3), RL, RH);
7562 // Handle a simple select with vector operands.
7563 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
7565 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
7570 SDValue LL, LH, RL, RH;
7571 SplitVectorOp(Node->getOperand(0), LL, LH);
7572 SplitVectorOp(Node->getOperand(1), RL, RH);
7573 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
7574 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
7596 SDValue LL, LH, RL, RH;
7597 SplitVectorOp(Node->getOperand(0), LL, LH);
7598 SplitVectorOp(Node->getOperand(1), RL, RH);
7600 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
7601 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
7607 SplitVectorOp(Node->getOperand(0), L, H);
7609 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
7610 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
7626 case ISD::FP_TO_SINT:
7627 case ISD::FP_TO_UINT:
7628 case ISD::SINT_TO_FP:
7629 case ISD::UINT_TO_FP:
7631 case ISD::ANY_EXTEND:
7632 case ISD::SIGN_EXTEND:
7633 case ISD::ZERO_EXTEND:
7634 case ISD::FP_EXTEND: {
7636 SplitVectorOp(Node->getOperand(0), L, H);
7638 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
7639 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
7642 case ISD::CONVERT_RNDSAT: {
7643 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
7645 SplitVectorOp(Node->getOperand(0), L, H);
7646 SDValue DTyOpL = DAG.getValueType(NewVT_Lo);
7647 SDValue DTyOpH = DAG.getValueType(NewVT_Hi);
7648 SDValue STyOpL = DAG.getValueType(L.getValueType());
7649 SDValue STyOpH = DAG.getValueType(H.getValueType());
7651 SDValue RndOp = Node->getOperand(3);
7652 SDValue SatOp = Node->getOperand(4);
7654 Lo = DAG.getConvertRndSat(NewVT_Lo, L, DTyOpL, STyOpL,
7655 RndOp, SatOp, CvtCode);
7656 Hi = DAG.getConvertRndSat(NewVT_Hi, H, DTyOpH, STyOpH,
7657 RndOp, SatOp, CvtCode);
7661 LoadSDNode *LD = cast<LoadSDNode>(Node);
7662 SDValue Ch = LD->getChain();
7663 SDValue Ptr = LD->getBasePtr();
7664 ISD::LoadExtType ExtType = LD->getExtensionType();
7665 const Value *SV = LD->getSrcValue();
7666 int SVOffset = LD->getSrcValueOffset();
7667 MVT MemoryVT = LD->getMemoryVT();
7668 unsigned Alignment = LD->getAlignment();
7669 bool isVolatile = LD->isVolatile();
7671 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7672 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7674 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7675 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7676 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7678 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType,
7679 NewVT_Lo, Ch, Ptr, Offset,
7680 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7681 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7682 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
7683 DAG.getIntPtrConstant(IncrementSize));
7684 SVOffset += IncrementSize;
7685 Alignment = MinAlign(Alignment, IncrementSize);
7686 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType,
7687 NewVT_Hi, Ch, Ptr, Offset,
7688 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7690 // Build a factor node to remember that this load is independent of the
7692 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
7695 // Remember that we legalized the chain.
7696 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7699 case ISD::BIT_CONVERT: {
7700 // We know the result is a vector. The input may be either a vector or a
7702 SDValue InOp = Node->getOperand(0);
7703 if (!InOp.getValueType().isVector() ||
7704 InOp.getValueType().getVectorNumElements() == 1) {
7705 // The input is a scalar or single-element vector.
7706 // Lower to a store/load so that it can be split.
7707 // FIXME: this could be improved probably.
7708 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
7709 Op.getValueType().getTypeForMVT());
7710 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7711 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7713 SDValue St = DAG.getStore(DAG.getEntryNode(),
7715 PseudoSourceValue::getFixedStack(FI), 0);
7716 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
7717 PseudoSourceValue::getFixedStack(FI), 0);
7719 // Split the vector and convert each of the pieces now.
7720 SplitVectorOp(InOp, Lo, Hi);
7721 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
7722 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
7727 // Remember in a map if the values will be reused later.
7729 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7730 assert(isNew && "Value already split?!?");
7735 /// ScalarizeVectorOp - Given an operand of single-element vector type
7736 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7737 /// scalar (e.g. f32) value.
7738 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7739 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7740 SDNode *Node = Op.getNode();
7741 MVT NewVT = Op.getValueType().getVectorElementType();
7742 assert(Op.getValueType().getVectorNumElements() == 1);
7744 // See if we already scalarized it.
7745 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7746 if (I != ScalarizedNodes.end()) return I->second;
7749 switch (Node->getOpcode()) {
7752 Node->dump(&DAG); cerr << "\n";
7754 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7771 Result = DAG.getNode(Node->getOpcode(),
7773 ScalarizeVectorOp(Node->getOperand(0)),
7774 ScalarizeVectorOp(Node->getOperand(1)));
7786 case ISD::FP_TO_SINT:
7787 case ISD::FP_TO_UINT:
7788 case ISD::SINT_TO_FP:
7789 case ISD::UINT_TO_FP:
7790 case ISD::SIGN_EXTEND:
7791 case ISD::ZERO_EXTEND:
7792 case ISD::ANY_EXTEND:
7794 case ISD::FP_EXTEND:
7795 Result = DAG.getNode(Node->getOpcode(),
7797 ScalarizeVectorOp(Node->getOperand(0)));
7799 case ISD::CONVERT_RNDSAT: {
7800 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
7801 Result = DAG.getConvertRndSat(NewVT, Op0,
7802 DAG.getValueType(NewVT),
7803 DAG.getValueType(Op0.getValueType()),
7804 Node->getOperand(3),
7805 Node->getOperand(4),
7806 cast<CvtRndSatSDNode>(Node)->getCvtCode());
7811 Result = DAG.getNode(Node->getOpcode(),
7813 ScalarizeVectorOp(Node->getOperand(0)),
7814 Node->getOperand(1));
7817 LoadSDNode *LD = cast<LoadSDNode>(Node);
7818 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7819 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7820 ISD::LoadExtType ExtType = LD->getExtensionType();
7821 const Value *SV = LD->getSrcValue();
7822 int SVOffset = LD->getSrcValueOffset();
7823 MVT MemoryVT = LD->getMemoryVT();
7824 unsigned Alignment = LD->getAlignment();
7825 bool isVolatile = LD->isVolatile();
7827 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7828 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7830 Result = DAG.getLoad(ISD::UNINDEXED, ExtType,
7831 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7832 MemoryVT.getVectorElementType(),
7833 isVolatile, Alignment);
7835 // Remember that we legalized the chain.
7836 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7839 case ISD::BUILD_VECTOR:
7840 Result = Node->getOperand(0);
7842 case ISD::INSERT_VECTOR_ELT:
7843 // Returning the inserted scalar element.
7844 Result = Node->getOperand(1);
7846 case ISD::CONCAT_VECTORS:
7847 assert(Node->getOperand(0).getValueType() == NewVT &&
7848 "Concat of non-legal vectors not yet supported!");
7849 Result = Node->getOperand(0);
7851 case ISD::VECTOR_SHUFFLE: {
7852 // Figure out if the scalar is the LHS or RHS and return it.
7853 SDValue EltNum = Node->getOperand(2).getOperand(0);
7854 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7855 Result = ScalarizeVectorOp(Node->getOperand(1));
7857 Result = ScalarizeVectorOp(Node->getOperand(0));
7860 case ISD::EXTRACT_SUBVECTOR:
7861 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, Node->getOperand(0),
7862 Node->getOperand(1));
7864 case ISD::BIT_CONVERT: {
7865 SDValue Op0 = Op.getOperand(0);
7866 if (Op0.getValueType().getVectorNumElements() == 1)
7867 Op0 = ScalarizeVectorOp(Op0);
7868 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7872 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7873 ScalarizeVectorOp(Op.getOperand(1)),
7874 ScalarizeVectorOp(Op.getOperand(2)));
7876 case ISD::SELECT_CC:
7877 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
7878 Node->getOperand(1),
7879 ScalarizeVectorOp(Op.getOperand(2)),
7880 ScalarizeVectorOp(Op.getOperand(3)),
7881 Node->getOperand(4));
7884 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7885 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7886 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0.getValueType()),
7887 Op0, Op1, Op.getOperand(2));
7888 Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7889 DAG.getConstant(-1ULL, NewVT),
7890 DAG.getConstant(0ULL, NewVT));
7895 if (TLI.isTypeLegal(NewVT))
7896 Result = LegalizeOp(Result);
7897 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7898 assert(isNew && "Value already scalarized?");
7904 SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
7905 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op);
7906 if (I != WidenNodes.end()) return I->second;
7908 MVT VT = Op.getValueType();
7909 assert(VT.isVector() && "Cannot widen non-vector type!");
7912 SDNode *Node = Op.getNode();
7913 MVT EVT = VT.getVectorElementType();
7915 unsigned NumElts = VT.getVectorNumElements();
7916 unsigned NewNumElts = WidenVT.getVectorNumElements();
7917 assert(NewNumElts > NumElts && "Cannot widen to smaller type!");
7918 assert(NewNumElts < 17);
7920 // When widen is called, it is assumed that it is more efficient to use a
7921 // wide type. The default action is to widen to operation to a wider legal
7922 // vector type and then do the operation if it is legal by calling LegalizeOp
7923 // again. If there is no vector equivalent, we will unroll the operation, do
7924 // it, and rebuild the vector. If most of the operations are vectorizible to
7925 // the legal type, the resulting code will be more efficient. If this is not
7926 // the case, the resulting code will preform badly as we end up generating
7927 // code to pack/unpack the results. It is the function that calls widen
7928 // that is responsible for seeing this doesn't happen.
7929 switch (Node->getOpcode()) {
7934 assert(0 && "Unexpected operation in WidenVectorOp!");
7936 case ISD::CopyFromReg:
7937 assert(0 && "CopyFromReg doesn't need widening!");
7939 case ISD::ConstantFP:
7940 // To build a vector of these elements, clients should call BuildVector
7941 // and with each element instead of creating a node with a vector type
7942 assert(0 && "Unexpected operation in WidenVectorOp!");
7944 // Variable Arguments with vector types doesn't make any sense to me
7945 assert(0 && "Unexpected operation in WidenVectorOp!");
7948 Result = DAG.getNode(ISD::UNDEF, WidenVT);
7950 case ISD::BUILD_VECTOR: {
7951 // Build a vector with undefined for the new nodes
7952 SDValueVector NewOps(Node->op_begin(), Node->op_end());
7953 for (unsigned i = NumElts; i < NewNumElts; ++i) {
7954 NewOps.push_back(DAG.getNode(ISD::UNDEF,EVT));
7956 Result = DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &NewOps[0], NewOps.size());
7959 case ISD::INSERT_VECTOR_ELT: {
7960 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7961 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, WidenVT, Tmp1,
7962 Node->getOperand(1), Node->getOperand(2));
7965 case ISD::VECTOR_SHUFFLE: {
7966 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7967 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
7968 // VECTOR_SHUFFLE 3rd operand must be a constant build vector that is
7969 // used as permutation array. We build the vector here instead of widening
7970 // because we don't want to legalize and have it turned to something else.
7971 SDValue PermOp = Node->getOperand(2);
7972 SDValueVector NewOps;
7973 MVT PVT = PermOp.getValueType().getVectorElementType();
7974 for (unsigned i = 0; i < NumElts; ++i) {
7975 if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) {
7976 NewOps.push_back(PermOp.getOperand(i));
7979 cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue();
7980 if (Idx < NumElts) {
7981 NewOps.push_back(PermOp.getOperand(i));
7984 NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts,
7985 PermOp.getOperand(i).getValueType()));
7989 for (unsigned i = NumElts; i < NewNumElts; ++i) {
7990 NewOps.push_back(DAG.getNode(ISD::UNDEF,PVT));
7993 SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR,
7994 MVT::getVectorVT(PVT, NewOps.size()),
7995 &NewOps[0], NewOps.size());
7997 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, WidenVT, Tmp1, Tmp2, Tmp3);
8001 // If the load widen returns true, we can use a single load for the
8002 // vector. Otherwise, it is returning a token factor for multiple
8005 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT))
8006 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1)));
8008 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0)));
8012 case ISD::BIT_CONVERT: {
8013 SDValue Tmp1 = Node->getOperand(0);
8014 // Converts between two different types so we need to determine
8015 // the correct widen type for the input operand.
8016 MVT InVT = Tmp1.getValueType();
8017 unsigned WidenSize = WidenVT.getSizeInBits();
8018 if (InVT.isVector()) {
8019 MVT InEltVT = InVT.getVectorElementType();
8020 unsigned InEltSize = InEltVT.getSizeInBits();
8021 assert(WidenSize % InEltSize == 0 &&
8022 "can not widen bit convert that are not multiple of element type");
8023 MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize);
8024 Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT);
8025 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
8026 Result = DAG.getNode(ISD::BIT_CONVERT, WidenVT, Tmp1);
8028 // If the result size is a multiple of the input size, widen the input
8029 // and then convert.
8030 unsigned InSize = InVT.getSizeInBits();
8031 assert(WidenSize % InSize == 0 &&
8032 "can not widen bit convert that are not multiple of element type");
8033 unsigned NewNumElts = WidenSize / InSize;
8034 SmallVector<SDValue, 16> Ops(NewNumElts);
8035 SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT);
8037 for (unsigned i = 1; i < NewNumElts; ++i)
8040 MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts);
8041 Result = DAG.getNode(ISD::BUILD_VECTOR, NewInVT, &Ops[0], NewNumElts);
8042 Result = DAG.getNode(ISD::BIT_CONVERT, WidenVT, Result);
8047 case ISD::SINT_TO_FP:
8048 case ISD::UINT_TO_FP:
8049 case ISD::FP_TO_SINT:
8050 case ISD::FP_TO_UINT:
8051 case ISD::FP_ROUND: {
8052 SDValue Tmp1 = Node->getOperand(0);
8053 // Converts between two different types so we need to determine
8054 // the correct widen type for the input operand.
8055 MVT TVT = Tmp1.getValueType();
8056 assert(TVT.isVector() && "can not widen non vector type");
8057 MVT TEVT = TVT.getVectorElementType();
8058 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts);
8059 Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
8060 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts);
8061 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
8065 case ISD::FP_EXTEND:
8066 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
8068 case ISD::SIGN_EXTEND:
8069 case ISD::ZERO_EXTEND:
8070 case ISD::ANY_EXTEND:
8071 case ISD::SIGN_EXTEND_INREG:
8080 // Unary op widening
8082 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8083 assert(Tmp1.getValueType() == WidenVT);
8084 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
8087 case ISD::CONVERT_RNDSAT: {
8088 SDValue RndOp = Node->getOperand(3);
8089 SDValue SatOp = Node->getOperand(4);
8090 SDValue SrcOp = Node->getOperand(0);
8092 // Converts between two different types so we need to determine
8093 // the correct widen type for the input operand.
8094 MVT SVT = SrcOp.getValueType();
8095 assert(SVT.isVector() && "can not widen non vector type");
8096 MVT SEVT = SVT.getVectorElementType();
8097 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts);
8099 SrcOp = WidenVectorOp(SrcOp, SWidenVT);
8100 assert(SrcOp.getValueType() == WidenVT);
8101 SDValue DTyOp = DAG.getValueType(WidenVT);
8102 SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
8103 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
8105 Result = DAG.getConvertRndSat(WidenVT, SrcOp, DTyOp, STyOp,
8106 RndOp, SatOp, CvtCode);
8126 case ISD::FCOPYSIGN:
8130 // Binary op widening
8131 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8132 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8133 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8134 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2);
8141 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8142 assert(Tmp1.getValueType() == WidenVT);
8143 SDValue ShOp = Node->getOperand(1);
8144 MVT ShVT = ShOp.getValueType();
8145 MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(),
8146 WidenVT.getVectorNumElements());
8147 ShOp = WidenVectorOp(ShOp, NewShVT);
8148 assert(ShOp.getValueType() == NewShVT);
8149 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, ShOp);
8153 case ISD::EXTRACT_VECTOR_ELT: {
8154 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8155 assert(Tmp1.getValueType() == WidenVT);
8156 Result = DAG.getNode(Node->getOpcode(), EVT, Tmp1, Node->getOperand(1));
8159 case ISD::CONCAT_VECTORS: {
8160 // We concurrently support only widen on a multiple of the incoming vector.
8161 // We could widen on a multiple of the incoming operand if necessary.
8162 unsigned NumConcat = NewNumElts / NumElts;
8163 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
8164 SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT);
8165 SmallVector<SDValue, 8> MOps;
8167 for (unsigned i = 1; i != NumConcat; ++i) {
8168 MOps.push_back(UndefVal);
8170 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
8171 &MOps[0], MOps.size()));
8174 case ISD::EXTRACT_SUBVECTOR: {
8175 SDValue Tmp1 = Node->getOperand(0);
8176 SDValue Idx = Node->getOperand(1);
8177 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
8178 if (CIdx && CIdx->getZExtValue() == 0) {
8179 // Since we are access the start of the vector, the incoming
8180 // vector type might be the proper.
8181 MVT Tmp1VT = Tmp1.getValueType();
8182 if (Tmp1VT == WidenVT)
8185 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements();
8186 if (Tmp1VTNumElts < NewNumElts)
8187 Result = WidenVectorOp(Tmp1, WidenVT);
8189 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, WidenVT, Tmp1, Idx);
8191 } else if (NewNumElts % NumElts == 0) {
8192 // Widen the extracted subvector.
8193 unsigned NumConcat = NewNumElts / NumElts;
8194 SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT);
8195 SmallVector<SDValue, 8> MOps;
8197 for (unsigned i = 1; i != NumConcat; ++i) {
8198 MOps.push_back(UndefVal);
8200 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
8201 &MOps[0], MOps.size()));
8203 assert(0 && "can not widen extract subvector");
8204 // This could be implemented using insert and build vector but I would
8205 // like to see when this happens.
8211 // Determine new condition widen type and widen
8212 SDValue Cond1 = Node->getOperand(0);
8213 MVT CondVT = Cond1.getValueType();
8214 assert(CondVT.isVector() && "can not widen non vector type");
8215 MVT CondEVT = CondVT.getVectorElementType();
8216 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8217 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8218 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen");
8220 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT);
8221 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT);
8222 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8223 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Tmp1, Tmp2);
8227 case ISD::SELECT_CC: {
8228 // Determine new condition widen type and widen
8229 SDValue Cond1 = Node->getOperand(0);
8230 SDValue Cond2 = Node->getOperand(1);
8231 MVT CondVT = Cond1.getValueType();
8232 assert(CondVT.isVector() && "can not widen non vector type");
8233 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs");
8234 MVT CondEVT = CondVT.getVectorElementType();
8235 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8236 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8237 Cond2 = WidenVectorOp(Cond2, CondWidenVT);
8238 assert(Cond1.getValueType() == CondWidenVT &&
8239 Cond2.getValueType() == CondWidenVT && "condition not widen");
8241 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT);
8242 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT);
8243 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT &&
8244 "operands not widen");
8245 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Cond2, Tmp1,
8246 Tmp2, Node->getOperand(4));
8250 // Determine widen for the operand
8251 SDValue Tmp1 = Node->getOperand(0);
8252 MVT TmpVT = Tmp1.getValueType();
8253 assert(TmpVT.isVector() && "can not widen non vector type");
8254 MVT TmpEVT = TmpVT.getVectorElementType();
8255 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts);
8256 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT);
8257 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT);
8258 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2,
8259 Node->getOperand(2));
8262 case ISD::ATOMIC_CMP_SWAP:
8263 case ISD::ATOMIC_LOAD_ADD:
8264 case ISD::ATOMIC_LOAD_SUB:
8265 case ISD::ATOMIC_LOAD_AND:
8266 case ISD::ATOMIC_LOAD_OR:
8267 case ISD::ATOMIC_LOAD_XOR:
8268 case ISD::ATOMIC_LOAD_NAND:
8269 case ISD::ATOMIC_LOAD_MIN:
8270 case ISD::ATOMIC_LOAD_MAX:
8271 case ISD::ATOMIC_LOAD_UMIN:
8272 case ISD::ATOMIC_LOAD_UMAX:
8273 case ISD::ATOMIC_SWAP: {
8274 // For now, we assume that using vectors for these operations don't make
8275 // much sense so we just split it. We return an empty result
8277 SplitVectorOp(Op, X, Y);
8282 } // end switch (Node->getOpcode())
8284 assert(Result.getNode() && "Didn't set a result!");
8286 Result = LegalizeOp(Result);
8288 AddWidenedOperand(Op, Result);
8292 // Utility function to find a legal vector type and its associated element
8293 // type from a preferred width and whose vector type must be the same size
8295 // TLI: Target lowering used to determine legal types
8296 // Width: Preferred width of element type
8297 // VVT: Vector value type whose size we must match.
8298 // Returns VecEVT and EVT - the vector type and its associated element type
8299 static void FindWidenVecType(TargetLowering &TLI, unsigned Width, MVT VVT,
8300 MVT& EVT, MVT& VecEVT) {
8301 // We start with the preferred width, make it a power of 2 and see if
8302 // we can find a vector type of that width. If not, we reduce it by
8303 // another power of 2. If we have widen the type, a vector of bytes should
8305 assert(TLI.isTypeLegal(VVT));
8306 unsigned EWidth = Width + 1;
8309 EWidth = (1 << Log2_32(EWidth-1));
8310 EVT = MVT::getIntegerVT(EWidth);
8311 unsigned NumEVT = VVT.getSizeInBits()/EWidth;
8312 VecEVT = MVT::getVectorVT(EVT, NumEVT);
8313 } while (!TLI.isTypeLegal(VecEVT) ||
8314 VVT.getSizeInBits() != VecEVT.getSizeInBits());
8317 SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
8326 // We assume that we have good rules to handle loading power of two loads so
8327 // we break down the operations to power of 2 loads. The strategy is to
8328 // load the largest power of 2 that we can easily transform to a legal vector
8329 // and then insert into that vector, and the cast the result into the legal
8330 // vector that we want. This avoids unnecessary stack converts.
8331 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
8332 // the load is nonvolatile, we an use a wider load for the value.
8333 // Find a vector length we can load a large chunk
8336 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8337 EVTWidth = EVT.getSizeInBits();
8339 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV, SVOffset,
8340 isVolatile, Alignment);
8341 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecEVT, LdOp);
8342 LdChain.push_back(LdOp.getValue(1));
8344 // Check if we can load the element with one instruction
8345 if (LdWidth == EVTWidth) {
8346 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
8349 // The vector element order is endianness dependent.
8351 LdWidth -= EVTWidth;
8352 unsigned Offset = 0;
8354 while (LdWidth > 0) {
8355 unsigned Increment = EVTWidth / 8;
8356 Offset += Increment;
8357 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
8358 DAG.getIntPtrConstant(Increment));
8360 if (LdWidth < EVTWidth) {
8361 // Our current type we are using is too large, use a smaller size by
8362 // using a smaller power of 2
8363 unsigned oEVTWidth = EVTWidth;
8364 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8365 EVTWidth = EVT.getSizeInBits();
8366 // Readjust position and vector position based on new load type
8367 Idx = Idx * (oEVTWidth/EVTWidth);
8368 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
8371 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV,
8372 SVOffset+Offset, isVolatile,
8373 MinAlign(Alignment, Offset));
8374 LdChain.push_back(LdOp.getValue(1));
8375 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, VecEVT, VecOp, LdOp,
8376 DAG.getIntPtrConstant(Idx++));
8378 LdWidth -= EVTWidth;
8381 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
8384 bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
8388 // TODO: Add support for ConcatVec and the ability to load many vector
8389 // types (e.g., v4i8). This will not work when a vector register
8390 // to memory mapping is strange (e.g., vector elements are not
8391 // stored in some sequential order).
8393 // It must be true that the widen vector type is bigger than where
8394 // we need to load from.
8395 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
8396 MVT LdVT = LD->getMemoryVT();
8397 assert(LdVT.isVector() && NVT.isVector());
8398 assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
8401 SDValue Chain = LD->getChain();
8402 SDValue BasePtr = LD->getBasePtr();
8403 int SVOffset = LD->getSrcValueOffset();
8404 unsigned Alignment = LD->getAlignment();
8405 bool isVolatile = LD->isVolatile();
8406 const Value *SV = LD->getSrcValue();
8407 unsigned int LdWidth = LdVT.getSizeInBits();
8409 // Load value as a large register
8410 SDValueVector LdChain;
8411 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
8412 Alignment, isVolatile, LdWidth, NVT);
8414 if (LdChain.size() == 1) {
8419 TFOp=DAG.getNode(ISD::TokenFactor, MVT::Other, &LdChain[0], LdChain.size());
8425 void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
8434 // Breaks the stores into a series of power of 2 width stores. For any
8435 // width, we convert the vector to the vector of element size that we
8436 // want to store. This avoids requiring a stack convert.
8438 // Find a width of the element type we can store with
8439 MVT VVT = ValOp.getValueType();
8442 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8443 EVTWidth = EVT.getSizeInBits();
8445 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, ValOp);
8446 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
8447 DAG.getIntPtrConstant(0));
8448 SDValue StOp = DAG.getStore(Chain, EOp, BasePtr, SV, SVOffset,
8449 isVolatile, Alignment);
8450 StChain.push_back(StOp);
8452 // Check if we are done
8453 if (StWidth == EVTWidth) {
8458 StWidth -= EVTWidth;
8459 unsigned Offset = 0;
8461 while (StWidth > 0) {
8462 unsigned Increment = EVTWidth / 8;
8463 Offset += Increment;
8464 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
8465 DAG.getIntPtrConstant(Increment));
8467 if (StWidth < EVTWidth) {
8468 // Our current type we are using is too large, use a smaller size by
8469 // using a smaller power of 2
8470 unsigned oEVTWidth = EVTWidth;
8471 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8472 EVTWidth = EVT.getSizeInBits();
8473 // Readjust position and vector position based on new load type
8474 Idx = Idx * (oEVTWidth/EVTWidth);
8475 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
8478 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
8479 DAG.getIntPtrConstant(Idx++));
8480 StChain.push_back(DAG.getStore(Chain, EOp, BasePtr, SV,
8481 SVOffset + Offset, isVolatile,
8482 MinAlign(Alignment, Offset)));
8483 StWidth -= EVTWidth;
8488 SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
8491 // TODO: It might be cleaner if we can use SplitVector and have more legal
8492 // vector types that can be stored into memory (e.g., v4xi8 can
8493 // be stored as a word). This will not work when a vector register
8494 // to memory mapping is strange (e.g., vector elements are not
8495 // stored in some sequential order).
8497 MVT StVT = ST->getMemoryVT();
8498 SDValue ValOp = ST->getValue();
8500 // Check if we have widen this node with another value
8501 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
8502 if (I != WidenNodes.end())
8505 MVT VVT = ValOp.getValueType();
8507 // It must be true that we the widen vector type is bigger than where
8508 // we need to store.
8509 assert(StVT.isVector() && VVT.isVector());
8510 assert(StVT.getSizeInBits() < VVT.getSizeInBits());
8511 assert(StVT.getVectorElementType() == VVT.getVectorElementType());
8514 SDValueVector StChain;
8515 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(),
8516 ST->getSrcValueOffset(), ST->getAlignment(),
8517 ST->isVolatile(), ValOp, StVT.getSizeInBits());
8518 if (StChain.size() == 1)
8521 return DAG.getNode(ISD::TokenFactor, MVT::Other,&StChain[0],StChain.size());
8525 // SelectionDAG::Legalize - This is the entry point for the file.
8527 void SelectionDAG::Legalize(bool TypesNeedLegalizing) {
8528 /// run - This is the main entry point to this class.
8530 SelectionDAGLegalize(*this, TypesNeedLegalizing).LegalizeDAG();