1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/DwarfWriter.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetSubtarget.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/DerivedTypes.h"
31 #include "llvm/Function.h"
32 #include "llvm/GlobalVariable.h"
33 #include "llvm/LLVMContext.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/ADT/DenseMap.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/ADT/SmallPtrSet.h"
44 //===----------------------------------------------------------------------===//
45 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
46 /// hacks on it until the target machine can handle it. This involves
47 /// eliminating value sizes the machine cannot handle (promoting small sizes to
48 /// large sizes or splitting up large values into small values) as well as
49 /// eliminating operations the machine cannot handle.
51 /// This code also does a small amount of optimization and recognition of idioms
52 /// as part of its processing. For example, if a target does not support a
53 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
54 /// will attempt merge setcc and brc instructions into brcc's.
57 class SelectionDAGLegalize {
60 CodeGenOpt::Level OptLevel;
62 // Libcall insertion helpers.
64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
65 /// legalized. We use this to ensure that calls are properly serialized
66 /// against each other, including inserted libcalls.
67 SDValue LastCALLSEQ_END;
69 /// IsLegalizingCall - This member is used *only* for purposes of providing
70 /// helpful assertions that a libcall isn't created while another call is
71 /// being legalized (which could lead to non-serialized call sequences).
72 bool IsLegalizingCall;
75 Legal, // The target natively supports this operation.
76 Promote, // This operation should be executed in a larger type.
77 Expand // Try to expand this to other ops, otherwise use a libcall.
80 /// ValueTypeActions - This is a bitvector that contains two bits for each
81 /// value type, where the two bits correspond to the LegalizeAction enum.
82 /// This can be queried with "getTypeAction(VT)".
83 TargetLowering::ValueTypeActionImpl ValueTypeActions;
85 /// LegalizedNodes - For nodes that are of legal width, and that have more
86 /// than one use, this map indicates what regularized operand to use. This
87 /// allows us to avoid legalizing the same thing more than once.
88 DenseMap<SDValue, SDValue> LegalizedNodes;
90 void AddLegalizedOperand(SDValue From, SDValue To) {
91 LegalizedNodes.insert(std::make_pair(From, To));
92 // If someone requests legalization of the new node, return itself.
94 LegalizedNodes.insert(std::make_pair(To, To));
98 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol);
100 /// getTypeAction - Return how we should legalize values of this type, either
101 /// it is already legal or we need to expand it into multiple registers of
102 /// smaller integer type, or we need to promote it to a larger type.
103 LegalizeAction getTypeAction(EVT VT) const {
105 (LegalizeAction)ValueTypeActions.getTypeAction(*DAG.getContext(), VT);
108 /// isTypeLegal - Return true if this type is legal on this target.
110 bool isTypeLegal(EVT VT) const {
111 return getTypeAction(VT) == Legal;
117 /// LegalizeOp - We know that the specified value has a legal type.
118 /// Recursively ensure that the operands have legal types, then return the
120 SDValue LegalizeOp(SDValue O);
122 SDValue OptimizeFloatStore(StoreSDNode *ST);
124 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
125 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
126 /// is necessary to spill the vector being inserted into to memory, perform
127 /// the insert there, and then read the result back.
128 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
129 SDValue Idx, DebugLoc dl);
130 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
131 SDValue Idx, DebugLoc dl);
133 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
134 /// performs the same shuffe in terms of order or result bytes, but on a type
135 /// whose vector element type is narrower than the original shuffle type.
136 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
137 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
138 SDValue N1, SDValue N2,
139 SmallVectorImpl<int> &Mask) const;
141 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
142 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
144 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
147 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
148 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
149 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
150 RTLIB::Libcall Call_PPCF128);
151 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
152 RTLIB::Libcall Call_I8,
153 RTLIB::Libcall Call_I16,
154 RTLIB::Libcall Call_I32,
155 RTLIB::Libcall Call_I64,
156 RTLIB::Libcall Call_I128);
158 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
159 SDValue ExpandBUILD_VECTOR(SDNode *Node);
160 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
161 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
162 SmallVectorImpl<SDValue> &Results);
163 SDValue ExpandFCOPYSIGN(SDNode *Node);
164 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
166 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
168 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
171 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
172 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
174 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
175 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
177 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
178 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
182 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
183 /// performs the same shuffe in terms of order or result bytes, but on a type
184 /// whose vector element type is narrower than the original shuffle type.
185 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
187 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
188 SDValue N1, SDValue N2,
189 SmallVectorImpl<int> &Mask) const {
190 unsigned NumMaskElts = VT.getVectorNumElements();
191 unsigned NumDestElts = NVT.getVectorNumElements();
192 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
194 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
196 if (NumEltsGrowth == 1)
197 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
199 SmallVector<int, 8> NewMask;
200 for (unsigned i = 0; i != NumMaskElts; ++i) {
202 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
204 NewMask.push_back(-1);
206 NewMask.push_back(Idx * NumEltsGrowth + j);
209 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
210 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
211 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
214 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
215 CodeGenOpt::Level ol)
216 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
217 ValueTypeActions(TLI.getValueTypeActions()) {
218 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
219 "Too many value types for ValueTypeActions to hold!");
222 void SelectionDAGLegalize::LegalizeDAG() {
223 LastCALLSEQ_END = DAG.getEntryNode();
224 IsLegalizingCall = false;
226 // The legalize process is inherently a bottom-up recursive process (users
227 // legalize their uses before themselves). Given infinite stack space, we
228 // could just start legalizing on the root and traverse the whole graph. In
229 // practice however, this causes us to run out of stack space on large basic
230 // blocks. To avoid this problem, compute an ordering of the nodes where each
231 // node is only legalized after all of its operands are legalized.
232 DAG.AssignTopologicalOrder();
233 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
234 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
235 LegalizeOp(SDValue(I, 0));
237 // Finally, it's possible the root changed. Get the new root.
238 SDValue OldRoot = DAG.getRoot();
239 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
240 DAG.setRoot(LegalizedNodes[OldRoot]);
242 LegalizedNodes.clear();
244 // Remove dead nodes now.
245 DAG.RemoveDeadNodes();
249 /// FindCallEndFromCallStart - Given a chained node that is part of a call
250 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
251 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
252 if (Node->getOpcode() == ISD::CALLSEQ_END)
254 if (Node->use_empty())
255 return 0; // No CallSeqEnd
257 // The chain is usually at the end.
258 SDValue TheChain(Node, Node->getNumValues()-1);
259 if (TheChain.getValueType() != MVT::Other) {
260 // Sometimes it's at the beginning.
261 TheChain = SDValue(Node, 0);
262 if (TheChain.getValueType() != MVT::Other) {
263 // Otherwise, hunt for it.
264 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
265 if (Node->getValueType(i) == MVT::Other) {
266 TheChain = SDValue(Node, i);
270 // Otherwise, we walked into a node without a chain.
271 if (TheChain.getValueType() != MVT::Other)
276 for (SDNode::use_iterator UI = Node->use_begin(),
277 E = Node->use_end(); UI != E; ++UI) {
279 // Make sure to only follow users of our token chain.
281 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
282 if (User->getOperand(i) == TheChain)
283 if (SDNode *Result = FindCallEndFromCallStart(User))
289 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
290 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
291 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
292 assert(Node && "Didn't find callseq_start for a call??");
293 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
295 assert(Node->getOperand(0).getValueType() == MVT::Other &&
296 "Node doesn't have a token chain argument!");
297 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
300 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
301 /// see if any uses can reach Dest. If no dest operands can get to dest,
302 /// legalize them, legalize ourself, and return false, otherwise, return true.
304 /// Keep track of the nodes we fine that actually do lead to Dest in
305 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
307 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
308 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
309 if (N == Dest) return true; // N certainly leads to Dest :)
311 // If we've already processed this node and it does lead to Dest, there is no
312 // need to reprocess it.
313 if (NodesLeadingTo.count(N)) return true;
315 // If the first result of this node has been already legalized, then it cannot
317 if (LegalizedNodes.count(SDValue(N, 0))) return false;
319 // Okay, this node has not already been legalized. Check and legalize all
320 // operands. If none lead to Dest, then we can legalize this node.
321 bool OperandsLeadToDest = false;
322 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
323 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
324 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
326 if (OperandsLeadToDest) {
327 NodesLeadingTo.insert(N);
331 // Okay, this node looks safe, legalize it and return false.
332 LegalizeOp(SDValue(N, 0));
336 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
337 /// a load from the constant pool.
338 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
339 SelectionDAG &DAG, const TargetLowering &TLI) {
341 DebugLoc dl = CFP->getDebugLoc();
343 // If a FP immediate is precise when represented as a float and if the
344 // target can do an extending load from float to double, we put it into
345 // the constant pool as a float, even if it's is statically typed as a
346 // double. This shrinks FP constants and canonicalizes them for targets where
347 // an FP extending load is the same cost as a normal load (such as on the x87
348 // fp stack or PPC FP unit).
349 EVT VT = CFP->getValueType(0);
350 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
352 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
353 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
354 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
359 while (SVT != MVT::f32) {
360 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
361 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
362 // Only do this if the target has a native EXTLOAD instruction from
364 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
365 TLI.ShouldShrinkFPConstant(OrigVT)) {
366 const Type *SType = SVT.getTypeForEVT(*DAG.getContext());
367 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
373 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
374 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
376 return DAG.getExtLoad(ISD::EXTLOAD, dl,
377 OrigVT, DAG.getEntryNode(),
378 CPIdx, PseudoSourceValue::getConstantPool(),
379 0, VT, false, Alignment);
380 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
381 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
384 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
386 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
387 const TargetLowering &TLI) {
388 SDValue Chain = ST->getChain();
389 SDValue Ptr = ST->getBasePtr();
390 SDValue Val = ST->getValue();
391 EVT VT = Val.getValueType();
392 int Alignment = ST->getAlignment();
393 int SVOffset = ST->getSrcValueOffset();
394 DebugLoc dl = ST->getDebugLoc();
395 if (ST->getMemoryVT().isFloatingPoint() ||
396 ST->getMemoryVT().isVector()) {
397 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
398 if (TLI.isTypeLegal(intVT)) {
399 // Expand to a bitconvert of the value to the integer type of the
400 // same size, then a (misaligned) int store.
401 // FIXME: Does not handle truncating floating point stores!
402 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
403 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
404 SVOffset, ST->isVolatile(), Alignment);
406 // Do a (aligned) store to a stack slot, then copy from the stack slot
407 // to the final destination using (unaligned) integer loads and stores.
408 EVT StoredVT = ST->getMemoryVT();
410 TLI.getRegisterType(*DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(), StoredVT.getSizeInBits()));
411 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
412 unsigned RegBytes = RegVT.getSizeInBits() / 8;
413 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
415 // Make sure the stack slot is also aligned for the register type.
416 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
418 // Perform the original store, only redirected to the stack slot.
419 SDValue Store = DAG.getTruncStore(Chain, dl,
420 Val, StackPtr, NULL, 0, StoredVT);
421 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
422 SmallVector<SDValue, 8> Stores;
425 // Do all but one copies using the full register width.
426 for (unsigned i = 1; i < NumRegs; i++) {
427 // Load one integer register's worth from the stack slot.
428 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0);
429 // Store it to the final location. Remember the store.
430 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
431 ST->getSrcValue(), SVOffset + Offset,
433 MinAlign(ST->getAlignment(), Offset)));
434 // Increment the pointers.
436 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
438 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
441 // The last store may be partial. Do a truncating store. On big-endian
442 // machines this requires an extending load from the stack slot to ensure
443 // that the bits are in the right place.
444 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (StoredBytes - Offset));
446 // Load from the stack slot.
447 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
450 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
451 ST->getSrcValue(), SVOffset + Offset,
452 MemVT, ST->isVolatile(),
453 MinAlign(ST->getAlignment(), Offset)));
454 // The order of the stores doesn't matter - say it with a TokenFactor.
455 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
459 assert(ST->getMemoryVT().isInteger() &&
460 !ST->getMemoryVT().isVector() &&
461 "Unaligned store of unknown type.");
462 // Get the half-size VT
463 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
464 int NumBits = NewStoredVT.getSizeInBits();
465 int IncrementSize = NumBits / 8;
467 // Divide the stored value in two parts.
468 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
470 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
472 // Store the two parts
473 SDValue Store1, Store2;
474 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
475 ST->getSrcValue(), SVOffset, NewStoredVT,
476 ST->isVolatile(), Alignment);
477 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
478 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
479 Alignment = MinAlign(Alignment, IncrementSize);
480 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
481 ST->getSrcValue(), SVOffset + IncrementSize,
482 NewStoredVT, ST->isVolatile(), Alignment);
484 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
487 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
489 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
490 const TargetLowering &TLI) {
491 int SVOffset = LD->getSrcValueOffset();
492 SDValue Chain = LD->getChain();
493 SDValue Ptr = LD->getBasePtr();
494 EVT VT = LD->getValueType(0);
495 EVT LoadedVT = LD->getMemoryVT();
496 DebugLoc dl = LD->getDebugLoc();
497 if (VT.isFloatingPoint() || VT.isVector()) {
498 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
499 if (TLI.isTypeLegal(intVT)) {
500 // Expand to a (misaligned) integer load of the same size,
501 // then bitconvert to floating point or vector.
502 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
503 SVOffset, LD->isVolatile(),
505 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
506 if (VT.isFloatingPoint() && LoadedVT != VT)
507 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
509 SDValue Ops[] = { Result, Chain };
510 return DAG.getMergeValues(Ops, 2, dl);
512 // Copy the value to a (aligned) stack slot using (unaligned) integer
513 // loads and stores, then do a (aligned) load from the stack slot.
514 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
515 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
516 unsigned RegBytes = RegVT.getSizeInBits() / 8;
517 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
519 // Make sure the stack slot is also aligned for the register type.
520 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
522 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
523 SmallVector<SDValue, 8> Stores;
524 SDValue StackPtr = StackBase;
527 // Do all but one copies using the full register width.
528 for (unsigned i = 1; i < NumRegs; i++) {
529 // Load one integer register's worth from the original location.
530 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
531 SVOffset + Offset, LD->isVolatile(),
532 MinAlign(LD->getAlignment(), Offset));
533 // Follow the load with a store to the stack slot. Remember the store.
534 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
536 // Increment the pointers.
538 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
539 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
543 // The last copy may be partial. Do an extending load.
544 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (LoadedBytes - Offset));
545 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
546 LD->getSrcValue(), SVOffset + Offset,
547 MemVT, LD->isVolatile(),
548 MinAlign(LD->getAlignment(), Offset));
549 // Follow the load with a store to the stack slot. Remember the store.
550 // On big-endian machines this requires a truncating store to ensure
551 // that the bits end up in the right place.
552 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
555 // The order of the stores doesn't matter - say it with a TokenFactor.
556 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
559 // Finally, perform the original load only redirected to the stack slot.
560 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
563 // Callers expect a MERGE_VALUES node.
564 SDValue Ops[] = { Load, TF };
565 return DAG.getMergeValues(Ops, 2, dl);
568 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
569 "Unaligned load of unsupported type.");
571 // Compute the new VT that is half the size of the old one. This is an
573 unsigned NumBits = LoadedVT.getSizeInBits();
575 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
578 unsigned Alignment = LD->getAlignment();
579 unsigned IncrementSize = NumBits / 8;
580 ISD::LoadExtType HiExtType = LD->getExtensionType();
582 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
583 if (HiExtType == ISD::NON_EXTLOAD)
584 HiExtType = ISD::ZEXTLOAD;
586 // Load the value in two parts
588 if (TLI.isLittleEndian()) {
589 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
590 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
591 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
592 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
593 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
594 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
595 MinAlign(Alignment, IncrementSize));
597 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
598 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
599 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
600 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
601 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
602 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
603 MinAlign(Alignment, IncrementSize));
606 // aggregate the two parts
607 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
608 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
609 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
611 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
614 SDValue Ops[] = { Result, TF };
615 return DAG.getMergeValues(Ops, 2, dl);
618 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
619 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
620 /// is necessary to spill the vector being inserted into to memory, perform
621 /// the insert there, and then read the result back.
622 SDValue SelectionDAGLegalize::
623 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
629 // If the target doesn't support this, we have to spill the input vector
630 // to a temporary stack slot, update the element, then reload it. This is
631 // badness. We could also load the value into a vector register (either
632 // with a "move to register" or "extload into register" instruction, then
633 // permute it into place, if the idx is a constant and if the idx is
634 // supported by the target.
635 EVT VT = Tmp1.getValueType();
636 EVT EltVT = VT.getVectorElementType();
637 EVT IdxVT = Tmp3.getValueType();
638 EVT PtrVT = TLI.getPointerTy();
639 SDValue StackPtr = DAG.CreateStackTemporary(VT);
641 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
644 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
645 PseudoSourceValue::getFixedStack(SPFI), 0);
647 // Truncate or zero extend offset to target pointer type.
648 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
649 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
650 // Add the offset to the index.
651 unsigned EltSize = EltVT.getSizeInBits()/8;
652 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
653 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
654 // Store the scalar value.
655 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
656 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
657 // Load the updated vector.
658 return DAG.getLoad(VT, dl, Ch, StackPtr,
659 PseudoSourceValue::getFixedStack(SPFI), 0);
663 SDValue SelectionDAGLegalize::
664 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
665 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
666 // SCALAR_TO_VECTOR requires that the type of the value being inserted
667 // match the element type of the vector being created, except for
668 // integers in which case the inserted value can be over width.
669 EVT EltVT = Vec.getValueType().getVectorElementType();
670 if (Val.getValueType() == EltVT ||
671 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
672 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
673 Vec.getValueType(), Val);
675 unsigned NumElts = Vec.getValueType().getVectorNumElements();
676 // We generate a shuffle of InVec and ScVec, so the shuffle mask
677 // should be 0,1,2,3,4,5... with the appropriate element replaced with
679 SmallVector<int, 8> ShufOps;
680 for (unsigned i = 0; i != NumElts; ++i)
681 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
683 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
687 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
690 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
691 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
692 // FIXME: We shouldn't do this for TargetConstantFP's.
693 // FIXME: move this to the DAG Combiner! Note that we can't regress due
694 // to phase ordering between legalized code and the dag combiner. This
695 // probably means that we need to integrate dag combiner and legalizer
697 // We generally can't do this one for long doubles.
698 SDValue Tmp1 = ST->getChain();
699 SDValue Tmp2 = ST->getBasePtr();
701 int SVOffset = ST->getSrcValueOffset();
702 unsigned Alignment = ST->getAlignment();
703 bool isVolatile = ST->isVolatile();
704 DebugLoc dl = ST->getDebugLoc();
705 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
706 if (CFP->getValueType(0) == MVT::f32 &&
707 getTypeAction(MVT::i32) == Legal) {
708 Tmp3 = DAG.getConstant(CFP->getValueAPF().
709 bitcastToAPInt().zextOrTrunc(32),
711 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
712 SVOffset, isVolatile, Alignment);
713 } else if (CFP->getValueType(0) == MVT::f64) {
714 // If this target supports 64-bit registers, do a single 64-bit store.
715 if (getTypeAction(MVT::i64) == Legal) {
716 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
717 zextOrTrunc(64), MVT::i64);
718 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
719 SVOffset, isVolatile, Alignment);
720 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
721 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
722 // stores. If the target supports neither 32- nor 64-bits, this
723 // xform is certainly not worth it.
724 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
725 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
726 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
727 if (TLI.isBigEndian()) std::swap(Lo, Hi);
729 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
730 SVOffset, isVolatile, Alignment);
731 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
732 DAG.getIntPtrConstant(4));
733 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
734 isVolatile, MinAlign(Alignment, 4U));
736 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
743 /// LegalizeOp - We know that the specified value has a legal type, and
744 /// that its operands are legal. Now ensure that the operation itself
745 /// is legal, recursively ensuring that the operands' operations remain
747 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
748 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
751 SDNode *Node = Op.getNode();
752 DebugLoc dl = Node->getDebugLoc();
754 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
755 assert(getTypeAction(Node->getValueType(i)) == Legal &&
756 "Unexpected illegal type!");
758 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
759 assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
760 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
761 "Unexpected illegal type!");
763 // Note that LegalizeOp may be reentered even from single-use nodes, which
764 // means that we always must cache transformed nodes.
765 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
766 if (I != LegalizedNodes.end()) return I->second;
768 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
770 bool isCustom = false;
772 // Figure out the correct action; the way to query this varies by opcode
773 TargetLowering::LegalizeAction Action;
774 bool SimpleFinishLegalizing = true;
775 switch (Node->getOpcode()) {
776 case ISD::INTRINSIC_W_CHAIN:
777 case ISD::INTRINSIC_WO_CHAIN:
778 case ISD::INTRINSIC_VOID:
781 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
783 case ISD::SINT_TO_FP:
784 case ISD::UINT_TO_FP:
785 case ISD::EXTRACT_VECTOR_ELT:
786 Action = TLI.getOperationAction(Node->getOpcode(),
787 Node->getOperand(0).getValueType());
789 case ISD::FP_ROUND_INREG:
790 case ISD::SIGN_EXTEND_INREG: {
791 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
792 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
798 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
799 Node->getOpcode() == ISD::SETCC ? 2 : 1;
800 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
801 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
802 ISD::CondCode CCCode =
803 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
804 Action = TLI.getCondCodeAction(CCCode, OpVT);
805 if (Action == TargetLowering::Legal) {
806 if (Node->getOpcode() == ISD::SELECT_CC)
807 Action = TLI.getOperationAction(Node->getOpcode(),
808 Node->getValueType(0));
810 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
816 // FIXME: Model these properly. LOAD and STORE are complicated, and
817 // STORE expects the unlegalized operand in some cases.
818 SimpleFinishLegalizing = false;
820 case ISD::CALLSEQ_START:
821 case ISD::CALLSEQ_END:
822 // FIXME: This shouldn't be necessary. These nodes have special properties
823 // dealing with the recursive nature of legalization. Removing this
824 // special case should be done as part of making LegalizeDAG non-recursive.
825 SimpleFinishLegalizing = false;
827 case ISD::EXTRACT_ELEMENT:
828 case ISD::FLT_ROUNDS_:
836 case ISD::MERGE_VALUES:
838 case ISD::FRAME_TO_ARGS_OFFSET:
839 // These operations lie about being legal: when they claim to be legal,
840 // they should actually be expanded.
841 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
842 if (Action == TargetLowering::Legal)
843 Action = TargetLowering::Expand;
845 case ISD::TRAMPOLINE:
847 case ISD::RETURNADDR:
848 // These operations lie about being legal: when they claim to be legal,
849 // they should actually be custom-lowered.
850 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
851 if (Action == TargetLowering::Legal)
852 Action = TargetLowering::Custom;
854 case ISD::BUILD_VECTOR:
855 // A weird case: legalization for BUILD_VECTOR never legalizes the
857 // FIXME: This really sucks... changing it isn't semantically incorrect,
858 // but it massively pessimizes the code for floating-point BUILD_VECTORs
859 // because ConstantFP operands get legalized into constant pool loads
860 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
861 // though, because BUILD_VECTORS usually get lowered into other nodes
862 // which get legalized properly.
863 SimpleFinishLegalizing = false;
866 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
867 Action = TargetLowering::Legal;
869 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
874 if (SimpleFinishLegalizing) {
875 SmallVector<SDValue, 8> Ops, ResultVals;
876 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
877 Ops.push_back(LegalizeOp(Node->getOperand(i)));
878 switch (Node->getOpcode()) {
885 // Branches tweak the chain to include LastCALLSEQ_END
886 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
888 Ops[0] = LegalizeOp(Ops[0]);
889 LastCALLSEQ_END = DAG.getEntryNode();
896 // Legalizing shifts/rotates requires adjusting the shift amount
897 // to the appropriate width.
898 if (!Ops[1].getValueType().isVector())
899 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1]));
904 // Legalizing shifts/rotates requires adjusting the shift amount
905 // to the appropriate width.
906 if (!Ops[2].getValueType().isVector())
907 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2]));
911 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(),
914 case TargetLowering::Legal:
915 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
916 ResultVals.push_back(Result.getValue(i));
918 case TargetLowering::Custom:
919 // FIXME: The handling for custom lowering with multiple results is
921 Tmp1 = TLI.LowerOperation(Result, DAG);
922 if (Tmp1.getNode()) {
923 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
925 ResultVals.push_back(Tmp1);
927 ResultVals.push_back(Tmp1.getValue(i));
933 case TargetLowering::Expand:
934 ExpandNode(Result.getNode(), ResultVals);
936 case TargetLowering::Promote:
937 PromoteNode(Result.getNode(), ResultVals);
940 if (!ResultVals.empty()) {
941 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
942 if (ResultVals[i] != SDValue(Node, i))
943 ResultVals[i] = LegalizeOp(ResultVals[i]);
944 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
946 return ResultVals[Op.getResNo()];
950 switch (Node->getOpcode()) {
957 llvm_unreachable("Do not know how to legalize this operator!");
959 case ISD::BUILD_VECTOR:
960 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
961 default: llvm_unreachable("This action is not supported yet!");
962 case TargetLowering::Custom:
963 Tmp3 = TLI.LowerOperation(Result, DAG);
964 if (Tmp3.getNode()) {
969 case TargetLowering::Expand:
970 Result = ExpandBUILD_VECTOR(Result.getNode());
974 case ISD::CALLSEQ_START: {
975 SDNode *CallEnd = FindCallEndFromCallStart(Node);
977 // Recursively Legalize all of the inputs of the call end that do not lead
978 // to this call start. This ensures that any libcalls that need be inserted
979 // are inserted *before* the CALLSEQ_START.
980 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
981 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
982 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
986 // Now that we legalized all of the inputs (which may have inserted
987 // libcalls) create the new CALLSEQ_START node.
988 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
990 // Merge in the last call, to ensure that this call start after the last
992 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
993 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
994 Tmp1, LastCALLSEQ_END);
995 Tmp1 = LegalizeOp(Tmp1);
998 // Do not try to legalize the target-specific arguments (#1+).
999 if (Tmp1 != Node->getOperand(0)) {
1000 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1002 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1005 // Remember that the CALLSEQ_START is legalized.
1006 AddLegalizedOperand(Op.getValue(0), Result);
1007 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1008 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1010 // Now that the callseq_start and all of the non-call nodes above this call
1011 // sequence have been legalized, legalize the call itself. During this
1012 // process, no libcalls can/will be inserted, guaranteeing that no calls
1014 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1015 // Note that we are selecting this call!
1016 LastCALLSEQ_END = SDValue(CallEnd, 0);
1017 IsLegalizingCall = true;
1019 // Legalize the call, starting from the CALLSEQ_END.
1020 LegalizeOp(LastCALLSEQ_END);
1021 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1024 case ISD::CALLSEQ_END:
1025 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1026 // will cause this node to be legalized as well as handling libcalls right.
1027 if (LastCALLSEQ_END.getNode() != Node) {
1028 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1029 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1030 assert(I != LegalizedNodes.end() &&
1031 "Legalizing the call start should have legalized this node!");
1035 // Otherwise, the call start has been legalized and everything is going
1036 // according to plan. Just legalize ourselves normally here.
1037 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1038 // Do not try to legalize the target-specific arguments (#1+), except for
1039 // an optional flag input.
1040 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1041 if (Tmp1 != Node->getOperand(0)) {
1042 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1044 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1047 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1048 if (Tmp1 != Node->getOperand(0) ||
1049 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1050 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1053 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1056 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1057 // This finishes up call legalization.
1058 IsLegalizingCall = false;
1060 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1061 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1062 if (Node->getNumValues() == 2)
1063 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1064 return Result.getValue(Op.getResNo());
1066 LoadSDNode *LD = cast<LoadSDNode>(Node);
1067 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1068 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1070 ISD::LoadExtType ExtType = LD->getExtensionType();
1071 if (ExtType == ISD::NON_EXTLOAD) {
1072 EVT VT = Node->getValueType(0);
1073 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1074 Tmp3 = Result.getValue(0);
1075 Tmp4 = Result.getValue(1);
1077 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1078 default: llvm_unreachable("This action is not supported yet!");
1079 case TargetLowering::Legal:
1080 // If this is an unaligned load and the target doesn't support it,
1082 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1083 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1084 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1085 if (LD->getAlignment() < ABIAlignment){
1086 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1088 Tmp3 = Result.getOperand(0);
1089 Tmp4 = Result.getOperand(1);
1090 Tmp3 = LegalizeOp(Tmp3);
1091 Tmp4 = LegalizeOp(Tmp4);
1095 case TargetLowering::Custom:
1096 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1097 if (Tmp1.getNode()) {
1098 Tmp3 = LegalizeOp(Tmp1);
1099 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1102 case TargetLowering::Promote: {
1103 // Only promote a load of vector type to another.
1104 assert(VT.isVector() && "Cannot promote this load!");
1105 // Change base type to a different vector type.
1106 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1108 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1109 LD->getSrcValueOffset(),
1110 LD->isVolatile(), LD->getAlignment());
1111 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
1112 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1116 // Since loads produce two values, make sure to remember that we
1117 // legalized both of them.
1118 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1119 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1120 return Op.getResNo() ? Tmp4 : Tmp3;
1122 EVT SrcVT = LD->getMemoryVT();
1123 unsigned SrcWidth = SrcVT.getSizeInBits();
1124 int SVOffset = LD->getSrcValueOffset();
1125 unsigned Alignment = LD->getAlignment();
1126 bool isVolatile = LD->isVolatile();
1128 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1129 // Some targets pretend to have an i1 loading operation, and actually
1130 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1131 // bits are guaranteed to be zero; it helps the optimizers understand
1132 // that these bits are zero. It is also useful for EXTLOAD, since it
1133 // tells the optimizers that those bits are undefined. It would be
1134 // nice to have an effective generic way of getting these benefits...
1135 // Until such a way is found, don't insist on promoting i1 here.
1136 (SrcVT != MVT::i1 ||
1137 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1138 // Promote to a byte-sized load if not loading an integral number of
1139 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1140 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1141 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
1144 // The extra bits are guaranteed to be zero, since we stored them that
1145 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1147 ISD::LoadExtType NewExtType =
1148 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1150 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
1151 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1152 NVT, isVolatile, Alignment);
1154 Ch = Result.getValue(1); // The chain.
1156 if (ExtType == ISD::SEXTLOAD)
1157 // Having the top bits zero doesn't help when sign extending.
1158 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1159 Result.getValueType(),
1160 Result, DAG.getValueType(SrcVT));
1161 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1162 // All the top bits are guaranteed to be zero - inform the optimizers.
1163 Result = DAG.getNode(ISD::AssertZext, dl,
1164 Result.getValueType(), Result,
1165 DAG.getValueType(SrcVT));
1167 Tmp1 = LegalizeOp(Result);
1168 Tmp2 = LegalizeOp(Ch);
1169 } else if (SrcWidth & (SrcWidth - 1)) {
1170 // If not loading a power-of-2 number of bits, expand as two loads.
1171 assert(!SrcVT.isVector() && "Unsupported extload!");
1172 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1173 assert(RoundWidth < SrcWidth);
1174 unsigned ExtraWidth = SrcWidth - RoundWidth;
1175 assert(ExtraWidth < RoundWidth);
1176 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1177 "Load size not an integral number of bytes!");
1178 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1179 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1181 unsigned IncrementSize;
1183 if (TLI.isLittleEndian()) {
1184 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1185 // Load the bottom RoundWidth bits.
1186 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
1187 Node->getValueType(0), Tmp1, Tmp2,
1188 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1191 // Load the remaining ExtraWidth bits.
1192 IncrementSize = RoundWidth / 8;
1193 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1194 DAG.getIntPtrConstant(IncrementSize));
1195 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1196 LD->getSrcValue(), SVOffset + IncrementSize,
1197 ExtraVT, isVolatile,
1198 MinAlign(Alignment, IncrementSize));
1200 // Build a factor node to remember that this load is independent of the
1202 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1205 // Move the top bits to the right place.
1206 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1207 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1209 // Join the hi and lo parts.
1210 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1212 // Big endian - avoid unaligned loads.
1213 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1214 // Load the top RoundWidth bits.
1215 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1216 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1219 // Load the remaining ExtraWidth bits.
1220 IncrementSize = RoundWidth / 8;
1221 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1222 DAG.getIntPtrConstant(IncrementSize));
1223 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
1224 Node->getValueType(0), Tmp1, Tmp2,
1225 LD->getSrcValue(), SVOffset + IncrementSize,
1226 ExtraVT, isVolatile,
1227 MinAlign(Alignment, IncrementSize));
1229 // Build a factor node to remember that this load is independent of the
1231 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1234 // Move the top bits to the right place.
1235 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1236 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1238 // Join the hi and lo parts.
1239 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1242 Tmp1 = LegalizeOp(Result);
1243 Tmp2 = LegalizeOp(Ch);
1245 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1246 default: llvm_unreachable("This action is not supported yet!");
1247 case TargetLowering::Custom:
1250 case TargetLowering::Legal:
1251 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1252 Tmp1 = Result.getValue(0);
1253 Tmp2 = Result.getValue(1);
1256 Tmp3 = TLI.LowerOperation(Result, DAG);
1257 if (Tmp3.getNode()) {
1258 Tmp1 = LegalizeOp(Tmp3);
1259 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1262 // If this is an unaligned load and the target doesn't support it,
1264 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1265 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1266 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1267 if (LD->getAlignment() < ABIAlignment){
1268 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1270 Tmp1 = Result.getOperand(0);
1271 Tmp2 = Result.getOperand(1);
1272 Tmp1 = LegalizeOp(Tmp1);
1273 Tmp2 = LegalizeOp(Tmp2);
1278 case TargetLowering::Expand:
1279 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1280 // f128 = EXTLOAD {f32,f64} too
1281 if ((SrcVT == MVT::f32 && (Node->getValueType(0) == MVT::f64 ||
1282 Node->getValueType(0) == MVT::f128)) ||
1283 (SrcVT == MVT::f64 && Node->getValueType(0) == MVT::f128)) {
1284 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1285 LD->getSrcValueOffset(),
1286 LD->isVolatile(), LD->getAlignment());
1287 Result = DAG.getNode(ISD::FP_EXTEND, dl,
1288 Node->getValueType(0), Load);
1289 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1290 Tmp2 = LegalizeOp(Load.getValue(1));
1293 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1294 // Turn the unsupported load into an EXTLOAD followed by an explicit
1295 // zero/sign extend inreg.
1296 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1297 Tmp1, Tmp2, LD->getSrcValue(),
1298 LD->getSrcValueOffset(), SrcVT,
1299 LD->isVolatile(), LD->getAlignment());
1301 if (ExtType == ISD::SEXTLOAD)
1302 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1303 Result.getValueType(),
1304 Result, DAG.getValueType(SrcVT));
1306 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
1307 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1308 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1313 // Since loads produce two values, make sure to remember that we legalized
1315 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1316 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1317 return Op.getResNo() ? Tmp2 : Tmp1;
1321 StoreSDNode *ST = cast<StoreSDNode>(Node);
1322 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1323 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1324 int SVOffset = ST->getSrcValueOffset();
1325 unsigned Alignment = ST->getAlignment();
1326 bool isVolatile = ST->isVolatile();
1328 if (!ST->isTruncatingStore()) {
1329 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1330 Result = SDValue(OptStore, 0);
1335 Tmp3 = LegalizeOp(ST->getValue());
1336 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1339 EVT VT = Tmp3.getValueType();
1340 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1341 default: llvm_unreachable("This action is not supported yet!");
1342 case TargetLowering::Legal:
1343 // If this is an unaligned store and the target doesn't support it,
1345 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1346 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1347 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1348 if (ST->getAlignment() < ABIAlignment)
1349 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1353 case TargetLowering::Custom:
1354 Tmp1 = TLI.LowerOperation(Result, DAG);
1355 if (Tmp1.getNode()) Result = Tmp1;
1357 case TargetLowering::Promote:
1358 assert(VT.isVector() && "Unknown legal promote case!");
1359 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
1360 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1361 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1362 ST->getSrcValue(), SVOffset, isVolatile,
1369 Tmp3 = LegalizeOp(ST->getValue());
1371 EVT StVT = ST->getMemoryVT();
1372 unsigned StWidth = StVT.getSizeInBits();
1374 if (StWidth != StVT.getStoreSizeInBits()) {
1375 // Promote to a byte-sized store with upper bits zero if not
1376 // storing an integral number of bytes. For example, promote
1377 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1378 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), StVT.getStoreSizeInBits());
1379 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1380 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1381 SVOffset, NVT, isVolatile, Alignment);
1382 } else if (StWidth & (StWidth - 1)) {
1383 // If not storing a power-of-2 number of bits, expand as two stores.
1384 assert(!StVT.isVector() && "Unsupported truncstore!");
1385 unsigned RoundWidth = 1 << Log2_32(StWidth);
1386 assert(RoundWidth < StWidth);
1387 unsigned ExtraWidth = StWidth - RoundWidth;
1388 assert(ExtraWidth < RoundWidth);
1389 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1390 "Store size not an integral number of bytes!");
1391 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1392 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1394 unsigned IncrementSize;
1396 if (TLI.isLittleEndian()) {
1397 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1398 // Store the bottom RoundWidth bits.
1399 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1401 isVolatile, Alignment);
1403 // Store the remaining ExtraWidth bits.
1404 IncrementSize = RoundWidth / 8;
1405 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1406 DAG.getIntPtrConstant(IncrementSize));
1407 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1408 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1409 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1410 SVOffset + IncrementSize, ExtraVT, isVolatile,
1411 MinAlign(Alignment, IncrementSize));
1413 // Big endian - avoid unaligned stores.
1414 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1415 // Store the top RoundWidth bits.
1416 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1417 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1418 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1419 SVOffset, RoundVT, isVolatile, Alignment);
1421 // Store the remaining ExtraWidth bits.
1422 IncrementSize = RoundWidth / 8;
1423 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1424 DAG.getIntPtrConstant(IncrementSize));
1425 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1426 SVOffset + IncrementSize, ExtraVT, isVolatile,
1427 MinAlign(Alignment, IncrementSize));
1430 // The order of the stores doesn't matter.
1431 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1433 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1434 Tmp2 != ST->getBasePtr())
1435 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1438 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1439 default: llvm_unreachable("This action is not supported yet!");
1440 case TargetLowering::Legal:
1441 // If this is an unaligned store and the target doesn't support it,
1443 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1444 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1445 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1446 if (ST->getAlignment() < ABIAlignment)
1447 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1451 case TargetLowering::Custom:
1452 Result = TLI.LowerOperation(Result, DAG);
1455 // TRUNCSTORE:i16 i32 -> STORE i16
1456 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
1457 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1458 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1459 SVOffset, isVolatile, Alignment);
1467 assert(Result.getValueType() == Op.getValueType() &&
1468 "Bad legalization!");
1470 // Make sure that the generated code is itself legal.
1472 Result = LegalizeOp(Result);
1474 // Note that LegalizeOp may be reentered even from single-use nodes, which
1475 // means that we always must cache transformed nodes.
1476 AddLegalizedOperand(Op, Result);
1480 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1481 SDValue Vec = Op.getOperand(0);
1482 SDValue Idx = Op.getOperand(1);
1483 DebugLoc dl = Op.getDebugLoc();
1484 // Store the value to a temporary stack slot, then LOAD the returned part.
1485 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1486 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
1488 // Add the offset to the index.
1490 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1491 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1492 DAG.getConstant(EltSize, Idx.getValueType()));
1494 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1495 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1497 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1499 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1501 if (Op.getValueType().isVector())
1502 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0);
1504 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1505 NULL, 0, Vec.getValueType().getVectorElementType());
1508 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1509 // We can't handle this case efficiently. Allocate a sufficiently
1510 // aligned object on the stack, store each element into it, then load
1511 // the result as a vector.
1512 // Create the stack frame object.
1513 EVT VT = Node->getValueType(0);
1514 EVT OpVT = Node->getOperand(0).getValueType();
1515 EVT EltVT = VT.getVectorElementType();
1516 DebugLoc dl = Node->getDebugLoc();
1517 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1518 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1519 const Value *SV = PseudoSourceValue::getFixedStack(FI);
1521 // Emit a store of each element to the stack slot.
1522 SmallVector<SDValue, 8> Stores;
1523 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1524 // Store (in the right endianness) the elements to memory.
1525 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1526 // Ignore undef elements.
1527 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1529 unsigned Offset = TypeByteSize*i;
1531 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1532 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1534 // If EltVT smaller than OpVT, only store the bits necessary.
1535 if (EltVT.bitsLT(OpVT))
1536 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1537 Node->getOperand(i), Idx, SV, Offset, EltVT));
1539 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1540 Node->getOperand(i), Idx, SV, Offset));
1544 if (!Stores.empty()) // Not all undef elements?
1545 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1546 &Stores[0], Stores.size());
1548 StoreChain = DAG.getEntryNode();
1550 // Result is a load from the stack slot.
1551 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0);
1554 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1555 DebugLoc dl = Node->getDebugLoc();
1556 SDValue Tmp1 = Node->getOperand(0);
1557 SDValue Tmp2 = Node->getOperand(1);
1558 assert((Tmp2.getValueType() == MVT::f32 ||
1559 Tmp2.getValueType() == MVT::f64) &&
1560 "Ugly special-cased code!");
1561 // Get the sign bit of the RHS.
1563 EVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32;
1564 if (isTypeLegal(IVT)) {
1565 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
1567 assert(isTypeLegal(TLI.getPointerTy()) &&
1568 (TLI.getPointerTy() == MVT::i32 ||
1569 TLI.getPointerTy() == MVT::i64) &&
1570 "Legal type for load?!");
1571 SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType());
1572 SDValue StorePtr = StackPtr, LoadPtr = StackPtr;
1574 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0);
1575 if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian())
1576 LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(),
1577 LoadPtr, DAG.getIntPtrConstant(4));
1578 SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(),
1579 Ch, LoadPtr, NULL, 0, MVT::i32);
1582 DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1583 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1585 // Get the absolute value of the result.
1586 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1587 // Select between the nabs and abs value based on the sign bit of
1589 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1590 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1594 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1595 SmallVectorImpl<SDValue> &Results) {
1596 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1597 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1598 " not tell us which reg is the stack pointer!");
1599 DebugLoc dl = Node->getDebugLoc();
1600 EVT VT = Node->getValueType(0);
1601 SDValue Tmp1 = SDValue(Node, 0);
1602 SDValue Tmp2 = SDValue(Node, 1);
1603 SDValue Tmp3 = Node->getOperand(2);
1604 SDValue Chain = Tmp1.getOperand(0);
1606 // Chain the dynamic stack allocation so that it doesn't modify the stack
1607 // pointer when other instructions are using the stack.
1608 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1610 SDValue Size = Tmp2.getOperand(1);
1611 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1612 Chain = SP.getValue(1);
1613 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1614 unsigned StackAlign =
1615 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1616 if (Align > StackAlign)
1617 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1618 DAG.getConstant(-(uint64_t)Align, VT));
1619 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1620 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1622 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1623 DAG.getIntPtrConstant(0, true), SDValue());
1625 Results.push_back(Tmp1);
1626 Results.push_back(Tmp2);
1629 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1630 /// condition code CC on the current target. This routine expands SETCC with
1631 /// illegal condition code into AND / OR of multiple SETCC values.
1632 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1633 SDValue &LHS, SDValue &RHS,
1636 EVT OpVT = LHS.getValueType();
1637 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1638 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1639 default: llvm_unreachable("Unknown condition code action!");
1640 case TargetLowering::Legal:
1643 case TargetLowering::Expand: {
1644 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1647 default: llvm_unreachable("Don't know how to expand this condition!");
1648 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1649 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1650 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1651 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1652 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1653 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1654 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1655 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1656 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1657 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1658 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1659 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1660 // FIXME: Implement more expansions.
1663 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1664 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1665 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1673 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1674 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1675 /// a load from the stack slot to DestVT, extending it if needed.
1676 /// The resultant code need not be legal.
1677 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1681 // Create the stack frame object.
1683 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1684 getTypeForEVT(*DAG.getContext()));
1685 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1687 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1688 int SPFI = StackPtrFI->getIndex();
1689 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
1691 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1692 unsigned SlotSize = SlotVT.getSizeInBits();
1693 unsigned DestSize = DestVT.getSizeInBits();
1694 unsigned DestAlign =
1695 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForEVT(*DAG.getContext()));
1697 // Emit a store to the stack slot. Use a truncstore if the input value is
1698 // later than DestVT.
1701 if (SrcSize > SlotSize)
1702 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1703 SV, 0, SlotVT, false, SrcAlign);
1705 assert(SrcSize == SlotSize && "Invalid store");
1706 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1707 SV, 0, false, SrcAlign);
1710 // Result is a load from the stack slot.
1711 if (SlotSize == DestSize)
1712 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign);
1714 assert(SlotSize < DestSize && "Unknown extension!");
1715 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
1719 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1720 DebugLoc dl = Node->getDebugLoc();
1721 // Create a vector sized/aligned stack slot, store the value to element #0,
1722 // then load the whole vector back out.
1723 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1725 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1726 int SPFI = StackPtrFI->getIndex();
1728 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1730 PseudoSourceValue::getFixedStack(SPFI), 0,
1731 Node->getValueType(0).getVectorElementType());
1732 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1733 PseudoSourceValue::getFixedStack(SPFI), 0);
1737 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1738 /// support the operation, but do support the resultant vector type.
1739 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1740 unsigned NumElems = Node->getNumOperands();
1741 SDValue Value1, Value2;
1742 DebugLoc dl = Node->getDebugLoc();
1743 EVT VT = Node->getValueType(0);
1744 EVT OpVT = Node->getOperand(0).getValueType();
1745 EVT EltVT = VT.getVectorElementType();
1747 // If the only non-undef value is the low element, turn this into a
1748 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1749 bool isOnlyLowElement = true;
1750 bool MoreThanTwoValues = false;
1751 bool isConstant = true;
1752 for (unsigned i = 0; i < NumElems; ++i) {
1753 SDValue V = Node->getOperand(i);
1754 if (V.getOpcode() == ISD::UNDEF)
1757 isOnlyLowElement = false;
1758 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1761 if (!Value1.getNode()) {
1763 } else if (!Value2.getNode()) {
1766 } else if (V != Value1 && V != Value2) {
1767 MoreThanTwoValues = true;
1771 if (!Value1.getNode())
1772 return DAG.getUNDEF(VT);
1774 if (isOnlyLowElement)
1775 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1777 // If all elements are constants, create a load from the constant pool.
1779 std::vector<Constant*> CV;
1780 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1781 if (ConstantFPSDNode *V =
1782 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1783 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1784 } else if (ConstantSDNode *V =
1785 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1787 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1789 // If OpVT and EltVT don't match, EltVT is not legal and the
1790 // element values have been promoted/truncated earlier. Undo this;
1791 // we don't want a v16i8 to become a v16i32 for example.
1792 const ConstantInt *CI = V->getConstantIntValue();
1793 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1794 CI->getZExtValue()));
1797 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1798 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1799 CV.push_back(UndefValue::get(OpNTy));
1802 Constant *CP = ConstantVector::get(CV);
1803 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1804 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1805 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1806 PseudoSourceValue::getConstantPool(), 0,
1810 if (!MoreThanTwoValues) {
1811 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1812 for (unsigned i = 0; i < NumElems; ++i) {
1813 SDValue V = Node->getOperand(i);
1814 if (V.getOpcode() == ISD::UNDEF)
1816 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1818 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1819 // Get the splatted value into the low element of a vector register.
1820 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1822 if (Value2.getNode())
1823 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1825 Vec2 = DAG.getUNDEF(VT);
1827 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1828 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1832 // Otherwise, we can't handle this case efficiently.
1833 return ExpandVectorBuildThroughStack(Node);
1836 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1837 // does not fit into a register, return the lo part and set the hi part to the
1838 // by-reg argument. If it does fit into a single register, return the result
1839 // and leave the Hi part unset.
1840 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1842 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
1843 // The input chain to this libcall is the entry node of the function.
1844 // Legalizing the call will automatically add the previous call to the
1846 SDValue InChain = DAG.getEntryNode();
1848 TargetLowering::ArgListTy Args;
1849 TargetLowering::ArgListEntry Entry;
1850 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1851 EVT ArgVT = Node->getOperand(i).getValueType();
1852 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1853 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1854 Entry.isSExt = isSigned;
1855 Entry.isZExt = !isSigned;
1856 Args.push_back(Entry);
1858 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1859 TLI.getPointerTy());
1861 // Splice the libcall in wherever FindInputOutputChains tells us to.
1862 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1863 std::pair<SDValue, SDValue> CallInfo =
1864 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
1865 0, TLI.getLibcallCallingConv(LC), false,
1866 /*isReturnValueUsed=*/true,
1868 Node->getDebugLoc(), DAG.GetOrdering(Node));
1870 // Legalize the call sequence, starting with the chain. This will advance
1871 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
1872 // was added by LowerCallTo (guaranteeing proper serialization of calls).
1873 LegalizeOp(CallInfo.second);
1874 return CallInfo.first;
1877 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1878 RTLIB::Libcall Call_F32,
1879 RTLIB::Libcall Call_F64,
1880 RTLIB::Libcall Call_F80,
1881 RTLIB::Libcall Call_PPCF128) {
1883 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1884 default: llvm_unreachable("Unexpected request for libcall!");
1885 case MVT::f32: LC = Call_F32; break;
1886 case MVT::f64: LC = Call_F64; break;
1887 case MVT::f80: LC = Call_F80; break;
1888 case MVT::ppcf128: LC = Call_PPCF128; break;
1890 return ExpandLibCall(LC, Node, false);
1893 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1894 RTLIB::Libcall Call_I8,
1895 RTLIB::Libcall Call_I16,
1896 RTLIB::Libcall Call_I32,
1897 RTLIB::Libcall Call_I64,
1898 RTLIB::Libcall Call_I128) {
1900 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1901 default: llvm_unreachable("Unexpected request for libcall!");
1902 case MVT::i8: LC = Call_I8; break;
1903 case MVT::i16: LC = Call_I16; break;
1904 case MVT::i32: LC = Call_I32; break;
1905 case MVT::i64: LC = Call_I64; break;
1906 case MVT::i128: LC = Call_I128; break;
1908 return ExpandLibCall(LC, Node, isSigned);
1911 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
1912 /// INT_TO_FP operation of the specified operand when the target requests that
1913 /// we expand it. At this point, we know that the result and operand types are
1914 /// legal for the target.
1915 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
1919 if (Op0.getValueType() == MVT::i32) {
1920 // simple 32-bit [signed|unsigned] integer to float/double expansion
1922 // Get the stack frame index of a 8 byte buffer.
1923 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
1925 // word offset constant for Hi/Lo address computation
1926 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
1927 // set up Hi and Lo (into buffer) address based on endian
1928 SDValue Hi = StackSlot;
1929 SDValue Lo = DAG.getNode(ISD::ADD, dl,
1930 TLI.getPointerTy(), StackSlot, WordOff);
1931 if (TLI.isLittleEndian())
1934 // if signed map to unsigned space
1937 // constant used to invert sign bit (signed to unsigned mapping)
1938 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
1939 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
1943 // store the lo of the constructed double - based on integer input
1944 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
1945 Op0Mapped, Lo, NULL, 0);
1946 // initial hi portion of constructed double
1947 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
1948 // store the hi of the constructed double - biased exponent
1949 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
1950 // load the constructed double
1951 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
1952 // FP constant to bias correct the final result
1953 SDValue Bias = DAG.getConstantFP(isSigned ?
1954 BitsToDouble(0x4330000080000000ULL) :
1955 BitsToDouble(0x4330000000000000ULL),
1957 // subtract the bias
1958 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
1961 // handle final rounding
1962 if (DestVT == MVT::f64) {
1965 } else if (DestVT.bitsLT(MVT::f64)) {
1966 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
1967 DAG.getIntPtrConstant(0));
1968 } else if (DestVT.bitsGT(MVT::f64)) {
1969 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
1973 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
1974 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
1976 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
1977 Op0, DAG.getConstant(0, Op0.getValueType()),
1979 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
1980 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
1981 SignSet, Four, Zero);
1983 // If the sign bit of the integer is set, the large number will be treated
1984 // as a negative number. To counteract this, the dynamic code adds an
1985 // offset depending on the data type.
1987 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
1988 default: llvm_unreachable("Unsupported integer type!");
1989 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
1990 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
1991 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
1992 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
1994 if (TLI.isLittleEndian()) FF <<= 32;
1995 Constant *FudgeFactor = ConstantInt::get(
1996 Type::getInt64Ty(*DAG.getContext()), FF);
1998 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
1999 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2000 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2001 Alignment = std::min(Alignment, 4u);
2003 if (DestVT == MVT::f32)
2004 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2005 PseudoSourceValue::getConstantPool(), 0,
2009 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2010 DAG.getEntryNode(), CPIdx,
2011 PseudoSourceValue::getConstantPool(), 0,
2012 MVT::f32, false, Alignment));
2015 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2018 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2019 /// *INT_TO_FP operation of the specified operand when the target requests that
2020 /// we promote it. At this point, we know that the result and operand types are
2021 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2022 /// operation that takes a larger input.
2023 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2027 // First step, figure out the appropriate *INT_TO_FP operation to use.
2028 EVT NewInTy = LegalOp.getValueType();
2030 unsigned OpToUse = 0;
2032 // Scan for the appropriate larger type to use.
2034 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2035 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2037 // If the target supports SINT_TO_FP of this type, use it.
2038 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2039 OpToUse = ISD::SINT_TO_FP;
2042 if (isSigned) continue;
2044 // If the target supports UINT_TO_FP of this type, use it.
2045 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2046 OpToUse = ISD::UINT_TO_FP;
2050 // Otherwise, try a larger type.
2053 // Okay, we found the operation and type to use. Zero extend our input to the
2054 // desired type then run the operation on it.
2055 return DAG.getNode(OpToUse, dl, DestVT,
2056 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2057 dl, NewInTy, LegalOp));
2060 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2061 /// FP_TO_*INT operation of the specified operand when the target requests that
2062 /// we promote it. At this point, we know that the result and operand types are
2063 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2064 /// operation that returns a larger result.
2065 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2069 // First step, figure out the appropriate FP_TO*INT operation to use.
2070 EVT NewOutTy = DestVT;
2072 unsigned OpToUse = 0;
2074 // Scan for the appropriate larger type to use.
2076 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2077 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2079 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2080 OpToUse = ISD::FP_TO_SINT;
2084 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2085 OpToUse = ISD::FP_TO_UINT;
2089 // Otherwise, try a larger type.
2093 // Okay, we found the operation and type to use.
2094 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2096 // Truncate the result of the extended FP_TO_*INT operation to the desired
2098 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2101 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2103 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2104 EVT VT = Op.getValueType();
2105 EVT SHVT = TLI.getShiftAmountTy();
2106 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2107 switch (VT.getSimpleVT().SimpleTy) {
2108 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2110 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2111 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2112 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2114 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2115 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2116 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2117 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2118 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2119 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2120 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2121 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2122 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2124 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2125 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2126 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2127 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2128 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2129 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2130 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2131 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2132 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2133 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2134 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2135 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2136 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2137 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2138 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2139 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2140 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2141 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2142 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2143 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2144 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2148 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2150 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2153 default: llvm_unreachable("Cannot expand this yet!");
2155 static const uint64_t mask[6] = {
2156 0x5555555555555555ULL, 0x3333333333333333ULL,
2157 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
2158 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
2160 EVT VT = Op.getValueType();
2161 EVT ShVT = TLI.getShiftAmountTy();
2162 unsigned len = VT.getSizeInBits();
2163 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2164 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
2165 unsigned EltSize = VT.isVector() ?
2166 VT.getVectorElementType().getSizeInBits() : len;
2167 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
2168 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2169 Op = DAG.getNode(ISD::ADD, dl, VT,
2170 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
2171 DAG.getNode(ISD::AND, dl, VT,
2172 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
2178 // for now, we do this:
2179 // x = x | (x >> 1);
2180 // x = x | (x >> 2);
2182 // x = x | (x >>16);
2183 // x = x | (x >>32); // for 64-bit input
2184 // return popcount(~x);
2186 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2187 EVT VT = Op.getValueType();
2188 EVT ShVT = TLI.getShiftAmountTy();
2189 unsigned len = VT.getSizeInBits();
2190 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2191 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2192 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2193 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2195 Op = DAG.getNOT(dl, Op, VT);
2196 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2199 // for now, we use: { return popcount(~x & (x - 1)); }
2200 // unless the target has ctlz but not ctpop, in which case we use:
2201 // { return 32 - nlz(~x & (x-1)); }
2202 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2203 EVT VT = Op.getValueType();
2204 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2205 DAG.getNOT(dl, Op, VT),
2206 DAG.getNode(ISD::SUB, dl, VT, Op,
2207 DAG.getConstant(1, VT)));
2208 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2209 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2210 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2211 return DAG.getNode(ISD::SUB, dl, VT,
2212 DAG.getConstant(VT.getSizeInBits(), VT),
2213 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2214 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2219 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2220 SmallVectorImpl<SDValue> &Results) {
2221 DebugLoc dl = Node->getDebugLoc();
2222 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2223 switch (Node->getOpcode()) {
2227 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2228 Results.push_back(Tmp1);
2231 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2233 case ISD::FRAMEADDR:
2234 case ISD::RETURNADDR:
2235 case ISD::FRAME_TO_ARGS_OFFSET:
2236 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2238 case ISD::FLT_ROUNDS_:
2239 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2241 case ISD::EH_RETURN:
2244 case ISD::MEMBARRIER:
2246 Results.push_back(Node->getOperand(0));
2248 case ISD::DYNAMIC_STACKALLOC:
2249 ExpandDYNAMIC_STACKALLOC(Node, Results);
2251 case ISD::MERGE_VALUES:
2252 for (unsigned i = 0; i < Node->getNumValues(); i++)
2253 Results.push_back(Node->getOperand(i));
2256 EVT VT = Node->getValueType(0);
2258 Results.push_back(DAG.getConstant(0, VT));
2259 else if (VT.isFloatingPoint())
2260 Results.push_back(DAG.getConstantFP(0, VT));
2262 llvm_unreachable("Unknown value type!");
2266 // If this operation is not supported, lower it to 'abort()' call
2267 TargetLowering::ArgListTy Args;
2268 std::pair<SDValue, SDValue> CallResult =
2269 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2270 false, false, false, false, 0, CallingConv::C, false,
2271 /*isReturnValueUsed=*/true,
2272 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2273 Args, DAG, dl, DAG.GetOrdering(Node));
2274 Results.push_back(CallResult.second);
2278 case ISD::BIT_CONVERT:
2279 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2280 Node->getValueType(0), dl);
2281 Results.push_back(Tmp1);
2283 case ISD::FP_EXTEND:
2284 Tmp1 = EmitStackConvert(Node->getOperand(0),
2285 Node->getOperand(0).getValueType(),
2286 Node->getValueType(0), dl);
2287 Results.push_back(Tmp1);
2289 case ISD::SIGN_EXTEND_INREG: {
2290 // NOTE: we could fall back on load/store here too for targets without
2291 // SAR. However, it is doubtful that any exist.
2292 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2293 EVT VT = Node->getValueType(0);
2294 EVT ShiftAmountTy = TLI.getShiftAmountTy();
2295 if (VT.isVector()) {
2297 VT = VT.getVectorElementType();
2299 unsigned BitsDiff = VT.getSizeInBits() -
2300 ExtraVT.getSizeInBits();
2301 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2302 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2303 Node->getOperand(0), ShiftCst);
2304 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2305 Results.push_back(Tmp1);
2308 case ISD::FP_ROUND_INREG: {
2309 // The only way we can lower this is to turn it into a TRUNCSTORE,
2310 // EXTLOAD pair, targetting a temporary location (a stack slot).
2312 // NOTE: there is a choice here between constantly creating new stack
2313 // slots and always reusing the same one. We currently always create
2314 // new ones, as reuse may inhibit scheduling.
2315 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2316 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2317 Node->getValueType(0), dl);
2318 Results.push_back(Tmp1);
2321 case ISD::SINT_TO_FP:
2322 case ISD::UINT_TO_FP:
2323 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2324 Node->getOperand(0), Node->getValueType(0), dl);
2325 Results.push_back(Tmp1);
2327 case ISD::FP_TO_UINT: {
2328 SDValue True, False;
2329 EVT VT = Node->getOperand(0).getValueType();
2330 EVT NVT = Node->getValueType(0);
2331 const uint64_t zero[] = {0, 0};
2332 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
2333 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2334 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2335 Tmp1 = DAG.getConstantFP(apf, VT);
2336 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2337 Node->getOperand(0),
2339 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2340 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2341 DAG.getNode(ISD::FSUB, dl, VT,
2342 Node->getOperand(0), Tmp1));
2343 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2344 DAG.getConstant(x, NVT));
2345 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2346 Results.push_back(Tmp1);
2350 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2351 EVT VT = Node->getValueType(0);
2352 Tmp1 = Node->getOperand(0);
2353 Tmp2 = Node->getOperand(1);
2354 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
2355 // Increment the pointer, VAList, to the next vaarg
2356 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2357 DAG.getConstant(TLI.getTargetData()->
2358 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2359 TLI.getPointerTy()));
2360 // Store the incremented VAList to the legalized pointer
2361 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
2362 // Load the actual argument out of the pointer VAList
2363 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0));
2364 Results.push_back(Results[0].getValue(1));
2368 // This defaults to loading a pointer from the input and storing it to the
2369 // output, returning the chain.
2370 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2371 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2372 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2373 Node->getOperand(2), VS, 0);
2374 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0);
2375 Results.push_back(Tmp1);
2378 case ISD::EXTRACT_VECTOR_ELT:
2379 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2380 // This must be an access of the only element. Return it.
2381 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
2382 Node->getOperand(0));
2384 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2385 Results.push_back(Tmp1);
2387 case ISD::EXTRACT_SUBVECTOR:
2388 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2390 case ISD::CONCAT_VECTORS: {
2391 Results.push_back(ExpandVectorBuildThroughStack(Node));
2394 case ISD::SCALAR_TO_VECTOR:
2395 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2397 case ISD::INSERT_VECTOR_ELT:
2398 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2399 Node->getOperand(1),
2400 Node->getOperand(2), dl));
2402 case ISD::VECTOR_SHUFFLE: {
2403 SmallVector<int, 8> Mask;
2404 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
2406 EVT VT = Node->getValueType(0);
2407 EVT EltVT = VT.getVectorElementType();
2408 unsigned NumElems = VT.getVectorNumElements();
2409 SmallVector<SDValue, 8> Ops;
2410 for (unsigned i = 0; i != NumElems; ++i) {
2412 Ops.push_back(DAG.getUNDEF(EltVT));
2415 unsigned Idx = Mask[i];
2417 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2418 Node->getOperand(0),
2419 DAG.getIntPtrConstant(Idx)));
2421 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2422 Node->getOperand(1),
2423 DAG.getIntPtrConstant(Idx - NumElems)));
2425 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2426 Results.push_back(Tmp1);
2429 case ISD::EXTRACT_ELEMENT: {
2430 EVT OpTy = Node->getOperand(0).getValueType();
2431 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2433 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2434 DAG.getConstant(OpTy.getSizeInBits()/2,
2435 TLI.getShiftAmountTy()));
2436 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2439 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2440 Node->getOperand(0));
2442 Results.push_back(Tmp1);
2445 case ISD::STACKSAVE:
2446 // Expand to CopyFromReg if the target set
2447 // StackPointerRegisterToSaveRestore.
2448 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2449 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2450 Node->getValueType(0)));
2451 Results.push_back(Results[0].getValue(1));
2453 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2454 Results.push_back(Node->getOperand(0));
2457 case ISD::STACKRESTORE:
2458 // Expand to CopyToReg if the target set
2459 // StackPointerRegisterToSaveRestore.
2460 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2461 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2462 Node->getOperand(1)));
2464 Results.push_back(Node->getOperand(0));
2467 case ISD::FCOPYSIGN:
2468 Results.push_back(ExpandFCOPYSIGN(Node));
2471 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2472 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2473 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
2474 Node->getOperand(0));
2475 Results.push_back(Tmp1);
2478 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2479 EVT VT = Node->getValueType(0);
2480 Tmp1 = Node->getOperand(0);
2481 Tmp2 = DAG.getConstantFP(0.0, VT);
2482 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2483 Tmp1, Tmp2, ISD::SETUGT);
2484 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
2485 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
2486 Results.push_back(Tmp1);
2490 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
2491 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
2494 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
2495 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
2498 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
2499 RTLIB::COS_F80, RTLIB::COS_PPCF128));
2502 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
2503 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
2506 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
2507 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
2510 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
2511 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
2514 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
2515 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
2518 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
2519 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
2522 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
2523 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
2526 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
2527 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
2530 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
2531 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
2534 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
2535 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
2537 case ISD::FNEARBYINT:
2538 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
2539 RTLIB::NEARBYINT_F64,
2540 RTLIB::NEARBYINT_F80,
2541 RTLIB::NEARBYINT_PPCF128));
2544 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
2545 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
2548 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
2549 RTLIB::POW_F80, RTLIB::POW_PPCF128));
2552 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
2553 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
2556 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
2557 RTLIB::REM_F80, RTLIB::REM_PPCF128));
2559 case ISD::ConstantFP: {
2560 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
2561 // Check to see if this FP immediate is already legal.
2562 // If this is a legal constant, turn it into a TargetConstantFP node.
2563 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
2564 Results.push_back(SDValue(Node, 0));
2566 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
2569 case ISD::EHSELECTION: {
2570 unsigned Reg = TLI.getExceptionSelectorRegister();
2571 assert(Reg && "Can't expand to unknown register!");
2572 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
2573 Node->getValueType(0)));
2574 Results.push_back(Results[0].getValue(1));
2577 case ISD::EXCEPTIONADDR: {
2578 unsigned Reg = TLI.getExceptionAddressRegister();
2579 assert(Reg && "Can't expand to unknown register!");
2580 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
2581 Node->getValueType(0)));
2582 Results.push_back(Results[0].getValue(1));
2586 EVT VT = Node->getValueType(0);
2587 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
2588 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
2589 "Don't know how to expand this subtraction!");
2590 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
2591 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
2592 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
2593 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
2598 EVT VT = Node->getValueType(0);
2599 SDVTList VTs = DAG.getVTList(VT, VT);
2600 bool isSigned = Node->getOpcode() == ISD::SREM;
2601 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
2602 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2603 Tmp2 = Node->getOperand(0);
2604 Tmp3 = Node->getOperand(1);
2605 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
2606 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
2607 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
2609 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
2610 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
2611 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
2612 } else if (isSigned) {
2613 Tmp1 = ExpandIntLibCall(Node, true,
2615 RTLIB::SREM_I16, RTLIB::SREM_I32,
2616 RTLIB::SREM_I64, RTLIB::SREM_I128);
2618 Tmp1 = ExpandIntLibCall(Node, false,
2620 RTLIB::UREM_I16, RTLIB::UREM_I32,
2621 RTLIB::UREM_I64, RTLIB::UREM_I128);
2623 Results.push_back(Tmp1);
2628 bool isSigned = Node->getOpcode() == ISD::SDIV;
2629 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2630 EVT VT = Node->getValueType(0);
2631 SDVTList VTs = DAG.getVTList(VT, VT);
2632 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT))
2633 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
2634 Node->getOperand(1));
2636 Tmp1 = ExpandIntLibCall(Node, true,
2638 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
2639 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
2641 Tmp1 = ExpandIntLibCall(Node, false,
2643 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
2644 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
2645 Results.push_back(Tmp1);
2650 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
2652 EVT VT = Node->getValueType(0);
2653 SDVTList VTs = DAG.getVTList(VT, VT);
2654 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
2655 "If this wasn't legal, it shouldn't have been created!");
2656 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
2657 Node->getOperand(1));
2658 Results.push_back(Tmp1.getValue(1));
2662 EVT VT = Node->getValueType(0);
2663 SDVTList VTs = DAG.getVTList(VT, VT);
2664 // See if multiply or divide can be lowered using two-result operations.
2665 // We just need the low half of the multiply; try both the signed
2666 // and unsigned forms. If the target supports both SMUL_LOHI and
2667 // UMUL_LOHI, form a preference by checking which forms of plain
2668 // MULH it supports.
2669 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
2670 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
2671 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
2672 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
2673 unsigned OpToUse = 0;
2674 if (HasSMUL_LOHI && !HasMULHS) {
2675 OpToUse = ISD::SMUL_LOHI;
2676 } else if (HasUMUL_LOHI && !HasMULHU) {
2677 OpToUse = ISD::UMUL_LOHI;
2678 } else if (HasSMUL_LOHI) {
2679 OpToUse = ISD::SMUL_LOHI;
2680 } else if (HasUMUL_LOHI) {
2681 OpToUse = ISD::UMUL_LOHI;
2684 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
2685 Node->getOperand(1)));
2688 Tmp1 = ExpandIntLibCall(Node, false,
2690 RTLIB::MUL_I16, RTLIB::MUL_I32,
2691 RTLIB::MUL_I64, RTLIB::MUL_I128);
2692 Results.push_back(Tmp1);
2697 SDValue LHS = Node->getOperand(0);
2698 SDValue RHS = Node->getOperand(1);
2699 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2700 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2702 Results.push_back(Sum);
2703 EVT OType = Node->getValueType(1);
2705 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2707 // LHSSign -> LHS >= 0
2708 // RHSSign -> RHS >= 0
2709 // SumSign -> Sum >= 0
2712 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2714 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2716 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2717 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2718 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2719 Node->getOpcode() == ISD::SADDO ?
2720 ISD::SETEQ : ISD::SETNE);
2722 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2723 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2725 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2726 Results.push_back(Cmp);
2731 SDValue LHS = Node->getOperand(0);
2732 SDValue RHS = Node->getOperand(1);
2733 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
2734 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2736 Results.push_back(Sum);
2737 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
2738 Node->getOpcode () == ISD::UADDO ?
2739 ISD::SETULT : ISD::SETUGT));
2744 EVT VT = Node->getValueType(0);
2745 SDValue LHS = Node->getOperand(0);
2746 SDValue RHS = Node->getOperand(1);
2749 static const unsigned Ops[2][3] =
2750 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
2751 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
2752 bool isSigned = Node->getOpcode() == ISD::SMULO;
2753 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
2754 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
2755 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
2756 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
2757 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
2759 TopHalf = BottomHalf.getValue(1);
2760 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2))) {
2761 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
2762 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
2763 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
2764 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
2765 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
2766 DAG.getIntPtrConstant(0));
2767 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
2768 DAG.getIntPtrConstant(1));
2770 // FIXME: We should be able to fall back to a libcall with an illegal
2771 // type in some cases cases.
2772 // Also, we can fall back to a division in some cases, but that's a big
2773 // performance hit in the general case.
2774 llvm_unreachable("Don't know how to expand this operation yet!");
2777 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy());
2778 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
2779 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
2782 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
2783 DAG.getConstant(0, VT), ISD::SETNE);
2785 Results.push_back(BottomHalf);
2786 Results.push_back(TopHalf);
2789 case ISD::BUILD_PAIR: {
2790 EVT PairTy = Node->getValueType(0);
2791 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
2792 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
2793 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
2794 DAG.getConstant(PairTy.getSizeInBits()/2,
2795 TLI.getShiftAmountTy()));
2796 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
2800 Tmp1 = Node->getOperand(0);
2801 Tmp2 = Node->getOperand(1);
2802 Tmp3 = Node->getOperand(2);
2803 if (Tmp1.getOpcode() == ISD::SETCC) {
2804 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
2806 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2808 Tmp1 = DAG.getSelectCC(dl, Tmp1,
2809 DAG.getConstant(0, Tmp1.getValueType()),
2810 Tmp2, Tmp3, ISD::SETNE);
2812 Results.push_back(Tmp1);
2815 SDValue Chain = Node->getOperand(0);
2816 SDValue Table = Node->getOperand(1);
2817 SDValue Index = Node->getOperand(2);
2819 EVT PTy = TLI.getPointerTy();
2820 MachineFunction &MF = DAG.getMachineFunction();
2821 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
2822 Index= DAG.getNode(ISD::MUL, dl, PTy,
2823 Index, DAG.getConstant(EntrySize, PTy));
2824 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2826 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
2827 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
2828 PseudoSourceValue::getJumpTable(), 0, MemVT);
2830 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2831 // For PIC, the sequence is:
2832 // BRIND(load(Jumptable + index) + RelocBase)
2833 // RelocBase can be JumpTable, GOT or some sort of global base.
2834 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
2835 TLI.getPICJumpTableRelocBase(Table, DAG));
2837 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
2838 Results.push_back(Tmp1);
2842 // Expand brcond's setcc into its constituent parts and create a BR_CC
2844 Tmp1 = Node->getOperand(0);
2845 Tmp2 = Node->getOperand(1);
2846 if (Tmp2.getOpcode() == ISD::SETCC) {
2847 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
2848 Tmp1, Tmp2.getOperand(2),
2849 Tmp2.getOperand(0), Tmp2.getOperand(1),
2850 Node->getOperand(2));
2852 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
2853 DAG.getCondCode(ISD::SETNE), Tmp2,
2854 DAG.getConstant(0, Tmp2.getValueType()),
2855 Node->getOperand(2));
2857 Results.push_back(Tmp1);
2860 Tmp1 = Node->getOperand(0);
2861 Tmp2 = Node->getOperand(1);
2862 Tmp3 = Node->getOperand(2);
2863 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
2865 // If we expanded the SETCC into an AND/OR, return the new node
2866 if (Tmp2.getNode() == 0) {
2867 Results.push_back(Tmp1);
2871 // Otherwise, SETCC for the given comparison type must be completely
2872 // illegal; expand it into a SELECT_CC.
2873 EVT VT = Node->getValueType(0);
2874 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
2875 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
2876 Results.push_back(Tmp1);
2879 case ISD::SELECT_CC: {
2880 Tmp1 = Node->getOperand(0); // LHS
2881 Tmp2 = Node->getOperand(1); // RHS
2882 Tmp3 = Node->getOperand(2); // True
2883 Tmp4 = Node->getOperand(3); // False
2884 SDValue CC = Node->getOperand(4);
2886 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
2887 Tmp1, Tmp2, CC, dl);
2889 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
2890 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2891 CC = DAG.getCondCode(ISD::SETNE);
2892 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
2894 Results.push_back(Tmp1);
2898 Tmp1 = Node->getOperand(0); // Chain
2899 Tmp2 = Node->getOperand(2); // LHS
2900 Tmp3 = Node->getOperand(3); // RHS
2901 Tmp4 = Node->getOperand(1); // CC
2903 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
2904 Tmp2, Tmp3, Tmp4, dl);
2905 LastCALLSEQ_END = DAG.getEntryNode();
2907 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
2908 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2909 Tmp4 = DAG.getCondCode(ISD::SETNE);
2910 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
2911 Tmp3, Node->getOperand(4));
2912 Results.push_back(Tmp1);
2915 case ISD::GLOBAL_OFFSET_TABLE:
2916 case ISD::GlobalAddress:
2917 case ISD::GlobalTLSAddress:
2918 case ISD::ExternalSymbol:
2919 case ISD::ConstantPool:
2920 case ISD::JumpTable:
2921 case ISD::INTRINSIC_W_CHAIN:
2922 case ISD::INTRINSIC_WO_CHAIN:
2923 case ISD::INTRINSIC_VOID:
2924 // FIXME: Custom lowering for these operations shouldn't return null!
2925 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2926 Results.push_back(SDValue(Node, i));
2930 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
2931 SmallVectorImpl<SDValue> &Results) {
2932 EVT OVT = Node->getValueType(0);
2933 if (Node->getOpcode() == ISD::UINT_TO_FP ||
2934 Node->getOpcode() == ISD::SINT_TO_FP ||
2935 Node->getOpcode() == ISD::SETCC) {
2936 OVT = Node->getOperand(0).getValueType();
2938 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2939 DebugLoc dl = Node->getDebugLoc();
2940 SDValue Tmp1, Tmp2, Tmp3;
2941 switch (Node->getOpcode()) {
2945 // Zero extend the argument.
2946 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
2947 // Perform the larger operation.
2948 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
2949 if (Node->getOpcode() == ISD::CTTZ) {
2950 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2951 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
2952 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
2954 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
2955 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
2956 } else if (Node->getOpcode() == ISD::CTLZ) {
2957 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2958 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
2959 DAG.getConstant(NVT.getSizeInBits() -
2960 OVT.getSizeInBits(), NVT));
2962 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
2965 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
2966 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
2967 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
2968 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
2969 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2970 Results.push_back(Tmp1);
2973 case ISD::FP_TO_UINT:
2974 case ISD::FP_TO_SINT:
2975 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
2976 Node->getOpcode() == ISD::FP_TO_SINT, dl);
2977 Results.push_back(Tmp1);
2979 case ISD::UINT_TO_FP:
2980 case ISD::SINT_TO_FP:
2981 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
2982 Node->getOpcode() == ISD::SINT_TO_FP, dl);
2983 Results.push_back(Tmp1);
2988 unsigned ExtOp, TruncOp;
2989 if (OVT.isVector()) {
2990 ExtOp = ISD::BIT_CONVERT;
2991 TruncOp = ISD::BIT_CONVERT;
2992 } else if (OVT.isInteger()) {
2993 ExtOp = ISD::ANY_EXTEND;
2994 TruncOp = ISD::TRUNCATE;
2996 llvm_report_error("Cannot promote logic operation");
2998 // Promote each of the values to the new type.
2999 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3000 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3001 // Perform the larger operation, then convert back
3002 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3003 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3007 unsigned ExtOp, TruncOp;
3008 if (Node->getValueType(0).isVector()) {
3009 ExtOp = ISD::BIT_CONVERT;
3010 TruncOp = ISD::BIT_CONVERT;
3011 } else if (Node->getValueType(0).isInteger()) {
3012 ExtOp = ISD::ANY_EXTEND;
3013 TruncOp = ISD::TRUNCATE;
3015 ExtOp = ISD::FP_EXTEND;
3016 TruncOp = ISD::FP_ROUND;
3018 Tmp1 = Node->getOperand(0);
3019 // Promote each of the values to the new type.
3020 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3021 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3022 // Perform the larger operation, then round down.
3023 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3024 if (TruncOp != ISD::FP_ROUND)
3025 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3027 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3028 DAG.getIntPtrConstant(0));
3029 Results.push_back(Tmp1);
3032 case ISD::VECTOR_SHUFFLE: {
3033 SmallVector<int, 8> Mask;
3034 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3036 // Cast the two input vectors.
3037 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
3038 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1));
3040 // Convert the shuffle mask to the right # elements.
3041 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3042 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1);
3043 Results.push_back(Tmp1);
3047 unsigned ExtOp = ISD::FP_EXTEND;
3048 if (NVT.isInteger()) {
3049 ISD::CondCode CCCode =
3050 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3051 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3053 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3054 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3055 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3056 Tmp1, Tmp2, Node->getOperand(2)));
3062 // SelectionDAG::Legalize - This is the entry point for the file.
3064 void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) {
3065 /// run - This is the main entry point to this class.
3067 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG();