1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/Target/TargetFrameInfo.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetData.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/CallingConv.h"
25 #include "llvm/Constants.h"
26 #include "llvm/DerivedTypes.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/ADT/SmallPtrSet.h"
38 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
39 cl::desc("Pop up a window to show dags before legalize"));
41 static const bool ViewLegalizeDAGs = 0;
44 //===----------------------------------------------------------------------===//
45 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
46 /// hacks on it until the target machine can handle it. This involves
47 /// eliminating value sizes the machine cannot handle (promoting small sizes to
48 /// large sizes or splitting up large values into small values) as well as
49 /// eliminating operations the machine cannot handle.
51 /// This code also does a small amount of optimization and recognition of idioms
52 /// as part of its processing. For example, if a target does not support a
53 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
54 /// will attempt merge setcc and brc instructions into brcc's.
57 class VISIBILITY_HIDDEN SelectionDAGLegalize {
61 // Libcall insertion helpers.
63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
64 /// legalized. We use this to ensure that calls are properly serialized
65 /// against each other, including inserted libcalls.
66 SDOperand LastCALLSEQ_END;
68 /// IsLegalizingCall - This member is used *only* for purposes of providing
69 /// helpful assertions that a libcall isn't created while another call is
70 /// being legalized (which could lead to non-serialized call sequences).
71 bool IsLegalizingCall;
74 Legal, // The target natively supports this operation.
75 Promote, // This operation should be executed in a larger type.
76 Expand // Try to expand this to other ops, otherwise use a libcall.
79 /// ValueTypeActions - This is a bitvector that contains two bits for each
80 /// value type, where the two bits correspond to the LegalizeAction enum.
81 /// This can be queried with "getTypeAction(VT)".
82 TargetLowering::ValueTypeActionImpl ValueTypeActions;
84 /// LegalizedNodes - For nodes that are of legal width, and that have more
85 /// than one use, this map indicates what regularized operand to use. This
86 /// allows us to avoid legalizing the same thing more than once.
87 DenseMap<SDOperand, SDOperand> LegalizedNodes;
89 /// PromotedNodes - For nodes that are below legal width, and that have more
90 /// than one use, this map indicates what promoted value to use. This allows
91 /// us to avoid promoting the same thing more than once.
92 DenseMap<SDOperand, SDOperand> PromotedNodes;
94 /// ExpandedNodes - For nodes that need to be expanded this map indicates
95 /// which which operands are the expanded version of the input. This allows
96 /// us to avoid expanding the same node more than once.
97 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
99 /// SplitNodes - For vector nodes that need to be split, this map indicates
100 /// which which operands are the split version of the input. This allows us
101 /// to avoid splitting the same node more than once.
102 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
104 /// ScalarizedNodes - For nodes that need to be converted from vector types to
105 /// scalar types, this contains the mapping of ones we have already
106 /// processed to the result.
107 std::map<SDOperand, SDOperand> ScalarizedNodes;
109 void AddLegalizedOperand(SDOperand From, SDOperand To) {
110 LegalizedNodes.insert(std::make_pair(From, To));
111 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
115 void AddPromotedOperand(SDOperand From, SDOperand To) {
116 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
117 assert(isNew && "Got into the map somehow?");
118 // If someone requests legalization of the new node, return itself.
119 LegalizedNodes.insert(std::make_pair(To, To));
124 SelectionDAGLegalize(SelectionDAG &DAG);
126 /// getTypeAction - Return how we should legalize values of this type, either
127 /// it is already legal or we need to expand it into multiple registers of
128 /// smaller integer type, or we need to promote it to a larger type.
129 LegalizeAction getTypeAction(MVT::ValueType VT) const {
130 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
133 /// isTypeLegal - Return true if this type is legal on this target.
135 bool isTypeLegal(MVT::ValueType VT) const {
136 return getTypeAction(VT) == Legal;
142 /// HandleOp - Legalize, Promote, or Expand the specified operand as
143 /// appropriate for its type.
144 void HandleOp(SDOperand Op);
146 /// LegalizeOp - We know that the specified value has a legal type.
147 /// Recursively ensure that the operands have legal types, then return the
149 SDOperand LegalizeOp(SDOperand O);
151 /// UnrollVectorOp - We know that the given vector has a legal type, however
152 /// the operation it performs is not legal and is an operation that we have
153 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
154 /// operating on each element individually.
155 SDOperand UnrollVectorOp(SDOperand O);
157 /// PromoteOp - Given an operation that produces a value in an invalid type,
158 /// promote it to compute the value into a larger type. The produced value
159 /// will have the correct bits for the low portion of the register, but no
160 /// guarantee is made about the top bits: it may be zero, sign-extended, or
162 SDOperand PromoteOp(SDOperand O);
164 /// ExpandOp - Expand the specified SDOperand into its two component pieces
165 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
166 /// the LegalizeNodes map is filled in for any results that are not expanded,
167 /// the ExpandedNodes map is filled in for any results that are expanded, and
168 /// the Lo/Hi values are returned. This applies to integer types and Vector
170 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
172 /// SplitVectorOp - Given an operand of vector type, break it down into
173 /// two smaller values.
174 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
176 /// ScalarizeVectorOp - Given an operand of single-element vector type
177 /// (e.g. v1f32), convert it into the equivalent operation that returns a
178 /// scalar (e.g. f32) value.
179 SDOperand ScalarizeVectorOp(SDOperand O);
181 /// isShuffleLegal - Return true if a vector shuffle is legal with the
182 /// specified mask and type. Targets can specify exactly which masks they
183 /// support and the code generator is tasked with not creating illegal masks.
185 /// Note that this will also return true for shuffles that are promoted to a
188 /// If this is a legal shuffle, this method returns the (possibly promoted)
189 /// build_vector Mask. If it's not a legal shuffle, it returns null.
190 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
192 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
193 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
195 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
197 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
199 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
202 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT,
203 MVT::ValueType DestVT);
204 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
205 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
206 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
208 MVT::ValueType DestVT);
209 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
211 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
214 SDOperand ExpandBSWAP(SDOperand Op);
215 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
216 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
217 SDOperand &Lo, SDOperand &Hi);
218 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
219 SDOperand &Lo, SDOperand &Hi);
221 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
222 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
226 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
227 /// specified mask and type. Targets can specify exactly which masks they
228 /// support and the code generator is tasked with not creating illegal masks.
230 /// Note that this will also return true for shuffles that are promoted to a
232 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
233 SDOperand Mask) const {
234 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
236 case TargetLowering::Legal:
237 case TargetLowering::Custom:
239 case TargetLowering::Promote: {
240 // If this is promoted to a different type, convert the shuffle mask and
241 // ask if it is legal in the promoted type!
242 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
244 // If we changed # elements, change the shuffle mask.
245 unsigned NumEltsGrowth =
246 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
247 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
248 if (NumEltsGrowth > 1) {
249 // Renumber the elements.
250 SmallVector<SDOperand, 8> Ops;
251 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
252 SDOperand InOp = Mask.getOperand(i);
253 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
254 if (InOp.getOpcode() == ISD::UNDEF)
255 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
257 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
258 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
262 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
268 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
271 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
272 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
273 ValueTypeActions(TLI.getValueTypeActions()) {
274 assert(MVT::LAST_VALUETYPE <= 32 &&
275 "Too many value types for ValueTypeActions to hold!");
278 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
279 /// contains all of a nodes operands before it contains the node.
280 static void ComputeTopDownOrdering(SelectionDAG &DAG,
281 SmallVector<SDNode*, 64> &Order) {
283 DenseMap<SDNode*, unsigned> Visited;
284 std::vector<SDNode*> Worklist;
285 Worklist.reserve(128);
287 // Compute ordering from all of the leaves in the graphs, those (like the
288 // entry node) that have no operands.
289 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
290 E = DAG.allnodes_end(); I != E; ++I) {
291 if (I->getNumOperands() == 0) {
293 Worklist.push_back(I);
297 while (!Worklist.empty()) {
298 SDNode *N = Worklist.back();
301 if (++Visited[N] != N->getNumOperands())
302 continue; // Haven't visited all operands yet
306 // Now that we have N in, add anything that uses it if all of their operands
308 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
310 Worklist.push_back(*UI);
313 assert(Order.size() == Visited.size() &&
315 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
316 "Error: DAG is cyclic!");
320 void SelectionDAGLegalize::LegalizeDAG() {
321 LastCALLSEQ_END = DAG.getEntryNode();
322 IsLegalizingCall = false;
324 // The legalize process is inherently a bottom-up recursive process (users
325 // legalize their uses before themselves). Given infinite stack space, we
326 // could just start legalizing on the root and traverse the whole graph. In
327 // practice however, this causes us to run out of stack space on large basic
328 // blocks. To avoid this problem, compute an ordering of the nodes where each
329 // node is only legalized after all of its operands are legalized.
330 SmallVector<SDNode*, 64> Order;
331 ComputeTopDownOrdering(DAG, Order);
333 for (unsigned i = 0, e = Order.size(); i != e; ++i)
334 HandleOp(SDOperand(Order[i], 0));
336 // Finally, it's possible the root changed. Get the new root.
337 SDOperand OldRoot = DAG.getRoot();
338 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
339 DAG.setRoot(LegalizedNodes[OldRoot]);
341 ExpandedNodes.clear();
342 LegalizedNodes.clear();
343 PromotedNodes.clear();
345 ScalarizedNodes.clear();
347 // Remove dead nodes now.
348 DAG.RemoveDeadNodes();
352 /// FindCallEndFromCallStart - Given a chained node that is part of a call
353 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
354 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
355 if (Node->getOpcode() == ISD::CALLSEQ_END)
357 if (Node->use_empty())
358 return 0; // No CallSeqEnd
360 // The chain is usually at the end.
361 SDOperand TheChain(Node, Node->getNumValues()-1);
362 if (TheChain.getValueType() != MVT::Other) {
363 // Sometimes it's at the beginning.
364 TheChain = SDOperand(Node, 0);
365 if (TheChain.getValueType() != MVT::Other) {
366 // Otherwise, hunt for it.
367 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
368 if (Node->getValueType(i) == MVT::Other) {
369 TheChain = SDOperand(Node, i);
373 // Otherwise, we walked into a node without a chain.
374 if (TheChain.getValueType() != MVT::Other)
379 for (SDNode::use_iterator UI = Node->use_begin(),
380 E = Node->use_end(); UI != E; ++UI) {
382 // Make sure to only follow users of our token chain.
384 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
385 if (User->getOperand(i) == TheChain)
386 if (SDNode *Result = FindCallEndFromCallStart(User))
392 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
393 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
394 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
395 assert(Node && "Didn't find callseq_start for a call??");
396 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
398 assert(Node->getOperand(0).getValueType() == MVT::Other &&
399 "Node doesn't have a token chain argument!");
400 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
403 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
404 /// see if any uses can reach Dest. If no dest operands can get to dest,
405 /// legalize them, legalize ourself, and return false, otherwise, return true.
407 /// Keep track of the nodes we fine that actually do lead to Dest in
408 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
410 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
411 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
412 if (N == Dest) return true; // N certainly leads to Dest :)
414 // If we've already processed this node and it does lead to Dest, there is no
415 // need to reprocess it.
416 if (NodesLeadingTo.count(N)) return true;
418 // If the first result of this node has been already legalized, then it cannot
420 switch (getTypeAction(N->getValueType(0))) {
422 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
425 if (PromotedNodes.count(SDOperand(N, 0))) return false;
428 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
432 // Okay, this node has not already been legalized. Check and legalize all
433 // operands. If none lead to Dest, then we can legalize this node.
434 bool OperandsLeadToDest = false;
435 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
436 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
437 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
439 if (OperandsLeadToDest) {
440 NodesLeadingTo.insert(N);
444 // Okay, this node looks safe, legalize it and return false.
445 HandleOp(SDOperand(N, 0));
449 /// HandleOp - Legalize, Promote, or Expand the specified operand as
450 /// appropriate for its type.
451 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
452 MVT::ValueType VT = Op.getValueType();
453 switch (getTypeAction(VT)) {
454 default: assert(0 && "Bad type action!");
455 case Legal: (void)LegalizeOp(Op); break;
456 case Promote: (void)PromoteOp(Op); break;
458 if (!MVT::isVector(VT)) {
459 // If this is an illegal scalar, expand it into its two component
462 if (Op.getOpcode() == ISD::TargetConstant)
463 break; // Allow illegal target nodes.
465 } else if (MVT::getVectorNumElements(VT) == 1) {
466 // If this is an illegal single element vector, convert it to a
468 (void)ScalarizeVectorOp(Op);
470 // Otherwise, this is an illegal multiple element vector.
471 // Split it in half and legalize both parts.
473 SplitVectorOp(Op, X, Y);
479 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
480 /// a load from the constant pool.
481 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
482 SelectionDAG &DAG, TargetLowering &TLI) {
485 // If a FP immediate is precise when represented as a float and if the
486 // target can do an extending load from float to double, we put it into
487 // the constant pool as a float, even if it's is statically typed as a
489 MVT::ValueType VT = CFP->getValueType(0);
490 bool isDouble = VT == MVT::f64;
491 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
494 if (VT!=MVT::f64 && VT!=MVT::f32)
495 assert(0 && "Invalid type expansion");
496 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(),
497 isDouble ? MVT::i64 : MVT::i32);
500 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) &&
501 // Only do this if the target has a native EXTLOAD instruction from f32.
502 // Do not try to be clever about long doubles (so far)
503 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
504 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
509 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
511 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
512 CPIdx, NULL, 0, MVT::f32);
514 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
519 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
522 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
523 SelectionDAG &DAG, TargetLowering &TLI) {
524 MVT::ValueType VT = Node->getValueType(0);
525 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
526 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
527 "fcopysign expansion only supported for f32 and f64");
528 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
530 // First get the sign bit of second operand.
531 SDOperand Mask1 = (SrcVT == MVT::f64)
532 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
533 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
534 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
535 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
536 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
537 // Shift right or sign-extend it if the two operands have different types.
538 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
540 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
541 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
542 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
543 } else if (SizeDiff < 0)
544 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
546 // Clear the sign bit of first operand.
547 SDOperand Mask2 = (VT == MVT::f64)
548 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
549 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
550 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
551 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
552 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
554 // Or the value with the sign bit.
555 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
559 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
561 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
562 TargetLowering &TLI) {
563 SDOperand Chain = ST->getChain();
564 SDOperand Ptr = ST->getBasePtr();
565 SDOperand Val = ST->getValue();
566 MVT::ValueType VT = Val.getValueType();
567 int Alignment = ST->getAlignment();
568 int SVOffset = ST->getSrcValueOffset();
569 if (MVT::isFloatingPoint(ST->getStoredVT())) {
570 // Expand to a bitconvert of the value to the integer type of the
571 // same size, then a (misaligned) int store.
572 MVT::ValueType intVT;
575 else if (VT==MVT::f32)
578 assert(0 && "Unaligned load of unsupported floating point type");
580 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
581 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
582 SVOffset, ST->isVolatile(), Alignment);
584 assert(MVT::isInteger(ST->getStoredVT()) &&
585 "Unaligned store of unknown type.");
586 // Get the half-size VT
587 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1;
588 int NumBits = MVT::getSizeInBits(NewStoredVT);
589 int IncrementSize = NumBits / 8;
591 // Divide the stored value in two parts.
592 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
594 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
596 // Store the two parts
597 SDOperand Store1, Store2;
598 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
599 ST->getSrcValue(), SVOffset, NewStoredVT,
600 ST->isVolatile(), Alignment);
601 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
602 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
603 Alignment = MinAlign(Alignment, IncrementSize);
604 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
605 ST->getSrcValue(), SVOffset + IncrementSize,
606 NewStoredVT, ST->isVolatile(), Alignment);
608 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
611 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
613 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
614 TargetLowering &TLI) {
615 int SVOffset = LD->getSrcValueOffset();
616 SDOperand Chain = LD->getChain();
617 SDOperand Ptr = LD->getBasePtr();
618 MVT::ValueType VT = LD->getValueType(0);
619 MVT::ValueType LoadedVT = LD->getLoadedVT();
620 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT)) {
621 // Expand to a (misaligned) integer load of the same size,
622 // then bitconvert to floating point.
623 MVT::ValueType intVT;
624 if (LoadedVT == MVT::f64)
626 else if (LoadedVT == MVT::f32)
629 assert(0 && "Unaligned load of unsupported floating point type");
631 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
632 SVOffset, LD->isVolatile(),
634 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
636 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
638 SDOperand Ops[] = { Result, Chain };
639 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
642 assert((MVT::isInteger(LoadedVT) || MVT::isVector(LoadedVT)) &&
643 "Unaligned load of unsupported type.");
645 // Compute the new VT that is half the size of the old one. We either have an
646 // integer MVT or we have a vector MVT.
647 unsigned NumBits = MVT::getSizeInBits(LoadedVT);
648 MVT::ValueType NewLoadedVT;
649 if (!MVT::isVector(LoadedVT)) {
650 NewLoadedVT = MVT::getIntegerType(NumBits/2);
652 // FIXME: This is not right for <1 x anything> it is also not right for
653 // non-power-of-two vectors.
654 NewLoadedVT = MVT::getVectorType(MVT::getVectorElementType(LoadedVT),
655 MVT::getVectorNumElements(LoadedVT)/2);
659 unsigned Alignment = LD->getAlignment();
660 unsigned IncrementSize = NumBits / 8;
661 ISD::LoadExtType HiExtType = LD->getExtensionType();
663 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
664 if (HiExtType == ISD::NON_EXTLOAD)
665 HiExtType = ISD::ZEXTLOAD;
667 // Load the value in two parts
669 if (TLI.isLittleEndian()) {
670 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
671 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
672 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
673 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
674 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
675 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
676 MinAlign(Alignment, IncrementSize));
678 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
679 NewLoadedVT,LD->isVolatile(), Alignment);
680 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
681 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
682 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
683 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
684 MinAlign(Alignment, IncrementSize));
687 // aggregate the two parts
688 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
689 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
690 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
692 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
695 SDOperand Ops[] = { Result, TF };
696 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
699 /// UnrollVectorOp - We know that the given vector has a legal type, however
700 /// the operation it performs is not legal and is an operation that we have
701 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
702 /// operating on each element individually.
703 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
704 MVT::ValueType VT = Op.getValueType();
705 assert(isTypeLegal(VT) &&
706 "Caller should expand or promote operands that are not legal!");
707 assert(Op.Val->getNumValues() == 1 &&
708 "Can't unroll a vector with multiple results!");
709 unsigned NE = MVT::getVectorNumElements(VT);
710 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
712 SmallVector<SDOperand, 8> Scalars;
713 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
714 for (unsigned i = 0; i != NE; ++i) {
715 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
716 SDOperand Operand = Op.getOperand(j);
717 MVT::ValueType OperandVT = Operand.getValueType();
718 if (MVT::isVector(OperandVT)) {
719 // A vector operand; extract a single element.
720 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
721 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
724 DAG.getConstant(i, MVT::i32));
726 // A scalar operand; just use it as is.
727 Operands[j] = Operand;
730 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
731 &Operands[0], Operands.size()));
734 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
737 /// GetFPLibCall - Return the right libcall for the given floating point type.
738 static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
739 RTLIB::Libcall Call_F32,
740 RTLIB::Libcall Call_F64,
741 RTLIB::Libcall Call_F80,
742 RTLIB::Libcall Call_PPCF128) {
744 VT == MVT::f32 ? Call_F32 :
745 VT == MVT::f64 ? Call_F64 :
746 VT == MVT::f80 ? Call_F80 :
747 VT == MVT::ppcf128 ? Call_PPCF128 :
748 RTLIB::UNKNOWN_LIBCALL;
751 /// LegalizeOp - We know that the specified value has a legal type, and
752 /// that its operands are legal. Now ensure that the operation itself
753 /// is legal, recursively ensuring that the operands' operations remain
755 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
756 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
759 assert(isTypeLegal(Op.getValueType()) &&
760 "Caller should expand or promote operands that are not legal!");
761 SDNode *Node = Op.Val;
763 // If this operation defines any values that cannot be represented in a
764 // register on this target, make sure to expand or promote them.
765 if (Node->getNumValues() > 1) {
766 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
767 if (getTypeAction(Node->getValueType(i)) != Legal) {
768 HandleOp(Op.getValue(i));
769 assert(LegalizedNodes.count(Op) &&
770 "Handling didn't add legal operands!");
771 return LegalizedNodes[Op];
775 // Note that LegalizeOp may be reentered even from single-use nodes, which
776 // means that we always must cache transformed nodes.
777 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
778 if (I != LegalizedNodes.end()) return I->second;
780 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
781 SDOperand Result = Op;
782 bool isCustom = false;
784 switch (Node->getOpcode()) {
785 case ISD::FrameIndex:
786 case ISD::EntryToken:
788 case ISD::BasicBlock:
789 case ISD::TargetFrameIndex:
790 case ISD::TargetJumpTable:
791 case ISD::TargetConstant:
792 case ISD::TargetConstantFP:
793 case ISD::TargetConstantPool:
794 case ISD::TargetGlobalAddress:
795 case ISD::TargetGlobalTLSAddress:
796 case ISD::TargetExternalSymbol:
801 // Primitives must all be legal.
802 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
803 "This must be legal!");
806 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
807 // If this is a target node, legalize it by legalizing the operands then
808 // passing it through.
809 SmallVector<SDOperand, 8> Ops;
810 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
811 Ops.push_back(LegalizeOp(Node->getOperand(i)));
813 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
815 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
816 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
817 return Result.getValue(Op.ResNo);
819 // Otherwise this is an unhandled builtin node. splat.
821 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
823 assert(0 && "Do not know how to legalize this operator!");
825 case ISD::GLOBAL_OFFSET_TABLE:
826 case ISD::GlobalAddress:
827 case ISD::GlobalTLSAddress:
828 case ISD::ExternalSymbol:
829 case ISD::ConstantPool:
830 case ISD::JumpTable: // Nothing to do.
831 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
832 default: assert(0 && "This action is not supported yet!");
833 case TargetLowering::Custom:
834 Tmp1 = TLI.LowerOperation(Op, DAG);
835 if (Tmp1.Val) Result = Tmp1;
836 // FALLTHROUGH if the target doesn't want to lower this op after all.
837 case TargetLowering::Legal:
842 case ISD::RETURNADDR:
843 // The only option for these nodes is to custom lower them. If the target
844 // does not custom lower them, then return zero.
845 Tmp1 = TLI.LowerOperation(Op, DAG);
849 Result = DAG.getConstant(0, TLI.getPointerTy());
851 case ISD::FRAME_TO_ARGS_OFFSET: {
852 MVT::ValueType VT = Node->getValueType(0);
853 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
854 default: assert(0 && "This action is not supported yet!");
855 case TargetLowering::Custom:
856 Result = TLI.LowerOperation(Op, DAG);
857 if (Result.Val) break;
859 case TargetLowering::Legal:
860 Result = DAG.getConstant(0, VT);
865 case ISD::EXCEPTIONADDR: {
866 Tmp1 = LegalizeOp(Node->getOperand(0));
867 MVT::ValueType VT = Node->getValueType(0);
868 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
869 default: assert(0 && "This action is not supported yet!");
870 case TargetLowering::Expand: {
871 unsigned Reg = TLI.getExceptionAddressRegister();
872 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
875 case TargetLowering::Custom:
876 Result = TLI.LowerOperation(Op, DAG);
877 if (Result.Val) break;
879 case TargetLowering::Legal: {
880 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
881 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
887 if (Result.Val->getNumValues() == 1) break;
889 assert(Result.Val->getNumValues() == 2 &&
890 "Cannot return more than two values!");
892 // Since we produced two values, make sure to remember that we
893 // legalized both of them.
894 Tmp1 = LegalizeOp(Result);
895 Tmp2 = LegalizeOp(Result.getValue(1));
896 AddLegalizedOperand(Op.getValue(0), Tmp1);
897 AddLegalizedOperand(Op.getValue(1), Tmp2);
898 return Op.ResNo ? Tmp2 : Tmp1;
899 case ISD::EHSELECTION: {
900 Tmp1 = LegalizeOp(Node->getOperand(0));
901 Tmp2 = LegalizeOp(Node->getOperand(1));
902 MVT::ValueType VT = Node->getValueType(0);
903 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
904 default: assert(0 && "This action is not supported yet!");
905 case TargetLowering::Expand: {
906 unsigned Reg = TLI.getExceptionSelectorRegister();
907 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
910 case TargetLowering::Custom:
911 Result = TLI.LowerOperation(Op, DAG);
912 if (Result.Val) break;
914 case TargetLowering::Legal: {
915 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
916 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
922 if (Result.Val->getNumValues() == 1) break;
924 assert(Result.Val->getNumValues() == 2 &&
925 "Cannot return more than two values!");
927 // Since we produced two values, make sure to remember that we
928 // legalized both of them.
929 Tmp1 = LegalizeOp(Result);
930 Tmp2 = LegalizeOp(Result.getValue(1));
931 AddLegalizedOperand(Op.getValue(0), Tmp1);
932 AddLegalizedOperand(Op.getValue(1), Tmp2);
933 return Op.ResNo ? Tmp2 : Tmp1;
934 case ISD::EH_RETURN: {
935 MVT::ValueType VT = Node->getValueType(0);
936 // The only "good" option for this node is to custom lower it.
937 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
938 default: assert(0 && "This action is not supported at all!");
939 case TargetLowering::Custom:
940 Result = TLI.LowerOperation(Op, DAG);
941 if (Result.Val) break;
943 case TargetLowering::Legal:
944 // Target does not know, how to lower this, lower to noop
945 Result = LegalizeOp(Node->getOperand(0));
950 case ISD::AssertSext:
951 case ISD::AssertZext:
952 Tmp1 = LegalizeOp(Node->getOperand(0));
953 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
955 case ISD::MERGE_VALUES:
956 // Legalize eliminates MERGE_VALUES nodes.
957 Result = Node->getOperand(Op.ResNo);
959 case ISD::CopyFromReg:
960 Tmp1 = LegalizeOp(Node->getOperand(0));
961 Result = Op.getValue(0);
962 if (Node->getNumValues() == 2) {
963 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
965 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
966 if (Node->getNumOperands() == 3) {
967 Tmp2 = LegalizeOp(Node->getOperand(2));
968 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
970 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
972 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
974 // Since CopyFromReg produces two values, make sure to remember that we
975 // legalized both of them.
976 AddLegalizedOperand(Op.getValue(0), Result);
977 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
978 return Result.getValue(Op.ResNo);
980 MVT::ValueType VT = Op.getValueType();
981 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
982 default: assert(0 && "This action is not supported yet!");
983 case TargetLowering::Expand:
984 if (MVT::isInteger(VT))
985 Result = DAG.getConstant(0, VT);
986 else if (MVT::isFloatingPoint(VT))
987 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
990 assert(0 && "Unknown value type!");
992 case TargetLowering::Legal:
998 case ISD::INTRINSIC_W_CHAIN:
999 case ISD::INTRINSIC_WO_CHAIN:
1000 case ISD::INTRINSIC_VOID: {
1001 SmallVector<SDOperand, 8> Ops;
1002 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1003 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1004 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1006 // Allow the target to custom lower its intrinsics if it wants to.
1007 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1008 TargetLowering::Custom) {
1009 Tmp3 = TLI.LowerOperation(Result, DAG);
1010 if (Tmp3.Val) Result = Tmp3;
1013 if (Result.Val->getNumValues() == 1) break;
1015 // Must have return value and chain result.
1016 assert(Result.Val->getNumValues() == 2 &&
1017 "Cannot return more than two values!");
1019 // Since loads produce two values, make sure to remember that we
1020 // legalized both of them.
1021 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1022 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1023 return Result.getValue(Op.ResNo);
1027 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
1028 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1030 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
1031 case TargetLowering::Promote:
1032 default: assert(0 && "This action is not supported yet!");
1033 case TargetLowering::Expand: {
1034 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1035 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1036 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
1038 if (MMI && (useDEBUG_LOC || useLABEL)) {
1039 const std::string &FName =
1040 cast<StringSDNode>(Node->getOperand(3))->getValue();
1041 const std::string &DirName =
1042 cast<StringSDNode>(Node->getOperand(4))->getValue();
1043 unsigned SrcFile = MMI->RecordSource(DirName, FName);
1045 SmallVector<SDOperand, 8> Ops;
1046 Ops.push_back(Tmp1); // chain
1047 SDOperand LineOp = Node->getOperand(1);
1048 SDOperand ColOp = Node->getOperand(2);
1051 Ops.push_back(LineOp); // line #
1052 Ops.push_back(ColOp); // col #
1053 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1054 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1056 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
1057 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
1058 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
1059 Ops.push_back(DAG.getConstant(ID, MVT::i32));
1060 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
1063 Result = Tmp1; // chain
1067 case TargetLowering::Legal:
1068 if (Tmp1 != Node->getOperand(0) ||
1069 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1070 SmallVector<SDOperand, 8> Ops;
1071 Ops.push_back(Tmp1);
1072 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1073 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1074 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1076 // Otherwise promote them.
1077 Ops.push_back(PromoteOp(Node->getOperand(1)));
1078 Ops.push_back(PromoteOp(Node->getOperand(2)));
1080 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1081 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1082 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1088 case ISD::DEBUG_LOC:
1089 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1090 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1091 default: assert(0 && "This action is not supported yet!");
1092 case TargetLowering::Legal:
1093 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1094 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1095 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1096 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1097 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1103 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
1104 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1105 default: assert(0 && "This action is not supported yet!");
1106 case TargetLowering::Legal:
1107 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1108 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1109 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1111 case TargetLowering::Expand:
1112 Result = LegalizeOp(Node->getOperand(0));
1117 case ISD::Constant: {
1118 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1120 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1122 // We know we don't need to expand constants here, constants only have one
1123 // value and we check that it is fine above.
1125 if (opAction == TargetLowering::Custom) {
1126 Tmp1 = TLI.LowerOperation(Result, DAG);
1132 case ISD::ConstantFP: {
1133 // Spill FP immediates to the constant pool if the target cannot directly
1134 // codegen them. Targets often have some immediate values that can be
1135 // efficiently generated into an FP register without a load. We explicitly
1136 // leave these constants as ConstantFP nodes for the target to deal with.
1137 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1139 // Check to see if this FP immediate is already legal.
1140 bool isLegal = false;
1141 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1142 E = TLI.legal_fpimm_end(); I != E; ++I)
1143 if (CFP->isExactlyValue(*I)) {
1148 // If this is a legal constant, turn it into a TargetConstantFP node.
1150 Result = DAG.getTargetConstantFP(CFP->getValueAPF(),
1151 CFP->getValueType(0));
1155 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1156 default: assert(0 && "This action is not supported yet!");
1157 case TargetLowering::Custom:
1158 Tmp3 = TLI.LowerOperation(Result, DAG);
1164 case TargetLowering::Expand:
1165 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1169 case ISD::TokenFactor:
1170 if (Node->getNumOperands() == 2) {
1171 Tmp1 = LegalizeOp(Node->getOperand(0));
1172 Tmp2 = LegalizeOp(Node->getOperand(1));
1173 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1174 } else if (Node->getNumOperands() == 3) {
1175 Tmp1 = LegalizeOp(Node->getOperand(0));
1176 Tmp2 = LegalizeOp(Node->getOperand(1));
1177 Tmp3 = LegalizeOp(Node->getOperand(2));
1178 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1180 SmallVector<SDOperand, 8> Ops;
1181 // Legalize the operands.
1182 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1183 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1184 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1188 case ISD::FORMAL_ARGUMENTS:
1190 // The only option for this is to custom lower it.
1191 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1192 assert(Tmp3.Val && "Target didn't custom lower this node!");
1194 // The number of incoming and outgoing values should match; unless the final
1195 // outgoing value is a flag.
1196 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1197 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1198 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1200 "Lowering call/formal_arguments produced unexpected # results!");
1202 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1203 // remember that we legalized all of them, so it doesn't get relegalized.
1204 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1205 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1207 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1210 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1213 case ISD::EXTRACT_SUBREG: {
1214 Tmp1 = LegalizeOp(Node->getOperand(0));
1215 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1216 assert(idx && "Operand must be a constant");
1217 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1218 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1221 case ISD::INSERT_SUBREG: {
1222 Tmp1 = LegalizeOp(Node->getOperand(0));
1223 Tmp2 = LegalizeOp(Node->getOperand(1));
1224 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1225 assert(idx && "Operand must be a constant");
1226 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1227 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1230 case ISD::BUILD_VECTOR:
1231 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1232 default: assert(0 && "This action is not supported yet!");
1233 case TargetLowering::Custom:
1234 Tmp3 = TLI.LowerOperation(Result, DAG);
1240 case TargetLowering::Expand:
1241 Result = ExpandBUILD_VECTOR(Result.Val);
1245 case ISD::INSERT_VECTOR_ELT:
1246 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1247 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
1248 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1249 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1251 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1252 Node->getValueType(0))) {
1253 default: assert(0 && "This action is not supported yet!");
1254 case TargetLowering::Legal:
1256 case TargetLowering::Custom:
1257 Tmp4 = TLI.LowerOperation(Result, DAG);
1263 case TargetLowering::Expand: {
1264 // If the insert index is a constant, codegen this as a scalar_to_vector,
1265 // then a shuffle that inserts it into the right position in the vector.
1266 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1267 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1268 Tmp1.getValueType(), Tmp2);
1270 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1271 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1272 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1274 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
1275 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
1277 SmallVector<SDOperand, 8> ShufOps;
1278 for (unsigned i = 0; i != NumElts; ++i) {
1279 if (i != InsertPos->getValue())
1280 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1282 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1284 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1285 &ShufOps[0], ShufOps.size());
1287 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1288 Tmp1, ScVec, ShufMask);
1289 Result = LegalizeOp(Result);
1293 // If the target doesn't support this, we have to spill the input vector
1294 // to a temporary stack slot, update the element, then reload it. This is
1295 // badness. We could also load the value into a vector register (either
1296 // with a "move to register" or "extload into register" instruction, then
1297 // permute it into place, if the idx is a constant and if the idx is
1298 // supported by the target.
1299 MVT::ValueType VT = Tmp1.getValueType();
1300 MVT::ValueType EltVT = Tmp2.getValueType();
1301 MVT::ValueType IdxVT = Tmp3.getValueType();
1302 MVT::ValueType PtrVT = TLI.getPointerTy();
1303 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
1304 // Store the vector.
1305 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
1307 // Truncate or zero extend offset to target pointer type.
1308 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1309 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1310 // Add the offset to the index.
1311 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1312 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1313 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1314 // Store the scalar value.
1315 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
1316 // Load the updated vector.
1317 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1322 case ISD::SCALAR_TO_VECTOR:
1323 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1324 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1328 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1329 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1330 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1331 Node->getValueType(0))) {
1332 default: assert(0 && "This action is not supported yet!");
1333 case TargetLowering::Legal:
1335 case TargetLowering::Custom:
1336 Tmp3 = TLI.LowerOperation(Result, DAG);
1342 case TargetLowering::Expand:
1343 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1347 case ISD::VECTOR_SHUFFLE:
1348 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1349 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1350 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1352 // Allow targets to custom lower the SHUFFLEs they support.
1353 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1354 default: assert(0 && "Unknown operation action!");
1355 case TargetLowering::Legal:
1356 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1357 "vector shuffle should not be created if not legal!");
1359 case TargetLowering::Custom:
1360 Tmp3 = TLI.LowerOperation(Result, DAG);
1366 case TargetLowering::Expand: {
1367 MVT::ValueType VT = Node->getValueType(0);
1368 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1369 MVT::ValueType PtrVT = TLI.getPointerTy();
1370 SDOperand Mask = Node->getOperand(2);
1371 unsigned NumElems = Mask.getNumOperands();
1372 SmallVector<SDOperand,8> Ops;
1373 for (unsigned i = 0; i != NumElems; ++i) {
1374 SDOperand Arg = Mask.getOperand(i);
1375 if (Arg.getOpcode() == ISD::UNDEF) {
1376 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1378 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1379 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1381 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1382 DAG.getConstant(Idx, PtrVT)));
1384 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1385 DAG.getConstant(Idx - NumElems, PtrVT)));
1388 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1391 case TargetLowering::Promote: {
1392 // Change base type to a different vector type.
1393 MVT::ValueType OVT = Node->getValueType(0);
1394 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1396 // Cast the two input vectors.
1397 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1398 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1400 // Convert the shuffle mask to the right # elements.
1401 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1402 assert(Tmp3.Val && "Shuffle not legal?");
1403 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1404 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1410 case ISD::EXTRACT_VECTOR_ELT:
1411 Tmp1 = Node->getOperand(0);
1412 Tmp2 = LegalizeOp(Node->getOperand(1));
1413 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1414 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1417 case ISD::EXTRACT_SUBVECTOR:
1418 Tmp1 = Node->getOperand(0);
1419 Tmp2 = LegalizeOp(Node->getOperand(1));
1420 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1421 Result = ExpandEXTRACT_SUBVECTOR(Result);
1424 case ISD::CALLSEQ_START: {
1425 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1427 // Recursively Legalize all of the inputs of the call end that do not lead
1428 // to this call start. This ensures that any libcalls that need be inserted
1429 // are inserted *before* the CALLSEQ_START.
1430 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1431 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1432 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1436 // Now that we legalized all of the inputs (which may have inserted
1437 // libcalls) create the new CALLSEQ_START node.
1438 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1440 // Merge in the last call, to ensure that this call start after the last
1442 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1443 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1444 Tmp1 = LegalizeOp(Tmp1);
1447 // Do not try to legalize the target-specific arguments (#1+).
1448 if (Tmp1 != Node->getOperand(0)) {
1449 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1451 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1454 // Remember that the CALLSEQ_START is legalized.
1455 AddLegalizedOperand(Op.getValue(0), Result);
1456 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1457 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1459 // Now that the callseq_start and all of the non-call nodes above this call
1460 // sequence have been legalized, legalize the call itself. During this
1461 // process, no libcalls can/will be inserted, guaranteeing that no calls
1463 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1464 SDOperand InCallSEQ = LastCALLSEQ_END;
1465 // Note that we are selecting this call!
1466 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1467 IsLegalizingCall = true;
1469 // Legalize the call, starting from the CALLSEQ_END.
1470 LegalizeOp(LastCALLSEQ_END);
1471 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1474 case ISD::CALLSEQ_END:
1475 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1476 // will cause this node to be legalized as well as handling libcalls right.
1477 if (LastCALLSEQ_END.Val != Node) {
1478 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1479 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1480 assert(I != LegalizedNodes.end() &&
1481 "Legalizing the call start should have legalized this node!");
1485 // Otherwise, the call start has been legalized and everything is going
1486 // according to plan. Just legalize ourselves normally here.
1487 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1488 // Do not try to legalize the target-specific arguments (#1+), except for
1489 // an optional flag input.
1490 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1491 if (Tmp1 != Node->getOperand(0)) {
1492 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1494 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1497 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1498 if (Tmp1 != Node->getOperand(0) ||
1499 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1500 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1503 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1506 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1507 // This finishes up call legalization.
1508 IsLegalizingCall = false;
1510 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1511 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1512 if (Node->getNumValues() == 2)
1513 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1514 return Result.getValue(Op.ResNo);
1515 case ISD::DYNAMIC_STACKALLOC: {
1516 MVT::ValueType VT = Node->getValueType(0);
1517 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1518 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1519 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1520 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1522 Tmp1 = Result.getValue(0);
1523 Tmp2 = Result.getValue(1);
1524 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1525 default: assert(0 && "This action is not supported yet!");
1526 case TargetLowering::Expand: {
1527 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1528 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1529 " not tell us which reg is the stack pointer!");
1530 SDOperand Chain = Tmp1.getOperand(0);
1532 // Chain the dynamic stack allocation so that it doesn't modify the stack
1533 // pointer when other instructions are using the stack.
1534 Chain = DAG.getCALLSEQ_START(Chain,
1535 DAG.getConstant(0, TLI.getPointerTy()));
1537 SDOperand Size = Tmp2.getOperand(1);
1538 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1539 Chain = SP.getValue(1);
1540 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1541 unsigned StackAlign =
1542 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1543 if (Align > StackAlign)
1544 SP = DAG.getNode(ISD::AND, VT, SP,
1545 DAG.getConstant(-(uint64_t)Align, VT));
1546 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1547 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1550 DAG.getCALLSEQ_END(Chain,
1551 DAG.getConstant(0, TLI.getPointerTy()),
1552 DAG.getConstant(0, TLI.getPointerTy()),
1555 Tmp1 = LegalizeOp(Tmp1);
1556 Tmp2 = LegalizeOp(Tmp2);
1559 case TargetLowering::Custom:
1560 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1562 Tmp1 = LegalizeOp(Tmp3);
1563 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1566 case TargetLowering::Legal:
1569 // Since this op produce two values, make sure to remember that we
1570 // legalized both of them.
1571 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1572 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1573 return Op.ResNo ? Tmp2 : Tmp1;
1575 case ISD::INLINEASM: {
1576 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1577 bool Changed = false;
1578 // Legalize all of the operands of the inline asm, in case they are nodes
1579 // that need to be expanded or something. Note we skip the asm string and
1580 // all of the TargetConstant flags.
1581 SDOperand Op = LegalizeOp(Ops[0]);
1582 Changed = Op != Ops[0];
1585 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1586 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1587 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1588 for (++i; NumVals; ++i, --NumVals) {
1589 SDOperand Op = LegalizeOp(Ops[i]);
1598 Op = LegalizeOp(Ops.back());
1599 Changed |= Op != Ops.back();
1604 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1606 // INLINE asm returns a chain and flag, make sure to add both to the map.
1607 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1608 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1609 return Result.getValue(Op.ResNo);
1612 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1613 // Ensure that libcalls are emitted before a branch.
1614 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1615 Tmp1 = LegalizeOp(Tmp1);
1616 LastCALLSEQ_END = DAG.getEntryNode();
1618 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1621 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1622 // Ensure that libcalls are emitted before a branch.
1623 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1624 Tmp1 = LegalizeOp(Tmp1);
1625 LastCALLSEQ_END = DAG.getEntryNode();
1627 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1628 default: assert(0 && "Indirect target must be legal type (pointer)!");
1630 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1633 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1636 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1637 // Ensure that libcalls are emitted before a branch.
1638 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1639 Tmp1 = LegalizeOp(Tmp1);
1640 LastCALLSEQ_END = DAG.getEntryNode();
1642 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1643 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1645 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1646 default: assert(0 && "This action is not supported yet!");
1647 case TargetLowering::Legal: break;
1648 case TargetLowering::Custom:
1649 Tmp1 = TLI.LowerOperation(Result, DAG);
1650 if (Tmp1.Val) Result = Tmp1;
1652 case TargetLowering::Expand: {
1653 SDOperand Chain = Result.getOperand(0);
1654 SDOperand Table = Result.getOperand(1);
1655 SDOperand Index = Result.getOperand(2);
1657 MVT::ValueType PTy = TLI.getPointerTy();
1658 MachineFunction &MF = DAG.getMachineFunction();
1659 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1660 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1661 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1664 switch (EntrySize) {
1665 default: assert(0 && "Size of jump table not supported yet."); break;
1666 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1667 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1671 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1672 // For PIC, the sequence is:
1673 // BRIND(load(Jumptable + index) + RelocBase)
1674 // RelocBase can be JumpTable, GOT or some sort of global base.
1675 if (PTy != MVT::i32)
1676 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1677 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1678 TLI.getPICJumpTableRelocBase(Table, DAG));
1680 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1685 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1686 // Ensure that libcalls are emitted before a return.
1687 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1688 Tmp1 = LegalizeOp(Tmp1);
1689 LastCALLSEQ_END = DAG.getEntryNode();
1691 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1692 case Expand: assert(0 && "It's impossible to expand bools");
1694 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1697 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1699 // The top bits of the promoted condition are not necessarily zero, ensure
1700 // that the value is properly zero extended.
1701 if (!DAG.MaskedValueIsZero(Tmp2,
1702 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1703 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1707 // Basic block destination (Op#2) is always legal.
1708 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1710 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1711 default: assert(0 && "This action is not supported yet!");
1712 case TargetLowering::Legal: break;
1713 case TargetLowering::Custom:
1714 Tmp1 = TLI.LowerOperation(Result, DAG);
1715 if (Tmp1.Val) Result = Tmp1;
1717 case TargetLowering::Expand:
1718 // Expand brcond's setcc into its constituent parts and create a BR_CC
1720 if (Tmp2.getOpcode() == ISD::SETCC) {
1721 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1722 Tmp2.getOperand(0), Tmp2.getOperand(1),
1723 Node->getOperand(2));
1725 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1726 DAG.getCondCode(ISD::SETNE), Tmp2,
1727 DAG.getConstant(0, Tmp2.getValueType()),
1728 Node->getOperand(2));
1734 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1735 // Ensure that libcalls are emitted before a branch.
1736 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1737 Tmp1 = LegalizeOp(Tmp1);
1738 Tmp2 = Node->getOperand(2); // LHS
1739 Tmp3 = Node->getOperand(3); // RHS
1740 Tmp4 = Node->getOperand(1); // CC
1742 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1743 LastCALLSEQ_END = DAG.getEntryNode();
1745 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1746 // the LHS is a legal SETCC itself. In this case, we need to compare
1747 // the result against zero to select between true and false values.
1748 if (Tmp3.Val == 0) {
1749 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1750 Tmp4 = DAG.getCondCode(ISD::SETNE);
1753 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1754 Node->getOperand(4));
1756 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1757 default: assert(0 && "Unexpected action for BR_CC!");
1758 case TargetLowering::Legal: break;
1759 case TargetLowering::Custom:
1760 Tmp4 = TLI.LowerOperation(Result, DAG);
1761 if (Tmp4.Val) Result = Tmp4;
1766 LoadSDNode *LD = cast<LoadSDNode>(Node);
1767 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1768 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1770 ISD::LoadExtType ExtType = LD->getExtensionType();
1771 if (ExtType == ISD::NON_EXTLOAD) {
1772 MVT::ValueType VT = Node->getValueType(0);
1773 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1774 Tmp3 = Result.getValue(0);
1775 Tmp4 = Result.getValue(1);
1777 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1778 default: assert(0 && "This action is not supported yet!");
1779 case TargetLowering::Legal:
1780 // If this is an unaligned load and the target doesn't support it,
1782 if (!TLI.allowsUnalignedMemoryAccesses()) {
1783 unsigned ABIAlignment = TLI.getTargetData()->
1784 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1785 if (LD->getAlignment() < ABIAlignment){
1786 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1788 Tmp3 = Result.getOperand(0);
1789 Tmp4 = Result.getOperand(1);
1790 Tmp3 = LegalizeOp(Tmp3);
1791 Tmp4 = LegalizeOp(Tmp4);
1795 case TargetLowering::Custom:
1796 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1798 Tmp3 = LegalizeOp(Tmp1);
1799 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1802 case TargetLowering::Promote: {
1803 // Only promote a load of vector type to another.
1804 assert(MVT::isVector(VT) && "Cannot promote this load!");
1805 // Change base type to a different vector type.
1806 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1808 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1809 LD->getSrcValueOffset(),
1810 LD->isVolatile(), LD->getAlignment());
1811 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1812 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1816 // Since loads produce two values, make sure to remember that we
1817 // legalized both of them.
1818 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1819 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1820 return Op.ResNo ? Tmp4 : Tmp3;
1822 MVT::ValueType SrcVT = LD->getLoadedVT();
1823 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1824 default: assert(0 && "This action is not supported yet!");
1825 case TargetLowering::Promote:
1826 assert(SrcVT == MVT::i1 &&
1827 "Can only promote extending LOAD from i1 -> i8!");
1828 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1829 LD->getSrcValue(), LD->getSrcValueOffset(),
1830 MVT::i8, LD->isVolatile(), LD->getAlignment());
1831 Tmp1 = Result.getValue(0);
1832 Tmp2 = Result.getValue(1);
1834 case TargetLowering::Custom:
1837 case TargetLowering::Legal:
1838 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1839 Tmp1 = Result.getValue(0);
1840 Tmp2 = Result.getValue(1);
1843 Tmp3 = TLI.LowerOperation(Result, DAG);
1845 Tmp1 = LegalizeOp(Tmp3);
1846 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1849 // If this is an unaligned load and the target doesn't support it,
1851 if (!TLI.allowsUnalignedMemoryAccesses()) {
1852 unsigned ABIAlignment = TLI.getTargetData()->
1853 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1854 if (LD->getAlignment() < ABIAlignment){
1855 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1857 Tmp1 = Result.getOperand(0);
1858 Tmp2 = Result.getOperand(1);
1859 Tmp1 = LegalizeOp(Tmp1);
1860 Tmp2 = LegalizeOp(Tmp2);
1865 case TargetLowering::Expand:
1866 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1867 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1868 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1869 LD->getSrcValueOffset(),
1870 LD->isVolatile(), LD->getAlignment());
1871 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1872 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1873 Tmp2 = LegalizeOp(Load.getValue(1));
1876 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1877 // Turn the unsupported load into an EXTLOAD followed by an explicit
1878 // zero/sign extend inreg.
1879 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1880 Tmp1, Tmp2, LD->getSrcValue(),
1881 LD->getSrcValueOffset(), SrcVT,
1882 LD->isVolatile(), LD->getAlignment());
1884 if (ExtType == ISD::SEXTLOAD)
1885 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1886 Result, DAG.getValueType(SrcVT));
1888 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1889 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1890 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1893 // Since loads produce two values, make sure to remember that we legalized
1895 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1896 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1897 return Op.ResNo ? Tmp2 : Tmp1;
1900 case ISD::EXTRACT_ELEMENT: {
1901 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1902 switch (getTypeAction(OpTy)) {
1903 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1905 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1907 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1908 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1909 TLI.getShiftAmountTy()));
1910 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1913 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1914 Node->getOperand(0));
1918 // Get both the low and high parts.
1919 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1920 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1921 Result = Tmp2; // 1 -> Hi
1923 Result = Tmp1; // 0 -> Lo
1929 case ISD::CopyToReg:
1930 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1932 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1933 "Register type must be legal!");
1934 // Legalize the incoming value (must be a legal type).
1935 Tmp2 = LegalizeOp(Node->getOperand(2));
1936 if (Node->getNumValues() == 1) {
1937 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1939 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1940 if (Node->getNumOperands() == 4) {
1941 Tmp3 = LegalizeOp(Node->getOperand(3));
1942 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1945 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1948 // Since this produces two values, make sure to remember that we legalized
1950 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1951 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1957 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1959 // Ensure that libcalls are emitted before a return.
1960 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1961 Tmp1 = LegalizeOp(Tmp1);
1962 LastCALLSEQ_END = DAG.getEntryNode();
1964 switch (Node->getNumOperands()) {
1966 Tmp2 = Node->getOperand(1);
1967 Tmp3 = Node->getOperand(2); // Signness
1968 switch (getTypeAction(Tmp2.getValueType())) {
1970 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1973 if (!MVT::isVector(Tmp2.getValueType())) {
1975 ExpandOp(Tmp2, Lo, Hi);
1977 // Big endian systems want the hi reg first.
1978 if (!TLI.isLittleEndian())
1982 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1984 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1985 Result = LegalizeOp(Result);
1987 SDNode *InVal = Tmp2.Val;
1988 int InIx = Tmp2.ResNo;
1989 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
1990 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
1992 // Figure out if there is a simple type corresponding to this Vector
1993 // type. If so, convert to the vector type.
1994 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1995 if (TLI.isTypeLegal(TVT)) {
1996 // Turn this into a return of the vector type.
1997 Tmp2 = LegalizeOp(Tmp2);
1998 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1999 } else if (NumElems == 1) {
2000 // Turn this into a return of the scalar type.
2001 Tmp2 = ScalarizeVectorOp(Tmp2);
2002 Tmp2 = LegalizeOp(Tmp2);
2003 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2005 // FIXME: Returns of gcc generic vectors smaller than a legal type
2006 // should be returned in integer registers!
2008 // The scalarized value type may not be legal, e.g. it might require
2009 // promotion or expansion. Relegalize the return.
2010 Result = LegalizeOp(Result);
2012 // FIXME: Returns of gcc generic vectors larger than a legal vector
2013 // type should be returned by reference!
2015 SplitVectorOp(Tmp2, Lo, Hi);
2016 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2017 Result = LegalizeOp(Result);
2022 Tmp2 = PromoteOp(Node->getOperand(1));
2023 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2024 Result = LegalizeOp(Result);
2029 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2031 default: { // ret <values>
2032 SmallVector<SDOperand, 8> NewValues;
2033 NewValues.push_back(Tmp1);
2034 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2035 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2037 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2038 NewValues.push_back(Node->getOperand(i+1));
2042 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
2043 "FIXME: TODO: implement returning non-legal vector types!");
2044 ExpandOp(Node->getOperand(i), Lo, Hi);
2045 NewValues.push_back(Lo);
2046 NewValues.push_back(Node->getOperand(i+1));
2048 NewValues.push_back(Hi);
2049 NewValues.push_back(Node->getOperand(i+1));
2054 assert(0 && "Can't promote multiple return value yet!");
2057 if (NewValues.size() == Node->getNumOperands())
2058 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2060 Result = DAG.getNode(ISD::RET, MVT::Other,
2061 &NewValues[0], NewValues.size());
2066 if (Result.getOpcode() == ISD::RET) {
2067 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2068 default: assert(0 && "This action is not supported yet!");
2069 case TargetLowering::Legal: break;
2070 case TargetLowering::Custom:
2071 Tmp1 = TLI.LowerOperation(Result, DAG);
2072 if (Tmp1.Val) Result = Tmp1;
2078 StoreSDNode *ST = cast<StoreSDNode>(Node);
2079 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2080 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2081 int SVOffset = ST->getSrcValueOffset();
2082 unsigned Alignment = ST->getAlignment();
2083 bool isVolatile = ST->isVolatile();
2085 if (!ST->isTruncatingStore()) {
2086 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2087 // FIXME: We shouldn't do this for TargetConstantFP's.
2088 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2089 // to phase ordering between legalized code and the dag combiner. This
2090 // probably means that we need to integrate dag combiner and legalizer
2092 // We generally can't do this one for long doubles.
2093 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2094 if (CFP->getValueType(0) == MVT::f32 &&
2095 getTypeAction(MVT::i32) == Legal) {
2096 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF().
2097 convertToAPInt().getZExtValue(),
2099 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2100 SVOffset, isVolatile, Alignment);
2102 } else if (CFP->getValueType(0) == MVT::f64) {
2103 // If this target supports 64-bit registers, do a single 64-bit store.
2104 if (getTypeAction(MVT::i64) == Legal) {
2105 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2106 getZExtValue(), MVT::i64);
2107 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2108 SVOffset, isVolatile, Alignment);
2110 } else if (getTypeAction(MVT::i32) == Legal) {
2111 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2112 // stores. If the target supports neither 32- nor 64-bits, this
2113 // xform is certainly not worth it.
2114 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue();
2115 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32);
2116 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32);
2117 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
2119 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2120 SVOffset, isVolatile, Alignment);
2121 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2122 DAG.getIntPtrConstant(4));
2123 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2124 isVolatile, MinAlign(Alignment, 4U));
2126 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2132 switch (getTypeAction(ST->getStoredVT())) {
2134 Tmp3 = LegalizeOp(ST->getValue());
2135 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2138 MVT::ValueType VT = Tmp3.getValueType();
2139 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2140 default: assert(0 && "This action is not supported yet!");
2141 case TargetLowering::Legal:
2142 // If this is an unaligned store and the target doesn't support it,
2144 if (!TLI.allowsUnalignedMemoryAccesses()) {
2145 unsigned ABIAlignment = TLI.getTargetData()->
2146 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
2147 if (ST->getAlignment() < ABIAlignment)
2148 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2152 case TargetLowering::Custom:
2153 Tmp1 = TLI.LowerOperation(Result, DAG);
2154 if (Tmp1.Val) Result = Tmp1;
2156 case TargetLowering::Promote:
2157 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2158 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2159 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2160 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2161 ST->getSrcValue(), SVOffset, isVolatile,
2168 // Truncate the value and store the result.
2169 Tmp3 = PromoteOp(ST->getValue());
2170 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2171 SVOffset, ST->getStoredVT(),
2172 isVolatile, Alignment);
2176 unsigned IncrementSize = 0;
2179 // If this is a vector type, then we have to calculate the increment as
2180 // the product of the element size in bytes, and the number of elements
2181 // in the high half of the vector.
2182 if (MVT::isVector(ST->getValue().getValueType())) {
2183 SDNode *InVal = ST->getValue().Val;
2184 int InIx = ST->getValue().ResNo;
2185 MVT::ValueType InVT = InVal->getValueType(InIx);
2186 unsigned NumElems = MVT::getVectorNumElements(InVT);
2187 MVT::ValueType EVT = MVT::getVectorElementType(InVT);
2189 // Figure out if there is a simple type corresponding to this Vector
2190 // type. If so, convert to the vector type.
2191 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2192 if (TLI.isTypeLegal(TVT)) {
2193 // Turn this into a normal store of the vector type.
2194 Tmp3 = LegalizeOp(Node->getOperand(1));
2195 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2196 SVOffset, isVolatile, Alignment);
2197 Result = LegalizeOp(Result);
2199 } else if (NumElems == 1) {
2200 // Turn this into a normal store of the scalar type.
2201 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
2202 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2203 SVOffset, isVolatile, Alignment);
2204 // The scalarized value type may not be legal, e.g. it might require
2205 // promotion or expansion. Relegalize the scalar store.
2206 Result = LegalizeOp(Result);
2209 SplitVectorOp(Node->getOperand(1), Lo, Hi);
2210 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
2211 MVT::getSizeInBits(EVT)/8;
2214 ExpandOp(Node->getOperand(1), Lo, Hi);
2215 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2217 if (!TLI.isLittleEndian())
2221 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2222 SVOffset, isVolatile, Alignment);
2224 if (Hi.Val == NULL) {
2225 // Must be int <-> float one-to-one expansion.
2230 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2231 DAG.getIntPtrConstant(IncrementSize));
2232 assert(isTypeLegal(Tmp2.getValueType()) &&
2233 "Pointers must be legal!");
2234 SVOffset += IncrementSize;
2235 Alignment = MinAlign(Alignment, IncrementSize);
2236 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2237 SVOffset, isVolatile, Alignment);
2238 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2242 switch (getTypeAction(ST->getValue().getValueType())) {
2244 Tmp3 = LegalizeOp(ST->getValue());
2247 // We can promote the value, the truncstore will still take care of it.
2248 Tmp3 = PromoteOp(ST->getValue());
2251 // Just store the low part. This may become a non-trunc store, so make
2252 // sure to use getTruncStore, not UpdateNodeOperands below.
2253 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2254 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2255 SVOffset, MVT::i8, isVolatile, Alignment);
2258 // Unconditionally promote TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2259 if (ST->getStoredVT() == MVT::i1) {
2260 // Promote the bool to a mask then store.
2261 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
2262 DAG.getConstant(1, Tmp3.getValueType()));
2263 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2265 isVolatile, Alignment);
2266 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2267 Tmp2 != ST->getBasePtr()) {
2268 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2272 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
2273 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2274 default: assert(0 && "This action is not supported yet!");
2275 case TargetLowering::Legal:
2276 // If this is an unaligned store and the target doesn't support it,
2278 if (!TLI.allowsUnalignedMemoryAccesses()) {
2279 unsigned ABIAlignment = TLI.getTargetData()->
2280 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
2281 if (ST->getAlignment() < ABIAlignment)
2282 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2286 case TargetLowering::Custom:
2287 Result = TLI.LowerOperation(Result, DAG);
2294 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2295 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2297 case ISD::STACKSAVE:
2298 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2299 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2300 Tmp1 = Result.getValue(0);
2301 Tmp2 = Result.getValue(1);
2303 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2304 default: assert(0 && "This action is not supported yet!");
2305 case TargetLowering::Legal: break;
2306 case TargetLowering::Custom:
2307 Tmp3 = TLI.LowerOperation(Result, DAG);
2309 Tmp1 = LegalizeOp(Tmp3);
2310 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2313 case TargetLowering::Expand:
2314 // Expand to CopyFromReg if the target set
2315 // StackPointerRegisterToSaveRestore.
2316 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2317 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2318 Node->getValueType(0));
2319 Tmp2 = Tmp1.getValue(1);
2321 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2322 Tmp2 = Node->getOperand(0);
2327 // Since stacksave produce two values, make sure to remember that we
2328 // legalized both of them.
2329 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2330 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2331 return Op.ResNo ? Tmp2 : Tmp1;
2333 case ISD::STACKRESTORE:
2334 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2335 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2336 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2338 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2339 default: assert(0 && "This action is not supported yet!");
2340 case TargetLowering::Legal: break;
2341 case TargetLowering::Custom:
2342 Tmp1 = TLI.LowerOperation(Result, DAG);
2343 if (Tmp1.Val) Result = Tmp1;
2345 case TargetLowering::Expand:
2346 // Expand to CopyToReg if the target set
2347 // StackPointerRegisterToSaveRestore.
2348 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2349 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2357 case ISD::READCYCLECOUNTER:
2358 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2359 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2360 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2361 Node->getValueType(0))) {
2362 default: assert(0 && "This action is not supported yet!");
2363 case TargetLowering::Legal:
2364 Tmp1 = Result.getValue(0);
2365 Tmp2 = Result.getValue(1);
2367 case TargetLowering::Custom:
2368 Result = TLI.LowerOperation(Result, DAG);
2369 Tmp1 = LegalizeOp(Result.getValue(0));
2370 Tmp2 = LegalizeOp(Result.getValue(1));
2374 // Since rdcc produce two values, make sure to remember that we legalized
2376 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2377 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2381 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2382 case Expand: assert(0 && "It's impossible to expand bools");
2384 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2387 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2388 // Make sure the condition is either zero or one.
2389 if (!DAG.MaskedValueIsZero(Tmp1,
2390 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2391 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2394 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2395 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2397 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2399 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2400 default: assert(0 && "This action is not supported yet!");
2401 case TargetLowering::Legal: break;
2402 case TargetLowering::Custom: {
2403 Tmp1 = TLI.LowerOperation(Result, DAG);
2404 if (Tmp1.Val) Result = Tmp1;
2407 case TargetLowering::Expand:
2408 if (Tmp1.getOpcode() == ISD::SETCC) {
2409 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2411 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2413 Result = DAG.getSelectCC(Tmp1,
2414 DAG.getConstant(0, Tmp1.getValueType()),
2415 Tmp2, Tmp3, ISD::SETNE);
2418 case TargetLowering::Promote: {
2419 MVT::ValueType NVT =
2420 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2421 unsigned ExtOp, TruncOp;
2422 if (MVT::isVector(Tmp2.getValueType())) {
2423 ExtOp = ISD::BIT_CONVERT;
2424 TruncOp = ISD::BIT_CONVERT;
2425 } else if (MVT::isInteger(Tmp2.getValueType())) {
2426 ExtOp = ISD::ANY_EXTEND;
2427 TruncOp = ISD::TRUNCATE;
2429 ExtOp = ISD::FP_EXTEND;
2430 TruncOp = ISD::FP_ROUND;
2432 // Promote each of the values to the new type.
2433 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2434 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2435 // Perform the larger operation, then round down.
2436 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2437 if (TruncOp != ISD::FP_ROUND)
2438 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2440 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2441 DAG.getIntPtrConstant(0));
2446 case ISD::SELECT_CC: {
2447 Tmp1 = Node->getOperand(0); // LHS
2448 Tmp2 = Node->getOperand(1); // RHS
2449 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2450 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2451 SDOperand CC = Node->getOperand(4);
2453 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2455 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2456 // the LHS is a legal SETCC itself. In this case, we need to compare
2457 // the result against zero to select between true and false values.
2458 if (Tmp2.Val == 0) {
2459 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2460 CC = DAG.getCondCode(ISD::SETNE);
2462 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2464 // Everything is legal, see if we should expand this op or something.
2465 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2466 default: assert(0 && "This action is not supported yet!");
2467 case TargetLowering::Legal: break;
2468 case TargetLowering::Custom:
2469 Tmp1 = TLI.LowerOperation(Result, DAG);
2470 if (Tmp1.Val) Result = Tmp1;
2476 Tmp1 = Node->getOperand(0);
2477 Tmp2 = Node->getOperand(1);
2478 Tmp3 = Node->getOperand(2);
2479 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2481 // If we had to Expand the SetCC operands into a SELECT node, then it may
2482 // not always be possible to return a true LHS & RHS. In this case, just
2483 // return the value we legalized, returned in the LHS
2484 if (Tmp2.Val == 0) {
2489 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2490 default: assert(0 && "Cannot handle this action for SETCC yet!");
2491 case TargetLowering::Custom:
2494 case TargetLowering::Legal:
2495 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2497 Tmp4 = TLI.LowerOperation(Result, DAG);
2498 if (Tmp4.Val) Result = Tmp4;
2501 case TargetLowering::Promote: {
2502 // First step, figure out the appropriate operation to use.
2503 // Allow SETCC to not be supported for all legal data types
2504 // Mostly this targets FP
2505 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2506 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2508 // Scan for the appropriate larger type to use.
2510 NewInTy = (MVT::ValueType)(NewInTy+1);
2512 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2513 "Fell off of the edge of the integer world");
2514 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2515 "Fell off of the edge of the floating point world");
2517 // If the target supports SETCC of this type, use it.
2518 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2521 if (MVT::isInteger(NewInTy))
2522 assert(0 && "Cannot promote Legal Integer SETCC yet");
2524 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2525 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2527 Tmp1 = LegalizeOp(Tmp1);
2528 Tmp2 = LegalizeOp(Tmp2);
2529 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2530 Result = LegalizeOp(Result);
2533 case TargetLowering::Expand:
2534 // Expand a setcc node into a select_cc of the same condition, lhs, and
2535 // rhs that selects between const 1 (true) and const 0 (false).
2536 MVT::ValueType VT = Node->getValueType(0);
2537 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2538 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2545 case ISD::MEMMOVE: {
2546 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2547 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2549 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2550 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2551 case Expand: assert(0 && "Cannot expand a byte!");
2553 Tmp3 = LegalizeOp(Node->getOperand(2));
2556 Tmp3 = PromoteOp(Node->getOperand(2));
2560 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2564 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2566 // Length is too big, just take the lo-part of the length.
2568 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2572 Tmp4 = LegalizeOp(Node->getOperand(3));
2575 Tmp4 = PromoteOp(Node->getOperand(3));
2580 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2581 case Expand: assert(0 && "Cannot expand this yet!");
2583 Tmp5 = LegalizeOp(Node->getOperand(4));
2586 Tmp5 = PromoteOp(Node->getOperand(4));
2591 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool
2592 case Expand: assert(0 && "Cannot expand this yet!");
2594 Tmp6 = LegalizeOp(Node->getOperand(5));
2597 Tmp6 = PromoteOp(Node->getOperand(5));
2601 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2602 default: assert(0 && "This action not implemented for this operation!");
2603 case TargetLowering::Custom:
2606 case TargetLowering::Legal: {
2607 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 };
2608 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
2610 Tmp1 = TLI.LowerOperation(Result, DAG);
2611 if (Tmp1.Val) Result = Tmp1;
2615 case TargetLowering::Expand: {
2616 // Otherwise, the target does not support this operation. Lower the
2617 // operation to an explicit libcall as appropriate.
2618 MVT::ValueType IntPtr = TLI.getPointerTy();
2619 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2620 TargetLowering::ArgListTy Args;
2621 TargetLowering::ArgListEntry Entry;
2623 const char *FnName = 0;
2624 if (Node->getOpcode() == ISD::MEMSET) {
2625 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2626 Args.push_back(Entry);
2627 // Extend the (previously legalized) ubyte argument to be an int value
2629 if (Tmp3.getValueType() > MVT::i32)
2630 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2632 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2633 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2634 Args.push_back(Entry);
2635 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2636 Args.push_back(Entry);
2639 } else if (Node->getOpcode() == ISD::MEMCPY ||
2640 Node->getOpcode() == ISD::MEMMOVE) {
2641 Entry.Ty = IntPtrTy;
2642 Entry.Node = Tmp2; Args.push_back(Entry);
2643 Entry.Node = Tmp3; Args.push_back(Entry);
2644 Entry.Node = Tmp4; Args.push_back(Entry);
2645 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2647 assert(0 && "Unknown op!");
2650 std::pair<SDOperand,SDOperand> CallResult =
2651 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2652 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2653 Result = CallResult.second;
2660 case ISD::SHL_PARTS:
2661 case ISD::SRA_PARTS:
2662 case ISD::SRL_PARTS: {
2663 SmallVector<SDOperand, 8> Ops;
2664 bool Changed = false;
2665 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2666 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2667 Changed |= Ops.back() != Node->getOperand(i);
2670 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2672 switch (TLI.getOperationAction(Node->getOpcode(),
2673 Node->getValueType(0))) {
2674 default: assert(0 && "This action is not supported yet!");
2675 case TargetLowering::Legal: break;
2676 case TargetLowering::Custom:
2677 Tmp1 = TLI.LowerOperation(Result, DAG);
2679 SDOperand Tmp2, RetVal(0, 0);
2680 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2681 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2682 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2686 assert(RetVal.Val && "Illegal result number");
2692 // Since these produce multiple values, make sure to remember that we
2693 // legalized all of them.
2694 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2695 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2696 return Result.getValue(Op.ResNo);
2718 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2719 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2720 case Expand: assert(0 && "Not possible");
2722 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2725 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2729 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2731 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2732 default: assert(0 && "BinOp legalize operation not supported");
2733 case TargetLowering::Legal: break;
2734 case TargetLowering::Custom:
2735 Tmp1 = TLI.LowerOperation(Result, DAG);
2736 if (Tmp1.Val) Result = Tmp1;
2738 case TargetLowering::Expand: {
2739 MVT::ValueType VT = Op.getValueType();
2741 // See if multiply or divide can be lowered using two-result operations.
2742 SDVTList VTs = DAG.getVTList(VT, VT);
2743 if (Node->getOpcode() == ISD::MUL) {
2744 // We just need the low half of the multiply; try both the signed
2745 // and unsigned forms. If the target supports both SMUL_LOHI and
2746 // UMUL_LOHI, form a preference by checking which forms of plain
2747 // MULH it supports.
2748 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2749 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2750 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2751 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2752 unsigned OpToUse = 0;
2753 if (HasSMUL_LOHI && !HasMULHS) {
2754 OpToUse = ISD::SMUL_LOHI;
2755 } else if (HasUMUL_LOHI && !HasMULHU) {
2756 OpToUse = ISD::UMUL_LOHI;
2757 } else if (HasSMUL_LOHI) {
2758 OpToUse = ISD::SMUL_LOHI;
2759 } else if (HasUMUL_LOHI) {
2760 OpToUse = ISD::UMUL_LOHI;
2763 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
2767 if (Node->getOpcode() == ISD::MULHS &&
2768 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
2769 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2772 if (Node->getOpcode() == ISD::MULHU &&
2773 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
2774 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2777 if (Node->getOpcode() == ISD::SDIV &&
2778 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
2779 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2782 if (Node->getOpcode() == ISD::UDIV &&
2783 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
2784 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2788 // Check to see if we have a libcall for this operator.
2789 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2790 bool isSigned = false;
2791 switch (Node->getOpcode()) {
2794 if (VT == MVT::i32) {
2795 LC = Node->getOpcode() == ISD::UDIV
2796 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2797 isSigned = Node->getOpcode() == ISD::SDIV;
2801 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
2802 RTLIB::POW_PPCF128);
2806 if (LC != RTLIB::UNKNOWN_LIBCALL) {
2808 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2812 assert(MVT::isVector(Node->getValueType(0)) &&
2813 "Cannot expand this binary operator!");
2814 // Expand the operation into a bunch of nasty scalar code.
2815 Result = LegalizeOp(UnrollVectorOp(Op));
2818 case TargetLowering::Promote: {
2819 switch (Node->getOpcode()) {
2820 default: assert(0 && "Do not know how to promote this BinOp!");
2824 MVT::ValueType OVT = Node->getValueType(0);
2825 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2826 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2827 // Bit convert each of the values to the new type.
2828 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2829 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2830 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2831 // Bit convert the result back the original type.
2832 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2840 case ISD::SMUL_LOHI:
2841 case ISD::UMUL_LOHI:
2844 // These nodes will only be produced by target-specific lowering, so
2845 // they shouldn't be here if they aren't legal.
2846 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2847 "This must be legal!");
2849 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2850 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2851 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2854 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2855 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2856 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2857 case Expand: assert(0 && "Not possible");
2859 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2862 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2866 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2868 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2869 default: assert(0 && "Operation not supported");
2870 case TargetLowering::Custom:
2871 Tmp1 = TLI.LowerOperation(Result, DAG);
2872 if (Tmp1.Val) Result = Tmp1;
2874 case TargetLowering::Legal: break;
2875 case TargetLowering::Expand: {
2876 // If this target supports fabs/fneg natively and select is cheap,
2877 // do this efficiently.
2878 if (!TLI.isSelectExpensive() &&
2879 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
2880 TargetLowering::Legal &&
2881 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
2882 TargetLowering::Legal) {
2883 // Get the sign bit of the RHS.
2884 MVT::ValueType IVT =
2885 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2886 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2887 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2888 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2889 // Get the absolute value of the result.
2890 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2891 // Select between the nabs and abs value based on the sign bit of
2893 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2894 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2897 Result = LegalizeOp(Result);
2901 // Otherwise, do bitwise ops!
2902 MVT::ValueType NVT =
2903 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
2904 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
2905 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
2906 Result = LegalizeOp(Result);
2914 Tmp1 = LegalizeOp(Node->getOperand(0));
2915 Tmp2 = LegalizeOp(Node->getOperand(1));
2916 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2917 // Since this produces two values, make sure to remember that we legalized
2919 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2920 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2925 Tmp1 = LegalizeOp(Node->getOperand(0));
2926 Tmp2 = LegalizeOp(Node->getOperand(1));
2927 Tmp3 = LegalizeOp(Node->getOperand(2));
2928 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2929 // Since this produces two values, make sure to remember that we legalized
2931 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2932 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2935 case ISD::BUILD_PAIR: {
2936 MVT::ValueType PairTy = Node->getValueType(0);
2937 // TODO: handle the case where the Lo and Hi operands are not of legal type
2938 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2939 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2940 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2941 case TargetLowering::Promote:
2942 case TargetLowering::Custom:
2943 assert(0 && "Cannot promote/custom this yet!");
2944 case TargetLowering::Legal:
2945 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2946 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2948 case TargetLowering::Expand:
2949 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2950 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2951 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2952 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2953 TLI.getShiftAmountTy()));
2954 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2963 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2964 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2966 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2967 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2968 case TargetLowering::Custom:
2971 case TargetLowering::Legal:
2972 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2974 Tmp1 = TLI.LowerOperation(Result, DAG);
2975 if (Tmp1.Val) Result = Tmp1;
2978 case TargetLowering::Expand: {
2979 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2980 bool isSigned = DivOpc == ISD::SDIV;
2981 MVT::ValueType VT = Node->getValueType(0);
2983 // See if remainder can be lowered using two-result operations.
2984 SDVTList VTs = DAG.getVTList(VT, VT);
2985 if (Node->getOpcode() == ISD::SREM &&
2986 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
2987 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
2990 if (Node->getOpcode() == ISD::UREM &&
2991 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
2992 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
2996 if (MVT::isInteger(VT)) {
2997 if (TLI.getOperationAction(DivOpc, VT) ==
2998 TargetLowering::Legal) {
3000 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3001 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3002 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3003 } else if (MVT::isVector(VT)) {
3004 Result = LegalizeOp(UnrollVectorOp(Op));
3006 assert(VT == MVT::i32 &&
3007 "Cannot expand this binary operator!");
3008 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3009 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3011 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3014 assert(MVT::isFloatingPoint(VT) &&
3015 "remainder op must have integer or floating-point type");
3016 if (MVT::isVector(VT)) {
3017 Result = LegalizeOp(UnrollVectorOp(Op));
3019 // Floating point mod -> fmod libcall.
3020 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3021 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3023 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3024 false/*sign irrelevant*/, Dummy);
3032 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3033 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3035 MVT::ValueType VT = Node->getValueType(0);
3036 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3037 default: assert(0 && "This action is not supported yet!");
3038 case TargetLowering::Custom:
3041 case TargetLowering::Legal:
3042 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3043 Result = Result.getValue(0);
3044 Tmp1 = Result.getValue(1);
3047 Tmp2 = TLI.LowerOperation(Result, DAG);
3049 Result = LegalizeOp(Tmp2);
3050 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3054 case TargetLowering::Expand: {
3055 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3056 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3057 SV->getValue(), SV->getOffset());
3058 // Increment the pointer, VAList, to the next vaarg
3059 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3060 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3061 TLI.getPointerTy()));
3062 // Store the incremented VAList to the legalized pointer
3063 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3065 // Load the actual argument out of the pointer VAList
3066 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3067 Tmp1 = LegalizeOp(Result.getValue(1));
3068 Result = LegalizeOp(Result);
3072 // Since VAARG produces two values, make sure to remember that we
3073 // legalized both of them.
3074 AddLegalizedOperand(SDOperand(Node, 0), Result);
3075 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3076 return Op.ResNo ? Tmp1 : Result;
3080 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3081 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3082 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3084 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3085 default: assert(0 && "This action is not supported yet!");
3086 case TargetLowering::Custom:
3089 case TargetLowering::Legal:
3090 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3091 Node->getOperand(3), Node->getOperand(4));
3093 Tmp1 = TLI.LowerOperation(Result, DAG);
3094 if (Tmp1.Val) Result = Tmp1;
3097 case TargetLowering::Expand:
3098 // This defaults to loading a pointer from the input and storing it to the
3099 // output, returning the chain.
3100 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
3101 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
3102 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
3104 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
3111 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3112 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3114 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3115 default: assert(0 && "This action is not supported yet!");
3116 case TargetLowering::Custom:
3119 case TargetLowering::Legal:
3120 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3122 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3123 if (Tmp1.Val) Result = Tmp1;
3126 case TargetLowering::Expand:
3127 Result = Tmp1; // Default to a no-op, return the chain
3133 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3134 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3136 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3138 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3139 default: assert(0 && "This action is not supported yet!");
3140 case TargetLowering::Legal: break;
3141 case TargetLowering::Custom:
3142 Tmp1 = TLI.LowerOperation(Result, DAG);
3143 if (Tmp1.Val) Result = Tmp1;
3150 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3151 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3152 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3153 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3155 assert(0 && "ROTL/ROTR legalize operation not supported");
3157 case TargetLowering::Legal:
3159 case TargetLowering::Custom:
3160 Tmp1 = TLI.LowerOperation(Result, DAG);
3161 if (Tmp1.Val) Result = Tmp1;
3163 case TargetLowering::Promote:
3164 assert(0 && "Do not know how to promote ROTL/ROTR");
3166 case TargetLowering::Expand:
3167 assert(0 && "Do not know how to expand ROTL/ROTR");
3173 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3174 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3175 case TargetLowering::Custom:
3176 assert(0 && "Cannot custom legalize this yet!");
3177 case TargetLowering::Legal:
3178 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3180 case TargetLowering::Promote: {
3181 MVT::ValueType OVT = Tmp1.getValueType();
3182 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3183 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
3185 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3186 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3187 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3188 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3191 case TargetLowering::Expand:
3192 Result = ExpandBSWAP(Tmp1);
3200 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3201 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3202 case TargetLowering::Custom:
3203 case TargetLowering::Legal:
3204 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3205 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3206 TargetLowering::Custom) {
3207 Tmp1 = TLI.LowerOperation(Result, DAG);
3213 case TargetLowering::Promote: {
3214 MVT::ValueType OVT = Tmp1.getValueType();
3215 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3217 // Zero extend the argument.
3218 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3219 // Perform the larger operation, then subtract if needed.
3220 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3221 switch (Node->getOpcode()) {
3226 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3227 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3228 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3230 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3231 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
3234 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3235 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3236 DAG.getConstant(MVT::getSizeInBits(NVT) -
3237 MVT::getSizeInBits(OVT), NVT));
3242 case TargetLowering::Expand:
3243 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3254 Tmp1 = LegalizeOp(Node->getOperand(0));
3255 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3256 case TargetLowering::Promote:
3257 case TargetLowering::Custom:
3260 case TargetLowering::Legal:
3261 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3263 Tmp1 = TLI.LowerOperation(Result, DAG);
3264 if (Tmp1.Val) Result = Tmp1;
3267 case TargetLowering::Expand:
3268 switch (Node->getOpcode()) {
3269 default: assert(0 && "Unreachable!");
3271 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3272 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3273 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3276 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3277 MVT::ValueType VT = Node->getValueType(0);
3278 Tmp2 = DAG.getConstantFP(0.0, VT);
3279 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
3280 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3281 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3287 MVT::ValueType VT = Node->getValueType(0);
3289 // Expand unsupported unary vector operators by unrolling them.
3290 if (MVT::isVector(VT)) {
3291 Result = LegalizeOp(UnrollVectorOp(Op));
3295 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3296 switch(Node->getOpcode()) {
3298 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3299 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3302 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3303 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3306 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3307 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3309 default: assert(0 && "Unreachable!");
3312 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3313 false/*sign irrelevant*/, Dummy);
3321 MVT::ValueType VT = Node->getValueType(0);
3323 // Expand unsupported unary vector operators by unrolling them.
3324 if (MVT::isVector(VT)) {
3325 Result = LegalizeOp(UnrollVectorOp(Op));
3329 // We always lower FPOWI into a libcall. No target support for it yet.
3330 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3331 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3333 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3334 false/*sign irrelevant*/, Dummy);
3337 case ISD::BIT_CONVERT:
3338 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3339 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3340 Node->getValueType(0));
3341 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3342 // The input has to be a vector type, we have to either scalarize it, pack
3343 // it, or convert it based on whether the input vector type is legal.
3344 SDNode *InVal = Node->getOperand(0).Val;
3345 int InIx = Node->getOperand(0).ResNo;
3346 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
3347 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
3349 // Figure out if there is a simple type corresponding to this Vector
3350 // type. If so, convert to the vector type.
3351 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3352 if (TLI.isTypeLegal(TVT)) {
3353 // Turn this into a bit convert of the vector input.
3354 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3355 LegalizeOp(Node->getOperand(0)));
3357 } else if (NumElems == 1) {
3358 // Turn this into a bit convert of the scalar input.
3359 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3360 ScalarizeVectorOp(Node->getOperand(0)));
3363 // FIXME: UNIMP! Store then reload
3364 assert(0 && "Cast from unsupported vector type not implemented yet!");
3367 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3368 Node->getOperand(0).getValueType())) {
3369 default: assert(0 && "Unknown operation action!");
3370 case TargetLowering::Expand:
3371 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3372 Node->getValueType(0));
3374 case TargetLowering::Legal:
3375 Tmp1 = LegalizeOp(Node->getOperand(0));
3376 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3382 // Conversion operators. The source and destination have different types.
3383 case ISD::SINT_TO_FP:
3384 case ISD::UINT_TO_FP: {
3385 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3386 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3388 switch (TLI.getOperationAction(Node->getOpcode(),
3389 Node->getOperand(0).getValueType())) {
3390 default: assert(0 && "Unknown operation action!");
3391 case TargetLowering::Custom:
3394 case TargetLowering::Legal:
3395 Tmp1 = LegalizeOp(Node->getOperand(0));
3396 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3398 Tmp1 = TLI.LowerOperation(Result, DAG);
3399 if (Tmp1.Val) Result = Tmp1;
3402 case TargetLowering::Expand:
3403 Result = ExpandLegalINT_TO_FP(isSigned,
3404 LegalizeOp(Node->getOperand(0)),
3405 Node->getValueType(0));
3407 case TargetLowering::Promote:
3408 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3409 Node->getValueType(0),
3415 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3416 Node->getValueType(0), Node->getOperand(0));
3419 Tmp1 = PromoteOp(Node->getOperand(0));
3421 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3422 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3424 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3425 Node->getOperand(0).getValueType());
3427 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3428 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3434 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3436 Tmp1 = LegalizeOp(Node->getOperand(0));
3437 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3440 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3442 // Since the result is legal, we should just be able to truncate the low
3443 // part of the source.
3444 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3447 Result = PromoteOp(Node->getOperand(0));
3448 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3453 case ISD::FP_TO_SINT:
3454 case ISD::FP_TO_UINT:
3455 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3457 Tmp1 = LegalizeOp(Node->getOperand(0));
3459 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3460 default: assert(0 && "Unknown operation action!");
3461 case TargetLowering::Custom:
3464 case TargetLowering::Legal:
3465 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3467 Tmp1 = TLI.LowerOperation(Result, DAG);
3468 if (Tmp1.Val) Result = Tmp1;
3471 case TargetLowering::Promote:
3472 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3473 Node->getOpcode() == ISD::FP_TO_SINT);
3475 case TargetLowering::Expand:
3476 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3477 SDOperand True, False;
3478 MVT::ValueType VT = Node->getOperand(0).getValueType();
3479 MVT::ValueType NVT = Node->getValueType(0);
3480 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1;
3481 const uint64_t zero[] = {0, 0};
3482 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3483 uint64_t x = 1ULL << ShiftAmt;
3484 (void)apf.convertFromZeroExtendedInteger
3485 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven);
3486 Tmp2 = DAG.getConstantFP(apf, VT);
3487 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3488 Node->getOperand(0), Tmp2, ISD::SETLT);
3489 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3490 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3491 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3493 False = DAG.getNode(ISD::XOR, NVT, False,
3494 DAG.getConstant(1ULL << ShiftAmt, NVT));
3495 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3498 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3504 MVT::ValueType VT = Op.getValueType();
3505 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3506 // Convert ppcf128 to i32
3507 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3508 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3509 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3510 Node->getOperand(0), DAG.getValueType(MVT::f64));
3511 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3512 DAG.getIntPtrConstant(1));
3513 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3515 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3516 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3517 Tmp2 = DAG.getConstantFP(apf, OVT);
3518 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3519 // FIXME: generated code sucks.
3520 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3521 DAG.getNode(ISD::ADD, MVT::i32,
3522 DAG.getNode(ISD::FP_TO_SINT, VT,
3523 DAG.getNode(ISD::FSUB, OVT,
3524 Node->getOperand(0), Tmp2)),
3525 DAG.getConstant(0x80000000, MVT::i32)),
3526 DAG.getNode(ISD::FP_TO_SINT, VT,
3527 Node->getOperand(0)),
3528 DAG.getCondCode(ISD::SETGE));
3532 // Convert f32 / f64 to i32 / i64.
3533 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3534 switch (Node->getOpcode()) {
3535 case ISD::FP_TO_SINT: {
3536 if (OVT == MVT::f32)
3537 LC = (VT == MVT::i32)
3538 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3539 else if (OVT == MVT::f64)
3540 LC = (VT == MVT::i32)
3541 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3542 else if (OVT == MVT::f80) {
3543 assert(VT == MVT::i64);
3544 LC = RTLIB::FPTOSINT_F80_I64;
3546 else if (OVT == MVT::ppcf128) {
3547 assert(VT == MVT::i64);
3548 LC = RTLIB::FPTOSINT_PPCF128_I64;
3552 case ISD::FP_TO_UINT: {
3553 if (OVT == MVT::f32)
3554 LC = (VT == MVT::i32)
3555 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3556 else if (OVT == MVT::f64)
3557 LC = (VT == MVT::i32)
3558 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3559 else if (OVT == MVT::f80) {
3560 LC = (VT == MVT::i32)
3561 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64;
3563 else if (OVT == MVT::ppcf128) {
3564 assert(VT == MVT::i64);
3565 LC = RTLIB::FPTOUINT_PPCF128_I64;
3569 default: assert(0 && "Unreachable!");
3572 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3573 false/*sign irrelevant*/, Dummy);
3577 Tmp1 = PromoteOp(Node->getOperand(0));
3578 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3579 Result = LegalizeOp(Result);
3584 case ISD::FP_EXTEND: {
3585 MVT::ValueType DstVT = Op.getValueType();
3586 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3587 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3588 // The only other way we can lower this is to turn it into a STORE,
3589 // LOAD pair, targetting a temporary location (a stack slot).
3590 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3593 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3594 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3596 Tmp1 = LegalizeOp(Node->getOperand(0));
3597 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3600 Tmp1 = PromoteOp(Node->getOperand(0));
3601 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3606 case ISD::FP_ROUND: {
3607 MVT::ValueType DstVT = Op.getValueType();
3608 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3609 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3610 if (SrcVT == MVT::ppcf128) {
3612 ExpandOp(Node->getOperand(0), Lo, Hi);
3613 // Round it the rest of the way (e.g. to f32) if needed.
3614 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Hi, Op.getOperand(1));
3617 // The only other way we can lower this is to turn it into a STORE,
3618 // LOAD pair, targetting a temporary location (a stack slot).
3619 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3622 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3623 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3625 Tmp1 = LegalizeOp(Node->getOperand(0));
3626 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3629 Tmp1 = PromoteOp(Node->getOperand(0));
3630 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3631 Node->getOperand(1));
3636 case ISD::ANY_EXTEND:
3637 case ISD::ZERO_EXTEND:
3638 case ISD::SIGN_EXTEND:
3639 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3640 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3642 Tmp1 = LegalizeOp(Node->getOperand(0));
3643 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3646 switch (Node->getOpcode()) {
3647 case ISD::ANY_EXTEND:
3648 Tmp1 = PromoteOp(Node->getOperand(0));
3649 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3651 case ISD::ZERO_EXTEND:
3652 Result = PromoteOp(Node->getOperand(0));
3653 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3654 Result = DAG.getZeroExtendInReg(Result,
3655 Node->getOperand(0).getValueType());
3657 case ISD::SIGN_EXTEND:
3658 Result = PromoteOp(Node->getOperand(0));
3659 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3660 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3662 DAG.getValueType(Node->getOperand(0).getValueType()));
3667 case ISD::FP_ROUND_INREG:
3668 case ISD::SIGN_EXTEND_INREG: {
3669 Tmp1 = LegalizeOp(Node->getOperand(0));
3670 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3672 // If this operation is not supported, convert it to a shl/shr or load/store
3674 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3675 default: assert(0 && "This action not supported for this op yet!");
3676 case TargetLowering::Legal:
3677 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3679 case TargetLowering::Expand:
3680 // If this is an integer extend and shifts are supported, do that.
3681 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3682 // NOTE: we could fall back on load/store here too for targets without
3683 // SAR. However, it is doubtful that any exist.
3684 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3685 MVT::getSizeInBits(ExtraVT);
3686 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3687 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3688 Node->getOperand(0), ShiftCst);
3689 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3691 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3692 // The only way we can lower this is to turn it into a TRUNCSTORE,
3693 // EXTLOAD pair, targetting a temporary location (a stack slot).
3695 // NOTE: there is a choice here between constantly creating new stack
3696 // slots and always reusing the same one. We currently always create
3697 // new ones, as reuse may inhibit scheduling.
3698 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3699 Node->getValueType(0));
3701 assert(0 && "Unknown op");
3707 case ISD::TRAMPOLINE: {
3709 for (unsigned i = 0; i != 6; ++i)
3710 Ops[i] = LegalizeOp(Node->getOperand(i));
3711 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3712 // The only option for this node is to custom lower it.
3713 Result = TLI.LowerOperation(Result, DAG);
3714 assert(Result.Val && "Should always custom lower!");
3716 // Since trampoline produces two values, make sure to remember that we
3717 // legalized both of them.
3718 Tmp1 = LegalizeOp(Result.getValue(1));
3719 Result = LegalizeOp(Result);
3720 AddLegalizedOperand(SDOperand(Node, 0), Result);
3721 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3722 return Op.ResNo ? Tmp1 : Result;
3724 case ISD::FLT_ROUNDS: {
3725 MVT::ValueType VT = Node->getValueType(0);
3726 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3727 default: assert(0 && "This action not supported for this op yet!");
3728 case TargetLowering::Custom:
3729 Result = TLI.LowerOperation(Op, DAG);
3730 if (Result.Val) break;
3732 case TargetLowering::Legal:
3733 // If this operation is not supported, lower it to constant 1
3734 Result = DAG.getConstant(1, VT);
3739 MVT::ValueType VT = Node->getValueType(0);
3740 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3741 default: assert(0 && "This action not supported for this op yet!");
3742 case TargetLowering::Legal:
3743 Tmp1 = LegalizeOp(Node->getOperand(0));
3744 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3746 case TargetLowering::Custom:
3747 Result = TLI.LowerOperation(Op, DAG);
3748 if (Result.Val) break;
3750 case TargetLowering::Expand:
3751 // If this operation is not supported, lower it to 'abort()' call
3752 Tmp1 = LegalizeOp(Node->getOperand(0));
3753 TargetLowering::ArgListTy Args;
3754 std::pair<SDOperand,SDOperand> CallResult =
3755 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
3756 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3758 Result = CallResult.second;
3765 assert(Result.getValueType() == Op.getValueType() &&
3766 "Bad legalization!");
3768 // Make sure that the generated code is itself legal.
3770 Result = LegalizeOp(Result);
3772 // Note that LegalizeOp may be reentered even from single-use nodes, which
3773 // means that we always must cache transformed nodes.
3774 AddLegalizedOperand(Op, Result);
3778 /// PromoteOp - Given an operation that produces a value in an invalid type,
3779 /// promote it to compute the value into a larger type. The produced value will
3780 /// have the correct bits for the low portion of the register, but no guarantee
3781 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3782 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3783 MVT::ValueType VT = Op.getValueType();
3784 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3785 assert(getTypeAction(VT) == Promote &&
3786 "Caller should expand or legalize operands that are not promotable!");
3787 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3788 "Cannot promote to smaller type!");
3790 SDOperand Tmp1, Tmp2, Tmp3;
3792 SDNode *Node = Op.Val;
3794 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3795 if (I != PromotedNodes.end()) return I->second;
3797 switch (Node->getOpcode()) {
3798 case ISD::CopyFromReg:
3799 assert(0 && "CopyFromReg must be legal!");
3802 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
3804 assert(0 && "Do not know how to promote this operator!");
3807 Result = DAG.getNode(ISD::UNDEF, NVT);
3811 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3813 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3814 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3816 case ISD::ConstantFP:
3817 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3818 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3822 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3823 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3824 Node->getOperand(1), Node->getOperand(2));
3828 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3830 Result = LegalizeOp(Node->getOperand(0));
3831 assert(Result.getValueType() >= NVT &&
3832 "This truncation doesn't make sense!");
3833 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3834 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3837 // The truncation is not required, because we don't guarantee anything
3838 // about high bits anyway.
3839 Result = PromoteOp(Node->getOperand(0));
3842 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3843 // Truncate the low part of the expanded value to the result type
3844 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3847 case ISD::SIGN_EXTEND:
3848 case ISD::ZERO_EXTEND:
3849 case ISD::ANY_EXTEND:
3850 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3851 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3853 // Input is legal? Just do extend all the way to the larger type.
3854 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3857 // Promote the reg if it's smaller.
3858 Result = PromoteOp(Node->getOperand(0));
3859 // The high bits are not guaranteed to be anything. Insert an extend.
3860 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3861 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3862 DAG.getValueType(Node->getOperand(0).getValueType()));
3863 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3864 Result = DAG.getZeroExtendInReg(Result,
3865 Node->getOperand(0).getValueType());
3869 case ISD::BIT_CONVERT:
3870 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3871 Node->getValueType(0));
3872 Result = PromoteOp(Result);
3875 case ISD::FP_EXTEND:
3876 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3878 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3879 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3880 case Promote: assert(0 && "Unreachable with 2 FP types!");
3882 if (Node->getConstantOperandVal(1) == 0) {
3883 // Input is legal? Do an FP_ROUND_INREG.
3884 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3885 DAG.getValueType(VT));
3887 // Just remove the truncate, it isn't affecting the value.
3888 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
3889 Node->getOperand(1));
3894 case ISD::SINT_TO_FP:
3895 case ISD::UINT_TO_FP:
3896 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3898 // No extra round required here.
3899 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3903 Result = PromoteOp(Node->getOperand(0));
3904 if (Node->getOpcode() == ISD::SINT_TO_FP)
3905 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3907 DAG.getValueType(Node->getOperand(0).getValueType()));
3909 Result = DAG.getZeroExtendInReg(Result,
3910 Node->getOperand(0).getValueType());
3911 // No extra round required here.
3912 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3915 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3916 Node->getOperand(0));
3917 // Round if we cannot tolerate excess precision.
3918 if (NoExcessFPPrecision)
3919 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3920 DAG.getValueType(VT));
3925 case ISD::SIGN_EXTEND_INREG:
3926 Result = PromoteOp(Node->getOperand(0));
3927 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3928 Node->getOperand(1));
3930 case ISD::FP_TO_SINT:
3931 case ISD::FP_TO_UINT:
3932 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3935 Tmp1 = Node->getOperand(0);
3938 // The input result is prerounded, so we don't have to do anything
3940 Tmp1 = PromoteOp(Node->getOperand(0));
3943 // If we're promoting a UINT to a larger size, check to see if the new node
3944 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3945 // we can use that instead. This allows us to generate better code for
3946 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3947 // legal, such as PowerPC.
3948 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3949 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3950 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3951 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3952 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3954 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3960 Tmp1 = PromoteOp(Node->getOperand(0));
3961 assert(Tmp1.getValueType() == NVT);
3962 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3963 // NOTE: we do not have to do any extra rounding here for
3964 // NoExcessFPPrecision, because we know the input will have the appropriate
3965 // precision, and these operations don't modify precision at all.
3971 Tmp1 = PromoteOp(Node->getOperand(0));
3972 assert(Tmp1.getValueType() == NVT);
3973 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3974 if (NoExcessFPPrecision)
3975 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3976 DAG.getValueType(VT));
3980 // Promote f32 powi to f64 powi. Note that this could insert a libcall
3981 // directly as well, which may be better.
3982 Tmp1 = PromoteOp(Node->getOperand(0));
3983 assert(Tmp1.getValueType() == NVT);
3984 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
3985 if (NoExcessFPPrecision)
3986 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3987 DAG.getValueType(VT));
3997 // The input may have strange things in the top bits of the registers, but
3998 // these operations don't care. They may have weird bits going out, but
3999 // that too is okay if they are integer operations.
4000 Tmp1 = PromoteOp(Node->getOperand(0));
4001 Tmp2 = PromoteOp(Node->getOperand(1));
4002 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4003 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4008 Tmp1 = PromoteOp(Node->getOperand(0));
4009 Tmp2 = PromoteOp(Node->getOperand(1));
4010 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4011 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4013 // Floating point operations will give excess precision that we may not be
4014 // able to tolerate. If we DO allow excess precision, just leave it,
4015 // otherwise excise it.
4016 // FIXME: Why would we need to round FP ops more than integer ones?
4017 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4018 if (NoExcessFPPrecision)
4019 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4020 DAG.getValueType(VT));
4025 // These operators require that their input be sign extended.
4026 Tmp1 = PromoteOp(Node->getOperand(0));
4027 Tmp2 = PromoteOp(Node->getOperand(1));
4028 if (MVT::isInteger(NVT)) {
4029 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4030 DAG.getValueType(VT));
4031 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4032 DAG.getValueType(VT));
4034 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4036 // Perform FP_ROUND: this is probably overly pessimistic.
4037 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
4038 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4039 DAG.getValueType(VT));
4043 case ISD::FCOPYSIGN:
4044 // These operators require that their input be fp extended.
4045 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4046 case Expand: assert(0 && "not implemented");
4047 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4048 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4050 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4051 case Expand: assert(0 && "not implemented");
4052 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4053 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4055 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4057 // Perform FP_ROUND: this is probably overly pessimistic.
4058 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4059 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4060 DAG.getValueType(VT));
4065 // These operators require that their input be zero extended.
4066 Tmp1 = PromoteOp(Node->getOperand(0));
4067 Tmp2 = PromoteOp(Node->getOperand(1));
4068 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
4069 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4070 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4071 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4075 Tmp1 = PromoteOp(Node->getOperand(0));
4076 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4079 // The input value must be properly sign extended.
4080 Tmp1 = PromoteOp(Node->getOperand(0));
4081 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4082 DAG.getValueType(VT));
4083 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4086 // The input value must be properly zero extended.
4087 Tmp1 = PromoteOp(Node->getOperand(0));
4088 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4089 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4093 Tmp1 = Node->getOperand(0); // Get the chain.
4094 Tmp2 = Node->getOperand(1); // Get the pointer.
4095 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4096 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4097 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
4099 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
4100 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
4101 SV->getValue(), SV->getOffset());
4102 // Increment the pointer, VAList, to the next vaarg
4103 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4104 DAG.getConstant(MVT::getSizeInBits(VT)/8,
4105 TLI.getPointerTy()));
4106 // Store the incremented VAList to the legalized pointer
4107 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
4109 // Load the actual argument out of the pointer VAList
4110 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4112 // Remember that we legalized the chain.
4113 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4117 LoadSDNode *LD = cast<LoadSDNode>(Node);
4118 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4119 ? ISD::EXTLOAD : LD->getExtensionType();
4120 Result = DAG.getExtLoad(ExtType, NVT,
4121 LD->getChain(), LD->getBasePtr(),
4122 LD->getSrcValue(), LD->getSrcValueOffset(),
4125 LD->getAlignment());
4126 // Remember that we legalized the chain.
4127 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4131 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4132 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4133 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
4135 case ISD::SELECT_CC:
4136 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4137 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4138 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4139 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4142 Tmp1 = Node->getOperand(0);
4143 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4144 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4145 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4146 DAG.getConstant(MVT::getSizeInBits(NVT) -
4147 MVT::getSizeInBits(VT),
4148 TLI.getShiftAmountTy()));
4153 // Zero extend the argument
4154 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4155 // Perform the larger operation, then subtract if needed.
4156 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4157 switch(Node->getOpcode()) {
4162 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4163 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
4164 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
4166 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4167 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
4170 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4171 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4172 DAG.getConstant(MVT::getSizeInBits(NVT) -
4173 MVT::getSizeInBits(VT), NVT));
4177 case ISD::EXTRACT_SUBVECTOR:
4178 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4180 case ISD::EXTRACT_VECTOR_ELT:
4181 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4185 assert(Result.Val && "Didn't set a result!");
4187 // Make sure the result is itself legal.
4188 Result = LegalizeOp(Result);
4190 // Remember that we promoted this!
4191 AddPromotedOperand(Op, Result);
4195 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4196 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4197 /// based on the vector type. The return type of this matches the element type
4198 /// of the vector, which may not be legal for the target.
4199 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4200 // We know that operand #0 is the Vec vector. If the index is a constant
4201 // or if the invec is a supported hardware type, we can use it. Otherwise,
4202 // lower to a store then an indexed load.
4203 SDOperand Vec = Op.getOperand(0);
4204 SDOperand Idx = Op.getOperand(1);
4206 MVT::ValueType TVT = Vec.getValueType();
4207 unsigned NumElems = MVT::getVectorNumElements(TVT);
4209 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4210 default: assert(0 && "This action is not supported yet!");
4211 case TargetLowering::Custom: {
4212 Vec = LegalizeOp(Vec);
4213 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4214 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4219 case TargetLowering::Legal:
4220 if (isTypeLegal(TVT)) {
4221 Vec = LegalizeOp(Vec);
4222 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4226 case TargetLowering::Expand:
4230 if (NumElems == 1) {
4231 // This must be an access of the only element. Return it.
4232 Op = ScalarizeVectorOp(Vec);
4233 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4234 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4236 SplitVectorOp(Vec, Lo, Hi);
4237 if (CIdx->getValue() < NumElems/2) {
4241 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2,
4242 Idx.getValueType());
4245 // It's now an extract from the appropriate high or low part. Recurse.
4246 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4247 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4249 // Store the value to a temporary stack slot, then LOAD the scalar
4250 // element back out.
4251 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4252 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4254 // Add the offset to the index.
4255 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
4256 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4257 DAG.getConstant(EltSize, Idx.getValueType()));
4259 if (MVT::getSizeInBits(Idx.getValueType()) >
4260 MVT::getSizeInBits(TLI.getPointerTy()))
4261 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4263 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4265 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4267 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4272 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4273 /// we assume the operation can be split if it is not already legal.
4274 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4275 // We know that operand #0 is the Vec vector. For now we assume the index
4276 // is a constant and that the extracted result is a supported hardware type.
4277 SDOperand Vec = Op.getOperand(0);
4278 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4280 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
4282 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
4283 // This must be an access of the desired vector length. Return it.
4287 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4289 SplitVectorOp(Vec, Lo, Hi);
4290 if (CIdx->getValue() < NumElems/2) {
4294 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4297 // It's now an extract from the appropriate high or low part. Recurse.
4298 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4299 return ExpandEXTRACT_SUBVECTOR(Op);
4302 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4303 /// with condition CC on the current target. This usually involves legalizing
4304 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4305 /// there may be no choice but to create a new SetCC node to represent the
4306 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4307 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4308 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4311 SDOperand Tmp1, Tmp2, Tmp3, Result;
4313 switch (getTypeAction(LHS.getValueType())) {
4315 Tmp1 = LegalizeOp(LHS); // LHS
4316 Tmp2 = LegalizeOp(RHS); // RHS
4319 Tmp1 = PromoteOp(LHS); // LHS
4320 Tmp2 = PromoteOp(RHS); // RHS
4322 // If this is an FP compare, the operands have already been extended.
4323 if (MVT::isInteger(LHS.getValueType())) {
4324 MVT::ValueType VT = LHS.getValueType();
4325 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4327 // Otherwise, we have to insert explicit sign or zero extends. Note
4328 // that we could insert sign extends for ALL conditions, but zero extend
4329 // is cheaper on many machines (an AND instead of two shifts), so prefer
4331 switch (cast<CondCodeSDNode>(CC)->get()) {
4332 default: assert(0 && "Unknown integer comparison!");
4339 // ALL of these operations will work if we either sign or zero extend
4340 // the operands (including the unsigned comparisons!). Zero extend is
4341 // usually a simpler/cheaper operation, so prefer it.
4342 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4343 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4349 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4350 DAG.getValueType(VT));
4351 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4352 DAG.getValueType(VT));
4358 MVT::ValueType VT = LHS.getValueType();
4359 if (VT == MVT::f32 || VT == MVT::f64) {
4360 // Expand into one or more soft-fp libcall(s).
4361 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4362 switch (cast<CondCodeSDNode>(CC)->get()) {
4365 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4369 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4373 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4377 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4381 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4385 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4388 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4391 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4394 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4395 switch (cast<CondCodeSDNode>(CC)->get()) {
4397 // SETONE = SETOLT | SETOGT
4398 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4401 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4404 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4407 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4410 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4413 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4415 default: assert(0 && "Unsupported FP setcc!");
4420 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4421 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4422 false /*sign irrelevant*/, Dummy);
4423 Tmp2 = DAG.getConstant(0, MVT::i32);
4424 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4425 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4426 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4427 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4428 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4429 false /*sign irrelevant*/, Dummy);
4430 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4431 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4432 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4440 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4441 ExpandOp(LHS, LHSLo, LHSHi);
4442 ExpandOp(RHS, RHSLo, RHSHi);
4443 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4445 if (VT==MVT::ppcf128) {
4446 // FIXME: This generated code sucks. We want to generate
4447 // FCMP crN, hi1, hi2
4449 // FCMP crN, lo1, lo2
4450 // The following can be improved, but not that much.
4451 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4452 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
4453 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4454 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
4455 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
4456 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4457 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4466 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4467 if (RHSCST->isAllOnesValue()) {
4468 // Comparison to -1.
4469 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4474 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4475 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4476 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4477 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4480 // If this is a comparison of the sign bit, just look at the top part.
4482 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4483 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4484 CST->getValue() == 0) || // X < 0
4485 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4486 CST->isAllOnesValue())) { // X > -1
4492 // FIXME: This generated code sucks.
4493 ISD::CondCode LowCC;
4495 default: assert(0 && "Unknown integer setcc!");
4497 case ISD::SETULT: LowCC = ISD::SETULT; break;
4499 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4501 case ISD::SETULE: LowCC = ISD::SETULE; break;
4503 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4506 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4507 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4508 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4510 // NOTE: on targets without efficient SELECT of bools, we can always use
4511 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4512 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4513 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4514 false, DagCombineInfo);
4516 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4517 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4518 CCCode, false, DagCombineInfo);
4520 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC);
4522 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4523 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4524 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4525 (Tmp2C && Tmp2C->getValue() == 0 &&
4526 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4527 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4528 (Tmp2C && Tmp2C->getValue() == 1 &&
4529 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4530 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4531 // low part is known false, returns high part.
4532 // For LE / GE, if high part is known false, ignore the low part.
4533 // For LT / GT, if high part is known true, ignore the low part.
4537 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4538 ISD::SETEQ, false, DagCombineInfo);
4540 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4541 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4542 Result, Tmp1, Tmp2));
4553 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4554 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4555 /// a load from the stack slot to DestVT, extending it if needed.
4556 /// The resultant code need not be legal.
4557 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4558 MVT::ValueType SlotVT,
4559 MVT::ValueType DestVT) {
4560 // Create the stack frame object.
4561 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
4563 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType());
4564 unsigned SlotSize = MVT::getSizeInBits(SlotVT);
4565 unsigned DestSize = MVT::getSizeInBits(DestVT);
4567 // Emit a store to the stack slot. Use a truncstore if the input value is
4568 // later than DestVT.
4570 if (SrcSize > SlotSize)
4571 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0,SlotVT);
4573 assert(SrcSize == SlotSize && "Invalid store");
4574 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
4577 // Result is a load from the stack slot.
4578 if (SlotSize == DestSize)
4579 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4581 assert(SlotSize < DestSize && "Unknown extension!");
4582 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT);
4585 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4586 // Create a vector sized/aligned stack slot, store the value to element #0,
4587 // then load the whole vector back out.
4588 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4589 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4591 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
4595 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4596 /// support the operation, but do support the resultant vector type.
4597 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4599 // If the only non-undef value is the low element, turn this into a
4600 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4601 unsigned NumElems = Node->getNumOperands();
4602 bool isOnlyLowElement = true;
4603 SDOperand SplatValue = Node->getOperand(0);
4604 std::map<SDOperand, std::vector<unsigned> > Values;
4605 Values[SplatValue].push_back(0);
4606 bool isConstant = true;
4607 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4608 SplatValue.getOpcode() != ISD::UNDEF)
4611 for (unsigned i = 1; i < NumElems; ++i) {
4612 SDOperand V = Node->getOperand(i);
4613 Values[V].push_back(i);
4614 if (V.getOpcode() != ISD::UNDEF)
4615 isOnlyLowElement = false;
4616 if (SplatValue != V)
4617 SplatValue = SDOperand(0,0);
4619 // If this isn't a constant element or an undef, we can't use a constant
4621 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4622 V.getOpcode() != ISD::UNDEF)
4626 if (isOnlyLowElement) {
4627 // If the low element is an undef too, then this whole things is an undef.
4628 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4629 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4630 // Otherwise, turn this into a scalar_to_vector node.
4631 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4632 Node->getOperand(0));
4635 // If all elements are constants, create a load from the constant pool.
4637 MVT::ValueType VT = Node->getValueType(0);
4639 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4640 std::vector<Constant*> CV;
4641 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4642 if (ConstantFPSDNode *V =
4643 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4644 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4645 } else if (ConstantSDNode *V =
4646 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4647 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4649 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4650 CV.push_back(UndefValue::get(OpNTy));
4653 Constant *CP = ConstantVector::get(CV);
4654 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4655 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
4658 if (SplatValue.Val) { // Splat of one value?
4659 // Build the shuffle constant vector: <0, 0, 0, 0>
4660 MVT::ValueType MaskVT =
4661 MVT::getIntVectorWithNumElements(NumElems);
4662 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4663 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4664 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4665 &ZeroVec[0], ZeroVec.size());
4667 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4668 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4669 // Get the splatted value into the low element of a vector register.
4670 SDOperand LowValVec =
4671 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4673 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4674 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4675 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4680 // If there are only two unique elements, we may be able to turn this into a
4682 if (Values.size() == 2) {
4683 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4684 MVT::ValueType MaskVT =
4685 MVT::getIntVectorWithNumElements(NumElems);
4686 std::vector<SDOperand> MaskVec(NumElems);
4688 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4689 E = Values.end(); I != E; ++I) {
4690 for (std::vector<unsigned>::iterator II = I->second.begin(),
4691 EE = I->second.end(); II != EE; ++II)
4692 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4695 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4696 &MaskVec[0], MaskVec.size());
4698 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4699 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4700 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4701 SmallVector<SDOperand, 8> Ops;
4702 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4703 E = Values.end(); I != E; ++I) {
4704 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4708 Ops.push_back(ShuffleMask);
4710 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4711 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4712 &Ops[0], Ops.size());
4716 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4717 // aligned object on the stack, store each element into it, then load
4718 // the result as a vector.
4719 MVT::ValueType VT = Node->getValueType(0);
4720 // Create the stack frame object.
4721 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
4723 // Emit a store of each element to the stack slot.
4724 SmallVector<SDOperand, 8> Stores;
4725 unsigned TypeByteSize =
4726 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4727 // Store (in the right endianness) the elements to memory.
4728 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4729 // Ignore undef elements.
4730 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4732 unsigned Offset = TypeByteSize*i;
4734 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4735 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4737 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4741 SDOperand StoreChain;
4742 if (!Stores.empty()) // Not all undef elements?
4743 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4744 &Stores[0], Stores.size());
4746 StoreChain = DAG.getEntryNode();
4748 // Result is a load from the stack slot.
4749 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4752 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4753 SDOperand Op, SDOperand Amt,
4754 SDOperand &Lo, SDOperand &Hi) {
4755 // Expand the subcomponents.
4756 SDOperand LHSL, LHSH;
4757 ExpandOp(Op, LHSL, LHSH);
4759 SDOperand Ops[] = { LHSL, LHSH, Amt };
4760 MVT::ValueType VT = LHSL.getValueType();
4761 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4762 Hi = Lo.getValue(1);
4766 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4767 /// smaller elements. If we can't find a way that is more efficient than a
4768 /// libcall on this target, return false. Otherwise, return true with the
4769 /// low-parts expanded into Lo and Hi.
4770 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4771 SDOperand &Lo, SDOperand &Hi) {
4772 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4773 "This is not a shift!");
4775 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4776 SDOperand ShAmt = LegalizeOp(Amt);
4777 MVT::ValueType ShTy = ShAmt.getValueType();
4778 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4779 unsigned NVTBits = MVT::getSizeInBits(NVT);
4781 // Handle the case when Amt is an immediate.
4782 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4783 unsigned Cst = CN->getValue();
4784 // Expand the incoming operand to be shifted, so that we have its parts
4786 ExpandOp(Op, InL, InH);
4790 Lo = DAG.getConstant(0, NVT);
4791 Hi = DAG.getConstant(0, NVT);
4792 } else if (Cst > NVTBits) {
4793 Lo = DAG.getConstant(0, NVT);
4794 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4795 } else if (Cst == NVTBits) {
4796 Lo = DAG.getConstant(0, NVT);
4799 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4800 Hi = DAG.getNode(ISD::OR, NVT,
4801 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4802 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4807 Lo = DAG.getConstant(0, NVT);
4808 Hi = DAG.getConstant(0, NVT);
4809 } else if (Cst > NVTBits) {
4810 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
4811 Hi = DAG.getConstant(0, NVT);
4812 } else if (Cst == NVTBits) {
4814 Hi = DAG.getConstant(0, NVT);
4816 Lo = DAG.getNode(ISD::OR, NVT,
4817 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4818 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4819 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
4824 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
4825 DAG.getConstant(NVTBits-1, ShTy));
4826 } else if (Cst > NVTBits) {
4827 Lo = DAG.getNode(ISD::SRA, NVT, InH,
4828 DAG.getConstant(Cst-NVTBits, ShTy));
4829 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4830 DAG.getConstant(NVTBits-1, ShTy));
4831 } else if (Cst == NVTBits) {
4833 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4834 DAG.getConstant(NVTBits-1, ShTy));
4836 Lo = DAG.getNode(ISD::OR, NVT,
4837 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4838 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4839 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
4845 // Okay, the shift amount isn't constant. However, if we can tell that it is
4846 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
4847 uint64_t Mask = NVTBits, KnownZero, KnownOne;
4848 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
4850 // If we know that the high bit of the shift amount is one, then we can do
4851 // this as a couple of simple shifts.
4852 if (KnownOne & Mask) {
4853 // Mask out the high bit, which we know is set.
4854 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
4855 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4857 // Expand the incoming operand to be shifted, so that we have its parts
4859 ExpandOp(Op, InL, InH);
4862 Lo = DAG.getConstant(0, NVT); // Low part is zero.
4863 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
4866 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
4867 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
4870 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
4871 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4872 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
4877 // If we know that the high bit of the shift amount is zero, then we can do
4878 // this as a couple of simple shifts.
4879 if (KnownZero & Mask) {
4881 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
4882 DAG.getConstant(NVTBits, Amt.getValueType()),
4885 // Expand the incoming operand to be shifted, so that we have its parts
4887 ExpandOp(Op, InL, InH);
4890 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
4891 Hi = DAG.getNode(ISD::OR, NVT,
4892 DAG.getNode(ISD::SHL, NVT, InH, Amt),
4893 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
4896 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
4897 Lo = DAG.getNode(ISD::OR, NVT,
4898 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4899 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4902 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
4903 Lo = DAG.getNode(ISD::OR, NVT,
4904 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4905 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4914 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
4915 // does not fit into a register, return the lo part and set the hi part to the
4916 // by-reg argument. If it does fit into a single register, return the result
4917 // and leave the Hi part unset.
4918 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
4919 bool isSigned, SDOperand &Hi) {
4920 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
4921 // The input chain to this libcall is the entry node of the function.
4922 // Legalizing the call will automatically add the previous call to the
4924 SDOperand InChain = DAG.getEntryNode();
4926 TargetLowering::ArgListTy Args;
4927 TargetLowering::ArgListEntry Entry;
4928 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4929 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
4930 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
4931 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
4932 Entry.isSExt = isSigned;
4933 Args.push_back(Entry);
4935 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
4937 // Splice the libcall in wherever FindInputOutputChains tells us to.
4938 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
4939 std::pair<SDOperand,SDOperand> CallInfo =
4940 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
4943 // Legalize the call sequence, starting with the chain. This will advance
4944 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
4945 // was added by LowerCallTo (guaranteeing proper serialization of calls).
4946 LegalizeOp(CallInfo.second);
4948 switch (getTypeAction(CallInfo.first.getValueType())) {
4949 default: assert(0 && "Unknown thing");
4951 Result = CallInfo.first;
4954 ExpandOp(CallInfo.first, Result, Hi);
4961 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
4963 SDOperand SelectionDAGLegalize::
4964 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
4965 assert(getTypeAction(Source.getValueType()) == Expand &&
4966 "This is not an expansion!");
4967 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
4970 assert(Source.getValueType() == MVT::i64 &&
4971 "This only works for 64-bit -> FP");
4972 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
4973 // incoming integer is set. To handle this, we dynamically test to see if
4974 // it is set, and, if so, add a fudge factor.
4976 ExpandOp(Source, Lo, Hi);
4978 // If this is unsigned, and not supported, first perform the conversion to
4979 // signed, then adjust the result if the sign bit is set.
4980 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
4981 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
4983 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
4984 DAG.getConstant(0, Hi.getValueType()),
4986 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
4987 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4988 SignSet, Four, Zero);
4989 uint64_t FF = 0x5f800000ULL;
4990 if (TLI.isLittleEndian()) FF <<= 32;
4991 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4993 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4994 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4995 SDOperand FudgeInReg;
4996 if (DestTy == MVT::f32)
4997 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4998 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
4999 // FIXME: Avoid the extend by construction the right constantpool?
5000 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5001 CPIdx, NULL, 0, MVT::f32);
5003 assert(0 && "Unexpected conversion");
5005 MVT::ValueType SCVT = SignedConv.getValueType();
5006 if (SCVT != DestTy) {
5007 // Destination type needs to be expanded as well. The FADD now we are
5008 // constructing will be expanded into a libcall.
5009 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
5010 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
5011 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
5012 SignedConv, SignedConv.getValue(1));
5014 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5016 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5019 // Check to see if the target has a custom way to lower this. If so, use it.
5020 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
5021 default: assert(0 && "This action not implemented for this operation!");
5022 case TargetLowering::Legal:
5023 case TargetLowering::Expand:
5024 break; // This case is handled below.
5025 case TargetLowering::Custom: {
5026 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5029 return LegalizeOp(NV);
5030 break; // The target decided this was legal after all
5034 // Expand the source, then glue it back together for the call. We must expand
5035 // the source in case it is shared (this pass of legalize must traverse it).
5036 SDOperand SrcLo, SrcHi;
5037 ExpandOp(Source, SrcLo, SrcHi);
5038 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
5041 if (DestTy == MVT::f32)
5042 LC = RTLIB::SINTTOFP_I64_F32;
5044 assert(DestTy == MVT::f64 && "Unknown fp value type!");
5045 LC = RTLIB::SINTTOFP_I64_F64;
5048 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
5049 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5050 SDOperand UnusedHiPart;
5051 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
5055 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5056 /// INT_TO_FP operation of the specified operand when the target requests that
5057 /// we expand it. At this point, we know that the result and operand types are
5058 /// legal for the target.
5059 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5061 MVT::ValueType DestVT) {
5062 if (Op0.getValueType() == MVT::i32) {
5063 // simple 32-bit [signed|unsigned] integer to float/double expansion
5065 // Get the stack frame index of a 8 byte buffer.
5066 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5068 // word offset constant for Hi/Lo address computation
5069 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5070 // set up Hi and Lo (into buffer) address based on endian
5071 SDOperand Hi = StackSlot;
5072 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5073 if (TLI.isLittleEndian())
5076 // if signed map to unsigned space
5077 SDOperand Op0Mapped;
5079 // constant used to invert sign bit (signed to unsigned mapping)
5080 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5081 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5085 // store the lo of the constructed double - based on integer input
5086 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5087 Op0Mapped, Lo, NULL, 0);
5088 // initial hi portion of constructed double
5089 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5090 // store the hi of the constructed double - biased exponent
5091 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5092 // load the constructed double
5093 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5094 // FP constant to bias correct the final result
5095 SDOperand Bias = DAG.getConstantFP(isSigned ?
5096 BitsToDouble(0x4330000080000000ULL)
5097 : BitsToDouble(0x4330000000000000ULL),
5099 // subtract the bias
5100 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5103 // handle final rounding
5104 if (DestVT == MVT::f64) {
5107 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
5108 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5109 DAG.getIntPtrConstant(0));
5110 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
5111 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5115 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5116 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5118 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
5119 DAG.getConstant(0, Op0.getValueType()),
5121 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5122 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5123 SignSet, Four, Zero);
5125 // If the sign bit of the integer is set, the large number will be treated
5126 // as a negative number. To counteract this, the dynamic code adds an
5127 // offset depending on the data type.
5129 switch (Op0.getValueType()) {
5130 default: assert(0 && "Unsupported integer type!");
5131 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5132 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5133 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5134 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5136 if (TLI.isLittleEndian()) FF <<= 32;
5137 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5139 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5140 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5141 SDOperand FudgeInReg;
5142 if (DestVT == MVT::f32)
5143 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
5145 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5146 DAG.getEntryNode(), CPIdx,
5147 NULL, 0, MVT::f32));
5150 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5153 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5154 /// *INT_TO_FP operation of the specified operand when the target requests that
5155 /// we promote it. At this point, we know that the result and operand types are
5156 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5157 /// operation that takes a larger input.
5158 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5159 MVT::ValueType DestVT,
5161 // First step, figure out the appropriate *INT_TO_FP operation to use.
5162 MVT::ValueType NewInTy = LegalOp.getValueType();
5164 unsigned OpToUse = 0;
5166 // Scan for the appropriate larger type to use.
5168 NewInTy = (MVT::ValueType)(NewInTy+1);
5169 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
5171 // If the target supports SINT_TO_FP of this type, use it.
5172 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5174 case TargetLowering::Legal:
5175 if (!TLI.isTypeLegal(NewInTy))
5176 break; // Can't use this datatype.
5178 case TargetLowering::Custom:
5179 OpToUse = ISD::SINT_TO_FP;
5183 if (isSigned) continue;
5185 // If the target supports UINT_TO_FP of this type, use it.
5186 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5188 case TargetLowering::Legal:
5189 if (!TLI.isTypeLegal(NewInTy))
5190 break; // Can't use this datatype.
5192 case TargetLowering::Custom:
5193 OpToUse = ISD::UINT_TO_FP;
5198 // Otherwise, try a larger type.
5201 // Okay, we found the operation and type to use. Zero extend our input to the
5202 // desired type then run the operation on it.
5203 return DAG.getNode(OpToUse, DestVT,
5204 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5208 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5209 /// FP_TO_*INT operation of the specified operand when the target requests that
5210 /// we promote it. At this point, we know that the result and operand types are
5211 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5212 /// operation that returns a larger result.
5213 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5214 MVT::ValueType DestVT,
5216 // First step, figure out the appropriate FP_TO*INT operation to use.
5217 MVT::ValueType NewOutTy = DestVT;
5219 unsigned OpToUse = 0;
5221 // Scan for the appropriate larger type to use.
5223 NewOutTy = (MVT::ValueType)(NewOutTy+1);
5224 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
5226 // If the target supports FP_TO_SINT returning this type, use it.
5227 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5229 case TargetLowering::Legal:
5230 if (!TLI.isTypeLegal(NewOutTy))
5231 break; // Can't use this datatype.
5233 case TargetLowering::Custom:
5234 OpToUse = ISD::FP_TO_SINT;
5239 // If the target supports FP_TO_UINT of this type, use it.
5240 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5242 case TargetLowering::Legal:
5243 if (!TLI.isTypeLegal(NewOutTy))
5244 break; // Can't use this datatype.
5246 case TargetLowering::Custom:
5247 OpToUse = ISD::FP_TO_UINT;
5252 // Otherwise, try a larger type.
5256 // Okay, we found the operation and type to use.
5257 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5259 // If the operation produces an invalid type, it must be custom lowered. Use
5260 // the target lowering hooks to expand it. Just keep the low part of the
5261 // expanded operation, we know that we're truncating anyway.
5262 if (getTypeAction(NewOutTy) == Expand) {
5263 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
5264 assert(Operation.Val && "Didn't return anything");
5267 // Truncate the result of the extended FP_TO_*INT operation to the desired
5269 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5272 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5274 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5275 MVT::ValueType VT = Op.getValueType();
5276 MVT::ValueType SHVT = TLI.getShiftAmountTy();
5277 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5279 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5281 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5282 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5283 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5285 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5286 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5287 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5288 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5289 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5290 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5291 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5292 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5293 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5295 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5296 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5297 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5298 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5299 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5300 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5301 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5302 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5303 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5304 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5305 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5306 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5307 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5308 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5309 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5310 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5311 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5312 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5313 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5314 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5315 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5319 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5321 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5323 default: assert(0 && "Cannot expand this yet!");
5325 static const uint64_t mask[6] = {
5326 0x5555555555555555ULL, 0x3333333333333333ULL,
5327 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5328 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5330 MVT::ValueType VT = Op.getValueType();
5331 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5332 unsigned len = MVT::getSizeInBits(VT);
5333 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5334 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5335 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5336 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5337 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5338 DAG.getNode(ISD::AND, VT,
5339 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5344 // for now, we do this:
5345 // x = x | (x >> 1);
5346 // x = x | (x >> 2);
5348 // x = x | (x >>16);
5349 // x = x | (x >>32); // for 64-bit input
5350 // return popcount(~x);
5352 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5353 MVT::ValueType VT = Op.getValueType();
5354 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5355 unsigned len = MVT::getSizeInBits(VT);
5356 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5357 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5358 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5360 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5361 return DAG.getNode(ISD::CTPOP, VT, Op);
5364 // for now, we use: { return popcount(~x & (x - 1)); }
5365 // unless the target has ctlz but not ctpop, in which case we use:
5366 // { return 32 - nlz(~x & (x-1)); }
5367 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5368 MVT::ValueType VT = Op.getValueType();
5369 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5370 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5371 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5372 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5373 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5374 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5375 TLI.isOperationLegal(ISD::CTLZ, VT))
5376 return DAG.getNode(ISD::SUB, VT,
5377 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5378 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5379 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5384 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5385 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5386 /// LegalizeNodes map is filled in for any results that are not expanded, the
5387 /// ExpandedNodes map is filled in for any results that are expanded, and the
5388 /// Lo/Hi values are returned.
5389 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5390 MVT::ValueType VT = Op.getValueType();
5391 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5392 SDNode *Node = Op.Val;
5393 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5394 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5395 MVT::isVector(VT)) &&
5396 "Cannot expand to FP value or to larger int value!");
5398 // See if we already expanded it.
5399 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5400 = ExpandedNodes.find(Op);
5401 if (I != ExpandedNodes.end()) {
5402 Lo = I->second.first;
5403 Hi = I->second.second;
5407 switch (Node->getOpcode()) {
5408 case ISD::CopyFromReg:
5409 assert(0 && "CopyFromReg must be legal!");
5410 case ISD::FP_ROUND_INREG:
5411 if (VT == MVT::ppcf128 &&
5412 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5413 TargetLowering::Custom) {
5414 SDOperand SrcLo, SrcHi, Src;
5415 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5416 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5417 SDOperand Result = TLI.LowerOperation(
5418 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5419 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5420 Lo = Result.Val->getOperand(0);
5421 Hi = Result.Val->getOperand(1);
5427 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5429 assert(0 && "Do not know how to expand this operator!");
5431 case ISD::EXTRACT_VECTOR_ELT:
5432 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5433 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5434 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5435 return ExpandOp(Lo, Lo, Hi);
5437 NVT = TLI.getTypeToExpandTo(VT);
5438 Lo = DAG.getNode(ISD::UNDEF, NVT);
5439 Hi = DAG.getNode(ISD::UNDEF, NVT);
5441 case ISD::Constant: {
5442 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
5443 Lo = DAG.getConstant(Cst, NVT);
5444 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
5447 case ISD::ConstantFP: {
5448 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5449 if (CFP->getValueType(0) == MVT::ppcf128) {
5450 APInt api = CFP->getValueAPF().convertToAPInt();
5451 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5453 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5457 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5458 if (getTypeAction(Lo.getValueType()) == Expand)
5459 ExpandOp(Lo, Lo, Hi);
5462 case ISD::BUILD_PAIR:
5463 // Return the operands.
5464 Lo = Node->getOperand(0);
5465 Hi = Node->getOperand(1);
5468 case ISD::MERGE_VALUES:
5469 if (Node->getNumValues() == 1) {
5470 ExpandOp(Op.getOperand(0), Lo, Hi);
5473 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5474 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5475 Op.getValue(1).getValueType() == MVT::Other &&
5476 "unhandled MERGE_VALUES");
5477 ExpandOp(Op.getOperand(0), Lo, Hi);
5478 // Remember that we legalized the chain.
5479 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5482 case ISD::SIGN_EXTEND_INREG:
5483 ExpandOp(Node->getOperand(0), Lo, Hi);
5484 // sext_inreg the low part if needed.
5485 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5487 // The high part gets the sign extension from the lo-part. This handles
5488 // things like sextinreg V:i64 from i8.
5489 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5490 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5491 TLI.getShiftAmountTy()));
5495 ExpandOp(Node->getOperand(0), Lo, Hi);
5496 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5497 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5503 ExpandOp(Node->getOperand(0), Lo, Hi);
5504 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5505 DAG.getNode(ISD::CTPOP, NVT, Lo),
5506 DAG.getNode(ISD::CTPOP, NVT, Hi));
5507 Hi = DAG.getConstant(0, NVT);
5511 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5512 ExpandOp(Node->getOperand(0), Lo, Hi);
5513 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5514 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5515 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5517 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5518 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5520 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5521 Hi = DAG.getConstant(0, NVT);
5526 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5527 ExpandOp(Node->getOperand(0), Lo, Hi);
5528 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5529 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5530 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5532 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5533 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5535 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5536 Hi = DAG.getConstant(0, NVT);
5541 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5542 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5543 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5544 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5546 // Remember that we legalized the chain.
5547 Hi = LegalizeOp(Hi);
5548 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5549 if (!TLI.isLittleEndian())
5555 LoadSDNode *LD = cast<LoadSDNode>(Node);
5556 SDOperand Ch = LD->getChain(); // Legalize the chain.
5557 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5558 ISD::LoadExtType ExtType = LD->getExtensionType();
5559 int SVOffset = LD->getSrcValueOffset();
5560 unsigned Alignment = LD->getAlignment();
5561 bool isVolatile = LD->isVolatile();
5563 if (ExtType == ISD::NON_EXTLOAD) {
5564 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5565 isVolatile, Alignment);
5566 if (VT == MVT::f32 || VT == MVT::f64) {
5567 // f32->i32 or f64->i64 one to one expansion.
5568 // Remember that we legalized the chain.
5569 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5570 // Recursively expand the new load.
5571 if (getTypeAction(NVT) == Expand)
5572 ExpandOp(Lo, Lo, Hi);
5576 // Increment the pointer to the other half.
5577 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5578 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5579 DAG.getIntPtrConstant(IncrementSize));
5580 SVOffset += IncrementSize;
5581 Alignment = MinAlign(Alignment, IncrementSize);
5582 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5583 isVolatile, Alignment);
5585 // Build a factor node to remember that this load is independent of the
5587 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5590 // Remember that we legalized the chain.
5591 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5592 if (!TLI.isLittleEndian())
5595 MVT::ValueType EVT = LD->getLoadedVT();
5597 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5598 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5599 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5600 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5601 SVOffset, isVolatile, Alignment);
5602 // Remember that we legalized the chain.
5603 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5604 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5609 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5610 SVOffset, isVolatile, Alignment);
5612 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5613 SVOffset, EVT, isVolatile,
5616 // Remember that we legalized the chain.
5617 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5619 if (ExtType == ISD::SEXTLOAD) {
5620 // The high part is obtained by SRA'ing all but one of the bits of the
5622 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5623 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5624 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5625 } else if (ExtType == ISD::ZEXTLOAD) {
5626 // The high part is just a zero.
5627 Hi = DAG.getConstant(0, NVT);
5628 } else /* if (ExtType == ISD::EXTLOAD) */ {
5629 // The high part is undefined.
5630 Hi = DAG.getNode(ISD::UNDEF, NVT);
5637 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5638 SDOperand LL, LH, RL, RH;
5639 ExpandOp(Node->getOperand(0), LL, LH);
5640 ExpandOp(Node->getOperand(1), RL, RH);
5641 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5642 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5646 SDOperand LL, LH, RL, RH;
5647 ExpandOp(Node->getOperand(1), LL, LH);
5648 ExpandOp(Node->getOperand(2), RL, RH);
5649 if (getTypeAction(NVT) == Expand)
5650 NVT = TLI.getTypeToExpandTo(NVT);
5651 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5653 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5656 case ISD::SELECT_CC: {
5657 SDOperand TL, TH, FL, FH;
5658 ExpandOp(Node->getOperand(2), TL, TH);
5659 ExpandOp(Node->getOperand(3), FL, FH);
5660 if (getTypeAction(NVT) == Expand)
5661 NVT = TLI.getTypeToExpandTo(NVT);
5662 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5663 Node->getOperand(1), TL, FL, Node->getOperand(4));
5665 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5666 Node->getOperand(1), TH, FH, Node->getOperand(4));
5669 case ISD::ANY_EXTEND:
5670 // The low part is any extension of the input (which degenerates to a copy).
5671 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5672 // The high part is undefined.
5673 Hi = DAG.getNode(ISD::UNDEF, NVT);
5675 case ISD::SIGN_EXTEND: {
5676 // The low part is just a sign extension of the input (which degenerates to
5678 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5680 // The high part is obtained by SRA'ing all but one of the bits of the lo
5682 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5683 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5684 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5687 case ISD::ZERO_EXTEND:
5688 // The low part is just a zero extension of the input (which degenerates to
5690 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5692 // The high part is just a zero.
5693 Hi = DAG.getConstant(0, NVT);
5696 case ISD::TRUNCATE: {
5697 // The input value must be larger than this value. Expand *it*.
5699 ExpandOp(Node->getOperand(0), NewLo, Hi);
5701 // The low part is now either the right size, or it is closer. If not the
5702 // right size, make an illegal truncate so we recursively expand it.
5703 if (NewLo.getValueType() != Node->getValueType(0))
5704 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
5705 ExpandOp(NewLo, Lo, Hi);
5709 case ISD::BIT_CONVERT: {
5711 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
5712 // If the target wants to, allow it to lower this itself.
5713 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5714 case Expand: assert(0 && "cannot expand FP!");
5715 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
5716 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
5718 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
5721 // f32 / f64 must be expanded to i32 / i64.
5722 if (VT == MVT::f32 || VT == MVT::f64) {
5723 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5724 if (getTypeAction(NVT) == Expand)
5725 ExpandOp(Lo, Lo, Hi);
5729 // If source operand will be expanded to the same type as VT, i.e.
5730 // i64 <- f64, i32 <- f32, expand the source operand instead.
5731 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
5732 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
5733 ExpandOp(Node->getOperand(0), Lo, Hi);
5737 // Turn this into a load/store pair by default.
5739 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
5741 ExpandOp(Tmp, Lo, Hi);
5745 case ISD::READCYCLECOUNTER: {
5746 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5747 TargetLowering::Custom &&
5748 "Must custom expand ReadCycleCounter");
5749 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
5750 assert(Tmp.Val && "Node must be custom expanded!");
5751 ExpandOp(Tmp.getValue(0), Lo, Hi);
5752 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5753 LegalizeOp(Tmp.getValue(1)));
5757 // These operators cannot be expanded directly, emit them as calls to
5758 // library functions.
5759 case ISD::FP_TO_SINT: {
5760 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5762 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5763 case Expand: assert(0 && "cannot expand FP!");
5764 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5765 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5768 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5770 // Now that the custom expander is done, expand the result, which is still
5773 ExpandOp(Op, Lo, Hi);
5778 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5779 if (Node->getOperand(0).getValueType() == MVT::f32)
5780 LC = RTLIB::FPTOSINT_F32_I64;
5781 else if (Node->getOperand(0).getValueType() == MVT::f64)
5782 LC = RTLIB::FPTOSINT_F64_I64;
5783 else if (Node->getOperand(0).getValueType() == MVT::f80)
5784 LC = RTLIB::FPTOSINT_F80_I64;
5785 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
5786 LC = RTLIB::FPTOSINT_PPCF128_I64;
5787 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5788 false/*sign irrelevant*/, Hi);
5792 case ISD::FP_TO_UINT: {
5793 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
5795 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5796 case Expand: assert(0 && "cannot expand FP!");
5797 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5798 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5801 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
5803 // Now that the custom expander is done, expand the result.
5805 ExpandOp(Op, Lo, Hi);
5810 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5811 if (Node->getOperand(0).getValueType() == MVT::f32)
5812 LC = RTLIB::FPTOUINT_F32_I64;
5813 else if (Node->getOperand(0).getValueType() == MVT::f64)
5814 LC = RTLIB::FPTOUINT_F64_I64;
5815 else if (Node->getOperand(0).getValueType() == MVT::f80)
5816 LC = RTLIB::FPTOUINT_F80_I64;
5817 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
5818 LC = RTLIB::FPTOUINT_PPCF128_I64;
5819 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5820 false/*sign irrelevant*/, Hi);
5825 // If the target wants custom lowering, do so.
5826 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5827 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
5828 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
5829 Op = TLI.LowerOperation(Op, DAG);
5831 // Now that the custom expander is done, expand the result, which is
5833 ExpandOp(Op, Lo, Hi);
5838 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
5839 // this X << 1 as X+X.
5840 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
5841 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
5842 TLI.isOperationLegal(ISD::ADDE, NVT)) {
5843 SDOperand LoOps[2], HiOps[3];
5844 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
5845 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
5846 LoOps[1] = LoOps[0];
5847 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5849 HiOps[1] = HiOps[0];
5850 HiOps[2] = Lo.getValue(1);
5851 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5856 // If we can emit an efficient shift operation, do so now.
5857 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5860 // If this target supports SHL_PARTS, use it.
5861 TargetLowering::LegalizeAction Action =
5862 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
5863 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5864 Action == TargetLowering::Custom) {
5865 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5869 // Otherwise, emit a libcall.
5870 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
5871 false/*left shift=unsigned*/, Hi);
5876 // If the target wants custom lowering, do so.
5877 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5878 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
5879 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
5880 Op = TLI.LowerOperation(Op, DAG);
5882 // Now that the custom expander is done, expand the result, which is
5884 ExpandOp(Op, Lo, Hi);
5889 // If we can emit an efficient shift operation, do so now.
5890 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
5893 // If this target supports SRA_PARTS, use it.
5894 TargetLowering::LegalizeAction Action =
5895 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
5896 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5897 Action == TargetLowering::Custom) {
5898 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5902 // Otherwise, emit a libcall.
5903 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
5904 true/*ashr is signed*/, Hi);
5909 // If the target wants custom lowering, do so.
5910 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5911 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
5912 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
5913 Op = TLI.LowerOperation(Op, DAG);
5915 // Now that the custom expander is done, expand the result, which is
5917 ExpandOp(Op, Lo, Hi);
5922 // If we can emit an efficient shift operation, do so now.
5923 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5926 // If this target supports SRL_PARTS, use it.
5927 TargetLowering::LegalizeAction Action =
5928 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
5929 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5930 Action == TargetLowering::Custom) {
5931 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5935 // Otherwise, emit a libcall.
5936 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
5937 false/*lshr is unsigned*/, Hi);
5943 // If the target wants to custom expand this, let them.
5944 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
5945 TargetLowering::Custom) {
5946 Op = TLI.LowerOperation(Op, DAG);
5948 ExpandOp(Op, Lo, Hi);
5953 // Expand the subcomponents.
5954 SDOperand LHSL, LHSH, RHSL, RHSH;
5955 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5956 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5957 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5958 SDOperand LoOps[2], HiOps[3];
5963 if (Node->getOpcode() == ISD::ADD) {
5964 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5965 HiOps[2] = Lo.getValue(1);
5966 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5968 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5969 HiOps[2] = Lo.getValue(1);
5970 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5977 // Expand the subcomponents.
5978 SDOperand LHSL, LHSH, RHSL, RHSH;
5979 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5980 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5981 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5982 SDOperand LoOps[2] = { LHSL, RHSL };
5983 SDOperand HiOps[3] = { LHSH, RHSH };
5985 if (Node->getOpcode() == ISD::ADDC) {
5986 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5987 HiOps[2] = Lo.getValue(1);
5988 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5990 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5991 HiOps[2] = Lo.getValue(1);
5992 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5994 // Remember that we legalized the flag.
5995 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6000 // Expand the subcomponents.
6001 SDOperand LHSL, LHSH, RHSL, RHSH;
6002 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6003 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6004 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6005 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6006 SDOperand HiOps[3] = { LHSH, RHSH };
6008 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6009 HiOps[2] = Lo.getValue(1);
6010 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6012 // Remember that we legalized the flag.
6013 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6017 // If the target wants to custom expand this, let them.
6018 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6019 SDOperand New = TLI.LowerOperation(Op, DAG);
6021 ExpandOp(New, Lo, Hi);
6026 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6027 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6028 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6029 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6030 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6031 SDOperand LL, LH, RL, RH;
6032 ExpandOp(Node->getOperand(0), LL, LH);
6033 ExpandOp(Node->getOperand(1), RL, RH);
6034 unsigned BitSize = MVT::getSizeInBits(RH.getValueType());
6035 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6036 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6037 // FIXME: generalize this to handle other bit sizes
6038 if (LHSSB == 32 && RHSSB == 32 &&
6039 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) &&
6040 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) {
6041 // The inputs are both zero-extended.
6043 // We can emit a umul_lohi.
6044 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6045 Hi = SDOperand(Lo.Val, 1);
6049 // We can emit a mulhu+mul.
6050 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6051 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6055 if (LHSSB > BitSize && RHSSB > BitSize) {
6056 // The input values are both sign-extended.
6058 // We can emit a smul_lohi.
6059 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6060 Hi = SDOperand(Lo.Val, 1);
6064 // We can emit a mulhs+mul.
6065 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6066 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6071 // Lo,Hi = umul LHS, RHS.
6072 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6073 DAG.getVTList(NVT, NVT), LL, RL);
6075 Hi = UMulLOHI.getValue(1);
6076 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6077 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6078 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6079 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6083 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6084 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6085 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6086 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6087 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6088 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6093 // If nothing else, we can make a libcall.
6094 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
6095 false/*sign irrelevant*/, Hi);
6099 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
6102 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
6105 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
6108 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
6112 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32,
6115 RTLIB::ADD_PPCF128)),
6119 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32,
6122 RTLIB::SUB_PPCF128)),
6126 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32,
6129 RTLIB::MUL_PPCF128)),
6133 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32,
6136 RTLIB::DIV_PPCF128)),
6139 case ISD::FP_EXTEND:
6140 if (VT == MVT::ppcf128) {
6141 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6142 Node->getOperand(0).getValueType()==MVT::f64);
6143 const uint64_t zero = 0;
6144 if (Node->getOperand(0).getValueType()==MVT::f32)
6145 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6147 Hi = Node->getOperand(0);
6148 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6151 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
6154 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
6157 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32,
6160 RTLIB::POWI_PPCF128)),
6166 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6167 switch(Node->getOpcode()) {
6169 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6170 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6173 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6174 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6177 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6178 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6180 default: assert(0 && "Unreachable!");
6182 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
6186 if (VT == MVT::ppcf128) {
6188 ExpandOp(Node->getOperand(0), Lo, Tmp);
6189 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6190 // lo = hi==fabs(hi) ? lo : -lo;
6191 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6192 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6193 DAG.getCondCode(ISD::SETEQ));
6196 SDOperand Mask = (VT == MVT::f64)
6197 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6198 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6199 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6200 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6201 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6202 if (getTypeAction(NVT) == Expand)
6203 ExpandOp(Lo, Lo, Hi);
6207 if (VT == MVT::ppcf128) {
6208 ExpandOp(Node->getOperand(0), Lo, Hi);
6209 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6210 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6213 SDOperand Mask = (VT == MVT::f64)
6214 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6215 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6216 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6217 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6218 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6219 if (getTypeAction(NVT) == Expand)
6220 ExpandOp(Lo, Lo, Hi);
6223 case ISD::FCOPYSIGN: {
6224 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6225 if (getTypeAction(NVT) == Expand)
6226 ExpandOp(Lo, Lo, Hi);
6229 case ISD::SINT_TO_FP:
6230 case ISD::UINT_TO_FP: {
6231 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6232 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
6233 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) {
6234 static uint64_t zero = 0;
6236 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6237 Node->getOperand(0)));
6238 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6240 static uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6241 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6242 Node->getOperand(0)));
6243 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6244 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6245 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6246 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6247 DAG.getConstant(0, MVT::i32),
6248 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6250 APFloat(APInt(128, 2, TwoE32)),
6253 DAG.getCondCode(ISD::SETLT)),
6258 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6259 // si64->ppcf128 done by libcall, below
6260 static uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6261 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6263 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6264 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6265 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6266 DAG.getConstant(0, MVT::i64),
6267 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6269 APFloat(APInt(128, 2, TwoE64)),
6272 DAG.getCondCode(ISD::SETLT)),
6276 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6277 if (Node->getOperand(0).getValueType() == MVT::i64) {
6279 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
6280 else if (VT == MVT::f64)
6281 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
6282 else if (VT == MVT::f80) {
6284 LC = RTLIB::SINTTOFP_I64_F80;
6286 else if (VT == MVT::ppcf128) {
6288 LC = RTLIB::SINTTOFP_I64_PPCF128;
6292 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
6294 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
6297 // Promote the operand if needed.
6298 if (getTypeAction(SrcVT) == Promote) {
6299 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6301 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6302 DAG.getValueType(SrcVT))
6303 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6304 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6307 const char *LibCall = TLI.getLibcallName(LC);
6309 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
6311 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6312 Node->getOperand(0));
6313 if (getTypeAction(Lo.getValueType()) == Expand)
6314 ExpandOp(Lo, Lo, Hi);
6320 // Make sure the resultant values have been legalized themselves, unless this
6321 // is a type that requires multi-step expansion.
6322 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6323 Lo = LegalizeOp(Lo);
6325 // Don't legalize the high part if it is expanded to a single node.
6326 Hi = LegalizeOp(Hi);
6329 // Remember in a map if the values will be reused later.
6330 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6331 assert(isNew && "Value already expanded?!?");
6334 /// SplitVectorOp - Given an operand of vector type, break it down into
6335 /// two smaller values, still of vector type.
6336 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6338 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
6339 SDNode *Node = Op.Val;
6340 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
6341 assert(NumElements > 1 && "Cannot split a single element vector!");
6343 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
6345 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6346 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6348 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
6349 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
6351 // See if we already split it.
6352 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6353 = SplitNodes.find(Op);
6354 if (I != SplitNodes.end()) {
6355 Lo = I->second.first;
6356 Hi = I->second.second;
6360 switch (Node->getOpcode()) {
6365 assert(0 && "Unhandled operation in SplitVectorOp!");
6367 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6368 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6370 case ISD::BUILD_PAIR:
6371 Lo = Node->getOperand(0);
6372 Hi = Node->getOperand(1);
6374 case ISD::INSERT_VECTOR_ELT: {
6375 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6376 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
6377 SDOperand ScalarOp = Node->getOperand(1);
6378 if (Index < NewNumElts_Lo)
6379 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6380 DAG.getConstant(Index, TLI.getPointerTy()));
6382 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6383 DAG.getConstant(Index - NewNumElts_Lo,
6384 TLI.getPointerTy()));
6387 case ISD::VECTOR_SHUFFLE: {
6388 // Build the low part.
6389 SDOperand Mask = Node->getOperand(2);
6390 SmallVector<SDOperand, 8> Ops;
6391 MVT::ValueType PtrVT = TLI.getPointerTy();
6393 // Insert all of the elements from the input that are needed. We use
6394 // buildvector of extractelement here because the input vectors will have
6395 // to be legalized, so this makes the code simpler.
6396 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6397 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6398 SDOperand InVec = Node->getOperand(0);
6399 if (Idx >= NumElements) {
6400 InVec = Node->getOperand(1);
6403 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6404 DAG.getConstant(Idx, PtrVT)));
6406 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6409 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6410 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6411 SDOperand InVec = Node->getOperand(0);
6412 if (Idx >= NumElements) {
6413 InVec = Node->getOperand(1);
6416 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6417 DAG.getConstant(Idx, PtrVT)));
6419 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6422 case ISD::BUILD_VECTOR: {
6423 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6424 Node->op_begin()+NewNumElts_Lo);
6425 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6427 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6429 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6432 case ISD::CONCAT_VECTORS: {
6433 // FIXME: Handle non-power-of-two vectors?
6434 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6435 if (NewNumSubvectors == 1) {
6436 Lo = Node->getOperand(0);
6437 Hi = Node->getOperand(1);
6439 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6440 Node->op_begin()+NewNumSubvectors);
6441 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6443 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6445 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6450 SDOperand Cond = Node->getOperand(0);
6452 SDOperand LL, LH, RL, RH;
6453 SplitVectorOp(Node->getOperand(1), LL, LH);
6454 SplitVectorOp(Node->getOperand(2), RL, RH);
6456 if (MVT::isVector(Cond.getValueType())) {
6457 // Handle a vector merge.
6459 SplitVectorOp(Cond, CL, CH);
6460 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6461 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6463 // Handle a simple select with vector operands.
6464 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6465 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6485 SDOperand LL, LH, RL, RH;
6486 SplitVectorOp(Node->getOperand(0), LL, LH);
6487 SplitVectorOp(Node->getOperand(1), RL, RH);
6489 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6490 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6495 SplitVectorOp(Node->getOperand(0), L, H);
6497 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6498 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6509 case ISD::FP_TO_SINT:
6510 case ISD::FP_TO_UINT:
6511 case ISD::SINT_TO_FP:
6512 case ISD::UINT_TO_FP: {
6514 SplitVectorOp(Node->getOperand(0), L, H);
6516 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6517 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6521 LoadSDNode *LD = cast<LoadSDNode>(Node);
6522 SDOperand Ch = LD->getChain();
6523 SDOperand Ptr = LD->getBasePtr();
6524 const Value *SV = LD->getSrcValue();
6525 int SVOffset = LD->getSrcValueOffset();
6526 unsigned Alignment = LD->getAlignment();
6527 bool isVolatile = LD->isVolatile();
6529 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6530 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
6531 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6532 DAG.getIntPtrConstant(IncrementSize));
6533 SVOffset += IncrementSize;
6534 Alignment = MinAlign(Alignment, IncrementSize);
6535 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6537 // Build a factor node to remember that this load is independent of the
6539 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6542 // Remember that we legalized the chain.
6543 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6546 case ISD::BIT_CONVERT: {
6547 // We know the result is a vector. The input may be either a vector or a
6549 SDOperand InOp = Node->getOperand(0);
6550 if (!MVT::isVector(InOp.getValueType()) ||
6551 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
6552 // The input is a scalar or single-element vector.
6553 // Lower to a store/load so that it can be split.
6554 // FIXME: this could be improved probably.
6555 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6557 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6558 InOp, Ptr, NULL, 0);
6559 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0);
6561 // Split the vector and convert each of the pieces now.
6562 SplitVectorOp(InOp, Lo, Hi);
6563 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6564 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6569 // Remember in a map if the values will be reused later.
6571 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6572 assert(isNew && "Value already split?!?");
6576 /// ScalarizeVectorOp - Given an operand of single-element vector type
6577 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6578 /// scalar (e.g. f32) value.
6579 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6580 assert(MVT::isVector(Op.getValueType()) &&
6581 "Bad ScalarizeVectorOp invocation!");
6582 SDNode *Node = Op.Val;
6583 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
6584 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
6586 // See if we already scalarized it.
6587 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
6588 if (I != ScalarizedNodes.end()) return I->second;
6591 switch (Node->getOpcode()) {
6594 Node->dump(&DAG); cerr << "\n";
6596 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
6613 Result = DAG.getNode(Node->getOpcode(),
6615 ScalarizeVectorOp(Node->getOperand(0)),
6616 ScalarizeVectorOp(Node->getOperand(1)));
6623 Result = DAG.getNode(Node->getOpcode(),
6625 ScalarizeVectorOp(Node->getOperand(0)));
6628 Result = DAG.getNode(Node->getOpcode(),
6630 ScalarizeVectorOp(Node->getOperand(0)),
6631 Node->getOperand(1));
6634 LoadSDNode *LD = cast<LoadSDNode>(Node);
6635 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
6636 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
6638 const Value *SV = LD->getSrcValue();
6639 int SVOffset = LD->getSrcValueOffset();
6640 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
6641 LD->isVolatile(), LD->getAlignment());
6643 // Remember that we legalized the chain.
6644 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
6647 case ISD::BUILD_VECTOR:
6648 Result = Node->getOperand(0);
6650 case ISD::INSERT_VECTOR_ELT:
6651 // Returning the inserted scalar element.
6652 Result = Node->getOperand(1);
6654 case ISD::CONCAT_VECTORS:
6655 assert(Node->getOperand(0).getValueType() == NewVT &&
6656 "Concat of non-legal vectors not yet supported!");
6657 Result = Node->getOperand(0);
6659 case ISD::VECTOR_SHUFFLE: {
6660 // Figure out if the scalar is the LHS or RHS and return it.
6661 SDOperand EltNum = Node->getOperand(2).getOperand(0);
6662 if (cast<ConstantSDNode>(EltNum)->getValue())
6663 Result = ScalarizeVectorOp(Node->getOperand(1));
6665 Result = ScalarizeVectorOp(Node->getOperand(0));
6668 case ISD::EXTRACT_SUBVECTOR:
6669 Result = Node->getOperand(0);
6670 assert(Result.getValueType() == NewVT);
6672 case ISD::BIT_CONVERT:
6673 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
6676 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
6677 ScalarizeVectorOp(Op.getOperand(1)),
6678 ScalarizeVectorOp(Op.getOperand(2)));
6682 if (TLI.isTypeLegal(NewVT))
6683 Result = LegalizeOp(Result);
6684 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
6685 assert(isNew && "Value already scalarized?");
6690 // SelectionDAG::Legalize - This is the entry point for the file.
6692 void SelectionDAG::Legalize() {
6693 if (ViewLegalizeDAGs) viewGraph();
6695 /// run - This is the main entry point to this class.
6697 SelectionDAGLegalize(*this).LegalizeDAG();