1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Target/TargetLowering.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Visibility.h"
31 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
32 cl::desc("Pop up a window to show dags before legalize"));
34 static const bool ViewLegalizeDAGs = 0;
37 //===----------------------------------------------------------------------===//
38 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
39 /// hacks on it until the target machine can handle it. This involves
40 /// eliminating value sizes the machine cannot handle (promoting small sizes to
41 /// large sizes or splitting up large values into small values) as well as
42 /// eliminating operations the machine cannot handle.
44 /// This code also does a small amount of optimization and recognition of idioms
45 /// as part of its processing. For example, if a target does not support a
46 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
47 /// will attempt merge setcc and brc instructions into brcc's.
50 class VISIBILITY_HIDDEN SelectionDAGLegalize {
54 // Libcall insertion helpers.
56 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
57 /// legalized. We use this to ensure that calls are properly serialized
58 /// against each other, including inserted libcalls.
59 SDOperand LastCALLSEQ_END;
61 /// IsLegalizingCall - This member is used *only* for purposes of providing
62 /// helpful assertions that a libcall isn't created while another call is
63 /// being legalized (which could lead to non-serialized call sequences).
64 bool IsLegalizingCall;
67 Legal, // The target natively supports this operation.
68 Promote, // This operation should be executed in a larger type.
69 Expand // Try to expand this to other ops, otherwise use a libcall.
72 /// ValueTypeActions - This is a bitvector that contains two bits for each
73 /// value type, where the two bits correspond to the LegalizeAction enum.
74 /// This can be queried with "getTypeAction(VT)".
75 TargetLowering::ValueTypeActionImpl ValueTypeActions;
77 /// LegalizedNodes - For nodes that are of legal width, and that have more
78 /// than one use, this map indicates what regularized operand to use. This
79 /// allows us to avoid legalizing the same thing more than once.
80 std::map<SDOperand, SDOperand> LegalizedNodes;
82 /// PromotedNodes - For nodes that are below legal width, and that have more
83 /// than one use, this map indicates what promoted value to use. This allows
84 /// us to avoid promoting the same thing more than once.
85 std::map<SDOperand, SDOperand> PromotedNodes;
87 /// ExpandedNodes - For nodes that need to be expanded this map indicates
88 /// which which operands are the expanded version of the input. This allows
89 /// us to avoid expanding the same node more than once.
90 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
92 /// SplitNodes - For vector nodes that need to be split, this map indicates
93 /// which which operands are the split version of the input. This allows us
94 /// to avoid splitting the same node more than once.
95 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
97 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
98 /// concrete packed types, this contains the mapping of ones we have already
99 /// processed to the result.
100 std::map<SDOperand, SDOperand> PackedNodes;
102 void AddLegalizedOperand(SDOperand From, SDOperand To) {
103 LegalizedNodes.insert(std::make_pair(From, To));
104 // If someone requests legalization of the new node, return itself.
106 LegalizedNodes.insert(std::make_pair(To, To));
108 void AddPromotedOperand(SDOperand From, SDOperand To) {
109 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
110 assert(isNew && "Got into the map somehow?");
111 // If someone requests legalization of the new node, return itself.
112 LegalizedNodes.insert(std::make_pair(To, To));
117 SelectionDAGLegalize(SelectionDAG &DAG);
119 /// getTypeAction - Return how we should legalize values of this type, either
120 /// it is already legal or we need to expand it into multiple registers of
121 /// smaller integer type, or we need to promote it to a larger type.
122 LegalizeAction getTypeAction(MVT::ValueType VT) const {
123 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
126 /// isTypeLegal - Return true if this type is legal on this target.
128 bool isTypeLegal(MVT::ValueType VT) const {
129 return getTypeAction(VT) == Legal;
135 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
136 /// appropriate for its type.
137 void HandleOp(SDOperand Op);
139 /// LegalizeOp - We know that the specified value has a legal type.
140 /// Recursively ensure that the operands have legal types, then return the
142 SDOperand LegalizeOp(SDOperand O);
144 /// PromoteOp - Given an operation that produces a value in an invalid type,
145 /// promote it to compute the value into a larger type. The produced value
146 /// will have the correct bits for the low portion of the register, but no
147 /// guarantee is made about the top bits: it may be zero, sign-extended, or
149 SDOperand PromoteOp(SDOperand O);
151 /// ExpandOp - Expand the specified SDOperand into its two component pieces
152 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
153 /// the LegalizeNodes map is filled in for any results that are not expanded,
154 /// the ExpandedNodes map is filled in for any results that are expanded, and
155 /// the Lo/Hi values are returned. This applies to integer types and Vector
157 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
159 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
160 /// two smaller values of MVT::Vector type.
161 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
163 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
164 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
165 /// this is called, we know that PackedVT is the right type for the result and
166 /// we know that this type is legal for the target.
167 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
169 /// isShuffleLegal - Return true if a vector shuffle is legal with the
170 /// specified mask and type. Targets can specify exactly which masks they
171 /// support and the code generator is tasked with not creating illegal masks.
173 /// Note that this will also return true for shuffles that are promoted to a
176 /// If this is a legal shuffle, this method returns the (possibly promoted)
177 /// build_vector Mask. If it's not a legal shuffle, it returns null.
178 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
180 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest);
182 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
184 SDOperand CreateStackTemporary(MVT::ValueType VT);
186 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
188 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
191 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
192 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
193 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
194 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
196 MVT::ValueType DestVT);
197 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
199 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
202 SDOperand ExpandBSWAP(SDOperand Op);
203 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
204 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
205 SDOperand &Lo, SDOperand &Hi);
206 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
207 SDOperand &Lo, SDOperand &Hi);
209 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
210 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
212 SDOperand getIntPtrConstant(uint64_t Val) {
213 return DAG.getConstant(Val, TLI.getPointerTy());
218 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
219 /// specified mask and type. Targets can specify exactly which masks they
220 /// support and the code generator is tasked with not creating illegal masks.
222 /// Note that this will also return true for shuffles that are promoted to a
224 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
225 SDOperand Mask) const {
226 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
228 case TargetLowering::Legal:
229 case TargetLowering::Custom:
231 case TargetLowering::Promote: {
232 // If this is promoted to a different type, convert the shuffle mask and
233 // ask if it is legal in the promoted type!
234 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
236 // If we changed # elements, change the shuffle mask.
237 unsigned NumEltsGrowth =
238 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
239 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
240 if (NumEltsGrowth > 1) {
241 // Renumber the elements.
242 std::vector<SDOperand> Ops;
243 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
244 SDOperand InOp = Mask.getOperand(i);
245 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
246 if (InOp.getOpcode() == ISD::UNDEF)
247 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
249 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
250 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
254 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, Ops);
260 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
263 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
264 /// specified vector opcode.
265 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
267 default: assert(0 && "Don't know how to scalarize this opcode!");
268 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
269 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
270 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
271 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
272 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
273 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
274 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
275 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
279 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
280 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
281 ValueTypeActions(TLI.getValueTypeActions()) {
282 assert(MVT::LAST_VALUETYPE <= 32 &&
283 "Too many value types for ValueTypeActions to hold!");
286 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
287 /// not been visited yet and if all of its operands have already been visited.
288 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
289 std::map<SDNode*, unsigned> &Visited) {
290 if (++Visited[N] != N->getNumOperands())
291 return; // Haven't visited all operands yet
295 if (N->hasOneUse()) { // Tail recurse in common case.
296 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
300 // Now that we have N in, add anything that uses it if all of their operands
302 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
303 ComputeTopDownOrdering(*UI, Order, Visited);
307 void SelectionDAGLegalize::LegalizeDAG() {
308 LastCALLSEQ_END = DAG.getEntryNode();
309 IsLegalizingCall = false;
311 // The legalize process is inherently a bottom-up recursive process (users
312 // legalize their uses before themselves). Given infinite stack space, we
313 // could just start legalizing on the root and traverse the whole graph. In
314 // practice however, this causes us to run out of stack space on large basic
315 // blocks. To avoid this problem, compute an ordering of the nodes where each
316 // node is only legalized after all of its operands are legalized.
317 std::map<SDNode*, unsigned> Visited;
318 std::vector<SDNode*> Order;
320 // Compute ordering from all of the leaves in the graphs, those (like the
321 // entry node) that have no operands.
322 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
323 E = DAG.allnodes_end(); I != E; ++I) {
324 if (I->getNumOperands() == 0) {
326 ComputeTopDownOrdering(I, Order, Visited);
330 assert(Order.size() == Visited.size() &&
332 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
333 "Error: DAG is cyclic!");
336 for (unsigned i = 0, e = Order.size(); i != e; ++i)
337 HandleOp(SDOperand(Order[i], 0));
339 // Finally, it's possible the root changed. Get the new root.
340 SDOperand OldRoot = DAG.getRoot();
341 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
342 DAG.setRoot(LegalizedNodes[OldRoot]);
344 ExpandedNodes.clear();
345 LegalizedNodes.clear();
346 PromotedNodes.clear();
350 // Remove dead nodes now.
351 DAG.RemoveDeadNodes(OldRoot.Val);
355 /// FindCallEndFromCallStart - Given a chained node that is part of a call
356 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
357 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
358 if (Node->getOpcode() == ISD::CALLSEQ_END)
360 if (Node->use_empty())
361 return 0; // No CallSeqEnd
363 // The chain is usually at the end.
364 SDOperand TheChain(Node, Node->getNumValues()-1);
365 if (TheChain.getValueType() != MVT::Other) {
366 // Sometimes it's at the beginning.
367 TheChain = SDOperand(Node, 0);
368 if (TheChain.getValueType() != MVT::Other) {
369 // Otherwise, hunt for it.
370 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
371 if (Node->getValueType(i) == MVT::Other) {
372 TheChain = SDOperand(Node, i);
376 // Otherwise, we walked into a node without a chain.
377 if (TheChain.getValueType() != MVT::Other)
382 for (SDNode::use_iterator UI = Node->use_begin(),
383 E = Node->use_end(); UI != E; ++UI) {
385 // Make sure to only follow users of our token chain.
387 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
388 if (User->getOperand(i) == TheChain)
389 if (SDNode *Result = FindCallEndFromCallStart(User))
395 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
396 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
397 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
398 assert(Node && "Didn't find callseq_start for a call??");
399 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
401 assert(Node->getOperand(0).getValueType() == MVT::Other &&
402 "Node doesn't have a token chain argument!");
403 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
406 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
407 /// see if any uses can reach Dest. If no dest operands can get to dest,
408 /// legalize them, legalize ourself, and return false, otherwise, return true.
409 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N,
411 if (N == Dest) return true; // N certainly leads to Dest :)
413 // If the first result of this node has been already legalized, then it cannot
415 switch (getTypeAction(N->getValueType(0))) {
417 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
420 if (PromotedNodes.count(SDOperand(N, 0))) return false;
423 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
427 // Okay, this node has not already been legalized. Check and legalize all
428 // operands. If none lead to Dest, then we can legalize this node.
429 bool OperandsLeadToDest = false;
430 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
431 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
432 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest);
434 if (OperandsLeadToDest) return true;
436 // Okay, this node looks safe, legalize it and return false.
437 HandleOp(SDOperand(N, 0));
441 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
442 /// appropriate for its type.
443 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
444 switch (getTypeAction(Op.getValueType())) {
445 default: assert(0 && "Bad type action!");
446 case Legal: LegalizeOp(Op); break;
447 case Promote: PromoteOp(Op); break;
449 if (Op.getValueType() != MVT::Vector) {
454 unsigned NumOps = N->getNumOperands();
455 unsigned NumElements =
456 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
457 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
458 MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
459 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
460 // In the common case, this is a legal vector type, convert it to the
461 // packed operation and type now.
462 PackVectorOp(Op, PackedVT);
463 } else if (NumElements == 1) {
464 // Otherwise, if this is a single element vector, convert it to a
466 PackVectorOp(Op, EVT);
468 // Otherwise, this is a multiple element vector that isn't supported.
469 // Split it in half and legalize both parts.
471 SplitVectorOp(Op, X, Y);
479 /// LegalizeOp - We know that the specified value has a legal type.
480 /// Recursively ensure that the operands have legal types, then return the
482 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
483 assert(isTypeLegal(Op.getValueType()) &&
484 "Caller should expand or promote operands that are not legal!");
485 SDNode *Node = Op.Val;
487 // If this operation defines any values that cannot be represented in a
488 // register on this target, make sure to expand or promote them.
489 if (Node->getNumValues() > 1) {
490 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
491 if (getTypeAction(Node->getValueType(i)) != Legal) {
492 HandleOp(Op.getValue(i));
493 assert(LegalizedNodes.count(Op) &&
494 "Handling didn't add legal operands!");
495 return LegalizedNodes[Op];
499 // Note that LegalizeOp may be reentered even from single-use nodes, which
500 // means that we always must cache transformed nodes.
501 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
502 if (I != LegalizedNodes.end()) return I->second;
504 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
505 SDOperand Result = Op;
506 bool isCustom = false;
508 switch (Node->getOpcode()) {
509 case ISD::FrameIndex:
510 case ISD::EntryToken:
512 case ISD::BasicBlock:
513 case ISD::TargetFrameIndex:
514 case ISD::TargetJumpTable:
515 case ISD::TargetConstant:
516 case ISD::TargetConstantFP:
517 case ISD::TargetConstantPool:
518 case ISD::TargetGlobalAddress:
519 case ISD::TargetExternalSymbol:
524 // Primitives must all be legal.
525 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
526 "This must be legal!");
529 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
530 // If this is a target node, legalize it by legalizing the operands then
531 // passing it through.
532 std::vector<SDOperand> Ops;
533 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
534 Ops.push_back(LegalizeOp(Node->getOperand(i)));
536 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops);
538 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
539 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
540 return Result.getValue(Op.ResNo);
542 // Otherwise this is an unhandled builtin node. splat.
544 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
546 assert(0 && "Do not know how to legalize this operator!");
548 case ISD::GlobalAddress:
549 case ISD::ExternalSymbol:
550 case ISD::ConstantPool:
551 case ISD::JumpTable: // Nothing to do.
552 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
553 default: assert(0 && "This action is not supported yet!");
554 case TargetLowering::Custom:
555 Tmp1 = TLI.LowerOperation(Op, DAG);
556 if (Tmp1.Val) Result = Tmp1;
557 // FALLTHROUGH if the target doesn't want to lower this op after all.
558 case TargetLowering::Legal:
562 case ISD::AssertSext:
563 case ISD::AssertZext:
564 Tmp1 = LegalizeOp(Node->getOperand(0));
565 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
567 case ISD::MERGE_VALUES:
568 // Legalize eliminates MERGE_VALUES nodes.
569 Result = Node->getOperand(Op.ResNo);
571 case ISD::CopyFromReg:
572 Tmp1 = LegalizeOp(Node->getOperand(0));
573 Result = Op.getValue(0);
574 if (Node->getNumValues() == 2) {
575 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
577 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
578 if (Node->getNumOperands() == 3) {
579 Tmp2 = LegalizeOp(Node->getOperand(2));
580 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
582 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
584 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
586 // Since CopyFromReg produces two values, make sure to remember that we
587 // legalized both of them.
588 AddLegalizedOperand(Op.getValue(0), Result);
589 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
590 return Result.getValue(Op.ResNo);
592 MVT::ValueType VT = Op.getValueType();
593 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
594 default: assert(0 && "This action is not supported yet!");
595 case TargetLowering::Expand:
596 if (MVT::isInteger(VT))
597 Result = DAG.getConstant(0, VT);
598 else if (MVT::isFloatingPoint(VT))
599 Result = DAG.getConstantFP(0, VT);
601 assert(0 && "Unknown value type!");
603 case TargetLowering::Legal:
609 case ISD::INTRINSIC_W_CHAIN:
610 case ISD::INTRINSIC_WO_CHAIN:
611 case ISD::INTRINSIC_VOID: {
612 std::vector<SDOperand> Ops;
613 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
614 Ops.push_back(LegalizeOp(Node->getOperand(i)));
615 Result = DAG.UpdateNodeOperands(Result, Ops);
617 // Allow the target to custom lower its intrinsics if it wants to.
618 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
619 TargetLowering::Custom) {
620 Tmp3 = TLI.LowerOperation(Result, DAG);
621 if (Tmp3.Val) Result = Tmp3;
624 if (Result.Val->getNumValues() == 1) break;
626 // Must have return value and chain result.
627 assert(Result.Val->getNumValues() == 2 &&
628 "Cannot return more than two values!");
630 // Since loads produce two values, make sure to remember that we
631 // legalized both of them.
632 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
633 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
634 return Result.getValue(Op.ResNo);
638 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
639 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
641 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
642 case TargetLowering::Promote:
643 default: assert(0 && "This action is not supported yet!");
644 case TargetLowering::Expand: {
645 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
646 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
647 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
649 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
650 const std::string &FName =
651 cast<StringSDNode>(Node->getOperand(3))->getValue();
652 const std::string &DirName =
653 cast<StringSDNode>(Node->getOperand(4))->getValue();
654 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
656 std::vector<SDOperand> Ops;
657 Ops.push_back(Tmp1); // chain
658 SDOperand LineOp = Node->getOperand(1);
659 SDOperand ColOp = Node->getOperand(2);
662 Ops.push_back(LineOp); // line #
663 Ops.push_back(ColOp); // col #
664 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
665 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
667 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
668 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
669 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
670 Ops.push_back(DAG.getConstant(ID, MVT::i32));
671 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops);
674 Result = Tmp1; // chain
678 case TargetLowering::Legal:
679 if (Tmp1 != Node->getOperand(0) ||
680 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
681 std::vector<SDOperand> Ops;
683 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
684 Ops.push_back(Node->getOperand(1)); // line # must be legal.
685 Ops.push_back(Node->getOperand(2)); // col # must be legal.
687 // Otherwise promote them.
688 Ops.push_back(PromoteOp(Node->getOperand(1)));
689 Ops.push_back(PromoteOp(Node->getOperand(2)));
691 Ops.push_back(Node->getOperand(3)); // filename must be legal.
692 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
693 Result = DAG.UpdateNodeOperands(Result, Ops);
700 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
701 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
702 default: assert(0 && "This action is not supported yet!");
703 case TargetLowering::Legal:
704 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
705 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
706 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
707 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
708 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
713 case ISD::DEBUG_LABEL:
714 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
715 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
716 default: assert(0 && "This action is not supported yet!");
717 case TargetLowering::Legal:
718 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
719 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
720 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
726 // We know we don't need to expand constants here, constants only have one
727 // value and we check that it is fine above.
729 // FIXME: Maybe we should handle things like targets that don't support full
730 // 32-bit immediates?
732 case ISD::ConstantFP: {
733 // Spill FP immediates to the constant pool if the target cannot directly
734 // codegen them. Targets often have some immediate values that can be
735 // efficiently generated into an FP register without a load. We explicitly
736 // leave these constants as ConstantFP nodes for the target to deal with.
737 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
739 // Check to see if this FP immediate is already legal.
740 bool isLegal = false;
741 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
742 E = TLI.legal_fpimm_end(); I != E; ++I)
743 if (CFP->isExactlyValue(*I)) {
748 // If this is a legal constant, turn it into a TargetConstantFP node.
750 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
754 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
755 default: assert(0 && "This action is not supported yet!");
756 case TargetLowering::Custom:
757 Tmp3 = TLI.LowerOperation(Result, DAG);
763 case TargetLowering::Expand:
764 // Otherwise we need to spill the constant to memory.
767 // If a FP immediate is precise when represented as a float and if the
768 // target can do an extending load from float to double, we put it into
769 // the constant pool as a float, even if it's is statically typed as a
771 MVT::ValueType VT = CFP->getValueType(0);
772 bool isDouble = VT == MVT::f64;
773 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
774 Type::FloatTy, CFP->getValue());
775 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
776 // Only do this if the target has a native EXTLOAD instruction from
778 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
779 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
784 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
786 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
787 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
789 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
790 DAG.getSrcValue(NULL));
795 case ISD::TokenFactor:
796 if (Node->getNumOperands() == 2) {
797 Tmp1 = LegalizeOp(Node->getOperand(0));
798 Tmp2 = LegalizeOp(Node->getOperand(1));
799 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
800 } else if (Node->getNumOperands() == 3) {
801 Tmp1 = LegalizeOp(Node->getOperand(0));
802 Tmp2 = LegalizeOp(Node->getOperand(1));
803 Tmp3 = LegalizeOp(Node->getOperand(2));
804 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
806 std::vector<SDOperand> Ops;
807 // Legalize the operands.
808 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
809 Ops.push_back(LegalizeOp(Node->getOperand(i)));
810 Result = DAG.UpdateNodeOperands(Result, Ops);
814 case ISD::FORMAL_ARGUMENTS:
816 // The only option for this is to custom lower it.
817 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
818 assert(Tmp3.Val && "Target didn't custom lower this node!");
819 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
820 "Lowering call/formal_arguments produced unexpected # results!");
822 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
823 // remember that we legalized all of them, so it doesn't get relegalized.
824 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
825 Tmp1 = LegalizeOp(Tmp3.getValue(i));
828 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
832 case ISD::BUILD_VECTOR:
833 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
834 default: assert(0 && "This action is not supported yet!");
835 case TargetLowering::Custom:
836 Tmp3 = TLI.LowerOperation(Result, DAG);
842 case TargetLowering::Expand:
843 Result = ExpandBUILD_VECTOR(Result.Val);
847 case ISD::INSERT_VECTOR_ELT:
848 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
849 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
850 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
851 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
853 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
854 Node->getValueType(0))) {
855 default: assert(0 && "This action is not supported yet!");
856 case TargetLowering::Legal:
858 case TargetLowering::Custom:
859 Tmp3 = TLI.LowerOperation(Result, DAG);
865 case TargetLowering::Expand: {
866 // If the insert index is a constant, codegen this as a scalar_to_vector,
867 // then a shuffle that inserts it into the right position in the vector.
868 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
869 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
870 Tmp1.getValueType(), Tmp2);
872 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
873 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
874 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT);
876 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
877 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
879 std::vector<SDOperand> ShufOps;
880 for (unsigned i = 0; i != NumElts; ++i) {
881 if (i != InsertPos->getValue())
882 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
884 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
886 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,ShufOps);
888 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
889 Tmp1, ScVec, ShufMask);
890 Result = LegalizeOp(Result);
894 // If the target doesn't support this, we have to spill the input vector
895 // to a temporary stack slot, update the element, then reload it. This is
896 // badness. We could also load the value into a vector register (either
897 // with a "move to register" or "extload into register" instruction, then
898 // permute it into place, if the idx is a constant and if the idx is
899 // supported by the target.
900 MVT::ValueType VT = Tmp1.getValueType();
901 MVT::ValueType EltVT = Tmp2.getValueType();
902 MVT::ValueType IdxVT = Tmp3.getValueType();
903 MVT::ValueType PtrVT = TLI.getPointerTy();
904 SDOperand StackPtr = CreateStackTemporary(VT);
906 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
907 Tmp1, StackPtr, DAG.getSrcValue(NULL));
909 // Truncate or zero extend offset to target pointer type.
910 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
911 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
912 // Add the offset to the index.
913 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
914 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
915 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
916 // Store the scalar value.
917 Ch = DAG.getNode(ISD::STORE, MVT::Other, Ch,
918 Tmp2, StackPtr2, DAG.getSrcValue(NULL));
919 // Load the updated vector.
920 Result = DAG.getLoad(VT, Ch, StackPtr, DAG.getSrcValue(NULL));
925 case ISD::SCALAR_TO_VECTOR:
926 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
927 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
931 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
932 Result = DAG.UpdateNodeOperands(Result, Tmp1);
933 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
934 Node->getValueType(0))) {
935 default: assert(0 && "This action is not supported yet!");
936 case TargetLowering::Legal:
938 case TargetLowering::Custom:
939 Tmp3 = TLI.LowerOperation(Result, DAG);
945 case TargetLowering::Expand:
946 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
950 case ISD::VECTOR_SHUFFLE:
951 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
952 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
953 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
955 // Allow targets to custom lower the SHUFFLEs they support.
956 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
957 default: assert(0 && "Unknown operation action!");
958 case TargetLowering::Legal:
959 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
960 "vector shuffle should not be created if not legal!");
962 case TargetLowering::Custom:
963 Tmp3 = TLI.LowerOperation(Result, DAG);
969 case TargetLowering::Expand: {
970 MVT::ValueType VT = Node->getValueType(0);
971 MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
972 MVT::ValueType PtrVT = TLI.getPointerTy();
973 SDOperand Mask = Node->getOperand(2);
974 unsigned NumElems = Mask.getNumOperands();
975 std::vector<SDOperand> Ops;
976 for (unsigned i = 0; i != NumElems; ++i) {
977 SDOperand Arg = Mask.getOperand(i);
978 if (Arg.getOpcode() == ISD::UNDEF) {
979 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
981 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
982 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
984 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
985 DAG.getConstant(Idx, PtrVT)));
987 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
988 DAG.getConstant(Idx - NumElems, PtrVT)));
991 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, Ops);
994 case TargetLowering::Promote: {
995 // Change base type to a different vector type.
996 MVT::ValueType OVT = Node->getValueType(0);
997 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
999 // Cast the two input vectors.
1000 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1001 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1003 // Convert the shuffle mask to the right # elements.
1004 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1005 assert(Tmp3.Val && "Shuffle not legal?");
1006 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1007 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1013 case ISD::EXTRACT_VECTOR_ELT:
1014 Tmp1 = LegalizeOp(Node->getOperand(0));
1015 Tmp2 = LegalizeOp(Node->getOperand(1));
1016 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1018 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
1019 Tmp1.getValueType())) {
1020 default: assert(0 && "This action is not supported yet!");
1021 case TargetLowering::Legal:
1023 case TargetLowering::Custom:
1024 Tmp3 = TLI.LowerOperation(Result, DAG);
1030 case TargetLowering::Expand:
1031 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1036 case ISD::VEXTRACT_VECTOR_ELT:
1037 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
1040 case ISD::CALLSEQ_START: {
1041 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1043 // Recursively Legalize all of the inputs of the call end that do not lead
1044 // to this call start. This ensures that any libcalls that need be inserted
1045 // are inserted *before* the CALLSEQ_START.
1046 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1047 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node);
1049 // Now that we legalized all of the inputs (which may have inserted
1050 // libcalls) create the new CALLSEQ_START node.
1051 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1053 // Merge in the last call, to ensure that this call start after the last
1055 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1056 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1057 Tmp1 = LegalizeOp(Tmp1);
1060 // Do not try to legalize the target-specific arguments (#1+).
1061 if (Tmp1 != Node->getOperand(0)) {
1062 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
1064 Result = DAG.UpdateNodeOperands(Result, Ops);
1067 // Remember that the CALLSEQ_START is legalized.
1068 AddLegalizedOperand(Op.getValue(0), Result);
1069 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1070 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1072 // Now that the callseq_start and all of the non-call nodes above this call
1073 // sequence have been legalized, legalize the call itself. During this
1074 // process, no libcalls can/will be inserted, guaranteeing that no calls
1076 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1077 SDOperand InCallSEQ = LastCALLSEQ_END;
1078 // Note that we are selecting this call!
1079 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1080 IsLegalizingCall = true;
1082 // Legalize the call, starting from the CALLSEQ_END.
1083 LegalizeOp(LastCALLSEQ_END);
1084 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1087 case ISD::CALLSEQ_END:
1088 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1089 // will cause this node to be legalized as well as handling libcalls right.
1090 if (LastCALLSEQ_END.Val != Node) {
1091 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1092 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1093 assert(I != LegalizedNodes.end() &&
1094 "Legalizing the call start should have legalized this node!");
1098 // Otherwise, the call start has been legalized and everything is going
1099 // according to plan. Just legalize ourselves normally here.
1100 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1101 // Do not try to legalize the target-specific arguments (#1+), except for
1102 // an optional flag input.
1103 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1104 if (Tmp1 != Node->getOperand(0)) {
1105 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
1107 Result = DAG.UpdateNodeOperands(Result, Ops);
1110 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1111 if (Tmp1 != Node->getOperand(0) ||
1112 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1113 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
1116 Result = DAG.UpdateNodeOperands(Result, Ops);
1119 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1120 // This finishes up call legalization.
1121 IsLegalizingCall = false;
1123 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1124 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1125 if (Node->getNumValues() == 2)
1126 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1127 return Result.getValue(Op.ResNo);
1128 case ISD::DYNAMIC_STACKALLOC: {
1129 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1130 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1131 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1132 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1134 Tmp1 = Result.getValue(0);
1135 Tmp2 = Result.getValue(1);
1136 switch (TLI.getOperationAction(Node->getOpcode(),
1137 Node->getValueType(0))) {
1138 default: assert(0 && "This action is not supported yet!");
1139 case TargetLowering::Expand: {
1140 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1141 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1142 " not tell us which reg is the stack pointer!");
1143 SDOperand Chain = Tmp1.getOperand(0);
1144 SDOperand Size = Tmp2.getOperand(1);
1145 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1146 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1147 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1148 Tmp1 = LegalizeOp(Tmp1);
1149 Tmp2 = LegalizeOp(Tmp2);
1152 case TargetLowering::Custom:
1153 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1155 Tmp1 = LegalizeOp(Tmp3);
1156 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1159 case TargetLowering::Legal:
1162 // Since this op produce two values, make sure to remember that we
1163 // legalized both of them.
1164 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1165 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1166 return Op.ResNo ? Tmp2 : Tmp1;
1168 case ISD::INLINEASM: {
1169 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
1170 bool Changed = false;
1171 // Legalize all of the operands of the inline asm, in case they are nodes
1172 // that need to be expanded or something. Note we skip the asm string and
1173 // all of the TargetConstant flags.
1174 SDOperand Op = LegalizeOp(Ops[0]);
1175 Changed = Op != Ops[0];
1178 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1179 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1180 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1181 for (++i; NumVals; ++i, --NumVals) {
1182 SDOperand Op = LegalizeOp(Ops[i]);
1191 Op = LegalizeOp(Ops.back());
1192 Changed |= Op != Ops.back();
1197 Result = DAG.UpdateNodeOperands(Result, Ops);
1199 // INLINE asm returns a chain and flag, make sure to add both to the map.
1200 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1201 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1202 return Result.getValue(Op.ResNo);
1205 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1206 // Ensure that libcalls are emitted before a branch.
1207 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1208 Tmp1 = LegalizeOp(Tmp1);
1209 LastCALLSEQ_END = DAG.getEntryNode();
1211 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1214 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1215 // Ensure that libcalls are emitted before a branch.
1216 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1217 Tmp1 = LegalizeOp(Tmp1);
1218 LastCALLSEQ_END = DAG.getEntryNode();
1220 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1221 default: assert(0 && "Indirect target must be legal type (pointer)!");
1223 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1226 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1229 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1230 // Ensure that libcalls are emitted before a return.
1231 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1232 Tmp1 = LegalizeOp(Tmp1);
1233 LastCALLSEQ_END = DAG.getEntryNode();
1235 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1236 case Expand: assert(0 && "It's impossible to expand bools");
1238 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1241 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1245 // Basic block destination (Op#2) is always legal.
1246 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1248 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1249 default: assert(0 && "This action is not supported yet!");
1250 case TargetLowering::Legal: break;
1251 case TargetLowering::Custom:
1252 Tmp1 = TLI.LowerOperation(Result, DAG);
1253 if (Tmp1.Val) Result = Tmp1;
1255 case TargetLowering::Expand:
1256 // Expand brcond's setcc into its constituent parts and create a BR_CC
1258 if (Tmp2.getOpcode() == ISD::SETCC) {
1259 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1260 Tmp2.getOperand(0), Tmp2.getOperand(1),
1261 Node->getOperand(2));
1263 // Make sure the condition is either zero or one. It may have been
1264 // promoted from something else.
1265 unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType());
1266 if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1))
1267 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1269 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1270 DAG.getCondCode(ISD::SETNE), Tmp2,
1271 DAG.getConstant(0, Tmp2.getValueType()),
1272 Node->getOperand(2));
1278 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1279 // Ensure that libcalls are emitted before a branch.
1280 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1281 Tmp1 = LegalizeOp(Tmp1);
1282 LastCALLSEQ_END = DAG.getEntryNode();
1284 Tmp2 = Node->getOperand(2); // LHS
1285 Tmp3 = Node->getOperand(3); // RHS
1286 Tmp4 = Node->getOperand(1); // CC
1288 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1290 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1291 // the LHS is a legal SETCC itself. In this case, we need to compare
1292 // the result against zero to select between true and false values.
1293 if (Tmp3.Val == 0) {
1294 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1295 Tmp4 = DAG.getCondCode(ISD::SETNE);
1298 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1299 Node->getOperand(4));
1301 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1302 default: assert(0 && "Unexpected action for BR_CC!");
1303 case TargetLowering::Legal: break;
1304 case TargetLowering::Custom:
1305 Tmp4 = TLI.LowerOperation(Result, DAG);
1306 if (Tmp4.Val) Result = Tmp4;
1311 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1312 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1314 MVT::ValueType VT = Node->getValueType(0);
1315 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1316 Tmp3 = Result.getValue(0);
1317 Tmp4 = Result.getValue(1);
1319 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1320 default: assert(0 && "This action is not supported yet!");
1321 case TargetLowering::Legal: break;
1322 case TargetLowering::Custom:
1323 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1325 Tmp3 = LegalizeOp(Tmp1);
1326 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1329 case TargetLowering::Promote: {
1330 // Only promote a load of vector type to another.
1331 assert(MVT::isVector(VT) && "Cannot promote this load!");
1332 // Change base type to a different vector type.
1333 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1335 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, Node->getOperand(2));
1336 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1337 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1341 // Since loads produce two values, make sure to remember that we
1342 // legalized both of them.
1343 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1344 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1345 return Op.ResNo ? Tmp4 : Tmp3;
1349 case ISD::ZEXTLOAD: {
1350 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1351 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1353 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
1354 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
1355 default: assert(0 && "This action is not supported yet!");
1356 case TargetLowering::Promote:
1357 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
1358 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1359 DAG.getValueType(MVT::i8));
1360 Tmp1 = Result.getValue(0);
1361 Tmp2 = Result.getValue(1);
1363 case TargetLowering::Custom:
1366 case TargetLowering::Legal:
1367 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1368 Node->getOperand(3));
1369 Tmp1 = Result.getValue(0);
1370 Tmp2 = Result.getValue(1);
1373 Tmp3 = TLI.LowerOperation(Tmp3, DAG);
1375 Tmp1 = LegalizeOp(Tmp3);
1376 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1380 case TargetLowering::Expand:
1381 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1382 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1383 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
1384 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1385 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1386 Tmp2 = LegalizeOp(Load.getValue(1));
1389 assert(Node->getOpcode() != ISD::EXTLOAD &&
1390 "EXTLOAD should always be supported!");
1391 // Turn the unsupported load into an EXTLOAD followed by an explicit
1392 // zero/sign extend inreg.
1393 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1394 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1396 if (Node->getOpcode() == ISD::SEXTLOAD)
1397 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1398 Result, DAG.getValueType(SrcVT));
1400 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1401 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1402 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1405 // Since loads produce two values, make sure to remember that we legalized
1407 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1408 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1409 return Op.ResNo ? Tmp2 : Tmp1;
1411 case ISD::EXTRACT_ELEMENT: {
1412 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1413 switch (getTypeAction(OpTy)) {
1414 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1416 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1418 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1419 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1420 TLI.getShiftAmountTy()));
1421 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1424 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1425 Node->getOperand(0));
1429 // Get both the low and high parts.
1430 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1431 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1432 Result = Tmp2; // 1 -> Hi
1434 Result = Tmp1; // 0 -> Lo
1440 case ISD::CopyToReg:
1441 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1443 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1444 "Register type must be legal!");
1445 // Legalize the incoming value (must be a legal type).
1446 Tmp2 = LegalizeOp(Node->getOperand(2));
1447 if (Node->getNumValues() == 1) {
1448 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1450 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1451 if (Node->getNumOperands() == 4) {
1452 Tmp3 = LegalizeOp(Node->getOperand(3));
1453 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1456 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1459 // Since this produces two values, make sure to remember that we legalized
1461 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1462 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1468 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1470 // Ensure that libcalls are emitted before a return.
1471 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1472 Tmp1 = LegalizeOp(Tmp1);
1473 LastCALLSEQ_END = DAG.getEntryNode();
1475 switch (Node->getNumOperands()) {
1477 Tmp2 = Node->getOperand(1);
1478 Tmp3 = Node->getOperand(2); // Signness
1479 switch (getTypeAction(Tmp2.getValueType())) {
1481 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1484 if (Tmp2.getValueType() != MVT::Vector) {
1486 ExpandOp(Tmp2, Lo, Hi);
1487 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1489 SDNode *InVal = Tmp2.Val;
1491 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1492 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1494 // Figure out if there is a Packed type corresponding to this Vector
1495 // type. If so, convert to the packed type.
1496 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1497 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1498 // Turn this into a return of the packed type.
1499 Tmp2 = PackVectorOp(Tmp2, TVT);
1500 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1501 } else if (NumElems == 1) {
1502 // Turn this into a return of the scalar type.
1503 Tmp2 = PackVectorOp(Tmp2, EVT);
1504 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1506 // FIXME: Returns of gcc generic vectors smaller than a legal type
1507 // should be returned in integer registers!
1509 // The scalarized value type may not be legal, e.g. it might require
1510 // promotion or expansion. Relegalize the return.
1511 Result = LegalizeOp(Result);
1513 // FIXME: Returns of gcc generic vectors larger than a legal vector
1514 // type should be returned by reference!
1516 SplitVectorOp(Tmp2, Lo, Hi);
1517 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1518 Result = LegalizeOp(Result);
1523 Tmp2 = PromoteOp(Node->getOperand(1));
1524 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1525 Result = LegalizeOp(Result);
1530 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1532 default: { // ret <values>
1533 std::vector<SDOperand> NewValues;
1534 NewValues.push_back(Tmp1);
1535 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1536 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1538 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1539 NewValues.push_back(Node->getOperand(i+1));
1543 assert(Node->getOperand(i).getValueType() != MVT::Vector &&
1544 "FIXME: TODO: implement returning non-legal vector types!");
1545 ExpandOp(Node->getOperand(i), Lo, Hi);
1546 NewValues.push_back(Lo);
1547 NewValues.push_back(Node->getOperand(i+1));
1548 NewValues.push_back(Hi);
1549 NewValues.push_back(Node->getOperand(i+1));
1553 assert(0 && "Can't promote multiple return value yet!");
1556 if (NewValues.size() == Node->getNumOperands())
1557 Result = DAG.UpdateNodeOperands(Result, NewValues);
1559 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
1564 if (Result.getOpcode() == ISD::RET) {
1565 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1566 default: assert(0 && "This action is not supported yet!");
1567 case TargetLowering::Legal: break;
1568 case TargetLowering::Custom:
1569 Tmp1 = TLI.LowerOperation(Result, DAG);
1570 if (Tmp1.Val) Result = Tmp1;
1576 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1577 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1579 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1580 // FIXME: We shouldn't do this for TargetConstantFP's.
1581 // FIXME: move this to the DAG Combiner!
1582 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1583 if (CFP->getValueType(0) == MVT::f32) {
1584 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1586 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1587 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1589 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1590 Node->getOperand(3));
1594 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1596 Tmp3 = LegalizeOp(Node->getOperand(1));
1597 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1598 Node->getOperand(3));
1600 MVT::ValueType VT = Tmp3.getValueType();
1601 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1602 default: assert(0 && "This action is not supported yet!");
1603 case TargetLowering::Legal: break;
1604 case TargetLowering::Custom:
1605 Tmp1 = TLI.LowerOperation(Result, DAG);
1606 if (Tmp1.Val) Result = Tmp1;
1608 case TargetLowering::Promote:
1609 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1610 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1611 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1612 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1613 Node->getOperand(3));
1619 // Truncate the value and store the result.
1620 Tmp3 = PromoteOp(Node->getOperand(1));
1621 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1622 Node->getOperand(3),
1623 DAG.getValueType(Node->getOperand(1).getValueType()));
1627 unsigned IncrementSize = 0;
1630 // If this is a vector type, then we have to calculate the increment as
1631 // the product of the element size in bytes, and the number of elements
1632 // in the high half of the vector.
1633 if (Node->getOperand(1).getValueType() == MVT::Vector) {
1634 SDNode *InVal = Node->getOperand(1).Val;
1636 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1637 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1639 // Figure out if there is a Packed type corresponding to this Vector
1640 // type. If so, convert to the packed type.
1641 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1642 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1643 // Turn this into a normal store of the packed type.
1644 Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1645 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1646 Node->getOperand(3));
1647 Result = LegalizeOp(Result);
1649 } else if (NumElems == 1) {
1650 // Turn this into a normal store of the scalar type.
1651 Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1652 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1653 Node->getOperand(3));
1654 // The scalarized value type may not be legal, e.g. it might require
1655 // promotion or expansion. Relegalize the scalar store.
1656 Result = LegalizeOp(Result);
1659 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1660 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1663 ExpandOp(Node->getOperand(1), Lo, Hi);
1664 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1666 if (!TLI.isLittleEndian())
1670 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1671 Node->getOperand(3));
1672 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1673 getIntPtrConstant(IncrementSize));
1674 assert(isTypeLegal(Tmp2.getValueType()) &&
1675 "Pointers must be legal!");
1676 // FIXME: This sets the srcvalue of both halves to be the same, which is
1678 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1679 Node->getOperand(3));
1680 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1686 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1687 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1689 case ISD::STACKSAVE:
1690 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1691 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1692 Tmp1 = Result.getValue(0);
1693 Tmp2 = Result.getValue(1);
1695 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1696 default: assert(0 && "This action is not supported yet!");
1697 case TargetLowering::Legal: break;
1698 case TargetLowering::Custom:
1699 Tmp3 = TLI.LowerOperation(Result, DAG);
1701 Tmp1 = LegalizeOp(Tmp3);
1702 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1705 case TargetLowering::Expand:
1706 // Expand to CopyFromReg if the target set
1707 // StackPointerRegisterToSaveRestore.
1708 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1709 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1710 Node->getValueType(0));
1711 Tmp2 = Tmp1.getValue(1);
1713 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1714 Tmp2 = Node->getOperand(0);
1719 // Since stacksave produce two values, make sure to remember that we
1720 // legalized both of them.
1721 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1722 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1723 return Op.ResNo ? Tmp2 : Tmp1;
1725 case ISD::STACKRESTORE:
1726 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1727 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1728 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1730 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1731 default: assert(0 && "This action is not supported yet!");
1732 case TargetLowering::Legal: break;
1733 case TargetLowering::Custom:
1734 Tmp1 = TLI.LowerOperation(Result, DAG);
1735 if (Tmp1.Val) Result = Tmp1;
1737 case TargetLowering::Expand:
1738 // Expand to CopyToReg if the target set
1739 // StackPointerRegisterToSaveRestore.
1740 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1741 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1749 case ISD::READCYCLECOUNTER:
1750 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1751 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1753 // Since rdcc produce two values, make sure to remember that we legalized
1755 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1756 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1759 case ISD::TRUNCSTORE: {
1760 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1761 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1763 assert(isTypeLegal(Node->getOperand(1).getValueType()) &&
1764 "Cannot handle illegal TRUNCSTORE yet!");
1765 Tmp2 = LegalizeOp(Node->getOperand(1));
1767 // The only promote case we handle is TRUNCSTORE:i1 X into
1768 // -> TRUNCSTORE:i8 (and X, 1)
1769 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1770 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1771 TargetLowering::Promote) {
1772 // Promote the bool to a mask then store.
1773 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1774 DAG.getConstant(1, Tmp2.getValueType()));
1775 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1776 Node->getOperand(3), DAG.getValueType(MVT::i8));
1778 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1779 Tmp3 != Node->getOperand(2)) {
1780 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
1781 Node->getOperand(3), Node->getOperand(4));
1784 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT();
1785 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) {
1786 default: assert(0 && "This action is not supported yet!");
1787 case TargetLowering::Legal: break;
1788 case TargetLowering::Custom:
1789 Tmp1 = TLI.LowerOperation(Result, DAG);
1790 if (Tmp1.Val) Result = Tmp1;
1796 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1797 case Expand: assert(0 && "It's impossible to expand bools");
1799 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1802 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1805 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1806 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1808 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1810 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1811 default: assert(0 && "This action is not supported yet!");
1812 case TargetLowering::Legal: break;
1813 case TargetLowering::Custom: {
1814 Tmp1 = TLI.LowerOperation(Result, DAG);
1815 if (Tmp1.Val) Result = Tmp1;
1818 case TargetLowering::Expand:
1819 if (Tmp1.getOpcode() == ISD::SETCC) {
1820 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1822 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1824 // Make sure the condition is either zero or one. It may have been
1825 // promoted from something else.
1826 unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType());
1827 if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1))
1828 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1829 Result = DAG.getSelectCC(Tmp1,
1830 DAG.getConstant(0, Tmp1.getValueType()),
1831 Tmp2, Tmp3, ISD::SETNE);
1834 case TargetLowering::Promote: {
1835 MVT::ValueType NVT =
1836 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1837 unsigned ExtOp, TruncOp;
1838 if (MVT::isVector(Tmp2.getValueType())) {
1839 ExtOp = ISD::BIT_CONVERT;
1840 TruncOp = ISD::BIT_CONVERT;
1841 } else if (MVT::isInteger(Tmp2.getValueType())) {
1842 ExtOp = ISD::ANY_EXTEND;
1843 TruncOp = ISD::TRUNCATE;
1845 ExtOp = ISD::FP_EXTEND;
1846 TruncOp = ISD::FP_ROUND;
1848 // Promote each of the values to the new type.
1849 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1850 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1851 // Perform the larger operation, then round down.
1852 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1853 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1858 case ISD::SELECT_CC: {
1859 Tmp1 = Node->getOperand(0); // LHS
1860 Tmp2 = Node->getOperand(1); // RHS
1861 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1862 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1863 SDOperand CC = Node->getOperand(4);
1865 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
1867 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1868 // the LHS is a legal SETCC itself. In this case, we need to compare
1869 // the result against zero to select between true and false values.
1870 if (Tmp2.Val == 0) {
1871 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1872 CC = DAG.getCondCode(ISD::SETNE);
1874 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
1876 // Everything is legal, see if we should expand this op or something.
1877 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
1878 default: assert(0 && "This action is not supported yet!");
1879 case TargetLowering::Legal: break;
1880 case TargetLowering::Custom:
1881 Tmp1 = TLI.LowerOperation(Result, DAG);
1882 if (Tmp1.Val) Result = Tmp1;
1888 Tmp1 = Node->getOperand(0);
1889 Tmp2 = Node->getOperand(1);
1890 Tmp3 = Node->getOperand(2);
1891 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
1893 // If we had to Expand the SetCC operands into a SELECT node, then it may
1894 // not always be possible to return a true LHS & RHS. In this case, just
1895 // return the value we legalized, returned in the LHS
1896 if (Tmp2.Val == 0) {
1901 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
1902 default: assert(0 && "Cannot handle this action for SETCC yet!");
1903 case TargetLowering::Custom:
1906 case TargetLowering::Legal:
1907 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1909 Tmp3 = TLI.LowerOperation(Result, DAG);
1910 if (Tmp3.Val) Result = Tmp3;
1913 case TargetLowering::Promote: {
1914 // First step, figure out the appropriate operation to use.
1915 // Allow SETCC to not be supported for all legal data types
1916 // Mostly this targets FP
1917 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1918 MVT::ValueType OldVT = NewInTy;
1920 // Scan for the appropriate larger type to use.
1922 NewInTy = (MVT::ValueType)(NewInTy+1);
1924 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1925 "Fell off of the edge of the integer world");
1926 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1927 "Fell off of the edge of the floating point world");
1929 // If the target supports SETCC of this type, use it.
1930 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
1933 if (MVT::isInteger(NewInTy))
1934 assert(0 && "Cannot promote Legal Integer SETCC yet");
1936 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1937 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
1939 Tmp1 = LegalizeOp(Tmp1);
1940 Tmp2 = LegalizeOp(Tmp2);
1941 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1942 Result = LegalizeOp(Result);
1945 case TargetLowering::Expand:
1946 // Expand a setcc node into a select_cc of the same condition, lhs, and
1947 // rhs that selects between const 1 (true) and const 0 (false).
1948 MVT::ValueType VT = Node->getValueType(0);
1949 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1950 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1951 Node->getOperand(2));
1957 case ISD::MEMMOVE: {
1958 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1959 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1961 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1962 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1963 case Expand: assert(0 && "Cannot expand a byte!");
1965 Tmp3 = LegalizeOp(Node->getOperand(2));
1968 Tmp3 = PromoteOp(Node->getOperand(2));
1972 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1976 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1978 // Length is too big, just take the lo-part of the length.
1980 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
1984 Tmp4 = LegalizeOp(Node->getOperand(3));
1987 Tmp4 = PromoteOp(Node->getOperand(3));
1992 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
1993 case Expand: assert(0 && "Cannot expand this yet!");
1995 Tmp5 = LegalizeOp(Node->getOperand(4));
1998 Tmp5 = PromoteOp(Node->getOperand(4));
2002 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2003 default: assert(0 && "This action not implemented for this operation!");
2004 case TargetLowering::Custom:
2007 case TargetLowering::Legal:
2008 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2010 Tmp1 = TLI.LowerOperation(Result, DAG);
2011 if (Tmp1.Val) Result = Tmp1;
2014 case TargetLowering::Expand: {
2015 // Otherwise, the target does not support this operation. Lower the
2016 // operation to an explicit libcall as appropriate.
2017 MVT::ValueType IntPtr = TLI.getPointerTy();
2018 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2019 std::vector<std::pair<SDOperand, const Type*> > Args;
2021 const char *FnName = 0;
2022 if (Node->getOpcode() == ISD::MEMSET) {
2023 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2024 // Extend the (previously legalized) ubyte argument to be an int value
2026 if (Tmp3.getValueType() > MVT::i32)
2027 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2029 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2030 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
2031 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2034 } else if (Node->getOpcode() == ISD::MEMCPY ||
2035 Node->getOpcode() == ISD::MEMMOVE) {
2036 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2037 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
2038 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2039 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2041 assert(0 && "Unknown op!");
2044 std::pair<SDOperand,SDOperand> CallResult =
2045 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
2046 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2047 Result = CallResult.second;
2054 case ISD::SHL_PARTS:
2055 case ISD::SRA_PARTS:
2056 case ISD::SRL_PARTS: {
2057 std::vector<SDOperand> Ops;
2058 bool Changed = false;
2059 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2060 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2061 Changed |= Ops.back() != Node->getOperand(i);
2064 Result = DAG.UpdateNodeOperands(Result, Ops);
2066 switch (TLI.getOperationAction(Node->getOpcode(),
2067 Node->getValueType(0))) {
2068 default: assert(0 && "This action is not supported yet!");
2069 case TargetLowering::Legal: break;
2070 case TargetLowering::Custom:
2071 Tmp1 = TLI.LowerOperation(Result, DAG);
2073 SDOperand Tmp2, RetVal(0, 0);
2074 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2075 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2076 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2080 assert(RetVal.Val && "Illegal result number");
2086 // Since these produce multiple values, make sure to remember that we
2087 // legalized all of them.
2088 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2089 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2090 return Result.getValue(Op.ResNo);
2111 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2112 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2113 case Expand: assert(0 && "Not possible");
2115 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2118 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2122 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2124 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2125 default: assert(0 && "BinOp legalize operation not supported");
2126 case TargetLowering::Legal: break;
2127 case TargetLowering::Custom:
2128 Tmp1 = TLI.LowerOperation(Result, DAG);
2129 if (Tmp1.Val) Result = Tmp1;
2131 case TargetLowering::Expand: {
2132 assert(MVT::isVector(Node->getValueType(0)) &&
2133 "Cannot expand this binary operator!");
2134 // Expand the operation into a bunch of nasty scalar code.
2135 std::vector<SDOperand> Ops;
2136 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
2137 MVT::ValueType PtrVT = TLI.getPointerTy();
2138 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2140 SDOperand Idx = DAG.getConstant(i, PtrVT);
2141 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2142 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2143 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2145 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), Ops);
2148 case TargetLowering::Promote: {
2149 switch (Node->getOpcode()) {
2150 default: assert(0 && "Do not know how to promote this BinOp!");
2154 MVT::ValueType OVT = Node->getValueType(0);
2155 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2156 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2157 // Bit convert each of the values to the new type.
2158 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2159 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2160 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2161 // Bit convert the result back the original type.
2162 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2170 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2171 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2172 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2173 case Expand: assert(0 && "Not possible");
2175 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2178 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2182 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2184 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2185 default: assert(0 && "Operation not supported");
2186 case TargetLowering::Custom:
2187 Tmp1 = TLI.LowerOperation(Result, DAG);
2188 if (Tmp1.Val) Result = Tmp1;
2190 case TargetLowering::Legal: break;
2191 case TargetLowering::Expand:
2192 // If this target supports fabs/fneg natively, do this efficiently.
2193 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
2194 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
2195 // Get the sign bit of the RHS.
2196 MVT::ValueType IVT =
2197 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2198 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2199 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2200 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2201 // Get the absolute value of the result.
2202 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2203 // Select between the nabs and abs value based on the sign bit of
2205 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2206 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2209 Result = LegalizeOp(Result);
2213 // Otherwise, do bitwise ops!
2215 // copysign -> copysignf/copysign libcall.
2217 if (Node->getValueType(0) == MVT::f32) {
2218 FnName = "copysignf";
2219 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type.
2220 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2221 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2));
2223 FnName = "copysign";
2224 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type.
2225 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2226 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2));
2229 Result = ExpandLibCall(FnName, Node, Dummy);
2236 Tmp1 = LegalizeOp(Node->getOperand(0));
2237 Tmp2 = LegalizeOp(Node->getOperand(1));
2238 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2239 // Since this produces two values, make sure to remember that we legalized
2241 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2242 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2247 Tmp1 = LegalizeOp(Node->getOperand(0));
2248 Tmp2 = LegalizeOp(Node->getOperand(1));
2249 Tmp3 = LegalizeOp(Node->getOperand(2));
2250 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2251 // Since this produces two values, make sure to remember that we legalized
2253 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2254 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2257 case ISD::BUILD_PAIR: {
2258 MVT::ValueType PairTy = Node->getValueType(0);
2259 // TODO: handle the case where the Lo and Hi operands are not of legal type
2260 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2261 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2262 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2263 case TargetLowering::Promote:
2264 case TargetLowering::Custom:
2265 assert(0 && "Cannot promote/custom this yet!");
2266 case TargetLowering::Legal:
2267 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2268 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2270 case TargetLowering::Expand:
2271 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2272 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2273 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2274 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2275 TLI.getShiftAmountTy()));
2276 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2285 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2286 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2288 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2289 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2290 case TargetLowering::Custom:
2293 case TargetLowering::Legal:
2294 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2296 Tmp1 = TLI.LowerOperation(Result, DAG);
2297 if (Tmp1.Val) Result = Tmp1;
2300 case TargetLowering::Expand:
2301 if (MVT::isInteger(Node->getValueType(0))) {
2303 MVT::ValueType VT = Node->getValueType(0);
2304 unsigned Opc = Node->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
2305 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
2306 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2307 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2309 // Floating point mod -> fmod libcall.
2310 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
2312 Result = ExpandLibCall(FnName, Node, Dummy);
2318 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2319 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2321 MVT::ValueType VT = Node->getValueType(0);
2322 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2323 default: assert(0 && "This action is not supported yet!");
2324 case TargetLowering::Custom:
2327 case TargetLowering::Legal:
2328 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2329 Result = Result.getValue(0);
2330 Tmp1 = Result.getValue(1);
2333 Tmp2 = TLI.LowerOperation(Result, DAG);
2335 Result = LegalizeOp(Tmp2);
2336 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2340 case TargetLowering::Expand: {
2341 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2342 Node->getOperand(2));
2343 // Increment the pointer, VAList, to the next vaarg
2344 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2345 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2346 TLI.getPointerTy()));
2347 // Store the incremented VAList to the legalized pointer
2348 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2,
2349 Node->getOperand(2));
2350 // Load the actual argument out of the pointer VAList
2351 Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0));
2352 Tmp1 = LegalizeOp(Result.getValue(1));
2353 Result = LegalizeOp(Result);
2357 // Since VAARG produces two values, make sure to remember that we
2358 // legalized both of them.
2359 AddLegalizedOperand(SDOperand(Node, 0), Result);
2360 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2361 return Op.ResNo ? Tmp1 : Result;
2365 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2366 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2367 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2369 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2370 default: assert(0 && "This action is not supported yet!");
2371 case TargetLowering::Custom:
2374 case TargetLowering::Legal:
2375 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2376 Node->getOperand(3), Node->getOperand(4));
2378 Tmp1 = TLI.LowerOperation(Result, DAG);
2379 if (Tmp1.Val) Result = Tmp1;
2382 case TargetLowering::Expand:
2383 // This defaults to loading a pointer from the input and storing it to the
2384 // output, returning the chain.
2385 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, Node->getOperand(3));
2386 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp4.getValue(1), Tmp4, Tmp2,
2387 Node->getOperand(4));
2393 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2394 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2396 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2397 default: assert(0 && "This action is not supported yet!");
2398 case TargetLowering::Custom:
2401 case TargetLowering::Legal:
2402 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2404 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2405 if (Tmp1.Val) Result = Tmp1;
2408 case TargetLowering::Expand:
2409 Result = Tmp1; // Default to a no-op, return the chain
2415 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2416 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2418 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2420 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2421 default: assert(0 && "This action is not supported yet!");
2422 case TargetLowering::Legal: break;
2423 case TargetLowering::Custom:
2424 Tmp1 = TLI.LowerOperation(Result, DAG);
2425 if (Tmp1.Val) Result = Tmp1;
2432 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2433 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2435 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2436 "Cannot handle this yet!");
2437 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2441 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2442 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2443 case TargetLowering::Custom:
2444 assert(0 && "Cannot custom legalize this yet!");
2445 case TargetLowering::Legal:
2446 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2448 case TargetLowering::Promote: {
2449 MVT::ValueType OVT = Tmp1.getValueType();
2450 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2451 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2453 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2454 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2455 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2456 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2459 case TargetLowering::Expand:
2460 Result = ExpandBSWAP(Tmp1);
2468 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2469 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2470 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2471 case TargetLowering::Legal:
2472 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2474 case TargetLowering::Promote: {
2475 MVT::ValueType OVT = Tmp1.getValueType();
2476 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2478 // Zero extend the argument.
2479 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2480 // Perform the larger operation, then subtract if needed.
2481 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2482 switch (Node->getOpcode()) {
2487 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2488 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2489 DAG.getConstant(getSizeInBits(NVT), NVT),
2491 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2492 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2495 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2496 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2497 DAG.getConstant(getSizeInBits(NVT) -
2498 getSizeInBits(OVT), NVT));
2503 case TargetLowering::Expand:
2504 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2515 Tmp1 = LegalizeOp(Node->getOperand(0));
2516 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2517 case TargetLowering::Promote:
2518 case TargetLowering::Custom:
2521 case TargetLowering::Legal:
2522 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2524 Tmp1 = TLI.LowerOperation(Result, DAG);
2525 if (Tmp1.Val) Result = Tmp1;
2528 case TargetLowering::Expand:
2529 switch (Node->getOpcode()) {
2530 default: assert(0 && "Unreachable!");
2532 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2533 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2534 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2537 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2538 MVT::ValueType VT = Node->getValueType(0);
2539 Tmp2 = DAG.getConstantFP(0.0, VT);
2540 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2541 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2542 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2548 MVT::ValueType VT = Node->getValueType(0);
2549 const char *FnName = 0;
2550 switch(Node->getOpcode()) {
2551 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2552 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2553 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2554 default: assert(0 && "Unreachable!");
2557 Result = ExpandLibCall(FnName, Node, Dummy);
2565 case ISD::BIT_CONVERT:
2566 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2567 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2569 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2570 Node->getOperand(0).getValueType())) {
2571 default: assert(0 && "Unknown operation action!");
2572 case TargetLowering::Expand:
2573 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2575 case TargetLowering::Legal:
2576 Tmp1 = LegalizeOp(Node->getOperand(0));
2577 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2582 case ISD::VBIT_CONVERT: {
2583 assert(Op.getOperand(0).getValueType() == MVT::Vector &&
2584 "Can only have VBIT_CONVERT where input or output is MVT::Vector!");
2586 // The input has to be a vector type, we have to either scalarize it, pack
2587 // it, or convert it based on whether the input vector type is legal.
2588 SDNode *InVal = Node->getOperand(0).Val;
2590 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
2591 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
2593 // Figure out if there is a Packed type corresponding to this Vector
2594 // type. If so, convert to the packed type.
2595 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2596 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
2597 // Turn this into a bit convert of the packed input.
2598 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2599 PackVectorOp(Node->getOperand(0), TVT));
2601 } else if (NumElems == 1) {
2602 // Turn this into a bit convert of the scalar input.
2603 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2604 PackVectorOp(Node->getOperand(0), EVT));
2607 // FIXME: UNIMP! Store then reload
2608 assert(0 && "Cast from unsupported vector type not implemented yet!");
2612 // Conversion operators. The source and destination have different types.
2613 case ISD::SINT_TO_FP:
2614 case ISD::UINT_TO_FP: {
2615 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2616 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2618 switch (TLI.getOperationAction(Node->getOpcode(),
2619 Node->getOperand(0).getValueType())) {
2620 default: assert(0 && "Unknown operation action!");
2621 case TargetLowering::Custom:
2624 case TargetLowering::Legal:
2625 Tmp1 = LegalizeOp(Node->getOperand(0));
2626 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2628 Tmp1 = TLI.LowerOperation(Result, DAG);
2629 if (Tmp1.Val) Result = Tmp1;
2632 case TargetLowering::Expand:
2633 Result = ExpandLegalINT_TO_FP(isSigned,
2634 LegalizeOp(Node->getOperand(0)),
2635 Node->getValueType(0));
2637 case TargetLowering::Promote:
2638 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2639 Node->getValueType(0),
2645 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2646 Node->getValueType(0), Node->getOperand(0));
2649 Tmp1 = PromoteOp(Node->getOperand(0));
2651 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2652 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2654 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2655 Node->getOperand(0).getValueType());
2657 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2658 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2664 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2666 Tmp1 = LegalizeOp(Node->getOperand(0));
2667 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2670 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2672 // Since the result is legal, we should just be able to truncate the low
2673 // part of the source.
2674 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2677 Result = PromoteOp(Node->getOperand(0));
2678 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2683 case ISD::FP_TO_SINT:
2684 case ISD::FP_TO_UINT:
2685 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2687 Tmp1 = LegalizeOp(Node->getOperand(0));
2689 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2690 default: assert(0 && "Unknown operation action!");
2691 case TargetLowering::Custom:
2694 case TargetLowering::Legal:
2695 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2697 Tmp1 = TLI.LowerOperation(Result, DAG);
2698 if (Tmp1.Val) Result = Tmp1;
2701 case TargetLowering::Promote:
2702 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2703 Node->getOpcode() == ISD::FP_TO_SINT);
2705 case TargetLowering::Expand:
2706 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2707 SDOperand True, False;
2708 MVT::ValueType VT = Node->getOperand(0).getValueType();
2709 MVT::ValueType NVT = Node->getValueType(0);
2710 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2711 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2712 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2713 Node->getOperand(0), Tmp2, ISD::SETLT);
2714 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2715 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2716 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2718 False = DAG.getNode(ISD::XOR, NVT, False,
2719 DAG.getConstant(1ULL << ShiftAmt, NVT));
2720 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2723 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2729 assert(0 && "Shouldn't need to expand other operators here!");
2731 Tmp1 = PromoteOp(Node->getOperand(0));
2732 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
2733 Result = LegalizeOp(Result);
2738 case ISD::ANY_EXTEND:
2739 case ISD::ZERO_EXTEND:
2740 case ISD::SIGN_EXTEND:
2741 case ISD::FP_EXTEND:
2743 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2744 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
2746 Tmp1 = LegalizeOp(Node->getOperand(0));
2747 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2750 switch (Node->getOpcode()) {
2751 case ISD::ANY_EXTEND:
2752 Tmp1 = PromoteOp(Node->getOperand(0));
2753 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
2755 case ISD::ZERO_EXTEND:
2756 Result = PromoteOp(Node->getOperand(0));
2757 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2758 Result = DAG.getZeroExtendInReg(Result,
2759 Node->getOperand(0).getValueType());
2761 case ISD::SIGN_EXTEND:
2762 Result = PromoteOp(Node->getOperand(0));
2763 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2764 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2766 DAG.getValueType(Node->getOperand(0).getValueType()));
2768 case ISD::FP_EXTEND:
2769 Result = PromoteOp(Node->getOperand(0));
2770 if (Result.getValueType() != Op.getValueType())
2771 // Dynamically dead while we have only 2 FP types.
2772 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2775 Result = PromoteOp(Node->getOperand(0));
2776 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2781 case ISD::FP_ROUND_INREG:
2782 case ISD::SIGN_EXTEND_INREG: {
2783 Tmp1 = LegalizeOp(Node->getOperand(0));
2784 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2786 // If this operation is not supported, convert it to a shl/shr or load/store
2788 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2789 default: assert(0 && "This action not supported for this op yet!");
2790 case TargetLowering::Legal:
2791 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2793 case TargetLowering::Expand:
2794 // If this is an integer extend and shifts are supported, do that.
2795 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2796 // NOTE: we could fall back on load/store here too for targets without
2797 // SAR. However, it is doubtful that any exist.
2798 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2799 MVT::getSizeInBits(ExtraVT);
2800 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2801 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2802 Node->getOperand(0), ShiftCst);
2803 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2805 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2806 // The only way we can lower this is to turn it into a STORETRUNC,
2807 // EXTLOAD pair, targetting a temporary location (a stack slot).
2809 // NOTE: there is a choice here between constantly creating new stack
2810 // slots and always reusing the same one. We currently always create
2811 // new ones, as reuse may inhibit scheduling.
2812 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2813 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty);
2814 unsigned Align = TLI.getTargetData()->getTypeAlignment(Ty);
2815 MachineFunction &MF = DAG.getMachineFunction();
2817 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2818 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2819 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2820 Node->getOperand(0), StackSlot,
2821 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2822 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2823 Result, StackSlot, DAG.getSrcValue(NULL),
2826 assert(0 && "Unknown op");
2834 assert(Result.getValueType() == Op.getValueType() &&
2835 "Bad legalization!");
2837 // Make sure that the generated code is itself legal.
2839 Result = LegalizeOp(Result);
2841 // Note that LegalizeOp may be reentered even from single-use nodes, which
2842 // means that we always must cache transformed nodes.
2843 AddLegalizedOperand(Op, Result);
2847 /// PromoteOp - Given an operation that produces a value in an invalid type,
2848 /// promote it to compute the value into a larger type. The produced value will
2849 /// have the correct bits for the low portion of the register, but no guarantee
2850 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2851 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2852 MVT::ValueType VT = Op.getValueType();
2853 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2854 assert(getTypeAction(VT) == Promote &&
2855 "Caller should expand or legalize operands that are not promotable!");
2856 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2857 "Cannot promote to smaller type!");
2859 SDOperand Tmp1, Tmp2, Tmp3;
2861 SDNode *Node = Op.Val;
2863 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2864 if (I != PromotedNodes.end()) return I->second;
2866 switch (Node->getOpcode()) {
2867 case ISD::CopyFromReg:
2868 assert(0 && "CopyFromReg must be legal!");
2871 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2873 assert(0 && "Do not know how to promote this operator!");
2876 Result = DAG.getNode(ISD::UNDEF, NVT);
2880 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2882 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2883 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2885 case ISD::ConstantFP:
2886 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2887 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2891 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2892 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2893 Node->getOperand(1), Node->getOperand(2));
2897 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2899 Result = LegalizeOp(Node->getOperand(0));
2900 assert(Result.getValueType() >= NVT &&
2901 "This truncation doesn't make sense!");
2902 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2903 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2906 // The truncation is not required, because we don't guarantee anything
2907 // about high bits anyway.
2908 Result = PromoteOp(Node->getOperand(0));
2911 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2912 // Truncate the low part of the expanded value to the result type
2913 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2916 case ISD::SIGN_EXTEND:
2917 case ISD::ZERO_EXTEND:
2918 case ISD::ANY_EXTEND:
2919 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2920 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2922 // Input is legal? Just do extend all the way to the larger type.
2923 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2926 // Promote the reg if it's smaller.
2927 Result = PromoteOp(Node->getOperand(0));
2928 // The high bits are not guaranteed to be anything. Insert an extend.
2929 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2930 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2931 DAG.getValueType(Node->getOperand(0).getValueType()));
2932 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2933 Result = DAG.getZeroExtendInReg(Result,
2934 Node->getOperand(0).getValueType());
2938 case ISD::BIT_CONVERT:
2939 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2940 Result = PromoteOp(Result);
2943 case ISD::FP_EXTEND:
2944 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2946 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2947 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2948 case Promote: assert(0 && "Unreachable with 2 FP types!");
2950 // Input is legal? Do an FP_ROUND_INREG.
2951 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
2952 DAG.getValueType(VT));
2957 case ISD::SINT_TO_FP:
2958 case ISD::UINT_TO_FP:
2959 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2961 // No extra round required here.
2962 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2966 Result = PromoteOp(Node->getOperand(0));
2967 if (Node->getOpcode() == ISD::SINT_TO_FP)
2968 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2970 DAG.getValueType(Node->getOperand(0).getValueType()));
2972 Result = DAG.getZeroExtendInReg(Result,
2973 Node->getOperand(0).getValueType());
2974 // No extra round required here.
2975 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2978 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
2979 Node->getOperand(0));
2980 // Round if we cannot tolerate excess precision.
2981 if (NoExcessFPPrecision)
2982 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2983 DAG.getValueType(VT));
2988 case ISD::SIGN_EXTEND_INREG:
2989 Result = PromoteOp(Node->getOperand(0));
2990 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2991 Node->getOperand(1));
2993 case ISD::FP_TO_SINT:
2994 case ISD::FP_TO_UINT:
2995 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2997 Tmp1 = Node->getOperand(0);
3000 // The input result is prerounded, so we don't have to do anything
3002 Tmp1 = PromoteOp(Node->getOperand(0));
3005 assert(0 && "not implemented");
3007 // If we're promoting a UINT to a larger size, check to see if the new node
3008 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3009 // we can use that instead. This allows us to generate better code for
3010 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3011 // legal, such as PowerPC.
3012 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3013 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3014 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3015 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3016 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3018 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3024 Tmp1 = PromoteOp(Node->getOperand(0));
3025 assert(Tmp1.getValueType() == NVT);
3026 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3027 // NOTE: we do not have to do any extra rounding here for
3028 // NoExcessFPPrecision, because we know the input will have the appropriate
3029 // precision, and these operations don't modify precision at all.
3035 Tmp1 = PromoteOp(Node->getOperand(0));
3036 assert(Tmp1.getValueType() == NVT);
3037 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3038 if (NoExcessFPPrecision)
3039 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3040 DAG.getValueType(VT));
3049 // The input may have strange things in the top bits of the registers, but
3050 // these operations don't care. They may have weird bits going out, but
3051 // that too is okay if they are integer operations.
3052 Tmp1 = PromoteOp(Node->getOperand(0));
3053 Tmp2 = PromoteOp(Node->getOperand(1));
3054 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3055 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3060 Tmp1 = PromoteOp(Node->getOperand(0));
3061 Tmp2 = PromoteOp(Node->getOperand(1));
3062 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3063 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3065 // Floating point operations will give excess precision that we may not be
3066 // able to tolerate. If we DO allow excess precision, just leave it,
3067 // otherwise excise it.
3068 // FIXME: Why would we need to round FP ops more than integer ones?
3069 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3070 if (NoExcessFPPrecision)
3071 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3072 DAG.getValueType(VT));
3077 // These operators require that their input be sign extended.
3078 Tmp1 = PromoteOp(Node->getOperand(0));
3079 Tmp2 = PromoteOp(Node->getOperand(1));
3080 if (MVT::isInteger(NVT)) {
3081 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3082 DAG.getValueType(VT));
3083 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3084 DAG.getValueType(VT));
3086 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3088 // Perform FP_ROUND: this is probably overly pessimistic.
3089 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3090 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3091 DAG.getValueType(VT));
3095 case ISD::FCOPYSIGN:
3096 // These operators require that their input be fp extended.
3097 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3099 Tmp1 = LegalizeOp(Node->getOperand(0));
3102 Tmp1 = PromoteOp(Node->getOperand(0));
3105 assert(0 && "not implemented");
3107 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3109 Tmp2 = LegalizeOp(Node->getOperand(1));
3112 Tmp2 = PromoteOp(Node->getOperand(1));
3115 assert(0 && "not implemented");
3117 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3119 // Perform FP_ROUND: this is probably overly pessimistic.
3120 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3121 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3122 DAG.getValueType(VT));
3127 // These operators require that their input be zero extended.
3128 Tmp1 = PromoteOp(Node->getOperand(0));
3129 Tmp2 = PromoteOp(Node->getOperand(1));
3130 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3131 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3132 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3133 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3137 Tmp1 = PromoteOp(Node->getOperand(0));
3138 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3141 // The input value must be properly sign extended.
3142 Tmp1 = PromoteOp(Node->getOperand(0));
3143 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3144 DAG.getValueType(VT));
3145 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3148 // The input value must be properly zero extended.
3149 Tmp1 = PromoteOp(Node->getOperand(0));
3150 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3151 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3155 Tmp1 = Node->getOperand(0); // Get the chain.
3156 Tmp2 = Node->getOperand(1); // Get the pointer.
3157 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3158 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3159 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3161 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3162 Node->getOperand(2));
3163 // Increment the pointer, VAList, to the next vaarg
3164 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3165 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3166 TLI.getPointerTy()));
3167 // Store the incremented VAList to the legalized pointer
3168 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2,
3169 Node->getOperand(2));
3170 // Load the actual argument out of the pointer VAList
3171 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList,
3172 DAG.getSrcValue(0), VT);
3174 // Remember that we legalized the chain.
3175 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3179 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Node->getOperand(0),
3180 Node->getOperand(1), Node->getOperand(2), VT);
3181 // Remember that we legalized the chain.
3182 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3187 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Node->getOperand(0),
3188 Node->getOperand(1), Node->getOperand(2),
3189 cast<VTSDNode>(Node->getOperand(3))->getVT());
3190 // Remember that we legalized the chain.
3191 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3194 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3195 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3196 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3198 case ISD::SELECT_CC:
3199 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3200 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3201 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3202 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3205 Tmp1 = Node->getOperand(0);
3206 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3207 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3208 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3209 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
3210 TLI.getShiftAmountTy()));
3215 // Zero extend the argument
3216 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3217 // Perform the larger operation, then subtract if needed.
3218 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3219 switch(Node->getOpcode()) {
3224 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3225 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3226 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
3227 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3228 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
3231 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3232 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3233 DAG.getConstant(getSizeInBits(NVT) -
3234 getSizeInBits(VT), NVT));
3238 case ISD::VEXTRACT_VECTOR_ELT:
3239 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
3241 case ISD::EXTRACT_VECTOR_ELT:
3242 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3246 assert(Result.Val && "Didn't set a result!");
3248 // Make sure the result is itself legal.
3249 Result = LegalizeOp(Result);
3251 // Remember that we promoted this!
3252 AddPromotedOperand(Op, Result);
3256 /// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
3257 /// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
3258 /// on the vector type. The return type of this matches the element type of the
3259 /// vector, which may not be legal for the target.
3260 SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
3261 // We know that operand #0 is the Vec vector. If the index is a constant
3262 // or if the invec is a supported hardware type, we can use it. Otherwise,
3263 // lower to a store then an indexed load.
3264 SDOperand Vec = Op.getOperand(0);
3265 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3267 SDNode *InVal = Vec.Val;
3268 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
3269 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
3271 // Figure out if there is a Packed type corresponding to this Vector
3272 // type. If so, convert to the packed type.
3273 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3274 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
3275 // Turn this into a packed extract_vector_elt operation.
3276 Vec = PackVectorOp(Vec, TVT);
3277 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
3278 } else if (NumElems == 1) {
3279 // This must be an access of the only element. Return it.
3280 return PackVectorOp(Vec, EVT);
3281 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
3283 SplitVectorOp(Vec, Lo, Hi);
3284 if (CIdx->getValue() < NumElems/2) {
3288 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3291 // It's now an extract from the appropriate high or low part. Recurse.
3292 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3293 return LowerVEXTRACT_VECTOR_ELT(Op);
3295 // Variable index case for extract element.
3296 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
3297 assert(0 && "unimp!");
3302 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3304 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3305 SDOperand Vector = Op.getOperand(0);
3306 SDOperand Idx = Op.getOperand(1);
3308 // If the target doesn't support this, store the value to a temporary
3309 // stack slot, then LOAD the scalar element back out.
3310 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
3311 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3312 Vector, StackPtr, DAG.getSrcValue(NULL));
3314 // Add the offset to the index.
3315 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3316 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3317 DAG.getConstant(EltSize, Idx.getValueType()));
3318 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3320 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, DAG.getSrcValue(NULL));
3324 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3325 /// with condition CC on the current target. This usually involves legalizing
3326 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3327 /// there may be no choice but to create a new SetCC node to represent the
3328 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3329 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3330 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3333 SDOperand Tmp1, Tmp2, Result;
3335 switch (getTypeAction(LHS.getValueType())) {
3337 Tmp1 = LegalizeOp(LHS); // LHS
3338 Tmp2 = LegalizeOp(RHS); // RHS
3341 Tmp1 = PromoteOp(LHS); // LHS
3342 Tmp2 = PromoteOp(RHS); // RHS
3344 // If this is an FP compare, the operands have already been extended.
3345 if (MVT::isInteger(LHS.getValueType())) {
3346 MVT::ValueType VT = LHS.getValueType();
3347 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3349 // Otherwise, we have to insert explicit sign or zero extends. Note
3350 // that we could insert sign extends for ALL conditions, but zero extend
3351 // is cheaper on many machines (an AND instead of two shifts), so prefer
3353 switch (cast<CondCodeSDNode>(CC)->get()) {
3354 default: assert(0 && "Unknown integer comparison!");
3361 // ALL of these operations will work if we either sign or zero extend
3362 // the operands (including the unsigned comparisons!). Zero extend is
3363 // usually a simpler/cheaper operation, so prefer it.
3364 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3365 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3371 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3372 DAG.getValueType(VT));
3373 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3374 DAG.getValueType(VT));
3380 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3381 ExpandOp(LHS, LHSLo, LHSHi);
3382 ExpandOp(RHS, RHSLo, RHSHi);
3383 switch (cast<CondCodeSDNode>(CC)->get()) {
3387 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3388 if (RHSCST->isAllOnesValue()) {
3389 // Comparison to -1.
3390 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3395 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3396 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3397 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3398 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3401 // If this is a comparison of the sign bit, just look at the top part.
3403 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3404 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3405 CST->getValue() == 0) || // X < 0
3406 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3407 CST->isAllOnesValue())) { // X > -1
3413 // FIXME: This generated code sucks.
3414 ISD::CondCode LowCC;
3415 switch (cast<CondCodeSDNode>(CC)->get()) {
3416 default: assert(0 && "Unknown integer setcc!");
3418 case ISD::SETULT: LowCC = ISD::SETULT; break;
3420 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3422 case ISD::SETULE: LowCC = ISD::SETULE; break;
3424 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3427 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3428 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3429 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3431 // NOTE: on targets without efficient SELECT of bools, we can always use
3432 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3433 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3434 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3435 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3436 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3437 Result, Tmp1, Tmp2));
3446 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3447 /// The resultant code need not be legal. Note that SrcOp is the input operand
3448 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3449 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3451 // Create the stack frame object.
3452 SDOperand FIPtr = CreateStackTemporary(DestVT);
3454 // Emit a store to the stack slot.
3455 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3456 SrcOp, FIPtr, DAG.getSrcValue(NULL));
3457 // Result is a load from the stack slot.
3458 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0));
3461 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3462 // Create a vector sized/aligned stack slot, store the value to element #0,
3463 // then load the whole vector back out.
3464 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3465 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3466 Node->getOperand(0), StackPtr,
3467 DAG.getSrcValue(NULL));
3468 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,DAG.getSrcValue(NULL));
3472 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3473 /// support the operation, but do support the resultant packed vector type.
3474 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3476 // If the only non-undef value is the low element, turn this into a
3477 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3478 unsigned NumElems = Node->getNumOperands();
3479 bool isOnlyLowElement = true;
3480 SDOperand SplatValue = Node->getOperand(0);
3481 std::map<SDOperand, std::vector<unsigned> > Values;
3482 Values[SplatValue].push_back(0);
3483 bool isConstant = true;
3484 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3485 SplatValue.getOpcode() != ISD::UNDEF)
3488 for (unsigned i = 1; i < NumElems; ++i) {
3489 SDOperand V = Node->getOperand(i);
3490 Values[V].push_back(i);
3491 if (V.getOpcode() != ISD::UNDEF)
3492 isOnlyLowElement = false;
3493 if (SplatValue != V)
3494 SplatValue = SDOperand(0,0);
3496 // If this isn't a constant element or an undef, we can't use a constant
3498 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3499 V.getOpcode() != ISD::UNDEF)
3503 if (isOnlyLowElement) {
3504 // If the low element is an undef too, then this whole things is an undef.
3505 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3506 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3507 // Otherwise, turn this into a scalar_to_vector node.
3508 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3509 Node->getOperand(0));
3512 // If all elements are constants, create a load from the constant pool.
3514 MVT::ValueType VT = Node->getValueType(0);
3516 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3517 std::vector<Constant*> CV;
3518 for (unsigned i = 0, e = NumElems; i != e; ++i) {
3519 if (ConstantFPSDNode *V =
3520 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3521 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3522 } else if (ConstantSDNode *V =
3523 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3524 CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
3526 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3527 CV.push_back(UndefValue::get(OpNTy));
3530 Constant *CP = ConstantPacked::get(CV);
3531 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3532 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
3533 DAG.getSrcValue(NULL));
3536 if (SplatValue.Val) { // Splat of one value?
3537 // Build the shuffle constant vector: <0, 0, 0, 0>
3538 MVT::ValueType MaskVT =
3539 MVT::getIntVectorWithNumElements(NumElems);
3540 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
3541 std::vector<SDOperand> ZeroVec(NumElems, Zero);
3542 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, ZeroVec);
3544 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3545 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
3546 // Get the splatted value into the low element of a vector register.
3547 SDOperand LowValVec =
3548 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3550 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3551 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3552 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3557 // If there are only two unique elements, we may be able to turn this into a
3559 if (Values.size() == 2) {
3560 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
3561 MVT::ValueType MaskVT =
3562 MVT::getIntVectorWithNumElements(NumElems);
3563 std::vector<SDOperand> MaskVec(NumElems);
3565 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3566 E = Values.end(); I != E; ++I) {
3567 for (std::vector<unsigned>::iterator II = I->second.begin(),
3568 EE = I->second.end(); II != EE; ++II)
3569 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
3572 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
3574 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3575 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
3576 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
3577 std::vector<SDOperand> Ops;
3578 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3579 E = Values.end(); I != E; ++I) {
3580 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3584 Ops.push_back(ShuffleMask);
3586 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
3587 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops);
3591 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
3592 // aligned object on the stack, store each element into it, then load
3593 // the result as a vector.
3594 MVT::ValueType VT = Node->getValueType(0);
3595 // Create the stack frame object.
3596 SDOperand FIPtr = CreateStackTemporary(VT);
3598 // Emit a store of each element to the stack slot.
3599 std::vector<SDOperand> Stores;
3600 unsigned TypeByteSize =
3601 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
3602 unsigned VectorSize = MVT::getSizeInBits(VT)/8;
3603 // Store (in the right endianness) the elements to memory.
3604 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3605 // Ignore undef elements.
3606 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3608 unsigned Offset = TypeByteSize*i;
3610 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
3611 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
3613 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3614 Node->getOperand(i), Idx,
3615 DAG.getSrcValue(NULL)));
3618 SDOperand StoreChain;
3619 if (!Stores.empty()) // Not all undef elements?
3620 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
3622 StoreChain = DAG.getEntryNode();
3624 // Result is a load from the stack slot.
3625 return DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0));
3628 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
3629 /// specified value type.
3630 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
3631 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3632 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
3633 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
3634 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
3637 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
3638 SDOperand Op, SDOperand Amt,
3639 SDOperand &Lo, SDOperand &Hi) {
3640 // Expand the subcomponents.
3641 SDOperand LHSL, LHSH;
3642 ExpandOp(Op, LHSL, LHSH);
3644 std::vector<SDOperand> Ops;
3645 Ops.push_back(LHSL);
3646 Ops.push_back(LHSH);
3648 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
3649 Lo = DAG.getNode(NodeOp, VTs, Ops);
3650 Hi = Lo.getValue(1);
3654 /// ExpandShift - Try to find a clever way to expand this shift operation out to
3655 /// smaller elements. If we can't find a way that is more efficient than a
3656 /// libcall on this target, return false. Otherwise, return true with the
3657 /// low-parts expanded into Lo and Hi.
3658 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3659 SDOperand &Lo, SDOperand &Hi) {
3660 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3661 "This is not a shift!");
3663 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3664 SDOperand ShAmt = LegalizeOp(Amt);
3665 MVT::ValueType ShTy = ShAmt.getValueType();
3666 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3667 unsigned NVTBits = MVT::getSizeInBits(NVT);
3669 // Handle the case when Amt is an immediate. Other cases are currently broken
3670 // and are disabled.
3671 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3672 unsigned Cst = CN->getValue();
3673 // Expand the incoming operand to be shifted, so that we have its parts
3675 ExpandOp(Op, InL, InH);
3679 Lo = DAG.getConstant(0, NVT);
3680 Hi = DAG.getConstant(0, NVT);
3681 } else if (Cst > NVTBits) {
3682 Lo = DAG.getConstant(0, NVT);
3683 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
3684 } else if (Cst == NVTBits) {
3685 Lo = DAG.getConstant(0, NVT);
3688 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
3689 Hi = DAG.getNode(ISD::OR, NVT,
3690 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
3691 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
3696 Lo = DAG.getConstant(0, NVT);
3697 Hi = DAG.getConstant(0, NVT);
3698 } else if (Cst > NVTBits) {
3699 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
3700 Hi = DAG.getConstant(0, NVT);
3701 } else if (Cst == NVTBits) {
3703 Hi = DAG.getConstant(0, NVT);
3705 Lo = DAG.getNode(ISD::OR, NVT,
3706 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3707 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3708 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
3713 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
3714 DAG.getConstant(NVTBits-1, ShTy));
3715 } else if (Cst > NVTBits) {
3716 Lo = DAG.getNode(ISD::SRA, NVT, InH,
3717 DAG.getConstant(Cst-NVTBits, ShTy));
3718 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3719 DAG.getConstant(NVTBits-1, ShTy));
3720 } else if (Cst == NVTBits) {
3722 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3723 DAG.getConstant(NVTBits-1, ShTy));
3725 Lo = DAG.getNode(ISD::OR, NVT,
3726 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3727 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3728 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
3737 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
3738 // does not fit into a register, return the lo part and set the hi part to the
3739 // by-reg argument. If it does fit into a single register, return the result
3740 // and leave the Hi part unset.
3741 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3743 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
3744 // The input chain to this libcall is the entry node of the function.
3745 // Legalizing the call will automatically add the previous call to the
3747 SDOperand InChain = DAG.getEntryNode();
3749 TargetLowering::ArgListTy Args;
3750 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3751 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3752 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3753 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3755 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3757 // Splice the libcall in wherever FindInputOutputChains tells us to.
3758 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3759 std::pair<SDOperand,SDOperand> CallInfo =
3760 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3763 // Legalize the call sequence, starting with the chain. This will advance
3764 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
3765 // was added by LowerCallTo (guaranteeing proper serialization of calls).
3766 LegalizeOp(CallInfo.second);
3768 switch (getTypeAction(CallInfo.first.getValueType())) {
3769 default: assert(0 && "Unknown thing");
3771 Result = CallInfo.first;
3774 ExpandOp(CallInfo.first, Result, Hi);
3781 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3782 /// destination type is legal.
3783 SDOperand SelectionDAGLegalize::
3784 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3785 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3786 assert(getTypeAction(Source.getValueType()) == Expand &&
3787 "This is not an expansion!");
3788 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3791 assert(Source.getValueType() == MVT::i64 &&
3792 "This only works for 64-bit -> FP");
3793 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3794 // incoming integer is set. To handle this, we dynamically test to see if
3795 // it is set, and, if so, add a fudge factor.
3797 ExpandOp(Source, Lo, Hi);
3799 // If this is unsigned, and not supported, first perform the conversion to
3800 // signed, then adjust the result if the sign bit is set.
3801 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3802 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3804 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3805 DAG.getConstant(0, Hi.getValueType()),
3807 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3808 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3809 SignSet, Four, Zero);
3810 uint64_t FF = 0x5f800000ULL;
3811 if (TLI.isLittleEndian()) FF <<= 32;
3812 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3814 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3815 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3816 SDOperand FudgeInReg;
3817 if (DestTy == MVT::f32)
3818 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3819 DAG.getSrcValue(NULL));
3821 assert(DestTy == MVT::f64 && "Unexpected conversion");
3822 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3823 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
3825 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3828 // Check to see if the target has a custom way to lower this. If so, use it.
3829 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3830 default: assert(0 && "This action not implemented for this operation!");
3831 case TargetLowering::Legal:
3832 case TargetLowering::Expand:
3833 break; // This case is handled below.
3834 case TargetLowering::Custom: {
3835 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3838 return LegalizeOp(NV);
3839 break; // The target decided this was legal after all
3843 // Expand the source, then glue it back together for the call. We must expand
3844 // the source in case it is shared (this pass of legalize must traverse it).
3845 SDOperand SrcLo, SrcHi;
3846 ExpandOp(Source, SrcLo, SrcHi);
3847 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
3849 const char *FnName = 0;
3850 if (DestTy == MVT::f32)
3851 FnName = "__floatdisf";
3853 assert(DestTy == MVT::f64 && "Unknown fp value type!");
3854 FnName = "__floatdidf";
3857 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
3858 SDOperand UnusedHiPart;
3859 return ExpandLibCall(FnName, Source.Val, UnusedHiPart);
3862 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
3863 /// INT_TO_FP operation of the specified operand when the target requests that
3864 /// we expand it. At this point, we know that the result and operand types are
3865 /// legal for the target.
3866 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
3868 MVT::ValueType DestVT) {
3869 if (Op0.getValueType() == MVT::i32) {
3870 // simple 32-bit [signed|unsigned] integer to float/double expansion
3872 // get the stack frame index of a 8 byte buffer
3873 MachineFunction &MF = DAG.getMachineFunction();
3874 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3875 // get address of 8 byte buffer
3876 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3877 // word offset constant for Hi/Lo address computation
3878 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
3879 // set up Hi and Lo (into buffer) address based on endian
3880 SDOperand Hi = StackSlot;
3881 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
3882 if (TLI.isLittleEndian())
3885 // if signed map to unsigned space
3886 SDOperand Op0Mapped;
3888 // constant used to invert sign bit (signed to unsigned mapping)
3889 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
3890 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
3894 // store the lo of the constructed double - based on integer input
3895 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3896 Op0Mapped, Lo, DAG.getSrcValue(NULL));
3897 // initial hi portion of constructed double
3898 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
3899 // store the hi of the constructed double - biased exponent
3900 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
3901 InitialHi, Hi, DAG.getSrcValue(NULL));
3902 // load the constructed double
3903 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
3904 DAG.getSrcValue(NULL));
3905 // FP constant to bias correct the final result
3906 SDOperand Bias = DAG.getConstantFP(isSigned ?
3907 BitsToDouble(0x4330000080000000ULL)
3908 : BitsToDouble(0x4330000000000000ULL),
3910 // subtract the bias
3911 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
3914 // handle final rounding
3915 if (DestVT == MVT::f64) {
3919 // if f32 then cast to f32
3920 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
3924 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
3925 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
3927 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
3928 DAG.getConstant(0, Op0.getValueType()),
3930 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3931 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3932 SignSet, Four, Zero);
3934 // If the sign bit of the integer is set, the large number will be treated
3935 // as a negative number. To counteract this, the dynamic code adds an
3936 // offset depending on the data type.
3938 switch (Op0.getValueType()) {
3939 default: assert(0 && "Unsupported integer type!");
3940 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
3941 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
3942 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
3943 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
3945 if (TLI.isLittleEndian()) FF <<= 32;
3946 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3948 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3949 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3950 SDOperand FudgeInReg;
3951 if (DestVT == MVT::f32)
3952 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3953 DAG.getSrcValue(NULL));
3955 assert(DestVT == MVT::f64 && "Unexpected conversion");
3956 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
3957 DAG.getEntryNode(), CPIdx,
3958 DAG.getSrcValue(NULL), MVT::f32));
3961 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
3964 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
3965 /// *INT_TO_FP operation of the specified operand when the target requests that
3966 /// we promote it. At this point, we know that the result and operand types are
3967 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
3968 /// operation that takes a larger input.
3969 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
3970 MVT::ValueType DestVT,
3972 // First step, figure out the appropriate *INT_TO_FP operation to use.
3973 MVT::ValueType NewInTy = LegalOp.getValueType();
3975 unsigned OpToUse = 0;
3977 // Scan for the appropriate larger type to use.
3979 NewInTy = (MVT::ValueType)(NewInTy+1);
3980 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
3982 // If the target supports SINT_TO_FP of this type, use it.
3983 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
3985 case TargetLowering::Legal:
3986 if (!TLI.isTypeLegal(NewInTy))
3987 break; // Can't use this datatype.
3989 case TargetLowering::Custom:
3990 OpToUse = ISD::SINT_TO_FP;
3994 if (isSigned) continue;
3996 // If the target supports UINT_TO_FP of this type, use it.
3997 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
3999 case TargetLowering::Legal:
4000 if (!TLI.isTypeLegal(NewInTy))
4001 break; // Can't use this datatype.
4003 case TargetLowering::Custom:
4004 OpToUse = ISD::UINT_TO_FP;
4009 // Otherwise, try a larger type.
4012 // Okay, we found the operation and type to use. Zero extend our input to the
4013 // desired type then run the operation on it.
4014 return DAG.getNode(OpToUse, DestVT,
4015 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4019 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4020 /// FP_TO_*INT operation of the specified operand when the target requests that
4021 /// we promote it. At this point, we know that the result and operand types are
4022 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4023 /// operation that returns a larger result.
4024 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4025 MVT::ValueType DestVT,
4027 // First step, figure out the appropriate FP_TO*INT operation to use.
4028 MVT::ValueType NewOutTy = DestVT;
4030 unsigned OpToUse = 0;
4032 // Scan for the appropriate larger type to use.
4034 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4035 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4037 // If the target supports FP_TO_SINT returning this type, use it.
4038 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4040 case TargetLowering::Legal:
4041 if (!TLI.isTypeLegal(NewOutTy))
4042 break; // Can't use this datatype.
4044 case TargetLowering::Custom:
4045 OpToUse = ISD::FP_TO_SINT;
4050 // If the target supports FP_TO_UINT of this type, use it.
4051 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4053 case TargetLowering::Legal:
4054 if (!TLI.isTypeLegal(NewOutTy))
4055 break; // Can't use this datatype.
4057 case TargetLowering::Custom:
4058 OpToUse = ISD::FP_TO_UINT;
4063 // Otherwise, try a larger type.
4066 // Okay, we found the operation and type to use. Truncate the result of the
4067 // extended FP_TO_*INT operation to the desired size.
4068 return DAG.getNode(ISD::TRUNCATE, DestVT,
4069 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4072 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4074 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4075 MVT::ValueType VT = Op.getValueType();
4076 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4077 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4079 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4081 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4082 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4083 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4085 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4086 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4087 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4088 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4089 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4090 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4091 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4092 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4093 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4095 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4096 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4097 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4098 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4099 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4100 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4101 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4102 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4103 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4104 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4105 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4106 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4107 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4108 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4109 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4110 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4111 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4112 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4113 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4114 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4115 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4119 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4121 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4123 default: assert(0 && "Cannot expand this yet!");
4125 static const uint64_t mask[6] = {
4126 0x5555555555555555ULL, 0x3333333333333333ULL,
4127 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4128 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4130 MVT::ValueType VT = Op.getValueType();
4131 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4132 unsigned len = getSizeInBits(VT);
4133 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4134 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4135 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4136 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4137 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4138 DAG.getNode(ISD::AND, VT,
4139 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4144 // for now, we do this:
4145 // x = x | (x >> 1);
4146 // x = x | (x >> 2);
4148 // x = x | (x >>16);
4149 // x = x | (x >>32); // for 64-bit input
4150 // return popcount(~x);
4152 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4153 MVT::ValueType VT = Op.getValueType();
4154 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4155 unsigned len = getSizeInBits(VT);
4156 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4157 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4158 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4160 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4161 return DAG.getNode(ISD::CTPOP, VT, Op);
4164 // for now, we use: { return popcount(~x & (x - 1)); }
4165 // unless the target has ctlz but not ctpop, in which case we use:
4166 // { return 32 - nlz(~x & (x-1)); }
4167 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4168 MVT::ValueType VT = Op.getValueType();
4169 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4170 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4171 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4172 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4173 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4174 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4175 TLI.isOperationLegal(ISD::CTLZ, VT))
4176 return DAG.getNode(ISD::SUB, VT,
4177 DAG.getConstant(getSizeInBits(VT), VT),
4178 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4179 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4184 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4185 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4186 /// LegalizeNodes map is filled in for any results that are not expanded, the
4187 /// ExpandedNodes map is filled in for any results that are expanded, and the
4188 /// Lo/Hi values are returned.
4189 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4190 MVT::ValueType VT = Op.getValueType();
4191 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4192 SDNode *Node = Op.Val;
4193 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4194 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
4195 "Cannot expand FP values!");
4196 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
4197 "Cannot expand to FP value or to larger int value!");
4199 // See if we already expanded it.
4200 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4201 = ExpandedNodes.find(Op);
4202 if (I != ExpandedNodes.end()) {
4203 Lo = I->second.first;
4204 Hi = I->second.second;
4208 switch (Node->getOpcode()) {
4209 case ISD::CopyFromReg:
4210 assert(0 && "CopyFromReg must be legal!");
4213 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
4215 assert(0 && "Do not know how to expand this operator!");
4218 Lo = DAG.getNode(ISD::UNDEF, NVT);
4219 Hi = DAG.getNode(ISD::UNDEF, NVT);
4221 case ISD::Constant: {
4222 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4223 Lo = DAG.getConstant(Cst, NVT);
4224 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4227 case ISD::BUILD_PAIR:
4228 // Return the operands.
4229 Lo = Node->getOperand(0);
4230 Hi = Node->getOperand(1);
4233 case ISD::SIGN_EXTEND_INREG:
4234 ExpandOp(Node->getOperand(0), Lo, Hi);
4235 // Sign extend the lo-part.
4236 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4237 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4238 TLI.getShiftAmountTy()));
4239 // sext_inreg the low part if needed.
4240 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4244 ExpandOp(Node->getOperand(0), Lo, Hi);
4245 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4246 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4252 ExpandOp(Node->getOperand(0), Lo, Hi);
4253 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4254 DAG.getNode(ISD::CTPOP, NVT, Lo),
4255 DAG.getNode(ISD::CTPOP, NVT, Hi));
4256 Hi = DAG.getConstant(0, NVT);
4260 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4261 ExpandOp(Node->getOperand(0), Lo, Hi);
4262 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4263 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4264 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4266 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4267 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4269 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4270 Hi = DAG.getConstant(0, NVT);
4275 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4276 ExpandOp(Node->getOperand(0), Lo, Hi);
4277 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4278 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4279 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4281 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4282 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4284 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4285 Hi = DAG.getConstant(0, NVT);
4290 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4291 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4292 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4293 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4295 // Remember that we legalized the chain.
4296 Hi = LegalizeOp(Hi);
4297 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4298 if (!TLI.isLittleEndian())
4304 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4305 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4306 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
4308 // Increment the pointer to the other half.
4309 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4310 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4311 getIntPtrConstant(IncrementSize));
4312 // FIXME: This creates a bogus srcvalue!
4313 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
4315 // Build a factor node to remember that this load is independent of the
4317 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4320 // Remember that we legalized the chain.
4321 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4322 if (!TLI.isLittleEndian())
4328 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
4329 SDOperand LL, LH, RL, RH;
4330 ExpandOp(Node->getOperand(0), LL, LH);
4331 ExpandOp(Node->getOperand(1), RL, RH);
4332 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4333 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4337 SDOperand LL, LH, RL, RH;
4338 ExpandOp(Node->getOperand(1), LL, LH);
4339 ExpandOp(Node->getOperand(2), RL, RH);
4340 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4341 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4344 case ISD::SELECT_CC: {
4345 SDOperand TL, TH, FL, FH;
4346 ExpandOp(Node->getOperand(2), TL, TH);
4347 ExpandOp(Node->getOperand(3), FL, FH);
4348 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4349 Node->getOperand(1), TL, FL, Node->getOperand(4));
4350 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4351 Node->getOperand(1), TH, FH, Node->getOperand(4));
4354 case ISD::SEXTLOAD: {
4355 SDOperand Chain = Node->getOperand(0);
4356 SDOperand Ptr = Node->getOperand(1);
4357 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4360 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4362 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4365 // Remember that we legalized the chain.
4366 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4368 // The high part is obtained by SRA'ing all but one of the bits of the lo
4370 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4371 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
4372 TLI.getShiftAmountTy()));
4375 case ISD::ZEXTLOAD: {
4376 SDOperand Chain = Node->getOperand(0);
4377 SDOperand Ptr = Node->getOperand(1);
4378 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4381 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4383 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4386 // Remember that we legalized the chain.
4387 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4389 // The high part is just a zero.
4390 Hi = DAG.getConstant(0, NVT);
4393 case ISD::EXTLOAD: {
4394 SDOperand Chain = Node->getOperand(0);
4395 SDOperand Ptr = Node->getOperand(1);
4396 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4399 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4401 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4404 // Remember that we legalized the chain.
4405 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4407 // The high part is undefined.
4408 Hi = DAG.getNode(ISD::UNDEF, NVT);
4411 case ISD::ANY_EXTEND:
4412 // The low part is any extension of the input (which degenerates to a copy).
4413 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4414 // The high part is undefined.
4415 Hi = DAG.getNode(ISD::UNDEF, NVT);
4417 case ISD::SIGN_EXTEND: {
4418 // The low part is just a sign extension of the input (which degenerates to
4420 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4422 // The high part is obtained by SRA'ing all but one of the bits of the lo
4424 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4425 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4426 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4429 case ISD::ZERO_EXTEND:
4430 // The low part is just a zero extension of the input (which degenerates to
4432 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4434 // The high part is just a zero.
4435 Hi = DAG.getConstant(0, NVT);
4438 case ISD::BIT_CONVERT: {
4439 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0),
4440 Node->getOperand(0));
4441 ExpandOp(Tmp, Lo, Hi);
4445 case ISD::READCYCLECOUNTER:
4446 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
4447 TargetLowering::Custom &&
4448 "Must custom expand ReadCycleCounter");
4449 Lo = TLI.LowerOperation(Op, DAG);
4450 assert(Lo.Val && "Node must be custom expanded!");
4451 Hi = Lo.getValue(1);
4452 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
4453 LegalizeOp(Lo.getValue(2)));
4456 // These operators cannot be expanded directly, emit them as calls to
4457 // library functions.
4458 case ISD::FP_TO_SINT:
4459 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
4461 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4462 case Expand: assert(0 && "cannot expand FP!");
4463 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4464 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4467 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
4469 // Now that the custom expander is done, expand the result, which is still
4472 ExpandOp(Op, Lo, Hi);
4477 if (Node->getOperand(0).getValueType() == MVT::f32)
4478 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
4480 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
4483 case ISD::FP_TO_UINT:
4484 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
4486 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4487 case Expand: assert(0 && "cannot expand FP!");
4488 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4489 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4492 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
4494 // Now that the custom expander is done, expand the result.
4496 ExpandOp(Op, Lo, Hi);
4501 if (Node->getOperand(0).getValueType() == MVT::f32)
4502 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
4504 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
4508 // If the target wants custom lowering, do so.
4509 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4510 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
4511 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
4512 Op = TLI.LowerOperation(Op, DAG);
4514 // Now that the custom expander is done, expand the result, which is
4516 ExpandOp(Op, Lo, Hi);
4521 // If we can emit an efficient shift operation, do so now.
4522 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4525 // If this target supports SHL_PARTS, use it.
4526 TargetLowering::LegalizeAction Action =
4527 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
4528 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4529 Action == TargetLowering::Custom) {
4530 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4534 // Otherwise, emit a libcall.
4535 Lo = ExpandLibCall("__ashldi3", Node, Hi);
4540 // If the target wants custom lowering, do so.
4541 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4542 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
4543 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
4544 Op = TLI.LowerOperation(Op, DAG);
4546 // Now that the custom expander is done, expand the result, which is
4548 ExpandOp(Op, Lo, Hi);
4553 // If we can emit an efficient shift operation, do so now.
4554 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
4557 // If this target supports SRA_PARTS, use it.
4558 TargetLowering::LegalizeAction Action =
4559 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
4560 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4561 Action == TargetLowering::Custom) {
4562 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4566 // Otherwise, emit a libcall.
4567 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
4572 // If the target wants custom lowering, do so.
4573 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4574 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
4575 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
4576 Op = TLI.LowerOperation(Op, DAG);
4578 // Now that the custom expander is done, expand the result, which is
4580 ExpandOp(Op, Lo, Hi);
4585 // If we can emit an efficient shift operation, do so now.
4586 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4589 // If this target supports SRL_PARTS, use it.
4590 TargetLowering::LegalizeAction Action =
4591 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
4592 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4593 Action == TargetLowering::Custom) {
4594 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4598 // Otherwise, emit a libcall.
4599 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
4605 // If the target wants to custom expand this, let them.
4606 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
4607 TargetLowering::Custom) {
4608 Op = TLI.LowerOperation(Op, DAG);
4610 ExpandOp(Op, Lo, Hi);
4615 // Expand the subcomponents.
4616 SDOperand LHSL, LHSH, RHSL, RHSH;
4617 ExpandOp(Node->getOperand(0), LHSL, LHSH);
4618 ExpandOp(Node->getOperand(1), RHSL, RHSH);
4619 std::vector<MVT::ValueType> VTs;
4620 std::vector<SDOperand> LoOps, HiOps;
4621 VTs.push_back(LHSL.getValueType());
4622 VTs.push_back(MVT::Flag);
4623 LoOps.push_back(LHSL);
4624 LoOps.push_back(RHSL);
4625 HiOps.push_back(LHSH);
4626 HiOps.push_back(RHSH);
4627 if (Node->getOpcode() == ISD::ADD) {
4628 Lo = DAG.getNode(ISD::ADDC, VTs, LoOps);
4629 HiOps.push_back(Lo.getValue(1));
4630 Hi = DAG.getNode(ISD::ADDE, VTs, HiOps);
4632 Lo = DAG.getNode(ISD::SUBC, VTs, LoOps);
4633 HiOps.push_back(Lo.getValue(1));
4634 Hi = DAG.getNode(ISD::SUBE, VTs, HiOps);
4639 if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
4640 SDOperand LL, LH, RL, RH;
4641 ExpandOp(Node->getOperand(0), LL, LH);
4642 ExpandOp(Node->getOperand(1), RL, RH);
4643 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
4644 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
4645 // extended the sign bit of the low half through the upper half, and if so
4646 // emit a MULHS instead of the alternate sequence that is valid for any
4647 // i64 x i64 multiply.
4648 if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
4649 // is RH an extension of the sign bit of RL?
4650 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
4651 RH.getOperand(1).getOpcode() == ISD::Constant &&
4652 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
4653 // is LH an extension of the sign bit of LL?
4654 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
4655 LH.getOperand(1).getOpcode() == ISD::Constant &&
4656 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
4657 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
4659 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
4660 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
4661 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
4662 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
4663 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
4665 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4667 Lo = ExpandLibCall("__muldi3" , Node, Hi);
4671 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
4672 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
4673 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
4674 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
4677 // Make sure the resultant values have been legalized themselves, unless this
4678 // is a type that requires multi-step expansion.
4679 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
4680 Lo = LegalizeOp(Lo);
4681 Hi = LegalizeOp(Hi);
4684 // Remember in a map if the values will be reused later.
4686 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4687 assert(isNew && "Value already expanded?!?");
4690 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
4691 /// two smaller values of MVT::Vector type.
4692 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
4694 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
4695 SDNode *Node = Op.Val;
4696 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
4697 assert(NumElements > 1 && "Cannot split a single element vector!");
4698 unsigned NewNumElts = NumElements/2;
4699 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
4700 SDOperand TypeNode = *(Node->op_end()-1);
4702 // See if we already split it.
4703 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4704 = SplitNodes.find(Op);
4705 if (I != SplitNodes.end()) {
4706 Lo = I->second.first;
4707 Hi = I->second.second;
4711 switch (Node->getOpcode()) {
4716 assert(0 && "Unhandled operation in SplitVectorOp!");
4717 case ISD::VBUILD_VECTOR: {
4718 std::vector<SDOperand> LoOps(Node->op_begin(), Node->op_begin()+NewNumElts);
4719 LoOps.push_back(NewNumEltsNode);
4720 LoOps.push_back(TypeNode);
4721 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, LoOps);
4723 std::vector<SDOperand> HiOps(Node->op_begin()+NewNumElts, Node->op_end()-2);
4724 HiOps.push_back(NewNumEltsNode);
4725 HiOps.push_back(TypeNode);
4726 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, HiOps);
4737 SDOperand LL, LH, RL, RH;
4738 SplitVectorOp(Node->getOperand(0), LL, LH);
4739 SplitVectorOp(Node->getOperand(1), RL, RH);
4741 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
4742 NewNumEltsNode, TypeNode);
4743 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
4744 NewNumEltsNode, TypeNode);
4748 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4749 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4750 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4752 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4753 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
4754 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4755 getIntPtrConstant(IncrementSize));
4756 // FIXME: This creates a bogus srcvalue!
4757 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4759 // Build a factor node to remember that this load is independent of the
4761 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4764 // Remember that we legalized the chain.
4765 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4768 case ISD::VBIT_CONVERT: {
4769 // We know the result is a vector. The input may be either a vector or a
4771 if (Op.getOperand(0).getValueType() != MVT::Vector) {
4772 // Lower to a store/load. FIXME: this could be improved probably.
4773 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
4775 SDOperand St = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
4776 Op.getOperand(0), Ptr, DAG.getSrcValue(0));
4777 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4778 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0));
4779 SplitVectorOp(St, Lo, Hi);
4781 // If the input is a vector type, we have to either scalarize it, pack it
4782 // or convert it based on whether the input vector type is legal.
4783 SDNode *InVal = Node->getOperand(0).Val;
4785 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
4786 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
4788 // If the input is from a single element vector, scalarize the vector,
4789 // then treat like a scalar.
4790 if (NumElems == 1) {
4791 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT);
4792 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar,
4793 Op.getOperand(1), Op.getOperand(2));
4794 SplitVectorOp(Scalar, Lo, Hi);
4796 // Split the input vector.
4797 SplitVectorOp(Op.getOperand(0), Lo, Hi);
4799 // Convert each of the pieces now.
4800 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo,
4801 NewNumEltsNode, TypeNode);
4802 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi,
4803 NewNumEltsNode, TypeNode);
4810 // Remember in a map if the values will be reused later.
4812 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4813 assert(isNew && "Value already expanded?!?");
4817 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
4818 /// equivalent operation that returns a scalar (e.g. F32) or packed value
4819 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
4820 /// type for the result.
4821 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
4822 MVT::ValueType NewVT) {
4823 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
4824 SDNode *Node = Op.Val;
4826 // See if we already packed it.
4827 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
4828 if (I != PackedNodes.end()) return I->second;
4831 switch (Node->getOpcode()) {
4834 Node->dump(); std::cerr << "\n";
4836 assert(0 && "Unknown vector operation in PackVectorOp!");
4845 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
4847 PackVectorOp(Node->getOperand(0), NewVT),
4848 PackVectorOp(Node->getOperand(1), NewVT));
4851 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
4852 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
4854 Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(2));
4856 // Remember that we legalized the chain.
4857 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4860 case ISD::VBUILD_VECTOR:
4861 if (Node->getOperand(0).getValueType() == NewVT) {
4862 // Returning a scalar?
4863 Result = Node->getOperand(0);
4865 // Returning a BUILD_VECTOR?
4867 // If all elements of the build_vector are undefs, return an undef.
4868 bool AllUndef = true;
4869 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i)
4870 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) {
4875 Result = DAG.getNode(ISD::UNDEF, NewVT);
4877 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()-2);
4878 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops);
4882 case ISD::VINSERT_VECTOR_ELT:
4883 if (!MVT::isVector(NewVT)) {
4884 // Returning a scalar? Must be the inserted element.
4885 Result = Node->getOperand(1);
4887 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
4888 PackVectorOp(Node->getOperand(0), NewVT),
4889 Node->getOperand(1), Node->getOperand(2));
4892 case ISD::VVECTOR_SHUFFLE:
4893 if (!MVT::isVector(NewVT)) {
4894 // Returning a scalar? Figure out if it is the LHS or RHS and return it.
4895 SDOperand EltNum = Node->getOperand(2).getOperand(0);
4896 if (cast<ConstantSDNode>(EltNum)->getValue())
4897 Result = PackVectorOp(Node->getOperand(1), NewVT);
4899 Result = PackVectorOp(Node->getOperand(0), NewVT);
4901 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index
4902 // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
4903 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
4904 Node->getOperand(2).Val->op_end()-2);
4905 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
4906 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT, BuildVecIdx);
4908 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
4909 PackVectorOp(Node->getOperand(0), NewVT),
4910 PackVectorOp(Node->getOperand(1), NewVT), BV);
4913 case ISD::VBIT_CONVERT:
4914 if (Op.getOperand(0).getValueType() != MVT::Vector)
4915 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
4917 // If the input is a vector type, we have to either scalarize it, pack it
4918 // or convert it based on whether the input vector type is legal.
4919 SDNode *InVal = Node->getOperand(0).Val;
4921 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
4922 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
4924 // Figure out if there is a Packed type corresponding to this Vector
4925 // type. If so, convert to the packed type.
4926 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
4927 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
4928 // Turn this into a bit convert of the packed input.
4929 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
4930 PackVectorOp(Node->getOperand(0), TVT));
4932 } else if (NumElems == 1) {
4933 // Turn this into a bit convert of the scalar input.
4934 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
4935 PackVectorOp(Node->getOperand(0), EVT));
4939 assert(0 && "Cast from unsupported vector type not implemented yet!");
4944 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
4945 PackVectorOp(Op.getOperand(1), NewVT),
4946 PackVectorOp(Op.getOperand(2), NewVT));
4950 if (TLI.isTypeLegal(NewVT))
4951 Result = LegalizeOp(Result);
4952 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
4953 assert(isNew && "Value already packed?");
4958 // SelectionDAG::Legalize - This is the entry point for the file.
4960 void SelectionDAG::Legalize() {
4961 if (ViewLegalizeDAGs) viewGraph();
4963 /// run - This is the main entry point to this class.
4965 SelectionDAGLegalize(*this).LegalizeDAG();