1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineConstantPool.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/Constants.h"
25 //===----------------------------------------------------------------------===//
26 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
27 /// hacks on it until the target machine can handle it. This involves
28 /// eliminating value sizes the machine cannot handle (promoting small sizes to
29 /// large sizes or splitting up large values into small values) as well as
30 /// eliminating operations the machine cannot handle.
32 /// This code also does a small amount of optimization and recognition of idioms
33 /// as part of its processing. For example, if a target does not support a
34 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
35 /// will attempt merge setcc and brc instructions into brcc's.
38 class SelectionDAGLegalize {
42 /// LegalizeAction - This enum indicates what action we should take for each
43 /// value type the can occur in the program.
45 Legal, // The target natively supports this value type.
46 Promote, // This should be promoted to the next larger type.
47 Expand, // This integer type should be broken into smaller pieces.
50 /// ValueTypeActions - This is a bitvector that contains two bits for each
51 /// value type, where the two bits correspond to the LegalizeAction enum.
52 /// This can be queried with "getTypeAction(VT)".
53 unsigned ValueTypeActions;
55 /// NeedsAnotherIteration - This is set when we expand a large integer
56 /// operation into smaller integer operations, but the smaller operations are
57 /// not set. This occurs only rarely in practice, for targets that don't have
58 /// 32-bit or larger integer registers.
59 bool NeedsAnotherIteration;
61 /// LegalizedNodes - For nodes that are of legal width, and that have more
62 /// than one use, this map indicates what regularized operand to use. This
63 /// allows us to avoid legalizing the same thing more than once.
64 std::map<SDOperand, SDOperand> LegalizedNodes;
66 /// PromotedNodes - For nodes that are below legal width, and that have more
67 /// than one use, this map indicates what promoted value to use. This allows
68 /// us to avoid promoting the same thing more than once.
69 std::map<SDOperand, SDOperand> PromotedNodes;
71 /// ExpandedNodes - For nodes that need to be expanded, and which have more
72 /// than one use, this map indicates which which operands are the expanded
73 /// version of the input. This allows us to avoid expanding the same node
75 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
77 void AddLegalizedOperand(SDOperand From, SDOperand To) {
78 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second;
79 assert(isNew && "Got into the map somehow?");
81 void AddPromotedOperand(SDOperand From, SDOperand To) {
82 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
83 assert(isNew && "Got into the map somehow?");
88 SelectionDAGLegalize(SelectionDAG &DAG);
90 /// Run - While there is still lowering to do, perform a pass over the DAG.
91 /// Most regularization can be done in a single pass, but targets that require
92 /// large values to be split into registers multiple times (e.g. i64 -> 4x
93 /// i16) require iteration for these values (the first iteration will demote
94 /// to i32, the second will demote to i16).
97 NeedsAnotherIteration = false;
99 } while (NeedsAnotherIteration);
102 /// getTypeAction - Return how we should legalize values of this type, either
103 /// it is already legal or we need to expand it into multiple registers of
104 /// smaller integer type, or we need to promote it to a larger type.
105 LegalizeAction getTypeAction(MVT::ValueType VT) const {
106 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3);
109 /// isTypeLegal - Return true if this type is legal on this target.
111 bool isTypeLegal(MVT::ValueType VT) const {
112 return getTypeAction(VT) == Legal;
118 SDOperand LegalizeOp(SDOperand O);
119 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
120 SDOperand PromoteOp(SDOperand O);
122 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
124 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
126 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
127 SDOperand &Lo, SDOperand &Hi);
128 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
129 SDOperand &Lo, SDOperand &Hi);
130 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
131 SDOperand &Lo, SDOperand &Hi);
133 SDOperand getIntPtrConstant(uint64_t Val) {
134 return DAG.getConstant(Val, TLI.getPointerTy());
140 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
141 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
142 ValueTypeActions(TLI.getValueTypeActions()) {
143 assert(MVT::LAST_VALUETYPE <= 16 &&
144 "Too many value types for ValueTypeActions to hold!");
147 void SelectionDAGLegalize::LegalizeDAG() {
148 SDOperand OldRoot = DAG.getRoot();
149 SDOperand NewRoot = LegalizeOp(OldRoot);
150 DAG.setRoot(NewRoot);
152 ExpandedNodes.clear();
153 LegalizedNodes.clear();
154 PromotedNodes.clear();
156 // Remove dead nodes now.
157 DAG.RemoveDeadNodes(OldRoot.Val);
160 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
161 assert(getTypeAction(Op.getValueType()) == Legal &&
162 "Caller should expand or promote operands that are not legal!");
164 // If this operation defines any values that cannot be represented in a
165 // register on this target, make sure to expand or promote them.
166 if (Op.Val->getNumValues() > 1) {
167 for (unsigned i = 0, e = Op.Val->getNumValues(); i != e; ++i)
168 switch (getTypeAction(Op.Val->getValueType(i))) {
169 case Legal: break; // Nothing to do.
172 ExpandOp(Op.getValue(i), T1, T2);
173 assert(LegalizedNodes.count(Op) &&
174 "Expansion didn't add legal operands!");
175 return LegalizedNodes[Op];
178 PromoteOp(Op.getValue(i));
179 assert(LegalizedNodes.count(Op) &&
180 "Expansion didn't add legal operands!");
181 return LegalizedNodes[Op];
185 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
186 if (I != LegalizedNodes.end()) return I->second;
188 SDOperand Tmp1, Tmp2, Tmp3;
190 SDOperand Result = Op;
191 SDNode *Node = Op.Val;
193 switch (Node->getOpcode()) {
195 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
196 assert(0 && "Do not know how to legalize this operator!");
198 case ISD::EntryToken:
199 case ISD::FrameIndex:
200 case ISD::GlobalAddress:
201 case ISD::ExternalSymbol:
202 case ISD::ConstantPool: // Nothing to do.
203 assert(getTypeAction(Node->getValueType(0)) == Legal &&
204 "This must be legal!");
206 case ISD::CopyFromReg:
207 Tmp1 = LegalizeOp(Node->getOperand(0));
208 if (Tmp1 != Node->getOperand(0))
209 Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(),
210 Node->getValueType(0), Tmp1);
212 Result = Op.getValue(0);
214 // Since CopyFromReg produces two values, make sure to remember that we
215 // legalized both of them.
216 AddLegalizedOperand(Op.getValue(0), Result);
217 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
218 return Result.getValue(Op.ResNo);
219 case ISD::ImplicitDef:
220 Tmp1 = LegalizeOp(Node->getOperand(0));
221 if (Tmp1 != Node->getOperand(0))
222 Result = DAG.getImplicitDef(Tmp1, cast<RegSDNode>(Node)->getReg());
225 MVT::ValueType VT = Op.getValueType();
226 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
227 default: assert(0 && "This action is not supported yet!");
228 case TargetLowering::Expand:
229 case TargetLowering::Promote:
230 if (MVT::isInteger(VT))
231 Result = DAG.getConstant(0, VT);
232 else if (MVT::isFloatingPoint(VT))
233 Result = DAG.getConstantFP(0, VT);
235 assert(0 && "Unknown value type!");
237 case TargetLowering::Legal:
243 // We know we don't need to expand constants here, constants only have one
244 // value and we check that it is fine above.
246 // FIXME: Maybe we should handle things like targets that don't support full
247 // 32-bit immediates?
249 case ISD::ConstantFP: {
250 // Spill FP immediates to the constant pool if the target cannot directly
251 // codegen them. Targets often have some immediate values that can be
252 // efficiently generated into an FP register without a load. We explicitly
253 // leave these constants as ConstantFP nodes for the target to deal with.
255 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
257 // Check to see if this FP immediate is already legal.
258 bool isLegal = false;
259 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
260 E = TLI.legal_fpimm_end(); I != E; ++I)
261 if (CFP->isExactlyValue(*I)) {
267 // Otherwise we need to spill the constant to memory.
268 MachineConstantPool *CP = DAG.getMachineFunction().getConstantPool();
272 // If a FP immediate is precise when represented as a float, we put it
273 // into the constant pool as a float, even if it's is statically typed
275 MVT::ValueType VT = CFP->getValueType(0);
276 bool isDouble = VT == MVT::f64;
277 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
278 Type::FloatTy, CFP->getValue());
279 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
280 // Only do this if the target has a native EXTLOAD instruction from
282 TLI.getOperationAction(ISD::EXTLOAD,
283 MVT::f32) == TargetLowering::Legal) {
284 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
289 SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(LLVMC),
292 Result = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), CPIdx,
295 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx);
300 case ISD::TokenFactor: {
301 std::vector<SDOperand> Ops;
302 bool Changed = false;
303 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
304 SDOperand Op = Node->getOperand(i);
305 // Fold single-use TokenFactor nodes into this token factor as we go.
306 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
308 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
309 Ops.push_back(LegalizeOp(Op.getOperand(j)));
311 Ops.push_back(LegalizeOp(Op)); // Legalize the operands
312 Changed |= Ops[i] != Op;
316 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
320 case ISD::ADJCALLSTACKDOWN:
321 case ISD::ADJCALLSTACKUP:
322 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
323 // There is no need to legalize the size argument (Operand #1)
324 if (Tmp1 != Node->getOperand(0))
325 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1,
326 Node->getOperand(1));
328 case ISD::DYNAMIC_STACKALLOC:
329 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
330 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
331 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
332 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
333 Tmp3 != Node->getOperand(2))
334 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, Node->getValueType(0),
337 Result = Op.getValue(0);
339 // Since this op produces two values, make sure to remember that we
340 // legalized both of them.
341 AddLegalizedOperand(SDOperand(Node, 0), Result);
342 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
343 return Result.getValue(Op.ResNo);
346 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
347 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
349 bool Changed = false;
350 std::vector<SDOperand> Ops;
351 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
352 Ops.push_back(LegalizeOp(Node->getOperand(i)));
353 Changed |= Ops.back() != Node->getOperand(i);
356 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) {
357 std::vector<MVT::ValueType> RetTyVTs;
358 RetTyVTs.reserve(Node->getNumValues());
359 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
360 RetTyVTs.push_back(Node->getValueType(i));
361 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops), 0);
363 Result = Result.getValue(0);
365 // Since calls produce multiple values, make sure to remember that we
366 // legalized all of them.
367 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
368 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
369 return Result.getValue(Op.ResNo);
372 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
373 if (Tmp1 != Node->getOperand(0))
374 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1));
378 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
380 switch (getTypeAction(Node->getOperand(1).getValueType())) {
381 case Expand: assert(0 && "It's impossible to expand bools");
383 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
386 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
389 // Basic block destination (Op#2) is always legal.
390 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
391 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
392 Node->getOperand(2));
394 case ISD::BRCONDTWOWAY:
395 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
396 switch (getTypeAction(Node->getOperand(1).getValueType())) {
397 case Expand: assert(0 && "It's impossible to expand bools");
399 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
402 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
405 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR
407 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) {
408 case TargetLowering::Promote:
409 default: assert(0 && "This action is not supported yet!");
410 case TargetLowering::Legal:
411 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
412 std::vector<SDOperand> Ops;
415 Ops.push_back(Node->getOperand(2));
416 Ops.push_back(Node->getOperand(3));
417 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops);
420 case TargetLowering::Expand:
421 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
422 Node->getOperand(2));
423 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3));
429 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
430 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
431 if (Tmp1 != Node->getOperand(0) ||
432 Tmp2 != Node->getOperand(1))
433 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2);
435 Result = SDOperand(Node, 0);
437 // Since loads produce two values, make sure to remember that we legalized
439 AddLegalizedOperand(SDOperand(Node, 0), Result);
440 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
441 return Result.getValue(Op.ResNo);
445 case ISD::ZEXTLOAD: {
446 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
447 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
449 MVT::ValueType SrcVT = cast<MVTSDNode>(Node)->getExtraValueType();
450 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
451 default: assert(0 && "This action is not supported yet!");
452 case TargetLowering::Promote:
453 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
454 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0),
455 Tmp1, Tmp2, MVT::i8);
456 // Since loads produce two values, make sure to remember that we legalized
458 AddLegalizedOperand(SDOperand(Node, 0), Result);
459 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
460 return Result.getValue(Op.ResNo);
462 case TargetLowering::Legal:
463 if (Tmp1 != Node->getOperand(0) ||
464 Tmp2 != Node->getOperand(1))
465 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0),
468 Result = SDOperand(Node, 0);
470 // Since loads produce two values, make sure to remember that we legalized
472 AddLegalizedOperand(SDOperand(Node, 0), Result);
473 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
474 return Result.getValue(Op.ResNo);
475 case TargetLowering::Expand:
476 assert(Node->getOpcode() != ISD::EXTLOAD &&
477 "EXTLOAD should always be supported!");
478 // Turn the unsupported load into an EXTLOAD followed by an explicit
479 // zero/sign extend inreg.
480 Result = DAG.getNode(ISD::EXTLOAD, Node->getValueType(0),
483 if (Node->getOpcode() == ISD::SEXTLOAD)
484 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
487 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
488 AddLegalizedOperand(SDOperand(Node, 0), ValRes);
489 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
491 return Result.getValue(1);
494 assert(0 && "Unreachable");
496 case ISD::EXTRACT_ELEMENT:
497 // Get both the low and high parts.
498 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
499 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
500 Result = Tmp2; // 1 -> Hi
502 Result = Tmp1; // 0 -> Lo
506 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
508 switch (getTypeAction(Node->getOperand(1).getValueType())) {
510 // Legalize the incoming value (must be legal).
511 Tmp2 = LegalizeOp(Node->getOperand(1));
512 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
513 Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg());
516 Tmp2 = PromoteOp(Node->getOperand(1));
517 Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg());
521 ExpandOp(Node->getOperand(1), Lo, Hi);
522 unsigned Reg = cast<RegSDNode>(Node)->getReg();
523 Lo = DAG.getCopyToReg(Tmp1, Lo, Reg);
524 Hi = DAG.getCopyToReg(Tmp1, Hi, Reg+1);
525 // Note that the copytoreg nodes are independent of each other.
526 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
527 assert(isTypeLegal(Result.getValueType()) &&
528 "Cannot expand multiple times yet (i64 -> i16)");
534 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
535 switch (Node->getNumOperands()) {
537 switch (getTypeAction(Node->getOperand(1).getValueType())) {
539 Tmp2 = LegalizeOp(Node->getOperand(1));
540 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
541 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
545 ExpandOp(Node->getOperand(1), Lo, Hi);
546 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
550 Tmp2 = PromoteOp(Node->getOperand(1));
551 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
556 if (Tmp1 != Node->getOperand(0))
557 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1);
559 default: { // ret <values>
560 std::vector<SDOperand> NewValues;
561 NewValues.push_back(Tmp1);
562 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
563 switch (getTypeAction(Node->getOperand(i).getValueType())) {
565 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
569 ExpandOp(Node->getOperand(i), Lo, Hi);
570 NewValues.push_back(Lo);
571 NewValues.push_back(Hi);
575 assert(0 && "Can't promote multiple return value yet!");
577 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
583 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
584 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
586 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
587 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
588 if (CFP->getValueType(0) == MVT::f32) {
593 V.F = CFP->getValue();
594 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
595 DAG.getConstant(V.I, MVT::i32), Tmp2);
597 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
602 V.F = CFP->getValue();
603 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
604 DAG.getConstant(V.I, MVT::i64), Tmp2);
609 switch (getTypeAction(Node->getOperand(1).getValueType())) {
611 SDOperand Val = LegalizeOp(Node->getOperand(1));
612 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) ||
613 Tmp2 != Node->getOperand(2))
614 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2);
618 // Truncate the value and store the result.
619 Tmp3 = PromoteOp(Node->getOperand(1));
620 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
621 Node->getOperand(1).getValueType());
626 ExpandOp(Node->getOperand(1), Lo, Hi);
628 if (!TLI.isLittleEndian())
631 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2);
633 unsigned IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
634 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
635 getIntPtrConstant(IncrementSize));
636 assert(isTypeLegal(Tmp2.getValueType()) &&
637 "Pointers must be legal!");
638 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2);
639 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
644 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
645 if (Tmp1 != Node->getOperand(0))
646 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1));
648 case ISD::TRUNCSTORE:
649 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
650 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
652 switch (getTypeAction(Node->getOperand(1).getValueType())) {
654 Tmp2 = LegalizeOp(Node->getOperand(1));
655 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
656 Tmp3 != Node->getOperand(2))
657 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
658 cast<MVTSDNode>(Node)->getExtraValueType());
662 assert(0 && "Cannot handle illegal TRUNCSTORE yet!");
666 switch (getTypeAction(Node->getOperand(0).getValueType())) {
667 case Expand: assert(0 && "It's impossible to expand bools");
669 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
672 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
675 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
676 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
678 switch (TLI.getOperationAction(Node->getOpcode(), Tmp2.getValueType())) {
679 default: assert(0 && "This action is not supported yet!");
680 case TargetLowering::Legal:
681 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
682 Tmp3 != Node->getOperand(2))
683 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0),
686 case TargetLowering::Promote: {
688 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
689 unsigned ExtOp, TruncOp;
690 if (MVT::isInteger(Tmp2.getValueType())) {
691 ExtOp = ISD::ZERO_EXTEND;
692 TruncOp = ISD::TRUNCATE;
694 ExtOp = ISD::FP_EXTEND;
695 TruncOp = ISD::FP_ROUND;
697 // Promote each of the values to the new type.
698 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
699 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
700 // Perform the larger operation, then round down.
701 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
702 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
708 switch (getTypeAction(Node->getOperand(0).getValueType())) {
710 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
711 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
712 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
713 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
714 Node->getValueType(0), Tmp1, Tmp2);
717 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS
718 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS
720 // If this is an FP compare, the operands have already been extended.
721 if (MVT::isInteger(Node->getOperand(0).getValueType())) {
722 MVT::ValueType VT = Node->getOperand(0).getValueType();
723 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
725 // Otherwise, we have to insert explicit sign or zero extends. Note
726 // that we could insert sign extends for ALL conditions, but zero extend
727 // is cheaper on many machines (an AND instead of two shifts), so prefer
729 switch (cast<SetCCSDNode>(Node)->getCondition()) {
730 default: assert(0 && "Unknown integer comparison!");
737 // ALL of these operations will work if we either sign or zero extend
738 // the operands (including the unsigned comparisons!). Zero extend is
739 // usually a simpler/cheaper operation, so prefer it.
740 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
741 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
747 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT);
748 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, VT);
753 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
754 Node->getValueType(0), Tmp1, Tmp2);
757 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
758 ExpandOp(Node->getOperand(0), LHSLo, LHSHi);
759 ExpandOp(Node->getOperand(1), RHSLo, RHSHi);
760 switch (cast<SetCCSDNode>(Node)->getCondition()) {
764 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
765 if (RHSCST->isAllOnesValue()) {
767 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
768 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
769 Node->getValueType(0), Tmp1, RHSLo);
773 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
774 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
775 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
776 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
777 Node->getValueType(0), Tmp1,
778 DAG.getConstant(0, Tmp1.getValueType()));
781 // If this is a comparison of the sign bit, just look at the top part.
783 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
784 if ((cast<SetCCSDNode>(Node)->getCondition() == ISD::SETLT &&
785 CST->getValue() == 0) || // X < 0
786 (cast<SetCCSDNode>(Node)->getCondition() == ISD::SETGT &&
787 (CST->isAllOnesValue()))) // X > -1
788 return DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
789 Node->getValueType(0), LHSHi, RHSHi);
791 // FIXME: This generated code sucks.
793 switch (cast<SetCCSDNode>(Node)->getCondition()) {
794 default: assert(0 && "Unknown integer setcc!");
796 case ISD::SETULT: LowCC = ISD::SETULT; break;
798 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
800 case ISD::SETULE: LowCC = ISD::SETULE; break;
802 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
805 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
806 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
807 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
809 // NOTE: on targets without efficient SELECT of bools, we can always use
810 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
811 Tmp1 = DAG.getSetCC(LowCC, Node->getValueType(0), LHSLo, RHSLo);
812 Tmp2 = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
813 Node->getValueType(0), LHSHi, RHSHi);
814 Result = DAG.getSetCC(ISD::SETEQ, Node->getValueType(0), LHSHi, RHSHi);
815 Result = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
825 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
826 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
828 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
829 switch (getTypeAction(Node->getOperand(2).getValueType())) {
830 case Expand: assert(0 && "Cannot expand a byte!");
832 Tmp3 = LegalizeOp(Node->getOperand(2));
835 Tmp3 = PromoteOp(Node->getOperand(2));
839 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
843 switch (getTypeAction(Node->getOperand(3).getValueType())) {
844 case Expand: assert(0 && "Cannot expand this yet!");
846 Tmp4 = LegalizeOp(Node->getOperand(3));
849 Tmp4 = PromoteOp(Node->getOperand(3));
854 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
855 case Expand: assert(0 && "Cannot expand this yet!");
857 Tmp5 = LegalizeOp(Node->getOperand(4));
860 Tmp5 = PromoteOp(Node->getOperand(4));
864 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
865 default: assert(0 && "This action not implemented for this operation!");
866 case TargetLowering::Legal:
867 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
868 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) ||
869 Tmp5 != Node->getOperand(4)) {
870 std::vector<SDOperand> Ops;
871 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
872 Ops.push_back(Tmp4); Ops.push_back(Tmp5);
873 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops);
876 case TargetLowering::Expand: {
877 // Otherwise, the target does not support this operation. Lower the
878 // operation to an explicit libcall as appropriate.
879 MVT::ValueType IntPtr = TLI.getPointerTy();
880 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType();
881 std::vector<std::pair<SDOperand, const Type*> > Args;
883 const char *FnName = 0;
884 if (Node->getOpcode() == ISD::MEMSET) {
885 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
886 // Extend the ubyte argument to be an int value for the call.
887 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
888 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
889 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
892 } else if (Node->getOpcode() == ISD::MEMCPY ||
893 Node->getOpcode() == ISD::MEMMOVE) {
894 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
895 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
896 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
897 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
899 assert(0 && "Unknown op!");
901 std::pair<SDOperand,SDOperand> CallResult =
902 TLI.LowerCallTo(Tmp1, Type::VoidTy, false,
903 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
904 Result = LegalizeOp(CallResult.second);
907 case TargetLowering::Custom:
908 std::vector<SDOperand> Ops;
909 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
910 Ops.push_back(Tmp4); Ops.push_back(Tmp5);
911 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops);
912 Result = TLI.LowerOperation(Result);
913 Result = LegalizeOp(Result);
922 case ISD::SRL_PARTS: {
923 std::vector<SDOperand> Ops;
924 bool Changed = false;
925 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
926 Ops.push_back(LegalizeOp(Node->getOperand(i)));
927 Changed |= Ops.back() != Node->getOperand(i);
930 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops);
932 // Since these produce multiple values, make sure to remember that we
933 // legalized all of them.
934 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
935 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
936 return Result.getValue(Op.ResNo);
953 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
954 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
955 if (Tmp1 != Node->getOperand(0) ||
956 Tmp2 != Node->getOperand(1))
957 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
962 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
963 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
964 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
965 case TargetLowering::Legal:
966 if (Tmp1 != Node->getOperand(0) ||
967 Tmp2 != Node->getOperand(1))
968 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
971 case TargetLowering::Promote:
972 case TargetLowering::Custom:
973 assert(0 && "Cannot promote/custom handle this yet!");
974 case TargetLowering::Expand: {
975 MVT::ValueType VT = Node->getValueType(0);
976 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
977 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
978 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
979 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
988 Tmp1 = LegalizeOp(Node->getOperand(0));
989 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
990 case TargetLowering::Legal:
991 if (Tmp1 != Node->getOperand(0))
992 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
994 case TargetLowering::Promote:
995 case TargetLowering::Custom:
996 assert(0 && "Cannot promote/custom handle this yet!");
997 case TargetLowering::Expand:
998 if (Node->getOpcode() == ISD::FNEG) {
999 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
1000 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
1001 Result = LegalizeOp(DAG.getNode(ISD::SUB, Node->getValueType(0),
1003 } else if (Node->getOpcode() == ISD::FABS) {
1004 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
1005 MVT::ValueType VT = Node->getValueType(0);
1006 Tmp2 = DAG.getConstantFP(0.0, VT);
1007 Tmp2 = DAG.getSetCC(ISD::SETUGT, TLI.getSetCCResultTy(), Tmp1, Tmp2);
1008 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
1009 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
1010 Result = LegalizeOp(Result);
1012 assert(0 && "Unreachable!");
1018 // Conversion operators. The source and destination have different types.
1019 case ISD::ZERO_EXTEND:
1020 case ISD::SIGN_EXTEND:
1022 case ISD::FP_EXTEND:
1024 case ISD::FP_TO_SINT:
1025 case ISD::FP_TO_UINT:
1026 case ISD::SINT_TO_FP:
1027 case ISD::UINT_TO_FP:
1028 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1030 Tmp1 = LegalizeOp(Node->getOperand(0));
1031 if (Tmp1 != Node->getOperand(0))
1032 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1035 if (Node->getOpcode() == ISD::SINT_TO_FP ||
1036 Node->getOpcode() == ISD::UINT_TO_FP) {
1037 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
1038 Node->getValueType(0), Node->getOperand(0));
1039 Result = LegalizeOp(Result);
1041 } else if (Node->getOpcode() == ISD::TRUNCATE) {
1042 // In the expand case, we must be dealing with a truncate, because
1043 // otherwise the result would be larger than the source.
1044 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1046 // Since the result is legal, we should just be able to truncate the low
1047 // part of the source.
1048 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
1051 assert(0 && "Shouldn't need to expand other operators here!");
1054 switch (Node->getOpcode()) {
1055 case ISD::ZERO_EXTEND:
1056 Result = PromoteOp(Node->getOperand(0));
1057 // NOTE: Any extend would work here...
1058 Result = DAG.getNode(ISD::ZERO_EXTEND, Op.getValueType(), Result);
1059 Result = DAG.getZeroExtendInReg(Result,
1060 Node->getOperand(0).getValueType());
1062 case ISD::SIGN_EXTEND:
1063 Result = PromoteOp(Node->getOperand(0));
1064 // NOTE: Any extend would work here...
1065 Result = DAG.getNode(ISD::ZERO_EXTEND, Op.getValueType(), Result);
1066 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1067 Result, Node->getOperand(0).getValueType());
1070 Result = PromoteOp(Node->getOperand(0));
1071 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
1073 case ISD::FP_EXTEND:
1074 Result = PromoteOp(Node->getOperand(0));
1075 if (Result.getValueType() != Op.getValueType())
1076 // Dynamically dead while we have only 2 FP types.
1077 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
1080 case ISD::FP_TO_SINT:
1081 case ISD::FP_TO_UINT:
1082 Result = PromoteOp(Node->getOperand(0));
1083 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
1085 case ISD::SINT_TO_FP:
1086 Result = PromoteOp(Node->getOperand(0));
1087 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1088 Result, Node->getOperand(0).getValueType());
1089 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result);
1091 case ISD::UINT_TO_FP:
1092 Result = PromoteOp(Node->getOperand(0));
1093 Result = DAG.getZeroExtendInReg(Result,
1094 Node->getOperand(0).getValueType());
1095 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result);
1100 case ISD::FP_ROUND_INREG:
1101 case ISD::SIGN_EXTEND_INREG: {
1102 Tmp1 = LegalizeOp(Node->getOperand(0));
1103 MVT::ValueType ExtraVT = cast<MVTSDNode>(Node)->getExtraValueType();
1105 // If this operation is not supported, convert it to a shl/shr or load/store
1107 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
1108 default: assert(0 && "This action not supported for this op yet!");
1109 case TargetLowering::Legal:
1110 if (Tmp1 != Node->getOperand(0))
1111 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
1114 case TargetLowering::Expand:
1115 // If this is an integer extend and shifts are supported, do that.
1116 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
1117 // NOTE: we could fall back on load/store here too for targets without
1118 // SAR. However, it is doubtful that any exist.
1119 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
1120 MVT::getSizeInBits(ExtraVT);
1121 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
1122 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
1123 Node->getOperand(0), ShiftCst);
1124 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
1126 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
1127 // The only way we can lower this is to turn it into a STORETRUNC,
1128 // EXTLOAD pair, targetting a temporary location (a stack slot).
1130 // NOTE: there is a choice here between constantly creating new stack
1131 // slots and always reusing the same one. We currently always create
1132 // new ones, as reuse may inhibit scheduling.
1133 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
1134 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
1135 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
1136 MachineFunction &MF = DAG.getMachineFunction();
1138 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
1139 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
1140 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
1141 Node->getOperand(0), StackSlot, ExtraVT);
1142 Result = DAG.getNode(ISD::EXTLOAD, Node->getValueType(0),
1143 Result, StackSlot, ExtraVT);
1145 assert(0 && "Unknown op");
1147 Result = LegalizeOp(Result);
1154 if (!Op.Val->hasOneUse())
1155 AddLegalizedOperand(Op, Result);
1160 /// PromoteOp - Given an operation that produces a value in an invalid type,
1161 /// promote it to compute the value into a larger type. The produced value will
1162 /// have the correct bits for the low portion of the register, but no guarantee
1163 /// is made about the top bits: it may be zero, sign-extended, or garbage.
1164 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
1165 MVT::ValueType VT = Op.getValueType();
1166 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
1167 assert(getTypeAction(VT) == Promote &&
1168 "Caller should expand or legalize operands that are not promotable!");
1169 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
1170 "Cannot promote to smaller type!");
1172 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
1173 if (I != PromotedNodes.end()) return I->second;
1175 SDOperand Tmp1, Tmp2, Tmp3;
1178 SDNode *Node = Op.Val;
1180 // Promotion needs an optimization step to clean up after it, and is not
1181 // careful to avoid operations the target does not support. Make sure that
1182 // all generated operations are legalized in the next iteration.
1183 NeedsAnotherIteration = true;
1185 switch (Node->getOpcode()) {
1187 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
1188 assert(0 && "Do not know how to promote this operator!");
1191 Result = DAG.getNode(ISD::UNDEF, NVT);
1194 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
1195 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
1197 case ISD::ConstantFP:
1198 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
1199 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
1201 case ISD::CopyFromReg:
1202 Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(), NVT,
1203 Node->getOperand(0));
1204 // Remember that we legalized the chain.
1205 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1209 assert(getTypeAction(TLI.getSetCCResultTy()) == Legal &&
1210 "SetCC type is not legal??");
1211 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
1212 TLI.getSetCCResultTy(), Node->getOperand(0),
1213 Node->getOperand(1));
1214 Result = LegalizeOp(Result);
1218 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1220 Result = LegalizeOp(Node->getOperand(0));
1221 assert(Result.getValueType() >= NVT &&
1222 "This truncation doesn't make sense!");
1223 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
1224 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
1227 // The truncation is not required, because we don't guarantee anything
1228 // about high bits anyway.
1229 Result = PromoteOp(Node->getOperand(0));
1232 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1233 // Truncate the low part of the expanded value to the result type
1234 Result = DAG.getNode(ISD::TRUNCATE, VT, Tmp1);
1237 case ISD::SIGN_EXTEND:
1238 case ISD::ZERO_EXTEND:
1239 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1240 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
1242 // Input is legal? Just do extend all the way to the larger type.
1243 Result = LegalizeOp(Node->getOperand(0));
1244 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
1247 // Promote the reg if it's smaller.
1248 Result = PromoteOp(Node->getOperand(0));
1249 // The high bits are not guaranteed to be anything. Insert an extend.
1250 if (Node->getOpcode() == ISD::SIGN_EXTEND)
1251 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
1252 Node->getOperand(0).getValueType());
1254 Result = DAG.getZeroExtendInReg(Result,
1255 Node->getOperand(0).getValueType());
1260 case ISD::FP_EXTEND:
1261 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
1263 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1264 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
1265 case Promote: assert(0 && "Unreachable with 2 FP types!");
1267 // Input is legal? Do an FP_ROUND_INREG.
1268 Result = LegalizeOp(Node->getOperand(0));
1269 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT);
1274 case ISD::SINT_TO_FP:
1275 case ISD::UINT_TO_FP:
1276 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1278 Result = LegalizeOp(Node->getOperand(0));
1279 // No extra round required here.
1280 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
1284 Result = PromoteOp(Node->getOperand(0));
1285 if (Node->getOpcode() == ISD::SINT_TO_FP)
1286 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1287 Result, Node->getOperand(0).getValueType());
1289 Result = DAG.getZeroExtendInReg(Result,
1290 Node->getOperand(0).getValueType());
1291 // No extra round required here.
1292 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
1295 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
1296 Node->getOperand(0));
1297 Result = LegalizeOp(Result);
1299 // Round if we cannot tolerate excess precision.
1300 if (NoExcessFPPrecision)
1301 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT);
1306 case ISD::FP_TO_SINT:
1307 case ISD::FP_TO_UINT:
1308 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1310 Tmp1 = LegalizeOp(Node->getOperand(0));
1313 // The input result is prerounded, so we don't have to do anything
1315 Tmp1 = PromoteOp(Node->getOperand(0));
1318 assert(0 && "not implemented");
1320 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
1325 Tmp1 = PromoteOp(Node->getOperand(0));
1326 assert(Tmp1.getValueType() == NVT);
1327 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
1328 // NOTE: we do not have to do any extra rounding here for
1329 // NoExcessFPPrecision, because we know the input will have the appropriate
1330 // precision, and these operations don't modify precision at all.
1339 // The input may have strange things in the top bits of the registers, but
1340 // these operations don't care. They may have wierd bits going out, but
1341 // that too is okay if they are integer operations.
1342 Tmp1 = PromoteOp(Node->getOperand(0));
1343 Tmp2 = PromoteOp(Node->getOperand(1));
1344 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
1345 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
1347 // However, if this is a floating point operation, they will give excess
1348 // precision that we may not be able to tolerate. If we DO allow excess
1349 // precision, just leave it, otherwise excise it.
1350 // FIXME: Why would we need to round FP ops more than integer ones?
1351 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
1352 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
1353 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT);
1358 // These operators require that their input be sign extended.
1359 Tmp1 = PromoteOp(Node->getOperand(0));
1360 Tmp2 = PromoteOp(Node->getOperand(1));
1361 if (MVT::isInteger(NVT)) {
1362 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT);
1363 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, VT);
1365 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
1367 // Perform FP_ROUND: this is probably overly pessimistic.
1368 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
1369 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT);
1374 // These operators require that their input be zero extended.
1375 Tmp1 = PromoteOp(Node->getOperand(0));
1376 Tmp2 = PromoteOp(Node->getOperand(1));
1377 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
1378 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
1379 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
1380 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
1384 Tmp1 = PromoteOp(Node->getOperand(0));
1385 Tmp2 = LegalizeOp(Node->getOperand(1));
1386 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2);
1389 // The input value must be properly sign extended.
1390 Tmp1 = PromoteOp(Node->getOperand(0));
1391 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT);
1392 Tmp2 = LegalizeOp(Node->getOperand(1));
1393 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2);
1396 // The input value must be properly zero extended.
1397 Tmp1 = PromoteOp(Node->getOperand(0));
1398 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
1399 Tmp2 = LegalizeOp(Node->getOperand(1));
1400 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2);
1403 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1404 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1405 // FIXME: When the DAG combiner exists, change this to use EXTLOAD!
1406 if (MVT::isInteger(NVT))
1407 Result = DAG.getNode(ISD::ZEXTLOAD, NVT, Tmp1, Tmp2, VT);
1409 Result = DAG.getNode(ISD::EXTLOAD, NVT, Tmp1, Tmp2, VT);
1411 // Remember that we legalized the chain.
1412 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1415 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1416 case Expand: assert(0 && "It's impossible to expand bools");
1418 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition.
1421 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1424 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
1425 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
1426 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3);
1429 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1430 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
1432 std::vector<SDOperand> Ops;
1433 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i)
1434 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1436 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
1437 "Can only promote single result calls");
1438 std::vector<MVT::ValueType> RetTyVTs;
1439 RetTyVTs.reserve(2);
1440 RetTyVTs.push_back(NVT);
1441 RetTyVTs.push_back(MVT::Other);
1442 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops);
1443 Result = SDOperand(NC, 0);
1445 // Insert the new chain mapping.
1446 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1451 assert(Result.Val && "Didn't set a result!");
1452 AddPromotedOperand(Op, Result);
1456 /// ExpandAddSub - Find a clever way to expand this add operation into
1458 void SelectionDAGLegalize::
1459 ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
1460 SDOperand &Lo, SDOperand &Hi) {
1461 // Expand the subcomponents.
1462 SDOperand LHSL, LHSH, RHSL, RHSH;
1463 ExpandOp(LHS, LHSL, LHSH);
1464 ExpandOp(RHS, RHSL, RHSH);
1466 // FIXME: this should be moved to the dag combiner someday.
1467 if (NodeOp == ISD::ADD_PARTS || NodeOp == ISD::SUB_PARTS)
1468 if (LHSL.getValueType() == MVT::i32) {
1470 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHSL))
1471 if (C->getValue() == 0)
1473 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHSL))
1474 if (C->getValue() == 0)
1477 // Turn this into an add/sub of the high part only.
1479 DAG.getNode(NodeOp == ISD::ADD_PARTS ? ISD::ADD : ISD::SUB,
1480 LowEl.getValueType(), LHSH, RHSH);
1487 std::vector<SDOperand> Ops;
1488 Ops.push_back(LHSL);
1489 Ops.push_back(LHSH);
1490 Ops.push_back(RHSL);
1491 Ops.push_back(RHSH);
1492 Lo = DAG.getNode(NodeOp, LHSL.getValueType(), Ops);
1493 Hi = Lo.getValue(1);
1496 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
1497 SDOperand Op, SDOperand Amt,
1498 SDOperand &Lo, SDOperand &Hi) {
1499 // Expand the subcomponents.
1500 SDOperand LHSL, LHSH;
1501 ExpandOp(Op, LHSL, LHSH);
1503 std::vector<SDOperand> Ops;
1504 Ops.push_back(LHSL);
1505 Ops.push_back(LHSH);
1507 Lo = DAG.getNode(NodeOp, LHSL.getValueType(), Ops);
1508 Hi = Lo.getValue(1);
1512 /// ExpandShift - Try to find a clever way to expand this shift operation out to
1513 /// smaller elements. If we can't find a way that is more efficient than a
1514 /// libcall on this target, return false. Otherwise, return true with the
1515 /// low-parts expanded into Lo and Hi.
1516 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
1517 SDOperand &Lo, SDOperand &Hi) {
1518 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
1519 "This is not a shift!");
1521 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
1522 SDOperand ShAmt = LegalizeOp(Amt);
1523 MVT::ValueType ShTy = ShAmt.getValueType();
1524 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
1525 unsigned NVTBits = MVT::getSizeInBits(NVT);
1527 // Handle the case when Amt is an immediate. Other cases are currently broken
1528 // and are disabled.
1529 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
1530 unsigned Cst = CN->getValue();
1531 // Expand the incoming operand to be shifted, so that we have its parts
1533 ExpandOp(Op, InL, InH);
1537 Lo = DAG.getConstant(0, NVT);
1538 Hi = DAG.getConstant(0, NVT);
1539 } else if (Cst > NVTBits) {
1540 Lo = DAG.getConstant(0, NVT);
1541 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
1542 } else if (Cst == NVTBits) {
1543 Lo = DAG.getConstant(0, NVT);
1546 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
1547 Hi = DAG.getNode(ISD::OR, NVT,
1548 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
1549 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
1554 Lo = DAG.getConstant(0, NVT);
1555 Hi = DAG.getConstant(0, NVT);
1556 } else if (Cst > NVTBits) {
1557 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
1558 Hi = DAG.getConstant(0, NVT);
1559 } else if (Cst == NVTBits) {
1561 Hi = DAG.getConstant(0, NVT);
1563 Lo = DAG.getNode(ISD::OR, NVT,
1564 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
1565 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
1566 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
1571 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
1572 DAG.getConstant(NVTBits-1, ShTy));
1573 } else if (Cst > NVTBits) {
1574 Lo = DAG.getNode(ISD::SRA, NVT, InH,
1575 DAG.getConstant(Cst-NVTBits, ShTy));
1576 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1577 DAG.getConstant(NVTBits-1, ShTy));
1578 } else if (Cst == NVTBits) {
1580 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1581 DAG.getConstant(NVTBits-1, ShTy));
1583 Lo = DAG.getNode(ISD::OR, NVT,
1584 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
1585 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
1586 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
1591 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy,
1592 // so disable it for now. Currently targets are handling this via SHL_PARTS
1596 // If we have an efficient select operation (or if the selects will all fold
1597 // away), lower to some complex code, otherwise just emit the libcall.
1598 if (TLI.getOperationAction(ISD::SELECT, NVT) != TargetLowering::Legal &&
1599 !isa<ConstantSDNode>(Amt))
1603 ExpandOp(Op, InL, InH);
1604 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt
1605 DAG.getConstant(NVTBits, ShTy), ShAmt);
1607 // Compare the unmasked shift amount against 32.
1608 SDOperand Cond = DAG.getSetCC(ISD::SETGE, TLI.getSetCCResultTy(), ShAmt,
1609 DAG.getConstant(NVTBits, ShTy));
1611 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) {
1612 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31
1613 DAG.getConstant(NVTBits-1, ShTy));
1614 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31
1615 DAG.getConstant(NVTBits-1, ShTy));
1618 if (Opc == ISD::SHL) {
1619 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt)
1620 DAG.getNode(ISD::SHL, NVT, InH, ShAmt),
1621 DAG.getNode(ISD::SRL, NVT, InL, NAmt));
1622 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31
1624 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
1625 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2);
1627 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT,
1628 DAG.getSetCC(ISD::SETEQ,
1629 TLI.getSetCCResultTy(), NAmt,
1630 DAG.getConstant(32, ShTy)),
1631 DAG.getConstant(0, NVT),
1632 DAG.getNode(ISD::SHL, NVT, InH, NAmt));
1633 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt)
1635 DAG.getNode(ISD::SRL, NVT, InL, ShAmt));
1636 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31
1639 if (Opc == ISD::SRA)
1640 HiPart = DAG.getNode(ISD::SRA, NVT, InH,
1641 DAG.getConstant(NVTBits-1, ShTy));
1643 HiPart = DAG.getConstant(0, NVT);
1644 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
1645 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2);
1650 /// FindLatestAdjCallStackDown - Scan up the dag to find the latest (highest
1651 /// NodeDepth) node that is an AdjCallStackDown operation and occurs later than
1653 static void FindLatestAdjCallStackDown(SDNode *Node, SDNode *&Found) {
1654 if (Node->getNodeDepth() <= Found->getNodeDepth()) return;
1656 // If we found an ADJCALLSTACKDOWN, we already know this node occurs later
1657 // than the Found node. Just remember this node and return.
1658 if (Node->getOpcode() == ISD::ADJCALLSTACKDOWN) {
1663 // Otherwise, scan the operands of Node to see if any of them is a call.
1664 assert(Node->getNumOperands() != 0 &&
1665 "All leaves should have depth equal to the entry node!");
1666 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i)
1667 FindLatestAdjCallStackDown(Node->getOperand(i).Val, Found);
1669 // Tail recurse for the last iteration.
1670 FindLatestAdjCallStackDown(Node->getOperand(Node->getNumOperands()-1).Val,
1675 /// FindEarliestAdjCallStackUp - Scan down the dag to find the earliest (lowest
1676 /// NodeDepth) node that is an AdjCallStackUp operation and occurs more recent
1678 static void FindEarliestAdjCallStackUp(SDNode *Node, SDNode *&Found) {
1679 if (Found && Node->getNodeDepth() >= Found->getNodeDepth()) return;
1681 // If we found an ADJCALLSTACKUP, we already know this node occurs earlier
1682 // than the Found node. Just remember this node and return.
1683 if (Node->getOpcode() == ISD::ADJCALLSTACKUP) {
1688 // Otherwise, scan the operands of Node to see if any of them is a call.
1689 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
1690 if (UI == E) return;
1691 for (--E; UI != E; ++UI)
1692 FindEarliestAdjCallStackUp(*UI, Found);
1694 // Tail recurse for the last iteration.
1695 FindEarliestAdjCallStackUp(*UI, Found);
1698 /// FindAdjCallStackUp - Given a chained node that is part of a call sequence,
1699 /// find the ADJCALLSTACKUP node that terminates the call sequence.
1700 static SDNode *FindAdjCallStackUp(SDNode *Node) {
1701 if (Node->getOpcode() == ISD::ADJCALLSTACKUP)
1703 if (Node->use_empty())
1704 return 0; // No adjcallstackup
1706 if (Node->hasOneUse()) // Simple case, only has one user to check.
1707 return FindAdjCallStackUp(*Node->use_begin());
1709 SDOperand TheChain(Node, Node->getNumValues()-1);
1710 assert(TheChain.getValueType() == MVT::Other && "Is not a token chain!");
1712 for (SDNode::use_iterator UI = Node->use_begin(),
1713 E = Node->use_end(); ; ++UI) {
1714 assert(UI != E && "Didn't find a user of the tokchain, no ADJCALLSTACKUP!");
1716 // Make sure to only follow users of our token chain.
1718 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
1719 if (User->getOperand(i) == TheChain)
1720 return FindAdjCallStackUp(User);
1722 assert(0 && "Unreachable");
1726 /// FindInputOutputChains - If we are replacing an operation with a call we need
1727 /// to find the call that occurs before and the call that occurs after it to
1728 /// properly serialize the calls in the block.
1729 static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain,
1731 SDNode *LatestAdjCallStackDown = Entry.Val;
1732 SDNode *LatestAdjCallStackUp = 0;
1733 FindLatestAdjCallStackDown(OpNode, LatestAdjCallStackDown);
1734 //std::cerr << "Found node: "; LatestAdjCallStackDown->dump(); std::cerr <<"\n";
1736 // It is possible that no ISD::ADJCALLSTACKDOWN was found because there is no
1737 // previous call in the function. LatestCallStackDown may in that case be
1738 // the entry node itself. Do not attempt to find a matching ADJCALLSTACKUP
1739 // unless LatestCallStackDown is an ADJCALLSTACKDOWN.
1740 if (LatestAdjCallStackDown->getOpcode() == ISD::ADJCALLSTACKDOWN)
1741 LatestAdjCallStackUp = FindAdjCallStackUp(LatestAdjCallStackDown);
1743 LatestAdjCallStackUp = Entry.Val;
1744 assert(LatestAdjCallStackUp && "NULL return from FindAdjCallStackUp");
1746 SDNode *EarliestAdjCallStackUp = 0;
1747 FindEarliestAdjCallStackUp(OpNode, EarliestAdjCallStackUp);
1749 if (EarliestAdjCallStackUp) {
1750 //std::cerr << "Found node: ";
1751 //EarliestAdjCallStackUp->dump(); std::cerr <<"\n";
1754 return SDOperand(LatestAdjCallStackUp, 0);
1759 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1760 // does not fit into a register, return the lo part and set the hi part to the
1761 // by-reg argument. If it does fit into a single register, return the result
1762 // and leave the Hi part unset.
1763 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
1766 SDOperand InChain = FindInputOutputChains(Node, OutChain,
1767 DAG.getEntryNode());
1768 if (InChain.Val == 0)
1769 InChain = DAG.getEntryNode();
1771 TargetLowering::ArgListTy Args;
1772 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1773 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
1774 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
1775 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
1777 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
1779 // We don't care about token chains for libcalls. We just use the entry
1780 // node as our input and ignore the output chain. This allows us to place
1781 // calls wherever we need them to satisfy data dependences.
1782 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
1783 SDOperand Result = TLI.LowerCallTo(InChain, RetTy, false, Callee,
1785 switch (getTypeAction(Result.getValueType())) {
1786 default: assert(0 && "Unknown thing");
1790 assert(0 && "Cannot promote this yet!");
1793 ExpandOp(Result, Lo, Hi);
1799 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
1800 /// destination type is legal.
1801 SDOperand SelectionDAGLegalize::
1802 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
1803 assert(getTypeAction(DestTy) == Legal && "Destination type is not legal!");
1804 assert(getTypeAction(Source.getValueType()) == Expand &&
1805 "This is not an expansion!");
1806 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
1809 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain,
1810 DAG.getEntryNode());
1812 const char *FnName = 0;
1814 if (DestTy == MVT::f32)
1815 FnName = "__floatdisf";
1817 assert(DestTy == MVT::f64 && "Unknown fp value type!");
1818 FnName = "__floatdidf";
1821 // If this is unsigned, and not supported, first perform the conversion to
1822 // signed, then adjust the result if the sign bit is set.
1823 SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source);
1825 assert(Source.getValueType() == MVT::i64 &&
1826 "This only works for 64-bit -> FP");
1827 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
1828 // incoming integer is set. To handle this, we dynamically test to see if
1829 // it is set, and, if so, add a fudge factor.
1831 ExpandOp(Source, Lo, Hi);
1833 SDOperand SignSet = DAG.getSetCC(ISD::SETLT, TLI.getSetCCResultTy(), Hi,
1834 DAG.getConstant(0, Hi.getValueType()));
1835 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
1836 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
1837 SignSet, Four, Zero);
1838 // FIXME: This is almost certainly broken for big-endian systems. Should
1839 // this just put the fudge factor in the low bits of the uint64 constant or?
1840 static Constant *FudgeFactor =
1841 ConstantUInt::get(Type::ULongTy, 0x5f800000ULL << 32);
1843 MachineConstantPool *CP = DAG.getMachineFunction().getConstantPool();
1844 SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(FudgeFactor),
1845 TLI.getPointerTy());
1846 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
1847 SDOperand FudgeInReg;
1848 if (DestTy == MVT::f32)
1849 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx);
1851 assert(DestTy == MVT::f64 && "Unexpected conversion");
1852 FudgeInReg = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
1855 return DAG.getNode(ISD::ADD, DestTy, SignedConv, FudgeInReg);
1857 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy());
1859 TargetLowering::ArgListTy Args;
1860 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType());
1861 Args.push_back(std::make_pair(Source, ArgTy));
1863 // We don't care about token chains for libcalls. We just use the entry
1864 // node as our input and ignore the output chain. This allows us to place
1865 // calls wherever we need them to satisfy data dependences.
1866 const Type *RetTy = MVT::getTypeForValueType(DestTy);
1867 return TLI.LowerCallTo(InChain, RetTy, false, Callee, Args, DAG).first;
1872 /// ExpandOp - Expand the specified SDOperand into its two component pieces
1873 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
1874 /// LegalizeNodes map is filled in for any results that are not expanded, the
1875 /// ExpandedNodes map is filled in for any results that are expanded, and the
1876 /// Lo/Hi values are returned.
1877 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
1878 MVT::ValueType VT = Op.getValueType();
1879 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
1880 SDNode *Node = Op.Val;
1881 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
1882 assert(MVT::isInteger(VT) && "Cannot expand FP values!");
1883 assert(MVT::isInteger(NVT) && NVT < VT &&
1884 "Cannot expand to FP value or to larger int value!");
1886 // If there is more than one use of this, see if we already expanded it.
1887 // There is no use remembering values that only have a single use, as the map
1888 // entries will never be reused.
1889 if (!Node->hasOneUse()) {
1890 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
1891 = ExpandedNodes.find(Op);
1892 if (I != ExpandedNodes.end()) {
1893 Lo = I->second.first;
1894 Hi = I->second.second;
1899 // Expanding to multiple registers needs to perform an optimization step, and
1900 // is not careful to avoid operations the target does not support. Make sure
1901 // that all generated operations are legalized in the next iteration.
1902 NeedsAnotherIteration = true;
1904 switch (Node->getOpcode()) {
1906 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
1907 assert(0 && "Do not know how to expand this operator!");
1910 Lo = DAG.getNode(ISD::UNDEF, NVT);
1911 Hi = DAG.getNode(ISD::UNDEF, NVT);
1913 case ISD::Constant: {
1914 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
1915 Lo = DAG.getConstant(Cst, NVT);
1916 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
1920 case ISD::CopyFromReg: {
1921 unsigned Reg = cast<RegSDNode>(Node)->getReg();
1922 // Aggregate register values are always in consequtive pairs.
1923 Lo = DAG.getCopyFromReg(Reg, NVT, Node->getOperand(0));
1924 Hi = DAG.getCopyFromReg(Reg+1, NVT, Lo.getValue(1));
1926 // Remember that we legalized the chain.
1927 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
1929 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
1933 case ISD::BUILD_PAIR:
1934 // Legalize both operands. FIXME: in the future we should handle the case
1935 // where the two elements are not legal.
1936 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
1937 Lo = LegalizeOp(Node->getOperand(0));
1938 Hi = LegalizeOp(Node->getOperand(1));
1942 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1943 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1944 Lo = DAG.getLoad(NVT, Ch, Ptr);
1946 // Increment the pointer to the other half.
1947 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
1948 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1949 getIntPtrConstant(IncrementSize));
1950 Hi = DAG.getLoad(NVT, Ch, Ptr);
1952 // Build a factor node to remember that this load is independent of the
1954 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1957 // Remember that we legalized the chain.
1958 AddLegalizedOperand(Op.getValue(1), TF);
1959 if (!TLI.isLittleEndian())
1964 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1965 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
1967 bool Changed = false;
1968 std::vector<SDOperand> Ops;
1969 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
1970 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1971 Changed |= Ops.back() != Node->getOperand(i);
1974 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
1975 "Can only expand a call once so far, not i64 -> i16!");
1977 std::vector<MVT::ValueType> RetTyVTs;
1978 RetTyVTs.reserve(3);
1979 RetTyVTs.push_back(NVT);
1980 RetTyVTs.push_back(NVT);
1981 RetTyVTs.push_back(MVT::Other);
1982 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops);
1983 Lo = SDOperand(NC, 0);
1984 Hi = SDOperand(NC, 1);
1986 // Insert the new chain mapping.
1987 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2));
1992 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
1993 SDOperand LL, LH, RL, RH;
1994 ExpandOp(Node->getOperand(0), LL, LH);
1995 ExpandOp(Node->getOperand(1), RL, RH);
1996 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
1997 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
2001 SDOperand C, LL, LH, RL, RH;
2003 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2004 case Expand: assert(0 && "It's impossible to expand bools");
2006 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2009 C = PromoteOp(Node->getOperand(0)); // Promote the condition.
2012 ExpandOp(Node->getOperand(1), LL, LH);
2013 ExpandOp(Node->getOperand(2), RL, RH);
2014 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL);
2015 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH);
2018 case ISD::SIGN_EXTEND: {
2020 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2021 case Expand: assert(0 && "expand-expand not implemented yet!");
2022 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
2024 In = PromoteOp(Node->getOperand(0));
2025 // Emit the appropriate sign_extend_inreg to get the value we want.
2026 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In,
2027 Node->getOperand(0).getValueType());
2031 // The low part is just a sign extension of the input (which degenerates to
2033 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In);
2035 // The high part is obtained by SRA'ing all but one of the bits of the lo
2037 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
2038 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
2039 TLI.getShiftAmountTy()));
2042 case ISD::ZERO_EXTEND: {
2044 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2045 case Expand: assert(0 && "expand-expand not implemented yet!");
2046 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
2048 In = PromoteOp(Node->getOperand(0));
2049 // Emit the appropriate zero_extend_inreg to get the value we want.
2050 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType());
2054 // The low part is just a zero extension of the input (which degenerates to
2056 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In);
2058 // The high part is just a zero.
2059 Hi = DAG.getConstant(0, NVT);
2062 // These operators cannot be expanded directly, emit them as calls to
2063 // library functions.
2064 case ISD::FP_TO_SINT:
2065 if (Node->getOperand(0).getValueType() == MVT::f32)
2066 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
2068 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
2070 case ISD::FP_TO_UINT:
2071 if (Node->getOperand(0).getValueType() == MVT::f32)
2072 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
2074 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
2078 // If we can emit an efficient shift operation, do so now.
2079 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
2082 // If this target supports SHL_PARTS, use it.
2083 if (TLI.getOperationAction(ISD::SHL_PARTS, NVT) == TargetLowering::Legal) {
2084 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1),
2089 // Otherwise, emit a libcall.
2090 Lo = ExpandLibCall("__ashldi3", Node, Hi);
2094 // If we can emit an efficient shift operation, do so now.
2095 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
2098 // If this target supports SRA_PARTS, use it.
2099 if (TLI.getOperationAction(ISD::SRA_PARTS, NVT) == TargetLowering::Legal) {
2100 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1),
2105 // Otherwise, emit a libcall.
2106 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
2109 // If we can emit an efficient shift operation, do so now.
2110 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
2113 // If this target supports SRL_PARTS, use it.
2114 if (TLI.getOperationAction(ISD::SRL_PARTS, NVT) == TargetLowering::Legal) {
2115 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1),
2120 // Otherwise, emit a libcall.
2121 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
2125 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1),
2129 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1),
2133 if (TLI.getOperationAction(ISD::MULHU, NVT) == TargetLowering::Legal) {
2134 SDOperand LL, LH, RL, RH;
2135 ExpandOp(Node->getOperand(0), LL, LH);
2136 ExpandOp(Node->getOperand(1), RL, RH);
2137 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
2138 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
2139 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
2140 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
2141 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
2142 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
2144 Lo = ExpandLibCall("__muldi3" , Node, Hi); break;
2148 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
2149 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
2150 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
2151 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
2154 // Remember in a map if the values will be reused later.
2155 if (!Node->hasOneUse()) {
2156 bool isNew = ExpandedNodes.insert(std::make_pair(Op,
2157 std::make_pair(Lo, Hi))).second;
2158 assert(isNew && "Value already expanded?!?");
2163 // SelectionDAG::Legalize - This is the entry point for the file.
2165 void SelectionDAG::Legalize() {
2166 /// run - This is the main entry point to this class.
2168 SelectionDAGLegalize(*this).Run();