1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Target/TargetLowering.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Compiler.h"
25 #include "llvm/ADT/SmallVector.h"
32 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
33 cl::desc("Pop up a window to show dags before legalize"));
35 static const bool ViewLegalizeDAGs = 0;
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class VISIBILITY_HIDDEN SelectionDAGLegalize {
55 // Libcall insertion helpers.
57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
58 /// legalized. We use this to ensure that calls are properly serialized
59 /// against each other, including inserted libcalls.
60 SDOperand LastCALLSEQ_END;
62 /// IsLegalizingCall - This member is used *only* for purposes of providing
63 /// helpful assertions that a libcall isn't created while another call is
64 /// being legalized (which could lead to non-serialized call sequences).
65 bool IsLegalizingCall;
68 Legal, // The target natively supports this operation.
69 Promote, // This operation should be executed in a larger type.
70 Expand // Try to expand this to other ops, otherwise use a libcall.
73 /// ValueTypeActions - This is a bitvector that contains two bits for each
74 /// value type, where the two bits correspond to the LegalizeAction enum.
75 /// This can be queried with "getTypeAction(VT)".
76 TargetLowering::ValueTypeActionImpl ValueTypeActions;
78 /// LegalizedNodes - For nodes that are of legal width, and that have more
79 /// than one use, this map indicates what regularized operand to use. This
80 /// allows us to avoid legalizing the same thing more than once.
81 std::map<SDOperand, SDOperand> LegalizedNodes;
83 /// PromotedNodes - For nodes that are below legal width, and that have more
84 /// than one use, this map indicates what promoted value to use. This allows
85 /// us to avoid promoting the same thing more than once.
86 std::map<SDOperand, SDOperand> PromotedNodes;
88 /// ExpandedNodes - For nodes that need to be expanded this map indicates
89 /// which which operands are the expanded version of the input. This allows
90 /// us to avoid expanding the same node more than once.
91 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
93 /// SplitNodes - For vector nodes that need to be split, this map indicates
94 /// which which operands are the split version of the input. This allows us
95 /// to avoid splitting the same node more than once.
96 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
98 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
99 /// concrete packed types, this contains the mapping of ones we have already
100 /// processed to the result.
101 std::map<SDOperand, SDOperand> PackedNodes;
103 void AddLegalizedOperand(SDOperand From, SDOperand To) {
104 LegalizedNodes.insert(std::make_pair(From, To));
105 // If someone requests legalization of the new node, return itself.
107 LegalizedNodes.insert(std::make_pair(To, To));
109 void AddPromotedOperand(SDOperand From, SDOperand To) {
110 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
111 assert(isNew && "Got into the map somehow?");
112 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
118 SelectionDAGLegalize(SelectionDAG &DAG);
120 /// getTypeAction - Return how we should legalize values of this type, either
121 /// it is already legal or we need to expand it into multiple registers of
122 /// smaller integer type, or we need to promote it to a larger type.
123 LegalizeAction getTypeAction(MVT::ValueType VT) const {
124 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
127 /// isTypeLegal - Return true if this type is legal on this target.
129 bool isTypeLegal(MVT::ValueType VT) const {
130 return getTypeAction(VT) == Legal;
136 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
137 /// appropriate for its type.
138 void HandleOp(SDOperand Op);
140 /// LegalizeOp - We know that the specified value has a legal type.
141 /// Recursively ensure that the operands have legal types, then return the
143 SDOperand LegalizeOp(SDOperand O);
145 /// PromoteOp - Given an operation that produces a value in an invalid type,
146 /// promote it to compute the value into a larger type. The produced value
147 /// will have the correct bits for the low portion of the register, but no
148 /// guarantee is made about the top bits: it may be zero, sign-extended, or
150 SDOperand PromoteOp(SDOperand O);
152 /// ExpandOp - Expand the specified SDOperand into its two component pieces
153 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
154 /// the LegalizeNodes map is filled in for any results that are not expanded,
155 /// the ExpandedNodes map is filled in for any results that are expanded, and
156 /// the Lo/Hi values are returned. This applies to integer types and Vector
158 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
160 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
161 /// two smaller values of MVT::Vector type.
162 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
164 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
165 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
166 /// this is called, we know that PackedVT is the right type for the result and
167 /// we know that this type is legal for the target.
168 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
170 /// isShuffleLegal - Return true if a vector shuffle is legal with the
171 /// specified mask and type. Targets can specify exactly which masks they
172 /// support and the code generator is tasked with not creating illegal masks.
174 /// Note that this will also return true for shuffles that are promoted to a
177 /// If this is a legal shuffle, this method returns the (possibly promoted)
178 /// build_vector Mask. If it's not a legal shuffle, it returns null.
179 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
181 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
182 std::set<SDNode*> &NodesLeadingTo);
184 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
186 SDOperand CreateStackTemporary(MVT::ValueType VT);
188 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
190 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
193 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
194 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
195 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
196 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
198 MVT::ValueType DestVT);
199 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
201 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
204 SDOperand ExpandBSWAP(SDOperand Op);
205 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
206 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
207 SDOperand &Lo, SDOperand &Hi);
208 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
209 SDOperand &Lo, SDOperand &Hi);
211 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
212 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
214 SDOperand getIntPtrConstant(uint64_t Val) {
215 return DAG.getConstant(Val, TLI.getPointerTy());
220 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
221 /// specified mask and type. Targets can specify exactly which masks they
222 /// support and the code generator is tasked with not creating illegal masks.
224 /// Note that this will also return true for shuffles that are promoted to a
226 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
227 SDOperand Mask) const {
228 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
230 case TargetLowering::Legal:
231 case TargetLowering::Custom:
233 case TargetLowering::Promote: {
234 // If this is promoted to a different type, convert the shuffle mask and
235 // ask if it is legal in the promoted type!
236 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
238 // If we changed # elements, change the shuffle mask.
239 unsigned NumEltsGrowth =
240 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
241 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
242 if (NumEltsGrowth > 1) {
243 // Renumber the elements.
244 SmallVector<SDOperand, 8> Ops;
245 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
246 SDOperand InOp = Mask.getOperand(i);
247 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
248 if (InOp.getOpcode() == ISD::UNDEF)
249 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
251 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
252 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
256 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
262 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
265 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
266 /// specified vector opcode.
267 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
269 default: assert(0 && "Don't know how to scalarize this opcode!");
270 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
271 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
272 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
273 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
274 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
275 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
276 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
277 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
281 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
282 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
283 ValueTypeActions(TLI.getValueTypeActions()) {
284 assert(MVT::LAST_VALUETYPE <= 32 &&
285 "Too many value types for ValueTypeActions to hold!");
288 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
289 /// not been visited yet and if all of its operands have already been visited.
290 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
291 std::map<SDNode*, unsigned> &Visited) {
292 if (++Visited[N] != N->getNumOperands())
293 return; // Haven't visited all operands yet
297 if (N->hasOneUse()) { // Tail recurse in common case.
298 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
302 // Now that we have N in, add anything that uses it if all of their operands
304 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
305 ComputeTopDownOrdering(*UI, Order, Visited);
309 void SelectionDAGLegalize::LegalizeDAG() {
310 LastCALLSEQ_END = DAG.getEntryNode();
311 IsLegalizingCall = false;
313 // The legalize process is inherently a bottom-up recursive process (users
314 // legalize their uses before themselves). Given infinite stack space, we
315 // could just start legalizing on the root and traverse the whole graph. In
316 // practice however, this causes us to run out of stack space on large basic
317 // blocks. To avoid this problem, compute an ordering of the nodes where each
318 // node is only legalized after all of its operands are legalized.
319 std::map<SDNode*, unsigned> Visited;
320 std::vector<SDNode*> Order;
322 // Compute ordering from all of the leaves in the graphs, those (like the
323 // entry node) that have no operands.
324 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
325 E = DAG.allnodes_end(); I != E; ++I) {
326 if (I->getNumOperands() == 0) {
328 ComputeTopDownOrdering(I, Order, Visited);
332 assert(Order.size() == Visited.size() &&
334 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
335 "Error: DAG is cyclic!");
338 for (unsigned i = 0, e = Order.size(); i != e; ++i)
339 HandleOp(SDOperand(Order[i], 0));
341 // Finally, it's possible the root changed. Get the new root.
342 SDOperand OldRoot = DAG.getRoot();
343 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
344 DAG.setRoot(LegalizedNodes[OldRoot]);
346 ExpandedNodes.clear();
347 LegalizedNodes.clear();
348 PromotedNodes.clear();
352 // Remove dead nodes now.
353 DAG.RemoveDeadNodes();
357 /// FindCallEndFromCallStart - Given a chained node that is part of a call
358 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
359 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
360 if (Node->getOpcode() == ISD::CALLSEQ_END)
362 if (Node->use_empty())
363 return 0; // No CallSeqEnd
365 // The chain is usually at the end.
366 SDOperand TheChain(Node, Node->getNumValues()-1);
367 if (TheChain.getValueType() != MVT::Other) {
368 // Sometimes it's at the beginning.
369 TheChain = SDOperand(Node, 0);
370 if (TheChain.getValueType() != MVT::Other) {
371 // Otherwise, hunt for it.
372 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
373 if (Node->getValueType(i) == MVT::Other) {
374 TheChain = SDOperand(Node, i);
378 // Otherwise, we walked into a node without a chain.
379 if (TheChain.getValueType() != MVT::Other)
384 for (SDNode::use_iterator UI = Node->use_begin(),
385 E = Node->use_end(); UI != E; ++UI) {
387 // Make sure to only follow users of our token chain.
389 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
390 if (User->getOperand(i) == TheChain)
391 if (SDNode *Result = FindCallEndFromCallStart(User))
397 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
398 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
399 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
400 assert(Node && "Didn't find callseq_start for a call??");
401 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
403 assert(Node->getOperand(0).getValueType() == MVT::Other &&
404 "Node doesn't have a token chain argument!");
405 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
408 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
409 /// see if any uses can reach Dest. If no dest operands can get to dest,
410 /// legalize them, legalize ourself, and return false, otherwise, return true.
412 /// Keep track of the nodes we fine that actually do lead to Dest in
413 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
415 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
416 std::set<SDNode*> &NodesLeadingTo) {
417 if (N == Dest) return true; // N certainly leads to Dest :)
419 // If we've already processed this node and it does lead to Dest, there is no
420 // need to reprocess it.
421 if (NodesLeadingTo.count(N)) return true;
423 // If the first result of this node has been already legalized, then it cannot
425 switch (getTypeAction(N->getValueType(0))) {
427 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
430 if (PromotedNodes.count(SDOperand(N, 0))) return false;
433 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
437 // Okay, this node has not already been legalized. Check and legalize all
438 // operands. If none lead to Dest, then we can legalize this node.
439 bool OperandsLeadToDest = false;
440 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
441 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
442 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
444 if (OperandsLeadToDest) {
445 NodesLeadingTo.insert(N);
449 // Okay, this node looks safe, legalize it and return false.
450 HandleOp(SDOperand(N, 0));
454 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
455 /// appropriate for its type.
456 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
457 switch (getTypeAction(Op.getValueType())) {
458 default: assert(0 && "Bad type action!");
459 case Legal: LegalizeOp(Op); break;
460 case Promote: PromoteOp(Op); break;
462 if (Op.getValueType() != MVT::Vector) {
467 unsigned NumOps = N->getNumOperands();
468 unsigned NumElements =
469 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
470 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
471 MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
472 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
473 // In the common case, this is a legal vector type, convert it to the
474 // packed operation and type now.
475 PackVectorOp(Op, PackedVT);
476 } else if (NumElements == 1) {
477 // Otherwise, if this is a single element vector, convert it to a
479 PackVectorOp(Op, EVT);
481 // Otherwise, this is a multiple element vector that isn't supported.
482 // Split it in half and legalize both parts.
484 SplitVectorOp(Op, X, Y);
492 /// LegalizeOp - We know that the specified value has a legal type.
493 /// Recursively ensure that the operands have legal types, then return the
495 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
496 assert(isTypeLegal(Op.getValueType()) &&
497 "Caller should expand or promote operands that are not legal!");
498 SDNode *Node = Op.Val;
500 // If this operation defines any values that cannot be represented in a
501 // register on this target, make sure to expand or promote them.
502 if (Node->getNumValues() > 1) {
503 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
504 if (getTypeAction(Node->getValueType(i)) != Legal) {
505 HandleOp(Op.getValue(i));
506 assert(LegalizedNodes.count(Op) &&
507 "Handling didn't add legal operands!");
508 return LegalizedNodes[Op];
512 // Note that LegalizeOp may be reentered even from single-use nodes, which
513 // means that we always must cache transformed nodes.
514 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
515 if (I != LegalizedNodes.end()) return I->second;
517 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
518 SDOperand Result = Op;
519 bool isCustom = false;
521 switch (Node->getOpcode()) {
522 case ISD::FrameIndex:
523 case ISD::EntryToken:
525 case ISD::BasicBlock:
526 case ISD::TargetFrameIndex:
527 case ISD::TargetJumpTable:
528 case ISD::TargetConstant:
529 case ISD::TargetConstantFP:
530 case ISD::TargetConstantPool:
531 case ISD::TargetGlobalAddress:
532 case ISD::TargetExternalSymbol:
537 // Primitives must all be legal.
538 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
539 "This must be legal!");
542 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
543 // If this is a target node, legalize it by legalizing the operands then
544 // passing it through.
545 SmallVector<SDOperand, 8> Ops;
546 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
547 Ops.push_back(LegalizeOp(Node->getOperand(i)));
549 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
551 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
552 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
553 return Result.getValue(Op.ResNo);
555 // Otherwise this is an unhandled builtin node. splat.
557 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
559 assert(0 && "Do not know how to legalize this operator!");
561 case ISD::JumpTableRelocBase:
562 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
563 case TargetLowering::Custom:
564 Tmp1 = TLI.LowerOperation(Op, DAG);
565 if (Tmp1.Val) Result = Tmp1;
568 Result = LegalizeOp(Node->getOperand(0));
572 case ISD::GlobalAddress:
573 case ISD::ExternalSymbol:
574 case ISD::ConstantPool:
575 case ISD::JumpTable: // Nothing to do.
576 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
577 default: assert(0 && "This action is not supported yet!");
578 case TargetLowering::Custom:
579 Tmp1 = TLI.LowerOperation(Op, DAG);
580 if (Tmp1.Val) Result = Tmp1;
581 // FALLTHROUGH if the target doesn't want to lower this op after all.
582 case TargetLowering::Legal:
586 case ISD::AssertSext:
587 case ISD::AssertZext:
588 Tmp1 = LegalizeOp(Node->getOperand(0));
589 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
591 case ISD::MERGE_VALUES:
592 // Legalize eliminates MERGE_VALUES nodes.
593 Result = Node->getOperand(Op.ResNo);
595 case ISD::CopyFromReg:
596 Tmp1 = LegalizeOp(Node->getOperand(0));
597 Result = Op.getValue(0);
598 if (Node->getNumValues() == 2) {
599 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
601 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
602 if (Node->getNumOperands() == 3) {
603 Tmp2 = LegalizeOp(Node->getOperand(2));
604 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
606 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
608 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
610 // Since CopyFromReg produces two values, make sure to remember that we
611 // legalized both of them.
612 AddLegalizedOperand(Op.getValue(0), Result);
613 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
614 return Result.getValue(Op.ResNo);
616 MVT::ValueType VT = Op.getValueType();
617 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
618 default: assert(0 && "This action is not supported yet!");
619 case TargetLowering::Expand:
620 if (MVT::isInteger(VT))
621 Result = DAG.getConstant(0, VT);
622 else if (MVT::isFloatingPoint(VT))
623 Result = DAG.getConstantFP(0, VT);
625 assert(0 && "Unknown value type!");
627 case TargetLowering::Legal:
633 case ISD::INTRINSIC_W_CHAIN:
634 case ISD::INTRINSIC_WO_CHAIN:
635 case ISD::INTRINSIC_VOID: {
636 SmallVector<SDOperand, 8> Ops;
637 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
638 Ops.push_back(LegalizeOp(Node->getOperand(i)));
639 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
641 // Allow the target to custom lower its intrinsics if it wants to.
642 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
643 TargetLowering::Custom) {
644 Tmp3 = TLI.LowerOperation(Result, DAG);
645 if (Tmp3.Val) Result = Tmp3;
648 if (Result.Val->getNumValues() == 1) break;
650 // Must have return value and chain result.
651 assert(Result.Val->getNumValues() == 2 &&
652 "Cannot return more than two values!");
654 // Since loads produce two values, make sure to remember that we
655 // legalized both of them.
656 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
657 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
658 return Result.getValue(Op.ResNo);
662 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
663 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
665 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
666 case TargetLowering::Promote:
667 default: assert(0 && "This action is not supported yet!");
668 case TargetLowering::Expand: {
669 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
670 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
671 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
673 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
674 const std::string &FName =
675 cast<StringSDNode>(Node->getOperand(3))->getValue();
676 const std::string &DirName =
677 cast<StringSDNode>(Node->getOperand(4))->getValue();
678 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
680 SmallVector<SDOperand, 8> Ops;
681 Ops.push_back(Tmp1); // chain
682 SDOperand LineOp = Node->getOperand(1);
683 SDOperand ColOp = Node->getOperand(2);
686 Ops.push_back(LineOp); // line #
687 Ops.push_back(ColOp); // col #
688 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
689 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
691 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
692 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
693 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
694 Ops.push_back(DAG.getConstant(ID, MVT::i32));
695 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,&Ops[0],Ops.size());
698 Result = Tmp1; // chain
702 case TargetLowering::Legal:
703 if (Tmp1 != Node->getOperand(0) ||
704 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
705 SmallVector<SDOperand, 8> Ops;
707 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
708 Ops.push_back(Node->getOperand(1)); // line # must be legal.
709 Ops.push_back(Node->getOperand(2)); // col # must be legal.
711 // Otherwise promote them.
712 Ops.push_back(PromoteOp(Node->getOperand(1)));
713 Ops.push_back(PromoteOp(Node->getOperand(2)));
715 Ops.push_back(Node->getOperand(3)); // filename must be legal.
716 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
717 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
724 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
725 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
726 default: assert(0 && "This action is not supported yet!");
727 case TargetLowering::Legal:
728 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
729 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
730 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
731 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
732 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
737 case ISD::DEBUG_LABEL:
738 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
739 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
740 default: assert(0 && "This action is not supported yet!");
741 case TargetLowering::Legal:
742 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
743 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
744 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
750 // We know we don't need to expand constants here, constants only have one
751 // value and we check that it is fine above.
753 // FIXME: Maybe we should handle things like targets that don't support full
754 // 32-bit immediates?
756 case ISD::ConstantFP: {
757 // Spill FP immediates to the constant pool if the target cannot directly
758 // codegen them. Targets often have some immediate values that can be
759 // efficiently generated into an FP register without a load. We explicitly
760 // leave these constants as ConstantFP nodes for the target to deal with.
761 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
763 // Check to see if this FP immediate is already legal.
764 bool isLegal = false;
765 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
766 E = TLI.legal_fpimm_end(); I != E; ++I)
767 if (CFP->isExactlyValue(*I)) {
772 // If this is a legal constant, turn it into a TargetConstantFP node.
774 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
778 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
779 default: assert(0 && "This action is not supported yet!");
780 case TargetLowering::Custom:
781 Tmp3 = TLI.LowerOperation(Result, DAG);
787 case TargetLowering::Expand:
788 // Otherwise we need to spill the constant to memory.
791 // If a FP immediate is precise when represented as a float and if the
792 // target can do an extending load from float to double, we put it into
793 // the constant pool as a float, even if it's is statically typed as a
795 MVT::ValueType VT = CFP->getValueType(0);
796 bool isDouble = VT == MVT::f64;
797 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
798 Type::FloatTy, CFP->getValue());
799 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
800 // Only do this if the target has a native EXTLOAD instruction from
802 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
803 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
808 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
810 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
811 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
813 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
814 DAG.getSrcValue(NULL));
819 case ISD::TokenFactor:
820 if (Node->getNumOperands() == 2) {
821 Tmp1 = LegalizeOp(Node->getOperand(0));
822 Tmp2 = LegalizeOp(Node->getOperand(1));
823 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
824 } else if (Node->getNumOperands() == 3) {
825 Tmp1 = LegalizeOp(Node->getOperand(0));
826 Tmp2 = LegalizeOp(Node->getOperand(1));
827 Tmp3 = LegalizeOp(Node->getOperand(2));
828 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
830 SmallVector<SDOperand, 8> Ops;
831 // Legalize the operands.
832 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
833 Ops.push_back(LegalizeOp(Node->getOperand(i)));
834 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
838 case ISD::FORMAL_ARGUMENTS:
840 // The only option for this is to custom lower it.
841 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
842 assert(Tmp3.Val && "Target didn't custom lower this node!");
843 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
844 "Lowering call/formal_arguments produced unexpected # results!");
846 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
847 // remember that we legalized all of them, so it doesn't get relegalized.
848 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
849 Tmp1 = LegalizeOp(Tmp3.getValue(i));
852 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
856 case ISD::BUILD_VECTOR:
857 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
858 default: assert(0 && "This action is not supported yet!");
859 case TargetLowering::Custom:
860 Tmp3 = TLI.LowerOperation(Result, DAG);
866 case TargetLowering::Expand:
867 Result = ExpandBUILD_VECTOR(Result.Val);
871 case ISD::INSERT_VECTOR_ELT:
872 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
873 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
874 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
875 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
877 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
878 Node->getValueType(0))) {
879 default: assert(0 && "This action is not supported yet!");
880 case TargetLowering::Legal:
882 case TargetLowering::Custom:
883 Tmp3 = TLI.LowerOperation(Result, DAG);
889 case TargetLowering::Expand: {
890 // If the insert index is a constant, codegen this as a scalar_to_vector,
891 // then a shuffle that inserts it into the right position in the vector.
892 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
893 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
894 Tmp1.getValueType(), Tmp2);
896 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
897 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
898 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT);
900 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
901 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
903 SmallVector<SDOperand, 8> ShufOps;
904 for (unsigned i = 0; i != NumElts; ++i) {
905 if (i != InsertPos->getValue())
906 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
908 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
910 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
911 &ShufOps[0], ShufOps.size());
913 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
914 Tmp1, ScVec, ShufMask);
915 Result = LegalizeOp(Result);
919 // If the target doesn't support this, we have to spill the input vector
920 // to a temporary stack slot, update the element, then reload it. This is
921 // badness. We could also load the value into a vector register (either
922 // with a "move to register" or "extload into register" instruction, then
923 // permute it into place, if the idx is a constant and if the idx is
924 // supported by the target.
925 MVT::ValueType VT = Tmp1.getValueType();
926 MVT::ValueType EltVT = Tmp2.getValueType();
927 MVT::ValueType IdxVT = Tmp3.getValueType();
928 MVT::ValueType PtrVT = TLI.getPointerTy();
929 SDOperand StackPtr = CreateStackTemporary(VT);
931 SDOperand Ch = DAG.getStore(DAG.getEntryNode(),
932 Tmp1, StackPtr, DAG.getSrcValue(NULL));
934 // Truncate or zero extend offset to target pointer type.
935 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
936 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
937 // Add the offset to the index.
938 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
939 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
940 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
941 // Store the scalar value.
942 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, DAG.getSrcValue(NULL));
943 // Load the updated vector.
944 Result = DAG.getLoad(VT, Ch, StackPtr, DAG.getSrcValue(NULL));
949 case ISD::SCALAR_TO_VECTOR:
950 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
951 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
955 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
956 Result = DAG.UpdateNodeOperands(Result, Tmp1);
957 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
958 Node->getValueType(0))) {
959 default: assert(0 && "This action is not supported yet!");
960 case TargetLowering::Legal:
962 case TargetLowering::Custom:
963 Tmp3 = TLI.LowerOperation(Result, DAG);
969 case TargetLowering::Expand:
970 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
974 case ISD::VECTOR_SHUFFLE:
975 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
976 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
977 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
979 // Allow targets to custom lower the SHUFFLEs they support.
980 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
981 default: assert(0 && "Unknown operation action!");
982 case TargetLowering::Legal:
983 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
984 "vector shuffle should not be created if not legal!");
986 case TargetLowering::Custom:
987 Tmp3 = TLI.LowerOperation(Result, DAG);
993 case TargetLowering::Expand: {
994 MVT::ValueType VT = Node->getValueType(0);
995 MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
996 MVT::ValueType PtrVT = TLI.getPointerTy();
997 SDOperand Mask = Node->getOperand(2);
998 unsigned NumElems = Mask.getNumOperands();
999 SmallVector<SDOperand,8> Ops;
1000 for (unsigned i = 0; i != NumElems; ++i) {
1001 SDOperand Arg = Mask.getOperand(i);
1002 if (Arg.getOpcode() == ISD::UNDEF) {
1003 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1005 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1006 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1008 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1009 DAG.getConstant(Idx, PtrVT)));
1011 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1012 DAG.getConstant(Idx - NumElems, PtrVT)));
1015 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1018 case TargetLowering::Promote: {
1019 // Change base type to a different vector type.
1020 MVT::ValueType OVT = Node->getValueType(0);
1021 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1023 // Cast the two input vectors.
1024 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1025 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1027 // Convert the shuffle mask to the right # elements.
1028 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1029 assert(Tmp3.Val && "Shuffle not legal?");
1030 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1031 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1037 case ISD::EXTRACT_VECTOR_ELT:
1038 Tmp1 = LegalizeOp(Node->getOperand(0));
1039 Tmp2 = LegalizeOp(Node->getOperand(1));
1040 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1042 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
1043 Tmp1.getValueType())) {
1044 default: assert(0 && "This action is not supported yet!");
1045 case TargetLowering::Legal:
1047 case TargetLowering::Custom:
1048 Tmp3 = TLI.LowerOperation(Result, DAG);
1054 case TargetLowering::Expand:
1055 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1060 case ISD::VEXTRACT_VECTOR_ELT:
1061 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
1064 case ISD::CALLSEQ_START: {
1065 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1067 // Recursively Legalize all of the inputs of the call end that do not lead
1068 // to this call start. This ensures that any libcalls that need be inserted
1069 // are inserted *before* the CALLSEQ_START.
1070 {std::set<SDNode*> NodesLeadingTo;
1071 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1072 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1076 // Now that we legalized all of the inputs (which may have inserted
1077 // libcalls) create the new CALLSEQ_START node.
1078 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1080 // Merge in the last call, to ensure that this call start after the last
1082 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1083 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1084 Tmp1 = LegalizeOp(Tmp1);
1087 // Do not try to legalize the target-specific arguments (#1+).
1088 if (Tmp1 != Node->getOperand(0)) {
1089 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1091 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1094 // Remember that the CALLSEQ_START is legalized.
1095 AddLegalizedOperand(Op.getValue(0), Result);
1096 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1097 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1099 // Now that the callseq_start and all of the non-call nodes above this call
1100 // sequence have been legalized, legalize the call itself. During this
1101 // process, no libcalls can/will be inserted, guaranteeing that no calls
1103 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1104 SDOperand InCallSEQ = LastCALLSEQ_END;
1105 // Note that we are selecting this call!
1106 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1107 IsLegalizingCall = true;
1109 // Legalize the call, starting from the CALLSEQ_END.
1110 LegalizeOp(LastCALLSEQ_END);
1111 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1114 case ISD::CALLSEQ_END:
1115 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1116 // will cause this node to be legalized as well as handling libcalls right.
1117 if (LastCALLSEQ_END.Val != Node) {
1118 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1119 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1120 assert(I != LegalizedNodes.end() &&
1121 "Legalizing the call start should have legalized this node!");
1125 // Otherwise, the call start has been legalized and everything is going
1126 // according to plan. Just legalize ourselves normally here.
1127 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1128 // Do not try to legalize the target-specific arguments (#1+), except for
1129 // an optional flag input.
1130 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1131 if (Tmp1 != Node->getOperand(0)) {
1132 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1134 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1137 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1138 if (Tmp1 != Node->getOperand(0) ||
1139 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1140 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1143 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1146 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1147 // This finishes up call legalization.
1148 IsLegalizingCall = false;
1150 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1151 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1152 if (Node->getNumValues() == 2)
1153 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1154 return Result.getValue(Op.ResNo);
1155 case ISD::DYNAMIC_STACKALLOC: {
1156 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1157 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1158 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1159 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1161 Tmp1 = Result.getValue(0);
1162 Tmp2 = Result.getValue(1);
1163 switch (TLI.getOperationAction(Node->getOpcode(),
1164 Node->getValueType(0))) {
1165 default: assert(0 && "This action is not supported yet!");
1166 case TargetLowering::Expand: {
1167 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1168 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1169 " not tell us which reg is the stack pointer!");
1170 SDOperand Chain = Tmp1.getOperand(0);
1171 SDOperand Size = Tmp2.getOperand(1);
1172 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1173 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1174 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1175 Tmp1 = LegalizeOp(Tmp1);
1176 Tmp2 = LegalizeOp(Tmp2);
1179 case TargetLowering::Custom:
1180 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1182 Tmp1 = LegalizeOp(Tmp3);
1183 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1186 case TargetLowering::Legal:
1189 // Since this op produce two values, make sure to remember that we
1190 // legalized both of them.
1191 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1192 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1193 return Op.ResNo ? Tmp2 : Tmp1;
1195 case ISD::INLINEASM: {
1196 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1197 bool Changed = false;
1198 // Legalize all of the operands of the inline asm, in case they are nodes
1199 // that need to be expanded or something. Note we skip the asm string and
1200 // all of the TargetConstant flags.
1201 SDOperand Op = LegalizeOp(Ops[0]);
1202 Changed = Op != Ops[0];
1205 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1206 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1207 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1208 for (++i; NumVals; ++i, --NumVals) {
1209 SDOperand Op = LegalizeOp(Ops[i]);
1218 Op = LegalizeOp(Ops.back());
1219 Changed |= Op != Ops.back();
1224 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1226 // INLINE asm returns a chain and flag, make sure to add both to the map.
1227 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1228 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1229 return Result.getValue(Op.ResNo);
1232 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1233 // Ensure that libcalls are emitted before a branch.
1234 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1235 Tmp1 = LegalizeOp(Tmp1);
1236 LastCALLSEQ_END = DAG.getEntryNode();
1238 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1241 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1242 // Ensure that libcalls are emitted before a branch.
1243 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1244 Tmp1 = LegalizeOp(Tmp1);
1245 LastCALLSEQ_END = DAG.getEntryNode();
1247 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1248 default: assert(0 && "Indirect target must be legal type (pointer)!");
1250 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1253 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1256 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1257 // Ensure that libcalls are emitted before a return.
1258 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1259 Tmp1 = LegalizeOp(Tmp1);
1260 LastCALLSEQ_END = DAG.getEntryNode();
1262 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1263 case Expand: assert(0 && "It's impossible to expand bools");
1265 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1268 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1272 // Basic block destination (Op#2) is always legal.
1273 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1275 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1276 default: assert(0 && "This action is not supported yet!");
1277 case TargetLowering::Legal: break;
1278 case TargetLowering::Custom:
1279 Tmp1 = TLI.LowerOperation(Result, DAG);
1280 if (Tmp1.Val) Result = Tmp1;
1282 case TargetLowering::Expand:
1283 // Expand brcond's setcc into its constituent parts and create a BR_CC
1285 if (Tmp2.getOpcode() == ISD::SETCC) {
1286 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1287 Tmp2.getOperand(0), Tmp2.getOperand(1),
1288 Node->getOperand(2));
1290 // Make sure the condition is either zero or one. It may have been
1291 // promoted from something else.
1292 unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType());
1293 if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1))
1294 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1296 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1297 DAG.getCondCode(ISD::SETNE), Tmp2,
1298 DAG.getConstant(0, Tmp2.getValueType()),
1299 Node->getOperand(2));
1305 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1306 // Ensure that libcalls are emitted before a branch.
1307 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1308 Tmp1 = LegalizeOp(Tmp1);
1309 LastCALLSEQ_END = DAG.getEntryNode();
1311 Tmp2 = Node->getOperand(2); // LHS
1312 Tmp3 = Node->getOperand(3); // RHS
1313 Tmp4 = Node->getOperand(1); // CC
1315 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1317 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1318 // the LHS is a legal SETCC itself. In this case, we need to compare
1319 // the result against zero to select between true and false values.
1320 if (Tmp3.Val == 0) {
1321 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1322 Tmp4 = DAG.getCondCode(ISD::SETNE);
1325 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1326 Node->getOperand(4));
1328 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1329 default: assert(0 && "Unexpected action for BR_CC!");
1330 case TargetLowering::Legal: break;
1331 case TargetLowering::Custom:
1332 Tmp4 = TLI.LowerOperation(Result, DAG);
1333 if (Tmp4.Val) Result = Tmp4;
1338 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1339 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1341 MVT::ValueType VT = Node->getValueType(0);
1342 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1343 Tmp3 = Result.getValue(0);
1344 Tmp4 = Result.getValue(1);
1346 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1347 default: assert(0 && "This action is not supported yet!");
1348 case TargetLowering::Legal: break;
1349 case TargetLowering::Custom:
1350 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1352 Tmp3 = LegalizeOp(Tmp1);
1353 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1356 case TargetLowering::Promote: {
1357 // Only promote a load of vector type to another.
1358 assert(MVT::isVector(VT) && "Cannot promote this load!");
1359 // Change base type to a different vector type.
1360 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1362 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, Node->getOperand(2));
1363 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1364 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1368 // Since loads produce two values, make sure to remember that we
1369 // legalized both of them.
1370 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1371 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1372 return Op.ResNo ? Tmp4 : Tmp3;
1375 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1376 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1378 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
1379 unsigned LType = cast<ConstantSDNode>(Node->getOperand(4))->getValue();
1380 switch (TLI.getLoadXAction(LType, SrcVT)) {
1381 default: assert(0 && "This action is not supported yet!");
1382 case TargetLowering::Promote:
1383 assert(SrcVT == MVT::i1 && "Can only promote LOADX from i1 -> i8!");
1384 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1385 DAG.getValueType(MVT::i8),
1386 Node->getOperand(4));
1387 Tmp1 = Result.getValue(0);
1388 Tmp2 = Result.getValue(1);
1390 case TargetLowering::Custom:
1393 case TargetLowering::Legal:
1394 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1395 Node->getOperand(3), Node->getOperand(4));
1396 Tmp1 = Result.getValue(0);
1397 Tmp2 = Result.getValue(1);
1400 Tmp3 = TLI.LowerOperation(Result, DAG);
1402 Tmp1 = LegalizeOp(Tmp3);
1403 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1407 case TargetLowering::Expand:
1408 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1409 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1410 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
1411 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1412 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1413 Tmp2 = LegalizeOp(Load.getValue(1));
1416 assert(LType != ISD::EXTLOAD && "EXTLOAD should always be supported!");
1417 // Turn the unsupported load into an EXTLOAD followed by an explicit
1418 // zero/sign extend inreg.
1419 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1420 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1422 if (LType == ISD::SEXTLOAD)
1423 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1424 Result, DAG.getValueType(SrcVT));
1426 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1427 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1428 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1431 // Since loads produce two values, make sure to remember that we legalized
1433 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1434 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1435 return Op.ResNo ? Tmp2 : Tmp1;
1437 case ISD::EXTRACT_ELEMENT: {
1438 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1439 switch (getTypeAction(OpTy)) {
1440 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1442 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1444 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1445 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1446 TLI.getShiftAmountTy()));
1447 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1450 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1451 Node->getOperand(0));
1455 // Get both the low and high parts.
1456 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1457 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1458 Result = Tmp2; // 1 -> Hi
1460 Result = Tmp1; // 0 -> Lo
1466 case ISD::CopyToReg:
1467 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1469 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1470 "Register type must be legal!");
1471 // Legalize the incoming value (must be a legal type).
1472 Tmp2 = LegalizeOp(Node->getOperand(2));
1473 if (Node->getNumValues() == 1) {
1474 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1476 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1477 if (Node->getNumOperands() == 4) {
1478 Tmp3 = LegalizeOp(Node->getOperand(3));
1479 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1482 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1485 // Since this produces two values, make sure to remember that we legalized
1487 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1488 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1494 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1496 // Ensure that libcalls are emitted before a return.
1497 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1498 Tmp1 = LegalizeOp(Tmp1);
1499 LastCALLSEQ_END = DAG.getEntryNode();
1501 switch (Node->getNumOperands()) {
1503 Tmp2 = Node->getOperand(1);
1504 Tmp3 = Node->getOperand(2); // Signness
1505 switch (getTypeAction(Tmp2.getValueType())) {
1507 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1510 if (Tmp2.getValueType() != MVT::Vector) {
1512 ExpandOp(Tmp2, Lo, Hi);
1513 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1514 Result = LegalizeOp(Result);
1516 SDNode *InVal = Tmp2.Val;
1518 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1519 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1521 // Figure out if there is a Packed type corresponding to this Vector
1522 // type. If so, convert to the packed type.
1523 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1524 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1525 // Turn this into a return of the packed type.
1526 Tmp2 = PackVectorOp(Tmp2, TVT);
1527 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1528 } else if (NumElems == 1) {
1529 // Turn this into a return of the scalar type.
1530 Tmp2 = PackVectorOp(Tmp2, EVT);
1531 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1533 // FIXME: Returns of gcc generic vectors smaller than a legal type
1534 // should be returned in integer registers!
1536 // The scalarized value type may not be legal, e.g. it might require
1537 // promotion or expansion. Relegalize the return.
1538 Result = LegalizeOp(Result);
1540 // FIXME: Returns of gcc generic vectors larger than a legal vector
1541 // type should be returned by reference!
1543 SplitVectorOp(Tmp2, Lo, Hi);
1544 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1545 Result = LegalizeOp(Result);
1550 Tmp2 = PromoteOp(Node->getOperand(1));
1551 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1552 Result = LegalizeOp(Result);
1557 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1559 default: { // ret <values>
1560 SmallVector<SDOperand, 8> NewValues;
1561 NewValues.push_back(Tmp1);
1562 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1563 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1565 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1566 NewValues.push_back(Node->getOperand(i+1));
1570 assert(Node->getOperand(i).getValueType() != MVT::Vector &&
1571 "FIXME: TODO: implement returning non-legal vector types!");
1572 ExpandOp(Node->getOperand(i), Lo, Hi);
1573 NewValues.push_back(Lo);
1574 NewValues.push_back(Node->getOperand(i+1));
1575 NewValues.push_back(Hi);
1576 NewValues.push_back(Node->getOperand(i+1));
1580 assert(0 && "Can't promote multiple return value yet!");
1583 if (NewValues.size() == Node->getNumOperands())
1584 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1586 Result = DAG.getNode(ISD::RET, MVT::Other,
1587 &NewValues[0], NewValues.size());
1592 if (Result.getOpcode() == ISD::RET) {
1593 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1594 default: assert(0 && "This action is not supported yet!");
1595 case TargetLowering::Legal: break;
1596 case TargetLowering::Custom:
1597 Tmp1 = TLI.LowerOperation(Result, DAG);
1598 if (Tmp1.Val) Result = Tmp1;
1604 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1605 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1607 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1608 // FIXME: We shouldn't do this for TargetConstantFP's.
1609 // FIXME: move this to the DAG Combiner!
1610 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1611 if (CFP->getValueType(0) == MVT::f32) {
1612 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1614 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1615 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1617 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, Node->getOperand(3));
1621 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1623 Tmp3 = LegalizeOp(Node->getOperand(1));
1624 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1625 Node->getOperand(3));
1627 MVT::ValueType VT = Tmp3.getValueType();
1628 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1629 default: assert(0 && "This action is not supported yet!");
1630 case TargetLowering::Legal: break;
1631 case TargetLowering::Custom:
1632 Tmp1 = TLI.LowerOperation(Result, DAG);
1633 if (Tmp1.Val) Result = Tmp1;
1635 case TargetLowering::Promote:
1636 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1637 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1638 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1639 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1640 Node->getOperand(3));
1646 // Truncate the value and store the result.
1647 Tmp3 = PromoteOp(Node->getOperand(1));
1648 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1649 Node->getOperand(3),
1650 DAG.getValueType(Node->getOperand(1).getValueType()));
1654 unsigned IncrementSize = 0;
1657 // If this is a vector type, then we have to calculate the increment as
1658 // the product of the element size in bytes, and the number of elements
1659 // in the high half of the vector.
1660 if (Node->getOperand(1).getValueType() == MVT::Vector) {
1661 SDNode *InVal = Node->getOperand(1).Val;
1663 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1664 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1666 // Figure out if there is a Packed type corresponding to this Vector
1667 // type. If so, convert to the packed type.
1668 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1669 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1670 // Turn this into a normal store of the packed type.
1671 Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1672 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1673 Node->getOperand(3));
1674 Result = LegalizeOp(Result);
1676 } else if (NumElems == 1) {
1677 // Turn this into a normal store of the scalar type.
1678 Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1679 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1680 Node->getOperand(3));
1681 // The scalarized value type may not be legal, e.g. it might require
1682 // promotion or expansion. Relegalize the scalar store.
1683 Result = LegalizeOp(Result);
1686 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1687 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1690 ExpandOp(Node->getOperand(1), Lo, Hi);
1691 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1693 if (!TLI.isLittleEndian())
1697 Lo = DAG.getStore(Tmp1, Lo, Tmp2, Node->getOperand(3));
1698 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1699 getIntPtrConstant(IncrementSize));
1700 assert(isTypeLegal(Tmp2.getValueType()) &&
1701 "Pointers must be legal!");
1702 // FIXME: This sets the srcvalue of both halves to be the same, which is
1704 Hi = DAG.getStore(Tmp1, Hi, Tmp2, Node->getOperand(3));
1705 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1711 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1712 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1714 case ISD::STACKSAVE:
1715 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1716 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1717 Tmp1 = Result.getValue(0);
1718 Tmp2 = Result.getValue(1);
1720 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1721 default: assert(0 && "This action is not supported yet!");
1722 case TargetLowering::Legal: break;
1723 case TargetLowering::Custom:
1724 Tmp3 = TLI.LowerOperation(Result, DAG);
1726 Tmp1 = LegalizeOp(Tmp3);
1727 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1730 case TargetLowering::Expand:
1731 // Expand to CopyFromReg if the target set
1732 // StackPointerRegisterToSaveRestore.
1733 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1734 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1735 Node->getValueType(0));
1736 Tmp2 = Tmp1.getValue(1);
1738 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1739 Tmp2 = Node->getOperand(0);
1744 // Since stacksave produce two values, make sure to remember that we
1745 // legalized both of them.
1746 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1747 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1748 return Op.ResNo ? Tmp2 : Tmp1;
1750 case ISD::STACKRESTORE:
1751 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1752 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1753 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1755 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1756 default: assert(0 && "This action is not supported yet!");
1757 case TargetLowering::Legal: break;
1758 case TargetLowering::Custom:
1759 Tmp1 = TLI.LowerOperation(Result, DAG);
1760 if (Tmp1.Val) Result = Tmp1;
1762 case TargetLowering::Expand:
1763 // Expand to CopyToReg if the target set
1764 // StackPointerRegisterToSaveRestore.
1765 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1766 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1774 case ISD::READCYCLECOUNTER:
1775 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1776 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1778 // Since rdcc produce two values, make sure to remember that we legalized
1780 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1781 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1784 case ISD::TRUNCSTORE: {
1785 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1786 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1788 assert(isTypeLegal(Node->getOperand(1).getValueType()) &&
1789 "Cannot handle illegal TRUNCSTORE yet!");
1790 Tmp2 = LegalizeOp(Node->getOperand(1));
1792 // The only promote case we handle is TRUNCSTORE:i1 X into
1793 // -> TRUNCSTORE:i8 (and X, 1)
1794 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1795 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1796 TargetLowering::Promote) {
1797 // Promote the bool to a mask then store.
1798 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1799 DAG.getConstant(1, Tmp2.getValueType()));
1800 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1801 Node->getOperand(3), DAG.getValueType(MVT::i8));
1803 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1804 Tmp3 != Node->getOperand(2)) {
1805 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
1806 Node->getOperand(3), Node->getOperand(4));
1809 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT();
1810 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) {
1811 default: assert(0 && "This action is not supported yet!");
1812 case TargetLowering::Legal: break;
1813 case TargetLowering::Custom:
1814 Tmp1 = TLI.LowerOperation(Result, DAG);
1815 if (Tmp1.Val) Result = Tmp1;
1821 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1822 case Expand: assert(0 && "It's impossible to expand bools");
1824 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1827 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1830 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1831 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1833 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1835 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1836 default: assert(0 && "This action is not supported yet!");
1837 case TargetLowering::Legal: break;
1838 case TargetLowering::Custom: {
1839 Tmp1 = TLI.LowerOperation(Result, DAG);
1840 if (Tmp1.Val) Result = Tmp1;
1843 case TargetLowering::Expand:
1844 if (Tmp1.getOpcode() == ISD::SETCC) {
1845 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1847 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1849 // Make sure the condition is either zero or one. It may have been
1850 // promoted from something else.
1851 unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType());
1852 if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1))
1853 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1854 Result = DAG.getSelectCC(Tmp1,
1855 DAG.getConstant(0, Tmp1.getValueType()),
1856 Tmp2, Tmp3, ISD::SETNE);
1859 case TargetLowering::Promote: {
1860 MVT::ValueType NVT =
1861 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1862 unsigned ExtOp, TruncOp;
1863 if (MVT::isVector(Tmp2.getValueType())) {
1864 ExtOp = ISD::BIT_CONVERT;
1865 TruncOp = ISD::BIT_CONVERT;
1866 } else if (MVT::isInteger(Tmp2.getValueType())) {
1867 ExtOp = ISD::ANY_EXTEND;
1868 TruncOp = ISD::TRUNCATE;
1870 ExtOp = ISD::FP_EXTEND;
1871 TruncOp = ISD::FP_ROUND;
1873 // Promote each of the values to the new type.
1874 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1875 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1876 // Perform the larger operation, then round down.
1877 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1878 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1883 case ISD::SELECT_CC: {
1884 Tmp1 = Node->getOperand(0); // LHS
1885 Tmp2 = Node->getOperand(1); // RHS
1886 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1887 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1888 SDOperand CC = Node->getOperand(4);
1890 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
1892 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1893 // the LHS is a legal SETCC itself. In this case, we need to compare
1894 // the result against zero to select between true and false values.
1895 if (Tmp2.Val == 0) {
1896 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1897 CC = DAG.getCondCode(ISD::SETNE);
1899 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
1901 // Everything is legal, see if we should expand this op or something.
1902 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
1903 default: assert(0 && "This action is not supported yet!");
1904 case TargetLowering::Legal: break;
1905 case TargetLowering::Custom:
1906 Tmp1 = TLI.LowerOperation(Result, DAG);
1907 if (Tmp1.Val) Result = Tmp1;
1913 Tmp1 = Node->getOperand(0);
1914 Tmp2 = Node->getOperand(1);
1915 Tmp3 = Node->getOperand(2);
1916 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
1918 // If we had to Expand the SetCC operands into a SELECT node, then it may
1919 // not always be possible to return a true LHS & RHS. In this case, just
1920 // return the value we legalized, returned in the LHS
1921 if (Tmp2.Val == 0) {
1926 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
1927 default: assert(0 && "Cannot handle this action for SETCC yet!");
1928 case TargetLowering::Custom:
1931 case TargetLowering::Legal:
1932 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1934 Tmp3 = TLI.LowerOperation(Result, DAG);
1935 if (Tmp3.Val) Result = Tmp3;
1938 case TargetLowering::Promote: {
1939 // First step, figure out the appropriate operation to use.
1940 // Allow SETCC to not be supported for all legal data types
1941 // Mostly this targets FP
1942 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1943 MVT::ValueType OldVT = NewInTy;
1945 // Scan for the appropriate larger type to use.
1947 NewInTy = (MVT::ValueType)(NewInTy+1);
1949 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1950 "Fell off of the edge of the integer world");
1951 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1952 "Fell off of the edge of the floating point world");
1954 // If the target supports SETCC of this type, use it.
1955 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
1958 if (MVT::isInteger(NewInTy))
1959 assert(0 && "Cannot promote Legal Integer SETCC yet");
1961 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1962 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
1964 Tmp1 = LegalizeOp(Tmp1);
1965 Tmp2 = LegalizeOp(Tmp2);
1966 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1967 Result = LegalizeOp(Result);
1970 case TargetLowering::Expand:
1971 // Expand a setcc node into a select_cc of the same condition, lhs, and
1972 // rhs that selects between const 1 (true) and const 0 (false).
1973 MVT::ValueType VT = Node->getValueType(0);
1974 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1975 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1976 Node->getOperand(2));
1982 case ISD::MEMMOVE: {
1983 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1984 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1986 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1987 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1988 case Expand: assert(0 && "Cannot expand a byte!");
1990 Tmp3 = LegalizeOp(Node->getOperand(2));
1993 Tmp3 = PromoteOp(Node->getOperand(2));
1997 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2001 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2003 // Length is too big, just take the lo-part of the length.
2005 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
2009 Tmp4 = LegalizeOp(Node->getOperand(3));
2012 Tmp4 = PromoteOp(Node->getOperand(3));
2017 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2018 case Expand: assert(0 && "Cannot expand this yet!");
2020 Tmp5 = LegalizeOp(Node->getOperand(4));
2023 Tmp5 = PromoteOp(Node->getOperand(4));
2027 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2028 default: assert(0 && "This action not implemented for this operation!");
2029 case TargetLowering::Custom:
2032 case TargetLowering::Legal:
2033 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2035 Tmp1 = TLI.LowerOperation(Result, DAG);
2036 if (Tmp1.Val) Result = Tmp1;
2039 case TargetLowering::Expand: {
2040 // Otherwise, the target does not support this operation. Lower the
2041 // operation to an explicit libcall as appropriate.
2042 MVT::ValueType IntPtr = TLI.getPointerTy();
2043 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2044 std::vector<std::pair<SDOperand, const Type*> > Args;
2046 const char *FnName = 0;
2047 if (Node->getOpcode() == ISD::MEMSET) {
2048 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2049 // Extend the (previously legalized) ubyte argument to be an int value
2051 if (Tmp3.getValueType() > MVT::i32)
2052 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2054 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2055 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
2056 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2059 } else if (Node->getOpcode() == ISD::MEMCPY ||
2060 Node->getOpcode() == ISD::MEMMOVE) {
2061 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2062 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
2063 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2064 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2066 assert(0 && "Unknown op!");
2069 std::pair<SDOperand,SDOperand> CallResult =
2070 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
2071 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2072 Result = CallResult.second;
2079 case ISD::SHL_PARTS:
2080 case ISD::SRA_PARTS:
2081 case ISD::SRL_PARTS: {
2082 SmallVector<SDOperand, 8> Ops;
2083 bool Changed = false;
2084 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2085 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2086 Changed |= Ops.back() != Node->getOperand(i);
2089 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2091 switch (TLI.getOperationAction(Node->getOpcode(),
2092 Node->getValueType(0))) {
2093 default: assert(0 && "This action is not supported yet!");
2094 case TargetLowering::Legal: break;
2095 case TargetLowering::Custom:
2096 Tmp1 = TLI.LowerOperation(Result, DAG);
2098 SDOperand Tmp2, RetVal(0, 0);
2099 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2100 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2101 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2105 assert(RetVal.Val && "Illegal result number");
2111 // Since these produce multiple values, make sure to remember that we
2112 // legalized all of them.
2113 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2114 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2115 return Result.getValue(Op.ResNo);
2136 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2137 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2138 case Expand: assert(0 && "Not possible");
2140 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2143 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2147 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2149 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2150 default: assert(0 && "BinOp legalize operation not supported");
2151 case TargetLowering::Legal: break;
2152 case TargetLowering::Custom:
2153 Tmp1 = TLI.LowerOperation(Result, DAG);
2154 if (Tmp1.Val) Result = Tmp1;
2156 case TargetLowering::Expand: {
2157 if (Node->getValueType(0) == MVT::i32) {
2158 switch (Node->getOpcode()) {
2159 default: assert(0 && "Do not know how to expand this integer BinOp!");
2162 const char *FnName = Node->getOpcode() == ISD::UDIV
2163 ? "__udivsi3" : "__divsi3";
2165 Result = ExpandLibCall(FnName, Node, Dummy);
2170 assert(MVT::isVector(Node->getValueType(0)) &&
2171 "Cannot expand this binary operator!");
2172 // Expand the operation into a bunch of nasty scalar code.
2173 SmallVector<SDOperand, 8> Ops;
2174 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
2175 MVT::ValueType PtrVT = TLI.getPointerTy();
2176 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2178 SDOperand Idx = DAG.getConstant(i, PtrVT);
2179 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2180 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2181 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2183 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2184 &Ops[0], Ops.size());
2187 case TargetLowering::Promote: {
2188 switch (Node->getOpcode()) {
2189 default: assert(0 && "Do not know how to promote this BinOp!");
2193 MVT::ValueType OVT = Node->getValueType(0);
2194 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2195 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2196 // Bit convert each of the values to the new type.
2197 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2198 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2199 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2200 // Bit convert the result back the original type.
2201 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2209 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2210 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2211 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2212 case Expand: assert(0 && "Not possible");
2214 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2217 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2221 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2223 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2224 default: assert(0 && "Operation not supported");
2225 case TargetLowering::Custom:
2226 Tmp1 = TLI.LowerOperation(Result, DAG);
2227 if (Tmp1.Val) Result = Tmp1;
2229 case TargetLowering::Legal: break;
2230 case TargetLowering::Expand:
2231 // If this target supports fabs/fneg natively, do this efficiently.
2232 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
2233 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
2234 // Get the sign bit of the RHS.
2235 MVT::ValueType IVT =
2236 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2237 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2238 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2239 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2240 // Get the absolute value of the result.
2241 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2242 // Select between the nabs and abs value based on the sign bit of
2244 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2245 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2248 Result = LegalizeOp(Result);
2252 // Otherwise, do bitwise ops!
2254 // copysign -> copysignf/copysign libcall.
2256 if (Node->getValueType(0) == MVT::f32) {
2257 FnName = "copysignf";
2258 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type.
2259 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2260 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2));
2262 FnName = "copysign";
2263 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type.
2264 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2265 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2));
2268 Result = ExpandLibCall(FnName, Node, Dummy);
2275 Tmp1 = LegalizeOp(Node->getOperand(0));
2276 Tmp2 = LegalizeOp(Node->getOperand(1));
2277 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2278 // Since this produces two values, make sure to remember that we legalized
2280 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2281 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2286 Tmp1 = LegalizeOp(Node->getOperand(0));
2287 Tmp2 = LegalizeOp(Node->getOperand(1));
2288 Tmp3 = LegalizeOp(Node->getOperand(2));
2289 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2290 // Since this produces two values, make sure to remember that we legalized
2292 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2293 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2296 case ISD::BUILD_PAIR: {
2297 MVT::ValueType PairTy = Node->getValueType(0);
2298 // TODO: handle the case where the Lo and Hi operands are not of legal type
2299 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2300 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2301 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2302 case TargetLowering::Promote:
2303 case TargetLowering::Custom:
2304 assert(0 && "Cannot promote/custom this yet!");
2305 case TargetLowering::Legal:
2306 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2307 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2309 case TargetLowering::Expand:
2310 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2311 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2312 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2313 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2314 TLI.getShiftAmountTy()));
2315 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2324 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2325 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2327 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2328 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2329 case TargetLowering::Custom:
2332 case TargetLowering::Legal:
2333 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2335 Tmp1 = TLI.LowerOperation(Result, DAG);
2336 if (Tmp1.Val) Result = Tmp1;
2339 case TargetLowering::Expand:
2340 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2341 if (MVT::isInteger(Node->getValueType(0))) {
2342 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2343 TargetLowering::Legal) {
2345 MVT::ValueType VT = Node->getValueType(0);
2346 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2347 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2348 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2350 assert(Node->getValueType(0) == MVT::i32 &&
2351 "Cannot expand this binary operator!");
2352 const char *FnName = Node->getOpcode() == ISD::UREM
2353 ? "__umodsi3" : "__modsi3";
2355 Result = ExpandLibCall(FnName, Node, Dummy);
2358 // Floating point mod -> fmod libcall.
2359 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
2361 Result = ExpandLibCall(FnName, Node, Dummy);
2367 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2368 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2370 MVT::ValueType VT = Node->getValueType(0);
2371 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2372 default: assert(0 && "This action is not supported yet!");
2373 case TargetLowering::Custom:
2376 case TargetLowering::Legal:
2377 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2378 Result = Result.getValue(0);
2379 Tmp1 = Result.getValue(1);
2382 Tmp2 = TLI.LowerOperation(Result, DAG);
2384 Result = LegalizeOp(Tmp2);
2385 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2389 case TargetLowering::Expand: {
2390 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2391 Node->getOperand(2));
2392 // Increment the pointer, VAList, to the next vaarg
2393 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2394 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2395 TLI.getPointerTy()));
2396 // Store the incremented VAList to the legalized pointer
2397 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, Node->getOperand(2));
2398 // Load the actual argument out of the pointer VAList
2399 Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0));
2400 Tmp1 = LegalizeOp(Result.getValue(1));
2401 Result = LegalizeOp(Result);
2405 // Since VAARG produces two values, make sure to remember that we
2406 // legalized both of them.
2407 AddLegalizedOperand(SDOperand(Node, 0), Result);
2408 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2409 return Op.ResNo ? Tmp1 : Result;
2413 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2414 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2415 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2417 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2418 default: assert(0 && "This action is not supported yet!");
2419 case TargetLowering::Custom:
2422 case TargetLowering::Legal:
2423 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2424 Node->getOperand(3), Node->getOperand(4));
2426 Tmp1 = TLI.LowerOperation(Result, DAG);
2427 if (Tmp1.Val) Result = Tmp1;
2430 case TargetLowering::Expand:
2431 // This defaults to loading a pointer from the input and storing it to the
2432 // output, returning the chain.
2433 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, Node->getOperand(3));
2434 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, Node->getOperand(4));
2440 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2441 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2443 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2444 default: assert(0 && "This action is not supported yet!");
2445 case TargetLowering::Custom:
2448 case TargetLowering::Legal:
2449 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2451 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2452 if (Tmp1.Val) Result = Tmp1;
2455 case TargetLowering::Expand:
2456 Result = Tmp1; // Default to a no-op, return the chain
2462 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2463 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2465 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2467 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2468 default: assert(0 && "This action is not supported yet!");
2469 case TargetLowering::Legal: break;
2470 case TargetLowering::Custom:
2471 Tmp1 = TLI.LowerOperation(Result, DAG);
2472 if (Tmp1.Val) Result = Tmp1;
2479 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2480 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2482 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2483 "Cannot handle this yet!");
2484 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2488 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2489 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2490 case TargetLowering::Custom:
2491 assert(0 && "Cannot custom legalize this yet!");
2492 case TargetLowering::Legal:
2493 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2495 case TargetLowering::Promote: {
2496 MVT::ValueType OVT = Tmp1.getValueType();
2497 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2498 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2500 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2501 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2502 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2503 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2506 case TargetLowering::Expand:
2507 Result = ExpandBSWAP(Tmp1);
2515 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2516 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2517 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2518 case TargetLowering::Legal:
2519 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2521 case TargetLowering::Promote: {
2522 MVT::ValueType OVT = Tmp1.getValueType();
2523 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2525 // Zero extend the argument.
2526 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2527 // Perform the larger operation, then subtract if needed.
2528 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2529 switch (Node->getOpcode()) {
2534 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2535 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2536 DAG.getConstant(getSizeInBits(NVT), NVT),
2538 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2539 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2542 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2543 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2544 DAG.getConstant(getSizeInBits(NVT) -
2545 getSizeInBits(OVT), NVT));
2550 case TargetLowering::Expand:
2551 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2562 Tmp1 = LegalizeOp(Node->getOperand(0));
2563 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2564 case TargetLowering::Promote:
2565 case TargetLowering::Custom:
2568 case TargetLowering::Legal:
2569 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2571 Tmp1 = TLI.LowerOperation(Result, DAG);
2572 if (Tmp1.Val) Result = Tmp1;
2575 case TargetLowering::Expand:
2576 switch (Node->getOpcode()) {
2577 default: assert(0 && "Unreachable!");
2579 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2580 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2581 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2584 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2585 MVT::ValueType VT = Node->getValueType(0);
2586 Tmp2 = DAG.getConstantFP(0.0, VT);
2587 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2588 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2589 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2595 MVT::ValueType VT = Node->getValueType(0);
2596 const char *FnName = 0;
2597 switch(Node->getOpcode()) {
2598 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2599 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2600 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2601 default: assert(0 && "Unreachable!");
2604 Result = ExpandLibCall(FnName, Node, Dummy);
2612 // We always lower FPOWI into a libcall. No target support it yet.
2613 const char *FnName = Node->getValueType(0) == MVT::f32
2614 ? "__powisf2" : "__powidf2";
2616 Result = ExpandLibCall(FnName, Node, Dummy);
2619 case ISD::BIT_CONVERT:
2620 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2621 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2623 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2624 Node->getOperand(0).getValueType())) {
2625 default: assert(0 && "Unknown operation action!");
2626 case TargetLowering::Expand:
2627 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2629 case TargetLowering::Legal:
2630 Tmp1 = LegalizeOp(Node->getOperand(0));
2631 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2636 case ISD::VBIT_CONVERT: {
2637 assert(Op.getOperand(0).getValueType() == MVT::Vector &&
2638 "Can only have VBIT_CONVERT where input or output is MVT::Vector!");
2640 // The input has to be a vector type, we have to either scalarize it, pack
2641 // it, or convert it based on whether the input vector type is legal.
2642 SDNode *InVal = Node->getOperand(0).Val;
2644 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
2645 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
2647 // Figure out if there is a Packed type corresponding to this Vector
2648 // type. If so, convert to the packed type.
2649 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2650 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
2651 // Turn this into a bit convert of the packed input.
2652 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2653 PackVectorOp(Node->getOperand(0), TVT));
2655 } else if (NumElems == 1) {
2656 // Turn this into a bit convert of the scalar input.
2657 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2658 PackVectorOp(Node->getOperand(0), EVT));
2661 // FIXME: UNIMP! Store then reload
2662 assert(0 && "Cast from unsupported vector type not implemented yet!");
2666 // Conversion operators. The source and destination have different types.
2667 case ISD::SINT_TO_FP:
2668 case ISD::UINT_TO_FP: {
2669 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2670 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2672 switch (TLI.getOperationAction(Node->getOpcode(),
2673 Node->getOperand(0).getValueType())) {
2674 default: assert(0 && "Unknown operation action!");
2675 case TargetLowering::Custom:
2678 case TargetLowering::Legal:
2679 Tmp1 = LegalizeOp(Node->getOperand(0));
2680 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2682 Tmp1 = TLI.LowerOperation(Result, DAG);
2683 if (Tmp1.Val) Result = Tmp1;
2686 case TargetLowering::Expand:
2687 Result = ExpandLegalINT_TO_FP(isSigned,
2688 LegalizeOp(Node->getOperand(0)),
2689 Node->getValueType(0));
2691 case TargetLowering::Promote:
2692 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2693 Node->getValueType(0),
2699 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2700 Node->getValueType(0), Node->getOperand(0));
2703 Tmp1 = PromoteOp(Node->getOperand(0));
2705 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2706 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2708 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2709 Node->getOperand(0).getValueType());
2711 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2712 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2718 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2720 Tmp1 = LegalizeOp(Node->getOperand(0));
2721 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2724 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2726 // Since the result is legal, we should just be able to truncate the low
2727 // part of the source.
2728 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2731 Result = PromoteOp(Node->getOperand(0));
2732 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2737 case ISD::FP_TO_SINT:
2738 case ISD::FP_TO_UINT:
2739 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2741 Tmp1 = LegalizeOp(Node->getOperand(0));
2743 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2744 default: assert(0 && "Unknown operation action!");
2745 case TargetLowering::Custom:
2748 case TargetLowering::Legal:
2749 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2751 Tmp1 = TLI.LowerOperation(Result, DAG);
2752 if (Tmp1.Val) Result = Tmp1;
2755 case TargetLowering::Promote:
2756 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2757 Node->getOpcode() == ISD::FP_TO_SINT);
2759 case TargetLowering::Expand:
2760 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2761 SDOperand True, False;
2762 MVT::ValueType VT = Node->getOperand(0).getValueType();
2763 MVT::ValueType NVT = Node->getValueType(0);
2764 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2765 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2766 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2767 Node->getOperand(0), Tmp2, ISD::SETLT);
2768 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2769 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2770 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2772 False = DAG.getNode(ISD::XOR, NVT, False,
2773 DAG.getConstant(1ULL << ShiftAmt, NVT));
2774 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2777 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2783 assert(0 && "Shouldn't need to expand other operators here!");
2785 Tmp1 = PromoteOp(Node->getOperand(0));
2786 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
2787 Result = LegalizeOp(Result);
2792 case ISD::ANY_EXTEND:
2793 case ISD::ZERO_EXTEND:
2794 case ISD::SIGN_EXTEND:
2795 case ISD::FP_EXTEND:
2797 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2798 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
2800 Tmp1 = LegalizeOp(Node->getOperand(0));
2801 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2804 switch (Node->getOpcode()) {
2805 case ISD::ANY_EXTEND:
2806 Tmp1 = PromoteOp(Node->getOperand(0));
2807 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
2809 case ISD::ZERO_EXTEND:
2810 Result = PromoteOp(Node->getOperand(0));
2811 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2812 Result = DAG.getZeroExtendInReg(Result,
2813 Node->getOperand(0).getValueType());
2815 case ISD::SIGN_EXTEND:
2816 Result = PromoteOp(Node->getOperand(0));
2817 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2818 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2820 DAG.getValueType(Node->getOperand(0).getValueType()));
2822 case ISD::FP_EXTEND:
2823 Result = PromoteOp(Node->getOperand(0));
2824 if (Result.getValueType() != Op.getValueType())
2825 // Dynamically dead while we have only 2 FP types.
2826 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2829 Result = PromoteOp(Node->getOperand(0));
2830 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2835 case ISD::FP_ROUND_INREG:
2836 case ISD::SIGN_EXTEND_INREG: {
2837 Tmp1 = LegalizeOp(Node->getOperand(0));
2838 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2840 // If this operation is not supported, convert it to a shl/shr or load/store
2842 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2843 default: assert(0 && "This action not supported for this op yet!");
2844 case TargetLowering::Legal:
2845 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2847 case TargetLowering::Expand:
2848 // If this is an integer extend and shifts are supported, do that.
2849 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2850 // NOTE: we could fall back on load/store here too for targets without
2851 // SAR. However, it is doubtful that any exist.
2852 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2853 MVT::getSizeInBits(ExtraVT);
2854 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2855 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2856 Node->getOperand(0), ShiftCst);
2857 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2859 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2860 // The only way we can lower this is to turn it into a STORETRUNC,
2861 // EXTLOAD pair, targetting a temporary location (a stack slot).
2863 // NOTE: there is a choice here between constantly creating new stack
2864 // slots and always reusing the same one. We currently always create
2865 // new ones, as reuse may inhibit scheduling.
2866 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2867 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty);
2868 unsigned Align = TLI.getTargetData()->getTypeAlignment(Ty);
2869 MachineFunction &MF = DAG.getMachineFunction();
2871 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2872 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2873 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2874 Node->getOperand(0), StackSlot,
2875 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2876 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2877 Result, StackSlot, DAG.getSrcValue(NULL),
2880 assert(0 && "Unknown op");
2888 assert(Result.getValueType() == Op.getValueType() &&
2889 "Bad legalization!");
2891 // Make sure that the generated code is itself legal.
2893 Result = LegalizeOp(Result);
2895 // Note that LegalizeOp may be reentered even from single-use nodes, which
2896 // means that we always must cache transformed nodes.
2897 AddLegalizedOperand(Op, Result);
2901 /// PromoteOp - Given an operation that produces a value in an invalid type,
2902 /// promote it to compute the value into a larger type. The produced value will
2903 /// have the correct bits for the low portion of the register, but no guarantee
2904 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2905 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2906 MVT::ValueType VT = Op.getValueType();
2907 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2908 assert(getTypeAction(VT) == Promote &&
2909 "Caller should expand or legalize operands that are not promotable!");
2910 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2911 "Cannot promote to smaller type!");
2913 SDOperand Tmp1, Tmp2, Tmp3;
2915 SDNode *Node = Op.Val;
2917 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2918 if (I != PromotedNodes.end()) return I->second;
2920 switch (Node->getOpcode()) {
2921 case ISD::CopyFromReg:
2922 assert(0 && "CopyFromReg must be legal!");
2925 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2927 assert(0 && "Do not know how to promote this operator!");
2930 Result = DAG.getNode(ISD::UNDEF, NVT);
2934 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2936 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2937 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2939 case ISD::ConstantFP:
2940 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2941 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2945 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2946 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2947 Node->getOperand(1), Node->getOperand(2));
2951 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2953 Result = LegalizeOp(Node->getOperand(0));
2954 assert(Result.getValueType() >= NVT &&
2955 "This truncation doesn't make sense!");
2956 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2957 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2960 // The truncation is not required, because we don't guarantee anything
2961 // about high bits anyway.
2962 Result = PromoteOp(Node->getOperand(0));
2965 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2966 // Truncate the low part of the expanded value to the result type
2967 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2970 case ISD::SIGN_EXTEND:
2971 case ISD::ZERO_EXTEND:
2972 case ISD::ANY_EXTEND:
2973 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2974 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2976 // Input is legal? Just do extend all the way to the larger type.
2977 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2980 // Promote the reg if it's smaller.
2981 Result = PromoteOp(Node->getOperand(0));
2982 // The high bits are not guaranteed to be anything. Insert an extend.
2983 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2984 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2985 DAG.getValueType(Node->getOperand(0).getValueType()));
2986 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2987 Result = DAG.getZeroExtendInReg(Result,
2988 Node->getOperand(0).getValueType());
2992 case ISD::BIT_CONVERT:
2993 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2994 Result = PromoteOp(Result);
2997 case ISD::FP_EXTEND:
2998 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3000 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3001 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3002 case Promote: assert(0 && "Unreachable with 2 FP types!");
3004 // Input is legal? Do an FP_ROUND_INREG.
3005 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3006 DAG.getValueType(VT));
3011 case ISD::SINT_TO_FP:
3012 case ISD::UINT_TO_FP:
3013 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3015 // No extra round required here.
3016 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3020 Result = PromoteOp(Node->getOperand(0));
3021 if (Node->getOpcode() == ISD::SINT_TO_FP)
3022 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3024 DAG.getValueType(Node->getOperand(0).getValueType()));
3026 Result = DAG.getZeroExtendInReg(Result,
3027 Node->getOperand(0).getValueType());
3028 // No extra round required here.
3029 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3032 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3033 Node->getOperand(0));
3034 // Round if we cannot tolerate excess precision.
3035 if (NoExcessFPPrecision)
3036 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3037 DAG.getValueType(VT));
3042 case ISD::SIGN_EXTEND_INREG:
3043 Result = PromoteOp(Node->getOperand(0));
3044 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3045 Node->getOperand(1));
3047 case ISD::FP_TO_SINT:
3048 case ISD::FP_TO_UINT:
3049 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3051 Tmp1 = Node->getOperand(0);
3054 // The input result is prerounded, so we don't have to do anything
3056 Tmp1 = PromoteOp(Node->getOperand(0));
3059 assert(0 && "not implemented");
3061 // If we're promoting a UINT to a larger size, check to see if the new node
3062 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3063 // we can use that instead. This allows us to generate better code for
3064 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3065 // legal, such as PowerPC.
3066 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3067 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3068 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3069 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3070 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3072 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3078 Tmp1 = PromoteOp(Node->getOperand(0));
3079 assert(Tmp1.getValueType() == NVT);
3080 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3081 // NOTE: we do not have to do any extra rounding here for
3082 // NoExcessFPPrecision, because we know the input will have the appropriate
3083 // precision, and these operations don't modify precision at all.
3089 Tmp1 = PromoteOp(Node->getOperand(0));
3090 assert(Tmp1.getValueType() == NVT);
3091 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3092 if (NoExcessFPPrecision)
3093 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3094 DAG.getValueType(VT));
3103 // The input may have strange things in the top bits of the registers, but
3104 // these operations don't care. They may have weird bits going out, but
3105 // that too is okay if they are integer operations.
3106 Tmp1 = PromoteOp(Node->getOperand(0));
3107 Tmp2 = PromoteOp(Node->getOperand(1));
3108 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3109 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3114 Tmp1 = PromoteOp(Node->getOperand(0));
3115 Tmp2 = PromoteOp(Node->getOperand(1));
3116 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3117 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3119 // Floating point operations will give excess precision that we may not be
3120 // able to tolerate. If we DO allow excess precision, just leave it,
3121 // otherwise excise it.
3122 // FIXME: Why would we need to round FP ops more than integer ones?
3123 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3124 if (NoExcessFPPrecision)
3125 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3126 DAG.getValueType(VT));
3131 // These operators require that their input be sign extended.
3132 Tmp1 = PromoteOp(Node->getOperand(0));
3133 Tmp2 = PromoteOp(Node->getOperand(1));
3134 if (MVT::isInteger(NVT)) {
3135 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3136 DAG.getValueType(VT));
3137 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3138 DAG.getValueType(VT));
3140 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3142 // Perform FP_ROUND: this is probably overly pessimistic.
3143 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3144 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3145 DAG.getValueType(VT));
3149 case ISD::FCOPYSIGN:
3150 // These operators require that their input be fp extended.
3151 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3153 Tmp1 = LegalizeOp(Node->getOperand(0));
3156 Tmp1 = PromoteOp(Node->getOperand(0));
3159 assert(0 && "not implemented");
3161 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3163 Tmp2 = LegalizeOp(Node->getOperand(1));
3166 Tmp2 = PromoteOp(Node->getOperand(1));
3169 assert(0 && "not implemented");
3171 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3173 // Perform FP_ROUND: this is probably overly pessimistic.
3174 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3175 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3176 DAG.getValueType(VT));
3181 // These operators require that their input be zero extended.
3182 Tmp1 = PromoteOp(Node->getOperand(0));
3183 Tmp2 = PromoteOp(Node->getOperand(1));
3184 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3185 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3186 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3187 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3191 Tmp1 = PromoteOp(Node->getOperand(0));
3192 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3195 // The input value must be properly sign extended.
3196 Tmp1 = PromoteOp(Node->getOperand(0));
3197 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3198 DAG.getValueType(VT));
3199 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3202 // The input value must be properly zero extended.
3203 Tmp1 = PromoteOp(Node->getOperand(0));
3204 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3205 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3209 Tmp1 = Node->getOperand(0); // Get the chain.
3210 Tmp2 = Node->getOperand(1); // Get the pointer.
3211 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3212 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3213 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3215 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3216 Node->getOperand(2));
3217 // Increment the pointer, VAList, to the next vaarg
3218 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3219 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3220 TLI.getPointerTy()));
3221 // Store the incremented VAList to the legalized pointer
3222 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, Node->getOperand(2));
3223 // Load the actual argument out of the pointer VAList
3224 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList,
3225 DAG.getSrcValue(0), VT);
3227 // Remember that we legalized the chain.
3228 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3232 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Node->getOperand(0),
3233 Node->getOperand(1), Node->getOperand(2), VT);
3234 // Remember that we legalized the chain.
3235 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3239 DAG.getExtLoad((ISD::LoadExtType)Node->getConstantOperandVal(4),
3240 NVT, Node->getOperand(0), Node->getOperand(1),
3241 Node->getOperand(2),
3242 cast<VTSDNode>(Node->getOperand(3))->getVT());
3243 // Remember that we legalized the chain.
3244 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3247 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3248 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3249 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3251 case ISD::SELECT_CC:
3252 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3253 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3254 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3255 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3258 Tmp1 = Node->getOperand(0);
3259 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3260 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3261 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3262 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
3263 TLI.getShiftAmountTy()));
3268 // Zero extend the argument
3269 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3270 // Perform the larger operation, then subtract if needed.
3271 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3272 switch(Node->getOpcode()) {
3277 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3278 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3279 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
3280 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3281 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
3284 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3285 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3286 DAG.getConstant(getSizeInBits(NVT) -
3287 getSizeInBits(VT), NVT));
3291 case ISD::VEXTRACT_VECTOR_ELT:
3292 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
3294 case ISD::EXTRACT_VECTOR_ELT:
3295 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3299 assert(Result.Val && "Didn't set a result!");
3301 // Make sure the result is itself legal.
3302 Result = LegalizeOp(Result);
3304 // Remember that we promoted this!
3305 AddPromotedOperand(Op, Result);
3309 /// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
3310 /// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
3311 /// on the vector type. The return type of this matches the element type of the
3312 /// vector, which may not be legal for the target.
3313 SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
3314 // We know that operand #0 is the Vec vector. If the index is a constant
3315 // or if the invec is a supported hardware type, we can use it. Otherwise,
3316 // lower to a store then an indexed load.
3317 SDOperand Vec = Op.getOperand(0);
3318 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3320 SDNode *InVal = Vec.Val;
3321 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
3322 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
3324 // Figure out if there is a Packed type corresponding to this Vector
3325 // type. If so, convert to the packed type.
3326 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3327 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
3328 // Turn this into a packed extract_vector_elt operation.
3329 Vec = PackVectorOp(Vec, TVT);
3330 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
3331 } else if (NumElems == 1) {
3332 // This must be an access of the only element. Return it.
3333 return PackVectorOp(Vec, EVT);
3334 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
3336 SplitVectorOp(Vec, Lo, Hi);
3337 if (CIdx->getValue() < NumElems/2) {
3341 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3344 // It's now an extract from the appropriate high or low part. Recurse.
3345 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3346 return LowerVEXTRACT_VECTOR_ELT(Op);
3348 // Variable index case for extract element.
3349 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
3350 assert(0 && "unimp!");
3355 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3357 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3358 SDOperand Vector = Op.getOperand(0);
3359 SDOperand Idx = Op.getOperand(1);
3361 // If the target doesn't support this, store the value to a temporary
3362 // stack slot, then LOAD the scalar element back out.
3363 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
3364 SDOperand Ch = DAG.getStore(DAG.getEntryNode(),
3365 Vector, StackPtr, DAG.getSrcValue(NULL));
3367 // Add the offset to the index.
3368 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3369 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3370 DAG.getConstant(EltSize, Idx.getValueType()));
3371 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3373 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, DAG.getSrcValue(NULL));
3377 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3378 /// with condition CC on the current target. This usually involves legalizing
3379 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3380 /// there may be no choice but to create a new SetCC node to represent the
3381 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3382 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3383 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3386 SDOperand Tmp1, Tmp2, Result;
3388 switch (getTypeAction(LHS.getValueType())) {
3390 Tmp1 = LegalizeOp(LHS); // LHS
3391 Tmp2 = LegalizeOp(RHS); // RHS
3394 Tmp1 = PromoteOp(LHS); // LHS
3395 Tmp2 = PromoteOp(RHS); // RHS
3397 // If this is an FP compare, the operands have already been extended.
3398 if (MVT::isInteger(LHS.getValueType())) {
3399 MVT::ValueType VT = LHS.getValueType();
3400 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3402 // Otherwise, we have to insert explicit sign or zero extends. Note
3403 // that we could insert sign extends for ALL conditions, but zero extend
3404 // is cheaper on many machines (an AND instead of two shifts), so prefer
3406 switch (cast<CondCodeSDNode>(CC)->get()) {
3407 default: assert(0 && "Unknown integer comparison!");
3414 // ALL of these operations will work if we either sign or zero extend
3415 // the operands (including the unsigned comparisons!). Zero extend is
3416 // usually a simpler/cheaper operation, so prefer it.
3417 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3418 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3424 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3425 DAG.getValueType(VT));
3426 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3427 DAG.getValueType(VT));
3433 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3434 ExpandOp(LHS, LHSLo, LHSHi);
3435 ExpandOp(RHS, RHSLo, RHSHi);
3436 switch (cast<CondCodeSDNode>(CC)->get()) {
3440 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3441 if (RHSCST->isAllOnesValue()) {
3442 // Comparison to -1.
3443 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3448 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3449 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3450 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3451 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3454 // If this is a comparison of the sign bit, just look at the top part.
3456 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3457 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3458 CST->getValue() == 0) || // X < 0
3459 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3460 CST->isAllOnesValue())) { // X > -1
3466 // FIXME: This generated code sucks.
3467 ISD::CondCode LowCC;
3468 switch (cast<CondCodeSDNode>(CC)->get()) {
3469 default: assert(0 && "Unknown integer setcc!");
3471 case ISD::SETULT: LowCC = ISD::SETULT; break;
3473 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3475 case ISD::SETULE: LowCC = ISD::SETULE; break;
3477 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3480 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3481 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3482 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3484 // NOTE: on targets without efficient SELECT of bools, we can always use
3485 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3486 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3487 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3488 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3489 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3490 Result, Tmp1, Tmp2));
3499 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3500 /// The resultant code need not be legal. Note that SrcOp is the input operand
3501 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3502 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3504 // Create the stack frame object.
3505 SDOperand FIPtr = CreateStackTemporary(DestVT);
3507 // Emit a store to the stack slot.
3508 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
3509 SrcOp, FIPtr, DAG.getSrcValue(NULL));
3510 // Result is a load from the stack slot.
3511 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0));
3514 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3515 // Create a vector sized/aligned stack slot, store the value to element #0,
3516 // then load the whole vector back out.
3517 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3518 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
3519 DAG.getSrcValue(NULL));
3520 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,DAG.getSrcValue(NULL));
3524 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3525 /// support the operation, but do support the resultant packed vector type.
3526 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3528 // If the only non-undef value is the low element, turn this into a
3529 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3530 unsigned NumElems = Node->getNumOperands();
3531 bool isOnlyLowElement = true;
3532 SDOperand SplatValue = Node->getOperand(0);
3533 std::map<SDOperand, std::vector<unsigned> > Values;
3534 Values[SplatValue].push_back(0);
3535 bool isConstant = true;
3536 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3537 SplatValue.getOpcode() != ISD::UNDEF)
3540 for (unsigned i = 1; i < NumElems; ++i) {
3541 SDOperand V = Node->getOperand(i);
3542 Values[V].push_back(i);
3543 if (V.getOpcode() != ISD::UNDEF)
3544 isOnlyLowElement = false;
3545 if (SplatValue != V)
3546 SplatValue = SDOperand(0,0);
3548 // If this isn't a constant element or an undef, we can't use a constant
3550 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3551 V.getOpcode() != ISD::UNDEF)
3555 if (isOnlyLowElement) {
3556 // If the low element is an undef too, then this whole things is an undef.
3557 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3558 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3559 // Otherwise, turn this into a scalar_to_vector node.
3560 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3561 Node->getOperand(0));
3564 // If all elements are constants, create a load from the constant pool.
3566 MVT::ValueType VT = Node->getValueType(0);
3568 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3569 std::vector<Constant*> CV;
3570 for (unsigned i = 0, e = NumElems; i != e; ++i) {
3571 if (ConstantFPSDNode *V =
3572 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3573 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3574 } else if (ConstantSDNode *V =
3575 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3576 CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
3578 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3579 CV.push_back(UndefValue::get(OpNTy));
3582 Constant *CP = ConstantPacked::get(CV);
3583 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3584 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
3585 DAG.getSrcValue(NULL));
3588 if (SplatValue.Val) { // Splat of one value?
3589 // Build the shuffle constant vector: <0, 0, 0, 0>
3590 MVT::ValueType MaskVT =
3591 MVT::getIntVectorWithNumElements(NumElems);
3592 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
3593 std::vector<SDOperand> ZeroVec(NumElems, Zero);
3594 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3595 &ZeroVec[0], ZeroVec.size());
3597 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3598 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
3599 // Get the splatted value into the low element of a vector register.
3600 SDOperand LowValVec =
3601 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3603 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3604 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3605 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3610 // If there are only two unique elements, we may be able to turn this into a
3612 if (Values.size() == 2) {
3613 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
3614 MVT::ValueType MaskVT =
3615 MVT::getIntVectorWithNumElements(NumElems);
3616 std::vector<SDOperand> MaskVec(NumElems);
3618 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3619 E = Values.end(); I != E; ++I) {
3620 for (std::vector<unsigned>::iterator II = I->second.begin(),
3621 EE = I->second.end(); II != EE; ++II)
3622 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
3625 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3626 &MaskVec[0], MaskVec.size());
3628 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3629 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
3630 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
3631 SmallVector<SDOperand, 8> Ops;
3632 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3633 E = Values.end(); I != E; ++I) {
3634 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3638 Ops.push_back(ShuffleMask);
3640 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
3641 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
3642 &Ops[0], Ops.size());
3646 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
3647 // aligned object on the stack, store each element into it, then load
3648 // the result as a vector.
3649 MVT::ValueType VT = Node->getValueType(0);
3650 // Create the stack frame object.
3651 SDOperand FIPtr = CreateStackTemporary(VT);
3653 // Emit a store of each element to the stack slot.
3654 SmallVector<SDOperand, 8> Stores;
3655 unsigned TypeByteSize =
3656 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
3657 unsigned VectorSize = MVT::getSizeInBits(VT)/8;
3658 // Store (in the right endianness) the elements to memory.
3659 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3660 // Ignore undef elements.
3661 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3663 unsigned Offset = TypeByteSize*i;
3665 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
3666 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
3668 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
3669 DAG.getSrcValue(NULL)));
3672 SDOperand StoreChain;
3673 if (!Stores.empty()) // Not all undef elements?
3674 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3675 &Stores[0], Stores.size());
3677 StoreChain = DAG.getEntryNode();
3679 // Result is a load from the stack slot.
3680 return DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0));
3683 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
3684 /// specified value type.
3685 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
3686 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3687 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
3688 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
3689 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
3692 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
3693 SDOperand Op, SDOperand Amt,
3694 SDOperand &Lo, SDOperand &Hi) {
3695 // Expand the subcomponents.
3696 SDOperand LHSL, LHSH;
3697 ExpandOp(Op, LHSL, LHSH);
3699 SDOperand Ops[] = { LHSL, LHSH, Amt };
3700 MVT::ValueType VT = LHSL.getValueType();
3701 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
3702 Hi = Lo.getValue(1);
3706 /// ExpandShift - Try to find a clever way to expand this shift operation out to
3707 /// smaller elements. If we can't find a way that is more efficient than a
3708 /// libcall on this target, return false. Otherwise, return true with the
3709 /// low-parts expanded into Lo and Hi.
3710 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3711 SDOperand &Lo, SDOperand &Hi) {
3712 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3713 "This is not a shift!");
3715 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3716 SDOperand ShAmt = LegalizeOp(Amt);
3717 MVT::ValueType ShTy = ShAmt.getValueType();
3718 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3719 unsigned NVTBits = MVT::getSizeInBits(NVT);
3721 // Handle the case when Amt is an immediate. Other cases are currently broken
3722 // and are disabled.
3723 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3724 unsigned Cst = CN->getValue();
3725 // Expand the incoming operand to be shifted, so that we have its parts
3727 ExpandOp(Op, InL, InH);
3731 Lo = DAG.getConstant(0, NVT);
3732 Hi = DAG.getConstant(0, NVT);
3733 } else if (Cst > NVTBits) {
3734 Lo = DAG.getConstant(0, NVT);
3735 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
3736 } else if (Cst == NVTBits) {
3737 Lo = DAG.getConstant(0, NVT);
3740 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
3741 Hi = DAG.getNode(ISD::OR, NVT,
3742 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
3743 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
3748 Lo = DAG.getConstant(0, NVT);
3749 Hi = DAG.getConstant(0, NVT);
3750 } else if (Cst > NVTBits) {
3751 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
3752 Hi = DAG.getConstant(0, NVT);
3753 } else if (Cst == NVTBits) {
3755 Hi = DAG.getConstant(0, NVT);
3757 Lo = DAG.getNode(ISD::OR, NVT,
3758 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3759 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3760 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
3765 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
3766 DAG.getConstant(NVTBits-1, ShTy));
3767 } else if (Cst > NVTBits) {
3768 Lo = DAG.getNode(ISD::SRA, NVT, InH,
3769 DAG.getConstant(Cst-NVTBits, ShTy));
3770 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3771 DAG.getConstant(NVTBits-1, ShTy));
3772 } else if (Cst == NVTBits) {
3774 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3775 DAG.getConstant(NVTBits-1, ShTy));
3777 Lo = DAG.getNode(ISD::OR, NVT,
3778 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3779 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3780 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
3786 // Okay, the shift amount isn't constant. However, if we can tell that it is
3787 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
3788 uint64_t Mask = NVTBits, KnownZero, KnownOne;
3789 TLI.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
3791 // If we know that the high bit of the shift amount is one, then we can do
3792 // this as a couple of simple shifts.
3793 if (KnownOne & Mask) {
3794 // Mask out the high bit, which we know is set.
3795 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
3796 DAG.getConstant(NVTBits-1, Amt.getValueType()));
3798 // Expand the incoming operand to be shifted, so that we have its parts
3800 ExpandOp(Op, InL, InH);
3803 Lo = DAG.getConstant(0, NVT); // Low part is zero.
3804 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
3807 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
3808 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
3811 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
3812 DAG.getConstant(NVTBits-1, Amt.getValueType()));
3813 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
3818 // If we know that the high bit of the shift amount is zero, then we can do
3819 // this as a couple of simple shifts.
3820 if (KnownZero & Mask) {
3822 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
3823 DAG.getConstant(NVTBits, Amt.getValueType()),
3826 // Expand the incoming operand to be shifted, so that we have its parts
3828 ExpandOp(Op, InL, InH);
3831 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
3832 Hi = DAG.getNode(ISD::OR, NVT,
3833 DAG.getNode(ISD::SHL, NVT, InH, Amt),
3834 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
3837 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
3838 Lo = DAG.getNode(ISD::OR, NVT,
3839 DAG.getNode(ISD::SRL, NVT, InL, Amt),
3840 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
3843 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
3844 Lo = DAG.getNode(ISD::OR, NVT,
3845 DAG.getNode(ISD::SRL, NVT, InL, Amt),
3846 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
3855 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
3856 // does not fit into a register, return the lo part and set the hi part to the
3857 // by-reg argument. If it does fit into a single register, return the result
3858 // and leave the Hi part unset.
3859 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3861 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
3862 // The input chain to this libcall is the entry node of the function.
3863 // Legalizing the call will automatically add the previous call to the
3865 SDOperand InChain = DAG.getEntryNode();
3867 TargetLowering::ArgListTy Args;
3868 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3869 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3870 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3871 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3873 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3875 // Splice the libcall in wherever FindInputOutputChains tells us to.
3876 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3877 std::pair<SDOperand,SDOperand> CallInfo =
3878 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3881 // Legalize the call sequence, starting with the chain. This will advance
3882 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
3883 // was added by LowerCallTo (guaranteeing proper serialization of calls).
3884 LegalizeOp(CallInfo.second);
3886 switch (getTypeAction(CallInfo.first.getValueType())) {
3887 default: assert(0 && "Unknown thing");
3889 Result = CallInfo.first;
3892 ExpandOp(CallInfo.first, Result, Hi);
3899 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3900 /// destination type is legal.
3901 SDOperand SelectionDAGLegalize::
3902 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3903 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3904 assert(getTypeAction(Source.getValueType()) == Expand &&
3905 "This is not an expansion!");
3906 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3909 assert(Source.getValueType() == MVT::i64 &&
3910 "This only works for 64-bit -> FP");
3911 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3912 // incoming integer is set. To handle this, we dynamically test to see if
3913 // it is set, and, if so, add a fudge factor.
3915 ExpandOp(Source, Lo, Hi);
3917 // If this is unsigned, and not supported, first perform the conversion to
3918 // signed, then adjust the result if the sign bit is set.
3919 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3920 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3922 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3923 DAG.getConstant(0, Hi.getValueType()),
3925 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3926 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3927 SignSet, Four, Zero);
3928 uint64_t FF = 0x5f800000ULL;
3929 if (TLI.isLittleEndian()) FF <<= 32;
3930 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3932 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3933 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3934 SDOperand FudgeInReg;
3935 if (DestTy == MVT::f32)
3936 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3937 DAG.getSrcValue(NULL));
3939 assert(DestTy == MVT::f64 && "Unexpected conversion");
3940 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3941 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
3943 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3946 // Check to see if the target has a custom way to lower this. If so, use it.
3947 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3948 default: assert(0 && "This action not implemented for this operation!");
3949 case TargetLowering::Legal:
3950 case TargetLowering::Expand:
3951 break; // This case is handled below.
3952 case TargetLowering::Custom: {
3953 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3956 return LegalizeOp(NV);
3957 break; // The target decided this was legal after all
3961 // Expand the source, then glue it back together for the call. We must expand
3962 // the source in case it is shared (this pass of legalize must traverse it).
3963 SDOperand SrcLo, SrcHi;
3964 ExpandOp(Source, SrcLo, SrcHi);
3965 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
3967 const char *FnName = 0;
3968 if (DestTy == MVT::f32)
3969 FnName = "__floatdisf";
3971 assert(DestTy == MVT::f64 && "Unknown fp value type!");
3972 FnName = "__floatdidf";
3975 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
3976 SDOperand UnusedHiPart;
3977 return ExpandLibCall(FnName, Source.Val, UnusedHiPart);
3980 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
3981 /// INT_TO_FP operation of the specified operand when the target requests that
3982 /// we expand it. At this point, we know that the result and operand types are
3983 /// legal for the target.
3984 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
3986 MVT::ValueType DestVT) {
3987 if (Op0.getValueType() == MVT::i32) {
3988 // simple 32-bit [signed|unsigned] integer to float/double expansion
3990 // get the stack frame index of a 8 byte buffer
3991 MachineFunction &MF = DAG.getMachineFunction();
3992 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3993 // get address of 8 byte buffer
3994 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3995 // word offset constant for Hi/Lo address computation
3996 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
3997 // set up Hi and Lo (into buffer) address based on endian
3998 SDOperand Hi = StackSlot;
3999 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4000 if (TLI.isLittleEndian())
4003 // if signed map to unsigned space
4004 SDOperand Op0Mapped;
4006 // constant used to invert sign bit (signed to unsigned mapping)
4007 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4008 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4012 // store the lo of the constructed double - based on integer input
4013 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4014 Op0Mapped, Lo, DAG.getSrcValue(NULL));
4015 // initial hi portion of constructed double
4016 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4017 // store the hi of the constructed double - biased exponent
4018 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, DAG.getSrcValue(NULL));
4019 // load the constructed double
4020 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
4021 DAG.getSrcValue(NULL));
4022 // FP constant to bias correct the final result
4023 SDOperand Bias = DAG.getConstantFP(isSigned ?
4024 BitsToDouble(0x4330000080000000ULL)
4025 : BitsToDouble(0x4330000000000000ULL),
4027 // subtract the bias
4028 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4031 // handle final rounding
4032 if (DestVT == MVT::f64) {
4036 // if f32 then cast to f32
4037 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
4041 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4042 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4044 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4045 DAG.getConstant(0, Op0.getValueType()),
4047 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4048 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4049 SignSet, Four, Zero);
4051 // If the sign bit of the integer is set, the large number will be treated
4052 // as a negative number. To counteract this, the dynamic code adds an
4053 // offset depending on the data type.
4055 switch (Op0.getValueType()) {
4056 default: assert(0 && "Unsupported integer type!");
4057 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4058 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4059 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4060 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4062 if (TLI.isLittleEndian()) FF <<= 32;
4063 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
4065 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4066 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4067 SDOperand FudgeInReg;
4068 if (DestVT == MVT::f32)
4069 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
4070 DAG.getSrcValue(NULL));
4072 assert(DestVT == MVT::f64 && "Unexpected conversion");
4073 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
4074 DAG.getEntryNode(), CPIdx,
4075 DAG.getSrcValue(NULL), MVT::f32));
4078 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4081 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4082 /// *INT_TO_FP operation of the specified operand when the target requests that
4083 /// we promote it. At this point, we know that the result and operand types are
4084 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4085 /// operation that takes a larger input.
4086 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4087 MVT::ValueType DestVT,
4089 // First step, figure out the appropriate *INT_TO_FP operation to use.
4090 MVT::ValueType NewInTy = LegalOp.getValueType();
4092 unsigned OpToUse = 0;
4094 // Scan for the appropriate larger type to use.
4096 NewInTy = (MVT::ValueType)(NewInTy+1);
4097 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4099 // If the target supports SINT_TO_FP of this type, use it.
4100 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4102 case TargetLowering::Legal:
4103 if (!TLI.isTypeLegal(NewInTy))
4104 break; // Can't use this datatype.
4106 case TargetLowering::Custom:
4107 OpToUse = ISD::SINT_TO_FP;
4111 if (isSigned) continue;
4113 // If the target supports UINT_TO_FP of this type, use it.
4114 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4116 case TargetLowering::Legal:
4117 if (!TLI.isTypeLegal(NewInTy))
4118 break; // Can't use this datatype.
4120 case TargetLowering::Custom:
4121 OpToUse = ISD::UINT_TO_FP;
4126 // Otherwise, try a larger type.
4129 // Okay, we found the operation and type to use. Zero extend our input to the
4130 // desired type then run the operation on it.
4131 return DAG.getNode(OpToUse, DestVT,
4132 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4136 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4137 /// FP_TO_*INT operation of the specified operand when the target requests that
4138 /// we promote it. At this point, we know that the result and operand types are
4139 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4140 /// operation that returns a larger result.
4141 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4142 MVT::ValueType DestVT,
4144 // First step, figure out the appropriate FP_TO*INT operation to use.
4145 MVT::ValueType NewOutTy = DestVT;
4147 unsigned OpToUse = 0;
4149 // Scan for the appropriate larger type to use.
4151 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4152 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4154 // If the target supports FP_TO_SINT returning this type, use it.
4155 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4157 case TargetLowering::Legal:
4158 if (!TLI.isTypeLegal(NewOutTy))
4159 break; // Can't use this datatype.
4161 case TargetLowering::Custom:
4162 OpToUse = ISD::FP_TO_SINT;
4167 // If the target supports FP_TO_UINT of this type, use it.
4168 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4170 case TargetLowering::Legal:
4171 if (!TLI.isTypeLegal(NewOutTy))
4172 break; // Can't use this datatype.
4174 case TargetLowering::Custom:
4175 OpToUse = ISD::FP_TO_UINT;
4180 // Otherwise, try a larger type.
4183 // Okay, we found the operation and type to use. Truncate the result of the
4184 // extended FP_TO_*INT operation to the desired size.
4185 return DAG.getNode(ISD::TRUNCATE, DestVT,
4186 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4189 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4191 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4192 MVT::ValueType VT = Op.getValueType();
4193 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4194 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4196 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4198 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4199 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4200 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4202 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4203 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4204 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4205 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4206 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4207 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4208 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4209 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4210 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4212 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4213 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4214 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4215 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4216 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4217 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4218 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4219 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4220 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4221 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4222 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4223 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4224 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4225 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4226 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4227 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4228 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4229 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4230 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4231 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4232 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4236 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4238 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4240 default: assert(0 && "Cannot expand this yet!");
4242 static const uint64_t mask[6] = {
4243 0x5555555555555555ULL, 0x3333333333333333ULL,
4244 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4245 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4247 MVT::ValueType VT = Op.getValueType();
4248 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4249 unsigned len = getSizeInBits(VT);
4250 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4251 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4252 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4253 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4254 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4255 DAG.getNode(ISD::AND, VT,
4256 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4261 // for now, we do this:
4262 // x = x | (x >> 1);
4263 // x = x | (x >> 2);
4265 // x = x | (x >>16);
4266 // x = x | (x >>32); // for 64-bit input
4267 // return popcount(~x);
4269 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4270 MVT::ValueType VT = Op.getValueType();
4271 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4272 unsigned len = getSizeInBits(VT);
4273 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4274 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4275 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4277 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4278 return DAG.getNode(ISD::CTPOP, VT, Op);
4281 // for now, we use: { return popcount(~x & (x - 1)); }
4282 // unless the target has ctlz but not ctpop, in which case we use:
4283 // { return 32 - nlz(~x & (x-1)); }
4284 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4285 MVT::ValueType VT = Op.getValueType();
4286 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4287 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4288 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4289 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4290 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4291 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4292 TLI.isOperationLegal(ISD::CTLZ, VT))
4293 return DAG.getNode(ISD::SUB, VT,
4294 DAG.getConstant(getSizeInBits(VT), VT),
4295 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4296 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4301 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4302 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4303 /// LegalizeNodes map is filled in for any results that are not expanded, the
4304 /// ExpandedNodes map is filled in for any results that are expanded, and the
4305 /// Lo/Hi values are returned.
4306 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4307 MVT::ValueType VT = Op.getValueType();
4308 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4309 SDNode *Node = Op.Val;
4310 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4311 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
4312 "Cannot expand FP values!");
4313 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
4314 "Cannot expand to FP value or to larger int value!");
4316 // See if we already expanded it.
4317 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4318 = ExpandedNodes.find(Op);
4319 if (I != ExpandedNodes.end()) {
4320 Lo = I->second.first;
4321 Hi = I->second.second;
4325 switch (Node->getOpcode()) {
4326 case ISD::CopyFromReg:
4327 assert(0 && "CopyFromReg must be legal!");
4330 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
4332 assert(0 && "Do not know how to expand this operator!");
4335 Lo = DAG.getNode(ISD::UNDEF, NVT);
4336 Hi = DAG.getNode(ISD::UNDEF, NVT);
4338 case ISD::Constant: {
4339 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4340 Lo = DAG.getConstant(Cst, NVT);
4341 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4344 case ISD::BUILD_PAIR:
4345 // Return the operands.
4346 Lo = Node->getOperand(0);
4347 Hi = Node->getOperand(1);
4350 case ISD::SIGN_EXTEND_INREG:
4351 ExpandOp(Node->getOperand(0), Lo, Hi);
4352 // sext_inreg the low part if needed.
4353 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4355 // The high part gets the sign extension from the lo-part. This handles
4356 // things like sextinreg V:i64 from i8.
4357 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4358 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4359 TLI.getShiftAmountTy()));
4363 ExpandOp(Node->getOperand(0), Lo, Hi);
4364 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4365 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4371 ExpandOp(Node->getOperand(0), Lo, Hi);
4372 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4373 DAG.getNode(ISD::CTPOP, NVT, Lo),
4374 DAG.getNode(ISD::CTPOP, NVT, Hi));
4375 Hi = DAG.getConstant(0, NVT);
4379 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4380 ExpandOp(Node->getOperand(0), Lo, Hi);
4381 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4382 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4383 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4385 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4386 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4388 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4389 Hi = DAG.getConstant(0, NVT);
4394 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4395 ExpandOp(Node->getOperand(0), Lo, Hi);
4396 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4397 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4398 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4400 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4401 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4403 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4404 Hi = DAG.getConstant(0, NVT);
4409 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4410 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4411 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4412 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4414 // Remember that we legalized the chain.
4415 Hi = LegalizeOp(Hi);
4416 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4417 if (!TLI.isLittleEndian())
4423 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4424 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4425 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
4427 // Increment the pointer to the other half.
4428 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4429 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4430 getIntPtrConstant(IncrementSize));
4431 // FIXME: This creates a bogus srcvalue!
4432 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
4434 // Build a factor node to remember that this load is independent of the
4436 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4439 // Remember that we legalized the chain.
4440 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4441 if (!TLI.isLittleEndian())
4447 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
4448 SDOperand LL, LH, RL, RH;
4449 ExpandOp(Node->getOperand(0), LL, LH);
4450 ExpandOp(Node->getOperand(1), RL, RH);
4451 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4452 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4456 SDOperand LL, LH, RL, RH;
4457 ExpandOp(Node->getOperand(1), LL, LH);
4458 ExpandOp(Node->getOperand(2), RL, RH);
4459 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4460 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4463 case ISD::SELECT_CC: {
4464 SDOperand TL, TH, FL, FH;
4465 ExpandOp(Node->getOperand(2), TL, TH);
4466 ExpandOp(Node->getOperand(3), FL, FH);
4467 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4468 Node->getOperand(1), TL, FL, Node->getOperand(4));
4469 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4470 Node->getOperand(1), TH, FH, Node->getOperand(4));
4474 SDOperand Chain = Node->getOperand(0);
4475 SDOperand Ptr = Node->getOperand(1);
4476 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4477 ISD::LoadExtType LType = (ISD::LoadExtType)Node->getConstantOperandVal(4);
4480 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4482 Lo = DAG.getExtLoad(LType, NVT, Chain, Ptr, Node->getOperand(2), EVT);
4484 // Remember that we legalized the chain.
4485 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4487 if (LType == ISD::SEXTLOAD) {
4488 // The high part is obtained by SRA'ing all but one of the bits of the lo
4490 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4491 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
4492 TLI.getShiftAmountTy()));
4493 } else if (LType == ISD::ZEXTLOAD) {
4494 // The high part is just a zero.
4495 Hi = DAG.getConstant(0, NVT);
4496 } else /* if (LType == ISD::EXTLOAD) */ {
4497 // The high part is undefined.
4498 Hi = DAG.getNode(ISD::UNDEF, NVT);
4502 case ISD::ANY_EXTEND:
4503 // The low part is any extension of the input (which degenerates to a copy).
4504 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4505 // The high part is undefined.
4506 Hi = DAG.getNode(ISD::UNDEF, NVT);
4508 case ISD::SIGN_EXTEND: {
4509 // The low part is just a sign extension of the input (which degenerates to
4511 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4513 // The high part is obtained by SRA'ing all but one of the bits of the lo
4515 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4516 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4517 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4520 case ISD::ZERO_EXTEND:
4521 // The low part is just a zero extension of the input (which degenerates to
4523 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4525 // The high part is just a zero.
4526 Hi = DAG.getConstant(0, NVT);
4529 case ISD::BIT_CONVERT: {
4531 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
4532 // If the target wants to, allow it to lower this itself.
4533 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4534 case Expand: assert(0 && "cannot expand FP!");
4535 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
4536 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
4538 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
4541 // Turn this into a load/store pair by default.
4543 Tmp = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
4545 ExpandOp(Tmp, Lo, Hi);
4549 case ISD::READCYCLECOUNTER:
4550 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
4551 TargetLowering::Custom &&
4552 "Must custom expand ReadCycleCounter");
4553 Lo = TLI.LowerOperation(Op, DAG);
4554 assert(Lo.Val && "Node must be custom expanded!");
4555 Hi = Lo.getValue(1);
4556 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
4557 LegalizeOp(Lo.getValue(2)));
4560 // These operators cannot be expanded directly, emit them as calls to
4561 // library functions.
4562 case ISD::FP_TO_SINT:
4563 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
4565 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4566 case Expand: assert(0 && "cannot expand FP!");
4567 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4568 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4571 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
4573 // Now that the custom expander is done, expand the result, which is still
4576 ExpandOp(Op, Lo, Hi);
4581 if (Node->getOperand(0).getValueType() == MVT::f32)
4582 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
4584 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
4587 case ISD::FP_TO_UINT:
4588 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
4590 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4591 case Expand: assert(0 && "cannot expand FP!");
4592 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4593 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4596 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
4598 // Now that the custom expander is done, expand the result.
4600 ExpandOp(Op, Lo, Hi);
4605 if (Node->getOperand(0).getValueType() == MVT::f32)
4606 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
4608 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
4612 // If the target wants custom lowering, do so.
4613 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4614 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
4615 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
4616 Op = TLI.LowerOperation(Op, DAG);
4618 // Now that the custom expander is done, expand the result, which is
4620 ExpandOp(Op, Lo, Hi);
4625 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
4626 // this X << 1 as X+X.
4627 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
4628 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
4629 TLI.isOperationLegal(ISD::ADDE, NVT)) {
4630 SDOperand LoOps[2], HiOps[3];
4631 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
4632 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
4633 LoOps[1] = LoOps[0];
4634 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
4636 HiOps[1] = HiOps[0];
4637 HiOps[2] = Lo.getValue(1);
4638 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
4643 // If we can emit an efficient shift operation, do so now.
4644 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4647 // If this target supports SHL_PARTS, use it.
4648 TargetLowering::LegalizeAction Action =
4649 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
4650 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4651 Action == TargetLowering::Custom) {
4652 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4656 // Otherwise, emit a libcall.
4657 Lo = ExpandLibCall("__ashldi3", Node, Hi);
4662 // If the target wants custom lowering, do so.
4663 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4664 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
4665 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
4666 Op = TLI.LowerOperation(Op, DAG);
4668 // Now that the custom expander is done, expand the result, which is
4670 ExpandOp(Op, Lo, Hi);
4675 // If we can emit an efficient shift operation, do so now.
4676 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
4679 // If this target supports SRA_PARTS, use it.
4680 TargetLowering::LegalizeAction Action =
4681 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
4682 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4683 Action == TargetLowering::Custom) {
4684 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4688 // Otherwise, emit a libcall.
4689 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
4694 // If the target wants custom lowering, do so.
4695 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4696 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
4697 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
4698 Op = TLI.LowerOperation(Op, DAG);
4700 // Now that the custom expander is done, expand the result, which is
4702 ExpandOp(Op, Lo, Hi);
4707 // If we can emit an efficient shift operation, do so now.
4708 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4711 // If this target supports SRL_PARTS, use it.
4712 TargetLowering::LegalizeAction Action =
4713 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
4714 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4715 Action == TargetLowering::Custom) {
4716 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4720 // Otherwise, emit a libcall.
4721 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
4727 // If the target wants to custom expand this, let them.
4728 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
4729 TargetLowering::Custom) {
4730 Op = TLI.LowerOperation(Op, DAG);
4732 ExpandOp(Op, Lo, Hi);
4737 // Expand the subcomponents.
4738 SDOperand LHSL, LHSH, RHSL, RHSH;
4739 ExpandOp(Node->getOperand(0), LHSL, LHSH);
4740 ExpandOp(Node->getOperand(1), RHSL, RHSH);
4741 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
4742 SDOperand LoOps[2], HiOps[3];
4747 if (Node->getOpcode() == ISD::ADD) {
4748 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
4749 HiOps[2] = Lo.getValue(1);
4750 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
4752 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
4753 HiOps[2] = Lo.getValue(1);
4754 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
4759 // If the target wants to custom expand this, let them.
4760 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
4761 SDOperand New = TLI.LowerOperation(Op, DAG);
4763 ExpandOp(New, Lo, Hi);
4768 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
4769 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
4770 bool UseLibCall = true;
4771 if (HasMULHS || HasMULHU) {
4772 SDOperand LL, LH, RL, RH;
4773 ExpandOp(Node->getOperand(0), LL, LH);
4774 ExpandOp(Node->getOperand(1), RL, RH);
4775 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
4776 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
4777 // extended the sign bit of the low half through the upper half, and if so
4778 // emit a MULHS instead of the alternate sequence that is valid for any
4779 // i64 x i64 multiply.
4781 // is RH an extension of the sign bit of RL?
4782 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
4783 RH.getOperand(1).getOpcode() == ISD::Constant &&
4784 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
4785 // is LH an extension of the sign bit of LL?
4786 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
4787 LH.getOperand(1).getOpcode() == ISD::Constant &&
4788 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
4789 // FIXME: Move this to the dag combiner.
4792 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4794 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
4796 } else if (HasMULHU) {
4798 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4801 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
4802 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
4803 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
4804 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
4805 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
4810 Lo = ExpandLibCall("__muldi3" , Node, Hi);
4813 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
4814 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
4815 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
4816 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
4819 // Make sure the resultant values have been legalized themselves, unless this
4820 // is a type that requires multi-step expansion.
4821 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
4822 Lo = LegalizeOp(Lo);
4823 Hi = LegalizeOp(Hi);
4826 // Remember in a map if the values will be reused later.
4828 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4829 assert(isNew && "Value already expanded?!?");
4832 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
4833 /// two smaller values of MVT::Vector type.
4834 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
4836 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
4837 SDNode *Node = Op.Val;
4838 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
4839 assert(NumElements > 1 && "Cannot split a single element vector!");
4840 unsigned NewNumElts = NumElements/2;
4841 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
4842 SDOperand TypeNode = *(Node->op_end()-1);
4844 // See if we already split it.
4845 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4846 = SplitNodes.find(Op);
4847 if (I != SplitNodes.end()) {
4848 Lo = I->second.first;
4849 Hi = I->second.second;
4853 switch (Node->getOpcode()) {
4858 assert(0 && "Unhandled operation in SplitVectorOp!");
4859 case ISD::VBUILD_VECTOR: {
4860 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
4861 Node->op_begin()+NewNumElts);
4862 LoOps.push_back(NewNumEltsNode);
4863 LoOps.push_back(TypeNode);
4864 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size());
4866 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
4868 HiOps.push_back(NewNumEltsNode);
4869 HiOps.push_back(TypeNode);
4870 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size());
4881 SDOperand LL, LH, RL, RH;
4882 SplitVectorOp(Node->getOperand(0), LL, LH);
4883 SplitVectorOp(Node->getOperand(1), RL, RH);
4885 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
4886 NewNumEltsNode, TypeNode);
4887 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
4888 NewNumEltsNode, TypeNode);
4892 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4893 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4894 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4896 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4897 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
4898 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4899 getIntPtrConstant(IncrementSize));
4900 // FIXME: This creates a bogus srcvalue!
4901 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4903 // Build a factor node to remember that this load is independent of the
4905 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4908 // Remember that we legalized the chain.
4909 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4912 case ISD::VBIT_CONVERT: {
4913 // We know the result is a vector. The input may be either a vector or a
4915 if (Op.getOperand(0).getValueType() != MVT::Vector) {
4916 // Lower to a store/load. FIXME: this could be improved probably.
4917 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
4919 SDOperand St = DAG.getStore(DAG.getEntryNode(),
4920 Op.getOperand(0), Ptr, DAG.getSrcValue(0));
4921 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4922 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0));
4923 SplitVectorOp(St, Lo, Hi);
4925 // If the input is a vector type, we have to either scalarize it, pack it
4926 // or convert it based on whether the input vector type is legal.
4927 SDNode *InVal = Node->getOperand(0).Val;
4929 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
4930 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
4932 // If the input is from a single element vector, scalarize the vector,
4933 // then treat like a scalar.
4934 if (NumElems == 1) {
4935 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT);
4936 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar,
4937 Op.getOperand(1), Op.getOperand(2));
4938 SplitVectorOp(Scalar, Lo, Hi);
4940 // Split the input vector.
4941 SplitVectorOp(Op.getOperand(0), Lo, Hi);
4943 // Convert each of the pieces now.
4944 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo,
4945 NewNumEltsNode, TypeNode);
4946 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi,
4947 NewNumEltsNode, TypeNode);
4954 // Remember in a map if the values will be reused later.
4956 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4957 assert(isNew && "Value already expanded?!?");
4961 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
4962 /// equivalent operation that returns a scalar (e.g. F32) or packed value
4963 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
4964 /// type for the result.
4965 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
4966 MVT::ValueType NewVT) {
4967 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
4968 SDNode *Node = Op.Val;
4970 // See if we already packed it.
4971 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
4972 if (I != PackedNodes.end()) return I->second;
4975 switch (Node->getOpcode()) {
4978 Node->dump(); std::cerr << "\n";
4980 assert(0 && "Unknown vector operation in PackVectorOp!");
4989 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
4991 PackVectorOp(Node->getOperand(0), NewVT),
4992 PackVectorOp(Node->getOperand(1), NewVT));
4995 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
4996 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
4998 Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(2));
5000 // Remember that we legalized the chain.
5001 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
5004 case ISD::VBUILD_VECTOR:
5005 if (Node->getOperand(0).getValueType() == NewVT) {
5006 // Returning a scalar?
5007 Result = Node->getOperand(0);
5009 // Returning a BUILD_VECTOR?
5011 // If all elements of the build_vector are undefs, return an undef.
5012 bool AllUndef = true;
5013 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i)
5014 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) {
5019 Result = DAG.getNode(ISD::UNDEF, NewVT);
5021 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(),
5022 Node->getNumOperands()-2);
5026 case ISD::VINSERT_VECTOR_ELT:
5027 if (!MVT::isVector(NewVT)) {
5028 // Returning a scalar? Must be the inserted element.
5029 Result = Node->getOperand(1);
5031 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
5032 PackVectorOp(Node->getOperand(0), NewVT),
5033 Node->getOperand(1), Node->getOperand(2));
5036 case ISD::VVECTOR_SHUFFLE:
5037 if (!MVT::isVector(NewVT)) {
5038 // Returning a scalar? Figure out if it is the LHS or RHS and return it.
5039 SDOperand EltNum = Node->getOperand(2).getOperand(0);
5040 if (cast<ConstantSDNode>(EltNum)->getValue())
5041 Result = PackVectorOp(Node->getOperand(1), NewVT);
5043 Result = PackVectorOp(Node->getOperand(0), NewVT);
5045 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index
5046 // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
5047 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
5048 Node->getOperand(2).Val->op_end()-2);
5049 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
5050 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT,
5051 Node->getOperand(2).Val->op_begin(),
5052 Node->getOperand(2).Val->getNumOperands()-2);
5054 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
5055 PackVectorOp(Node->getOperand(0), NewVT),
5056 PackVectorOp(Node->getOperand(1), NewVT), BV);
5059 case ISD::VBIT_CONVERT:
5060 if (Op.getOperand(0).getValueType() != MVT::Vector)
5061 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
5063 // If the input is a vector type, we have to either scalarize it, pack it
5064 // or convert it based on whether the input vector type is legal.
5065 SDNode *InVal = Node->getOperand(0).Val;
5067 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
5068 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
5070 // Figure out if there is a Packed type corresponding to this Vector
5071 // type. If so, convert to the packed type.
5072 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
5073 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
5074 // Turn this into a bit convert of the packed input.
5075 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5076 PackVectorOp(Node->getOperand(0), TVT));
5078 } else if (NumElems == 1) {
5079 // Turn this into a bit convert of the scalar input.
5080 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5081 PackVectorOp(Node->getOperand(0), EVT));
5085 assert(0 && "Cast from unsupported vector type not implemented yet!");
5090 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
5091 PackVectorOp(Op.getOperand(1), NewVT),
5092 PackVectorOp(Op.getOperand(2), NewVT));
5096 if (TLI.isTypeLegal(NewVT))
5097 Result = LegalizeOp(Result);
5098 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
5099 assert(isNew && "Value already packed?");
5104 // SelectionDAG::Legalize - This is the entry point for the file.
5106 void SelectionDAG::Legalize() {
5107 if (ViewLegalizeDAGs) viewGraph();
5109 /// run - This is the main entry point to this class.
5111 SelectionDAGLegalize(*this).LegalizeDAG();