1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/Target/TargetFrameInfo.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/Target/TargetData.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/Support/MathExtras.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/ADT/SmallPtrSet.h"
37 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
38 cl::desc("Pop up a window to show dags before legalize"));
40 static const bool ViewLegalizeDAGs = 0;
43 //===----------------------------------------------------------------------===//
44 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
45 /// hacks on it until the target machine can handle it. This involves
46 /// eliminating value sizes the machine cannot handle (promoting small sizes to
47 /// large sizes or splitting up large values into small values) as well as
48 /// eliminating operations the machine cannot handle.
50 /// This code also does a small amount of optimization and recognition of idioms
51 /// as part of its processing. For example, if a target does not support a
52 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
53 /// will attempt merge setcc and brc instructions into brcc's.
56 class VISIBILITY_HIDDEN SelectionDAGLegalize {
60 // Libcall insertion helpers.
62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
63 /// legalized. We use this to ensure that calls are properly serialized
64 /// against each other, including inserted libcalls.
65 SDOperand LastCALLSEQ_END;
67 /// IsLegalizingCall - This member is used *only* for purposes of providing
68 /// helpful assertions that a libcall isn't created while another call is
69 /// being legalized (which could lead to non-serialized call sequences).
70 bool IsLegalizingCall;
73 Legal, // The target natively supports this operation.
74 Promote, // This operation should be executed in a larger type.
75 Expand // Try to expand this to other ops, otherwise use a libcall.
78 /// ValueTypeActions - This is a bitvector that contains two bits for each
79 /// value type, where the two bits correspond to the LegalizeAction enum.
80 /// This can be queried with "getTypeAction(VT)".
81 TargetLowering::ValueTypeActionImpl ValueTypeActions;
83 /// LegalizedNodes - For nodes that are of legal width, and that have more
84 /// than one use, this map indicates what regularized operand to use. This
85 /// allows us to avoid legalizing the same thing more than once.
86 DenseMap<SDOperand, SDOperand> LegalizedNodes;
88 /// PromotedNodes - For nodes that are below legal width, and that have more
89 /// than one use, this map indicates what promoted value to use. This allows
90 /// us to avoid promoting the same thing more than once.
91 DenseMap<SDOperand, SDOperand> PromotedNodes;
93 /// ExpandedNodes - For nodes that need to be expanded this map indicates
94 /// which which operands are the expanded version of the input. This allows
95 /// us to avoid expanding the same node more than once.
96 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
98 /// SplitNodes - For vector nodes that need to be split, this map indicates
99 /// which which operands are the split version of the input. This allows us
100 /// to avoid splitting the same node more than once.
101 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
103 /// ScalarizedNodes - For nodes that need to be converted from vector types to
104 /// scalar types, this contains the mapping of ones we have already
105 /// processed to the result.
106 std::map<SDOperand, SDOperand> ScalarizedNodes;
108 void AddLegalizedOperand(SDOperand From, SDOperand To) {
109 LegalizedNodes.insert(std::make_pair(From, To));
110 // If someone requests legalization of the new node, return itself.
112 LegalizedNodes.insert(std::make_pair(To, To));
114 void AddPromotedOperand(SDOperand From, SDOperand To) {
115 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
116 assert(isNew && "Got into the map somehow?");
117 // If someone requests legalization of the new node, return itself.
118 LegalizedNodes.insert(std::make_pair(To, To));
123 SelectionDAGLegalize(SelectionDAG &DAG);
125 /// getTypeAction - Return how we should legalize values of this type, either
126 /// it is already legal or we need to expand it into multiple registers of
127 /// smaller integer type, or we need to promote it to a larger type.
128 LegalizeAction getTypeAction(MVT::ValueType VT) const {
129 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
132 /// isTypeLegal - Return true if this type is legal on this target.
134 bool isTypeLegal(MVT::ValueType VT) const {
135 return getTypeAction(VT) == Legal;
141 /// HandleOp - Legalize, Promote, or Expand the specified operand as
142 /// appropriate for its type.
143 void HandleOp(SDOperand Op);
145 /// LegalizeOp - We know that the specified value has a legal type.
146 /// Recursively ensure that the operands have legal types, then return the
148 SDOperand LegalizeOp(SDOperand O);
150 /// PromoteOp - Given an operation that produces a value in an invalid type,
151 /// promote it to compute the value into a larger type. The produced value
152 /// will have the correct bits for the low portion of the register, but no
153 /// guarantee is made about the top bits: it may be zero, sign-extended, or
155 SDOperand PromoteOp(SDOperand O);
157 /// ExpandOp - Expand the specified SDOperand into its two component pieces
158 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
159 /// the LegalizeNodes map is filled in for any results that are not expanded,
160 /// the ExpandedNodes map is filled in for any results that are expanded, and
161 /// the Lo/Hi values are returned. This applies to integer types and Vector
163 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
165 /// SplitVectorOp - Given an operand of vector type, break it down into
166 /// two smaller values.
167 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
169 /// ScalarizeVectorOp - Given an operand of single-element vector type
170 /// (e.g. v1f32), convert it into the equivalent operation that returns a
171 /// scalar (e.g. f32) value.
172 SDOperand ScalarizeVectorOp(SDOperand O);
174 /// isShuffleLegal - Return true if a vector shuffle is legal with the
175 /// specified mask and type. Targets can specify exactly which masks they
176 /// support and the code generator is tasked with not creating illegal masks.
178 /// Note that this will also return true for shuffles that are promoted to a
181 /// If this is a legal shuffle, this method returns the (possibly promoted)
182 /// build_vector Mask. If it's not a legal shuffle, it returns null.
183 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
185 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
186 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
188 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
190 SDOperand CreateStackTemporary(MVT::ValueType VT);
192 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
194 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
197 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
198 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
199 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
200 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
202 MVT::ValueType DestVT);
203 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
205 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
208 SDOperand ExpandBSWAP(SDOperand Op);
209 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
210 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
211 SDOperand &Lo, SDOperand &Hi);
212 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
213 SDOperand &Lo, SDOperand &Hi);
215 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
216 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
218 SDOperand getIntPtrConstant(uint64_t Val) {
219 return DAG.getConstant(Val, TLI.getPointerTy());
224 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
225 /// specified mask and type. Targets can specify exactly which masks they
226 /// support and the code generator is tasked with not creating illegal masks.
228 /// Note that this will also return true for shuffles that are promoted to a
230 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
231 SDOperand Mask) const {
232 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
234 case TargetLowering::Legal:
235 case TargetLowering::Custom:
237 case TargetLowering::Promote: {
238 // If this is promoted to a different type, convert the shuffle mask and
239 // ask if it is legal in the promoted type!
240 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
242 // If we changed # elements, change the shuffle mask.
243 unsigned NumEltsGrowth =
244 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
245 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
246 if (NumEltsGrowth > 1) {
247 // Renumber the elements.
248 SmallVector<SDOperand, 8> Ops;
249 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
250 SDOperand InOp = Mask.getOperand(i);
251 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
252 if (InOp.getOpcode() == ISD::UNDEF)
253 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
255 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
256 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
260 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
266 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
269 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
270 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
271 ValueTypeActions(TLI.getValueTypeActions()) {
272 assert(MVT::LAST_VALUETYPE <= 32 &&
273 "Too many value types for ValueTypeActions to hold!");
276 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
277 /// contains all of a nodes operands before it contains the node.
278 static void ComputeTopDownOrdering(SelectionDAG &DAG,
279 SmallVector<SDNode*, 64> &Order) {
281 DenseMap<SDNode*, unsigned> Visited;
282 std::vector<SDNode*> Worklist;
283 Worklist.reserve(128);
285 // Compute ordering from all of the leaves in the graphs, those (like the
286 // entry node) that have no operands.
287 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
288 E = DAG.allnodes_end(); I != E; ++I) {
289 if (I->getNumOperands() == 0) {
291 Worklist.push_back(I);
295 while (!Worklist.empty()) {
296 SDNode *N = Worklist.back();
299 if (++Visited[N] != N->getNumOperands())
300 continue; // Haven't visited all operands yet
304 // Now that we have N in, add anything that uses it if all of their operands
306 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
308 Worklist.push_back(*UI);
311 assert(Order.size() == Visited.size() &&
313 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
314 "Error: DAG is cyclic!");
318 void SelectionDAGLegalize::LegalizeDAG() {
319 LastCALLSEQ_END = DAG.getEntryNode();
320 IsLegalizingCall = false;
322 // The legalize process is inherently a bottom-up recursive process (users
323 // legalize their uses before themselves). Given infinite stack space, we
324 // could just start legalizing on the root and traverse the whole graph. In
325 // practice however, this causes us to run out of stack space on large basic
326 // blocks. To avoid this problem, compute an ordering of the nodes where each
327 // node is only legalized after all of its operands are legalized.
328 SmallVector<SDNode*, 64> Order;
329 ComputeTopDownOrdering(DAG, Order);
331 for (unsigned i = 0, e = Order.size(); i != e; ++i)
332 HandleOp(SDOperand(Order[i], 0));
334 // Finally, it's possible the root changed. Get the new root.
335 SDOperand OldRoot = DAG.getRoot();
336 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
337 DAG.setRoot(LegalizedNodes[OldRoot]);
339 ExpandedNodes.clear();
340 LegalizedNodes.clear();
341 PromotedNodes.clear();
343 ScalarizedNodes.clear();
345 // Remove dead nodes now.
346 DAG.RemoveDeadNodes();
350 /// FindCallEndFromCallStart - Given a chained node that is part of a call
351 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
352 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
353 if (Node->getOpcode() == ISD::CALLSEQ_END)
355 if (Node->use_empty())
356 return 0; // No CallSeqEnd
358 // The chain is usually at the end.
359 SDOperand TheChain(Node, Node->getNumValues()-1);
360 if (TheChain.getValueType() != MVT::Other) {
361 // Sometimes it's at the beginning.
362 TheChain = SDOperand(Node, 0);
363 if (TheChain.getValueType() != MVT::Other) {
364 // Otherwise, hunt for it.
365 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
366 if (Node->getValueType(i) == MVT::Other) {
367 TheChain = SDOperand(Node, i);
371 // Otherwise, we walked into a node without a chain.
372 if (TheChain.getValueType() != MVT::Other)
377 for (SDNode::use_iterator UI = Node->use_begin(),
378 E = Node->use_end(); UI != E; ++UI) {
380 // Make sure to only follow users of our token chain.
382 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
383 if (User->getOperand(i) == TheChain)
384 if (SDNode *Result = FindCallEndFromCallStart(User))
390 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
391 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
392 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
393 assert(Node && "Didn't find callseq_start for a call??");
394 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
396 assert(Node->getOperand(0).getValueType() == MVT::Other &&
397 "Node doesn't have a token chain argument!");
398 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
401 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
402 /// see if any uses can reach Dest. If no dest operands can get to dest,
403 /// legalize them, legalize ourself, and return false, otherwise, return true.
405 /// Keep track of the nodes we fine that actually do lead to Dest in
406 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
408 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
409 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
410 if (N == Dest) return true; // N certainly leads to Dest :)
412 // If we've already processed this node and it does lead to Dest, there is no
413 // need to reprocess it.
414 if (NodesLeadingTo.count(N)) return true;
416 // If the first result of this node has been already legalized, then it cannot
418 switch (getTypeAction(N->getValueType(0))) {
420 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
423 if (PromotedNodes.count(SDOperand(N, 0))) return false;
426 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
430 // Okay, this node has not already been legalized. Check and legalize all
431 // operands. If none lead to Dest, then we can legalize this node.
432 bool OperandsLeadToDest = false;
433 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
434 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
435 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
437 if (OperandsLeadToDest) {
438 NodesLeadingTo.insert(N);
442 // Okay, this node looks safe, legalize it and return false.
443 HandleOp(SDOperand(N, 0));
447 /// HandleOp - Legalize, Promote, or Expand the specified operand as
448 /// appropriate for its type.
449 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
450 MVT::ValueType VT = Op.getValueType();
451 switch (getTypeAction(VT)) {
452 default: assert(0 && "Bad type action!");
453 case Legal: (void)LegalizeOp(Op); break;
454 case Promote: (void)PromoteOp(Op); break;
456 if (!MVT::isVector(VT)) {
457 // If this is an illegal scalar, expand it into its two component
460 if (Op.getOpcode() == ISD::TargetConstant)
461 break; // Allow illegal target nodes.
463 } else if (MVT::getVectorNumElements(VT) == 1) {
464 // If this is an illegal single element vector, convert it to a
466 (void)ScalarizeVectorOp(Op);
468 // Otherwise, this is an illegal multiple element vector.
469 // Split it in half and legalize both parts.
471 SplitVectorOp(Op, X, Y);
477 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
478 /// a load from the constant pool.
479 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
480 SelectionDAG &DAG, TargetLowering &TLI) {
483 // If a FP immediate is precise when represented as a float and if the
484 // target can do an extending load from float to double, we put it into
485 // the constant pool as a float, even if it's is statically typed as a
487 MVT::ValueType VT = CFP->getValueType(0);
488 bool isDouble = VT == MVT::f64;
489 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
490 Type::FloatTy, CFP->getValueAPF());
492 const APFloat& Val = LLVMC->getValueAPF();
494 ? DAG.getConstant(DoubleToBits(Val.convertToDouble()), MVT::i64)
495 : DAG.getConstant(FloatToBits(Val.convertToFloat()), MVT::i32);
498 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) &&
499 // Only do this if the target has a native EXTLOAD instruction from f32.
500 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
501 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
506 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
508 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
509 CPIdx, NULL, 0, MVT::f32);
511 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
516 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
519 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
520 SelectionDAG &DAG, TargetLowering &TLI) {
521 MVT::ValueType VT = Node->getValueType(0);
522 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
523 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
524 "fcopysign expansion only supported for f32 and f64");
525 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
527 // First get the sign bit of second operand.
528 SDOperand Mask1 = (SrcVT == MVT::f64)
529 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
530 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
531 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
532 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
533 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
534 // Shift right or sign-extend it if the two operands have different types.
535 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
537 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
538 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
539 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
540 } else if (SizeDiff < 0)
541 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
543 // Clear the sign bit of first operand.
544 SDOperand Mask2 = (VT == MVT::f64)
545 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
546 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
547 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
548 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
549 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
551 // Or the value with the sign bit.
552 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
556 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
558 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
559 TargetLowering &TLI) {
560 assert(MVT::isInteger(ST->getStoredVT()) &&
561 "Non integer unaligned stores not implemented.");
562 int SVOffset = ST->getSrcValueOffset();
563 SDOperand Chain = ST->getChain();
564 SDOperand Ptr = ST->getBasePtr();
565 SDOperand Val = ST->getValue();
566 MVT::ValueType VT = Val.getValueType();
567 // Get the half-size VT
568 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1;
569 int NumBits = MVT::getSizeInBits(NewStoredVT);
570 int Alignment = ST->getAlignment();
571 int IncrementSize = NumBits / 8;
573 // Divide the stored value in two parts.
574 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
576 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
578 // Store the two parts
579 SDOperand Store1, Store2;
580 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
581 ST->getSrcValue(), SVOffset, NewStoredVT,
582 ST->isVolatile(), Alignment);
583 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
584 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
585 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
586 ST->getSrcValue(), SVOffset + IncrementSize,
587 NewStoredVT, ST->isVolatile(), Alignment);
589 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
592 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
594 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
595 TargetLowering &TLI) {
596 assert(MVT::isInteger(LD->getLoadedVT()) &&
597 "Non integer unaligned loads not implemented.");
598 int SVOffset = LD->getSrcValueOffset();
599 SDOperand Chain = LD->getChain();
600 SDOperand Ptr = LD->getBasePtr();
601 MVT::ValueType VT = LD->getValueType(0);
602 MVT::ValueType NewLoadedVT = LD->getLoadedVT() - 1;
603 int NumBits = MVT::getSizeInBits(NewLoadedVT);
604 int Alignment = LD->getAlignment();
605 int IncrementSize = NumBits / 8;
606 ISD::LoadExtType HiExtType = LD->getExtensionType();
608 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
609 if (HiExtType == ISD::NON_EXTLOAD)
610 HiExtType = ISD::ZEXTLOAD;
612 // Load the value in two parts
614 if (TLI.isLittleEndian()) {
615 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
616 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
617 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
618 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
619 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
620 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
623 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
624 NewLoadedVT,LD->isVolatile(), Alignment);
625 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
626 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
627 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
628 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
632 // aggregate the two parts
633 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
634 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
635 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
637 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
640 SDOperand Ops[] = { Result, TF };
641 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
644 /// LegalizeOp - We know that the specified value has a legal type, and
645 /// that its operands are legal. Now ensure that the operation itself
646 /// is legal, recursively ensuring that the operands' operations remain
648 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
649 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
652 assert(isTypeLegal(Op.getValueType()) &&
653 "Caller should expand or promote operands that are not legal!");
654 SDNode *Node = Op.Val;
656 // If this operation defines any values that cannot be represented in a
657 // register on this target, make sure to expand or promote them.
658 if (Node->getNumValues() > 1) {
659 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
660 if (getTypeAction(Node->getValueType(i)) != Legal) {
661 HandleOp(Op.getValue(i));
662 assert(LegalizedNodes.count(Op) &&
663 "Handling didn't add legal operands!");
664 return LegalizedNodes[Op];
668 // Note that LegalizeOp may be reentered even from single-use nodes, which
669 // means that we always must cache transformed nodes.
670 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
671 if (I != LegalizedNodes.end()) return I->second;
673 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
674 SDOperand Result = Op;
675 bool isCustom = false;
677 switch (Node->getOpcode()) {
678 case ISD::FrameIndex:
679 case ISD::EntryToken:
681 case ISD::BasicBlock:
682 case ISD::TargetFrameIndex:
683 case ISD::TargetJumpTable:
684 case ISD::TargetConstant:
685 case ISD::TargetConstantFP:
686 case ISD::TargetConstantPool:
687 case ISD::TargetGlobalAddress:
688 case ISD::TargetGlobalTLSAddress:
689 case ISD::TargetExternalSymbol:
694 // Primitives must all be legal.
695 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
696 "This must be legal!");
699 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
700 // If this is a target node, legalize it by legalizing the operands then
701 // passing it through.
702 SmallVector<SDOperand, 8> Ops;
703 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
704 Ops.push_back(LegalizeOp(Node->getOperand(i)));
706 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
708 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
709 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
710 return Result.getValue(Op.ResNo);
712 // Otherwise this is an unhandled builtin node. splat.
714 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
716 assert(0 && "Do not know how to legalize this operator!");
718 case ISD::GLOBAL_OFFSET_TABLE:
719 case ISD::GlobalAddress:
720 case ISD::GlobalTLSAddress:
721 case ISD::ExternalSymbol:
722 case ISD::ConstantPool:
723 case ISD::JumpTable: // Nothing to do.
724 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
725 default: assert(0 && "This action is not supported yet!");
726 case TargetLowering::Custom:
727 Tmp1 = TLI.LowerOperation(Op, DAG);
728 if (Tmp1.Val) Result = Tmp1;
729 // FALLTHROUGH if the target doesn't want to lower this op after all.
730 case TargetLowering::Legal:
735 case ISD::RETURNADDR:
736 // The only option for these nodes is to custom lower them. If the target
737 // does not custom lower them, then return zero.
738 Tmp1 = TLI.LowerOperation(Op, DAG);
742 Result = DAG.getConstant(0, TLI.getPointerTy());
744 case ISD::FRAME_TO_ARGS_OFFSET: {
745 MVT::ValueType VT = Node->getValueType(0);
746 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
747 default: assert(0 && "This action is not supported yet!");
748 case TargetLowering::Custom:
749 Result = TLI.LowerOperation(Op, DAG);
750 if (Result.Val) break;
752 case TargetLowering::Legal:
753 Result = DAG.getConstant(0, VT);
758 case ISD::EXCEPTIONADDR: {
759 Tmp1 = LegalizeOp(Node->getOperand(0));
760 MVT::ValueType VT = Node->getValueType(0);
761 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
762 default: assert(0 && "This action is not supported yet!");
763 case TargetLowering::Expand: {
764 unsigned Reg = TLI.getExceptionAddressRegister();
765 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo);
768 case TargetLowering::Custom:
769 Result = TLI.LowerOperation(Op, DAG);
770 if (Result.Val) break;
772 case TargetLowering::Legal: {
773 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
774 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
775 Ops, 2).getValue(Op.ResNo);
781 case ISD::EHSELECTION: {
782 Tmp1 = LegalizeOp(Node->getOperand(0));
783 Tmp2 = LegalizeOp(Node->getOperand(1));
784 MVT::ValueType VT = Node->getValueType(0);
785 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
786 default: assert(0 && "This action is not supported yet!");
787 case TargetLowering::Expand: {
788 unsigned Reg = TLI.getExceptionSelectorRegister();
789 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo);
792 case TargetLowering::Custom:
793 Result = TLI.LowerOperation(Op, DAG);
794 if (Result.Val) break;
796 case TargetLowering::Legal: {
797 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
798 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
799 Ops, 2).getValue(Op.ResNo);
805 case ISD::EH_RETURN: {
806 MVT::ValueType VT = Node->getValueType(0);
807 // The only "good" option for this node is to custom lower it.
808 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
809 default: assert(0 && "This action is not supported at all!");
810 case TargetLowering::Custom:
811 Result = TLI.LowerOperation(Op, DAG);
812 if (Result.Val) break;
814 case TargetLowering::Legal:
815 // Target does not know, how to lower this, lower to noop
816 Result = LegalizeOp(Node->getOperand(0));
821 case ISD::AssertSext:
822 case ISD::AssertZext:
823 Tmp1 = LegalizeOp(Node->getOperand(0));
824 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
826 case ISD::MERGE_VALUES:
827 // Legalize eliminates MERGE_VALUES nodes.
828 Result = Node->getOperand(Op.ResNo);
830 case ISD::CopyFromReg:
831 Tmp1 = LegalizeOp(Node->getOperand(0));
832 Result = Op.getValue(0);
833 if (Node->getNumValues() == 2) {
834 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
836 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
837 if (Node->getNumOperands() == 3) {
838 Tmp2 = LegalizeOp(Node->getOperand(2));
839 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
841 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
843 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
845 // Since CopyFromReg produces two values, make sure to remember that we
846 // legalized both of them.
847 AddLegalizedOperand(Op.getValue(0), Result);
848 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
849 return Result.getValue(Op.ResNo);
851 MVT::ValueType VT = Op.getValueType();
852 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
853 default: assert(0 && "This action is not supported yet!");
854 case TargetLowering::Expand:
855 if (MVT::isInteger(VT))
856 Result = DAG.getConstant(0, VT);
857 else if (MVT::isFloatingPoint(VT))
858 Result = DAG.getConstantFP(0, VT);
860 assert(0 && "Unknown value type!");
862 case TargetLowering::Legal:
868 case ISD::INTRINSIC_W_CHAIN:
869 case ISD::INTRINSIC_WO_CHAIN:
870 case ISD::INTRINSIC_VOID: {
871 SmallVector<SDOperand, 8> Ops;
872 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
873 Ops.push_back(LegalizeOp(Node->getOperand(i)));
874 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
876 // Allow the target to custom lower its intrinsics if it wants to.
877 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
878 TargetLowering::Custom) {
879 Tmp3 = TLI.LowerOperation(Result, DAG);
880 if (Tmp3.Val) Result = Tmp3;
883 if (Result.Val->getNumValues() == 1) break;
885 // Must have return value and chain result.
886 assert(Result.Val->getNumValues() == 2 &&
887 "Cannot return more than two values!");
889 // Since loads produce two values, make sure to remember that we
890 // legalized both of them.
891 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
892 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
893 return Result.getValue(Op.ResNo);
897 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
898 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
900 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
901 case TargetLowering::Promote:
902 default: assert(0 && "This action is not supported yet!");
903 case TargetLowering::Expand: {
904 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
905 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
906 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
908 if (MMI && (useDEBUG_LOC || useLABEL)) {
909 const std::string &FName =
910 cast<StringSDNode>(Node->getOperand(3))->getValue();
911 const std::string &DirName =
912 cast<StringSDNode>(Node->getOperand(4))->getValue();
913 unsigned SrcFile = MMI->RecordSource(DirName, FName);
915 SmallVector<SDOperand, 8> Ops;
916 Ops.push_back(Tmp1); // chain
917 SDOperand LineOp = Node->getOperand(1);
918 SDOperand ColOp = Node->getOperand(2);
921 Ops.push_back(LineOp); // line #
922 Ops.push_back(ColOp); // col #
923 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
924 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
926 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
927 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
928 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
929 Ops.push_back(DAG.getConstant(ID, MVT::i32));
930 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
933 Result = Tmp1; // chain
937 case TargetLowering::Legal:
938 if (Tmp1 != Node->getOperand(0) ||
939 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
940 SmallVector<SDOperand, 8> Ops;
942 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
943 Ops.push_back(Node->getOperand(1)); // line # must be legal.
944 Ops.push_back(Node->getOperand(2)); // col # must be legal.
946 // Otherwise promote them.
947 Ops.push_back(PromoteOp(Node->getOperand(1)));
948 Ops.push_back(PromoteOp(Node->getOperand(2)));
950 Ops.push_back(Node->getOperand(3)); // filename must be legal.
951 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
952 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
959 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
960 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
961 default: assert(0 && "This action is not supported yet!");
962 case TargetLowering::Legal:
963 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
964 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
965 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
966 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
967 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
973 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
974 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
975 default: assert(0 && "This action is not supported yet!");
976 case TargetLowering::Legal:
977 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
978 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
979 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
981 case TargetLowering::Expand:
982 Result = LegalizeOp(Node->getOperand(0));
987 case ISD::Constant: {
988 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
990 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
992 // We know we don't need to expand constants here, constants only have one
993 // value and we check that it is fine above.
995 if (opAction == TargetLowering::Custom) {
996 Tmp1 = TLI.LowerOperation(Result, DAG);
1002 case ISD::ConstantFP: {
1003 // Spill FP immediates to the constant pool if the target cannot directly
1004 // codegen them. Targets often have some immediate values that can be
1005 // efficiently generated into an FP register without a load. We explicitly
1006 // leave these constants as ConstantFP nodes for the target to deal with.
1007 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1009 // Check to see if this FP immediate is already legal.
1010 bool isLegal = false;
1011 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1012 E = TLI.legal_fpimm_end(); I != E; ++I)
1013 if (CFP->isExactlyValue(*I)) {
1018 // If this is a legal constant, turn it into a TargetConstantFP node.
1020 Result = DAG.getTargetConstantFP(CFP->getValueAPF(),
1021 CFP->getValueType(0));
1025 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1026 default: assert(0 && "This action is not supported yet!");
1027 case TargetLowering::Custom:
1028 Tmp3 = TLI.LowerOperation(Result, DAG);
1034 case TargetLowering::Expand:
1035 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1039 case ISD::TokenFactor:
1040 if (Node->getNumOperands() == 2) {
1041 Tmp1 = LegalizeOp(Node->getOperand(0));
1042 Tmp2 = LegalizeOp(Node->getOperand(1));
1043 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1044 } else if (Node->getNumOperands() == 3) {
1045 Tmp1 = LegalizeOp(Node->getOperand(0));
1046 Tmp2 = LegalizeOp(Node->getOperand(1));
1047 Tmp3 = LegalizeOp(Node->getOperand(2));
1048 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1050 SmallVector<SDOperand, 8> Ops;
1051 // Legalize the operands.
1052 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1053 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1054 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1058 case ISD::FORMAL_ARGUMENTS:
1060 // The only option for this is to custom lower it.
1061 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1062 assert(Tmp3.Val && "Target didn't custom lower this node!");
1063 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
1064 "Lowering call/formal_arguments produced unexpected # results!");
1066 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1067 // remember that we legalized all of them, so it doesn't get relegalized.
1068 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1069 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1072 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1075 case ISD::EXTRACT_SUBREG: {
1076 Tmp1 = LegalizeOp(Node->getOperand(0));
1077 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1078 assert(idx && "Operand must be a constant");
1079 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1080 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1083 case ISD::INSERT_SUBREG: {
1084 Tmp1 = LegalizeOp(Node->getOperand(0));
1085 Tmp2 = LegalizeOp(Node->getOperand(1));
1086 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1087 assert(idx && "Operand must be a constant");
1088 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1089 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1092 case ISD::BUILD_VECTOR:
1093 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1094 default: assert(0 && "This action is not supported yet!");
1095 case TargetLowering::Custom:
1096 Tmp3 = TLI.LowerOperation(Result, DAG);
1102 case TargetLowering::Expand:
1103 Result = ExpandBUILD_VECTOR(Result.Val);
1107 case ISD::INSERT_VECTOR_ELT:
1108 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1109 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
1110 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1111 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1113 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1114 Node->getValueType(0))) {
1115 default: assert(0 && "This action is not supported yet!");
1116 case TargetLowering::Legal:
1118 case TargetLowering::Custom:
1119 Tmp3 = TLI.LowerOperation(Result, DAG);
1125 case TargetLowering::Expand: {
1126 // If the insert index is a constant, codegen this as a scalar_to_vector,
1127 // then a shuffle that inserts it into the right position in the vector.
1128 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1129 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1130 Tmp1.getValueType(), Tmp2);
1132 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1133 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1134 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1136 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
1137 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
1139 SmallVector<SDOperand, 8> ShufOps;
1140 for (unsigned i = 0; i != NumElts; ++i) {
1141 if (i != InsertPos->getValue())
1142 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1144 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1146 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1147 &ShufOps[0], ShufOps.size());
1149 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1150 Tmp1, ScVec, ShufMask);
1151 Result = LegalizeOp(Result);
1155 // If the target doesn't support this, we have to spill the input vector
1156 // to a temporary stack slot, update the element, then reload it. This is
1157 // badness. We could also load the value into a vector register (either
1158 // with a "move to register" or "extload into register" instruction, then
1159 // permute it into place, if the idx is a constant and if the idx is
1160 // supported by the target.
1161 MVT::ValueType VT = Tmp1.getValueType();
1162 MVT::ValueType EltVT = Tmp2.getValueType();
1163 MVT::ValueType IdxVT = Tmp3.getValueType();
1164 MVT::ValueType PtrVT = TLI.getPointerTy();
1165 SDOperand StackPtr = CreateStackTemporary(VT);
1166 // Store the vector.
1167 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
1169 // Truncate or zero extend offset to target pointer type.
1170 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1171 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1172 // Add the offset to the index.
1173 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1174 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1175 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1176 // Store the scalar value.
1177 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
1178 // Load the updated vector.
1179 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1184 case ISD::SCALAR_TO_VECTOR:
1185 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1186 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1190 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1191 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1192 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1193 Node->getValueType(0))) {
1194 default: assert(0 && "This action is not supported yet!");
1195 case TargetLowering::Legal:
1197 case TargetLowering::Custom:
1198 Tmp3 = TLI.LowerOperation(Result, DAG);
1204 case TargetLowering::Expand:
1205 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1209 case ISD::VECTOR_SHUFFLE:
1210 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1211 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1212 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1214 // Allow targets to custom lower the SHUFFLEs they support.
1215 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1216 default: assert(0 && "Unknown operation action!");
1217 case TargetLowering::Legal:
1218 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1219 "vector shuffle should not be created if not legal!");
1221 case TargetLowering::Custom:
1222 Tmp3 = TLI.LowerOperation(Result, DAG);
1228 case TargetLowering::Expand: {
1229 MVT::ValueType VT = Node->getValueType(0);
1230 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1231 MVT::ValueType PtrVT = TLI.getPointerTy();
1232 SDOperand Mask = Node->getOperand(2);
1233 unsigned NumElems = Mask.getNumOperands();
1234 SmallVector<SDOperand,8> Ops;
1235 for (unsigned i = 0; i != NumElems; ++i) {
1236 SDOperand Arg = Mask.getOperand(i);
1237 if (Arg.getOpcode() == ISD::UNDEF) {
1238 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1240 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1241 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1243 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1244 DAG.getConstant(Idx, PtrVT)));
1246 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1247 DAG.getConstant(Idx - NumElems, PtrVT)));
1250 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1253 case TargetLowering::Promote: {
1254 // Change base type to a different vector type.
1255 MVT::ValueType OVT = Node->getValueType(0);
1256 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1258 // Cast the two input vectors.
1259 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1260 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1262 // Convert the shuffle mask to the right # elements.
1263 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1264 assert(Tmp3.Val && "Shuffle not legal?");
1265 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1266 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1272 case ISD::EXTRACT_VECTOR_ELT:
1273 Tmp1 = Node->getOperand(0);
1274 Tmp2 = LegalizeOp(Node->getOperand(1));
1275 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1276 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1279 case ISD::EXTRACT_SUBVECTOR:
1280 Tmp1 = Node->getOperand(0);
1281 Tmp2 = LegalizeOp(Node->getOperand(1));
1282 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1283 Result = ExpandEXTRACT_SUBVECTOR(Result);
1286 case ISD::CALLSEQ_START: {
1287 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1289 // Recursively Legalize all of the inputs of the call end that do not lead
1290 // to this call start. This ensures that any libcalls that need be inserted
1291 // are inserted *before* the CALLSEQ_START.
1292 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1293 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1294 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1298 // Now that we legalized all of the inputs (which may have inserted
1299 // libcalls) create the new CALLSEQ_START node.
1300 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1302 // Merge in the last call, to ensure that this call start after the last
1304 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1305 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1306 Tmp1 = LegalizeOp(Tmp1);
1309 // Do not try to legalize the target-specific arguments (#1+).
1310 if (Tmp1 != Node->getOperand(0)) {
1311 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1313 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1316 // Remember that the CALLSEQ_START is legalized.
1317 AddLegalizedOperand(Op.getValue(0), Result);
1318 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1319 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1321 // Now that the callseq_start and all of the non-call nodes above this call
1322 // sequence have been legalized, legalize the call itself. During this
1323 // process, no libcalls can/will be inserted, guaranteeing that no calls
1325 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1326 SDOperand InCallSEQ = LastCALLSEQ_END;
1327 // Note that we are selecting this call!
1328 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1329 IsLegalizingCall = true;
1331 // Legalize the call, starting from the CALLSEQ_END.
1332 LegalizeOp(LastCALLSEQ_END);
1333 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1336 case ISD::CALLSEQ_END:
1337 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1338 // will cause this node to be legalized as well as handling libcalls right.
1339 if (LastCALLSEQ_END.Val != Node) {
1340 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1341 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1342 assert(I != LegalizedNodes.end() &&
1343 "Legalizing the call start should have legalized this node!");
1347 // Otherwise, the call start has been legalized and everything is going
1348 // according to plan. Just legalize ourselves normally here.
1349 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1350 // Do not try to legalize the target-specific arguments (#1+), except for
1351 // an optional flag input.
1352 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1353 if (Tmp1 != Node->getOperand(0)) {
1354 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1356 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1359 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1360 if (Tmp1 != Node->getOperand(0) ||
1361 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1362 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1365 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1368 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1369 // This finishes up call legalization.
1370 IsLegalizingCall = false;
1372 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1373 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1374 if (Node->getNumValues() == 2)
1375 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1376 return Result.getValue(Op.ResNo);
1377 case ISD::DYNAMIC_STACKALLOC: {
1378 MVT::ValueType VT = Node->getValueType(0);
1379 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1380 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1381 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1382 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1384 Tmp1 = Result.getValue(0);
1385 Tmp2 = Result.getValue(1);
1386 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1387 default: assert(0 && "This action is not supported yet!");
1388 case TargetLowering::Expand: {
1389 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1390 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1391 " not tell us which reg is the stack pointer!");
1392 SDOperand Chain = Tmp1.getOperand(0);
1393 SDOperand Size = Tmp2.getOperand(1);
1394 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1395 Chain = SP.getValue(1);
1396 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1397 unsigned StackAlign =
1398 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1399 if (Align > StackAlign)
1400 SP = DAG.getNode(ISD::AND, VT, SP,
1401 DAG.getConstant(-(uint64_t)Align, VT));
1402 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1403 Tmp2 = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1404 Tmp1 = LegalizeOp(Tmp1);
1405 Tmp2 = LegalizeOp(Tmp2);
1408 case TargetLowering::Custom:
1409 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1411 Tmp1 = LegalizeOp(Tmp3);
1412 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1415 case TargetLowering::Legal:
1418 // Since this op produce two values, make sure to remember that we
1419 // legalized both of them.
1420 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1421 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1422 return Op.ResNo ? Tmp2 : Tmp1;
1424 case ISD::INLINEASM: {
1425 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1426 bool Changed = false;
1427 // Legalize all of the operands of the inline asm, in case they are nodes
1428 // that need to be expanded or something. Note we skip the asm string and
1429 // all of the TargetConstant flags.
1430 SDOperand Op = LegalizeOp(Ops[0]);
1431 Changed = Op != Ops[0];
1434 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1435 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1436 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1437 for (++i; NumVals; ++i, --NumVals) {
1438 SDOperand Op = LegalizeOp(Ops[i]);
1447 Op = LegalizeOp(Ops.back());
1448 Changed |= Op != Ops.back();
1453 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1455 // INLINE asm returns a chain and flag, make sure to add both to the map.
1456 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1457 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1458 return Result.getValue(Op.ResNo);
1461 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1462 // Ensure that libcalls are emitted before a branch.
1463 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1464 Tmp1 = LegalizeOp(Tmp1);
1465 LastCALLSEQ_END = DAG.getEntryNode();
1467 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1470 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1471 // Ensure that libcalls are emitted before a branch.
1472 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1473 Tmp1 = LegalizeOp(Tmp1);
1474 LastCALLSEQ_END = DAG.getEntryNode();
1476 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1477 default: assert(0 && "Indirect target must be legal type (pointer)!");
1479 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1482 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1485 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1486 // Ensure that libcalls are emitted before a branch.
1487 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1488 Tmp1 = LegalizeOp(Tmp1);
1489 LastCALLSEQ_END = DAG.getEntryNode();
1491 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1492 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1494 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1495 default: assert(0 && "This action is not supported yet!");
1496 case TargetLowering::Legal: break;
1497 case TargetLowering::Custom:
1498 Tmp1 = TLI.LowerOperation(Result, DAG);
1499 if (Tmp1.Val) Result = Tmp1;
1501 case TargetLowering::Expand: {
1502 SDOperand Chain = Result.getOperand(0);
1503 SDOperand Table = Result.getOperand(1);
1504 SDOperand Index = Result.getOperand(2);
1506 MVT::ValueType PTy = TLI.getPointerTy();
1507 MachineFunction &MF = DAG.getMachineFunction();
1508 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1509 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1510 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1513 switch (EntrySize) {
1514 default: assert(0 && "Size of jump table not supported yet."); break;
1515 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1516 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1519 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1520 // For PIC, the sequence is:
1521 // BRIND(load(Jumptable + index) + RelocBase)
1522 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
1524 if (TLI.usesGlobalOffsetTable())
1525 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
1528 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
1529 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
1530 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1532 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD);
1538 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1539 // Ensure that libcalls are emitted before a return.
1540 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1541 Tmp1 = LegalizeOp(Tmp1);
1542 LastCALLSEQ_END = DAG.getEntryNode();
1544 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1545 case Expand: assert(0 && "It's impossible to expand bools");
1547 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1550 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1552 // The top bits of the promoted condition are not necessarily zero, ensure
1553 // that the value is properly zero extended.
1554 if (!DAG.MaskedValueIsZero(Tmp2,
1555 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1556 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1560 // Basic block destination (Op#2) is always legal.
1561 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1563 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1564 default: assert(0 && "This action is not supported yet!");
1565 case TargetLowering::Legal: break;
1566 case TargetLowering::Custom:
1567 Tmp1 = TLI.LowerOperation(Result, DAG);
1568 if (Tmp1.Val) Result = Tmp1;
1570 case TargetLowering::Expand:
1571 // Expand brcond's setcc into its constituent parts and create a BR_CC
1573 if (Tmp2.getOpcode() == ISD::SETCC) {
1574 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1575 Tmp2.getOperand(0), Tmp2.getOperand(1),
1576 Node->getOperand(2));
1578 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1579 DAG.getCondCode(ISD::SETNE), Tmp2,
1580 DAG.getConstant(0, Tmp2.getValueType()),
1581 Node->getOperand(2));
1587 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1588 // Ensure that libcalls are emitted before a branch.
1589 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1590 Tmp1 = LegalizeOp(Tmp1);
1591 Tmp2 = Node->getOperand(2); // LHS
1592 Tmp3 = Node->getOperand(3); // RHS
1593 Tmp4 = Node->getOperand(1); // CC
1595 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1596 LastCALLSEQ_END = DAG.getEntryNode();
1598 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1599 // the LHS is a legal SETCC itself. In this case, we need to compare
1600 // the result against zero to select between true and false values.
1601 if (Tmp3.Val == 0) {
1602 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1603 Tmp4 = DAG.getCondCode(ISD::SETNE);
1606 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1607 Node->getOperand(4));
1609 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1610 default: assert(0 && "Unexpected action for BR_CC!");
1611 case TargetLowering::Legal: break;
1612 case TargetLowering::Custom:
1613 Tmp4 = TLI.LowerOperation(Result, DAG);
1614 if (Tmp4.Val) Result = Tmp4;
1619 LoadSDNode *LD = cast<LoadSDNode>(Node);
1620 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1621 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1623 ISD::LoadExtType ExtType = LD->getExtensionType();
1624 if (ExtType == ISD::NON_EXTLOAD) {
1625 MVT::ValueType VT = Node->getValueType(0);
1626 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1627 Tmp3 = Result.getValue(0);
1628 Tmp4 = Result.getValue(1);
1630 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1631 default: assert(0 && "This action is not supported yet!");
1632 case TargetLowering::Legal:
1633 // If this is an unaligned load and the target doesn't support it,
1635 if (!TLI.allowsUnalignedMemoryAccesses()) {
1636 unsigned ABIAlignment = TLI.getTargetData()->
1637 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1638 if (LD->getAlignment() < ABIAlignment){
1639 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1641 Tmp3 = Result.getOperand(0);
1642 Tmp4 = Result.getOperand(1);
1648 case TargetLowering::Custom:
1649 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1651 Tmp3 = LegalizeOp(Tmp1);
1652 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1655 case TargetLowering::Promote: {
1656 // Only promote a load of vector type to another.
1657 assert(MVT::isVector(VT) && "Cannot promote this load!");
1658 // Change base type to a different vector type.
1659 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1661 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1662 LD->getSrcValueOffset(),
1663 LD->isVolatile(), LD->getAlignment());
1664 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1665 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1669 // Since loads produce two values, make sure to remember that we
1670 // legalized both of them.
1671 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1672 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1673 return Op.ResNo ? Tmp4 : Tmp3;
1675 MVT::ValueType SrcVT = LD->getLoadedVT();
1676 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1677 default: assert(0 && "This action is not supported yet!");
1678 case TargetLowering::Promote:
1679 assert(SrcVT == MVT::i1 &&
1680 "Can only promote extending LOAD from i1 -> i8!");
1681 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1682 LD->getSrcValue(), LD->getSrcValueOffset(),
1683 MVT::i8, LD->isVolatile(), LD->getAlignment());
1684 Tmp1 = Result.getValue(0);
1685 Tmp2 = Result.getValue(1);
1687 case TargetLowering::Custom:
1690 case TargetLowering::Legal:
1691 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1692 Tmp1 = Result.getValue(0);
1693 Tmp2 = Result.getValue(1);
1696 Tmp3 = TLI.LowerOperation(Result, DAG);
1698 Tmp1 = LegalizeOp(Tmp3);
1699 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1702 // If this is an unaligned load and the target doesn't support it,
1704 if (!TLI.allowsUnalignedMemoryAccesses()) {
1705 unsigned ABIAlignment = TLI.getTargetData()->
1706 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1707 if (LD->getAlignment() < ABIAlignment){
1708 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1710 Tmp1 = Result.getOperand(0);
1711 Tmp2 = Result.getOperand(1);
1718 case TargetLowering::Expand:
1719 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1720 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1721 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1722 LD->getSrcValueOffset(),
1723 LD->isVolatile(), LD->getAlignment());
1724 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1725 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1726 Tmp2 = LegalizeOp(Load.getValue(1));
1729 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1730 // Turn the unsupported load into an EXTLOAD followed by an explicit
1731 // zero/sign extend inreg.
1732 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1733 Tmp1, Tmp2, LD->getSrcValue(),
1734 LD->getSrcValueOffset(), SrcVT,
1735 LD->isVolatile(), LD->getAlignment());
1737 if (ExtType == ISD::SEXTLOAD)
1738 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1739 Result, DAG.getValueType(SrcVT));
1741 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1742 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1743 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1746 // Since loads produce two values, make sure to remember that we legalized
1748 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1749 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1750 return Op.ResNo ? Tmp2 : Tmp1;
1753 case ISD::EXTRACT_ELEMENT: {
1754 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1755 switch (getTypeAction(OpTy)) {
1756 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1758 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1760 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1761 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1762 TLI.getShiftAmountTy()));
1763 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1766 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1767 Node->getOperand(0));
1771 // Get both the low and high parts.
1772 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1773 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1774 Result = Tmp2; // 1 -> Hi
1776 Result = Tmp1; // 0 -> Lo
1782 case ISD::CopyToReg:
1783 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1785 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1786 "Register type must be legal!");
1787 // Legalize the incoming value (must be a legal type).
1788 Tmp2 = LegalizeOp(Node->getOperand(2));
1789 if (Node->getNumValues() == 1) {
1790 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1792 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1793 if (Node->getNumOperands() == 4) {
1794 Tmp3 = LegalizeOp(Node->getOperand(3));
1795 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1798 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1801 // Since this produces two values, make sure to remember that we legalized
1803 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1804 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1810 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1812 // Ensure that libcalls are emitted before a return.
1813 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1814 Tmp1 = LegalizeOp(Tmp1);
1815 LastCALLSEQ_END = DAG.getEntryNode();
1817 switch (Node->getNumOperands()) {
1819 Tmp2 = Node->getOperand(1);
1820 Tmp3 = Node->getOperand(2); // Signness
1821 switch (getTypeAction(Tmp2.getValueType())) {
1823 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1826 if (!MVT::isVector(Tmp2.getValueType())) {
1828 ExpandOp(Tmp2, Lo, Hi);
1830 // Big endian systems want the hi reg first.
1831 if (!TLI.isLittleEndian())
1835 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1837 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1838 Result = LegalizeOp(Result);
1840 SDNode *InVal = Tmp2.Val;
1841 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
1842 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
1844 // Figure out if there is a simple type corresponding to this Vector
1845 // type. If so, convert to the vector type.
1846 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1847 if (TLI.isTypeLegal(TVT)) {
1848 // Turn this into a return of the vector type.
1849 Tmp2 = LegalizeOp(Tmp2);
1850 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1851 } else if (NumElems == 1) {
1852 // Turn this into a return of the scalar type.
1853 Tmp2 = ScalarizeVectorOp(Tmp2);
1854 Tmp2 = LegalizeOp(Tmp2);
1855 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1857 // FIXME: Returns of gcc generic vectors smaller than a legal type
1858 // should be returned in integer registers!
1860 // The scalarized value type may not be legal, e.g. it might require
1861 // promotion or expansion. Relegalize the return.
1862 Result = LegalizeOp(Result);
1864 // FIXME: Returns of gcc generic vectors larger than a legal vector
1865 // type should be returned by reference!
1867 SplitVectorOp(Tmp2, Lo, Hi);
1868 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1869 Result = LegalizeOp(Result);
1874 Tmp2 = PromoteOp(Node->getOperand(1));
1875 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1876 Result = LegalizeOp(Result);
1881 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1883 default: { // ret <values>
1884 SmallVector<SDOperand, 8> NewValues;
1885 NewValues.push_back(Tmp1);
1886 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1887 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1889 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1890 NewValues.push_back(Node->getOperand(i+1));
1894 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
1895 "FIXME: TODO: implement returning non-legal vector types!");
1896 ExpandOp(Node->getOperand(i), Lo, Hi);
1897 NewValues.push_back(Lo);
1898 NewValues.push_back(Node->getOperand(i+1));
1900 NewValues.push_back(Hi);
1901 NewValues.push_back(Node->getOperand(i+1));
1906 assert(0 && "Can't promote multiple return value yet!");
1909 if (NewValues.size() == Node->getNumOperands())
1910 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1912 Result = DAG.getNode(ISD::RET, MVT::Other,
1913 &NewValues[0], NewValues.size());
1918 if (Result.getOpcode() == ISD::RET) {
1919 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1920 default: assert(0 && "This action is not supported yet!");
1921 case TargetLowering::Legal: break;
1922 case TargetLowering::Custom:
1923 Tmp1 = TLI.LowerOperation(Result, DAG);
1924 if (Tmp1.Val) Result = Tmp1;
1930 StoreSDNode *ST = cast<StoreSDNode>(Node);
1931 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1932 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1933 int SVOffset = ST->getSrcValueOffset();
1934 unsigned Alignment = ST->getAlignment();
1935 bool isVolatile = ST->isVolatile();
1937 if (!ST->isTruncatingStore()) {
1938 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1939 // FIXME: We shouldn't do this for TargetConstantFP's.
1940 // FIXME: move this to the DAG Combiner! Note that we can't regress due
1941 // to phase ordering between legalized code and the dag combiner. This
1942 // probably means that we need to integrate dag combiner and legalizer
1944 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
1945 if (CFP->getValueType(0) == MVT::f32) {
1946 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValueAPF().
1947 convertToFloat()), MVT::i32);
1949 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1950 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValueAPF().
1951 convertToDouble()), MVT::i64);
1953 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1954 SVOffset, isVolatile, Alignment);
1958 switch (getTypeAction(ST->getStoredVT())) {
1960 Tmp3 = LegalizeOp(ST->getValue());
1961 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1964 MVT::ValueType VT = Tmp3.getValueType();
1965 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1966 default: assert(0 && "This action is not supported yet!");
1967 case TargetLowering::Legal:
1968 // If this is an unaligned store and the target doesn't support it,
1970 if (!TLI.allowsUnalignedMemoryAccesses()) {
1971 unsigned ABIAlignment = TLI.getTargetData()->
1972 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
1973 if (ST->getAlignment() < ABIAlignment)
1974 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
1978 case TargetLowering::Custom:
1979 Tmp1 = TLI.LowerOperation(Result, DAG);
1980 if (Tmp1.Val) Result = Tmp1;
1982 case TargetLowering::Promote:
1983 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1984 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1985 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1986 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
1987 ST->getSrcValue(), SVOffset, isVolatile,
1994 // Truncate the value and store the result.
1995 Tmp3 = PromoteOp(ST->getValue());
1996 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1997 SVOffset, ST->getStoredVT(),
1998 isVolatile, Alignment);
2002 unsigned IncrementSize = 0;
2005 // If this is a vector type, then we have to calculate the increment as
2006 // the product of the element size in bytes, and the number of elements
2007 // in the high half of the vector.
2008 if (MVT::isVector(ST->getValue().getValueType())) {
2009 SDNode *InVal = ST->getValue().Val;
2010 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
2011 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
2013 // Figure out if there is a simple type corresponding to this Vector
2014 // type. If so, convert to the vector type.
2015 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2016 if (TLI.isTypeLegal(TVT)) {
2017 // Turn this into a normal store of the vector type.
2018 Tmp3 = LegalizeOp(Node->getOperand(1));
2019 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2020 SVOffset, isVolatile, Alignment);
2021 Result = LegalizeOp(Result);
2023 } else if (NumElems == 1) {
2024 // Turn this into a normal store of the scalar type.
2025 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
2026 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2027 SVOffset, isVolatile, Alignment);
2028 // The scalarized value type may not be legal, e.g. it might require
2029 // promotion or expansion. Relegalize the scalar store.
2030 Result = LegalizeOp(Result);
2033 SplitVectorOp(Node->getOperand(1), Lo, Hi);
2034 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
2037 ExpandOp(Node->getOperand(1), Lo, Hi);
2038 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2040 if (!TLI.isLittleEndian())
2044 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2045 SVOffset, isVolatile, Alignment);
2047 if (Hi.Val == NULL) {
2048 // Must be int <-> float one-to-one expansion.
2053 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2054 getIntPtrConstant(IncrementSize));
2055 assert(isTypeLegal(Tmp2.getValueType()) &&
2056 "Pointers must be legal!");
2057 SVOffset += IncrementSize;
2058 if (Alignment > IncrementSize)
2059 Alignment = IncrementSize;
2060 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2061 SVOffset, isVolatile, Alignment);
2062 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2067 assert(isTypeLegal(ST->getValue().getValueType()) &&
2068 "Cannot handle illegal TRUNCSTORE yet!");
2069 Tmp3 = LegalizeOp(ST->getValue());
2071 // The only promote case we handle is TRUNCSTORE:i1 X into
2072 // -> TRUNCSTORE:i8 (and X, 1)
2073 if (ST->getStoredVT() == MVT::i1 &&
2074 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
2075 // Promote the bool to a mask then store.
2076 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
2077 DAG.getConstant(1, Tmp3.getValueType()));
2078 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2080 isVolatile, Alignment);
2081 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2082 Tmp2 != ST->getBasePtr()) {
2083 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2087 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
2088 switch (TLI.getStoreXAction(StVT)) {
2089 default: assert(0 && "This action is not supported yet!");
2090 case TargetLowering::Legal:
2091 // If this is an unaligned store and the target doesn't support it,
2093 if (!TLI.allowsUnalignedMemoryAccesses()) {
2094 unsigned ABIAlignment = TLI.getTargetData()->
2095 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
2096 if (ST->getAlignment() < ABIAlignment)
2097 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2101 case TargetLowering::Custom:
2102 Tmp1 = TLI.LowerOperation(Result, DAG);
2103 if (Tmp1.Val) Result = Tmp1;
2110 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2111 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2113 case ISD::STACKSAVE:
2114 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2115 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2116 Tmp1 = Result.getValue(0);
2117 Tmp2 = Result.getValue(1);
2119 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2120 default: assert(0 && "This action is not supported yet!");
2121 case TargetLowering::Legal: break;
2122 case TargetLowering::Custom:
2123 Tmp3 = TLI.LowerOperation(Result, DAG);
2125 Tmp1 = LegalizeOp(Tmp3);
2126 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2129 case TargetLowering::Expand:
2130 // Expand to CopyFromReg if the target set
2131 // StackPointerRegisterToSaveRestore.
2132 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2133 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2134 Node->getValueType(0));
2135 Tmp2 = Tmp1.getValue(1);
2137 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2138 Tmp2 = Node->getOperand(0);
2143 // Since stacksave produce two values, make sure to remember that we
2144 // legalized both of them.
2145 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2146 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2147 return Op.ResNo ? Tmp2 : Tmp1;
2149 case ISD::STACKRESTORE:
2150 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2151 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2152 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2154 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2155 default: assert(0 && "This action is not supported yet!");
2156 case TargetLowering::Legal: break;
2157 case TargetLowering::Custom:
2158 Tmp1 = TLI.LowerOperation(Result, DAG);
2159 if (Tmp1.Val) Result = Tmp1;
2161 case TargetLowering::Expand:
2162 // Expand to CopyToReg if the target set
2163 // StackPointerRegisterToSaveRestore.
2164 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2165 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2173 case ISD::READCYCLECOUNTER:
2174 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2175 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2176 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2177 Node->getValueType(0))) {
2178 default: assert(0 && "This action is not supported yet!");
2179 case TargetLowering::Legal:
2180 Tmp1 = Result.getValue(0);
2181 Tmp2 = Result.getValue(1);
2183 case TargetLowering::Custom:
2184 Result = TLI.LowerOperation(Result, DAG);
2185 Tmp1 = LegalizeOp(Result.getValue(0));
2186 Tmp2 = LegalizeOp(Result.getValue(1));
2190 // Since rdcc produce two values, make sure to remember that we legalized
2192 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2193 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2197 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2198 case Expand: assert(0 && "It's impossible to expand bools");
2200 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2203 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2204 // Make sure the condition is either zero or one.
2205 if (!DAG.MaskedValueIsZero(Tmp1,
2206 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2207 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2210 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2211 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2213 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2215 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2216 default: assert(0 && "This action is not supported yet!");
2217 case TargetLowering::Legal: break;
2218 case TargetLowering::Custom: {
2219 Tmp1 = TLI.LowerOperation(Result, DAG);
2220 if (Tmp1.Val) Result = Tmp1;
2223 case TargetLowering::Expand:
2224 if (Tmp1.getOpcode() == ISD::SETCC) {
2225 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2227 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2229 Result = DAG.getSelectCC(Tmp1,
2230 DAG.getConstant(0, Tmp1.getValueType()),
2231 Tmp2, Tmp3, ISD::SETNE);
2234 case TargetLowering::Promote: {
2235 MVT::ValueType NVT =
2236 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2237 unsigned ExtOp, TruncOp;
2238 if (MVT::isVector(Tmp2.getValueType())) {
2239 ExtOp = ISD::BIT_CONVERT;
2240 TruncOp = ISD::BIT_CONVERT;
2241 } else if (MVT::isInteger(Tmp2.getValueType())) {
2242 ExtOp = ISD::ANY_EXTEND;
2243 TruncOp = ISD::TRUNCATE;
2245 ExtOp = ISD::FP_EXTEND;
2246 TruncOp = ISD::FP_ROUND;
2248 // Promote each of the values to the new type.
2249 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2250 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2251 // Perform the larger operation, then round down.
2252 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2253 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2258 case ISD::SELECT_CC: {
2259 Tmp1 = Node->getOperand(0); // LHS
2260 Tmp2 = Node->getOperand(1); // RHS
2261 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2262 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2263 SDOperand CC = Node->getOperand(4);
2265 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2267 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2268 // the LHS is a legal SETCC itself. In this case, we need to compare
2269 // the result against zero to select between true and false values.
2270 if (Tmp2.Val == 0) {
2271 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2272 CC = DAG.getCondCode(ISD::SETNE);
2274 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2276 // Everything is legal, see if we should expand this op or something.
2277 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2278 default: assert(0 && "This action is not supported yet!");
2279 case TargetLowering::Legal: break;
2280 case TargetLowering::Custom:
2281 Tmp1 = TLI.LowerOperation(Result, DAG);
2282 if (Tmp1.Val) Result = Tmp1;
2288 Tmp1 = Node->getOperand(0);
2289 Tmp2 = Node->getOperand(1);
2290 Tmp3 = Node->getOperand(2);
2291 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2293 // If we had to Expand the SetCC operands into a SELECT node, then it may
2294 // not always be possible to return a true LHS & RHS. In this case, just
2295 // return the value we legalized, returned in the LHS
2296 if (Tmp2.Val == 0) {
2301 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2302 default: assert(0 && "Cannot handle this action for SETCC yet!");
2303 case TargetLowering::Custom:
2306 case TargetLowering::Legal:
2307 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2309 Tmp4 = TLI.LowerOperation(Result, DAG);
2310 if (Tmp4.Val) Result = Tmp4;
2313 case TargetLowering::Promote: {
2314 // First step, figure out the appropriate operation to use.
2315 // Allow SETCC to not be supported for all legal data types
2316 // Mostly this targets FP
2317 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2318 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2320 // Scan for the appropriate larger type to use.
2322 NewInTy = (MVT::ValueType)(NewInTy+1);
2324 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2325 "Fell off of the edge of the integer world");
2326 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2327 "Fell off of the edge of the floating point world");
2329 // If the target supports SETCC of this type, use it.
2330 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2333 if (MVT::isInteger(NewInTy))
2334 assert(0 && "Cannot promote Legal Integer SETCC yet");
2336 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2337 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2339 Tmp1 = LegalizeOp(Tmp1);
2340 Tmp2 = LegalizeOp(Tmp2);
2341 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2342 Result = LegalizeOp(Result);
2345 case TargetLowering::Expand:
2346 // Expand a setcc node into a select_cc of the same condition, lhs, and
2347 // rhs that selects between const 1 (true) and const 0 (false).
2348 MVT::ValueType VT = Node->getValueType(0);
2349 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2350 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2357 case ISD::MEMMOVE: {
2358 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2359 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2361 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2362 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2363 case Expand: assert(0 && "Cannot expand a byte!");
2365 Tmp3 = LegalizeOp(Node->getOperand(2));
2368 Tmp3 = PromoteOp(Node->getOperand(2));
2372 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2376 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2378 // Length is too big, just take the lo-part of the length.
2380 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2384 Tmp4 = LegalizeOp(Node->getOperand(3));
2387 Tmp4 = PromoteOp(Node->getOperand(3));
2392 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2393 case Expand: assert(0 && "Cannot expand this yet!");
2395 Tmp5 = LegalizeOp(Node->getOperand(4));
2398 Tmp5 = PromoteOp(Node->getOperand(4));
2402 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2403 default: assert(0 && "This action not implemented for this operation!");
2404 case TargetLowering::Custom:
2407 case TargetLowering::Legal:
2408 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2410 Tmp1 = TLI.LowerOperation(Result, DAG);
2411 if (Tmp1.Val) Result = Tmp1;
2414 case TargetLowering::Expand: {
2415 // Otherwise, the target does not support this operation. Lower the
2416 // operation to an explicit libcall as appropriate.
2417 MVT::ValueType IntPtr = TLI.getPointerTy();
2418 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2419 TargetLowering::ArgListTy Args;
2420 TargetLowering::ArgListEntry Entry;
2422 const char *FnName = 0;
2423 if (Node->getOpcode() == ISD::MEMSET) {
2424 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2425 Args.push_back(Entry);
2426 // Extend the (previously legalized) ubyte argument to be an int value
2428 if (Tmp3.getValueType() > MVT::i32)
2429 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2431 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2432 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2433 Args.push_back(Entry);
2434 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2435 Args.push_back(Entry);
2438 } else if (Node->getOpcode() == ISD::MEMCPY ||
2439 Node->getOpcode() == ISD::MEMMOVE) {
2440 Entry.Ty = IntPtrTy;
2441 Entry.Node = Tmp2; Args.push_back(Entry);
2442 Entry.Node = Tmp3; Args.push_back(Entry);
2443 Entry.Node = Tmp4; Args.push_back(Entry);
2444 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2446 assert(0 && "Unknown op!");
2449 std::pair<SDOperand,SDOperand> CallResult =
2450 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2451 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2452 Result = CallResult.second;
2459 case ISD::SHL_PARTS:
2460 case ISD::SRA_PARTS:
2461 case ISD::SRL_PARTS: {
2462 SmallVector<SDOperand, 8> Ops;
2463 bool Changed = false;
2464 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2465 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2466 Changed |= Ops.back() != Node->getOperand(i);
2469 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2471 switch (TLI.getOperationAction(Node->getOpcode(),
2472 Node->getValueType(0))) {
2473 default: assert(0 && "This action is not supported yet!");
2474 case TargetLowering::Legal: break;
2475 case TargetLowering::Custom:
2476 Tmp1 = TLI.LowerOperation(Result, DAG);
2478 SDOperand Tmp2, RetVal(0, 0);
2479 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2480 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2481 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2485 assert(RetVal.Val && "Illegal result number");
2491 // Since these produce multiple values, make sure to remember that we
2492 // legalized all of them.
2493 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2494 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2495 return Result.getValue(Op.ResNo);
2516 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2517 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2518 case Expand: assert(0 && "Not possible");
2520 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2523 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2527 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2529 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2530 default: assert(0 && "BinOp legalize operation not supported");
2531 case TargetLowering::Legal: break;
2532 case TargetLowering::Custom:
2533 Tmp1 = TLI.LowerOperation(Result, DAG);
2534 if (Tmp1.Val) Result = Tmp1;
2536 case TargetLowering::Expand: {
2537 if (Node->getValueType(0) == MVT::i32) {
2538 switch (Node->getOpcode()) {
2539 default: assert(0 && "Do not know how to expand this integer BinOp!");
2542 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV
2543 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2545 bool isSigned = Node->getOpcode() == ISD::SDIV;
2546 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2551 assert(MVT::isVector(Node->getValueType(0)) &&
2552 "Cannot expand this binary operator!");
2553 // Expand the operation into a bunch of nasty scalar code.
2554 SmallVector<SDOperand, 8> Ops;
2555 MVT::ValueType EltVT = MVT::getVectorElementType(Node->getValueType(0));
2556 MVT::ValueType PtrVT = TLI.getPointerTy();
2557 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2559 SDOperand Idx = DAG.getConstant(i, PtrVT);
2560 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2561 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2562 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2564 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2565 &Ops[0], Ops.size());
2568 case TargetLowering::Promote: {
2569 switch (Node->getOpcode()) {
2570 default: assert(0 && "Do not know how to promote this BinOp!");
2574 MVT::ValueType OVT = Node->getValueType(0);
2575 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2576 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2577 // Bit convert each of the values to the new type.
2578 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2579 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2580 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2581 // Bit convert the result back the original type.
2582 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2590 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2591 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2592 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2593 case Expand: assert(0 && "Not possible");
2595 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2598 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2602 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2604 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2605 default: assert(0 && "Operation not supported");
2606 case TargetLowering::Custom:
2607 Tmp1 = TLI.LowerOperation(Result, DAG);
2608 if (Tmp1.Val) Result = Tmp1;
2610 case TargetLowering::Legal: break;
2611 case TargetLowering::Expand: {
2612 // If this target supports fabs/fneg natively and select is cheap,
2613 // do this efficiently.
2614 if (!TLI.isSelectExpensive() &&
2615 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
2616 TargetLowering::Legal &&
2617 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
2618 TargetLowering::Legal) {
2619 // Get the sign bit of the RHS.
2620 MVT::ValueType IVT =
2621 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2622 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2623 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2624 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2625 // Get the absolute value of the result.
2626 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2627 // Select between the nabs and abs value based on the sign bit of
2629 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2630 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2633 Result = LegalizeOp(Result);
2637 // Otherwise, do bitwise ops!
2638 MVT::ValueType NVT =
2639 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
2640 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
2641 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
2642 Result = LegalizeOp(Result);
2650 Tmp1 = LegalizeOp(Node->getOperand(0));
2651 Tmp2 = LegalizeOp(Node->getOperand(1));
2652 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2653 // Since this produces two values, make sure to remember that we legalized
2655 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2656 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2661 Tmp1 = LegalizeOp(Node->getOperand(0));
2662 Tmp2 = LegalizeOp(Node->getOperand(1));
2663 Tmp3 = LegalizeOp(Node->getOperand(2));
2664 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2665 // Since this produces two values, make sure to remember that we legalized
2667 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2668 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2671 case ISD::BUILD_PAIR: {
2672 MVT::ValueType PairTy = Node->getValueType(0);
2673 // TODO: handle the case where the Lo and Hi operands are not of legal type
2674 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2675 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2676 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2677 case TargetLowering::Promote:
2678 case TargetLowering::Custom:
2679 assert(0 && "Cannot promote/custom this yet!");
2680 case TargetLowering::Legal:
2681 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2682 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2684 case TargetLowering::Expand:
2685 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2686 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2687 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2688 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2689 TLI.getShiftAmountTy()));
2690 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2699 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2700 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2702 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2703 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2704 case TargetLowering::Custom:
2707 case TargetLowering::Legal:
2708 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2710 Tmp1 = TLI.LowerOperation(Result, DAG);
2711 if (Tmp1.Val) Result = Tmp1;
2714 case TargetLowering::Expand:
2715 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2716 bool isSigned = DivOpc == ISD::SDIV;
2717 if (MVT::isInteger(Node->getValueType(0))) {
2718 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2719 TargetLowering::Legal) {
2721 MVT::ValueType VT = Node->getValueType(0);
2722 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2723 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2724 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2726 assert(Node->getValueType(0) == MVT::i32 &&
2727 "Cannot expand this binary operator!");
2728 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
2729 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
2731 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2734 // Floating point mod -> fmod libcall.
2735 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2736 ? RTLIB::REM_F32 : RTLIB::REM_F64;
2738 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2739 false/*sign irrelevant*/, Dummy);
2745 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2746 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2748 MVT::ValueType VT = Node->getValueType(0);
2749 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2750 default: assert(0 && "This action is not supported yet!");
2751 case TargetLowering::Custom:
2754 case TargetLowering::Legal:
2755 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2756 Result = Result.getValue(0);
2757 Tmp1 = Result.getValue(1);
2760 Tmp2 = TLI.LowerOperation(Result, DAG);
2762 Result = LegalizeOp(Tmp2);
2763 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2767 case TargetLowering::Expand: {
2768 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2769 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2770 SV->getValue(), SV->getOffset());
2771 // Increment the pointer, VAList, to the next vaarg
2772 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2773 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2774 TLI.getPointerTy()));
2775 // Store the incremented VAList to the legalized pointer
2776 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
2778 // Load the actual argument out of the pointer VAList
2779 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2780 Tmp1 = LegalizeOp(Result.getValue(1));
2781 Result = LegalizeOp(Result);
2785 // Since VAARG produces two values, make sure to remember that we
2786 // legalized both of them.
2787 AddLegalizedOperand(SDOperand(Node, 0), Result);
2788 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2789 return Op.ResNo ? Tmp1 : Result;
2793 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2794 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2795 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2797 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2798 default: assert(0 && "This action is not supported yet!");
2799 case TargetLowering::Custom:
2802 case TargetLowering::Legal:
2803 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2804 Node->getOperand(3), Node->getOperand(4));
2806 Tmp1 = TLI.LowerOperation(Result, DAG);
2807 if (Tmp1.Val) Result = Tmp1;
2810 case TargetLowering::Expand:
2811 // This defaults to loading a pointer from the input and storing it to the
2812 // output, returning the chain.
2813 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
2814 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
2815 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
2817 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
2824 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2825 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2827 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2828 default: assert(0 && "This action is not supported yet!");
2829 case TargetLowering::Custom:
2832 case TargetLowering::Legal:
2833 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2835 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2836 if (Tmp1.Val) Result = Tmp1;
2839 case TargetLowering::Expand:
2840 Result = Tmp1; // Default to a no-op, return the chain
2846 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2847 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2849 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2851 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2852 default: assert(0 && "This action is not supported yet!");
2853 case TargetLowering::Legal: break;
2854 case TargetLowering::Custom:
2855 Tmp1 = TLI.LowerOperation(Result, DAG);
2856 if (Tmp1.Val) Result = Tmp1;
2863 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2864 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2865 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2866 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2868 assert(0 && "ROTL/ROTR legalize operation not supported");
2870 case TargetLowering::Legal:
2872 case TargetLowering::Custom:
2873 Tmp1 = TLI.LowerOperation(Result, DAG);
2874 if (Tmp1.Val) Result = Tmp1;
2876 case TargetLowering::Promote:
2877 assert(0 && "Do not know how to promote ROTL/ROTR");
2879 case TargetLowering::Expand:
2880 assert(0 && "Do not know how to expand ROTL/ROTR");
2886 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2887 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2888 case TargetLowering::Custom:
2889 assert(0 && "Cannot custom legalize this yet!");
2890 case TargetLowering::Legal:
2891 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2893 case TargetLowering::Promote: {
2894 MVT::ValueType OVT = Tmp1.getValueType();
2895 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2896 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
2898 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2899 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2900 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2901 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2904 case TargetLowering::Expand:
2905 Result = ExpandBSWAP(Tmp1);
2913 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2914 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2915 case TargetLowering::Custom:
2916 case TargetLowering::Legal:
2917 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2918 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
2919 TargetLowering::Custom) {
2920 Tmp1 = TLI.LowerOperation(Result, DAG);
2926 case TargetLowering::Promote: {
2927 MVT::ValueType OVT = Tmp1.getValueType();
2928 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2930 // Zero extend the argument.
2931 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2932 // Perform the larger operation, then subtract if needed.
2933 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2934 switch (Node->getOpcode()) {
2939 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2940 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2941 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
2943 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2944 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
2947 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2948 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2949 DAG.getConstant(MVT::getSizeInBits(NVT) -
2950 MVT::getSizeInBits(OVT), NVT));
2955 case TargetLowering::Expand:
2956 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2967 Tmp1 = LegalizeOp(Node->getOperand(0));
2968 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2969 case TargetLowering::Promote:
2970 case TargetLowering::Custom:
2973 case TargetLowering::Legal:
2974 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2976 Tmp1 = TLI.LowerOperation(Result, DAG);
2977 if (Tmp1.Val) Result = Tmp1;
2980 case TargetLowering::Expand:
2981 switch (Node->getOpcode()) {
2982 default: assert(0 && "Unreachable!");
2984 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2985 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2986 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2989 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2990 MVT::ValueType VT = Node->getValueType(0);
2991 Tmp2 = DAG.getConstantFP(0.0, VT);
2992 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2993 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2994 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3000 MVT::ValueType VT = Node->getValueType(0);
3001 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3002 switch(Node->getOpcode()) {
3004 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
3007 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
3010 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64;
3012 default: assert(0 && "Unreachable!");
3015 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3016 false/*sign irrelevant*/, Dummy);
3024 // We always lower FPOWI into a libcall. No target support it yet.
3025 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
3026 ? RTLIB::POWI_F32 : RTLIB::POWI_F64;
3028 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3029 false/*sign irrelevant*/, Dummy);
3032 case ISD::BIT_CONVERT:
3033 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3034 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3035 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3036 // The input has to be a vector type, we have to either scalarize it, pack
3037 // it, or convert it based on whether the input vector type is legal.
3038 SDNode *InVal = Node->getOperand(0).Val;
3039 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
3040 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
3042 // Figure out if there is a simple type corresponding to this Vector
3043 // type. If so, convert to the vector type.
3044 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3045 if (TLI.isTypeLegal(TVT)) {
3046 // Turn this into a bit convert of the vector input.
3047 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3048 LegalizeOp(Node->getOperand(0)));
3050 } else if (NumElems == 1) {
3051 // Turn this into a bit convert of the scalar input.
3052 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3053 ScalarizeVectorOp(Node->getOperand(0)));
3056 // FIXME: UNIMP! Store then reload
3057 assert(0 && "Cast from unsupported vector type not implemented yet!");
3060 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3061 Node->getOperand(0).getValueType())) {
3062 default: assert(0 && "Unknown operation action!");
3063 case TargetLowering::Expand:
3064 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3066 case TargetLowering::Legal:
3067 Tmp1 = LegalizeOp(Node->getOperand(0));
3068 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3074 // Conversion operators. The source and destination have different types.
3075 case ISD::SINT_TO_FP:
3076 case ISD::UINT_TO_FP: {
3077 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3078 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3080 switch (TLI.getOperationAction(Node->getOpcode(),
3081 Node->getOperand(0).getValueType())) {
3082 default: assert(0 && "Unknown operation action!");
3083 case TargetLowering::Custom:
3086 case TargetLowering::Legal:
3087 Tmp1 = LegalizeOp(Node->getOperand(0));
3088 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3090 Tmp1 = TLI.LowerOperation(Result, DAG);
3091 if (Tmp1.Val) Result = Tmp1;
3094 case TargetLowering::Expand:
3095 Result = ExpandLegalINT_TO_FP(isSigned,
3096 LegalizeOp(Node->getOperand(0)),
3097 Node->getValueType(0));
3099 case TargetLowering::Promote:
3100 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3101 Node->getValueType(0),
3107 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3108 Node->getValueType(0), Node->getOperand(0));
3111 Tmp1 = PromoteOp(Node->getOperand(0));
3113 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3114 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3116 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3117 Node->getOperand(0).getValueType());
3119 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3120 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3126 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3128 Tmp1 = LegalizeOp(Node->getOperand(0));
3129 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3132 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3134 // Since the result is legal, we should just be able to truncate the low
3135 // part of the source.
3136 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3139 Result = PromoteOp(Node->getOperand(0));
3140 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3145 case ISD::FP_TO_SINT:
3146 case ISD::FP_TO_UINT:
3147 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3149 Tmp1 = LegalizeOp(Node->getOperand(0));
3151 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3152 default: assert(0 && "Unknown operation action!");
3153 case TargetLowering::Custom:
3156 case TargetLowering::Legal:
3157 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3159 Tmp1 = TLI.LowerOperation(Result, DAG);
3160 if (Tmp1.Val) Result = Tmp1;
3163 case TargetLowering::Promote:
3164 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3165 Node->getOpcode() == ISD::FP_TO_SINT);
3167 case TargetLowering::Expand:
3168 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3169 SDOperand True, False;
3170 MVT::ValueType VT = Node->getOperand(0).getValueType();
3171 MVT::ValueType NVT = Node->getValueType(0);
3172 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
3173 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
3174 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3175 Node->getOperand(0), Tmp2, ISD::SETLT);
3176 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3177 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3178 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3180 False = DAG.getNode(ISD::XOR, NVT, False,
3181 DAG.getConstant(1ULL << ShiftAmt, NVT));
3182 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3185 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3191 // Convert f32 / f64 to i32 / i64.
3192 MVT::ValueType VT = Op.getValueType();
3193 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3194 switch (Node->getOpcode()) {
3195 case ISD::FP_TO_SINT:
3196 if (Node->getOperand(0).getValueType() == MVT::f32)
3197 LC = (VT == MVT::i32)
3198 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3200 LC = (VT == MVT::i32)
3201 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3203 case ISD::FP_TO_UINT:
3204 if (Node->getOperand(0).getValueType() == MVT::f32)
3205 LC = (VT == MVT::i32)
3206 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3208 LC = (VT == MVT::i32)
3209 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3211 default: assert(0 && "Unreachable!");
3214 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3215 false/*sign irrelevant*/, Dummy);
3219 Tmp1 = PromoteOp(Node->getOperand(0));
3220 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3221 Result = LegalizeOp(Result);
3226 case ISD::FP_EXTEND:
3227 case ISD::FP_ROUND: {
3228 MVT::ValueType newVT = Op.getValueType();
3229 MVT::ValueType oldVT = Op.getOperand(0).getValueType();
3230 if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) {
3231 // The only way we can lower this is to turn it into a STORE,
3232 // LOAD pair, targetting a temporary location (a stack slot).
3234 // NOTE: there is a choice here between constantly creating new stack
3235 // slots and always reusing the same one. We currently always create
3236 // new ones, as reuse may inhibit scheduling.
3237 MVT::ValueType slotVT =
3238 (Node->getOpcode() == ISD::FP_EXTEND) ? oldVT : newVT;
3239 const Type *Ty = MVT::getTypeForValueType(slotVT);
3240 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3241 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3242 MachineFunction &MF = DAG.getMachineFunction();
3244 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3245 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3246 if (Node->getOpcode() == ISD::FP_EXTEND) {
3247 Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0),
3248 StackSlot, NULL, 0);
3249 Result = DAG.getExtLoad(ISD::EXTLOAD, newVT,
3250 Result, StackSlot, NULL, 0, oldVT);
3252 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3253 StackSlot, NULL, 0, newVT);
3254 Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0, newVT);
3260 case ISD::ANY_EXTEND:
3261 case ISD::ZERO_EXTEND:
3262 case ISD::SIGN_EXTEND:
3263 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3264 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3266 Tmp1 = LegalizeOp(Node->getOperand(0));
3267 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3270 switch (Node->getOpcode()) {
3271 case ISD::ANY_EXTEND:
3272 Tmp1 = PromoteOp(Node->getOperand(0));
3273 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3275 case ISD::ZERO_EXTEND:
3276 Result = PromoteOp(Node->getOperand(0));
3277 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3278 Result = DAG.getZeroExtendInReg(Result,
3279 Node->getOperand(0).getValueType());
3281 case ISD::SIGN_EXTEND:
3282 Result = PromoteOp(Node->getOperand(0));
3283 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3284 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3286 DAG.getValueType(Node->getOperand(0).getValueType()));
3288 case ISD::FP_EXTEND:
3289 Result = PromoteOp(Node->getOperand(0));
3290 if (Result.getValueType() != Op.getValueType())
3291 // Dynamically dead while we have only 2 FP types.
3292 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
3295 Result = PromoteOp(Node->getOperand(0));
3296 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
3301 case ISD::FP_ROUND_INREG:
3302 case ISD::SIGN_EXTEND_INREG: {
3303 Tmp1 = LegalizeOp(Node->getOperand(0));
3304 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3306 // If this operation is not supported, convert it to a shl/shr or load/store
3308 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3309 default: assert(0 && "This action not supported for this op yet!");
3310 case TargetLowering::Legal:
3311 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3313 case TargetLowering::Expand:
3314 // If this is an integer extend and shifts are supported, do that.
3315 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3316 // NOTE: we could fall back on load/store here too for targets without
3317 // SAR. However, it is doubtful that any exist.
3318 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3319 MVT::getSizeInBits(ExtraVT);
3320 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3321 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3322 Node->getOperand(0), ShiftCst);
3323 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3325 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3326 // The only way we can lower this is to turn it into a TRUNCSTORE,
3327 // EXTLOAD pair, targetting a temporary location (a stack slot).
3329 // NOTE: there is a choice here between constantly creating new stack
3330 // slots and always reusing the same one. We currently always create
3331 // new ones, as reuse may inhibit scheduling.
3332 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
3333 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3334 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3335 MachineFunction &MF = DAG.getMachineFunction();
3337 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3338 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3339 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3340 StackSlot, NULL, 0, ExtraVT);
3341 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
3342 Result, StackSlot, NULL, 0, ExtraVT);
3344 assert(0 && "Unknown op");
3350 case ISD::ADJUST_TRAMP: {
3351 Tmp1 = LegalizeOp(Node->getOperand(0));
3352 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3353 default: assert(0 && "This action is not supported yet!");
3354 case TargetLowering::Custom:
3355 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3356 Result = TLI.LowerOperation(Result, DAG);
3357 if (Result.Val) break;
3359 case TargetLowering::Expand:
3365 case ISD::TRAMPOLINE: {
3367 for (unsigned i = 0; i != 6; ++i)
3368 Ops[i] = LegalizeOp(Node->getOperand(i));
3369 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3370 // The only option for this node is to custom lower it.
3371 Result = TLI.LowerOperation(Result, DAG);
3372 assert(Result.Val && "Should always custom lower!");
3377 assert(Result.getValueType() == Op.getValueType() &&
3378 "Bad legalization!");
3380 // Make sure that the generated code is itself legal.
3382 Result = LegalizeOp(Result);
3384 // Note that LegalizeOp may be reentered even from single-use nodes, which
3385 // means that we always must cache transformed nodes.
3386 AddLegalizedOperand(Op, Result);
3390 /// PromoteOp - Given an operation that produces a value in an invalid type,
3391 /// promote it to compute the value into a larger type. The produced value will
3392 /// have the correct bits for the low portion of the register, but no guarantee
3393 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3394 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3395 MVT::ValueType VT = Op.getValueType();
3396 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3397 assert(getTypeAction(VT) == Promote &&
3398 "Caller should expand or legalize operands that are not promotable!");
3399 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3400 "Cannot promote to smaller type!");
3402 SDOperand Tmp1, Tmp2, Tmp3;
3404 SDNode *Node = Op.Val;
3406 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3407 if (I != PromotedNodes.end()) return I->second;
3409 switch (Node->getOpcode()) {
3410 case ISD::CopyFromReg:
3411 assert(0 && "CopyFromReg must be legal!");
3414 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
3416 assert(0 && "Do not know how to promote this operator!");
3419 Result = DAG.getNode(ISD::UNDEF, NVT);
3423 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3425 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3426 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3428 case ISD::ConstantFP:
3429 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3430 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3434 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3435 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3436 Node->getOperand(1), Node->getOperand(2));
3440 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3442 Result = LegalizeOp(Node->getOperand(0));
3443 assert(Result.getValueType() >= NVT &&
3444 "This truncation doesn't make sense!");
3445 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3446 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3449 // The truncation is not required, because we don't guarantee anything
3450 // about high bits anyway.
3451 Result = PromoteOp(Node->getOperand(0));
3454 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3455 // Truncate the low part of the expanded value to the result type
3456 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3459 case ISD::SIGN_EXTEND:
3460 case ISD::ZERO_EXTEND:
3461 case ISD::ANY_EXTEND:
3462 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3463 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3465 // Input is legal? Just do extend all the way to the larger type.
3466 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3469 // Promote the reg if it's smaller.
3470 Result = PromoteOp(Node->getOperand(0));
3471 // The high bits are not guaranteed to be anything. Insert an extend.
3472 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3473 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3474 DAG.getValueType(Node->getOperand(0).getValueType()));
3475 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3476 Result = DAG.getZeroExtendInReg(Result,
3477 Node->getOperand(0).getValueType());
3481 case ISD::BIT_CONVERT:
3482 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3483 Result = PromoteOp(Result);
3486 case ISD::FP_EXTEND:
3487 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3489 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3490 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3491 case Promote: assert(0 && "Unreachable with 2 FP types!");
3493 // Input is legal? Do an FP_ROUND_INREG.
3494 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3495 DAG.getValueType(VT));
3500 case ISD::SINT_TO_FP:
3501 case ISD::UINT_TO_FP:
3502 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3504 // No extra round required here.
3505 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3509 Result = PromoteOp(Node->getOperand(0));
3510 if (Node->getOpcode() == ISD::SINT_TO_FP)
3511 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3513 DAG.getValueType(Node->getOperand(0).getValueType()));
3515 Result = DAG.getZeroExtendInReg(Result,
3516 Node->getOperand(0).getValueType());
3517 // No extra round required here.
3518 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3521 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3522 Node->getOperand(0));
3523 // Round if we cannot tolerate excess precision.
3524 if (NoExcessFPPrecision)
3525 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3526 DAG.getValueType(VT));
3531 case ISD::SIGN_EXTEND_INREG:
3532 Result = PromoteOp(Node->getOperand(0));
3533 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3534 Node->getOperand(1));
3536 case ISD::FP_TO_SINT:
3537 case ISD::FP_TO_UINT:
3538 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3541 Tmp1 = Node->getOperand(0);
3544 // The input result is prerounded, so we don't have to do anything
3546 Tmp1 = PromoteOp(Node->getOperand(0));
3549 // If we're promoting a UINT to a larger size, check to see if the new node
3550 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3551 // we can use that instead. This allows us to generate better code for
3552 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3553 // legal, such as PowerPC.
3554 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3555 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3556 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3557 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3558 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3560 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3566 Tmp1 = PromoteOp(Node->getOperand(0));
3567 assert(Tmp1.getValueType() == NVT);
3568 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3569 // NOTE: we do not have to do any extra rounding here for
3570 // NoExcessFPPrecision, because we know the input will have the appropriate
3571 // precision, and these operations don't modify precision at all.
3577 Tmp1 = PromoteOp(Node->getOperand(0));
3578 assert(Tmp1.getValueType() == NVT);
3579 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3580 if (NoExcessFPPrecision)
3581 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3582 DAG.getValueType(VT));
3586 // Promote f32 powi to f64 powi. Note that this could insert a libcall
3587 // directly as well, which may be better.
3588 Tmp1 = PromoteOp(Node->getOperand(0));
3589 assert(Tmp1.getValueType() == NVT);
3590 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
3591 if (NoExcessFPPrecision)
3592 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3593 DAG.getValueType(VT));
3603 // The input may have strange things in the top bits of the registers, but
3604 // these operations don't care. They may have weird bits going out, but
3605 // that too is okay if they are integer operations.
3606 Tmp1 = PromoteOp(Node->getOperand(0));
3607 Tmp2 = PromoteOp(Node->getOperand(1));
3608 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3609 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3614 Tmp1 = PromoteOp(Node->getOperand(0));
3615 Tmp2 = PromoteOp(Node->getOperand(1));
3616 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3617 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3619 // Floating point operations will give excess precision that we may not be
3620 // able to tolerate. If we DO allow excess precision, just leave it,
3621 // otherwise excise it.
3622 // FIXME: Why would we need to round FP ops more than integer ones?
3623 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3624 if (NoExcessFPPrecision)
3625 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3626 DAG.getValueType(VT));
3631 // These operators require that their input be sign extended.
3632 Tmp1 = PromoteOp(Node->getOperand(0));
3633 Tmp2 = PromoteOp(Node->getOperand(1));
3634 if (MVT::isInteger(NVT)) {
3635 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3636 DAG.getValueType(VT));
3637 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3638 DAG.getValueType(VT));
3640 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3642 // Perform FP_ROUND: this is probably overly pessimistic.
3643 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3644 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3645 DAG.getValueType(VT));
3649 case ISD::FCOPYSIGN:
3650 // These operators require that their input be fp extended.
3651 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3653 Tmp1 = LegalizeOp(Node->getOperand(0));
3656 Tmp1 = PromoteOp(Node->getOperand(0));
3659 assert(0 && "not implemented");
3661 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3663 Tmp2 = LegalizeOp(Node->getOperand(1));
3666 Tmp2 = PromoteOp(Node->getOperand(1));
3669 assert(0 && "not implemented");
3671 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3673 // Perform FP_ROUND: this is probably overly pessimistic.
3674 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3675 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3676 DAG.getValueType(VT));
3681 // These operators require that their input be zero extended.
3682 Tmp1 = PromoteOp(Node->getOperand(0));
3683 Tmp2 = PromoteOp(Node->getOperand(1));
3684 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3685 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3686 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3687 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3691 Tmp1 = PromoteOp(Node->getOperand(0));
3692 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3695 // The input value must be properly sign extended.
3696 Tmp1 = PromoteOp(Node->getOperand(0));
3697 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3698 DAG.getValueType(VT));
3699 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3702 // The input value must be properly zero extended.
3703 Tmp1 = PromoteOp(Node->getOperand(0));
3704 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3705 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3709 Tmp1 = Node->getOperand(0); // Get the chain.
3710 Tmp2 = Node->getOperand(1); // Get the pointer.
3711 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3712 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3713 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3715 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3716 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3717 SV->getValue(), SV->getOffset());
3718 // Increment the pointer, VAList, to the next vaarg
3719 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3720 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3721 TLI.getPointerTy()));
3722 // Store the incremented VAList to the legalized pointer
3723 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3725 // Load the actual argument out of the pointer VAList
3726 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
3728 // Remember that we legalized the chain.
3729 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3733 LoadSDNode *LD = cast<LoadSDNode>(Node);
3734 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
3735 ? ISD::EXTLOAD : LD->getExtensionType();
3736 Result = DAG.getExtLoad(ExtType, NVT,
3737 LD->getChain(), LD->getBasePtr(),
3738 LD->getSrcValue(), LD->getSrcValueOffset(),
3741 LD->getAlignment());
3742 // Remember that we legalized the chain.
3743 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3747 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3748 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3749 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3751 case ISD::SELECT_CC:
3752 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3753 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3754 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3755 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3758 Tmp1 = Node->getOperand(0);
3759 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3760 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3761 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3762 DAG.getConstant(MVT::getSizeInBits(NVT) -
3763 MVT::getSizeInBits(VT),
3764 TLI.getShiftAmountTy()));
3769 // Zero extend the argument
3770 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3771 // Perform the larger operation, then subtract if needed.
3772 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3773 switch(Node->getOpcode()) {
3778 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3779 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3780 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3782 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3783 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
3786 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3787 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3788 DAG.getConstant(MVT::getSizeInBits(NVT) -
3789 MVT::getSizeInBits(VT), NVT));
3793 case ISD::EXTRACT_SUBVECTOR:
3794 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
3796 case ISD::EXTRACT_VECTOR_ELT:
3797 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3801 assert(Result.Val && "Didn't set a result!");
3803 // Make sure the result is itself legal.
3804 Result = LegalizeOp(Result);
3806 // Remember that we promoted this!
3807 AddPromotedOperand(Op, Result);
3811 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3812 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
3813 /// based on the vector type. The return type of this matches the element type
3814 /// of the vector, which may not be legal for the target.
3815 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3816 // We know that operand #0 is the Vec vector. If the index is a constant
3817 // or if the invec is a supported hardware type, we can use it. Otherwise,
3818 // lower to a store then an indexed load.
3819 SDOperand Vec = Op.getOperand(0);
3820 SDOperand Idx = Op.getOperand(1);
3822 SDNode *InVal = Vec.Val;
3823 MVT::ValueType TVT = InVal->getValueType(0);
3824 unsigned NumElems = MVT::getVectorNumElements(TVT);
3826 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
3827 default: assert(0 && "This action is not supported yet!");
3828 case TargetLowering::Custom: {
3829 Vec = LegalizeOp(Vec);
3830 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3831 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
3836 case TargetLowering::Legal:
3837 if (isTypeLegal(TVT)) {
3838 Vec = LegalizeOp(Vec);
3839 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3843 case TargetLowering::Expand:
3847 if (NumElems == 1) {
3848 // This must be an access of the only element. Return it.
3849 Op = ScalarizeVectorOp(Vec);
3850 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
3851 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
3853 SplitVectorOp(Vec, Lo, Hi);
3854 if (CIdx->getValue() < NumElems/2) {
3858 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2,
3859 Idx.getValueType());
3862 // It's now an extract from the appropriate high or low part. Recurse.
3863 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3864 Op = ExpandEXTRACT_VECTOR_ELT(Op);
3866 // Store the value to a temporary stack slot, then LOAD the scalar
3867 // element back out.
3868 SDOperand StackPtr = CreateStackTemporary(Vec.getValueType());
3869 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
3871 // Add the offset to the index.
3872 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3873 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3874 DAG.getConstant(EltSize, Idx.getValueType()));
3875 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3877 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
3882 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
3883 /// we assume the operation can be split if it is not already legal.
3884 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
3885 // We know that operand #0 is the Vec vector. For now we assume the index
3886 // is a constant and that the extracted result is a supported hardware type.
3887 SDOperand Vec = Op.getOperand(0);
3888 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3890 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
3892 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
3893 // This must be an access of the desired vector length. Return it.
3897 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
3899 SplitVectorOp(Vec, Lo, Hi);
3900 if (CIdx->getValue() < NumElems/2) {
3904 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3907 // It's now an extract from the appropriate high or low part. Recurse.
3908 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3909 return ExpandEXTRACT_SUBVECTOR(Op);
3912 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3913 /// with condition CC on the current target. This usually involves legalizing
3914 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3915 /// there may be no choice but to create a new SetCC node to represent the
3916 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3917 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3918 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3921 SDOperand Tmp1, Tmp2, Result;
3923 switch (getTypeAction(LHS.getValueType())) {
3925 Tmp1 = LegalizeOp(LHS); // LHS
3926 Tmp2 = LegalizeOp(RHS); // RHS
3929 Tmp1 = PromoteOp(LHS); // LHS
3930 Tmp2 = PromoteOp(RHS); // RHS
3932 // If this is an FP compare, the operands have already been extended.
3933 if (MVT::isInteger(LHS.getValueType())) {
3934 MVT::ValueType VT = LHS.getValueType();
3935 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3937 // Otherwise, we have to insert explicit sign or zero extends. Note
3938 // that we could insert sign extends for ALL conditions, but zero extend
3939 // is cheaper on many machines (an AND instead of two shifts), so prefer
3941 switch (cast<CondCodeSDNode>(CC)->get()) {
3942 default: assert(0 && "Unknown integer comparison!");
3949 // ALL of these operations will work if we either sign or zero extend
3950 // the operands (including the unsigned comparisons!). Zero extend is
3951 // usually a simpler/cheaper operation, so prefer it.
3952 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3953 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3959 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3960 DAG.getValueType(VT));
3961 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3962 DAG.getValueType(VT));
3968 MVT::ValueType VT = LHS.getValueType();
3969 if (VT == MVT::f32 || VT == MVT::f64) {
3970 // Expand into one or more soft-fp libcall(s).
3971 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
3972 switch (cast<CondCodeSDNode>(CC)->get()) {
3975 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
3979 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
3983 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
3987 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3991 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
3995 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
3998 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4001 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4004 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4005 switch (cast<CondCodeSDNode>(CC)->get()) {
4007 // SETONE = SETOLT | SETOGT
4008 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4011 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4014 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4017 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4020 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4023 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4025 default: assert(0 && "Unsupported FP setcc!");
4030 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4031 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4032 false /*sign irrelevant*/, Dummy);
4033 Tmp2 = DAG.getConstant(0, MVT::i32);
4034 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4035 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4036 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4037 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4038 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4039 false /*sign irrelevant*/, Dummy);
4040 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4041 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4042 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4050 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4051 ExpandOp(LHS, LHSLo, LHSHi);
4052 ExpandOp(RHS, RHSLo, RHSHi);
4053 switch (cast<CondCodeSDNode>(CC)->get()) {
4057 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4058 if (RHSCST->isAllOnesValue()) {
4059 // Comparison to -1.
4060 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4065 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4066 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4067 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4068 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4071 // If this is a comparison of the sign bit, just look at the top part.
4073 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4074 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4075 CST->getValue() == 0) || // X < 0
4076 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4077 CST->isAllOnesValue())) { // X > -1
4083 // FIXME: This generated code sucks.
4084 ISD::CondCode LowCC;
4085 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4087 default: assert(0 && "Unknown integer setcc!");
4089 case ISD::SETULT: LowCC = ISD::SETULT; break;
4091 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4093 case ISD::SETULE: LowCC = ISD::SETULE; break;
4095 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4098 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4099 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4100 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4102 // NOTE: on targets without efficient SELECT of bools, we can always use
4103 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4104 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4105 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4106 false, DagCombineInfo);
4108 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4109 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4110 CCCode, false, DagCombineInfo);
4112 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
4114 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4115 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4116 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4117 (Tmp2C && Tmp2C->getValue() == 0 &&
4118 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4119 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4120 (Tmp2C && Tmp2C->getValue() == 1 &&
4121 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4122 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4123 // low part is known false, returns high part.
4124 // For LE / GE, if high part is known false, ignore the low part.
4125 // For LT / GT, if high part is known true, ignore the low part.
4129 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4130 ISD::SETEQ, false, DagCombineInfo);
4132 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4133 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4134 Result, Tmp1, Tmp2));
4145 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
4146 /// The resultant code need not be legal. Note that SrcOp is the input operand
4147 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
4148 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
4150 // Create the stack frame object.
4151 SDOperand FIPtr = CreateStackTemporary(DestVT);
4153 // Emit a store to the stack slot.
4154 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
4155 // Result is a load from the stack slot.
4156 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4159 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4160 // Create a vector sized/aligned stack slot, store the value to element #0,
4161 // then load the whole vector back out.
4162 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
4163 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4165 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
4169 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4170 /// support the operation, but do support the resultant vector type.
4171 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4173 // If the only non-undef value is the low element, turn this into a
4174 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4175 unsigned NumElems = Node->getNumOperands();
4176 bool isOnlyLowElement = true;
4177 SDOperand SplatValue = Node->getOperand(0);
4178 std::map<SDOperand, std::vector<unsigned> > Values;
4179 Values[SplatValue].push_back(0);
4180 bool isConstant = true;
4181 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4182 SplatValue.getOpcode() != ISD::UNDEF)
4185 for (unsigned i = 1; i < NumElems; ++i) {
4186 SDOperand V = Node->getOperand(i);
4187 Values[V].push_back(i);
4188 if (V.getOpcode() != ISD::UNDEF)
4189 isOnlyLowElement = false;
4190 if (SplatValue != V)
4191 SplatValue = SDOperand(0,0);
4193 // If this isn't a constant element or an undef, we can't use a constant
4195 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4196 V.getOpcode() != ISD::UNDEF)
4200 if (isOnlyLowElement) {
4201 // If the low element is an undef too, then this whole things is an undef.
4202 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4203 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4204 // Otherwise, turn this into a scalar_to_vector node.
4205 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4206 Node->getOperand(0));
4209 // If all elements are constants, create a load from the constant pool.
4211 MVT::ValueType VT = Node->getValueType(0);
4213 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4214 std::vector<Constant*> CV;
4215 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4216 if (ConstantFPSDNode *V =
4217 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4218 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4219 } else if (ConstantSDNode *V =
4220 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4221 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4223 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4224 CV.push_back(UndefValue::get(OpNTy));
4227 Constant *CP = ConstantVector::get(CV);
4228 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4229 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
4232 if (SplatValue.Val) { // Splat of one value?
4233 // Build the shuffle constant vector: <0, 0, 0, 0>
4234 MVT::ValueType MaskVT =
4235 MVT::getIntVectorWithNumElements(NumElems);
4236 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4237 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4238 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4239 &ZeroVec[0], ZeroVec.size());
4241 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4242 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4243 // Get the splatted value into the low element of a vector register.
4244 SDOperand LowValVec =
4245 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4247 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4248 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4249 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4254 // If there are only two unique elements, we may be able to turn this into a
4256 if (Values.size() == 2) {
4257 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4258 MVT::ValueType MaskVT =
4259 MVT::getIntVectorWithNumElements(NumElems);
4260 std::vector<SDOperand> MaskVec(NumElems);
4262 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4263 E = Values.end(); I != E; ++I) {
4264 for (std::vector<unsigned>::iterator II = I->second.begin(),
4265 EE = I->second.end(); II != EE; ++II)
4266 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4269 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4270 &MaskVec[0], MaskVec.size());
4272 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4273 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4274 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4275 SmallVector<SDOperand, 8> Ops;
4276 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4277 E = Values.end(); I != E; ++I) {
4278 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4282 Ops.push_back(ShuffleMask);
4284 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4285 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4286 &Ops[0], Ops.size());
4290 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4291 // aligned object on the stack, store each element into it, then load
4292 // the result as a vector.
4293 MVT::ValueType VT = Node->getValueType(0);
4294 // Create the stack frame object.
4295 SDOperand FIPtr = CreateStackTemporary(VT);
4297 // Emit a store of each element to the stack slot.
4298 SmallVector<SDOperand, 8> Stores;
4299 unsigned TypeByteSize =
4300 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4301 // Store (in the right endianness) the elements to memory.
4302 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4303 // Ignore undef elements.
4304 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4306 unsigned Offset = TypeByteSize*i;
4308 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4309 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4311 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4315 SDOperand StoreChain;
4316 if (!Stores.empty()) // Not all undef elements?
4317 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4318 &Stores[0], Stores.size());
4320 StoreChain = DAG.getEntryNode();
4322 // Result is a load from the stack slot.
4323 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4326 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
4327 /// specified value type.
4328 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
4329 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4330 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
4331 const Type *Ty = MVT::getTypeForValueType(VT);
4332 unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty);
4333 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign);
4334 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
4337 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4338 SDOperand Op, SDOperand Amt,
4339 SDOperand &Lo, SDOperand &Hi) {
4340 // Expand the subcomponents.
4341 SDOperand LHSL, LHSH;
4342 ExpandOp(Op, LHSL, LHSH);
4344 SDOperand Ops[] = { LHSL, LHSH, Amt };
4345 MVT::ValueType VT = LHSL.getValueType();
4346 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4347 Hi = Lo.getValue(1);
4351 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4352 /// smaller elements. If we can't find a way that is more efficient than a
4353 /// libcall on this target, return false. Otherwise, return true with the
4354 /// low-parts expanded into Lo and Hi.
4355 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4356 SDOperand &Lo, SDOperand &Hi) {
4357 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4358 "This is not a shift!");
4360 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4361 SDOperand ShAmt = LegalizeOp(Amt);
4362 MVT::ValueType ShTy = ShAmt.getValueType();
4363 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4364 unsigned NVTBits = MVT::getSizeInBits(NVT);
4366 // Handle the case when Amt is an immediate. Other cases are currently broken
4367 // and are disabled.
4368 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4369 unsigned Cst = CN->getValue();
4370 // Expand the incoming operand to be shifted, so that we have its parts
4372 ExpandOp(Op, InL, InH);
4376 Lo = DAG.getConstant(0, NVT);
4377 Hi = DAG.getConstant(0, NVT);
4378 } else if (Cst > NVTBits) {
4379 Lo = DAG.getConstant(0, NVT);
4380 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4381 } else if (Cst == NVTBits) {
4382 Lo = DAG.getConstant(0, NVT);
4385 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4386 Hi = DAG.getNode(ISD::OR, NVT,
4387 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4388 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4393 Lo = DAG.getConstant(0, NVT);
4394 Hi = DAG.getConstant(0, NVT);
4395 } else if (Cst > NVTBits) {
4396 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
4397 Hi = DAG.getConstant(0, NVT);
4398 } else if (Cst == NVTBits) {
4400 Hi = DAG.getConstant(0, NVT);
4402 Lo = DAG.getNode(ISD::OR, NVT,
4403 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4404 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4405 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
4410 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
4411 DAG.getConstant(NVTBits-1, ShTy));
4412 } else if (Cst > NVTBits) {
4413 Lo = DAG.getNode(ISD::SRA, NVT, InH,
4414 DAG.getConstant(Cst-NVTBits, ShTy));
4415 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4416 DAG.getConstant(NVTBits-1, ShTy));
4417 } else if (Cst == NVTBits) {
4419 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4420 DAG.getConstant(NVTBits-1, ShTy));
4422 Lo = DAG.getNode(ISD::OR, NVT,
4423 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4424 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4425 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
4431 // Okay, the shift amount isn't constant. However, if we can tell that it is
4432 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
4433 uint64_t Mask = NVTBits, KnownZero, KnownOne;
4434 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
4436 // If we know that the high bit of the shift amount is one, then we can do
4437 // this as a couple of simple shifts.
4438 if (KnownOne & Mask) {
4439 // Mask out the high bit, which we know is set.
4440 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
4441 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4443 // Expand the incoming operand to be shifted, so that we have its parts
4445 ExpandOp(Op, InL, InH);
4448 Lo = DAG.getConstant(0, NVT); // Low part is zero.
4449 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
4452 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
4453 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
4456 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
4457 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4458 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
4463 // If we know that the high bit of the shift amount is zero, then we can do
4464 // this as a couple of simple shifts.
4465 if (KnownZero & Mask) {
4467 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
4468 DAG.getConstant(NVTBits, Amt.getValueType()),
4471 // Expand the incoming operand to be shifted, so that we have its parts
4473 ExpandOp(Op, InL, InH);
4476 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
4477 Hi = DAG.getNode(ISD::OR, NVT,
4478 DAG.getNode(ISD::SHL, NVT, InH, Amt),
4479 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
4482 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
4483 Lo = DAG.getNode(ISD::OR, NVT,
4484 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4485 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4488 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
4489 Lo = DAG.getNode(ISD::OR, NVT,
4490 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4491 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4500 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
4501 // does not fit into a register, return the lo part and set the hi part to the
4502 // by-reg argument. If it does fit into a single register, return the result
4503 // and leave the Hi part unset.
4504 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
4505 bool isSigned, SDOperand &Hi) {
4506 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
4507 // The input chain to this libcall is the entry node of the function.
4508 // Legalizing the call will automatically add the previous call to the
4510 SDOperand InChain = DAG.getEntryNode();
4512 TargetLowering::ArgListTy Args;
4513 TargetLowering::ArgListEntry Entry;
4514 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4515 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
4516 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
4517 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
4518 Entry.isSExt = isSigned;
4519 Args.push_back(Entry);
4521 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
4523 // Splice the libcall in wherever FindInputOutputChains tells us to.
4524 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
4525 std::pair<SDOperand,SDOperand> CallInfo =
4526 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
4529 // Legalize the call sequence, starting with the chain. This will advance
4530 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
4531 // was added by LowerCallTo (guaranteeing proper serialization of calls).
4532 LegalizeOp(CallInfo.second);
4534 switch (getTypeAction(CallInfo.first.getValueType())) {
4535 default: assert(0 && "Unknown thing");
4537 Result = CallInfo.first;
4540 ExpandOp(CallInfo.first, Result, Hi);
4547 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
4549 SDOperand SelectionDAGLegalize::
4550 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
4551 assert(getTypeAction(Source.getValueType()) == Expand &&
4552 "This is not an expansion!");
4553 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
4556 assert(Source.getValueType() == MVT::i64 &&
4557 "This only works for 64-bit -> FP");
4558 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
4559 // incoming integer is set. To handle this, we dynamically test to see if
4560 // it is set, and, if so, add a fudge factor.
4562 ExpandOp(Source, Lo, Hi);
4564 // If this is unsigned, and not supported, first perform the conversion to
4565 // signed, then adjust the result if the sign bit is set.
4566 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
4567 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
4569 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
4570 DAG.getConstant(0, Hi.getValueType()),
4572 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4573 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4574 SignSet, Four, Zero);
4575 uint64_t FF = 0x5f800000ULL;
4576 if (TLI.isLittleEndian()) FF <<= 32;
4577 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4579 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4580 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4581 SDOperand FudgeInReg;
4582 if (DestTy == MVT::f32)
4583 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4585 assert(DestTy == MVT::f64 && "Unexpected conversion");
4586 // FIXME: Avoid the extend by construction the right constantpool?
4587 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
4588 CPIdx, NULL, 0, MVT::f32);
4590 MVT::ValueType SCVT = SignedConv.getValueType();
4591 if (SCVT != DestTy) {
4592 // Destination type needs to be expanded as well. The FADD now we are
4593 // constructing will be expanded into a libcall.
4594 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
4595 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
4596 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
4597 SignedConv, SignedConv.getValue(1));
4599 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
4601 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
4604 // Check to see if the target has a custom way to lower this. If so, use it.
4605 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
4606 default: assert(0 && "This action not implemented for this operation!");
4607 case TargetLowering::Legal:
4608 case TargetLowering::Expand:
4609 break; // This case is handled below.
4610 case TargetLowering::Custom: {
4611 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
4614 return LegalizeOp(NV);
4615 break; // The target decided this was legal after all
4619 // Expand the source, then glue it back together for the call. We must expand
4620 // the source in case it is shared (this pass of legalize must traverse it).
4621 SDOperand SrcLo, SrcHi;
4622 ExpandOp(Source, SrcLo, SrcHi);
4623 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
4626 if (DestTy == MVT::f32)
4627 LC = RTLIB::SINTTOFP_I64_F32;
4629 assert(DestTy == MVT::f64 && "Unknown fp value type!");
4630 LC = RTLIB::SINTTOFP_I64_F64;
4633 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
4634 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
4635 SDOperand UnusedHiPart;
4636 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
4640 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
4641 /// INT_TO_FP operation of the specified operand when the target requests that
4642 /// we expand it. At this point, we know that the result and operand types are
4643 /// legal for the target.
4644 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
4646 MVT::ValueType DestVT) {
4647 if (Op0.getValueType() == MVT::i32) {
4648 // simple 32-bit [signed|unsigned] integer to float/double expansion
4650 // get the stack frame index of a 8 byte buffer, pessimistically aligned
4651 MachineFunction &MF = DAG.getMachineFunction();
4652 const Type *F64Type = MVT::getTypeForValueType(MVT::f64);
4653 unsigned StackAlign =
4654 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type);
4655 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign);
4656 // get address of 8 byte buffer
4657 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4658 // word offset constant for Hi/Lo address computation
4659 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
4660 // set up Hi and Lo (into buffer) address based on endian
4661 SDOperand Hi = StackSlot;
4662 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4663 if (TLI.isLittleEndian())
4666 // if signed map to unsigned space
4667 SDOperand Op0Mapped;
4669 // constant used to invert sign bit (signed to unsigned mapping)
4670 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4671 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4675 // store the lo of the constructed double - based on integer input
4676 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4677 Op0Mapped, Lo, NULL, 0);
4678 // initial hi portion of constructed double
4679 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4680 // store the hi of the constructed double - biased exponent
4681 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
4682 // load the constructed double
4683 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4684 // FP constant to bias correct the final result
4685 SDOperand Bias = DAG.getConstantFP(isSigned ?
4686 BitsToDouble(0x4330000080000000ULL)
4687 : BitsToDouble(0x4330000000000000ULL),
4689 // subtract the bias
4690 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4693 // handle final rounding
4694 if (DestVT == MVT::f64) {
4698 // if f32 then cast to f32
4699 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
4703 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4704 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4706 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4707 DAG.getConstant(0, Op0.getValueType()),
4709 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4710 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4711 SignSet, Four, Zero);
4713 // If the sign bit of the integer is set, the large number will be treated
4714 // as a negative number. To counteract this, the dynamic code adds an
4715 // offset depending on the data type.
4717 switch (Op0.getValueType()) {
4718 default: assert(0 && "Unsupported integer type!");
4719 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4720 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4721 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4722 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4724 if (TLI.isLittleEndian()) FF <<= 32;
4725 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4727 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4728 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4729 SDOperand FudgeInReg;
4730 if (DestVT == MVT::f32)
4731 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4733 assert(DestVT == MVT::f64 && "Unexpected conversion");
4734 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
4735 DAG.getEntryNode(), CPIdx,
4736 NULL, 0, MVT::f32));
4739 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4742 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4743 /// *INT_TO_FP operation of the specified operand when the target requests that
4744 /// we promote it. At this point, we know that the result and operand types are
4745 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4746 /// operation that takes a larger input.
4747 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4748 MVT::ValueType DestVT,
4750 // First step, figure out the appropriate *INT_TO_FP operation to use.
4751 MVT::ValueType NewInTy = LegalOp.getValueType();
4753 unsigned OpToUse = 0;
4755 // Scan for the appropriate larger type to use.
4757 NewInTy = (MVT::ValueType)(NewInTy+1);
4758 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4760 // If the target supports SINT_TO_FP of this type, use it.
4761 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4763 case TargetLowering::Legal:
4764 if (!TLI.isTypeLegal(NewInTy))
4765 break; // Can't use this datatype.
4767 case TargetLowering::Custom:
4768 OpToUse = ISD::SINT_TO_FP;
4772 if (isSigned) continue;
4774 // If the target supports UINT_TO_FP of this type, use it.
4775 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4777 case TargetLowering::Legal:
4778 if (!TLI.isTypeLegal(NewInTy))
4779 break; // Can't use this datatype.
4781 case TargetLowering::Custom:
4782 OpToUse = ISD::UINT_TO_FP;
4787 // Otherwise, try a larger type.
4790 // Okay, we found the operation and type to use. Zero extend our input to the
4791 // desired type then run the operation on it.
4792 return DAG.getNode(OpToUse, DestVT,
4793 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4797 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4798 /// FP_TO_*INT operation of the specified operand when the target requests that
4799 /// we promote it. At this point, we know that the result and operand types are
4800 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4801 /// operation that returns a larger result.
4802 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4803 MVT::ValueType DestVT,
4805 // First step, figure out the appropriate FP_TO*INT operation to use.
4806 MVT::ValueType NewOutTy = DestVT;
4808 unsigned OpToUse = 0;
4810 // Scan for the appropriate larger type to use.
4812 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4813 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4815 // If the target supports FP_TO_SINT returning this type, use it.
4816 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4818 case TargetLowering::Legal:
4819 if (!TLI.isTypeLegal(NewOutTy))
4820 break; // Can't use this datatype.
4822 case TargetLowering::Custom:
4823 OpToUse = ISD::FP_TO_SINT;
4828 // If the target supports FP_TO_UINT of this type, use it.
4829 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4831 case TargetLowering::Legal:
4832 if (!TLI.isTypeLegal(NewOutTy))
4833 break; // Can't use this datatype.
4835 case TargetLowering::Custom:
4836 OpToUse = ISD::FP_TO_UINT;
4841 // Otherwise, try a larger type.
4844 // Okay, we found the operation and type to use. Truncate the result of the
4845 // extended FP_TO_*INT operation to the desired size.
4846 return DAG.getNode(ISD::TRUNCATE, DestVT,
4847 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4850 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4852 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4853 MVT::ValueType VT = Op.getValueType();
4854 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4855 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4857 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4859 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4860 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4861 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4863 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4864 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4865 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4866 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4867 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4868 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4869 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4870 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4871 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4873 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4874 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4875 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4876 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4877 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4878 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4879 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4880 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4881 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4882 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4883 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4884 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4885 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4886 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4887 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4888 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4889 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4890 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4891 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4892 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4893 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4897 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4899 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4901 default: assert(0 && "Cannot expand this yet!");
4903 static const uint64_t mask[6] = {
4904 0x5555555555555555ULL, 0x3333333333333333ULL,
4905 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4906 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4908 MVT::ValueType VT = Op.getValueType();
4909 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4910 unsigned len = MVT::getSizeInBits(VT);
4911 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4912 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4913 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4914 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4915 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4916 DAG.getNode(ISD::AND, VT,
4917 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4922 // for now, we do this:
4923 // x = x | (x >> 1);
4924 // x = x | (x >> 2);
4926 // x = x | (x >>16);
4927 // x = x | (x >>32); // for 64-bit input
4928 // return popcount(~x);
4930 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4931 MVT::ValueType VT = Op.getValueType();
4932 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4933 unsigned len = MVT::getSizeInBits(VT);
4934 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4935 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4936 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4938 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4939 return DAG.getNode(ISD::CTPOP, VT, Op);
4942 // for now, we use: { return popcount(~x & (x - 1)); }
4943 // unless the target has ctlz but not ctpop, in which case we use:
4944 // { return 32 - nlz(~x & (x-1)); }
4945 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4946 MVT::ValueType VT = Op.getValueType();
4947 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4948 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4949 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4950 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4951 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4952 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4953 TLI.isOperationLegal(ISD::CTLZ, VT))
4954 return DAG.getNode(ISD::SUB, VT,
4955 DAG.getConstant(MVT::getSizeInBits(VT), VT),
4956 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4957 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4962 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4963 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4964 /// LegalizeNodes map is filled in for any results that are not expanded, the
4965 /// ExpandedNodes map is filled in for any results that are expanded, and the
4966 /// Lo/Hi values are returned.
4967 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4968 MVT::ValueType VT = Op.getValueType();
4969 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4970 SDNode *Node = Op.Val;
4971 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4972 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
4973 MVT::isVector(VT)) &&
4974 "Cannot expand to FP value or to larger int value!");
4976 // See if we already expanded it.
4977 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4978 = ExpandedNodes.find(Op);
4979 if (I != ExpandedNodes.end()) {
4980 Lo = I->second.first;
4981 Hi = I->second.second;
4985 switch (Node->getOpcode()) {
4986 case ISD::CopyFromReg:
4987 assert(0 && "CopyFromReg must be legal!");
4990 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4992 assert(0 && "Do not know how to expand this operator!");
4995 NVT = TLI.getTypeToExpandTo(VT);
4996 Lo = DAG.getNode(ISD::UNDEF, NVT);
4997 Hi = DAG.getNode(ISD::UNDEF, NVT);
4999 case ISD::Constant: {
5000 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
5001 Lo = DAG.getConstant(Cst, NVT);
5002 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
5005 case ISD::ConstantFP: {
5006 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5007 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5008 if (getTypeAction(Lo.getValueType()) == Expand)
5009 ExpandOp(Lo, Lo, Hi);
5012 case ISD::BUILD_PAIR:
5013 // Return the operands.
5014 Lo = Node->getOperand(0);
5015 Hi = Node->getOperand(1);
5018 case ISD::SIGN_EXTEND_INREG:
5019 ExpandOp(Node->getOperand(0), Lo, Hi);
5020 // sext_inreg the low part if needed.
5021 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5023 // The high part gets the sign extension from the lo-part. This handles
5024 // things like sextinreg V:i64 from i8.
5025 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5026 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5027 TLI.getShiftAmountTy()));
5031 ExpandOp(Node->getOperand(0), Lo, Hi);
5032 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5033 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5039 ExpandOp(Node->getOperand(0), Lo, Hi);
5040 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5041 DAG.getNode(ISD::CTPOP, NVT, Lo),
5042 DAG.getNode(ISD::CTPOP, NVT, Hi));
5043 Hi = DAG.getConstant(0, NVT);
5047 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5048 ExpandOp(Node->getOperand(0), Lo, Hi);
5049 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5050 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5051 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5053 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5054 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5056 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5057 Hi = DAG.getConstant(0, NVT);
5062 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5063 ExpandOp(Node->getOperand(0), Lo, Hi);
5064 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5065 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5066 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5068 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5069 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5071 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5072 Hi = DAG.getConstant(0, NVT);
5077 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5078 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5079 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5080 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5082 // Remember that we legalized the chain.
5083 Hi = LegalizeOp(Hi);
5084 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5085 if (!TLI.isLittleEndian())
5091 LoadSDNode *LD = cast<LoadSDNode>(Node);
5092 SDOperand Ch = LD->getChain(); // Legalize the chain.
5093 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5094 ISD::LoadExtType ExtType = LD->getExtensionType();
5095 int SVOffset = LD->getSrcValueOffset();
5096 unsigned Alignment = LD->getAlignment();
5097 bool isVolatile = LD->isVolatile();
5099 if (ExtType == ISD::NON_EXTLOAD) {
5100 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5101 isVolatile, Alignment);
5102 if (VT == MVT::f32 || VT == MVT::f64) {
5103 // f32->i32 or f64->i64 one to one expansion.
5104 // Remember that we legalized the chain.
5105 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5106 // Recursively expand the new load.
5107 if (getTypeAction(NVT) == Expand)
5108 ExpandOp(Lo, Lo, Hi);
5112 // Increment the pointer to the other half.
5113 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5114 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5115 getIntPtrConstant(IncrementSize));
5116 SVOffset += IncrementSize;
5117 if (Alignment > IncrementSize)
5118 Alignment = IncrementSize;
5119 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5120 isVolatile, Alignment);
5122 // Build a factor node to remember that this load is independent of the
5124 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5127 // Remember that we legalized the chain.
5128 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5129 if (!TLI.isLittleEndian())
5132 MVT::ValueType EVT = LD->getLoadedVT();
5134 if (VT == MVT::f64 && EVT == MVT::f32) {
5135 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5136 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5137 SVOffset, isVolatile, Alignment);
5138 // Remember that we legalized the chain.
5139 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5140 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5145 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5146 SVOffset, isVolatile, Alignment);
5148 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5149 SVOffset, EVT, isVolatile,
5152 // Remember that we legalized the chain.
5153 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5155 if (ExtType == ISD::SEXTLOAD) {
5156 // The high part is obtained by SRA'ing all but one of the bits of the
5158 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5159 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5160 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5161 } else if (ExtType == ISD::ZEXTLOAD) {
5162 // The high part is just a zero.
5163 Hi = DAG.getConstant(0, NVT);
5164 } else /* if (ExtType == ISD::EXTLOAD) */ {
5165 // The high part is undefined.
5166 Hi = DAG.getNode(ISD::UNDEF, NVT);
5173 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5174 SDOperand LL, LH, RL, RH;
5175 ExpandOp(Node->getOperand(0), LL, LH);
5176 ExpandOp(Node->getOperand(1), RL, RH);
5177 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5178 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5182 SDOperand LL, LH, RL, RH;
5183 ExpandOp(Node->getOperand(1), LL, LH);
5184 ExpandOp(Node->getOperand(2), RL, RH);
5185 if (getTypeAction(NVT) == Expand)
5186 NVT = TLI.getTypeToExpandTo(NVT);
5187 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5189 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5192 case ISD::SELECT_CC: {
5193 SDOperand TL, TH, FL, FH;
5194 ExpandOp(Node->getOperand(2), TL, TH);
5195 ExpandOp(Node->getOperand(3), FL, FH);
5196 if (getTypeAction(NVT) == Expand)
5197 NVT = TLI.getTypeToExpandTo(NVT);
5198 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5199 Node->getOperand(1), TL, FL, Node->getOperand(4));
5201 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5202 Node->getOperand(1), TH, FH, Node->getOperand(4));
5205 case ISD::ANY_EXTEND:
5206 // The low part is any extension of the input (which degenerates to a copy).
5207 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5208 // The high part is undefined.
5209 Hi = DAG.getNode(ISD::UNDEF, NVT);
5211 case ISD::SIGN_EXTEND: {
5212 // The low part is just a sign extension of the input (which degenerates to
5214 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5216 // The high part is obtained by SRA'ing all but one of the bits of the lo
5218 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5219 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5220 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5223 case ISD::ZERO_EXTEND:
5224 // The low part is just a zero extension of the input (which degenerates to
5226 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5228 // The high part is just a zero.
5229 Hi = DAG.getConstant(0, NVT);
5232 case ISD::TRUNCATE: {
5233 // The input value must be larger than this value. Expand *it*.
5235 ExpandOp(Node->getOperand(0), NewLo, Hi);
5237 // The low part is now either the right size, or it is closer. If not the
5238 // right size, make an illegal truncate so we recursively expand it.
5239 if (NewLo.getValueType() != Node->getValueType(0))
5240 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
5241 ExpandOp(NewLo, Lo, Hi);
5245 case ISD::BIT_CONVERT: {
5247 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
5248 // If the target wants to, allow it to lower this itself.
5249 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5250 case Expand: assert(0 && "cannot expand FP!");
5251 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
5252 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
5254 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
5257 // f32 / f64 must be expanded to i32 / i64.
5258 if (VT == MVT::f32 || VT == MVT::f64) {
5259 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5260 if (getTypeAction(NVT) == Expand)
5261 ExpandOp(Lo, Lo, Hi);
5265 // If source operand will be expanded to the same type as VT, i.e.
5266 // i64 <- f64, i32 <- f32, expand the source operand instead.
5267 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
5268 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
5269 ExpandOp(Node->getOperand(0), Lo, Hi);
5273 // Turn this into a load/store pair by default.
5275 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0));
5277 ExpandOp(Tmp, Lo, Hi);
5281 case ISD::READCYCLECOUNTER:
5282 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5283 TargetLowering::Custom &&
5284 "Must custom expand ReadCycleCounter");
5285 Lo = TLI.LowerOperation(Op, DAG);
5286 assert(Lo.Val && "Node must be custom expanded!");
5287 Hi = Lo.getValue(1);
5288 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5289 LegalizeOp(Lo.getValue(2)));
5292 // These operators cannot be expanded directly, emit them as calls to
5293 // library functions.
5294 case ISD::FP_TO_SINT: {
5295 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5297 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5298 case Expand: assert(0 && "cannot expand FP!");
5299 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5300 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5303 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5305 // Now that the custom expander is done, expand the result, which is still
5308 ExpandOp(Op, Lo, Hi);
5314 if (Node->getOperand(0).getValueType() == MVT::f32)
5315 LC = RTLIB::FPTOSINT_F32_I64;
5317 LC = RTLIB::FPTOSINT_F64_I64;
5318 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5319 false/*sign irrelevant*/, Hi);
5323 case ISD::FP_TO_UINT: {
5324 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
5326 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5327 case Expand: assert(0 && "cannot expand FP!");
5328 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5329 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5332 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
5334 // Now that the custom expander is done, expand the result.
5336 ExpandOp(Op, Lo, Hi);
5342 if (Node->getOperand(0).getValueType() == MVT::f32)
5343 LC = RTLIB::FPTOUINT_F32_I64;
5345 LC = RTLIB::FPTOUINT_F64_I64;
5346 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5347 false/*sign irrelevant*/, Hi);
5352 // If the target wants custom lowering, do so.
5353 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5354 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
5355 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
5356 Op = TLI.LowerOperation(Op, DAG);
5358 // Now that the custom expander is done, expand the result, which is
5360 ExpandOp(Op, Lo, Hi);
5365 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
5366 // this X << 1 as X+X.
5367 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
5368 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
5369 TLI.isOperationLegal(ISD::ADDE, NVT)) {
5370 SDOperand LoOps[2], HiOps[3];
5371 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
5372 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
5373 LoOps[1] = LoOps[0];
5374 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5376 HiOps[1] = HiOps[0];
5377 HiOps[2] = Lo.getValue(1);
5378 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5383 // If we can emit an efficient shift operation, do so now.
5384 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5387 // If this target supports SHL_PARTS, use it.
5388 TargetLowering::LegalizeAction Action =
5389 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
5390 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5391 Action == TargetLowering::Custom) {
5392 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5396 // Otherwise, emit a libcall.
5397 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
5398 false/*left shift=unsigned*/, Hi);
5403 // If the target wants custom lowering, do so.
5404 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5405 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
5406 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
5407 Op = TLI.LowerOperation(Op, DAG);
5409 // Now that the custom expander is done, expand the result, which is
5411 ExpandOp(Op, Lo, Hi);
5416 // If we can emit an efficient shift operation, do so now.
5417 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
5420 // If this target supports SRA_PARTS, use it.
5421 TargetLowering::LegalizeAction Action =
5422 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
5423 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5424 Action == TargetLowering::Custom) {
5425 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5429 // Otherwise, emit a libcall.
5430 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
5431 true/*ashr is signed*/, Hi);
5436 // If the target wants custom lowering, do so.
5437 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5438 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
5439 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
5440 Op = TLI.LowerOperation(Op, DAG);
5442 // Now that the custom expander is done, expand the result, which is
5444 ExpandOp(Op, Lo, Hi);
5449 // If we can emit an efficient shift operation, do so now.
5450 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5453 // If this target supports SRL_PARTS, use it.
5454 TargetLowering::LegalizeAction Action =
5455 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
5456 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5457 Action == TargetLowering::Custom) {
5458 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5462 // Otherwise, emit a libcall.
5463 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
5464 false/*lshr is unsigned*/, Hi);
5470 // If the target wants to custom expand this, let them.
5471 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
5472 TargetLowering::Custom) {
5473 Op = TLI.LowerOperation(Op, DAG);
5475 ExpandOp(Op, Lo, Hi);
5480 // Expand the subcomponents.
5481 SDOperand LHSL, LHSH, RHSL, RHSH;
5482 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5483 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5484 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5485 SDOperand LoOps[2], HiOps[3];
5490 if (Node->getOpcode() == ISD::ADD) {
5491 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5492 HiOps[2] = Lo.getValue(1);
5493 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5495 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5496 HiOps[2] = Lo.getValue(1);
5497 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5504 // Expand the subcomponents.
5505 SDOperand LHSL, LHSH, RHSL, RHSH;
5506 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5507 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5508 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5509 SDOperand LoOps[2] = { LHSL, RHSL };
5510 SDOperand HiOps[3] = { LHSH, RHSH };
5512 if (Node->getOpcode() == ISD::ADDC) {
5513 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5514 HiOps[2] = Lo.getValue(1);
5515 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5517 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5518 HiOps[2] = Lo.getValue(1);
5519 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5521 // Remember that we legalized the flag.
5522 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5527 // Expand the subcomponents.
5528 SDOperand LHSL, LHSH, RHSL, RHSH;
5529 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5530 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5531 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5532 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
5533 SDOperand HiOps[3] = { LHSH, RHSH };
5535 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
5536 HiOps[2] = Lo.getValue(1);
5537 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
5539 // Remember that we legalized the flag.
5540 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5544 // If the target wants to custom expand this, let them.
5545 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
5546 SDOperand New = TLI.LowerOperation(Op, DAG);
5548 ExpandOp(New, Lo, Hi);
5553 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
5554 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
5555 if (HasMULHS || HasMULHU) {
5556 SDOperand LL, LH, RL, RH;
5557 ExpandOp(Node->getOperand(0), LL, LH);
5558 ExpandOp(Node->getOperand(1), RL, RH);
5559 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
5560 // FIXME: Move this to the dag combiner.
5561 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
5562 // extended the sign bit of the low half through the upper half, and if so
5563 // emit a MULHS instead of the alternate sequence that is valid for any
5564 // i64 x i64 multiply.
5566 // is RH an extension of the sign bit of RL?
5567 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
5568 RH.getOperand(1).getOpcode() == ISD::Constant &&
5569 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
5570 // is LH an extension of the sign bit of LL?
5571 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
5572 LH.getOperand(1).getOpcode() == ISD::Constant &&
5573 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
5575 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5577 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
5579 } else if (HasMULHU) {
5581 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5584 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
5585 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
5586 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
5587 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
5588 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
5593 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
5594 false/*sign irrelevant*/, Hi);
5598 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
5601 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
5604 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
5607 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
5611 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5612 ? RTLIB::ADD_F32 : RTLIB::ADD_F64),
5616 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5617 ? RTLIB::SUB_F32 : RTLIB::SUB_F64),
5621 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5622 ? RTLIB::MUL_F32 : RTLIB::MUL_F64),
5626 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5627 ? RTLIB::DIV_F32 : RTLIB::DIV_F64),
5630 case ISD::FP_EXTEND:
5631 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
5634 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
5637 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5638 ? RTLIB::POWI_F32 : RTLIB::POWI_F64),
5644 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5645 switch(Node->getOpcode()) {
5647 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
5650 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
5653 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64;
5655 default: assert(0 && "Unreachable!");
5657 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
5661 SDOperand Mask = (VT == MVT::f64)
5662 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
5663 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
5664 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5665 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5666 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
5667 if (getTypeAction(NVT) == Expand)
5668 ExpandOp(Lo, Lo, Hi);
5672 SDOperand Mask = (VT == MVT::f64)
5673 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
5674 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
5675 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5676 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5677 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
5678 if (getTypeAction(NVT) == Expand)
5679 ExpandOp(Lo, Lo, Hi);
5682 case ISD::FCOPYSIGN: {
5683 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
5684 if (getTypeAction(NVT) == Expand)
5685 ExpandOp(Lo, Lo, Hi);
5688 case ISD::SINT_TO_FP:
5689 case ISD::UINT_TO_FP: {
5690 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
5691 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
5693 if (Node->getOperand(0).getValueType() == MVT::i64) {
5695 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
5697 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
5700 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
5702 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
5705 // Promote the operand if needed.
5706 if (getTypeAction(SrcVT) == Promote) {
5707 SDOperand Tmp = PromoteOp(Node->getOperand(0));
5709 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
5710 DAG.getValueType(SrcVT))
5711 : DAG.getZeroExtendInReg(Tmp, SrcVT);
5712 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
5715 const char *LibCall = TLI.getLibcallName(LC);
5717 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
5719 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
5720 Node->getOperand(0));
5721 if (getTypeAction(Lo.getValueType()) == Expand)
5722 ExpandOp(Lo, Lo, Hi);
5728 // Make sure the resultant values have been legalized themselves, unless this
5729 // is a type that requires multi-step expansion.
5730 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
5731 Lo = LegalizeOp(Lo);
5733 // Don't legalize the high part if it is expanded to a single node.
5734 Hi = LegalizeOp(Hi);
5737 // Remember in a map if the values will be reused later.
5738 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
5739 assert(isNew && "Value already expanded?!?");
5742 /// SplitVectorOp - Given an operand of vector type, break it down into
5743 /// two smaller values, still of vector type.
5744 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
5746 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
5747 SDNode *Node = Op.Val;
5748 unsigned NumElements = MVT::getVectorNumElements(Node->getValueType(0));
5749 assert(NumElements > 1 && "Cannot split a single element vector!");
5750 unsigned NewNumElts = NumElements/2;
5751 MVT::ValueType NewEltVT = MVT::getVectorElementType(Node->getValueType(0));
5752 MVT::ValueType NewVT = MVT::getVectorType(NewEltVT, NewNumElts);
5754 // See if we already split it.
5755 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5756 = SplitNodes.find(Op);
5757 if (I != SplitNodes.end()) {
5758 Lo = I->second.first;
5759 Hi = I->second.second;
5763 switch (Node->getOpcode()) {
5768 assert(0 && "Unhandled operation in SplitVectorOp!");
5769 case ISD::BUILD_PAIR:
5770 Lo = Node->getOperand(0);
5771 Hi = Node->getOperand(1);
5773 case ISD::BUILD_VECTOR: {
5774 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5775 Node->op_begin()+NewNumElts);
5776 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &LoOps[0], LoOps.size());
5778 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
5780 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &HiOps[0], HiOps.size());
5783 case ISD::CONCAT_VECTORS: {
5784 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
5785 if (NewNumSubvectors == 1) {
5786 Lo = Node->getOperand(0);
5787 Hi = Node->getOperand(1);
5789 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5790 Node->op_begin()+NewNumSubvectors);
5791 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &LoOps[0], LoOps.size());
5793 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
5795 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &HiOps[0], HiOps.size());
5811 SDOperand LL, LH, RL, RH;
5812 SplitVectorOp(Node->getOperand(0), LL, LH);
5813 SplitVectorOp(Node->getOperand(1), RL, RH);
5815 Lo = DAG.getNode(Node->getOpcode(), NewVT, LL, RL);
5816 Hi = DAG.getNode(Node->getOpcode(), NewVT, LH, RH);
5820 LoadSDNode *LD = cast<LoadSDNode>(Node);
5821 SDOperand Ch = LD->getChain();
5822 SDOperand Ptr = LD->getBasePtr();
5823 const Value *SV = LD->getSrcValue();
5824 int SVOffset = LD->getSrcValueOffset();
5825 unsigned Alignment = LD->getAlignment();
5826 bool isVolatile = LD->isVolatile();
5828 Lo = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
5829 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(NewEltVT)/8;
5830 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5831 getIntPtrConstant(IncrementSize));
5832 SVOffset += IncrementSize;
5833 if (Alignment > IncrementSize)
5834 Alignment = IncrementSize;
5835 Hi = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
5837 // Build a factor node to remember that this load is independent of the
5839 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5842 // Remember that we legalized the chain.
5843 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5846 case ISD::BIT_CONVERT: {
5847 // We know the result is a vector. The input may be either a vector or a
5849 SDOperand InOp = Node->getOperand(0);
5850 if (!MVT::isVector(InOp.getValueType()) ||
5851 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
5852 // The input is a scalar or single-element vector.
5853 // Lower to a store/load so that it can be split.
5854 // FIXME: this could be improved probably.
5855 SDOperand Ptr = CreateStackTemporary(InOp.getValueType());
5857 SDOperand St = DAG.getStore(DAG.getEntryNode(),
5858 InOp, Ptr, NULL, 0);
5859 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0);
5861 // Split the vector and convert each of the pieces now.
5862 SplitVectorOp(InOp, Lo, Hi);
5863 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT, Lo);
5864 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT, Hi);
5869 // Remember in a map if the values will be reused later.
5871 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
5872 assert(isNew && "Value already split?!?");
5876 /// ScalarizeVectorOp - Given an operand of single-element vector type
5877 /// (e.g. v1f32), convert it into the equivalent operation that returns a
5878 /// scalar (e.g. f32) value.
5879 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
5880 assert(MVT::isVector(Op.getValueType()) &&
5881 "Bad ScalarizeVectorOp invocation!");
5882 SDNode *Node = Op.Val;
5883 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
5884 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
5886 // See if we already scalarized it.
5887 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
5888 if (I != ScalarizedNodes.end()) return I->second;
5891 switch (Node->getOpcode()) {
5894 Node->dump(&DAG); cerr << "\n";
5896 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
5912 Result = DAG.getNode(Node->getOpcode(),
5914 ScalarizeVectorOp(Node->getOperand(0)),
5915 ScalarizeVectorOp(Node->getOperand(1)));
5922 Result = DAG.getNode(Node->getOpcode(),
5924 ScalarizeVectorOp(Node->getOperand(0)));
5927 LoadSDNode *LD = cast<LoadSDNode>(Node);
5928 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
5929 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
5931 const Value *SV = LD->getSrcValue();
5932 int SVOffset = LD->getSrcValueOffset();
5933 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
5934 LD->isVolatile(), LD->getAlignment());
5936 // Remember that we legalized the chain.
5937 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
5940 case ISD::BUILD_VECTOR:
5941 Result = Node->getOperand(0);
5943 case ISD::INSERT_VECTOR_ELT:
5944 // Returning the inserted scalar element.
5945 Result = Node->getOperand(1);
5947 case ISD::CONCAT_VECTORS:
5948 assert(Node->getOperand(0).getValueType() == NewVT &&
5949 "Concat of non-legal vectors not yet supported!");
5950 Result = Node->getOperand(0);
5952 case ISD::VECTOR_SHUFFLE: {
5953 // Figure out if the scalar is the LHS or RHS and return it.
5954 SDOperand EltNum = Node->getOperand(2).getOperand(0);
5955 if (cast<ConstantSDNode>(EltNum)->getValue())
5956 Result = ScalarizeVectorOp(Node->getOperand(1));
5958 Result = ScalarizeVectorOp(Node->getOperand(0));
5961 case ISD::EXTRACT_SUBVECTOR:
5962 Result = Node->getOperand(0);
5963 assert(Result.getValueType() == NewVT);
5965 case ISD::BIT_CONVERT:
5966 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
5969 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
5970 ScalarizeVectorOp(Op.getOperand(1)),
5971 ScalarizeVectorOp(Op.getOperand(2)));
5975 if (TLI.isTypeLegal(NewVT))
5976 Result = LegalizeOp(Result);
5977 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
5978 assert(isNew && "Value already scalarized?");
5983 // SelectionDAG::Legalize - This is the entry point for the file.
5985 void SelectionDAG::Legalize() {
5986 if (ViewLegalizeDAGs) viewGraph();
5988 /// run - This is the main entry point to this class.
5990 SelectionDAGLegalize(*this).LegalizeDAG();