1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/Constants.h"
27 #include "llvm/DerivedTypes.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/SmallPtrSet.h"
39 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
40 cl::desc("Pop up a window to show dags before legalize"));
42 static const bool ViewLegalizeDAGs = 0;
45 //===----------------------------------------------------------------------===//
46 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
47 /// hacks on it until the target machine can handle it. This involves
48 /// eliminating value sizes the machine cannot handle (promoting small sizes to
49 /// large sizes or splitting up large values into small values) as well as
50 /// eliminating operations the machine cannot handle.
52 /// This code also does a small amount of optimization and recognition of idioms
53 /// as part of its processing. For example, if a target does not support a
54 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
55 /// will attempt merge setcc and brc instructions into brcc's.
58 class VISIBILITY_HIDDEN SelectionDAGLegalize {
62 // Libcall insertion helpers.
64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
65 /// legalized. We use this to ensure that calls are properly serialized
66 /// against each other, including inserted libcalls.
67 SDOperand LastCALLSEQ_END;
69 /// IsLegalizingCall - This member is used *only* for purposes of providing
70 /// helpful assertions that a libcall isn't created while another call is
71 /// being legalized (which could lead to non-serialized call sequences).
72 bool IsLegalizingCall;
75 Legal, // The target natively supports this operation.
76 Promote, // This operation should be executed in a larger type.
77 Expand // Try to expand this to other ops, otherwise use a libcall.
80 /// ValueTypeActions - This is a bitvector that contains two bits for each
81 /// value type, where the two bits correspond to the LegalizeAction enum.
82 /// This can be queried with "getTypeAction(VT)".
83 TargetLowering::ValueTypeActionImpl ValueTypeActions;
85 /// LegalizedNodes - For nodes that are of legal width, and that have more
86 /// than one use, this map indicates what regularized operand to use. This
87 /// allows us to avoid legalizing the same thing more than once.
88 DenseMap<SDOperand, SDOperand> LegalizedNodes;
90 /// PromotedNodes - For nodes that are below legal width, and that have more
91 /// than one use, this map indicates what promoted value to use. This allows
92 /// us to avoid promoting the same thing more than once.
93 DenseMap<SDOperand, SDOperand> PromotedNodes;
95 /// ExpandedNodes - For nodes that need to be expanded this map indicates
96 /// which which operands are the expanded version of the input. This allows
97 /// us to avoid expanding the same node more than once.
98 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
100 /// SplitNodes - For vector nodes that need to be split, this map indicates
101 /// which which operands are the split version of the input. This allows us
102 /// to avoid splitting the same node more than once.
103 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
105 /// ScalarizedNodes - For nodes that need to be converted from vector types to
106 /// scalar types, this contains the mapping of ones we have already
107 /// processed to the result.
108 std::map<SDOperand, SDOperand> ScalarizedNodes;
110 void AddLegalizedOperand(SDOperand From, SDOperand To) {
111 LegalizedNodes.insert(std::make_pair(From, To));
112 // If someone requests legalization of the new node, return itself.
114 LegalizedNodes.insert(std::make_pair(To, To));
116 void AddPromotedOperand(SDOperand From, SDOperand To) {
117 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
118 assert(isNew && "Got into the map somehow?");
119 // If someone requests legalization of the new node, return itself.
120 LegalizedNodes.insert(std::make_pair(To, To));
125 SelectionDAGLegalize(SelectionDAG &DAG);
127 /// getTypeAction - Return how we should legalize values of this type, either
128 /// it is already legal or we need to expand it into multiple registers of
129 /// smaller integer type, or we need to promote it to a larger type.
130 LegalizeAction getTypeAction(MVT::ValueType VT) const {
131 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
134 /// isTypeLegal - Return true if this type is legal on this target.
136 bool isTypeLegal(MVT::ValueType VT) const {
137 return getTypeAction(VT) == Legal;
143 /// HandleOp - Legalize, Promote, or Expand the specified operand as
144 /// appropriate for its type.
145 void HandleOp(SDOperand Op);
147 /// LegalizeOp - We know that the specified value has a legal type.
148 /// Recursively ensure that the operands have legal types, then return the
150 SDOperand LegalizeOp(SDOperand O);
152 /// UnrollVectorOp - We know that the given vector has a legal type, however
153 /// the operation it performs is not legal and is an operation that we have
154 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
155 /// operating on each element individually.
156 SDOperand UnrollVectorOp(SDOperand O);
158 /// PromoteOp - Given an operation that produces a value in an invalid type,
159 /// promote it to compute the value into a larger type. The produced value
160 /// will have the correct bits for the low portion of the register, but no
161 /// guarantee is made about the top bits: it may be zero, sign-extended, or
163 SDOperand PromoteOp(SDOperand O);
165 /// ExpandOp - Expand the specified SDOperand into its two component pieces
166 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
167 /// the LegalizeNodes map is filled in for any results that are not expanded,
168 /// the ExpandedNodes map is filled in for any results that are expanded, and
169 /// the Lo/Hi values are returned. This applies to integer types and Vector
171 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
173 /// SplitVectorOp - Given an operand of vector type, break it down into
174 /// two smaller values.
175 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
177 /// ScalarizeVectorOp - Given an operand of single-element vector type
178 /// (e.g. v1f32), convert it into the equivalent operation that returns a
179 /// scalar (e.g. f32) value.
180 SDOperand ScalarizeVectorOp(SDOperand O);
182 /// isShuffleLegal - Return true if a vector shuffle is legal with the
183 /// specified mask and type. Targets can specify exactly which masks they
184 /// support and the code generator is tasked with not creating illegal masks.
186 /// Note that this will also return true for shuffles that are promoted to a
189 /// If this is a legal shuffle, this method returns the (possibly promoted)
190 /// build_vector Mask. If it's not a legal shuffle, it returns null.
191 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
193 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
194 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
196 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
198 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
200 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
203 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT,
204 MVT::ValueType DestVT);
205 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
206 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
207 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
209 MVT::ValueType DestVT);
210 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
212 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
215 SDOperand ExpandBSWAP(SDOperand Op);
216 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
217 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
218 SDOperand &Lo, SDOperand &Hi);
219 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
220 SDOperand &Lo, SDOperand &Hi);
222 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
223 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
227 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
228 /// specified mask and type. Targets can specify exactly which masks they
229 /// support and the code generator is tasked with not creating illegal masks.
231 /// Note that this will also return true for shuffles that are promoted to a
233 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
234 SDOperand Mask) const {
235 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
237 case TargetLowering::Legal:
238 case TargetLowering::Custom:
240 case TargetLowering::Promote: {
241 // If this is promoted to a different type, convert the shuffle mask and
242 // ask if it is legal in the promoted type!
243 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
245 // If we changed # elements, change the shuffle mask.
246 unsigned NumEltsGrowth =
247 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
248 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
249 if (NumEltsGrowth > 1) {
250 // Renumber the elements.
251 SmallVector<SDOperand, 8> Ops;
252 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
253 SDOperand InOp = Mask.getOperand(i);
254 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
255 if (InOp.getOpcode() == ISD::UNDEF)
256 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
258 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
259 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
263 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
269 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
272 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
273 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
274 ValueTypeActions(TLI.getValueTypeActions()) {
275 assert(MVT::LAST_VALUETYPE <= 32 &&
276 "Too many value types for ValueTypeActions to hold!");
279 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
280 /// contains all of a nodes operands before it contains the node.
281 static void ComputeTopDownOrdering(SelectionDAG &DAG,
282 SmallVector<SDNode*, 64> &Order) {
284 DenseMap<SDNode*, unsigned> Visited;
285 std::vector<SDNode*> Worklist;
286 Worklist.reserve(128);
288 // Compute ordering from all of the leaves in the graphs, those (like the
289 // entry node) that have no operands.
290 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
291 E = DAG.allnodes_end(); I != E; ++I) {
292 if (I->getNumOperands() == 0) {
294 Worklist.push_back(I);
298 while (!Worklist.empty()) {
299 SDNode *N = Worklist.back();
302 if (++Visited[N] != N->getNumOperands())
303 continue; // Haven't visited all operands yet
307 // Now that we have N in, add anything that uses it if all of their operands
309 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
311 Worklist.push_back(*UI);
314 assert(Order.size() == Visited.size() &&
316 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
317 "Error: DAG is cyclic!");
321 void SelectionDAGLegalize::LegalizeDAG() {
322 LastCALLSEQ_END = DAG.getEntryNode();
323 IsLegalizingCall = false;
325 // The legalize process is inherently a bottom-up recursive process (users
326 // legalize their uses before themselves). Given infinite stack space, we
327 // could just start legalizing on the root and traverse the whole graph. In
328 // practice however, this causes us to run out of stack space on large basic
329 // blocks. To avoid this problem, compute an ordering of the nodes where each
330 // node is only legalized after all of its operands are legalized.
331 SmallVector<SDNode*, 64> Order;
332 ComputeTopDownOrdering(DAG, Order);
334 for (unsigned i = 0, e = Order.size(); i != e; ++i)
335 HandleOp(SDOperand(Order[i], 0));
337 // Finally, it's possible the root changed. Get the new root.
338 SDOperand OldRoot = DAG.getRoot();
339 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
340 DAG.setRoot(LegalizedNodes[OldRoot]);
342 ExpandedNodes.clear();
343 LegalizedNodes.clear();
344 PromotedNodes.clear();
346 ScalarizedNodes.clear();
348 // Remove dead nodes now.
349 DAG.RemoveDeadNodes();
353 /// FindCallEndFromCallStart - Given a chained node that is part of a call
354 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
355 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
356 if (Node->getOpcode() == ISD::CALLSEQ_END)
358 if (Node->use_empty())
359 return 0; // No CallSeqEnd
361 // The chain is usually at the end.
362 SDOperand TheChain(Node, Node->getNumValues()-1);
363 if (TheChain.getValueType() != MVT::Other) {
364 // Sometimes it's at the beginning.
365 TheChain = SDOperand(Node, 0);
366 if (TheChain.getValueType() != MVT::Other) {
367 // Otherwise, hunt for it.
368 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
369 if (Node->getValueType(i) == MVT::Other) {
370 TheChain = SDOperand(Node, i);
374 // Otherwise, we walked into a node without a chain.
375 if (TheChain.getValueType() != MVT::Other)
380 for (SDNode::use_iterator UI = Node->use_begin(),
381 E = Node->use_end(); UI != E; ++UI) {
383 // Make sure to only follow users of our token chain.
385 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
386 if (User->getOperand(i) == TheChain)
387 if (SDNode *Result = FindCallEndFromCallStart(User))
393 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
394 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
395 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
396 assert(Node && "Didn't find callseq_start for a call??");
397 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
399 assert(Node->getOperand(0).getValueType() == MVT::Other &&
400 "Node doesn't have a token chain argument!");
401 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
404 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
405 /// see if any uses can reach Dest. If no dest operands can get to dest,
406 /// legalize them, legalize ourself, and return false, otherwise, return true.
408 /// Keep track of the nodes we fine that actually do lead to Dest in
409 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
411 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
412 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
413 if (N == Dest) return true; // N certainly leads to Dest :)
415 // If we've already processed this node and it does lead to Dest, there is no
416 // need to reprocess it.
417 if (NodesLeadingTo.count(N)) return true;
419 // If the first result of this node has been already legalized, then it cannot
421 switch (getTypeAction(N->getValueType(0))) {
423 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
426 if (PromotedNodes.count(SDOperand(N, 0))) return false;
429 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
433 // Okay, this node has not already been legalized. Check and legalize all
434 // operands. If none lead to Dest, then we can legalize this node.
435 bool OperandsLeadToDest = false;
436 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
437 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
438 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
440 if (OperandsLeadToDest) {
441 NodesLeadingTo.insert(N);
445 // Okay, this node looks safe, legalize it and return false.
446 HandleOp(SDOperand(N, 0));
450 /// HandleOp - Legalize, Promote, or Expand the specified operand as
451 /// appropriate for its type.
452 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
453 MVT::ValueType VT = Op.getValueType();
454 switch (getTypeAction(VT)) {
455 default: assert(0 && "Bad type action!");
456 case Legal: (void)LegalizeOp(Op); break;
457 case Promote: (void)PromoteOp(Op); break;
459 if (!MVT::isVector(VT)) {
460 // If this is an illegal scalar, expand it into its two component
463 if (Op.getOpcode() == ISD::TargetConstant)
464 break; // Allow illegal target nodes.
466 } else if (MVT::getVectorNumElements(VT) == 1) {
467 // If this is an illegal single element vector, convert it to a
469 (void)ScalarizeVectorOp(Op);
471 // Otherwise, this is an illegal multiple element vector.
472 // Split it in half and legalize both parts.
474 SplitVectorOp(Op, X, Y);
480 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
481 /// a load from the constant pool.
482 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
483 SelectionDAG &DAG, TargetLowering &TLI) {
486 // If a FP immediate is precise when represented as a float and if the
487 // target can do an extending load from float to double, we put it into
488 // the constant pool as a float, even if it's is statically typed as a
490 MVT::ValueType VT = CFP->getValueType(0);
491 bool isDouble = VT == MVT::f64;
492 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
495 if (VT!=MVT::f64 && VT!=MVT::f32)
496 assert(0 && "Invalid type expansion");
497 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(),
498 isDouble ? MVT::i64 : MVT::i32);
501 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) &&
502 // Only do this if the target has a native EXTLOAD instruction from f32.
503 // Do not try to be clever about long doubles (so far)
504 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
505 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
510 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
512 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
513 CPIdx, PseudoSourceValue::getConstantPool(),
516 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
517 PseudoSourceValue::getConstantPool(), 0);
522 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
525 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
526 SelectionDAG &DAG, TargetLowering &TLI) {
527 MVT::ValueType VT = Node->getValueType(0);
528 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
529 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
530 "fcopysign expansion only supported for f32 and f64");
531 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
533 // First get the sign bit of second operand.
534 SDOperand Mask1 = (SrcVT == MVT::f64)
535 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
536 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
537 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
538 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
539 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
540 // Shift right or sign-extend it if the two operands have different types.
541 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
543 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
544 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
545 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
546 } else if (SizeDiff < 0)
547 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
549 // Clear the sign bit of first operand.
550 SDOperand Mask2 = (VT == MVT::f64)
551 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
552 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
553 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
554 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
555 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
557 // Or the value with the sign bit.
558 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
562 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
564 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
565 TargetLowering &TLI) {
566 SDOperand Chain = ST->getChain();
567 SDOperand Ptr = ST->getBasePtr();
568 SDOperand Val = ST->getValue();
569 MVT::ValueType VT = Val.getValueType();
570 int Alignment = ST->getAlignment();
571 int SVOffset = ST->getSrcValueOffset();
572 if (MVT::isFloatingPoint(ST->getMemoryVT())) {
573 // Expand to a bitconvert of the value to the integer type of the
574 // same size, then a (misaligned) int store.
575 MVT::ValueType intVT;
578 else if (VT==MVT::f32)
581 assert(0 && "Unaligned load of unsupported floating point type");
583 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
584 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
585 SVOffset, ST->isVolatile(), Alignment);
587 assert(MVT::isInteger(ST->getMemoryVT()) &&
588 "Unaligned store of unknown type.");
589 // Get the half-size VT
590 MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1;
591 int NumBits = MVT::getSizeInBits(NewStoredVT);
592 int IncrementSize = NumBits / 8;
594 // Divide the stored value in two parts.
595 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
597 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
599 // Store the two parts
600 SDOperand Store1, Store2;
601 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
602 ST->getSrcValue(), SVOffset, NewStoredVT,
603 ST->isVolatile(), Alignment);
604 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
605 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
606 Alignment = MinAlign(Alignment, IncrementSize);
607 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
608 ST->getSrcValue(), SVOffset + IncrementSize,
609 NewStoredVT, ST->isVolatile(), Alignment);
611 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
614 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
616 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
617 TargetLowering &TLI) {
618 int SVOffset = LD->getSrcValueOffset();
619 SDOperand Chain = LD->getChain();
620 SDOperand Ptr = LD->getBasePtr();
621 MVT::ValueType VT = LD->getValueType(0);
622 MVT::ValueType LoadedVT = LD->getMemoryVT();
623 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT)) {
624 // Expand to a (misaligned) integer load of the same size,
625 // then bitconvert to floating point.
626 MVT::ValueType intVT;
627 if (LoadedVT == MVT::f64)
629 else if (LoadedVT == MVT::f32)
632 assert(0 && "Unaligned load of unsupported floating point type");
634 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
635 SVOffset, LD->isVolatile(),
637 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
639 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
641 SDOperand Ops[] = { Result, Chain };
642 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
645 assert((MVT::isInteger(LoadedVT) || MVT::isVector(LoadedVT)) &&
646 "Unaligned load of unsupported type.");
648 // Compute the new VT that is half the size of the old one. We either have an
649 // integer MVT or we have a vector MVT.
650 unsigned NumBits = MVT::getSizeInBits(LoadedVT);
651 MVT::ValueType NewLoadedVT;
652 if (!MVT::isVector(LoadedVT)) {
653 NewLoadedVT = MVT::getIntegerType(NumBits/2);
655 // FIXME: This is not right for <1 x anything> it is also not right for
656 // non-power-of-two vectors.
657 NewLoadedVT = MVT::getVectorType(MVT::getVectorElementType(LoadedVT),
658 MVT::getVectorNumElements(LoadedVT)/2);
662 unsigned Alignment = LD->getAlignment();
663 unsigned IncrementSize = NumBits / 8;
664 ISD::LoadExtType HiExtType = LD->getExtensionType();
666 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
667 if (HiExtType == ISD::NON_EXTLOAD)
668 HiExtType = ISD::ZEXTLOAD;
670 // Load the value in two parts
672 if (TLI.isLittleEndian()) {
673 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
674 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
675 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
676 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
677 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
678 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
679 MinAlign(Alignment, IncrementSize));
681 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
682 NewLoadedVT,LD->isVolatile(), Alignment);
683 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
684 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
685 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
686 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
687 MinAlign(Alignment, IncrementSize));
690 // aggregate the two parts
691 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
692 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
693 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
695 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
698 SDOperand Ops[] = { Result, TF };
699 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
702 /// UnrollVectorOp - We know that the given vector has a legal type, however
703 /// the operation it performs is not legal and is an operation that we have
704 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
705 /// operating on each element individually.
706 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
707 MVT::ValueType VT = Op.getValueType();
708 assert(isTypeLegal(VT) &&
709 "Caller should expand or promote operands that are not legal!");
710 assert(Op.Val->getNumValues() == 1 &&
711 "Can't unroll a vector with multiple results!");
712 unsigned NE = MVT::getVectorNumElements(VT);
713 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
715 SmallVector<SDOperand, 8> Scalars;
716 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
717 for (unsigned i = 0; i != NE; ++i) {
718 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
719 SDOperand Operand = Op.getOperand(j);
720 MVT::ValueType OperandVT = Operand.getValueType();
721 if (MVT::isVector(OperandVT)) {
722 // A vector operand; extract a single element.
723 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
724 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
727 DAG.getConstant(i, MVT::i32));
729 // A scalar operand; just use it as is.
730 Operands[j] = Operand;
733 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
734 &Operands[0], Operands.size()));
737 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
740 /// GetFPLibCall - Return the right libcall for the given floating point type.
741 static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
742 RTLIB::Libcall Call_F32,
743 RTLIB::Libcall Call_F64,
744 RTLIB::Libcall Call_F80,
745 RTLIB::Libcall Call_PPCF128) {
747 VT == MVT::f32 ? Call_F32 :
748 VT == MVT::f64 ? Call_F64 :
749 VT == MVT::f80 ? Call_F80 :
750 VT == MVT::ppcf128 ? Call_PPCF128 :
751 RTLIB::UNKNOWN_LIBCALL;
754 /// LegalizeOp - We know that the specified value has a legal type, and
755 /// that its operands are legal. Now ensure that the operation itself
756 /// is legal, recursively ensuring that the operands' operations remain
758 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
759 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
762 assert(isTypeLegal(Op.getValueType()) &&
763 "Caller should expand or promote operands that are not legal!");
764 SDNode *Node = Op.Val;
766 // If this operation defines any values that cannot be represented in a
767 // register on this target, make sure to expand or promote them.
768 if (Node->getNumValues() > 1) {
769 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
770 if (getTypeAction(Node->getValueType(i)) != Legal) {
771 HandleOp(Op.getValue(i));
772 assert(LegalizedNodes.count(Op) &&
773 "Handling didn't add legal operands!");
774 return LegalizedNodes[Op];
778 // Note that LegalizeOp may be reentered even from single-use nodes, which
779 // means that we always must cache transformed nodes.
780 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
781 if (I != LegalizedNodes.end()) return I->second;
783 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
784 SDOperand Result = Op;
785 bool isCustom = false;
787 switch (Node->getOpcode()) {
788 case ISD::FrameIndex:
789 case ISD::EntryToken:
791 case ISD::BasicBlock:
792 case ISD::TargetFrameIndex:
793 case ISD::TargetJumpTable:
794 case ISD::TargetConstant:
795 case ISD::TargetConstantFP:
796 case ISD::TargetConstantPool:
797 case ISD::TargetGlobalAddress:
798 case ISD::TargetGlobalTLSAddress:
799 case ISD::TargetExternalSymbol:
802 case ISD::MEMOPERAND:
805 // Primitives must all be legal.
806 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
807 "This must be legal!");
810 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
811 // If this is a target node, legalize it by legalizing the operands then
812 // passing it through.
813 SmallVector<SDOperand, 8> Ops;
814 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
815 Ops.push_back(LegalizeOp(Node->getOperand(i)));
817 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
819 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
820 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
821 return Result.getValue(Op.ResNo);
823 // Otherwise this is an unhandled builtin node. splat.
825 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
827 assert(0 && "Do not know how to legalize this operator!");
829 case ISD::GLOBAL_OFFSET_TABLE:
830 case ISD::GlobalAddress:
831 case ISD::GlobalTLSAddress:
832 case ISD::ExternalSymbol:
833 case ISD::ConstantPool:
834 case ISD::JumpTable: // Nothing to do.
835 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
836 default: assert(0 && "This action is not supported yet!");
837 case TargetLowering::Custom:
838 Tmp1 = TLI.LowerOperation(Op, DAG);
839 if (Tmp1.Val) Result = Tmp1;
840 // FALLTHROUGH if the target doesn't want to lower this op after all.
841 case TargetLowering::Legal:
846 case ISD::RETURNADDR:
847 // The only option for these nodes is to custom lower them. If the target
848 // does not custom lower them, then return zero.
849 Tmp1 = TLI.LowerOperation(Op, DAG);
853 Result = DAG.getConstant(0, TLI.getPointerTy());
855 case ISD::FRAME_TO_ARGS_OFFSET: {
856 MVT::ValueType VT = Node->getValueType(0);
857 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
858 default: assert(0 && "This action is not supported yet!");
859 case TargetLowering::Custom:
860 Result = TLI.LowerOperation(Op, DAG);
861 if (Result.Val) break;
863 case TargetLowering::Legal:
864 Result = DAG.getConstant(0, VT);
869 case ISD::EXCEPTIONADDR: {
870 Tmp1 = LegalizeOp(Node->getOperand(0));
871 MVT::ValueType VT = Node->getValueType(0);
872 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
873 default: assert(0 && "This action is not supported yet!");
874 case TargetLowering::Expand: {
875 unsigned Reg = TLI.getExceptionAddressRegister();
876 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
879 case TargetLowering::Custom:
880 Result = TLI.LowerOperation(Op, DAG);
881 if (Result.Val) break;
883 case TargetLowering::Legal: {
884 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
885 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
891 if (Result.Val->getNumValues() == 1) break;
893 assert(Result.Val->getNumValues() == 2 &&
894 "Cannot return more than two values!");
896 // Since we produced two values, make sure to remember that we
897 // legalized both of them.
898 Tmp1 = LegalizeOp(Result);
899 Tmp2 = LegalizeOp(Result.getValue(1));
900 AddLegalizedOperand(Op.getValue(0), Tmp1);
901 AddLegalizedOperand(Op.getValue(1), Tmp2);
902 return Op.ResNo ? Tmp2 : Tmp1;
903 case ISD::EHSELECTION: {
904 Tmp1 = LegalizeOp(Node->getOperand(0));
905 Tmp2 = LegalizeOp(Node->getOperand(1));
906 MVT::ValueType VT = Node->getValueType(0);
907 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
908 default: assert(0 && "This action is not supported yet!");
909 case TargetLowering::Expand: {
910 unsigned Reg = TLI.getExceptionSelectorRegister();
911 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
914 case TargetLowering::Custom:
915 Result = TLI.LowerOperation(Op, DAG);
916 if (Result.Val) break;
918 case TargetLowering::Legal: {
919 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
920 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
926 if (Result.Val->getNumValues() == 1) break;
928 assert(Result.Val->getNumValues() == 2 &&
929 "Cannot return more than two values!");
931 // Since we produced two values, make sure to remember that we
932 // legalized both of them.
933 Tmp1 = LegalizeOp(Result);
934 Tmp2 = LegalizeOp(Result.getValue(1));
935 AddLegalizedOperand(Op.getValue(0), Tmp1);
936 AddLegalizedOperand(Op.getValue(1), Tmp2);
937 return Op.ResNo ? Tmp2 : Tmp1;
938 case ISD::EH_RETURN: {
939 MVT::ValueType VT = Node->getValueType(0);
940 // The only "good" option for this node is to custom lower it.
941 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
942 default: assert(0 && "This action is not supported at all!");
943 case TargetLowering::Custom:
944 Result = TLI.LowerOperation(Op, DAG);
945 if (Result.Val) break;
947 case TargetLowering::Legal:
948 // Target does not know, how to lower this, lower to noop
949 Result = LegalizeOp(Node->getOperand(0));
954 case ISD::AssertSext:
955 case ISD::AssertZext:
956 Tmp1 = LegalizeOp(Node->getOperand(0));
957 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
959 case ISD::MERGE_VALUES:
960 // Legalize eliminates MERGE_VALUES nodes.
961 Result = Node->getOperand(Op.ResNo);
963 case ISD::CopyFromReg:
964 Tmp1 = LegalizeOp(Node->getOperand(0));
965 Result = Op.getValue(0);
966 if (Node->getNumValues() == 2) {
967 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
969 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
970 if (Node->getNumOperands() == 3) {
971 Tmp2 = LegalizeOp(Node->getOperand(2));
972 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
974 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
976 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
978 // Since CopyFromReg produces two values, make sure to remember that we
979 // legalized both of them.
980 AddLegalizedOperand(Op.getValue(0), Result);
981 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
982 return Result.getValue(Op.ResNo);
984 MVT::ValueType VT = Op.getValueType();
985 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
986 default: assert(0 && "This action is not supported yet!");
987 case TargetLowering::Expand:
988 if (MVT::isInteger(VT))
989 Result = DAG.getConstant(0, VT);
990 else if (MVT::isFloatingPoint(VT))
991 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
994 assert(0 && "Unknown value type!");
996 case TargetLowering::Legal:
1002 case ISD::INTRINSIC_W_CHAIN:
1003 case ISD::INTRINSIC_WO_CHAIN:
1004 case ISD::INTRINSIC_VOID: {
1005 SmallVector<SDOperand, 8> Ops;
1006 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1007 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1008 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1010 // Allow the target to custom lower its intrinsics if it wants to.
1011 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1012 TargetLowering::Custom) {
1013 Tmp3 = TLI.LowerOperation(Result, DAG);
1014 if (Tmp3.Val) Result = Tmp3;
1017 if (Result.Val->getNumValues() == 1) break;
1019 // Must have return value and chain result.
1020 assert(Result.Val->getNumValues() == 2 &&
1021 "Cannot return more than two values!");
1023 // Since loads produce two values, make sure to remember that we
1024 // legalized both of them.
1025 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1026 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1027 return Result.getValue(Op.ResNo);
1031 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
1032 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1034 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
1035 case TargetLowering::Promote:
1036 default: assert(0 && "This action is not supported yet!");
1037 case TargetLowering::Expand: {
1038 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1039 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1040 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
1042 if (MMI && (useDEBUG_LOC || useLABEL)) {
1043 const std::string &FName =
1044 cast<StringSDNode>(Node->getOperand(3))->getValue();
1045 const std::string &DirName =
1046 cast<StringSDNode>(Node->getOperand(4))->getValue();
1047 unsigned SrcFile = MMI->RecordSource(DirName, FName);
1049 SmallVector<SDOperand, 8> Ops;
1050 Ops.push_back(Tmp1); // chain
1051 SDOperand LineOp = Node->getOperand(1);
1052 SDOperand ColOp = Node->getOperand(2);
1055 Ops.push_back(LineOp); // line #
1056 Ops.push_back(ColOp); // col #
1057 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1058 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1060 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
1061 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
1062 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1063 Ops.push_back(DAG.getConstant(ID, MVT::i32));
1064 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label
1065 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size());
1068 Result = Tmp1; // chain
1072 case TargetLowering::Legal:
1073 if (Tmp1 != Node->getOperand(0) ||
1074 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1075 SmallVector<SDOperand, 8> Ops;
1076 Ops.push_back(Tmp1);
1077 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1078 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1079 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1081 // Otherwise promote them.
1082 Ops.push_back(PromoteOp(Node->getOperand(1)));
1083 Ops.push_back(PromoteOp(Node->getOperand(2)));
1085 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1086 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1087 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1094 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1095 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1096 default: assert(0 && "This action is not supported yet!");
1097 case TargetLowering::Legal:
1098 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1099 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1100 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1101 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1106 case ISD::DEBUG_LOC:
1107 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1108 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1109 default: assert(0 && "This action is not supported yet!");
1110 case TargetLowering::Legal:
1111 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1112 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1113 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1114 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1115 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1121 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!");
1122 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1123 default: assert(0 && "This action is not supported yet!");
1124 case TargetLowering::Legal:
1125 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1126 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1127 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand.
1128 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1130 case TargetLowering::Expand:
1131 Result = LegalizeOp(Node->getOperand(0));
1136 case ISD::MEMBARRIER: {
1137 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1138 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1139 default: assert(0 && "This action is not supported yet!");
1140 case TargetLowering::Legal: {
1142 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1143 for (int x = 1; x < 6; ++x)
1144 Ops[x] = PromoteOp(Node->getOperand(x));
1145 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1148 case TargetLowering::Expand:
1149 //There is no libgcc call for this op
1150 Result = Node->getOperand(0); // Noop
1156 case ISD::ATOMIC_LCS:
1157 case ISD::ATOMIC_LAS:
1158 case ISD::ATOMIC_SWAP: {
1159 assert(((Node->getNumOperands() == 4 && Node->getOpcode() == ISD::ATOMIC_LCS) ||
1160 (Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_LAS) ||
1161 (Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_SWAP)) &&
1162 "Invalid MemBarrier node!");
1163 int num = Node->getOpcode() == ISD::ATOMIC_LCS ? 4 : 3;
1164 MVT::ValueType VT = Node->getValueType(0);
1165 switch (TLI.getOperationAction(ISD::ATOMIC_LCS, VT)) {
1166 default: assert(0 && "This action is not supported yet!");
1167 case TargetLowering::Legal: {
1169 for (int x = 0; x < num; ++x)
1170 Ops[x] = LegalizeOp(Node->getOperand(x));
1171 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num);
1172 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1173 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1174 return Result.getValue(Op.ResNo);
1181 case ISD::Constant: {
1182 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1184 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1186 // We know we don't need to expand constants here, constants only have one
1187 // value and we check that it is fine above.
1189 if (opAction == TargetLowering::Custom) {
1190 Tmp1 = TLI.LowerOperation(Result, DAG);
1196 case ISD::ConstantFP: {
1197 // Spill FP immediates to the constant pool if the target cannot directly
1198 // codegen them. Targets often have some immediate values that can be
1199 // efficiently generated into an FP register without a load. We explicitly
1200 // leave these constants as ConstantFP nodes for the target to deal with.
1201 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1203 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1204 default: assert(0 && "This action is not supported yet!");
1205 case TargetLowering::Legal:
1207 case TargetLowering::Custom:
1208 Tmp3 = TLI.LowerOperation(Result, DAG);
1214 case TargetLowering::Expand: {
1215 // Check to see if this FP immediate is already legal.
1216 bool isLegal = false;
1217 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1218 E = TLI.legal_fpimm_end(); I != E; ++I) {
1219 if (CFP->isExactlyValue(*I)) {
1224 // If this is a legal constant, turn it into a TargetConstantFP node.
1227 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1232 case ISD::TokenFactor:
1233 if (Node->getNumOperands() == 2) {
1234 Tmp1 = LegalizeOp(Node->getOperand(0));
1235 Tmp2 = LegalizeOp(Node->getOperand(1));
1236 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1237 } else if (Node->getNumOperands() == 3) {
1238 Tmp1 = LegalizeOp(Node->getOperand(0));
1239 Tmp2 = LegalizeOp(Node->getOperand(1));
1240 Tmp3 = LegalizeOp(Node->getOperand(2));
1241 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1243 SmallVector<SDOperand, 8> Ops;
1244 // Legalize the operands.
1245 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1246 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1247 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1251 case ISD::FORMAL_ARGUMENTS:
1253 // The only option for this is to custom lower it.
1254 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1255 assert(Tmp3.Val && "Target didn't custom lower this node!");
1257 // The number of incoming and outgoing values should match; unless the final
1258 // outgoing value is a flag.
1259 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1260 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1261 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1263 "Lowering call/formal_arguments produced unexpected # results!");
1265 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1266 // remember that we legalized all of them, so it doesn't get relegalized.
1267 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1268 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1270 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1273 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1276 case ISD::EXTRACT_SUBREG: {
1277 Tmp1 = LegalizeOp(Node->getOperand(0));
1278 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1279 assert(idx && "Operand must be a constant");
1280 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1281 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1284 case ISD::INSERT_SUBREG: {
1285 Tmp1 = LegalizeOp(Node->getOperand(0));
1286 Tmp2 = LegalizeOp(Node->getOperand(1));
1287 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1288 assert(idx && "Operand must be a constant");
1289 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1290 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1293 case ISD::BUILD_VECTOR:
1294 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1295 default: assert(0 && "This action is not supported yet!");
1296 case TargetLowering::Custom:
1297 Tmp3 = TLI.LowerOperation(Result, DAG);
1303 case TargetLowering::Expand:
1304 Result = ExpandBUILD_VECTOR(Result.Val);
1308 case ISD::INSERT_VECTOR_ELT:
1309 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1310 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1312 // The type of the value to insert may not be legal, even though the vector
1313 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1315 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1316 default: assert(0 && "Cannot expand insert element operand");
1317 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1318 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1320 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1322 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1323 Node->getValueType(0))) {
1324 default: assert(0 && "This action is not supported yet!");
1325 case TargetLowering::Legal:
1327 case TargetLowering::Custom:
1328 Tmp4 = TLI.LowerOperation(Result, DAG);
1334 case TargetLowering::Expand: {
1335 // If the insert index is a constant, codegen this as a scalar_to_vector,
1336 // then a shuffle that inserts it into the right position in the vector.
1337 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1338 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1339 // match the element type of the vector being created.
1340 if (Tmp2.getValueType() ==
1341 MVT::getVectorElementType(Op.getValueType())) {
1342 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1343 Tmp1.getValueType(), Tmp2);
1345 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1346 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1347 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1349 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1350 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1351 // elt 0 of the RHS.
1352 SmallVector<SDOperand, 8> ShufOps;
1353 for (unsigned i = 0; i != NumElts; ++i) {
1354 if (i != InsertPos->getValue())
1355 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1357 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1359 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1360 &ShufOps[0], ShufOps.size());
1362 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1363 Tmp1, ScVec, ShufMask);
1364 Result = LegalizeOp(Result);
1369 // If the target doesn't support this, we have to spill the input vector
1370 // to a temporary stack slot, update the element, then reload it. This is
1371 // badness. We could also load the value into a vector register (either
1372 // with a "move to register" or "extload into register" instruction, then
1373 // permute it into place, if the idx is a constant and if the idx is
1374 // supported by the target.
1375 MVT::ValueType VT = Tmp1.getValueType();
1376 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1377 MVT::ValueType IdxVT = Tmp3.getValueType();
1378 MVT::ValueType PtrVT = TLI.getPointerTy();
1379 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
1381 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val);
1382 int SPFI = StackPtrFI->getIndex();
1384 // Store the vector.
1385 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
1386 PseudoSourceValue::getFixedStack(),
1389 // Truncate or zero extend offset to target pointer type.
1390 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1391 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1392 // Add the offset to the index.
1393 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1394 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1395 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1396 // Store the scalar value.
1397 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
1398 PseudoSourceValue::getFixedStack(), SPFI, EltVT);
1399 // Load the updated vector.
1400 Result = DAG.getLoad(VT, Ch, StackPtr,
1401 PseudoSourceValue::getFixedStack(), SPFI);
1406 case ISD::SCALAR_TO_VECTOR:
1407 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1408 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1412 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1413 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1414 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1415 Node->getValueType(0))) {
1416 default: assert(0 && "This action is not supported yet!");
1417 case TargetLowering::Legal:
1419 case TargetLowering::Custom:
1420 Tmp3 = TLI.LowerOperation(Result, DAG);
1426 case TargetLowering::Expand:
1427 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1431 case ISD::VECTOR_SHUFFLE:
1432 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1433 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1434 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1436 // Allow targets to custom lower the SHUFFLEs they support.
1437 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1438 default: assert(0 && "Unknown operation action!");
1439 case TargetLowering::Legal:
1440 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1441 "vector shuffle should not be created if not legal!");
1443 case TargetLowering::Custom:
1444 Tmp3 = TLI.LowerOperation(Result, DAG);
1450 case TargetLowering::Expand: {
1451 MVT::ValueType VT = Node->getValueType(0);
1452 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1453 MVT::ValueType PtrVT = TLI.getPointerTy();
1454 SDOperand Mask = Node->getOperand(2);
1455 unsigned NumElems = Mask.getNumOperands();
1456 SmallVector<SDOperand,8> Ops;
1457 for (unsigned i = 0; i != NumElems; ++i) {
1458 SDOperand Arg = Mask.getOperand(i);
1459 if (Arg.getOpcode() == ISD::UNDEF) {
1460 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1462 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1463 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1465 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1466 DAG.getConstant(Idx, PtrVT)));
1468 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1469 DAG.getConstant(Idx - NumElems, PtrVT)));
1472 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1475 case TargetLowering::Promote: {
1476 // Change base type to a different vector type.
1477 MVT::ValueType OVT = Node->getValueType(0);
1478 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1480 // Cast the two input vectors.
1481 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1482 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1484 // Convert the shuffle mask to the right # elements.
1485 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1486 assert(Tmp3.Val && "Shuffle not legal?");
1487 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1488 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1494 case ISD::EXTRACT_VECTOR_ELT:
1495 Tmp1 = Node->getOperand(0);
1496 Tmp2 = LegalizeOp(Node->getOperand(1));
1497 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1498 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1501 case ISD::EXTRACT_SUBVECTOR:
1502 Tmp1 = Node->getOperand(0);
1503 Tmp2 = LegalizeOp(Node->getOperand(1));
1504 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1505 Result = ExpandEXTRACT_SUBVECTOR(Result);
1508 case ISD::CALLSEQ_START: {
1509 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1511 // Recursively Legalize all of the inputs of the call end that do not lead
1512 // to this call start. This ensures that any libcalls that need be inserted
1513 // are inserted *before* the CALLSEQ_START.
1514 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1515 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1516 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1520 // Now that we legalized all of the inputs (which may have inserted
1521 // libcalls) create the new CALLSEQ_START node.
1522 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1524 // Merge in the last call, to ensure that this call start after the last
1526 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1527 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1528 Tmp1 = LegalizeOp(Tmp1);
1531 // Do not try to legalize the target-specific arguments (#1+).
1532 if (Tmp1 != Node->getOperand(0)) {
1533 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1535 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1538 // Remember that the CALLSEQ_START is legalized.
1539 AddLegalizedOperand(Op.getValue(0), Result);
1540 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1541 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1543 // Now that the callseq_start and all of the non-call nodes above this call
1544 // sequence have been legalized, legalize the call itself. During this
1545 // process, no libcalls can/will be inserted, guaranteeing that no calls
1547 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1548 SDOperand InCallSEQ = LastCALLSEQ_END;
1549 // Note that we are selecting this call!
1550 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1551 IsLegalizingCall = true;
1553 // Legalize the call, starting from the CALLSEQ_END.
1554 LegalizeOp(LastCALLSEQ_END);
1555 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1558 case ISD::CALLSEQ_END:
1559 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1560 // will cause this node to be legalized as well as handling libcalls right.
1561 if (LastCALLSEQ_END.Val != Node) {
1562 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1563 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1564 assert(I != LegalizedNodes.end() &&
1565 "Legalizing the call start should have legalized this node!");
1569 // Otherwise, the call start has been legalized and everything is going
1570 // according to plan. Just legalize ourselves normally here.
1571 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1572 // Do not try to legalize the target-specific arguments (#1+), except for
1573 // an optional flag input.
1574 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1575 if (Tmp1 != Node->getOperand(0)) {
1576 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1578 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1581 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1582 if (Tmp1 != Node->getOperand(0) ||
1583 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1584 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1587 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1590 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1591 // This finishes up call legalization.
1592 IsLegalizingCall = false;
1594 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1595 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1596 if (Node->getNumValues() == 2)
1597 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1598 return Result.getValue(Op.ResNo);
1599 case ISD::DYNAMIC_STACKALLOC: {
1600 MVT::ValueType VT = Node->getValueType(0);
1601 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1602 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1603 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1604 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1606 Tmp1 = Result.getValue(0);
1607 Tmp2 = Result.getValue(1);
1608 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1609 default: assert(0 && "This action is not supported yet!");
1610 case TargetLowering::Expand: {
1611 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1612 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1613 " not tell us which reg is the stack pointer!");
1614 SDOperand Chain = Tmp1.getOperand(0);
1616 // Chain the dynamic stack allocation so that it doesn't modify the stack
1617 // pointer when other instructions are using the stack.
1618 Chain = DAG.getCALLSEQ_START(Chain,
1619 DAG.getConstant(0, TLI.getPointerTy()));
1621 SDOperand Size = Tmp2.getOperand(1);
1622 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1623 Chain = SP.getValue(1);
1624 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1625 unsigned StackAlign =
1626 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1627 if (Align > StackAlign)
1628 SP = DAG.getNode(ISD::AND, VT, SP,
1629 DAG.getConstant(-(uint64_t)Align, VT));
1630 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1631 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1634 DAG.getCALLSEQ_END(Chain,
1635 DAG.getConstant(0, TLI.getPointerTy()),
1636 DAG.getConstant(0, TLI.getPointerTy()),
1639 Tmp1 = LegalizeOp(Tmp1);
1640 Tmp2 = LegalizeOp(Tmp2);
1643 case TargetLowering::Custom:
1644 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1646 Tmp1 = LegalizeOp(Tmp3);
1647 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1650 case TargetLowering::Legal:
1653 // Since this op produce two values, make sure to remember that we
1654 // legalized both of them.
1655 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1656 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1657 return Op.ResNo ? Tmp2 : Tmp1;
1659 case ISD::INLINEASM: {
1660 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1661 bool Changed = false;
1662 // Legalize all of the operands of the inline asm, in case they are nodes
1663 // that need to be expanded or something. Note we skip the asm string and
1664 // all of the TargetConstant flags.
1665 SDOperand Op = LegalizeOp(Ops[0]);
1666 Changed = Op != Ops[0];
1669 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1670 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1671 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1672 for (++i; NumVals; ++i, --NumVals) {
1673 SDOperand Op = LegalizeOp(Ops[i]);
1682 Op = LegalizeOp(Ops.back());
1683 Changed |= Op != Ops.back();
1688 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1690 // INLINE asm returns a chain and flag, make sure to add both to the map.
1691 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1692 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1693 return Result.getValue(Op.ResNo);
1696 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1697 // Ensure that libcalls are emitted before a branch.
1698 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1699 Tmp1 = LegalizeOp(Tmp1);
1700 LastCALLSEQ_END = DAG.getEntryNode();
1702 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1705 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1706 // Ensure that libcalls are emitted before a branch.
1707 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1708 Tmp1 = LegalizeOp(Tmp1);
1709 LastCALLSEQ_END = DAG.getEntryNode();
1711 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1712 default: assert(0 && "Indirect target must be legal type (pointer)!");
1714 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1717 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1720 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1721 // Ensure that libcalls are emitted before a branch.
1722 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1723 Tmp1 = LegalizeOp(Tmp1);
1724 LastCALLSEQ_END = DAG.getEntryNode();
1726 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1727 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1729 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1730 default: assert(0 && "This action is not supported yet!");
1731 case TargetLowering::Legal: break;
1732 case TargetLowering::Custom:
1733 Tmp1 = TLI.LowerOperation(Result, DAG);
1734 if (Tmp1.Val) Result = Tmp1;
1736 case TargetLowering::Expand: {
1737 SDOperand Chain = Result.getOperand(0);
1738 SDOperand Table = Result.getOperand(1);
1739 SDOperand Index = Result.getOperand(2);
1741 MVT::ValueType PTy = TLI.getPointerTy();
1742 MachineFunction &MF = DAG.getMachineFunction();
1743 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1744 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1745 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1748 switch (EntrySize) {
1749 default: assert(0 && "Size of jump table not supported yet."); break;
1750 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1751 PseudoSourceValue::getJumpTable(), 0); break;
1752 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1753 PseudoSourceValue::getJumpTable(), 0); break;
1757 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1758 // For PIC, the sequence is:
1759 // BRIND(load(Jumptable + index) + RelocBase)
1760 // RelocBase can be JumpTable, GOT or some sort of global base.
1761 if (PTy != MVT::i32)
1762 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1763 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1764 TLI.getPICJumpTableRelocBase(Table, DAG));
1766 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1771 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1772 // Ensure that libcalls are emitted before a return.
1773 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1774 Tmp1 = LegalizeOp(Tmp1);
1775 LastCALLSEQ_END = DAG.getEntryNode();
1777 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1778 case Expand: assert(0 && "It's impossible to expand bools");
1780 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1783 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1785 // The top bits of the promoted condition are not necessarily zero, ensure
1786 // that the value is properly zero extended.
1787 unsigned BitWidth = Tmp2.getValueSizeInBits();
1788 if (!DAG.MaskedValueIsZero(Tmp2,
1789 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1790 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1795 // Basic block destination (Op#2) is always legal.
1796 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1798 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1799 default: assert(0 && "This action is not supported yet!");
1800 case TargetLowering::Legal: break;
1801 case TargetLowering::Custom:
1802 Tmp1 = TLI.LowerOperation(Result, DAG);
1803 if (Tmp1.Val) Result = Tmp1;
1805 case TargetLowering::Expand:
1806 // Expand brcond's setcc into its constituent parts and create a BR_CC
1808 if (Tmp2.getOpcode() == ISD::SETCC) {
1809 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1810 Tmp2.getOperand(0), Tmp2.getOperand(1),
1811 Node->getOperand(2));
1813 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1814 DAG.getCondCode(ISD::SETNE), Tmp2,
1815 DAG.getConstant(0, Tmp2.getValueType()),
1816 Node->getOperand(2));
1822 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1823 // Ensure that libcalls are emitted before a branch.
1824 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1825 Tmp1 = LegalizeOp(Tmp1);
1826 Tmp2 = Node->getOperand(2); // LHS
1827 Tmp3 = Node->getOperand(3); // RHS
1828 Tmp4 = Node->getOperand(1); // CC
1830 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1831 LastCALLSEQ_END = DAG.getEntryNode();
1833 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1834 // the LHS is a legal SETCC itself. In this case, we need to compare
1835 // the result against zero to select between true and false values.
1836 if (Tmp3.Val == 0) {
1837 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1838 Tmp4 = DAG.getCondCode(ISD::SETNE);
1841 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1842 Node->getOperand(4));
1844 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1845 default: assert(0 && "Unexpected action for BR_CC!");
1846 case TargetLowering::Legal: break;
1847 case TargetLowering::Custom:
1848 Tmp4 = TLI.LowerOperation(Result, DAG);
1849 if (Tmp4.Val) Result = Tmp4;
1854 LoadSDNode *LD = cast<LoadSDNode>(Node);
1855 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1856 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1858 ISD::LoadExtType ExtType = LD->getExtensionType();
1859 if (ExtType == ISD::NON_EXTLOAD) {
1860 MVT::ValueType VT = Node->getValueType(0);
1861 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1862 Tmp3 = Result.getValue(0);
1863 Tmp4 = Result.getValue(1);
1865 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1866 default: assert(0 && "This action is not supported yet!");
1867 case TargetLowering::Legal:
1868 // If this is an unaligned load and the target doesn't support it,
1870 if (!TLI.allowsUnalignedMemoryAccesses()) {
1871 unsigned ABIAlignment = TLI.getTargetData()->
1872 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
1873 if (LD->getAlignment() < ABIAlignment){
1874 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1876 Tmp3 = Result.getOperand(0);
1877 Tmp4 = Result.getOperand(1);
1878 Tmp3 = LegalizeOp(Tmp3);
1879 Tmp4 = LegalizeOp(Tmp4);
1883 case TargetLowering::Custom:
1884 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1886 Tmp3 = LegalizeOp(Tmp1);
1887 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1890 case TargetLowering::Promote: {
1891 // Only promote a load of vector type to another.
1892 assert(MVT::isVector(VT) && "Cannot promote this load!");
1893 // Change base type to a different vector type.
1894 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1896 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1897 LD->getSrcValueOffset(),
1898 LD->isVolatile(), LD->getAlignment());
1899 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1900 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1904 // Since loads produce two values, make sure to remember that we
1905 // legalized both of them.
1906 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1907 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1908 return Op.ResNo ? Tmp4 : Tmp3;
1910 MVT::ValueType SrcVT = LD->getMemoryVT();
1911 unsigned SrcWidth = MVT::getSizeInBits(SrcVT);
1912 int SVOffset = LD->getSrcValueOffset();
1913 unsigned Alignment = LD->getAlignment();
1914 bool isVolatile = LD->isVolatile();
1916 if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) &&
1917 // Some targets pretend to have an i1 loading operation, and actually
1918 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1919 // bits are guaranteed to be zero; it helps the optimizers understand
1920 // that these bits are zero. It is also useful for EXTLOAD, since it
1921 // tells the optimizers that those bits are undefined. It would be
1922 // nice to have an effective generic way of getting these benefits...
1923 // Until such a way is found, don't insist on promoting i1 here.
1924 (SrcVT != MVT::i1 ||
1925 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1926 // Promote to a byte-sized load if not loading an integral number of
1927 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1928 unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT);
1929 MVT::ValueType NVT = MVT::getIntegerType(NewWidth);
1932 // The extra bits are guaranteed to be zero, since we stored them that
1933 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1935 ISD::LoadExtType NewExtType =
1936 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1938 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
1939 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1940 NVT, isVolatile, Alignment);
1942 Ch = Result.getValue(1); // The chain.
1944 if (ExtType == ISD::SEXTLOAD)
1945 // Having the top bits zero doesn't help when sign extending.
1946 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1947 Result, DAG.getValueType(SrcVT));
1948 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1949 // All the top bits are guaranteed to be zero - inform the optimizers.
1950 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
1951 DAG.getValueType(SrcVT));
1953 Tmp1 = LegalizeOp(Result);
1954 Tmp2 = LegalizeOp(Ch);
1955 } else if (SrcWidth & (SrcWidth - 1)) {
1956 // If not loading a power-of-2 number of bits, expand as two loads.
1957 assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) &&
1958 "Unsupported extload!");
1959 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1960 assert(RoundWidth < SrcWidth);
1961 unsigned ExtraWidth = SrcWidth - RoundWidth;
1962 assert(ExtraWidth < RoundWidth);
1963 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1964 "Load size not an integral number of bytes!");
1965 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
1966 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
1967 SDOperand Lo, Hi, Ch;
1968 unsigned IncrementSize;
1970 if (TLI.isLittleEndian()) {
1971 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1972 // Load the bottom RoundWidth bits.
1973 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
1974 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1977 // Load the remaining ExtraWidth bits.
1978 IncrementSize = RoundWidth / 8;
1979 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1980 DAG.getIntPtrConstant(IncrementSize));
1981 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1982 LD->getSrcValue(), SVOffset + IncrementSize,
1983 ExtraVT, isVolatile,
1984 MinAlign(Alignment, IncrementSize));
1986 // Build a factor node to remember that this load is independent of the
1988 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1991 // Move the top bits to the right place.
1992 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
1993 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1995 // Join the hi and lo parts.
1996 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
1998 // Big endian - avoid unaligned loads.
1999 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2000 // Load the top RoundWidth bits.
2001 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2002 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2005 // Load the remaining ExtraWidth bits.
2006 IncrementSize = RoundWidth / 8;
2007 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2008 DAG.getIntPtrConstant(IncrementSize));
2009 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2010 LD->getSrcValue(), SVOffset + IncrementSize,
2011 ExtraVT, isVolatile,
2012 MinAlign(Alignment, IncrementSize));
2014 // Build a factor node to remember that this load is independent of the
2016 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2019 // Move the top bits to the right place.
2020 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2021 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2023 // Join the hi and lo parts.
2024 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2027 Tmp1 = LegalizeOp(Result);
2028 Tmp2 = LegalizeOp(Ch);
2030 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2031 default: assert(0 && "This action is not supported yet!");
2032 case TargetLowering::Custom:
2035 case TargetLowering::Legal:
2036 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2037 Tmp1 = Result.getValue(0);
2038 Tmp2 = Result.getValue(1);
2041 Tmp3 = TLI.LowerOperation(Result, DAG);
2043 Tmp1 = LegalizeOp(Tmp3);
2044 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2047 // If this is an unaligned load and the target doesn't support it,
2049 if (!TLI.allowsUnalignedMemoryAccesses()) {
2050 unsigned ABIAlignment = TLI.getTargetData()->
2051 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
2052 if (LD->getAlignment() < ABIAlignment){
2053 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
2055 Tmp1 = Result.getOperand(0);
2056 Tmp2 = Result.getOperand(1);
2057 Tmp1 = LegalizeOp(Tmp1);
2058 Tmp2 = LegalizeOp(Tmp2);
2063 case TargetLowering::Expand:
2064 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2065 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2066 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2067 LD->getSrcValueOffset(),
2068 LD->isVolatile(), LD->getAlignment());
2069 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2070 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2071 Tmp2 = LegalizeOp(Load.getValue(1));
2074 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2075 // Turn the unsupported load into an EXTLOAD followed by an explicit
2076 // zero/sign extend inreg.
2077 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2078 Tmp1, Tmp2, LD->getSrcValue(),
2079 LD->getSrcValueOffset(), SrcVT,
2080 LD->isVolatile(), LD->getAlignment());
2082 if (ExtType == ISD::SEXTLOAD)
2083 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2084 Result, DAG.getValueType(SrcVT));
2086 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2087 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2088 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2093 // Since loads produce two values, make sure to remember that we legalized
2095 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2096 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2097 return Op.ResNo ? Tmp2 : Tmp1;
2100 case ISD::EXTRACT_ELEMENT: {
2101 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
2102 switch (getTypeAction(OpTy)) {
2103 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2105 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2107 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2108 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
2109 TLI.getShiftAmountTy()));
2110 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2113 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2114 Node->getOperand(0));
2118 // Get both the low and high parts.
2119 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2120 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2121 Result = Tmp2; // 1 -> Hi
2123 Result = Tmp1; // 0 -> Lo
2129 case ISD::CopyToReg:
2130 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2132 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2133 "Register type must be legal!");
2134 // Legalize the incoming value (must be a legal type).
2135 Tmp2 = LegalizeOp(Node->getOperand(2));
2136 if (Node->getNumValues() == 1) {
2137 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2139 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2140 if (Node->getNumOperands() == 4) {
2141 Tmp3 = LegalizeOp(Node->getOperand(3));
2142 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2145 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2148 // Since this produces two values, make sure to remember that we legalized
2150 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2151 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2157 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2159 // Ensure that libcalls are emitted before a return.
2160 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2161 Tmp1 = LegalizeOp(Tmp1);
2162 LastCALLSEQ_END = DAG.getEntryNode();
2164 switch (Node->getNumOperands()) {
2166 Tmp2 = Node->getOperand(1);
2167 Tmp3 = Node->getOperand(2); // Signness
2168 switch (getTypeAction(Tmp2.getValueType())) {
2170 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2173 if (!MVT::isVector(Tmp2.getValueType())) {
2175 ExpandOp(Tmp2, Lo, Hi);
2177 // Big endian systems want the hi reg first.
2178 if (TLI.isBigEndian())
2182 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2184 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2185 Result = LegalizeOp(Result);
2187 SDNode *InVal = Tmp2.Val;
2188 int InIx = Tmp2.ResNo;
2189 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
2190 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
2192 // Figure out if there is a simple type corresponding to this Vector
2193 // type. If so, convert to the vector type.
2194 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2195 if (TLI.isTypeLegal(TVT)) {
2196 // Turn this into a return of the vector type.
2197 Tmp2 = LegalizeOp(Tmp2);
2198 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2199 } else if (NumElems == 1) {
2200 // Turn this into a return of the scalar type.
2201 Tmp2 = ScalarizeVectorOp(Tmp2);
2202 Tmp2 = LegalizeOp(Tmp2);
2203 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2205 // FIXME: Returns of gcc generic vectors smaller than a legal type
2206 // should be returned in integer registers!
2208 // The scalarized value type may not be legal, e.g. it might require
2209 // promotion or expansion. Relegalize the return.
2210 Result = LegalizeOp(Result);
2212 // FIXME: Returns of gcc generic vectors larger than a legal vector
2213 // type should be returned by reference!
2215 SplitVectorOp(Tmp2, Lo, Hi);
2216 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2217 Result = LegalizeOp(Result);
2222 Tmp2 = PromoteOp(Node->getOperand(1));
2223 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2224 Result = LegalizeOp(Result);
2229 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2231 default: { // ret <values>
2232 SmallVector<SDOperand, 8> NewValues;
2233 NewValues.push_back(Tmp1);
2234 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2235 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2237 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2238 NewValues.push_back(Node->getOperand(i+1));
2242 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
2243 "FIXME: TODO: implement returning non-legal vector types!");
2244 ExpandOp(Node->getOperand(i), Lo, Hi);
2245 NewValues.push_back(Lo);
2246 NewValues.push_back(Node->getOperand(i+1));
2248 NewValues.push_back(Hi);
2249 NewValues.push_back(Node->getOperand(i+1));
2254 assert(0 && "Can't promote multiple return value yet!");
2257 if (NewValues.size() == Node->getNumOperands())
2258 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2260 Result = DAG.getNode(ISD::RET, MVT::Other,
2261 &NewValues[0], NewValues.size());
2266 if (Result.getOpcode() == ISD::RET) {
2267 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2268 default: assert(0 && "This action is not supported yet!");
2269 case TargetLowering::Legal: break;
2270 case TargetLowering::Custom:
2271 Tmp1 = TLI.LowerOperation(Result, DAG);
2272 if (Tmp1.Val) Result = Tmp1;
2278 StoreSDNode *ST = cast<StoreSDNode>(Node);
2279 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2280 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2281 int SVOffset = ST->getSrcValueOffset();
2282 unsigned Alignment = ST->getAlignment();
2283 bool isVolatile = ST->isVolatile();
2285 if (!ST->isTruncatingStore()) {
2286 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2287 // FIXME: We shouldn't do this for TargetConstantFP's.
2288 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2289 // to phase ordering between legalized code and the dag combiner. This
2290 // probably means that we need to integrate dag combiner and legalizer
2292 // We generally can't do this one for long doubles.
2293 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2294 if (CFP->getValueType(0) == MVT::f32 &&
2295 getTypeAction(MVT::i32) == Legal) {
2296 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF().
2297 convertToAPInt().getZExtValue(),
2299 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2300 SVOffset, isVolatile, Alignment);
2302 } else if (CFP->getValueType(0) == MVT::f64) {
2303 // If this target supports 64-bit registers, do a single 64-bit store.
2304 if (getTypeAction(MVT::i64) == Legal) {
2305 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2306 getZExtValue(), MVT::i64);
2307 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2308 SVOffset, isVolatile, Alignment);
2310 } else if (getTypeAction(MVT::i32) == Legal) {
2311 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2312 // stores. If the target supports neither 32- nor 64-bits, this
2313 // xform is certainly not worth it.
2314 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue();
2315 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32);
2316 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32);
2317 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2319 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2320 SVOffset, isVolatile, Alignment);
2321 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2322 DAG.getIntPtrConstant(4));
2323 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2324 isVolatile, MinAlign(Alignment, 4U));
2326 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2332 switch (getTypeAction(ST->getMemoryVT())) {
2334 Tmp3 = LegalizeOp(ST->getValue());
2335 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2338 MVT::ValueType VT = Tmp3.getValueType();
2339 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2340 default: assert(0 && "This action is not supported yet!");
2341 case TargetLowering::Legal:
2342 // If this is an unaligned store and the target doesn't support it,
2344 if (!TLI.allowsUnalignedMemoryAccesses()) {
2345 unsigned ABIAlignment = TLI.getTargetData()->
2346 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2347 if (ST->getAlignment() < ABIAlignment)
2348 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2352 case TargetLowering::Custom:
2353 Tmp1 = TLI.LowerOperation(Result, DAG);
2354 if (Tmp1.Val) Result = Tmp1;
2356 case TargetLowering::Promote:
2357 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2358 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2359 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2360 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2361 ST->getSrcValue(), SVOffset, isVolatile,
2368 // Truncate the value and store the result.
2369 Tmp3 = PromoteOp(ST->getValue());
2370 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2371 SVOffset, ST->getMemoryVT(),
2372 isVolatile, Alignment);
2376 unsigned IncrementSize = 0;
2379 // If this is a vector type, then we have to calculate the increment as
2380 // the product of the element size in bytes, and the number of elements
2381 // in the high half of the vector.
2382 if (MVT::isVector(ST->getValue().getValueType())) {
2383 SDNode *InVal = ST->getValue().Val;
2384 int InIx = ST->getValue().ResNo;
2385 MVT::ValueType InVT = InVal->getValueType(InIx);
2386 unsigned NumElems = MVT::getVectorNumElements(InVT);
2387 MVT::ValueType EVT = MVT::getVectorElementType(InVT);
2389 // Figure out if there is a simple type corresponding to this Vector
2390 // type. If so, convert to the vector type.
2391 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2392 if (TLI.isTypeLegal(TVT)) {
2393 // Turn this into a normal store of the vector type.
2394 Tmp3 = LegalizeOp(ST->getValue());
2395 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2396 SVOffset, isVolatile, Alignment);
2397 Result = LegalizeOp(Result);
2399 } else if (NumElems == 1) {
2400 // Turn this into a normal store of the scalar type.
2401 Tmp3 = ScalarizeVectorOp(ST->getValue());
2402 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2403 SVOffset, isVolatile, Alignment);
2404 // The scalarized value type may not be legal, e.g. it might require
2405 // promotion or expansion. Relegalize the scalar store.
2406 Result = LegalizeOp(Result);
2409 SplitVectorOp(ST->getValue(), Lo, Hi);
2410 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
2411 MVT::getSizeInBits(EVT)/8;
2414 ExpandOp(ST->getValue(), Lo, Hi);
2415 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2417 if (TLI.isBigEndian())
2421 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2422 SVOffset, isVolatile, Alignment);
2424 if (Hi.Val == NULL) {
2425 // Must be int <-> float one-to-one expansion.
2430 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2431 DAG.getIntPtrConstant(IncrementSize));
2432 assert(isTypeLegal(Tmp2.getValueType()) &&
2433 "Pointers must be legal!");
2434 SVOffset += IncrementSize;
2435 Alignment = MinAlign(Alignment, IncrementSize);
2436 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2437 SVOffset, isVolatile, Alignment);
2438 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2442 switch (getTypeAction(ST->getValue().getValueType())) {
2444 Tmp3 = LegalizeOp(ST->getValue());
2447 // We can promote the value, the truncstore will still take care of it.
2448 Tmp3 = PromoteOp(ST->getValue());
2451 // Just store the low part. This may become a non-trunc store, so make
2452 // sure to use getTruncStore, not UpdateNodeOperands below.
2453 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2454 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2455 SVOffset, MVT::i8, isVolatile, Alignment);
2458 MVT::ValueType StVT = ST->getMemoryVT();
2459 unsigned StWidth = MVT::getSizeInBits(StVT);
2461 if (StWidth != MVT::getStoreSizeInBits(StVT)) {
2462 // Promote to a byte-sized store with upper bits zero if not
2463 // storing an integral number of bytes. For example, promote
2464 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2465 MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT));
2466 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2467 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2468 SVOffset, NVT, isVolatile, Alignment);
2469 } else if (StWidth & (StWidth - 1)) {
2470 // If not storing a power-of-2 number of bits, expand as two stores.
2471 assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) &&
2472 "Unsupported truncstore!");
2473 unsigned RoundWidth = 1 << Log2_32(StWidth);
2474 assert(RoundWidth < StWidth);
2475 unsigned ExtraWidth = StWidth - RoundWidth;
2476 assert(ExtraWidth < RoundWidth);
2477 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2478 "Store size not an integral number of bytes!");
2479 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
2480 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
2482 unsigned IncrementSize;
2484 if (TLI.isLittleEndian()) {
2485 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2486 // Store the bottom RoundWidth bits.
2487 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2489 isVolatile, Alignment);
2491 // Store the remaining ExtraWidth bits.
2492 IncrementSize = RoundWidth / 8;
2493 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2494 DAG.getIntPtrConstant(IncrementSize));
2495 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2496 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2497 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2498 SVOffset + IncrementSize, ExtraVT, isVolatile,
2499 MinAlign(Alignment, IncrementSize));
2501 // Big endian - avoid unaligned stores.
2502 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2503 // Store the top RoundWidth bits.
2504 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2505 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2506 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2507 RoundVT, isVolatile, Alignment);
2509 // Store the remaining ExtraWidth bits.
2510 IncrementSize = RoundWidth / 8;
2511 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2512 DAG.getIntPtrConstant(IncrementSize));
2513 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2514 SVOffset + IncrementSize, ExtraVT, isVolatile,
2515 MinAlign(Alignment, IncrementSize));
2518 // The order of the stores doesn't matter.
2519 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2521 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2522 Tmp2 != ST->getBasePtr())
2523 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2526 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2527 default: assert(0 && "This action is not supported yet!");
2528 case TargetLowering::Legal:
2529 // If this is an unaligned store and the target doesn't support it,
2531 if (!TLI.allowsUnalignedMemoryAccesses()) {
2532 unsigned ABIAlignment = TLI.getTargetData()->
2533 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2534 if (ST->getAlignment() < ABIAlignment)
2535 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2539 case TargetLowering::Custom:
2540 Result = TLI.LowerOperation(Result, DAG);
2543 // TRUNCSTORE:i16 i32 -> STORE i16
2544 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2545 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2546 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2547 isVolatile, Alignment);
2555 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2556 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2558 case ISD::STACKSAVE:
2559 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2560 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2561 Tmp1 = Result.getValue(0);
2562 Tmp2 = Result.getValue(1);
2564 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2565 default: assert(0 && "This action is not supported yet!");
2566 case TargetLowering::Legal: break;
2567 case TargetLowering::Custom:
2568 Tmp3 = TLI.LowerOperation(Result, DAG);
2570 Tmp1 = LegalizeOp(Tmp3);
2571 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2574 case TargetLowering::Expand:
2575 // Expand to CopyFromReg if the target set
2576 // StackPointerRegisterToSaveRestore.
2577 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2578 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2579 Node->getValueType(0));
2580 Tmp2 = Tmp1.getValue(1);
2582 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2583 Tmp2 = Node->getOperand(0);
2588 // Since stacksave produce two values, make sure to remember that we
2589 // legalized both of them.
2590 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2591 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2592 return Op.ResNo ? Tmp2 : Tmp1;
2594 case ISD::STACKRESTORE:
2595 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2596 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2597 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2599 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2600 default: assert(0 && "This action is not supported yet!");
2601 case TargetLowering::Legal: break;
2602 case TargetLowering::Custom:
2603 Tmp1 = TLI.LowerOperation(Result, DAG);
2604 if (Tmp1.Val) Result = Tmp1;
2606 case TargetLowering::Expand:
2607 // Expand to CopyToReg if the target set
2608 // StackPointerRegisterToSaveRestore.
2609 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2610 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2618 case ISD::READCYCLECOUNTER:
2619 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2620 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2621 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2622 Node->getValueType(0))) {
2623 default: assert(0 && "This action is not supported yet!");
2624 case TargetLowering::Legal:
2625 Tmp1 = Result.getValue(0);
2626 Tmp2 = Result.getValue(1);
2628 case TargetLowering::Custom:
2629 Result = TLI.LowerOperation(Result, DAG);
2630 Tmp1 = LegalizeOp(Result.getValue(0));
2631 Tmp2 = LegalizeOp(Result.getValue(1));
2635 // Since rdcc produce two values, make sure to remember that we legalized
2637 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2638 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2642 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2643 case Expand: assert(0 && "It's impossible to expand bools");
2645 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2648 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2649 // Make sure the condition is either zero or one.
2650 unsigned BitWidth = Tmp1.getValueSizeInBits();
2651 if (!DAG.MaskedValueIsZero(Tmp1,
2652 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2653 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2657 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2658 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2660 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2662 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2663 default: assert(0 && "This action is not supported yet!");
2664 case TargetLowering::Legal: break;
2665 case TargetLowering::Custom: {
2666 Tmp1 = TLI.LowerOperation(Result, DAG);
2667 if (Tmp1.Val) Result = Tmp1;
2670 case TargetLowering::Expand:
2671 if (Tmp1.getOpcode() == ISD::SETCC) {
2672 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2674 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2676 Result = DAG.getSelectCC(Tmp1,
2677 DAG.getConstant(0, Tmp1.getValueType()),
2678 Tmp2, Tmp3, ISD::SETNE);
2681 case TargetLowering::Promote: {
2682 MVT::ValueType NVT =
2683 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2684 unsigned ExtOp, TruncOp;
2685 if (MVT::isVector(Tmp2.getValueType())) {
2686 ExtOp = ISD::BIT_CONVERT;
2687 TruncOp = ISD::BIT_CONVERT;
2688 } else if (MVT::isInteger(Tmp2.getValueType())) {
2689 ExtOp = ISD::ANY_EXTEND;
2690 TruncOp = ISD::TRUNCATE;
2692 ExtOp = ISD::FP_EXTEND;
2693 TruncOp = ISD::FP_ROUND;
2695 // Promote each of the values to the new type.
2696 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2697 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2698 // Perform the larger operation, then round down.
2699 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2700 if (TruncOp != ISD::FP_ROUND)
2701 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2703 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2704 DAG.getIntPtrConstant(0));
2709 case ISD::SELECT_CC: {
2710 Tmp1 = Node->getOperand(0); // LHS
2711 Tmp2 = Node->getOperand(1); // RHS
2712 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2713 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2714 SDOperand CC = Node->getOperand(4);
2716 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2718 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2719 // the LHS is a legal SETCC itself. In this case, we need to compare
2720 // the result against zero to select between true and false values.
2721 if (Tmp2.Val == 0) {
2722 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2723 CC = DAG.getCondCode(ISD::SETNE);
2725 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2727 // Everything is legal, see if we should expand this op or something.
2728 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2729 default: assert(0 && "This action is not supported yet!");
2730 case TargetLowering::Legal: break;
2731 case TargetLowering::Custom:
2732 Tmp1 = TLI.LowerOperation(Result, DAG);
2733 if (Tmp1.Val) Result = Tmp1;
2739 Tmp1 = Node->getOperand(0);
2740 Tmp2 = Node->getOperand(1);
2741 Tmp3 = Node->getOperand(2);
2742 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2744 // If we had to Expand the SetCC operands into a SELECT node, then it may
2745 // not always be possible to return a true LHS & RHS. In this case, just
2746 // return the value we legalized, returned in the LHS
2747 if (Tmp2.Val == 0) {
2752 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2753 default: assert(0 && "Cannot handle this action for SETCC yet!");
2754 case TargetLowering::Custom:
2757 case TargetLowering::Legal:
2758 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2760 Tmp4 = TLI.LowerOperation(Result, DAG);
2761 if (Tmp4.Val) Result = Tmp4;
2764 case TargetLowering::Promote: {
2765 // First step, figure out the appropriate operation to use.
2766 // Allow SETCC to not be supported for all legal data types
2767 // Mostly this targets FP
2768 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2769 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2771 // Scan for the appropriate larger type to use.
2773 NewInTy = (MVT::ValueType)(NewInTy+1);
2775 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2776 "Fell off of the edge of the integer world");
2777 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2778 "Fell off of the edge of the floating point world");
2780 // If the target supports SETCC of this type, use it.
2781 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2784 if (MVT::isInteger(NewInTy))
2785 assert(0 && "Cannot promote Legal Integer SETCC yet");
2787 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2788 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2790 Tmp1 = LegalizeOp(Tmp1);
2791 Tmp2 = LegalizeOp(Tmp2);
2792 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2793 Result = LegalizeOp(Result);
2796 case TargetLowering::Expand:
2797 // Expand a setcc node into a select_cc of the same condition, lhs, and
2798 // rhs that selects between const 1 (true) and const 0 (false).
2799 MVT::ValueType VT = Node->getValueType(0);
2800 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2801 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2808 case ISD::MEMMOVE: {
2809 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2810 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2812 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2813 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2814 case Expand: assert(0 && "Cannot expand a byte!");
2816 Tmp3 = LegalizeOp(Node->getOperand(2));
2819 Tmp3 = PromoteOp(Node->getOperand(2));
2823 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2827 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2829 // Length is too big, just take the lo-part of the length.
2831 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2835 Tmp4 = LegalizeOp(Node->getOperand(3));
2838 Tmp4 = PromoteOp(Node->getOperand(3));
2843 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2844 case Expand: assert(0 && "Cannot expand this yet!");
2846 Tmp5 = LegalizeOp(Node->getOperand(4));
2849 Tmp5 = PromoteOp(Node->getOperand(4));
2854 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool
2855 case Expand: assert(0 && "Cannot expand this yet!");
2857 Tmp6 = LegalizeOp(Node->getOperand(5));
2860 Tmp6 = PromoteOp(Node->getOperand(5));
2864 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2865 default: assert(0 && "This action not implemented for this operation!");
2866 case TargetLowering::Custom:
2869 case TargetLowering::Legal: {
2870 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 };
2871 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
2873 Tmp1 = TLI.LowerOperation(Result, DAG);
2874 if (Tmp1.Val) Result = Tmp1;
2878 case TargetLowering::Expand: {
2879 // Otherwise, the target does not support this operation. Lower the
2880 // operation to an explicit libcall as appropriate.
2881 MVT::ValueType IntPtr = TLI.getPointerTy();
2882 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2883 TargetLowering::ArgListTy Args;
2884 TargetLowering::ArgListEntry Entry;
2886 const char *FnName = 0;
2887 if (Node->getOpcode() == ISD::MEMSET) {
2888 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2889 Args.push_back(Entry);
2890 // Extend the (previously legalized) ubyte argument to be an int value
2892 if (Tmp3.getValueType() > MVT::i32)
2893 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2895 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2896 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2897 Args.push_back(Entry);
2898 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2899 Args.push_back(Entry);
2902 } else if (Node->getOpcode() == ISD::MEMCPY ||
2903 Node->getOpcode() == ISD::MEMMOVE) {
2904 Entry.Ty = IntPtrTy;
2905 Entry.Node = Tmp2; Args.push_back(Entry);
2906 Entry.Node = Tmp3; Args.push_back(Entry);
2907 Entry.Node = Tmp4; Args.push_back(Entry);
2908 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2910 assert(0 && "Unknown op!");
2913 std::pair<SDOperand,SDOperand> CallResult =
2914 TLI.LowerCallTo(Tmp1, Type::VoidTy,
2915 false, false, false, CallingConv::C, false,
2916 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2917 Result = CallResult.second;
2924 case ISD::SHL_PARTS:
2925 case ISD::SRA_PARTS:
2926 case ISD::SRL_PARTS: {
2927 SmallVector<SDOperand, 8> Ops;
2928 bool Changed = false;
2929 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2930 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2931 Changed |= Ops.back() != Node->getOperand(i);
2934 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2936 switch (TLI.getOperationAction(Node->getOpcode(),
2937 Node->getValueType(0))) {
2938 default: assert(0 && "This action is not supported yet!");
2939 case TargetLowering::Legal: break;
2940 case TargetLowering::Custom:
2941 Tmp1 = TLI.LowerOperation(Result, DAG);
2943 SDOperand Tmp2, RetVal(0, 0);
2944 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2945 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2946 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2950 assert(RetVal.Val && "Illegal result number");
2956 // Since these produce multiple values, make sure to remember that we
2957 // legalized all of them.
2958 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2959 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2960 return Result.getValue(Op.ResNo);
2982 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2983 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2984 case Expand: assert(0 && "Not possible");
2986 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2989 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2993 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2995 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2996 default: assert(0 && "BinOp legalize operation not supported");
2997 case TargetLowering::Legal: break;
2998 case TargetLowering::Custom:
2999 Tmp1 = TLI.LowerOperation(Result, DAG);
3000 if (Tmp1.Val) Result = Tmp1;
3002 case TargetLowering::Expand: {
3003 MVT::ValueType VT = Op.getValueType();
3005 // See if multiply or divide can be lowered using two-result operations.
3006 SDVTList VTs = DAG.getVTList(VT, VT);
3007 if (Node->getOpcode() == ISD::MUL) {
3008 // We just need the low half of the multiply; try both the signed
3009 // and unsigned forms. If the target supports both SMUL_LOHI and
3010 // UMUL_LOHI, form a preference by checking which forms of plain
3011 // MULH it supports.
3012 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
3013 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
3014 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
3015 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
3016 unsigned OpToUse = 0;
3017 if (HasSMUL_LOHI && !HasMULHS) {
3018 OpToUse = ISD::SMUL_LOHI;
3019 } else if (HasUMUL_LOHI && !HasMULHU) {
3020 OpToUse = ISD::UMUL_LOHI;
3021 } else if (HasSMUL_LOHI) {
3022 OpToUse = ISD::SMUL_LOHI;
3023 } else if (HasUMUL_LOHI) {
3024 OpToUse = ISD::UMUL_LOHI;
3027 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
3031 if (Node->getOpcode() == ISD::MULHS &&
3032 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3033 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3036 if (Node->getOpcode() == ISD::MULHU &&
3037 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3038 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3041 if (Node->getOpcode() == ISD::SDIV &&
3042 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3043 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3046 if (Node->getOpcode() == ISD::UDIV &&
3047 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3048 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3052 // Check to see if we have a libcall for this operator.
3053 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3054 bool isSigned = false;
3055 switch (Node->getOpcode()) {
3058 if (VT == MVT::i32) {
3059 LC = Node->getOpcode() == ISD::UDIV
3060 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3061 isSigned = Node->getOpcode() == ISD::SDIV;
3065 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3066 RTLIB::POW_PPCF128);
3070 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3072 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3076 assert(MVT::isVector(Node->getValueType(0)) &&
3077 "Cannot expand this binary operator!");
3078 // Expand the operation into a bunch of nasty scalar code.
3079 Result = LegalizeOp(UnrollVectorOp(Op));
3082 case TargetLowering::Promote: {
3083 switch (Node->getOpcode()) {
3084 default: assert(0 && "Do not know how to promote this BinOp!");
3088 MVT::ValueType OVT = Node->getValueType(0);
3089 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3090 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
3091 // Bit convert each of the values to the new type.
3092 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3093 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3094 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3095 // Bit convert the result back the original type.
3096 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3104 case ISD::SMUL_LOHI:
3105 case ISD::UMUL_LOHI:
3108 // These nodes will only be produced by target-specific lowering, so
3109 // they shouldn't be here if they aren't legal.
3110 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3111 "This must be legal!");
3113 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3114 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3115 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3118 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3119 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3120 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3121 case Expand: assert(0 && "Not possible");
3123 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3126 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3130 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3132 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3133 default: assert(0 && "Operation not supported");
3134 case TargetLowering::Custom:
3135 Tmp1 = TLI.LowerOperation(Result, DAG);
3136 if (Tmp1.Val) Result = Tmp1;
3138 case TargetLowering::Legal: break;
3139 case TargetLowering::Expand: {
3140 // If this target supports fabs/fneg natively and select is cheap,
3141 // do this efficiently.
3142 if (!TLI.isSelectExpensive() &&
3143 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3144 TargetLowering::Legal &&
3145 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3146 TargetLowering::Legal) {
3147 // Get the sign bit of the RHS.
3148 MVT::ValueType IVT =
3149 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3150 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3151 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
3152 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3153 // Get the absolute value of the result.
3154 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3155 // Select between the nabs and abs value based on the sign bit of
3157 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3158 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3161 Result = LegalizeOp(Result);
3165 // Otherwise, do bitwise ops!
3166 MVT::ValueType NVT =
3167 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3168 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3169 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3170 Result = LegalizeOp(Result);
3178 Tmp1 = LegalizeOp(Node->getOperand(0));
3179 Tmp2 = LegalizeOp(Node->getOperand(1));
3180 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3181 // Since this produces two values, make sure to remember that we legalized
3183 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3184 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3189 Tmp1 = LegalizeOp(Node->getOperand(0));
3190 Tmp2 = LegalizeOp(Node->getOperand(1));
3191 Tmp3 = LegalizeOp(Node->getOperand(2));
3192 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3193 // Since this produces two values, make sure to remember that we legalized
3195 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3196 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3199 case ISD::BUILD_PAIR: {
3200 MVT::ValueType PairTy = Node->getValueType(0);
3201 // TODO: handle the case where the Lo and Hi operands are not of legal type
3202 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3203 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3204 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3205 case TargetLowering::Promote:
3206 case TargetLowering::Custom:
3207 assert(0 && "Cannot promote/custom this yet!");
3208 case TargetLowering::Legal:
3209 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3210 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3212 case TargetLowering::Expand:
3213 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3214 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3215 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3216 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
3217 TLI.getShiftAmountTy()));
3218 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3227 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3228 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3230 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3231 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3232 case TargetLowering::Custom:
3235 case TargetLowering::Legal:
3236 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3238 Tmp1 = TLI.LowerOperation(Result, DAG);
3239 if (Tmp1.Val) Result = Tmp1;
3242 case TargetLowering::Expand: {
3243 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3244 bool isSigned = DivOpc == ISD::SDIV;
3245 MVT::ValueType VT = Node->getValueType(0);
3247 // See if remainder can be lowered using two-result operations.
3248 SDVTList VTs = DAG.getVTList(VT, VT);
3249 if (Node->getOpcode() == ISD::SREM &&
3250 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3251 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3254 if (Node->getOpcode() == ISD::UREM &&
3255 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3256 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3260 if (MVT::isInteger(VT)) {
3261 if (TLI.getOperationAction(DivOpc, VT) ==
3262 TargetLowering::Legal) {
3264 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3265 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3266 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3267 } else if (MVT::isVector(VT)) {
3268 Result = LegalizeOp(UnrollVectorOp(Op));
3270 assert(VT == MVT::i32 &&
3271 "Cannot expand this binary operator!");
3272 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3273 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3275 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3278 assert(MVT::isFloatingPoint(VT) &&
3279 "remainder op must have integer or floating-point type");
3280 if (MVT::isVector(VT)) {
3281 Result = LegalizeOp(UnrollVectorOp(Op));
3283 // Floating point mod -> fmod libcall.
3284 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3285 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3287 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3288 false/*sign irrelevant*/, Dummy);
3296 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3297 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3299 MVT::ValueType VT = Node->getValueType(0);
3300 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3301 default: assert(0 && "This action is not supported yet!");
3302 case TargetLowering::Custom:
3305 case TargetLowering::Legal:
3306 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3307 Result = Result.getValue(0);
3308 Tmp1 = Result.getValue(1);
3311 Tmp2 = TLI.LowerOperation(Result, DAG);
3313 Result = LegalizeOp(Tmp2);
3314 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3318 case TargetLowering::Expand: {
3319 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3320 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3321 // Increment the pointer, VAList, to the next vaarg
3322 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3323 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3324 TLI.getPointerTy()));
3325 // Store the incremented VAList to the legalized pointer
3326 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3327 // Load the actual argument out of the pointer VAList
3328 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3329 Tmp1 = LegalizeOp(Result.getValue(1));
3330 Result = LegalizeOp(Result);
3334 // Since VAARG produces two values, make sure to remember that we
3335 // legalized both of them.
3336 AddLegalizedOperand(SDOperand(Node, 0), Result);
3337 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3338 return Op.ResNo ? Tmp1 : Result;
3342 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3343 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3344 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3346 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3347 default: assert(0 && "This action is not supported yet!");
3348 case TargetLowering::Custom:
3351 case TargetLowering::Legal:
3352 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3353 Node->getOperand(3), Node->getOperand(4));
3355 Tmp1 = TLI.LowerOperation(Result, DAG);
3356 if (Tmp1.Val) Result = Tmp1;
3359 case TargetLowering::Expand:
3360 // This defaults to loading a pointer from the input and storing it to the
3361 // output, returning the chain.
3362 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3363 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3364 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VD, 0);
3365 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VS, 0);
3371 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3372 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3374 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3375 default: assert(0 && "This action is not supported yet!");
3376 case TargetLowering::Custom:
3379 case TargetLowering::Legal:
3380 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3382 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3383 if (Tmp1.Val) Result = Tmp1;
3386 case TargetLowering::Expand:
3387 Result = Tmp1; // Default to a no-op, return the chain
3393 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3394 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3396 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3398 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3399 default: assert(0 && "This action is not supported yet!");
3400 case TargetLowering::Legal: break;
3401 case TargetLowering::Custom:
3402 Tmp1 = TLI.LowerOperation(Result, DAG);
3403 if (Tmp1.Val) Result = Tmp1;
3410 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3411 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3412 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3413 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3415 assert(0 && "ROTL/ROTR legalize operation not supported");
3417 case TargetLowering::Legal:
3419 case TargetLowering::Custom:
3420 Tmp1 = TLI.LowerOperation(Result, DAG);
3421 if (Tmp1.Val) Result = Tmp1;
3423 case TargetLowering::Promote:
3424 assert(0 && "Do not know how to promote ROTL/ROTR");
3426 case TargetLowering::Expand:
3427 assert(0 && "Do not know how to expand ROTL/ROTR");
3433 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3434 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3435 case TargetLowering::Custom:
3436 assert(0 && "Cannot custom legalize this yet!");
3437 case TargetLowering::Legal:
3438 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3440 case TargetLowering::Promote: {
3441 MVT::ValueType OVT = Tmp1.getValueType();
3442 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3443 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
3445 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3446 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3447 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3448 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3451 case TargetLowering::Expand:
3452 Result = ExpandBSWAP(Tmp1);
3460 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3461 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3462 case TargetLowering::Custom:
3463 case TargetLowering::Legal:
3464 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3465 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3466 TargetLowering::Custom) {
3467 Tmp1 = TLI.LowerOperation(Result, DAG);
3473 case TargetLowering::Promote: {
3474 MVT::ValueType OVT = Tmp1.getValueType();
3475 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3477 // Zero extend the argument.
3478 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3479 // Perform the larger operation, then subtract if needed.
3480 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3481 switch (Node->getOpcode()) {
3486 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3487 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3488 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3490 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3491 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
3494 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3495 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3496 DAG.getConstant(MVT::getSizeInBits(NVT) -
3497 MVT::getSizeInBits(OVT), NVT));
3502 case TargetLowering::Expand:
3503 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3514 Tmp1 = LegalizeOp(Node->getOperand(0));
3515 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3516 case TargetLowering::Promote:
3517 case TargetLowering::Custom:
3520 case TargetLowering::Legal:
3521 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3523 Tmp1 = TLI.LowerOperation(Result, DAG);
3524 if (Tmp1.Val) Result = Tmp1;
3527 case TargetLowering::Expand:
3528 switch (Node->getOpcode()) {
3529 default: assert(0 && "Unreachable!");
3531 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3532 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3533 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3536 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3537 MVT::ValueType VT = Node->getValueType(0);
3538 Tmp2 = DAG.getConstantFP(0.0, VT);
3539 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
3540 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3541 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3547 MVT::ValueType VT = Node->getValueType(0);
3549 // Expand unsupported unary vector operators by unrolling them.
3550 if (MVT::isVector(VT)) {
3551 Result = LegalizeOp(UnrollVectorOp(Op));
3555 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3556 switch(Node->getOpcode()) {
3558 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3559 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3562 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3563 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3566 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3567 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3569 default: assert(0 && "Unreachable!");
3572 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3573 false/*sign irrelevant*/, Dummy);
3581 MVT::ValueType VT = Node->getValueType(0);
3583 // Expand unsupported unary vector operators by unrolling them.
3584 if (MVT::isVector(VT)) {
3585 Result = LegalizeOp(UnrollVectorOp(Op));
3589 // We always lower FPOWI into a libcall. No target support for it yet.
3590 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3591 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3593 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3594 false/*sign irrelevant*/, Dummy);
3597 case ISD::BIT_CONVERT:
3598 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3599 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3600 Node->getValueType(0));
3601 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3602 // The input has to be a vector type, we have to either scalarize it, pack
3603 // it, or convert it based on whether the input vector type is legal.
3604 SDNode *InVal = Node->getOperand(0).Val;
3605 int InIx = Node->getOperand(0).ResNo;
3606 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
3607 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
3609 // Figure out if there is a simple type corresponding to this Vector
3610 // type. If so, convert to the vector type.
3611 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3612 if (TLI.isTypeLegal(TVT)) {
3613 // Turn this into a bit convert of the vector input.
3614 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3615 LegalizeOp(Node->getOperand(0)));
3617 } else if (NumElems == 1) {
3618 // Turn this into a bit convert of the scalar input.
3619 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3620 ScalarizeVectorOp(Node->getOperand(0)));
3623 // FIXME: UNIMP! Store then reload
3624 assert(0 && "Cast from unsupported vector type not implemented yet!");
3627 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3628 Node->getOperand(0).getValueType())) {
3629 default: assert(0 && "Unknown operation action!");
3630 case TargetLowering::Expand:
3631 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3632 Node->getValueType(0));
3634 case TargetLowering::Legal:
3635 Tmp1 = LegalizeOp(Node->getOperand(0));
3636 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3642 // Conversion operators. The source and destination have different types.
3643 case ISD::SINT_TO_FP:
3644 case ISD::UINT_TO_FP: {
3645 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3646 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3648 switch (TLI.getOperationAction(Node->getOpcode(),
3649 Node->getOperand(0).getValueType())) {
3650 default: assert(0 && "Unknown operation action!");
3651 case TargetLowering::Custom:
3654 case TargetLowering::Legal:
3655 Tmp1 = LegalizeOp(Node->getOperand(0));
3656 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3658 Tmp1 = TLI.LowerOperation(Result, DAG);
3659 if (Tmp1.Val) Result = Tmp1;
3662 case TargetLowering::Expand:
3663 Result = ExpandLegalINT_TO_FP(isSigned,
3664 LegalizeOp(Node->getOperand(0)),
3665 Node->getValueType(0));
3667 case TargetLowering::Promote:
3668 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3669 Node->getValueType(0),
3675 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3676 Node->getValueType(0), Node->getOperand(0));
3679 Tmp1 = PromoteOp(Node->getOperand(0));
3681 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3682 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3684 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3685 Node->getOperand(0).getValueType());
3687 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3688 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3694 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3696 Tmp1 = LegalizeOp(Node->getOperand(0));
3697 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3700 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3702 // Since the result is legal, we should just be able to truncate the low
3703 // part of the source.
3704 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3707 Result = PromoteOp(Node->getOperand(0));
3708 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3713 case ISD::FP_TO_SINT:
3714 case ISD::FP_TO_UINT:
3715 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3717 Tmp1 = LegalizeOp(Node->getOperand(0));
3719 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3720 default: assert(0 && "Unknown operation action!");
3721 case TargetLowering::Custom:
3724 case TargetLowering::Legal:
3725 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3727 Tmp1 = TLI.LowerOperation(Result, DAG);
3728 if (Tmp1.Val) Result = Tmp1;
3731 case TargetLowering::Promote:
3732 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3733 Node->getOpcode() == ISD::FP_TO_SINT);
3735 case TargetLowering::Expand:
3736 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3737 SDOperand True, False;
3738 MVT::ValueType VT = Node->getOperand(0).getValueType();
3739 MVT::ValueType NVT = Node->getValueType(0);
3740 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1;
3741 const uint64_t zero[] = {0, 0};
3742 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3743 uint64_t x = 1ULL << ShiftAmt;
3744 (void)apf.convertFromZeroExtendedInteger
3745 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven);
3746 Tmp2 = DAG.getConstantFP(apf, VT);
3747 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3748 Node->getOperand(0), Tmp2, ISD::SETLT);
3749 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3750 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3751 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3753 False = DAG.getNode(ISD::XOR, NVT, False,
3754 DAG.getConstant(1ULL << ShiftAmt, NVT));
3755 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3758 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3764 MVT::ValueType VT = Op.getValueType();
3765 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3766 // Convert ppcf128 to i32
3767 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3768 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3769 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3770 Node->getOperand(0), DAG.getValueType(MVT::f64));
3771 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3772 DAG.getIntPtrConstant(1));
3773 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3775 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3776 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3777 Tmp2 = DAG.getConstantFP(apf, OVT);
3778 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3779 // FIXME: generated code sucks.
3780 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3781 DAG.getNode(ISD::ADD, MVT::i32,
3782 DAG.getNode(ISD::FP_TO_SINT, VT,
3783 DAG.getNode(ISD::FSUB, OVT,
3784 Node->getOperand(0), Tmp2)),
3785 DAG.getConstant(0x80000000, MVT::i32)),
3786 DAG.getNode(ISD::FP_TO_SINT, VT,
3787 Node->getOperand(0)),
3788 DAG.getCondCode(ISD::SETGE));
3792 // Convert f32 / f64 to i32 / i64.
3793 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3794 switch (Node->getOpcode()) {
3795 case ISD::FP_TO_SINT: {
3796 if (OVT == MVT::f32)
3797 LC = (VT == MVT::i32)
3798 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3799 else if (OVT == MVT::f64)
3800 LC = (VT == MVT::i32)
3801 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3802 else if (OVT == MVT::f80) {
3803 assert(VT == MVT::i64);
3804 LC = RTLIB::FPTOSINT_F80_I64;
3806 else if (OVT == MVT::ppcf128) {
3807 assert(VT == MVT::i64);
3808 LC = RTLIB::FPTOSINT_PPCF128_I64;
3812 case ISD::FP_TO_UINT: {
3813 if (OVT == MVT::f32)
3814 LC = (VT == MVT::i32)
3815 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3816 else if (OVT == MVT::f64)
3817 LC = (VT == MVT::i32)
3818 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3819 else if (OVT == MVT::f80) {
3820 LC = (VT == MVT::i32)
3821 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64;
3823 else if (OVT == MVT::ppcf128) {
3824 assert(VT == MVT::i64);
3825 LC = RTLIB::FPTOUINT_PPCF128_I64;
3829 default: assert(0 && "Unreachable!");
3832 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3833 false/*sign irrelevant*/, Dummy);
3837 Tmp1 = PromoteOp(Node->getOperand(0));
3838 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3839 Result = LegalizeOp(Result);
3844 case ISD::FP_EXTEND: {
3845 MVT::ValueType DstVT = Op.getValueType();
3846 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3847 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3848 // The only other way we can lower this is to turn it into a STORE,
3849 // LOAD pair, targetting a temporary location (a stack slot).
3850 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3853 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3854 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3856 Tmp1 = LegalizeOp(Node->getOperand(0));
3857 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3860 Tmp1 = PromoteOp(Node->getOperand(0));
3861 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3866 case ISD::FP_ROUND: {
3867 MVT::ValueType DstVT = Op.getValueType();
3868 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3869 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3870 if (SrcVT == MVT::ppcf128) {
3872 ExpandOp(Node->getOperand(0), Lo, Result);
3873 // Round it the rest of the way (e.g. to f32) if needed.
3874 if (DstVT!=MVT::f64)
3875 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3878 // The only other way we can lower this is to turn it into a STORE,
3879 // LOAD pair, targetting a temporary location (a stack slot).
3880 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3883 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3884 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3886 Tmp1 = LegalizeOp(Node->getOperand(0));
3887 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3890 Tmp1 = PromoteOp(Node->getOperand(0));
3891 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3892 Node->getOperand(1));
3897 case ISD::ANY_EXTEND:
3898 case ISD::ZERO_EXTEND:
3899 case ISD::SIGN_EXTEND:
3900 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3901 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3903 Tmp1 = LegalizeOp(Node->getOperand(0));
3904 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3905 TargetLowering::Custom) {
3906 Tmp2 = TLI.LowerOperation(Result, DAG);
3911 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3914 switch (Node->getOpcode()) {
3915 case ISD::ANY_EXTEND:
3916 Tmp1 = PromoteOp(Node->getOperand(0));
3917 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3919 case ISD::ZERO_EXTEND:
3920 Result = PromoteOp(Node->getOperand(0));
3921 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3922 Result = DAG.getZeroExtendInReg(Result,
3923 Node->getOperand(0).getValueType());
3925 case ISD::SIGN_EXTEND:
3926 Result = PromoteOp(Node->getOperand(0));
3927 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3928 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3930 DAG.getValueType(Node->getOperand(0).getValueType()));
3935 case ISD::FP_ROUND_INREG:
3936 case ISD::SIGN_EXTEND_INREG: {
3937 Tmp1 = LegalizeOp(Node->getOperand(0));
3938 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3940 // If this operation is not supported, convert it to a shl/shr or load/store
3942 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3943 default: assert(0 && "This action not supported for this op yet!");
3944 case TargetLowering::Legal:
3945 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3947 case TargetLowering::Expand:
3948 // If this is an integer extend and shifts are supported, do that.
3949 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3950 // NOTE: we could fall back on load/store here too for targets without
3951 // SAR. However, it is doubtful that any exist.
3952 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3953 MVT::getSizeInBits(ExtraVT);
3954 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3955 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3956 Node->getOperand(0), ShiftCst);
3957 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3959 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3960 // The only way we can lower this is to turn it into a TRUNCSTORE,
3961 // EXTLOAD pair, targetting a temporary location (a stack slot).
3963 // NOTE: there is a choice here between constantly creating new stack
3964 // slots and always reusing the same one. We currently always create
3965 // new ones, as reuse may inhibit scheduling.
3966 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3967 Node->getValueType(0));
3969 assert(0 && "Unknown op");
3975 case ISD::TRAMPOLINE: {
3977 for (unsigned i = 0; i != 6; ++i)
3978 Ops[i] = LegalizeOp(Node->getOperand(i));
3979 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3980 // The only option for this node is to custom lower it.
3981 Result = TLI.LowerOperation(Result, DAG);
3982 assert(Result.Val && "Should always custom lower!");
3984 // Since trampoline produces two values, make sure to remember that we
3985 // legalized both of them.
3986 Tmp1 = LegalizeOp(Result.getValue(1));
3987 Result = LegalizeOp(Result);
3988 AddLegalizedOperand(SDOperand(Node, 0), Result);
3989 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3990 return Op.ResNo ? Tmp1 : Result;
3992 case ISD::FLT_ROUNDS_: {
3993 MVT::ValueType VT = Node->getValueType(0);
3994 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3995 default: assert(0 && "This action not supported for this op yet!");
3996 case TargetLowering::Custom:
3997 Result = TLI.LowerOperation(Op, DAG);
3998 if (Result.Val) break;
4000 case TargetLowering::Legal:
4001 // If this operation is not supported, lower it to constant 1
4002 Result = DAG.getConstant(1, VT);
4007 MVT::ValueType VT = Node->getValueType(0);
4008 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4009 default: assert(0 && "This action not supported for this op yet!");
4010 case TargetLowering::Legal:
4011 Tmp1 = LegalizeOp(Node->getOperand(0));
4012 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4014 case TargetLowering::Custom:
4015 Result = TLI.LowerOperation(Op, DAG);
4016 if (Result.Val) break;
4018 case TargetLowering::Expand:
4019 // If this operation is not supported, lower it to 'abort()' call
4020 Tmp1 = LegalizeOp(Node->getOperand(0));
4021 TargetLowering::ArgListTy Args;
4022 std::pair<SDOperand,SDOperand> CallResult =
4023 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4024 false, false, false, CallingConv::C, false,
4025 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4027 Result = CallResult.second;
4034 assert(Result.getValueType() == Op.getValueType() &&
4035 "Bad legalization!");
4037 // Make sure that the generated code is itself legal.
4039 Result = LegalizeOp(Result);
4041 // Note that LegalizeOp may be reentered even from single-use nodes, which
4042 // means that we always must cache transformed nodes.
4043 AddLegalizedOperand(Op, Result);
4047 /// PromoteOp - Given an operation that produces a value in an invalid type,
4048 /// promote it to compute the value into a larger type. The produced value will
4049 /// have the correct bits for the low portion of the register, but no guarantee
4050 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4051 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
4052 MVT::ValueType VT = Op.getValueType();
4053 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4054 assert(getTypeAction(VT) == Promote &&
4055 "Caller should expand or legalize operands that are not promotable!");
4056 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
4057 "Cannot promote to smaller type!");
4059 SDOperand Tmp1, Tmp2, Tmp3;
4061 SDNode *Node = Op.Val;
4063 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
4064 if (I != PromotedNodes.end()) return I->second;
4066 switch (Node->getOpcode()) {
4067 case ISD::CopyFromReg:
4068 assert(0 && "CopyFromReg must be legal!");
4071 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4073 assert(0 && "Do not know how to promote this operator!");
4076 Result = DAG.getNode(ISD::UNDEF, NVT);
4080 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4082 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4083 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4085 case ISD::ConstantFP:
4086 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4087 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4091 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
4092 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
4093 Node->getOperand(1), Node->getOperand(2));
4097 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4099 Result = LegalizeOp(Node->getOperand(0));
4100 assert(Result.getValueType() >= NVT &&
4101 "This truncation doesn't make sense!");
4102 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
4103 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4106 // The truncation is not required, because we don't guarantee anything
4107 // about high bits anyway.
4108 Result = PromoteOp(Node->getOperand(0));
4111 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4112 // Truncate the low part of the expanded value to the result type
4113 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4116 case ISD::SIGN_EXTEND:
4117 case ISD::ZERO_EXTEND:
4118 case ISD::ANY_EXTEND:
4119 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4120 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4122 // Input is legal? Just do extend all the way to the larger type.
4123 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4126 // Promote the reg if it's smaller.
4127 Result = PromoteOp(Node->getOperand(0));
4128 // The high bits are not guaranteed to be anything. Insert an extend.
4129 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4130 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4131 DAG.getValueType(Node->getOperand(0).getValueType()));
4132 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4133 Result = DAG.getZeroExtendInReg(Result,
4134 Node->getOperand(0).getValueType());
4138 case ISD::BIT_CONVERT:
4139 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4140 Node->getValueType(0));
4141 Result = PromoteOp(Result);
4144 case ISD::FP_EXTEND:
4145 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4147 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4148 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4149 case Promote: assert(0 && "Unreachable with 2 FP types!");
4151 if (Node->getConstantOperandVal(1) == 0) {
4152 // Input is legal? Do an FP_ROUND_INREG.
4153 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4154 DAG.getValueType(VT));
4156 // Just remove the truncate, it isn't affecting the value.
4157 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4158 Node->getOperand(1));
4163 case ISD::SINT_TO_FP:
4164 case ISD::UINT_TO_FP:
4165 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4167 // No extra round required here.
4168 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4172 Result = PromoteOp(Node->getOperand(0));
4173 if (Node->getOpcode() == ISD::SINT_TO_FP)
4174 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4176 DAG.getValueType(Node->getOperand(0).getValueType()));
4178 Result = DAG.getZeroExtendInReg(Result,
4179 Node->getOperand(0).getValueType());
4180 // No extra round required here.
4181 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4184 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4185 Node->getOperand(0));
4186 // Round if we cannot tolerate excess precision.
4187 if (NoExcessFPPrecision)
4188 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4189 DAG.getValueType(VT));
4194 case ISD::SIGN_EXTEND_INREG:
4195 Result = PromoteOp(Node->getOperand(0));
4196 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4197 Node->getOperand(1));
4199 case ISD::FP_TO_SINT:
4200 case ISD::FP_TO_UINT:
4201 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4204 Tmp1 = Node->getOperand(0);
4207 // The input result is prerounded, so we don't have to do anything
4209 Tmp1 = PromoteOp(Node->getOperand(0));
4212 // If we're promoting a UINT to a larger size, check to see if the new node
4213 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4214 // we can use that instead. This allows us to generate better code for
4215 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4216 // legal, such as PowerPC.
4217 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4218 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4219 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4220 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4221 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4223 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4229 Tmp1 = PromoteOp(Node->getOperand(0));
4230 assert(Tmp1.getValueType() == NVT);
4231 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4232 // NOTE: we do not have to do any extra rounding here for
4233 // NoExcessFPPrecision, because we know the input will have the appropriate
4234 // precision, and these operations don't modify precision at all.
4240 Tmp1 = PromoteOp(Node->getOperand(0));
4241 assert(Tmp1.getValueType() == NVT);
4242 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4243 if (NoExcessFPPrecision)
4244 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4245 DAG.getValueType(VT));
4249 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4250 // directly as well, which may be better.
4251 Tmp1 = PromoteOp(Node->getOperand(0));
4252 assert(Tmp1.getValueType() == NVT);
4253 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4254 if (NoExcessFPPrecision)
4255 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4256 DAG.getValueType(VT));
4260 case ISD::ATOMIC_LCS: {
4261 Tmp2 = PromoteOp(Node->getOperand(2));
4262 Tmp3 = PromoteOp(Node->getOperand(3));
4263 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0),
4264 Node->getOperand(1), Tmp2, Tmp3,
4265 cast<AtomicSDNode>(Node)->getVT());
4266 // Remember that we legalized the chain.
4267 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4270 case ISD::ATOMIC_LAS:
4271 case ISD::ATOMIC_SWAP: {
4272 Tmp2 = PromoteOp(Node->getOperand(2));
4273 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0),
4274 Node->getOperand(1), Tmp2,
4275 cast<AtomicSDNode>(Node)->getVT());
4276 // Remember that we legalized the chain.
4277 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4287 // The input may have strange things in the top bits of the registers, but
4288 // these operations don't care. They may have weird bits going out, but
4289 // that too is okay if they are integer operations.
4290 Tmp1 = PromoteOp(Node->getOperand(0));
4291 Tmp2 = PromoteOp(Node->getOperand(1));
4292 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4293 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4298 Tmp1 = PromoteOp(Node->getOperand(0));
4299 Tmp2 = PromoteOp(Node->getOperand(1));
4300 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4301 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4303 // Floating point operations will give excess precision that we may not be
4304 // able to tolerate. If we DO allow excess precision, just leave it,
4305 // otherwise excise it.
4306 // FIXME: Why would we need to round FP ops more than integer ones?
4307 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4308 if (NoExcessFPPrecision)
4309 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4310 DAG.getValueType(VT));
4315 // These operators require that their input be sign extended.
4316 Tmp1 = PromoteOp(Node->getOperand(0));
4317 Tmp2 = PromoteOp(Node->getOperand(1));
4318 if (MVT::isInteger(NVT)) {
4319 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4320 DAG.getValueType(VT));
4321 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4322 DAG.getValueType(VT));
4324 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4326 // Perform FP_ROUND: this is probably overly pessimistic.
4327 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
4328 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4329 DAG.getValueType(VT));
4333 case ISD::FCOPYSIGN:
4334 // These operators require that their input be fp extended.
4335 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4336 case Expand: assert(0 && "not implemented");
4337 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4338 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4340 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4341 case Expand: assert(0 && "not implemented");
4342 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4343 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4345 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4347 // Perform FP_ROUND: this is probably overly pessimistic.
4348 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4349 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4350 DAG.getValueType(VT));
4355 // These operators require that their input be zero extended.
4356 Tmp1 = PromoteOp(Node->getOperand(0));
4357 Tmp2 = PromoteOp(Node->getOperand(1));
4358 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
4359 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4360 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4361 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4365 Tmp1 = PromoteOp(Node->getOperand(0));
4366 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4369 // The input value must be properly sign extended.
4370 Tmp1 = PromoteOp(Node->getOperand(0));
4371 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4372 DAG.getValueType(VT));
4373 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4376 // The input value must be properly zero extended.
4377 Tmp1 = PromoteOp(Node->getOperand(0));
4378 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4379 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4383 Tmp1 = Node->getOperand(0); // Get the chain.
4384 Tmp2 = Node->getOperand(1); // Get the pointer.
4385 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4386 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4387 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
4389 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4390 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4391 // Increment the pointer, VAList, to the next vaarg
4392 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4393 DAG.getConstant(MVT::getSizeInBits(VT)/8,
4394 TLI.getPointerTy()));
4395 // Store the incremented VAList to the legalized pointer
4396 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4397 // Load the actual argument out of the pointer VAList
4398 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4400 // Remember that we legalized the chain.
4401 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4405 LoadSDNode *LD = cast<LoadSDNode>(Node);
4406 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4407 ? ISD::EXTLOAD : LD->getExtensionType();
4408 Result = DAG.getExtLoad(ExtType, NVT,
4409 LD->getChain(), LD->getBasePtr(),
4410 LD->getSrcValue(), LD->getSrcValueOffset(),
4413 LD->getAlignment());
4414 // Remember that we legalized the chain.
4415 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4419 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4420 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4421 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
4423 case ISD::SELECT_CC:
4424 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4425 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4426 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4427 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4430 Tmp1 = Node->getOperand(0);
4431 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4432 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4433 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4434 DAG.getConstant(MVT::getSizeInBits(NVT) -
4435 MVT::getSizeInBits(VT),
4436 TLI.getShiftAmountTy()));
4441 // Zero extend the argument
4442 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4443 // Perform the larger operation, then subtract if needed.
4444 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4445 switch(Node->getOpcode()) {
4450 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4451 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
4452 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
4454 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4455 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
4458 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4459 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4460 DAG.getConstant(MVT::getSizeInBits(NVT) -
4461 MVT::getSizeInBits(VT), NVT));
4465 case ISD::EXTRACT_SUBVECTOR:
4466 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4468 case ISD::EXTRACT_VECTOR_ELT:
4469 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4473 assert(Result.Val && "Didn't set a result!");
4475 // Make sure the result is itself legal.
4476 Result = LegalizeOp(Result);
4478 // Remember that we promoted this!
4479 AddPromotedOperand(Op, Result);
4483 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4484 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4485 /// based on the vector type. The return type of this matches the element type
4486 /// of the vector, which may not be legal for the target.
4487 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4488 // We know that operand #0 is the Vec vector. If the index is a constant
4489 // or if the invec is a supported hardware type, we can use it. Otherwise,
4490 // lower to a store then an indexed load.
4491 SDOperand Vec = Op.getOperand(0);
4492 SDOperand Idx = Op.getOperand(1);
4494 MVT::ValueType TVT = Vec.getValueType();
4495 unsigned NumElems = MVT::getVectorNumElements(TVT);
4497 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4498 default: assert(0 && "This action is not supported yet!");
4499 case TargetLowering::Custom: {
4500 Vec = LegalizeOp(Vec);
4501 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4502 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4507 case TargetLowering::Legal:
4508 if (isTypeLegal(TVT)) {
4509 Vec = LegalizeOp(Vec);
4510 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4514 case TargetLowering::Expand:
4518 if (NumElems == 1) {
4519 // This must be an access of the only element. Return it.
4520 Op = ScalarizeVectorOp(Vec);
4521 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4522 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4523 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4525 SplitVectorOp(Vec, Lo, Hi);
4526 if (CIdx->getValue() < NumLoElts) {
4530 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4531 Idx.getValueType());
4534 // It's now an extract from the appropriate high or low part. Recurse.
4535 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4536 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4538 // Store the value to a temporary stack slot, then LOAD the scalar
4539 // element back out.
4540 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4541 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4543 // Add the offset to the index.
4544 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
4545 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4546 DAG.getConstant(EltSize, Idx.getValueType()));
4548 if (MVT::getSizeInBits(Idx.getValueType()) >
4549 MVT::getSizeInBits(TLI.getPointerTy()))
4550 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4552 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4554 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4556 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4561 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4562 /// we assume the operation can be split if it is not already legal.
4563 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4564 // We know that operand #0 is the Vec vector. For now we assume the index
4565 // is a constant and that the extracted result is a supported hardware type.
4566 SDOperand Vec = Op.getOperand(0);
4567 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4569 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
4571 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
4572 // This must be an access of the desired vector length. Return it.
4576 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4578 SplitVectorOp(Vec, Lo, Hi);
4579 if (CIdx->getValue() < NumElems/2) {
4583 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4586 // It's now an extract from the appropriate high or low part. Recurse.
4587 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4588 return ExpandEXTRACT_SUBVECTOR(Op);
4591 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4592 /// with condition CC on the current target. This usually involves legalizing
4593 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4594 /// there may be no choice but to create a new SetCC node to represent the
4595 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4596 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4597 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4600 SDOperand Tmp1, Tmp2, Tmp3, Result;
4602 switch (getTypeAction(LHS.getValueType())) {
4604 Tmp1 = LegalizeOp(LHS); // LHS
4605 Tmp2 = LegalizeOp(RHS); // RHS
4608 Tmp1 = PromoteOp(LHS); // LHS
4609 Tmp2 = PromoteOp(RHS); // RHS
4611 // If this is an FP compare, the operands have already been extended.
4612 if (MVT::isInteger(LHS.getValueType())) {
4613 MVT::ValueType VT = LHS.getValueType();
4614 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4616 // Otherwise, we have to insert explicit sign or zero extends. Note
4617 // that we could insert sign extends for ALL conditions, but zero extend
4618 // is cheaper on many machines (an AND instead of two shifts), so prefer
4620 switch (cast<CondCodeSDNode>(CC)->get()) {
4621 default: assert(0 && "Unknown integer comparison!");
4628 // ALL of these operations will work if we either sign or zero extend
4629 // the operands (including the unsigned comparisons!). Zero extend is
4630 // usually a simpler/cheaper operation, so prefer it.
4631 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4632 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4638 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4639 DAG.getValueType(VT));
4640 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4641 DAG.getValueType(VT));
4647 MVT::ValueType VT = LHS.getValueType();
4648 if (VT == MVT::f32 || VT == MVT::f64) {
4649 // Expand into one or more soft-fp libcall(s).
4650 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4651 switch (cast<CondCodeSDNode>(CC)->get()) {
4654 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4658 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4662 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4666 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4670 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4674 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4677 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4680 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4683 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4684 switch (cast<CondCodeSDNode>(CC)->get()) {
4686 // SETONE = SETOLT | SETOGT
4687 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4690 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4693 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4696 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4699 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4702 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4704 default: assert(0 && "Unsupported FP setcc!");
4709 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4710 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4711 false /*sign irrelevant*/, Dummy);
4712 Tmp2 = DAG.getConstant(0, MVT::i32);
4713 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4714 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4715 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4716 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4717 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4718 false /*sign irrelevant*/, Dummy);
4719 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4720 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4721 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4729 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4730 ExpandOp(LHS, LHSLo, LHSHi);
4731 ExpandOp(RHS, RHSLo, RHSHi);
4732 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4734 if (VT==MVT::ppcf128) {
4735 // FIXME: This generated code sucks. We want to generate
4736 // FCMP crN, hi1, hi2
4738 // FCMP crN, lo1, lo2
4739 // The following can be improved, but not that much.
4740 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4741 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
4742 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4743 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
4744 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
4745 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4746 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4755 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4756 if (RHSCST->isAllOnesValue()) {
4757 // Comparison to -1.
4758 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4763 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4764 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4765 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4766 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4769 // If this is a comparison of the sign bit, just look at the top part.
4771 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4772 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4773 CST->getValue() == 0) || // X < 0
4774 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4775 CST->isAllOnesValue())) { // X > -1
4781 // FIXME: This generated code sucks.
4782 ISD::CondCode LowCC;
4784 default: assert(0 && "Unknown integer setcc!");
4786 case ISD::SETULT: LowCC = ISD::SETULT; break;
4788 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4790 case ISD::SETULE: LowCC = ISD::SETULE; break;
4792 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4795 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4796 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4797 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4799 // NOTE: on targets without efficient SELECT of bools, we can always use
4800 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4801 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4802 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4803 false, DagCombineInfo);
4805 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4806 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4807 CCCode, false, DagCombineInfo);
4809 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC);
4811 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4812 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4813 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4814 (Tmp2C && Tmp2C->getValue() == 0 &&
4815 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4816 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4817 (Tmp2C && Tmp2C->getValue() == 1 &&
4818 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4819 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4820 // low part is known false, returns high part.
4821 // For LE / GE, if high part is known false, ignore the low part.
4822 // For LT / GT, if high part is known true, ignore the low part.
4826 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4827 ISD::SETEQ, false, DagCombineInfo);
4829 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4830 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4831 Result, Tmp1, Tmp2));
4842 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4843 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4844 /// a load from the stack slot to DestVT, extending it if needed.
4845 /// The resultant code need not be legal.
4846 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4847 MVT::ValueType SlotVT,
4848 MVT::ValueType DestVT) {
4849 // Create the stack frame object.
4850 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
4852 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4853 int SPFI = StackPtrFI->getIndex();
4855 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType());
4856 unsigned SlotSize = MVT::getSizeInBits(SlotVT);
4857 unsigned DestSize = MVT::getSizeInBits(DestVT);
4859 // Emit a store to the stack slot. Use a truncstore if the input value is
4860 // later than DestVT.
4862 if (SrcSize > SlotSize)
4863 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4864 PseudoSourceValue::getFixedStack(),
4867 assert(SrcSize == SlotSize && "Invalid store");
4868 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4869 PseudoSourceValue::getFixedStack(),
4873 // Result is a load from the stack slot.
4874 if (SlotSize == DestSize)
4875 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4877 assert(SlotSize < DestSize && "Unknown extension!");
4878 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT);
4881 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4882 // Create a vector sized/aligned stack slot, store the value to element #0,
4883 // then load the whole vector back out.
4884 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4886 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4887 int SPFI = StackPtrFI->getIndex();
4889 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4890 PseudoSourceValue::getFixedStack(), SPFI);
4891 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4892 PseudoSourceValue::getFixedStack(), SPFI);
4896 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4897 /// support the operation, but do support the resultant vector type.
4898 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4900 // If the only non-undef value is the low element, turn this into a
4901 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4902 unsigned NumElems = Node->getNumOperands();
4903 bool isOnlyLowElement = true;
4904 SDOperand SplatValue = Node->getOperand(0);
4905 std::map<SDOperand, std::vector<unsigned> > Values;
4906 Values[SplatValue].push_back(0);
4907 bool isConstant = true;
4908 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4909 SplatValue.getOpcode() != ISD::UNDEF)
4912 for (unsigned i = 1; i < NumElems; ++i) {
4913 SDOperand V = Node->getOperand(i);
4914 Values[V].push_back(i);
4915 if (V.getOpcode() != ISD::UNDEF)
4916 isOnlyLowElement = false;
4917 if (SplatValue != V)
4918 SplatValue = SDOperand(0,0);
4920 // If this isn't a constant element or an undef, we can't use a constant
4922 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4923 V.getOpcode() != ISD::UNDEF)
4927 if (isOnlyLowElement) {
4928 // If the low element is an undef too, then this whole things is an undef.
4929 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4930 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4931 // Otherwise, turn this into a scalar_to_vector node.
4932 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4933 Node->getOperand(0));
4936 // If all elements are constants, create a load from the constant pool.
4938 MVT::ValueType VT = Node->getValueType(0);
4940 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4941 std::vector<Constant*> CV;
4942 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4943 if (ConstantFPSDNode *V =
4944 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4945 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4946 } else if (ConstantSDNode *V =
4947 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4948 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4950 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4951 CV.push_back(UndefValue::get(OpNTy));
4954 Constant *CP = ConstantVector::get(CV);
4955 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4956 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4957 PseudoSourceValue::getConstantPool(), 0);
4960 if (SplatValue.Val) { // Splat of one value?
4961 // Build the shuffle constant vector: <0, 0, 0, 0>
4962 MVT::ValueType MaskVT =
4963 MVT::getIntVectorWithNumElements(NumElems);
4964 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4965 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4966 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4967 &ZeroVec[0], ZeroVec.size());
4969 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4970 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4971 // Get the splatted value into the low element of a vector register.
4972 SDOperand LowValVec =
4973 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4975 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4976 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4977 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4982 // If there are only two unique elements, we may be able to turn this into a
4984 if (Values.size() == 2) {
4985 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4986 MVT::ValueType MaskVT =
4987 MVT::getIntVectorWithNumElements(NumElems);
4988 std::vector<SDOperand> MaskVec(NumElems);
4990 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4991 E = Values.end(); I != E; ++I) {
4992 for (std::vector<unsigned>::iterator II = I->second.begin(),
4993 EE = I->second.end(); II != EE; ++II)
4994 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4997 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4998 &MaskVec[0], MaskVec.size());
5000 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5001 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5002 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5003 SmallVector<SDOperand, 8> Ops;
5004 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
5005 E = Values.end(); I != E; ++I) {
5006 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
5010 Ops.push_back(ShuffleMask);
5012 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5013 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
5014 &Ops[0], Ops.size());
5018 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5019 // aligned object on the stack, store each element into it, then load
5020 // the result as a vector.
5021 MVT::ValueType VT = Node->getValueType(0);
5022 // Create the stack frame object.
5023 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
5025 // Emit a store of each element to the stack slot.
5026 SmallVector<SDOperand, 8> Stores;
5027 unsigned TypeByteSize =
5028 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
5029 // Store (in the right endianness) the elements to memory.
5030 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5031 // Ignore undef elements.
5032 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5034 unsigned Offset = TypeByteSize*i;
5036 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5037 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5039 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5043 SDOperand StoreChain;
5044 if (!Stores.empty()) // Not all undef elements?
5045 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5046 &Stores[0], Stores.size());
5048 StoreChain = DAG.getEntryNode();
5050 // Result is a load from the stack slot.
5051 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5054 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5055 SDOperand Op, SDOperand Amt,
5056 SDOperand &Lo, SDOperand &Hi) {
5057 // Expand the subcomponents.
5058 SDOperand LHSL, LHSH;
5059 ExpandOp(Op, LHSL, LHSH);
5061 SDOperand Ops[] = { LHSL, LHSH, Amt };
5062 MVT::ValueType VT = LHSL.getValueType();
5063 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5064 Hi = Lo.getValue(1);
5068 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5069 /// smaller elements. If we can't find a way that is more efficient than a
5070 /// libcall on this target, return false. Otherwise, return true with the
5071 /// low-parts expanded into Lo and Hi.
5072 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
5073 SDOperand &Lo, SDOperand &Hi) {
5074 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5075 "This is not a shift!");
5077 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
5078 SDOperand ShAmt = LegalizeOp(Amt);
5079 MVT::ValueType ShTy = ShAmt.getValueType();
5080 unsigned ShBits = MVT::getSizeInBits(ShTy);
5081 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
5082 unsigned NVTBits = MVT::getSizeInBits(NVT);
5084 // Handle the case when Amt is an immediate.
5085 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
5086 unsigned Cst = CN->getValue();
5087 // Expand the incoming operand to be shifted, so that we have its parts
5089 ExpandOp(Op, InL, InH);
5093 Lo = DAG.getConstant(0, NVT);
5094 Hi = DAG.getConstant(0, NVT);
5095 } else if (Cst > NVTBits) {
5096 Lo = DAG.getConstant(0, NVT);
5097 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5098 } else if (Cst == NVTBits) {
5099 Lo = DAG.getConstant(0, NVT);
5102 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5103 Hi = DAG.getNode(ISD::OR, NVT,
5104 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5105 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5110 Lo = DAG.getConstant(0, NVT);
5111 Hi = DAG.getConstant(0, NVT);
5112 } else if (Cst > NVTBits) {
5113 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5114 Hi = DAG.getConstant(0, NVT);
5115 } else if (Cst == NVTBits) {
5117 Hi = DAG.getConstant(0, NVT);
5119 Lo = DAG.getNode(ISD::OR, NVT,
5120 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5121 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5122 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5127 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5128 DAG.getConstant(NVTBits-1, ShTy));
5129 } else if (Cst > NVTBits) {
5130 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5131 DAG.getConstant(Cst-NVTBits, ShTy));
5132 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5133 DAG.getConstant(NVTBits-1, ShTy));
5134 } else if (Cst == NVTBits) {
5136 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5137 DAG.getConstant(NVTBits-1, ShTy));
5139 Lo = DAG.getNode(ISD::OR, NVT,
5140 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5141 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5142 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5148 // Okay, the shift amount isn't constant. However, if we can tell that it is
5149 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5150 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5151 APInt KnownZero, KnownOne;
5152 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5154 // If we know that if any of the high bits of the shift amount are one, then
5155 // we can do this as a couple of simple shifts.
5156 if (KnownOne.intersects(Mask)) {
5157 // Mask out the high bit, which we know is set.
5158 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5159 DAG.getConstant(~Mask, Amt.getValueType()));
5161 // Expand the incoming operand to be shifted, so that we have its parts
5163 ExpandOp(Op, InL, InH);
5166 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5167 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5170 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5171 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5174 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5175 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5176 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5181 // If we know that the high bits of the shift amount are all zero, then we can
5182 // do this as a couple of simple shifts.
5183 if ((KnownZero & Mask) == Mask) {
5185 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5186 DAG.getConstant(NVTBits, Amt.getValueType()),
5189 // Expand the incoming operand to be shifted, so that we have its parts
5191 ExpandOp(Op, InL, InH);
5194 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5195 Hi = DAG.getNode(ISD::OR, NVT,
5196 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5197 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5200 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5201 Lo = DAG.getNode(ISD::OR, NVT,
5202 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5203 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5206 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5207 Lo = DAG.getNode(ISD::OR, NVT,
5208 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5209 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5218 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5219 // does not fit into a register, return the lo part and set the hi part to the
5220 // by-reg argument. If it does fit into a single register, return the result
5221 // and leave the Hi part unset.
5222 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
5223 bool isSigned, SDOperand &Hi) {
5224 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5225 // The input chain to this libcall is the entry node of the function.
5226 // Legalizing the call will automatically add the previous call to the
5228 SDOperand InChain = DAG.getEntryNode();
5230 TargetLowering::ArgListTy Args;
5231 TargetLowering::ArgListEntry Entry;
5232 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5233 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
5234 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
5235 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5236 Entry.isSExt = isSigned;
5237 Entry.isZExt = !isSigned;
5238 Args.push_back(Entry);
5240 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
5242 // Splice the libcall in wherever FindInputOutputChains tells us to.
5243 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
5244 std::pair<SDOperand,SDOperand> CallInfo =
5245 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
5246 false, Callee, Args, DAG);
5248 // Legalize the call sequence, starting with the chain. This will advance
5249 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5250 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5251 LegalizeOp(CallInfo.second);
5253 switch (getTypeAction(CallInfo.first.getValueType())) {
5254 default: assert(0 && "Unknown thing");
5256 Result = CallInfo.first;
5259 ExpandOp(CallInfo.first, Result, Hi);
5266 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5268 SDOperand SelectionDAGLegalize::
5269 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
5270 assert(getTypeAction(Source.getValueType()) == Expand &&
5271 "This is not an expansion!");
5272 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
5275 assert(Source.getValueType() == MVT::i64 &&
5276 "This only works for 64-bit -> FP");
5277 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
5278 // incoming integer is set. To handle this, we dynamically test to see if
5279 // it is set, and, if so, add a fudge factor.
5281 ExpandOp(Source, Lo, Hi);
5283 // If this is unsigned, and not supported, first perform the conversion to
5284 // signed, then adjust the result if the sign bit is set.
5285 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
5286 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
5288 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
5289 DAG.getConstant(0, Hi.getValueType()),
5291 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5292 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5293 SignSet, Four, Zero);
5294 uint64_t FF = 0x5f800000ULL;
5295 if (TLI.isLittleEndian()) FF <<= 32;
5296 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5298 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5299 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5300 SDOperand FudgeInReg;
5301 if (DestTy == MVT::f32)
5302 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5303 PseudoSourceValue::getConstantPool(), 0);
5304 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
5305 // FIXME: Avoid the extend by construction the right constantpool?
5306 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5308 PseudoSourceValue::getConstantPool(), 0,
5311 assert(0 && "Unexpected conversion");
5313 MVT::ValueType SCVT = SignedConv.getValueType();
5314 if (SCVT != DestTy) {
5315 // Destination type needs to be expanded as well. The FADD now we are
5316 // constructing will be expanded into a libcall.
5317 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
5318 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
5319 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
5320 SignedConv, SignedConv.getValue(1));
5322 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5324 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5327 // Check to see if the target has a custom way to lower this. If so, use it.
5328 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
5329 default: assert(0 && "This action not implemented for this operation!");
5330 case TargetLowering::Legal:
5331 case TargetLowering::Expand:
5332 break; // This case is handled below.
5333 case TargetLowering::Custom: {
5334 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5337 return LegalizeOp(NV);
5338 break; // The target decided this was legal after all
5342 // Expand the source, then glue it back together for the call. We must expand
5343 // the source in case it is shared (this pass of legalize must traverse it).
5344 SDOperand SrcLo, SrcHi;
5345 ExpandOp(Source, SrcLo, SrcHi);
5346 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
5349 if (DestTy == MVT::f32)
5350 LC = RTLIB::SINTTOFP_I64_F32;
5352 assert(DestTy == MVT::f64 && "Unknown fp value type!");
5353 LC = RTLIB::SINTTOFP_I64_F64;
5356 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
5357 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5358 SDOperand UnusedHiPart;
5359 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
5363 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5364 /// INT_TO_FP operation of the specified operand when the target requests that
5365 /// we expand it. At this point, we know that the result and operand types are
5366 /// legal for the target.
5367 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5369 MVT::ValueType DestVT) {
5370 if (Op0.getValueType() == MVT::i32) {
5371 // simple 32-bit [signed|unsigned] integer to float/double expansion
5373 // Get the stack frame index of a 8 byte buffer.
5374 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5376 // word offset constant for Hi/Lo address computation
5377 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5378 // set up Hi and Lo (into buffer) address based on endian
5379 SDOperand Hi = StackSlot;
5380 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5381 if (TLI.isLittleEndian())
5384 // if signed map to unsigned space
5385 SDOperand Op0Mapped;
5387 // constant used to invert sign bit (signed to unsigned mapping)
5388 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5389 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5393 // store the lo of the constructed double - based on integer input
5394 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5395 Op0Mapped, Lo, NULL, 0);
5396 // initial hi portion of constructed double
5397 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5398 // store the hi of the constructed double - biased exponent
5399 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5400 // load the constructed double
5401 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5402 // FP constant to bias correct the final result
5403 SDOperand Bias = DAG.getConstantFP(isSigned ?
5404 BitsToDouble(0x4330000080000000ULL)
5405 : BitsToDouble(0x4330000000000000ULL),
5407 // subtract the bias
5408 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5411 // handle final rounding
5412 if (DestVT == MVT::f64) {
5415 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
5416 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5417 DAG.getIntPtrConstant(0));
5418 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
5419 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5423 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5424 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5426 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
5427 DAG.getConstant(0, Op0.getValueType()),
5429 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5430 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5431 SignSet, Four, Zero);
5433 // If the sign bit of the integer is set, the large number will be treated
5434 // as a negative number. To counteract this, the dynamic code adds an
5435 // offset depending on the data type.
5437 switch (Op0.getValueType()) {
5438 default: assert(0 && "Unsupported integer type!");
5439 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5440 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5441 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5442 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5444 if (TLI.isLittleEndian()) FF <<= 32;
5445 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5447 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5448 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5449 SDOperand FudgeInReg;
5450 if (DestVT == MVT::f32)
5451 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5452 PseudoSourceValue::getConstantPool(), 0);
5455 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5456 DAG.getEntryNode(), CPIdx,
5457 PseudoSourceValue::getConstantPool(), 0,
5461 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5464 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5465 /// *INT_TO_FP operation of the specified operand when the target requests that
5466 /// we promote it. At this point, we know that the result and operand types are
5467 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5468 /// operation that takes a larger input.
5469 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5470 MVT::ValueType DestVT,
5472 // First step, figure out the appropriate *INT_TO_FP operation to use.
5473 MVT::ValueType NewInTy = LegalOp.getValueType();
5475 unsigned OpToUse = 0;
5477 // Scan for the appropriate larger type to use.
5479 NewInTy = (MVT::ValueType)(NewInTy+1);
5480 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
5482 // If the target supports SINT_TO_FP of this type, use it.
5483 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5485 case TargetLowering::Legal:
5486 if (!TLI.isTypeLegal(NewInTy))
5487 break; // Can't use this datatype.
5489 case TargetLowering::Custom:
5490 OpToUse = ISD::SINT_TO_FP;
5494 if (isSigned) continue;
5496 // If the target supports UINT_TO_FP of this type, use it.
5497 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5499 case TargetLowering::Legal:
5500 if (!TLI.isTypeLegal(NewInTy))
5501 break; // Can't use this datatype.
5503 case TargetLowering::Custom:
5504 OpToUse = ISD::UINT_TO_FP;
5509 // Otherwise, try a larger type.
5512 // Okay, we found the operation and type to use. Zero extend our input to the
5513 // desired type then run the operation on it.
5514 return DAG.getNode(OpToUse, DestVT,
5515 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5519 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5520 /// FP_TO_*INT operation of the specified operand when the target requests that
5521 /// we promote it. At this point, we know that the result and operand types are
5522 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5523 /// operation that returns a larger result.
5524 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5525 MVT::ValueType DestVT,
5527 // First step, figure out the appropriate FP_TO*INT operation to use.
5528 MVT::ValueType NewOutTy = DestVT;
5530 unsigned OpToUse = 0;
5532 // Scan for the appropriate larger type to use.
5534 NewOutTy = (MVT::ValueType)(NewOutTy+1);
5535 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
5537 // If the target supports FP_TO_SINT returning this type, use it.
5538 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5540 case TargetLowering::Legal:
5541 if (!TLI.isTypeLegal(NewOutTy))
5542 break; // Can't use this datatype.
5544 case TargetLowering::Custom:
5545 OpToUse = ISD::FP_TO_SINT;
5550 // If the target supports FP_TO_UINT of this type, use it.
5551 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5553 case TargetLowering::Legal:
5554 if (!TLI.isTypeLegal(NewOutTy))
5555 break; // Can't use this datatype.
5557 case TargetLowering::Custom:
5558 OpToUse = ISD::FP_TO_UINT;
5563 // Otherwise, try a larger type.
5567 // Okay, we found the operation and type to use.
5568 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5570 // If the operation produces an invalid type, it must be custom lowered. Use
5571 // the target lowering hooks to expand it. Just keep the low part of the
5572 // expanded operation, we know that we're truncating anyway.
5573 if (getTypeAction(NewOutTy) == Expand) {
5574 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
5575 assert(Operation.Val && "Didn't return anything");
5578 // Truncate the result of the extended FP_TO_*INT operation to the desired
5580 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5583 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5585 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5586 MVT::ValueType VT = Op.getValueType();
5587 MVT::ValueType SHVT = TLI.getShiftAmountTy();
5588 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5590 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5592 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5593 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5594 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5596 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5597 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5598 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5599 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5600 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5601 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5602 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5603 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5604 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5606 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5607 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5608 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5609 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5610 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5611 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5612 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5613 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5614 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5615 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5616 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5617 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5618 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5619 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5620 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5621 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5622 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5623 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5624 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5625 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5626 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5630 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5632 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5634 default: assert(0 && "Cannot expand this yet!");
5636 static const uint64_t mask[6] = {
5637 0x5555555555555555ULL, 0x3333333333333333ULL,
5638 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5639 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5641 MVT::ValueType VT = Op.getValueType();
5642 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5643 unsigned len = MVT::getSizeInBits(VT);
5644 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5645 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5646 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5647 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5648 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5649 DAG.getNode(ISD::AND, VT,
5650 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5655 // for now, we do this:
5656 // x = x | (x >> 1);
5657 // x = x | (x >> 2);
5659 // x = x | (x >>16);
5660 // x = x | (x >>32); // for 64-bit input
5661 // return popcount(~x);
5663 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5664 MVT::ValueType VT = Op.getValueType();
5665 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5666 unsigned len = MVT::getSizeInBits(VT);
5667 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5668 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5669 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5671 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5672 return DAG.getNode(ISD::CTPOP, VT, Op);
5675 // for now, we use: { return popcount(~x & (x - 1)); }
5676 // unless the target has ctlz but not ctpop, in which case we use:
5677 // { return 32 - nlz(~x & (x-1)); }
5678 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5679 MVT::ValueType VT = Op.getValueType();
5680 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5681 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5682 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5683 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5684 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5685 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5686 TLI.isOperationLegal(ISD::CTLZ, VT))
5687 return DAG.getNode(ISD::SUB, VT,
5688 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5689 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5690 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5695 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5696 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5697 /// LegalizeNodes map is filled in for any results that are not expanded, the
5698 /// ExpandedNodes map is filled in for any results that are expanded, and the
5699 /// Lo/Hi values are returned.
5700 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5701 MVT::ValueType VT = Op.getValueType();
5702 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5703 SDNode *Node = Op.Val;
5704 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5705 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5706 MVT::isVector(VT)) &&
5707 "Cannot expand to FP value or to larger int value!");
5709 // See if we already expanded it.
5710 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5711 = ExpandedNodes.find(Op);
5712 if (I != ExpandedNodes.end()) {
5713 Lo = I->second.first;
5714 Hi = I->second.second;
5718 switch (Node->getOpcode()) {
5719 case ISD::CopyFromReg:
5720 assert(0 && "CopyFromReg must be legal!");
5721 case ISD::FP_ROUND_INREG:
5722 if (VT == MVT::ppcf128 &&
5723 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5724 TargetLowering::Custom) {
5725 SDOperand SrcLo, SrcHi, Src;
5726 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5727 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5728 SDOperand Result = TLI.LowerOperation(
5729 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5730 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5731 Lo = Result.Val->getOperand(0);
5732 Hi = Result.Val->getOperand(1);
5738 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5740 assert(0 && "Do not know how to expand this operator!");
5742 case ISD::EXTRACT_VECTOR_ELT:
5743 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5744 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5745 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5746 return ExpandOp(Lo, Lo, Hi);
5748 NVT = TLI.getTypeToExpandTo(VT);
5749 Lo = DAG.getNode(ISD::UNDEF, NVT);
5750 Hi = DAG.getNode(ISD::UNDEF, NVT);
5752 case ISD::Constant: {
5753 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
5754 Lo = DAG.getConstant(Cst, NVT);
5755 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
5758 case ISD::ConstantFP: {
5759 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5760 if (CFP->getValueType(0) == MVT::ppcf128) {
5761 APInt api = CFP->getValueAPF().convertToAPInt();
5762 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5764 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5768 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5769 if (getTypeAction(Lo.getValueType()) == Expand)
5770 ExpandOp(Lo, Lo, Hi);
5773 case ISD::BUILD_PAIR:
5774 // Return the operands.
5775 Lo = Node->getOperand(0);
5776 Hi = Node->getOperand(1);
5779 case ISD::MERGE_VALUES:
5780 if (Node->getNumValues() == 1) {
5781 ExpandOp(Op.getOperand(0), Lo, Hi);
5784 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5785 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5786 Op.getValue(1).getValueType() == MVT::Other &&
5787 "unhandled MERGE_VALUES");
5788 ExpandOp(Op.getOperand(0), Lo, Hi);
5789 // Remember that we legalized the chain.
5790 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5793 case ISD::SIGN_EXTEND_INREG:
5794 ExpandOp(Node->getOperand(0), Lo, Hi);
5795 // sext_inreg the low part if needed.
5796 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5798 // The high part gets the sign extension from the lo-part. This handles
5799 // things like sextinreg V:i64 from i8.
5800 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5801 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5802 TLI.getShiftAmountTy()));
5806 ExpandOp(Node->getOperand(0), Lo, Hi);
5807 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5808 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5814 ExpandOp(Node->getOperand(0), Lo, Hi);
5815 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5816 DAG.getNode(ISD::CTPOP, NVT, Lo),
5817 DAG.getNode(ISD::CTPOP, NVT, Hi));
5818 Hi = DAG.getConstant(0, NVT);
5822 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5823 ExpandOp(Node->getOperand(0), Lo, Hi);
5824 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5825 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5826 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5828 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5829 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5831 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5832 Hi = DAG.getConstant(0, NVT);
5837 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5838 ExpandOp(Node->getOperand(0), Lo, Hi);
5839 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5840 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5841 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5843 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5844 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5846 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5847 Hi = DAG.getConstant(0, NVT);
5852 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5853 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5854 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5855 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5857 // Remember that we legalized the chain.
5858 Hi = LegalizeOp(Hi);
5859 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5860 if (TLI.isBigEndian())
5866 LoadSDNode *LD = cast<LoadSDNode>(Node);
5867 SDOperand Ch = LD->getChain(); // Legalize the chain.
5868 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5869 ISD::LoadExtType ExtType = LD->getExtensionType();
5870 int SVOffset = LD->getSrcValueOffset();
5871 unsigned Alignment = LD->getAlignment();
5872 bool isVolatile = LD->isVolatile();
5874 if (ExtType == ISD::NON_EXTLOAD) {
5875 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5876 isVolatile, Alignment);
5877 if (VT == MVT::f32 || VT == MVT::f64) {
5878 // f32->i32 or f64->i64 one to one expansion.
5879 // Remember that we legalized the chain.
5880 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5881 // Recursively expand the new load.
5882 if (getTypeAction(NVT) == Expand)
5883 ExpandOp(Lo, Lo, Hi);
5887 // Increment the pointer to the other half.
5888 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5889 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5890 DAG.getIntPtrConstant(IncrementSize));
5891 SVOffset += IncrementSize;
5892 Alignment = MinAlign(Alignment, IncrementSize);
5893 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5894 isVolatile, Alignment);
5896 // Build a factor node to remember that this load is independent of the
5898 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5901 // Remember that we legalized the chain.
5902 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5903 if (TLI.isBigEndian())
5906 MVT::ValueType EVT = LD->getMemoryVT();
5908 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5909 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5910 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5911 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5912 SVOffset, isVolatile, Alignment);
5913 // Remember that we legalized the chain.
5914 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5915 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5920 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5921 SVOffset, isVolatile, Alignment);
5923 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5924 SVOffset, EVT, isVolatile,
5927 // Remember that we legalized the chain.
5928 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5930 if (ExtType == ISD::SEXTLOAD) {
5931 // The high part is obtained by SRA'ing all but one of the bits of the
5933 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5934 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5935 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5936 } else if (ExtType == ISD::ZEXTLOAD) {
5937 // The high part is just a zero.
5938 Hi = DAG.getConstant(0, NVT);
5939 } else /* if (ExtType == ISD::EXTLOAD) */ {
5940 // The high part is undefined.
5941 Hi = DAG.getNode(ISD::UNDEF, NVT);
5948 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5949 SDOperand LL, LH, RL, RH;
5950 ExpandOp(Node->getOperand(0), LL, LH);
5951 ExpandOp(Node->getOperand(1), RL, RH);
5952 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5953 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5957 SDOperand LL, LH, RL, RH;
5958 ExpandOp(Node->getOperand(1), LL, LH);
5959 ExpandOp(Node->getOperand(2), RL, RH);
5960 if (getTypeAction(NVT) == Expand)
5961 NVT = TLI.getTypeToExpandTo(NVT);
5962 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5964 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5967 case ISD::SELECT_CC: {
5968 SDOperand TL, TH, FL, FH;
5969 ExpandOp(Node->getOperand(2), TL, TH);
5970 ExpandOp(Node->getOperand(3), FL, FH);
5971 if (getTypeAction(NVT) == Expand)
5972 NVT = TLI.getTypeToExpandTo(NVT);
5973 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5974 Node->getOperand(1), TL, FL, Node->getOperand(4));
5976 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5977 Node->getOperand(1), TH, FH, Node->getOperand(4));
5980 case ISD::ANY_EXTEND:
5981 // The low part is any extension of the input (which degenerates to a copy).
5982 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5983 // The high part is undefined.
5984 Hi = DAG.getNode(ISD::UNDEF, NVT);
5986 case ISD::SIGN_EXTEND: {
5987 // The low part is just a sign extension of the input (which degenerates to
5989 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5991 // The high part is obtained by SRA'ing all but one of the bits of the lo
5993 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5994 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5995 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5998 case ISD::ZERO_EXTEND:
5999 // The low part is just a zero extension of the input (which degenerates to
6001 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6003 // The high part is just a zero.
6004 Hi = DAG.getConstant(0, NVT);
6007 case ISD::TRUNCATE: {
6008 // The input value must be larger than this value. Expand *it*.
6010 ExpandOp(Node->getOperand(0), NewLo, Hi);
6012 // The low part is now either the right size, or it is closer. If not the
6013 // right size, make an illegal truncate so we recursively expand it.
6014 if (NewLo.getValueType() != Node->getValueType(0))
6015 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6016 ExpandOp(NewLo, Lo, Hi);
6020 case ISD::BIT_CONVERT: {
6022 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6023 // If the target wants to, allow it to lower this itself.
6024 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6025 case Expand: assert(0 && "cannot expand FP!");
6026 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6027 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6029 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6032 // f32 / f64 must be expanded to i32 / i64.
6033 if (VT == MVT::f32 || VT == MVT::f64) {
6034 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6035 if (getTypeAction(NVT) == Expand)
6036 ExpandOp(Lo, Lo, Hi);
6040 // If source operand will be expanded to the same type as VT, i.e.
6041 // i64 <- f64, i32 <- f32, expand the source operand instead.
6042 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
6043 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6044 ExpandOp(Node->getOperand(0), Lo, Hi);
6048 // Turn this into a load/store pair by default.
6050 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6052 ExpandOp(Tmp, Lo, Hi);
6056 case ISD::READCYCLECOUNTER: {
6057 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6058 TargetLowering::Custom &&
6059 "Must custom expand ReadCycleCounter");
6060 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6061 assert(Tmp.Val && "Node must be custom expanded!");
6062 ExpandOp(Tmp.getValue(0), Lo, Hi);
6063 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6064 LegalizeOp(Tmp.getValue(1)));
6068 // These operators cannot be expanded directly, emit them as calls to
6069 // library functions.
6070 case ISD::FP_TO_SINT: {
6071 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6073 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6074 case Expand: assert(0 && "cannot expand FP!");
6075 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6076 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6079 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6081 // Now that the custom expander is done, expand the result, which is still
6084 ExpandOp(Op, Lo, Hi);
6089 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6090 if (Node->getOperand(0).getValueType() == MVT::f32)
6091 LC = RTLIB::FPTOSINT_F32_I64;
6092 else if (Node->getOperand(0).getValueType() == MVT::f64)
6093 LC = RTLIB::FPTOSINT_F64_I64;
6094 else if (Node->getOperand(0).getValueType() == MVT::f80)
6095 LC = RTLIB::FPTOSINT_F80_I64;
6096 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6097 LC = RTLIB::FPTOSINT_PPCF128_I64;
6098 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6099 false/*sign irrelevant*/, Hi);
6103 case ISD::FP_TO_UINT: {
6104 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6106 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6107 case Expand: assert(0 && "cannot expand FP!");
6108 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6109 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6112 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6114 // Now that the custom expander is done, expand the result.
6116 ExpandOp(Op, Lo, Hi);
6121 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6122 if (Node->getOperand(0).getValueType() == MVT::f32)
6123 LC = RTLIB::FPTOUINT_F32_I64;
6124 else if (Node->getOperand(0).getValueType() == MVT::f64)
6125 LC = RTLIB::FPTOUINT_F64_I64;
6126 else if (Node->getOperand(0).getValueType() == MVT::f80)
6127 LC = RTLIB::FPTOUINT_F80_I64;
6128 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6129 LC = RTLIB::FPTOUINT_PPCF128_I64;
6130 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6131 false/*sign irrelevant*/, Hi);
6136 // If the target wants custom lowering, do so.
6137 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6138 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6139 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6140 Op = TLI.LowerOperation(Op, DAG);
6142 // Now that the custom expander is done, expand the result, which is
6144 ExpandOp(Op, Lo, Hi);
6149 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6150 // this X << 1 as X+X.
6151 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6152 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6153 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6154 SDOperand LoOps[2], HiOps[3];
6155 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6156 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6157 LoOps[1] = LoOps[0];
6158 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6160 HiOps[1] = HiOps[0];
6161 HiOps[2] = Lo.getValue(1);
6162 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6167 // If we can emit an efficient shift operation, do so now.
6168 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6171 // If this target supports SHL_PARTS, use it.
6172 TargetLowering::LegalizeAction Action =
6173 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6174 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6175 Action == TargetLowering::Custom) {
6176 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6180 // Otherwise, emit a libcall.
6181 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
6182 false/*left shift=unsigned*/, Hi);
6187 // If the target wants custom lowering, do so.
6188 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6189 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6190 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6191 Op = TLI.LowerOperation(Op, DAG);
6193 // Now that the custom expander is done, expand the result, which is
6195 ExpandOp(Op, Lo, Hi);
6200 // If we can emit an efficient shift operation, do so now.
6201 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6204 // If this target supports SRA_PARTS, use it.
6205 TargetLowering::LegalizeAction Action =
6206 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6207 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6208 Action == TargetLowering::Custom) {
6209 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6213 // Otherwise, emit a libcall.
6214 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
6215 true/*ashr is signed*/, Hi);
6220 // If the target wants custom lowering, do so.
6221 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6222 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6223 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6224 Op = TLI.LowerOperation(Op, DAG);
6226 // Now that the custom expander is done, expand the result, which is
6228 ExpandOp(Op, Lo, Hi);
6233 // If we can emit an efficient shift operation, do so now.
6234 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6237 // If this target supports SRL_PARTS, use it.
6238 TargetLowering::LegalizeAction Action =
6239 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6240 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6241 Action == TargetLowering::Custom) {
6242 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6246 // Otherwise, emit a libcall.
6247 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
6248 false/*lshr is unsigned*/, Hi);
6254 // If the target wants to custom expand this, let them.
6255 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6256 TargetLowering::Custom) {
6257 Op = TLI.LowerOperation(Op, DAG);
6259 ExpandOp(Op, Lo, Hi);
6264 // Expand the subcomponents.
6265 SDOperand LHSL, LHSH, RHSL, RHSH;
6266 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6267 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6268 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6269 SDOperand LoOps[2], HiOps[3];
6274 if (Node->getOpcode() == ISD::ADD) {
6275 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6276 HiOps[2] = Lo.getValue(1);
6277 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6279 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6280 HiOps[2] = Lo.getValue(1);
6281 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6288 // Expand the subcomponents.
6289 SDOperand LHSL, LHSH, RHSL, RHSH;
6290 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6291 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6292 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6293 SDOperand LoOps[2] = { LHSL, RHSL };
6294 SDOperand HiOps[3] = { LHSH, RHSH };
6296 if (Node->getOpcode() == ISD::ADDC) {
6297 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6298 HiOps[2] = Lo.getValue(1);
6299 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6301 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6302 HiOps[2] = Lo.getValue(1);
6303 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6305 // Remember that we legalized the flag.
6306 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6311 // Expand the subcomponents.
6312 SDOperand LHSL, LHSH, RHSL, RHSH;
6313 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6314 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6315 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6316 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6317 SDOperand HiOps[3] = { LHSH, RHSH };
6319 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6320 HiOps[2] = Lo.getValue(1);
6321 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6323 // Remember that we legalized the flag.
6324 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6328 // If the target wants to custom expand this, let them.
6329 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6330 SDOperand New = TLI.LowerOperation(Op, DAG);
6332 ExpandOp(New, Lo, Hi);
6337 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6338 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6339 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6340 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6341 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6342 SDOperand LL, LH, RL, RH;
6343 ExpandOp(Node->getOperand(0), LL, LH);
6344 ExpandOp(Node->getOperand(1), RL, RH);
6345 unsigned OuterBitSize = Op.getValueSizeInBits();
6346 unsigned InnerBitSize = RH.getValueSizeInBits();
6347 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6348 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6349 if (DAG.MaskedValueIsZero(Op.getOperand(0),
6350 APInt::getHighBitsSet(OuterBitSize, LHSSB)) &&
6351 DAG.MaskedValueIsZero(Op.getOperand(1),
6352 APInt::getHighBitsSet(OuterBitSize, RHSSB))) {
6353 // The inputs are both zero-extended.
6355 // We can emit a umul_lohi.
6356 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6357 Hi = SDOperand(Lo.Val, 1);
6361 // We can emit a mulhu+mul.
6362 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6363 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6367 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6368 // The input values are both sign-extended.
6370 // We can emit a smul_lohi.
6371 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6372 Hi = SDOperand(Lo.Val, 1);
6376 // We can emit a mulhs+mul.
6377 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6378 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6383 // Lo,Hi = umul LHS, RHS.
6384 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6385 DAG.getVTList(NVT, NVT), LL, RL);
6387 Hi = UMulLOHI.getValue(1);
6388 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6389 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6390 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6391 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6395 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6396 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6397 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6398 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6399 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6400 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6405 // If nothing else, we can make a libcall.
6406 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
6407 false/*sign irrelevant*/, Hi);
6411 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
6414 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
6417 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
6420 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
6424 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32,
6427 RTLIB::ADD_PPCF128)),
6431 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32,
6434 RTLIB::SUB_PPCF128)),
6438 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32,
6441 RTLIB::MUL_PPCF128)),
6445 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32,
6448 RTLIB::DIV_PPCF128)),
6451 case ISD::FP_EXTEND:
6452 if (VT == MVT::ppcf128) {
6453 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6454 Node->getOperand(0).getValueType()==MVT::f64);
6455 const uint64_t zero = 0;
6456 if (Node->getOperand(0).getValueType()==MVT::f32)
6457 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6459 Hi = Node->getOperand(0);
6460 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6463 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
6466 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
6469 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32,
6472 RTLIB::POWI_PPCF128)),
6478 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6479 switch(Node->getOpcode()) {
6481 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6482 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6485 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6486 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6489 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6490 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6492 default: assert(0 && "Unreachable!");
6494 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
6498 if (VT == MVT::ppcf128) {
6500 ExpandOp(Node->getOperand(0), Lo, Tmp);
6501 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6502 // lo = hi==fabs(hi) ? lo : -lo;
6503 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6504 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6505 DAG.getCondCode(ISD::SETEQ));
6508 SDOperand Mask = (VT == MVT::f64)
6509 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6510 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6511 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6512 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6513 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6514 if (getTypeAction(NVT) == Expand)
6515 ExpandOp(Lo, Lo, Hi);
6519 if (VT == MVT::ppcf128) {
6520 ExpandOp(Node->getOperand(0), Lo, Hi);
6521 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6522 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6525 SDOperand Mask = (VT == MVT::f64)
6526 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6527 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6528 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6529 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6530 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6531 if (getTypeAction(NVT) == Expand)
6532 ExpandOp(Lo, Lo, Hi);
6535 case ISD::FCOPYSIGN: {
6536 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6537 if (getTypeAction(NVT) == Expand)
6538 ExpandOp(Lo, Lo, Hi);
6541 case ISD::SINT_TO_FP:
6542 case ISD::UINT_TO_FP: {
6543 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6544 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
6545 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) {
6546 static const uint64_t zero = 0;
6548 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6549 Node->getOperand(0)));
6550 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6552 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6553 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6554 Node->getOperand(0)));
6555 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6556 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6557 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6558 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6559 DAG.getConstant(0, MVT::i32),
6560 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6562 APFloat(APInt(128, 2, TwoE32)),
6565 DAG.getCondCode(ISD::SETLT)),
6570 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6571 // si64->ppcf128 done by libcall, below
6572 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6573 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6575 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6576 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6577 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6578 DAG.getConstant(0, MVT::i64),
6579 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6581 APFloat(APInt(128, 2, TwoE64)),
6584 DAG.getCondCode(ISD::SETLT)),
6588 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6589 if (Node->getOperand(0).getValueType() == MVT::i64) {
6591 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
6592 else if (VT == MVT::f64)
6593 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
6594 else if (VT == MVT::f80) {
6596 LC = RTLIB::SINTTOFP_I64_F80;
6598 else if (VT == MVT::ppcf128) {
6600 LC = RTLIB::SINTTOFP_I64_PPCF128;
6604 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
6606 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
6609 // Promote the operand if needed.
6610 if (getTypeAction(SrcVT) == Promote) {
6611 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6613 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6614 DAG.getValueType(SrcVT))
6615 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6616 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6619 const char *LibCall = TLI.getLibcallName(LC);
6621 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
6623 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6624 Node->getOperand(0));
6625 if (getTypeAction(Lo.getValueType()) == Expand)
6626 ExpandOp(Lo, Lo, Hi);
6632 // Make sure the resultant values have been legalized themselves, unless this
6633 // is a type that requires multi-step expansion.
6634 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6635 Lo = LegalizeOp(Lo);
6637 // Don't legalize the high part if it is expanded to a single node.
6638 Hi = LegalizeOp(Hi);
6641 // Remember in a map if the values will be reused later.
6642 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6643 assert(isNew && "Value already expanded?!?");
6646 /// SplitVectorOp - Given an operand of vector type, break it down into
6647 /// two smaller values, still of vector type.
6648 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6650 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
6651 SDNode *Node = Op.Val;
6652 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
6653 assert(NumElements > 1 && "Cannot split a single element vector!");
6655 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
6657 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6658 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6660 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
6661 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
6663 // See if we already split it.
6664 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6665 = SplitNodes.find(Op);
6666 if (I != SplitNodes.end()) {
6667 Lo = I->second.first;
6668 Hi = I->second.second;
6672 switch (Node->getOpcode()) {
6677 assert(0 && "Unhandled operation in SplitVectorOp!");
6679 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6680 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6682 case ISD::BUILD_PAIR:
6683 Lo = Node->getOperand(0);
6684 Hi = Node->getOperand(1);
6686 case ISD::INSERT_VECTOR_ELT: {
6687 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6688 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
6689 SDOperand ScalarOp = Node->getOperand(1);
6690 if (Index < NewNumElts_Lo)
6691 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6692 DAG.getConstant(Index, TLI.getPointerTy()));
6694 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6695 DAG.getConstant(Index - NewNumElts_Lo,
6696 TLI.getPointerTy()));
6699 case ISD::VECTOR_SHUFFLE: {
6700 // Build the low part.
6701 SDOperand Mask = Node->getOperand(2);
6702 SmallVector<SDOperand, 8> Ops;
6703 MVT::ValueType PtrVT = TLI.getPointerTy();
6705 // Insert all of the elements from the input that are needed. We use
6706 // buildvector of extractelement here because the input vectors will have
6707 // to be legalized, so this makes the code simpler.
6708 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6709 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6710 SDOperand InVec = Node->getOperand(0);
6711 if (Idx >= NumElements) {
6712 InVec = Node->getOperand(1);
6715 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6716 DAG.getConstant(Idx, PtrVT)));
6718 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6721 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6722 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6723 SDOperand InVec = Node->getOperand(0);
6724 if (Idx >= NumElements) {
6725 InVec = Node->getOperand(1);
6728 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6729 DAG.getConstant(Idx, PtrVT)));
6731 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6734 case ISD::BUILD_VECTOR: {
6735 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6736 Node->op_begin()+NewNumElts_Lo);
6737 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6739 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6741 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6744 case ISD::CONCAT_VECTORS: {
6745 // FIXME: Handle non-power-of-two vectors?
6746 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6747 if (NewNumSubvectors == 1) {
6748 Lo = Node->getOperand(0);
6749 Hi = Node->getOperand(1);
6751 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6752 Node->op_begin()+NewNumSubvectors);
6753 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6755 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6757 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6762 SDOperand Cond = Node->getOperand(0);
6764 SDOperand LL, LH, RL, RH;
6765 SplitVectorOp(Node->getOperand(1), LL, LH);
6766 SplitVectorOp(Node->getOperand(2), RL, RH);
6768 if (MVT::isVector(Cond.getValueType())) {
6769 // Handle a vector merge.
6771 SplitVectorOp(Cond, CL, CH);
6772 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6773 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6775 // Handle a simple select with vector operands.
6776 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6777 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6797 SDOperand LL, LH, RL, RH;
6798 SplitVectorOp(Node->getOperand(0), LL, LH);
6799 SplitVectorOp(Node->getOperand(1), RL, RH);
6801 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6802 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6807 SplitVectorOp(Node->getOperand(0), L, H);
6809 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6810 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6821 case ISD::FP_TO_SINT:
6822 case ISD::FP_TO_UINT:
6823 case ISD::SINT_TO_FP:
6824 case ISD::UINT_TO_FP: {
6826 SplitVectorOp(Node->getOperand(0), L, H);
6828 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6829 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6833 LoadSDNode *LD = cast<LoadSDNode>(Node);
6834 SDOperand Ch = LD->getChain();
6835 SDOperand Ptr = LD->getBasePtr();
6836 const Value *SV = LD->getSrcValue();
6837 int SVOffset = LD->getSrcValueOffset();
6838 unsigned Alignment = LD->getAlignment();
6839 bool isVolatile = LD->isVolatile();
6841 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6842 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
6843 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6844 DAG.getIntPtrConstant(IncrementSize));
6845 SVOffset += IncrementSize;
6846 Alignment = MinAlign(Alignment, IncrementSize);
6847 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6849 // Build a factor node to remember that this load is independent of the
6851 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6854 // Remember that we legalized the chain.
6855 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6858 case ISD::BIT_CONVERT: {
6859 // We know the result is a vector. The input may be either a vector or a
6861 SDOperand InOp = Node->getOperand(0);
6862 if (!MVT::isVector(InOp.getValueType()) ||
6863 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
6864 // The input is a scalar or single-element vector.
6865 // Lower to a store/load so that it can be split.
6866 // FIXME: this could be improved probably.
6867 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6868 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val);
6870 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6872 PseudoSourceValue::getFixedStack(),
6874 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
6875 PseudoSourceValue::getFixedStack(),
6878 // Split the vector and convert each of the pieces now.
6879 SplitVectorOp(InOp, Lo, Hi);
6880 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6881 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6886 // Remember in a map if the values will be reused later.
6888 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6889 assert(isNew && "Value already split?!?");
6893 /// ScalarizeVectorOp - Given an operand of single-element vector type
6894 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6895 /// scalar (e.g. f32) value.
6896 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6897 assert(MVT::isVector(Op.getValueType()) &&
6898 "Bad ScalarizeVectorOp invocation!");
6899 SDNode *Node = Op.Val;
6900 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
6901 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
6903 // See if we already scalarized it.
6904 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
6905 if (I != ScalarizedNodes.end()) return I->second;
6908 switch (Node->getOpcode()) {
6911 Node->dump(&DAG); cerr << "\n";
6913 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
6930 Result = DAG.getNode(Node->getOpcode(),
6932 ScalarizeVectorOp(Node->getOperand(0)),
6933 ScalarizeVectorOp(Node->getOperand(1)));
6940 Result = DAG.getNode(Node->getOpcode(),
6942 ScalarizeVectorOp(Node->getOperand(0)));
6945 Result = DAG.getNode(Node->getOpcode(),
6947 ScalarizeVectorOp(Node->getOperand(0)),
6948 Node->getOperand(1));
6951 LoadSDNode *LD = cast<LoadSDNode>(Node);
6952 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
6953 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
6955 const Value *SV = LD->getSrcValue();
6956 int SVOffset = LD->getSrcValueOffset();
6957 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
6958 LD->isVolatile(), LD->getAlignment());
6960 // Remember that we legalized the chain.
6961 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
6964 case ISD::BUILD_VECTOR:
6965 Result = Node->getOperand(0);
6967 case ISD::INSERT_VECTOR_ELT:
6968 // Returning the inserted scalar element.
6969 Result = Node->getOperand(1);
6971 case ISD::CONCAT_VECTORS:
6972 assert(Node->getOperand(0).getValueType() == NewVT &&
6973 "Concat of non-legal vectors not yet supported!");
6974 Result = Node->getOperand(0);
6976 case ISD::VECTOR_SHUFFLE: {
6977 // Figure out if the scalar is the LHS or RHS and return it.
6978 SDOperand EltNum = Node->getOperand(2).getOperand(0);
6979 if (cast<ConstantSDNode>(EltNum)->getValue())
6980 Result = ScalarizeVectorOp(Node->getOperand(1));
6982 Result = ScalarizeVectorOp(Node->getOperand(0));
6985 case ISD::EXTRACT_SUBVECTOR:
6986 Result = Node->getOperand(0);
6987 assert(Result.getValueType() == NewVT);
6989 case ISD::BIT_CONVERT:
6990 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
6993 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
6994 ScalarizeVectorOp(Op.getOperand(1)),
6995 ScalarizeVectorOp(Op.getOperand(2)));
6999 if (TLI.isTypeLegal(NewVT))
7000 Result = LegalizeOp(Result);
7001 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7002 assert(isNew && "Value already scalarized?");
7007 // SelectionDAG::Legalize - This is the entry point for the file.
7009 void SelectionDAG::Legalize() {
7010 if (ViewLegalizeDAGs) viewGraph();
7012 /// run - This is the main entry point to this class.
7014 SelectionDAGLegalize(*this).LegalizeDAG();