1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Target/TargetLowering.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Visibility.h"
25 #include "llvm/ADT/SmallVector.h"
32 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
33 cl::desc("Pop up a window to show dags before legalize"));
35 static const bool ViewLegalizeDAGs = 0;
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class VISIBILITY_HIDDEN SelectionDAGLegalize {
55 // Libcall insertion helpers.
57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
58 /// legalized. We use this to ensure that calls are properly serialized
59 /// against each other, including inserted libcalls.
60 SDOperand LastCALLSEQ_END;
62 /// IsLegalizingCall - This member is used *only* for purposes of providing
63 /// helpful assertions that a libcall isn't created while another call is
64 /// being legalized (which could lead to non-serialized call sequences).
65 bool IsLegalizingCall;
68 Legal, // The target natively supports this operation.
69 Promote, // This operation should be executed in a larger type.
70 Expand // Try to expand this to other ops, otherwise use a libcall.
73 /// ValueTypeActions - This is a bitvector that contains two bits for each
74 /// value type, where the two bits correspond to the LegalizeAction enum.
75 /// This can be queried with "getTypeAction(VT)".
76 TargetLowering::ValueTypeActionImpl ValueTypeActions;
78 /// LegalizedNodes - For nodes that are of legal width, and that have more
79 /// than one use, this map indicates what regularized operand to use. This
80 /// allows us to avoid legalizing the same thing more than once.
81 std::map<SDOperand, SDOperand> LegalizedNodes;
83 /// PromotedNodes - For nodes that are below legal width, and that have more
84 /// than one use, this map indicates what promoted value to use. This allows
85 /// us to avoid promoting the same thing more than once.
86 std::map<SDOperand, SDOperand> PromotedNodes;
88 /// ExpandedNodes - For nodes that need to be expanded this map indicates
89 /// which which operands are the expanded version of the input. This allows
90 /// us to avoid expanding the same node more than once.
91 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
93 /// SplitNodes - For vector nodes that need to be split, this map indicates
94 /// which which operands are the split version of the input. This allows us
95 /// to avoid splitting the same node more than once.
96 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
98 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
99 /// concrete packed types, this contains the mapping of ones we have already
100 /// processed to the result.
101 std::map<SDOperand, SDOperand> PackedNodes;
103 void AddLegalizedOperand(SDOperand From, SDOperand To) {
104 LegalizedNodes.insert(std::make_pair(From, To));
105 // If someone requests legalization of the new node, return itself.
107 LegalizedNodes.insert(std::make_pair(To, To));
109 void AddPromotedOperand(SDOperand From, SDOperand To) {
110 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
111 assert(isNew && "Got into the map somehow?");
112 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
118 SelectionDAGLegalize(SelectionDAG &DAG);
120 /// getTypeAction - Return how we should legalize values of this type, either
121 /// it is already legal or we need to expand it into multiple registers of
122 /// smaller integer type, or we need to promote it to a larger type.
123 LegalizeAction getTypeAction(MVT::ValueType VT) const {
124 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
127 /// isTypeLegal - Return true if this type is legal on this target.
129 bool isTypeLegal(MVT::ValueType VT) const {
130 return getTypeAction(VT) == Legal;
136 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
137 /// appropriate for its type.
138 void HandleOp(SDOperand Op);
140 /// LegalizeOp - We know that the specified value has a legal type.
141 /// Recursively ensure that the operands have legal types, then return the
143 SDOperand LegalizeOp(SDOperand O);
145 /// PromoteOp - Given an operation that produces a value in an invalid type,
146 /// promote it to compute the value into a larger type. The produced value
147 /// will have the correct bits for the low portion of the register, but no
148 /// guarantee is made about the top bits: it may be zero, sign-extended, or
150 SDOperand PromoteOp(SDOperand O);
152 /// ExpandOp - Expand the specified SDOperand into its two component pieces
153 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
154 /// the LegalizeNodes map is filled in for any results that are not expanded,
155 /// the ExpandedNodes map is filled in for any results that are expanded, and
156 /// the Lo/Hi values are returned. This applies to integer types and Vector
158 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
160 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
161 /// two smaller values of MVT::Vector type.
162 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
164 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
165 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
166 /// this is called, we know that PackedVT is the right type for the result and
167 /// we know that this type is legal for the target.
168 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
170 /// isShuffleLegal - Return true if a vector shuffle is legal with the
171 /// specified mask and type. Targets can specify exactly which masks they
172 /// support and the code generator is tasked with not creating illegal masks.
174 /// Note that this will also return true for shuffles that are promoted to a
177 /// If this is a legal shuffle, this method returns the (possibly promoted)
178 /// build_vector Mask. If it's not a legal shuffle, it returns null.
179 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
181 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
182 std::set<SDNode*> &NodesLeadingTo);
184 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
186 SDOperand CreateStackTemporary(MVT::ValueType VT);
188 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
190 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
193 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
194 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
195 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
196 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
198 MVT::ValueType DestVT);
199 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
201 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
204 SDOperand ExpandBSWAP(SDOperand Op);
205 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
206 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
207 SDOperand &Lo, SDOperand &Hi);
208 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
209 SDOperand &Lo, SDOperand &Hi);
211 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
212 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
214 SDOperand getIntPtrConstant(uint64_t Val) {
215 return DAG.getConstant(Val, TLI.getPointerTy());
220 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
221 /// specified mask and type. Targets can specify exactly which masks they
222 /// support and the code generator is tasked with not creating illegal masks.
224 /// Note that this will also return true for shuffles that are promoted to a
226 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
227 SDOperand Mask) const {
228 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
230 case TargetLowering::Legal:
231 case TargetLowering::Custom:
233 case TargetLowering::Promote: {
234 // If this is promoted to a different type, convert the shuffle mask and
235 // ask if it is legal in the promoted type!
236 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
238 // If we changed # elements, change the shuffle mask.
239 unsigned NumEltsGrowth =
240 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
241 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
242 if (NumEltsGrowth > 1) {
243 // Renumber the elements.
244 SmallVector<SDOperand, 8> Ops;
245 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
246 SDOperand InOp = Mask.getOperand(i);
247 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
248 if (InOp.getOpcode() == ISD::UNDEF)
249 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
251 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
252 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
256 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
262 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
265 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
266 /// specified vector opcode.
267 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
269 default: assert(0 && "Don't know how to scalarize this opcode!");
270 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
271 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
272 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
273 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
274 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
275 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
276 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
277 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
281 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
282 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
283 ValueTypeActions(TLI.getValueTypeActions()) {
284 assert(MVT::LAST_VALUETYPE <= 32 &&
285 "Too many value types for ValueTypeActions to hold!");
288 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
289 /// not been visited yet and if all of its operands have already been visited.
290 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
291 std::map<SDNode*, unsigned> &Visited) {
292 if (++Visited[N] != N->getNumOperands())
293 return; // Haven't visited all operands yet
297 if (N->hasOneUse()) { // Tail recurse in common case.
298 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
302 // Now that we have N in, add anything that uses it if all of their operands
304 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
305 ComputeTopDownOrdering(*UI, Order, Visited);
309 void SelectionDAGLegalize::LegalizeDAG() {
310 LastCALLSEQ_END = DAG.getEntryNode();
311 IsLegalizingCall = false;
313 // The legalize process is inherently a bottom-up recursive process (users
314 // legalize their uses before themselves). Given infinite stack space, we
315 // could just start legalizing on the root and traverse the whole graph. In
316 // practice however, this causes us to run out of stack space on large basic
317 // blocks. To avoid this problem, compute an ordering of the nodes where each
318 // node is only legalized after all of its operands are legalized.
319 std::map<SDNode*, unsigned> Visited;
320 std::vector<SDNode*> Order;
322 // Compute ordering from all of the leaves in the graphs, those (like the
323 // entry node) that have no operands.
324 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
325 E = DAG.allnodes_end(); I != E; ++I) {
326 if (I->getNumOperands() == 0) {
328 ComputeTopDownOrdering(I, Order, Visited);
332 assert(Order.size() == Visited.size() &&
334 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
335 "Error: DAG is cyclic!");
338 for (unsigned i = 0, e = Order.size(); i != e; ++i)
339 HandleOp(SDOperand(Order[i], 0));
341 // Finally, it's possible the root changed. Get the new root.
342 SDOperand OldRoot = DAG.getRoot();
343 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
344 DAG.setRoot(LegalizedNodes[OldRoot]);
346 ExpandedNodes.clear();
347 LegalizedNodes.clear();
348 PromotedNodes.clear();
352 // Remove dead nodes now.
353 DAG.RemoveDeadNodes();
357 /// FindCallEndFromCallStart - Given a chained node that is part of a call
358 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
359 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
360 if (Node->getOpcode() == ISD::CALLSEQ_END)
362 if (Node->use_empty())
363 return 0; // No CallSeqEnd
365 // The chain is usually at the end.
366 SDOperand TheChain(Node, Node->getNumValues()-1);
367 if (TheChain.getValueType() != MVT::Other) {
368 // Sometimes it's at the beginning.
369 TheChain = SDOperand(Node, 0);
370 if (TheChain.getValueType() != MVT::Other) {
371 // Otherwise, hunt for it.
372 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
373 if (Node->getValueType(i) == MVT::Other) {
374 TheChain = SDOperand(Node, i);
378 // Otherwise, we walked into a node without a chain.
379 if (TheChain.getValueType() != MVT::Other)
384 for (SDNode::use_iterator UI = Node->use_begin(),
385 E = Node->use_end(); UI != E; ++UI) {
387 // Make sure to only follow users of our token chain.
389 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
390 if (User->getOperand(i) == TheChain)
391 if (SDNode *Result = FindCallEndFromCallStart(User))
397 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
398 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
399 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
400 assert(Node && "Didn't find callseq_start for a call??");
401 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
403 assert(Node->getOperand(0).getValueType() == MVT::Other &&
404 "Node doesn't have a token chain argument!");
405 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
408 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
409 /// see if any uses can reach Dest. If no dest operands can get to dest,
410 /// legalize them, legalize ourself, and return false, otherwise, return true.
412 /// Keep track of the nodes we fine that actually do lead to Dest in
413 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
415 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
416 std::set<SDNode*> &NodesLeadingTo) {
417 if (N == Dest) return true; // N certainly leads to Dest :)
419 // If we've already processed this node and it does lead to Dest, there is no
420 // need to reprocess it.
421 if (NodesLeadingTo.count(N)) return true;
423 // If the first result of this node has been already legalized, then it cannot
425 switch (getTypeAction(N->getValueType(0))) {
427 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
430 if (PromotedNodes.count(SDOperand(N, 0))) return false;
433 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
437 // Okay, this node has not already been legalized. Check and legalize all
438 // operands. If none lead to Dest, then we can legalize this node.
439 bool OperandsLeadToDest = false;
440 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
441 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
442 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
444 if (OperandsLeadToDest) {
445 NodesLeadingTo.insert(N);
449 // Okay, this node looks safe, legalize it and return false.
450 HandleOp(SDOperand(N, 0));
454 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
455 /// appropriate for its type.
456 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
457 switch (getTypeAction(Op.getValueType())) {
458 default: assert(0 && "Bad type action!");
459 case Legal: LegalizeOp(Op); break;
460 case Promote: PromoteOp(Op); break;
462 if (Op.getValueType() != MVT::Vector) {
467 unsigned NumOps = N->getNumOperands();
468 unsigned NumElements =
469 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
470 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
471 MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
472 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
473 // In the common case, this is a legal vector type, convert it to the
474 // packed operation and type now.
475 PackVectorOp(Op, PackedVT);
476 } else if (NumElements == 1) {
477 // Otherwise, if this is a single element vector, convert it to a
479 PackVectorOp(Op, EVT);
481 // Otherwise, this is a multiple element vector that isn't supported.
482 // Split it in half and legalize both parts.
484 SplitVectorOp(Op, X, Y);
492 /// LegalizeOp - We know that the specified value has a legal type.
493 /// Recursively ensure that the operands have legal types, then return the
495 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
496 assert(isTypeLegal(Op.getValueType()) &&
497 "Caller should expand or promote operands that are not legal!");
498 SDNode *Node = Op.Val;
500 // If this operation defines any values that cannot be represented in a
501 // register on this target, make sure to expand or promote them.
502 if (Node->getNumValues() > 1) {
503 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
504 if (getTypeAction(Node->getValueType(i)) != Legal) {
505 HandleOp(Op.getValue(i));
506 assert(LegalizedNodes.count(Op) &&
507 "Handling didn't add legal operands!");
508 return LegalizedNodes[Op];
512 // Note that LegalizeOp may be reentered even from single-use nodes, which
513 // means that we always must cache transformed nodes.
514 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
515 if (I != LegalizedNodes.end()) return I->second;
517 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
518 SDOperand Result = Op;
519 bool isCustom = false;
521 switch (Node->getOpcode()) {
522 case ISD::FrameIndex:
523 case ISD::EntryToken:
525 case ISD::BasicBlock:
526 case ISD::TargetFrameIndex:
527 case ISD::TargetJumpTable:
528 case ISD::TargetConstant:
529 case ISD::TargetConstantFP:
530 case ISD::TargetConstantPool:
531 case ISD::TargetGlobalAddress:
532 case ISD::TargetExternalSymbol:
537 // Primitives must all be legal.
538 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
539 "This must be legal!");
542 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
543 // If this is a target node, legalize it by legalizing the operands then
544 // passing it through.
545 SmallVector<SDOperand, 8> Ops;
546 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
547 Ops.push_back(LegalizeOp(Node->getOperand(i)));
549 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
551 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
552 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
553 return Result.getValue(Op.ResNo);
555 // Otherwise this is an unhandled builtin node. splat.
557 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
559 assert(0 && "Do not know how to legalize this operator!");
561 case ISD::GlobalAddress:
562 case ISD::ExternalSymbol:
563 case ISD::ConstantPool:
564 case ISD::JumpTable: // Nothing to do.
565 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
566 default: assert(0 && "This action is not supported yet!");
567 case TargetLowering::Custom:
568 Tmp1 = TLI.LowerOperation(Op, DAG);
569 if (Tmp1.Val) Result = Tmp1;
570 // FALLTHROUGH if the target doesn't want to lower this op after all.
571 case TargetLowering::Legal:
575 case ISD::AssertSext:
576 case ISD::AssertZext:
577 Tmp1 = LegalizeOp(Node->getOperand(0));
578 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
580 case ISD::MERGE_VALUES:
581 // Legalize eliminates MERGE_VALUES nodes.
582 Result = Node->getOperand(Op.ResNo);
584 case ISD::CopyFromReg:
585 Tmp1 = LegalizeOp(Node->getOperand(0));
586 Result = Op.getValue(0);
587 if (Node->getNumValues() == 2) {
588 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
590 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
591 if (Node->getNumOperands() == 3) {
592 Tmp2 = LegalizeOp(Node->getOperand(2));
593 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
595 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
597 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
599 // Since CopyFromReg produces two values, make sure to remember that we
600 // legalized both of them.
601 AddLegalizedOperand(Op.getValue(0), Result);
602 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
603 return Result.getValue(Op.ResNo);
605 MVT::ValueType VT = Op.getValueType();
606 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
607 default: assert(0 && "This action is not supported yet!");
608 case TargetLowering::Expand:
609 if (MVT::isInteger(VT))
610 Result = DAG.getConstant(0, VT);
611 else if (MVT::isFloatingPoint(VT))
612 Result = DAG.getConstantFP(0, VT);
614 assert(0 && "Unknown value type!");
616 case TargetLowering::Legal:
622 case ISD::INTRINSIC_W_CHAIN:
623 case ISD::INTRINSIC_WO_CHAIN:
624 case ISD::INTRINSIC_VOID: {
625 SmallVector<SDOperand, 8> Ops;
626 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
627 Ops.push_back(LegalizeOp(Node->getOperand(i)));
628 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
630 // Allow the target to custom lower its intrinsics if it wants to.
631 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
632 TargetLowering::Custom) {
633 Tmp3 = TLI.LowerOperation(Result, DAG);
634 if (Tmp3.Val) Result = Tmp3;
637 if (Result.Val->getNumValues() == 1) break;
639 // Must have return value and chain result.
640 assert(Result.Val->getNumValues() == 2 &&
641 "Cannot return more than two values!");
643 // Since loads produce two values, make sure to remember that we
644 // legalized both of them.
645 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
646 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
647 return Result.getValue(Op.ResNo);
651 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
652 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
654 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
655 case TargetLowering::Promote:
656 default: assert(0 && "This action is not supported yet!");
657 case TargetLowering::Expand: {
658 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
659 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
660 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
662 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
663 const std::string &FName =
664 cast<StringSDNode>(Node->getOperand(3))->getValue();
665 const std::string &DirName =
666 cast<StringSDNode>(Node->getOperand(4))->getValue();
667 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
669 SmallVector<SDOperand, 8> Ops;
670 Ops.push_back(Tmp1); // chain
671 SDOperand LineOp = Node->getOperand(1);
672 SDOperand ColOp = Node->getOperand(2);
675 Ops.push_back(LineOp); // line #
676 Ops.push_back(ColOp); // col #
677 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
678 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
680 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
681 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
682 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
683 Ops.push_back(DAG.getConstant(ID, MVT::i32));
684 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,&Ops[0],Ops.size());
687 Result = Tmp1; // chain
691 case TargetLowering::Legal:
692 if (Tmp1 != Node->getOperand(0) ||
693 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
694 SmallVector<SDOperand, 8> Ops;
696 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
697 Ops.push_back(Node->getOperand(1)); // line # must be legal.
698 Ops.push_back(Node->getOperand(2)); // col # must be legal.
700 // Otherwise promote them.
701 Ops.push_back(PromoteOp(Node->getOperand(1)));
702 Ops.push_back(PromoteOp(Node->getOperand(2)));
704 Ops.push_back(Node->getOperand(3)); // filename must be legal.
705 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
706 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
713 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
714 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
715 default: assert(0 && "This action is not supported yet!");
716 case TargetLowering::Legal:
717 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
718 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
719 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
720 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
721 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
726 case ISD::DEBUG_LABEL:
727 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
728 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
729 default: assert(0 && "This action is not supported yet!");
730 case TargetLowering::Legal:
731 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
732 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
733 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
739 // We know we don't need to expand constants here, constants only have one
740 // value and we check that it is fine above.
742 // FIXME: Maybe we should handle things like targets that don't support full
743 // 32-bit immediates?
745 case ISD::ConstantFP: {
746 // Spill FP immediates to the constant pool if the target cannot directly
747 // codegen them. Targets often have some immediate values that can be
748 // efficiently generated into an FP register without a load. We explicitly
749 // leave these constants as ConstantFP nodes for the target to deal with.
750 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
752 // Check to see if this FP immediate is already legal.
753 bool isLegal = false;
754 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
755 E = TLI.legal_fpimm_end(); I != E; ++I)
756 if (CFP->isExactlyValue(*I)) {
761 // If this is a legal constant, turn it into a TargetConstantFP node.
763 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
767 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
768 default: assert(0 && "This action is not supported yet!");
769 case TargetLowering::Custom:
770 Tmp3 = TLI.LowerOperation(Result, DAG);
776 case TargetLowering::Expand:
777 // Otherwise we need to spill the constant to memory.
780 // If a FP immediate is precise when represented as a float and if the
781 // target can do an extending load from float to double, we put it into
782 // the constant pool as a float, even if it's is statically typed as a
784 MVT::ValueType VT = CFP->getValueType(0);
785 bool isDouble = VT == MVT::f64;
786 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
787 Type::FloatTy, CFP->getValue());
788 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
789 // Only do this if the target has a native EXTLOAD instruction from
791 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
792 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
797 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
799 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
800 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
802 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
803 DAG.getSrcValue(NULL));
808 case ISD::TokenFactor:
809 if (Node->getNumOperands() == 2) {
810 Tmp1 = LegalizeOp(Node->getOperand(0));
811 Tmp2 = LegalizeOp(Node->getOperand(1));
812 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
813 } else if (Node->getNumOperands() == 3) {
814 Tmp1 = LegalizeOp(Node->getOperand(0));
815 Tmp2 = LegalizeOp(Node->getOperand(1));
816 Tmp3 = LegalizeOp(Node->getOperand(2));
817 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
819 SmallVector<SDOperand, 8> Ops;
820 // Legalize the operands.
821 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
822 Ops.push_back(LegalizeOp(Node->getOperand(i)));
823 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
827 case ISD::FORMAL_ARGUMENTS:
829 // The only option for this is to custom lower it.
830 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
831 assert(Tmp3.Val && "Target didn't custom lower this node!");
832 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
833 "Lowering call/formal_arguments produced unexpected # results!");
835 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
836 // remember that we legalized all of them, so it doesn't get relegalized.
837 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
838 Tmp1 = LegalizeOp(Tmp3.getValue(i));
841 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
845 case ISD::BUILD_VECTOR:
846 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
847 default: assert(0 && "This action is not supported yet!");
848 case TargetLowering::Custom:
849 Tmp3 = TLI.LowerOperation(Result, DAG);
855 case TargetLowering::Expand:
856 Result = ExpandBUILD_VECTOR(Result.Val);
860 case ISD::INSERT_VECTOR_ELT:
861 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
862 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
863 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
864 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
866 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
867 Node->getValueType(0))) {
868 default: assert(0 && "This action is not supported yet!");
869 case TargetLowering::Legal:
871 case TargetLowering::Custom:
872 Tmp3 = TLI.LowerOperation(Result, DAG);
878 case TargetLowering::Expand: {
879 // If the insert index is a constant, codegen this as a scalar_to_vector,
880 // then a shuffle that inserts it into the right position in the vector.
881 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
882 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
883 Tmp1.getValueType(), Tmp2);
885 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
886 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
887 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT);
889 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
890 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
892 SmallVector<SDOperand, 8> ShufOps;
893 for (unsigned i = 0; i != NumElts; ++i) {
894 if (i != InsertPos->getValue())
895 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
897 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
899 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
900 &ShufOps[0], ShufOps.size());
902 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
903 Tmp1, ScVec, ShufMask);
904 Result = LegalizeOp(Result);
908 // If the target doesn't support this, we have to spill the input vector
909 // to a temporary stack slot, update the element, then reload it. This is
910 // badness. We could also load the value into a vector register (either
911 // with a "move to register" or "extload into register" instruction, then
912 // permute it into place, if the idx is a constant and if the idx is
913 // supported by the target.
914 MVT::ValueType VT = Tmp1.getValueType();
915 MVT::ValueType EltVT = Tmp2.getValueType();
916 MVT::ValueType IdxVT = Tmp3.getValueType();
917 MVT::ValueType PtrVT = TLI.getPointerTy();
918 SDOperand StackPtr = CreateStackTemporary(VT);
920 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
921 Tmp1, StackPtr, DAG.getSrcValue(NULL));
923 // Truncate or zero extend offset to target pointer type.
924 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
925 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
926 // Add the offset to the index.
927 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
928 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
929 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
930 // Store the scalar value.
931 Ch = DAG.getNode(ISD::STORE, MVT::Other, Ch,
932 Tmp2, StackPtr2, DAG.getSrcValue(NULL));
933 // Load the updated vector.
934 Result = DAG.getLoad(VT, Ch, StackPtr, DAG.getSrcValue(NULL));
939 case ISD::SCALAR_TO_VECTOR:
940 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
941 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
945 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
946 Result = DAG.UpdateNodeOperands(Result, Tmp1);
947 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
948 Node->getValueType(0))) {
949 default: assert(0 && "This action is not supported yet!");
950 case TargetLowering::Legal:
952 case TargetLowering::Custom:
953 Tmp3 = TLI.LowerOperation(Result, DAG);
959 case TargetLowering::Expand:
960 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
964 case ISD::VECTOR_SHUFFLE:
965 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
966 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
967 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
969 // Allow targets to custom lower the SHUFFLEs they support.
970 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
971 default: assert(0 && "Unknown operation action!");
972 case TargetLowering::Legal:
973 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
974 "vector shuffle should not be created if not legal!");
976 case TargetLowering::Custom:
977 Tmp3 = TLI.LowerOperation(Result, DAG);
983 case TargetLowering::Expand: {
984 MVT::ValueType VT = Node->getValueType(0);
985 MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
986 MVT::ValueType PtrVT = TLI.getPointerTy();
987 SDOperand Mask = Node->getOperand(2);
988 unsigned NumElems = Mask.getNumOperands();
989 SmallVector<SDOperand,8> Ops;
990 for (unsigned i = 0; i != NumElems; ++i) {
991 SDOperand Arg = Mask.getOperand(i);
992 if (Arg.getOpcode() == ISD::UNDEF) {
993 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
995 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
996 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
998 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
999 DAG.getConstant(Idx, PtrVT)));
1001 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1002 DAG.getConstant(Idx - NumElems, PtrVT)));
1005 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1008 case TargetLowering::Promote: {
1009 // Change base type to a different vector type.
1010 MVT::ValueType OVT = Node->getValueType(0);
1011 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1013 // Cast the two input vectors.
1014 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1015 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1017 // Convert the shuffle mask to the right # elements.
1018 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1019 assert(Tmp3.Val && "Shuffle not legal?");
1020 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1021 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1027 case ISD::EXTRACT_VECTOR_ELT:
1028 Tmp1 = LegalizeOp(Node->getOperand(0));
1029 Tmp2 = LegalizeOp(Node->getOperand(1));
1030 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1032 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
1033 Tmp1.getValueType())) {
1034 default: assert(0 && "This action is not supported yet!");
1035 case TargetLowering::Legal:
1037 case TargetLowering::Custom:
1038 Tmp3 = TLI.LowerOperation(Result, DAG);
1044 case TargetLowering::Expand:
1045 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1050 case ISD::VEXTRACT_VECTOR_ELT:
1051 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
1054 case ISD::CALLSEQ_START: {
1055 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1057 // Recursively Legalize all of the inputs of the call end that do not lead
1058 // to this call start. This ensures that any libcalls that need be inserted
1059 // are inserted *before* the CALLSEQ_START.
1060 {std::set<SDNode*> NodesLeadingTo;
1061 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1062 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1066 // Now that we legalized all of the inputs (which may have inserted
1067 // libcalls) create the new CALLSEQ_START node.
1068 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1070 // Merge in the last call, to ensure that this call start after the last
1072 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1073 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1074 Tmp1 = LegalizeOp(Tmp1);
1077 // Do not try to legalize the target-specific arguments (#1+).
1078 if (Tmp1 != Node->getOperand(0)) {
1079 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1081 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1084 // Remember that the CALLSEQ_START is legalized.
1085 AddLegalizedOperand(Op.getValue(0), Result);
1086 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1087 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1089 // Now that the callseq_start and all of the non-call nodes above this call
1090 // sequence have been legalized, legalize the call itself. During this
1091 // process, no libcalls can/will be inserted, guaranteeing that no calls
1093 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1094 SDOperand InCallSEQ = LastCALLSEQ_END;
1095 // Note that we are selecting this call!
1096 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1097 IsLegalizingCall = true;
1099 // Legalize the call, starting from the CALLSEQ_END.
1100 LegalizeOp(LastCALLSEQ_END);
1101 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1104 case ISD::CALLSEQ_END:
1105 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1106 // will cause this node to be legalized as well as handling libcalls right.
1107 if (LastCALLSEQ_END.Val != Node) {
1108 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1109 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1110 assert(I != LegalizedNodes.end() &&
1111 "Legalizing the call start should have legalized this node!");
1115 // Otherwise, the call start has been legalized and everything is going
1116 // according to plan. Just legalize ourselves normally here.
1117 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1118 // Do not try to legalize the target-specific arguments (#1+), except for
1119 // an optional flag input.
1120 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1121 if (Tmp1 != Node->getOperand(0)) {
1122 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1124 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1127 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1128 if (Tmp1 != Node->getOperand(0) ||
1129 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1130 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1133 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1136 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1137 // This finishes up call legalization.
1138 IsLegalizingCall = false;
1140 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1141 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1142 if (Node->getNumValues() == 2)
1143 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1144 return Result.getValue(Op.ResNo);
1145 case ISD::DYNAMIC_STACKALLOC: {
1146 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1147 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1148 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1149 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1151 Tmp1 = Result.getValue(0);
1152 Tmp2 = Result.getValue(1);
1153 switch (TLI.getOperationAction(Node->getOpcode(),
1154 Node->getValueType(0))) {
1155 default: assert(0 && "This action is not supported yet!");
1156 case TargetLowering::Expand: {
1157 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1158 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1159 " not tell us which reg is the stack pointer!");
1160 SDOperand Chain = Tmp1.getOperand(0);
1161 SDOperand Size = Tmp2.getOperand(1);
1162 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1163 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1164 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1165 Tmp1 = LegalizeOp(Tmp1);
1166 Tmp2 = LegalizeOp(Tmp2);
1169 case TargetLowering::Custom:
1170 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1172 Tmp1 = LegalizeOp(Tmp3);
1173 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1176 case TargetLowering::Legal:
1179 // Since this op produce two values, make sure to remember that we
1180 // legalized both of them.
1181 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1182 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1183 return Op.ResNo ? Tmp2 : Tmp1;
1185 case ISD::INLINEASM: {
1186 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1187 bool Changed = false;
1188 // Legalize all of the operands of the inline asm, in case they are nodes
1189 // that need to be expanded or something. Note we skip the asm string and
1190 // all of the TargetConstant flags.
1191 SDOperand Op = LegalizeOp(Ops[0]);
1192 Changed = Op != Ops[0];
1195 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1196 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1197 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1198 for (++i; NumVals; ++i, --NumVals) {
1199 SDOperand Op = LegalizeOp(Ops[i]);
1208 Op = LegalizeOp(Ops.back());
1209 Changed |= Op != Ops.back();
1214 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1216 // INLINE asm returns a chain and flag, make sure to add both to the map.
1217 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1218 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1219 return Result.getValue(Op.ResNo);
1222 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1223 // Ensure that libcalls are emitted before a branch.
1224 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1225 Tmp1 = LegalizeOp(Tmp1);
1226 LastCALLSEQ_END = DAG.getEntryNode();
1228 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1231 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1232 // Ensure that libcalls are emitted before a branch.
1233 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1234 Tmp1 = LegalizeOp(Tmp1);
1235 LastCALLSEQ_END = DAG.getEntryNode();
1237 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1238 default: assert(0 && "Indirect target must be legal type (pointer)!");
1240 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1243 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1246 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1247 // Ensure that libcalls are emitted before a return.
1248 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1249 Tmp1 = LegalizeOp(Tmp1);
1250 LastCALLSEQ_END = DAG.getEntryNode();
1252 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1253 case Expand: assert(0 && "It's impossible to expand bools");
1255 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1258 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1262 // Basic block destination (Op#2) is always legal.
1263 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1265 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1266 default: assert(0 && "This action is not supported yet!");
1267 case TargetLowering::Legal: break;
1268 case TargetLowering::Custom:
1269 Tmp1 = TLI.LowerOperation(Result, DAG);
1270 if (Tmp1.Val) Result = Tmp1;
1272 case TargetLowering::Expand:
1273 // Expand brcond's setcc into its constituent parts and create a BR_CC
1275 if (Tmp2.getOpcode() == ISD::SETCC) {
1276 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1277 Tmp2.getOperand(0), Tmp2.getOperand(1),
1278 Node->getOperand(2));
1280 // Make sure the condition is either zero or one. It may have been
1281 // promoted from something else.
1282 unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType());
1283 if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1))
1284 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1286 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1287 DAG.getCondCode(ISD::SETNE), Tmp2,
1288 DAG.getConstant(0, Tmp2.getValueType()),
1289 Node->getOperand(2));
1295 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1296 // Ensure that libcalls are emitted before a branch.
1297 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1298 Tmp1 = LegalizeOp(Tmp1);
1299 LastCALLSEQ_END = DAG.getEntryNode();
1301 Tmp2 = Node->getOperand(2); // LHS
1302 Tmp3 = Node->getOperand(3); // RHS
1303 Tmp4 = Node->getOperand(1); // CC
1305 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1307 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1308 // the LHS is a legal SETCC itself. In this case, we need to compare
1309 // the result against zero to select between true and false values.
1310 if (Tmp3.Val == 0) {
1311 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1312 Tmp4 = DAG.getCondCode(ISD::SETNE);
1315 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1316 Node->getOperand(4));
1318 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1319 default: assert(0 && "Unexpected action for BR_CC!");
1320 case TargetLowering::Legal: break;
1321 case TargetLowering::Custom:
1322 Tmp4 = TLI.LowerOperation(Result, DAG);
1323 if (Tmp4.Val) Result = Tmp4;
1328 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1329 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1331 MVT::ValueType VT = Node->getValueType(0);
1332 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1333 Tmp3 = Result.getValue(0);
1334 Tmp4 = Result.getValue(1);
1336 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1337 default: assert(0 && "This action is not supported yet!");
1338 case TargetLowering::Legal: break;
1339 case TargetLowering::Custom:
1340 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1342 Tmp3 = LegalizeOp(Tmp1);
1343 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1346 case TargetLowering::Promote: {
1347 // Only promote a load of vector type to another.
1348 assert(MVT::isVector(VT) && "Cannot promote this load!");
1349 // Change base type to a different vector type.
1350 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1352 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, Node->getOperand(2));
1353 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1354 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1358 // Since loads produce two values, make sure to remember that we
1359 // legalized both of them.
1360 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1361 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1362 return Op.ResNo ? Tmp4 : Tmp3;
1366 case ISD::ZEXTLOAD: {
1367 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1368 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1370 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
1371 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
1372 default: assert(0 && "This action is not supported yet!");
1373 case TargetLowering::Promote:
1374 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
1375 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1376 DAG.getValueType(MVT::i8));
1377 Tmp1 = Result.getValue(0);
1378 Tmp2 = Result.getValue(1);
1380 case TargetLowering::Custom:
1383 case TargetLowering::Legal:
1384 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1385 Node->getOperand(3));
1386 Tmp1 = Result.getValue(0);
1387 Tmp2 = Result.getValue(1);
1390 Tmp3 = TLI.LowerOperation(Tmp3, DAG);
1392 Tmp1 = LegalizeOp(Tmp3);
1393 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1397 case TargetLowering::Expand:
1398 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1399 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1400 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
1401 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1402 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1403 Tmp2 = LegalizeOp(Load.getValue(1));
1406 assert(Node->getOpcode() != ISD::EXTLOAD &&
1407 "EXTLOAD should always be supported!");
1408 // Turn the unsupported load into an EXTLOAD followed by an explicit
1409 // zero/sign extend inreg.
1410 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1411 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1413 if (Node->getOpcode() == ISD::SEXTLOAD)
1414 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1415 Result, DAG.getValueType(SrcVT));
1417 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1418 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1419 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1422 // Since loads produce two values, make sure to remember that we legalized
1424 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1425 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1426 return Op.ResNo ? Tmp2 : Tmp1;
1428 case ISD::EXTRACT_ELEMENT: {
1429 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1430 switch (getTypeAction(OpTy)) {
1431 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1433 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1435 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1436 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1437 TLI.getShiftAmountTy()));
1438 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1441 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1442 Node->getOperand(0));
1446 // Get both the low and high parts.
1447 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1448 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1449 Result = Tmp2; // 1 -> Hi
1451 Result = Tmp1; // 0 -> Lo
1457 case ISD::CopyToReg:
1458 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1460 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1461 "Register type must be legal!");
1462 // Legalize the incoming value (must be a legal type).
1463 Tmp2 = LegalizeOp(Node->getOperand(2));
1464 if (Node->getNumValues() == 1) {
1465 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1467 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1468 if (Node->getNumOperands() == 4) {
1469 Tmp3 = LegalizeOp(Node->getOperand(3));
1470 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1473 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1476 // Since this produces two values, make sure to remember that we legalized
1478 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1479 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1485 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1487 // Ensure that libcalls are emitted before a return.
1488 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1489 Tmp1 = LegalizeOp(Tmp1);
1490 LastCALLSEQ_END = DAG.getEntryNode();
1492 switch (Node->getNumOperands()) {
1494 Tmp2 = Node->getOperand(1);
1495 Tmp3 = Node->getOperand(2); // Signness
1496 switch (getTypeAction(Tmp2.getValueType())) {
1498 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1501 if (Tmp2.getValueType() != MVT::Vector) {
1503 ExpandOp(Tmp2, Lo, Hi);
1504 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1506 SDNode *InVal = Tmp2.Val;
1508 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1509 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1511 // Figure out if there is a Packed type corresponding to this Vector
1512 // type. If so, convert to the packed type.
1513 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1514 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1515 // Turn this into a return of the packed type.
1516 Tmp2 = PackVectorOp(Tmp2, TVT);
1517 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1518 } else if (NumElems == 1) {
1519 // Turn this into a return of the scalar type.
1520 Tmp2 = PackVectorOp(Tmp2, EVT);
1521 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1523 // FIXME: Returns of gcc generic vectors smaller than a legal type
1524 // should be returned in integer registers!
1526 // The scalarized value type may not be legal, e.g. it might require
1527 // promotion or expansion. Relegalize the return.
1528 Result = LegalizeOp(Result);
1530 // FIXME: Returns of gcc generic vectors larger than a legal vector
1531 // type should be returned by reference!
1533 SplitVectorOp(Tmp2, Lo, Hi);
1534 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1535 Result = LegalizeOp(Result);
1540 Tmp2 = PromoteOp(Node->getOperand(1));
1541 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1542 Result = LegalizeOp(Result);
1547 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1549 default: { // ret <values>
1550 SmallVector<SDOperand, 8> NewValues;
1551 NewValues.push_back(Tmp1);
1552 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1553 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1555 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1556 NewValues.push_back(Node->getOperand(i+1));
1560 assert(Node->getOperand(i).getValueType() != MVT::Vector &&
1561 "FIXME: TODO: implement returning non-legal vector types!");
1562 ExpandOp(Node->getOperand(i), Lo, Hi);
1563 NewValues.push_back(Lo);
1564 NewValues.push_back(Node->getOperand(i+1));
1565 NewValues.push_back(Hi);
1566 NewValues.push_back(Node->getOperand(i+1));
1570 assert(0 && "Can't promote multiple return value yet!");
1573 if (NewValues.size() == Node->getNumOperands())
1574 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1576 Result = DAG.getNode(ISD::RET, MVT::Other,
1577 &NewValues[0], NewValues.size());
1582 if (Result.getOpcode() == ISD::RET) {
1583 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1584 default: assert(0 && "This action is not supported yet!");
1585 case TargetLowering::Legal: break;
1586 case TargetLowering::Custom:
1587 Tmp1 = TLI.LowerOperation(Result, DAG);
1588 if (Tmp1.Val) Result = Tmp1;
1594 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1595 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1597 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1598 // FIXME: We shouldn't do this for TargetConstantFP's.
1599 // FIXME: move this to the DAG Combiner!
1600 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1601 if (CFP->getValueType(0) == MVT::f32) {
1602 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1604 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1605 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1607 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1608 Node->getOperand(3));
1612 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1614 Tmp3 = LegalizeOp(Node->getOperand(1));
1615 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1616 Node->getOperand(3));
1618 MVT::ValueType VT = Tmp3.getValueType();
1619 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1620 default: assert(0 && "This action is not supported yet!");
1621 case TargetLowering::Legal: break;
1622 case TargetLowering::Custom:
1623 Tmp1 = TLI.LowerOperation(Result, DAG);
1624 if (Tmp1.Val) Result = Tmp1;
1626 case TargetLowering::Promote:
1627 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1628 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1629 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1630 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1631 Node->getOperand(3));
1637 // Truncate the value and store the result.
1638 Tmp3 = PromoteOp(Node->getOperand(1));
1639 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1640 Node->getOperand(3),
1641 DAG.getValueType(Node->getOperand(1).getValueType()));
1645 unsigned IncrementSize = 0;
1648 // If this is a vector type, then we have to calculate the increment as
1649 // the product of the element size in bytes, and the number of elements
1650 // in the high half of the vector.
1651 if (Node->getOperand(1).getValueType() == MVT::Vector) {
1652 SDNode *InVal = Node->getOperand(1).Val;
1654 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1655 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1657 // Figure out if there is a Packed type corresponding to this Vector
1658 // type. If so, convert to the packed type.
1659 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1660 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1661 // Turn this into a normal store of the packed type.
1662 Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1663 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1664 Node->getOperand(3));
1665 Result = LegalizeOp(Result);
1667 } else if (NumElems == 1) {
1668 // Turn this into a normal store of the scalar type.
1669 Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1670 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1671 Node->getOperand(3));
1672 // The scalarized value type may not be legal, e.g. it might require
1673 // promotion or expansion. Relegalize the scalar store.
1674 Result = LegalizeOp(Result);
1677 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1678 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1681 ExpandOp(Node->getOperand(1), Lo, Hi);
1682 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1684 if (!TLI.isLittleEndian())
1688 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1689 Node->getOperand(3));
1690 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1691 getIntPtrConstant(IncrementSize));
1692 assert(isTypeLegal(Tmp2.getValueType()) &&
1693 "Pointers must be legal!");
1694 // FIXME: This sets the srcvalue of both halves to be the same, which is
1696 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1697 Node->getOperand(3));
1698 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1704 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1705 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1707 case ISD::STACKSAVE:
1708 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1709 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1710 Tmp1 = Result.getValue(0);
1711 Tmp2 = Result.getValue(1);
1713 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1714 default: assert(0 && "This action is not supported yet!");
1715 case TargetLowering::Legal: break;
1716 case TargetLowering::Custom:
1717 Tmp3 = TLI.LowerOperation(Result, DAG);
1719 Tmp1 = LegalizeOp(Tmp3);
1720 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1723 case TargetLowering::Expand:
1724 // Expand to CopyFromReg if the target set
1725 // StackPointerRegisterToSaveRestore.
1726 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1727 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1728 Node->getValueType(0));
1729 Tmp2 = Tmp1.getValue(1);
1731 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1732 Tmp2 = Node->getOperand(0);
1737 // Since stacksave produce two values, make sure to remember that we
1738 // legalized both of them.
1739 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1740 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1741 return Op.ResNo ? Tmp2 : Tmp1;
1743 case ISD::STACKRESTORE:
1744 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1745 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1746 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1748 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1749 default: assert(0 && "This action is not supported yet!");
1750 case TargetLowering::Legal: break;
1751 case TargetLowering::Custom:
1752 Tmp1 = TLI.LowerOperation(Result, DAG);
1753 if (Tmp1.Val) Result = Tmp1;
1755 case TargetLowering::Expand:
1756 // Expand to CopyToReg if the target set
1757 // StackPointerRegisterToSaveRestore.
1758 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1759 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1767 case ISD::READCYCLECOUNTER:
1768 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1769 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1771 // Since rdcc produce two values, make sure to remember that we legalized
1773 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1774 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1777 case ISD::TRUNCSTORE: {
1778 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1779 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1781 assert(isTypeLegal(Node->getOperand(1).getValueType()) &&
1782 "Cannot handle illegal TRUNCSTORE yet!");
1783 Tmp2 = LegalizeOp(Node->getOperand(1));
1785 // The only promote case we handle is TRUNCSTORE:i1 X into
1786 // -> TRUNCSTORE:i8 (and X, 1)
1787 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1788 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1789 TargetLowering::Promote) {
1790 // Promote the bool to a mask then store.
1791 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1792 DAG.getConstant(1, Tmp2.getValueType()));
1793 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1794 Node->getOperand(3), DAG.getValueType(MVT::i8));
1796 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1797 Tmp3 != Node->getOperand(2)) {
1798 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
1799 Node->getOperand(3), Node->getOperand(4));
1802 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT();
1803 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) {
1804 default: assert(0 && "This action is not supported yet!");
1805 case TargetLowering::Legal: break;
1806 case TargetLowering::Custom:
1807 Tmp1 = TLI.LowerOperation(Result, DAG);
1808 if (Tmp1.Val) Result = Tmp1;
1814 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1815 case Expand: assert(0 && "It's impossible to expand bools");
1817 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1820 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1823 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1824 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1826 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1828 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1829 default: assert(0 && "This action is not supported yet!");
1830 case TargetLowering::Legal: break;
1831 case TargetLowering::Custom: {
1832 Tmp1 = TLI.LowerOperation(Result, DAG);
1833 if (Tmp1.Val) Result = Tmp1;
1836 case TargetLowering::Expand:
1837 if (Tmp1.getOpcode() == ISD::SETCC) {
1838 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1840 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1842 // Make sure the condition is either zero or one. It may have been
1843 // promoted from something else.
1844 unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType());
1845 if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1))
1846 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1847 Result = DAG.getSelectCC(Tmp1,
1848 DAG.getConstant(0, Tmp1.getValueType()),
1849 Tmp2, Tmp3, ISD::SETNE);
1852 case TargetLowering::Promote: {
1853 MVT::ValueType NVT =
1854 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1855 unsigned ExtOp, TruncOp;
1856 if (MVT::isVector(Tmp2.getValueType())) {
1857 ExtOp = ISD::BIT_CONVERT;
1858 TruncOp = ISD::BIT_CONVERT;
1859 } else if (MVT::isInteger(Tmp2.getValueType())) {
1860 ExtOp = ISD::ANY_EXTEND;
1861 TruncOp = ISD::TRUNCATE;
1863 ExtOp = ISD::FP_EXTEND;
1864 TruncOp = ISD::FP_ROUND;
1866 // Promote each of the values to the new type.
1867 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1868 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1869 // Perform the larger operation, then round down.
1870 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1871 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1876 case ISD::SELECT_CC: {
1877 Tmp1 = Node->getOperand(0); // LHS
1878 Tmp2 = Node->getOperand(1); // RHS
1879 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1880 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1881 SDOperand CC = Node->getOperand(4);
1883 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
1885 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1886 // the LHS is a legal SETCC itself. In this case, we need to compare
1887 // the result against zero to select between true and false values.
1888 if (Tmp2.Val == 0) {
1889 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1890 CC = DAG.getCondCode(ISD::SETNE);
1892 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
1894 // Everything is legal, see if we should expand this op or something.
1895 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
1896 default: assert(0 && "This action is not supported yet!");
1897 case TargetLowering::Legal: break;
1898 case TargetLowering::Custom:
1899 Tmp1 = TLI.LowerOperation(Result, DAG);
1900 if (Tmp1.Val) Result = Tmp1;
1906 Tmp1 = Node->getOperand(0);
1907 Tmp2 = Node->getOperand(1);
1908 Tmp3 = Node->getOperand(2);
1909 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
1911 // If we had to Expand the SetCC operands into a SELECT node, then it may
1912 // not always be possible to return a true LHS & RHS. In this case, just
1913 // return the value we legalized, returned in the LHS
1914 if (Tmp2.Val == 0) {
1919 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
1920 default: assert(0 && "Cannot handle this action for SETCC yet!");
1921 case TargetLowering::Custom:
1924 case TargetLowering::Legal:
1925 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1927 Tmp3 = TLI.LowerOperation(Result, DAG);
1928 if (Tmp3.Val) Result = Tmp3;
1931 case TargetLowering::Promote: {
1932 // First step, figure out the appropriate operation to use.
1933 // Allow SETCC to not be supported for all legal data types
1934 // Mostly this targets FP
1935 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1936 MVT::ValueType OldVT = NewInTy;
1938 // Scan for the appropriate larger type to use.
1940 NewInTy = (MVT::ValueType)(NewInTy+1);
1942 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1943 "Fell off of the edge of the integer world");
1944 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1945 "Fell off of the edge of the floating point world");
1947 // If the target supports SETCC of this type, use it.
1948 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
1951 if (MVT::isInteger(NewInTy))
1952 assert(0 && "Cannot promote Legal Integer SETCC yet");
1954 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1955 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
1957 Tmp1 = LegalizeOp(Tmp1);
1958 Tmp2 = LegalizeOp(Tmp2);
1959 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1960 Result = LegalizeOp(Result);
1963 case TargetLowering::Expand:
1964 // Expand a setcc node into a select_cc of the same condition, lhs, and
1965 // rhs that selects between const 1 (true) and const 0 (false).
1966 MVT::ValueType VT = Node->getValueType(0);
1967 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1968 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1969 Node->getOperand(2));
1975 case ISD::MEMMOVE: {
1976 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1977 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1979 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1980 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1981 case Expand: assert(0 && "Cannot expand a byte!");
1983 Tmp3 = LegalizeOp(Node->getOperand(2));
1986 Tmp3 = PromoteOp(Node->getOperand(2));
1990 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1994 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1996 // Length is too big, just take the lo-part of the length.
1998 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
2002 Tmp4 = LegalizeOp(Node->getOperand(3));
2005 Tmp4 = PromoteOp(Node->getOperand(3));
2010 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2011 case Expand: assert(0 && "Cannot expand this yet!");
2013 Tmp5 = LegalizeOp(Node->getOperand(4));
2016 Tmp5 = PromoteOp(Node->getOperand(4));
2020 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2021 default: assert(0 && "This action not implemented for this operation!");
2022 case TargetLowering::Custom:
2025 case TargetLowering::Legal:
2026 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2028 Tmp1 = TLI.LowerOperation(Result, DAG);
2029 if (Tmp1.Val) Result = Tmp1;
2032 case TargetLowering::Expand: {
2033 // Otherwise, the target does not support this operation. Lower the
2034 // operation to an explicit libcall as appropriate.
2035 MVT::ValueType IntPtr = TLI.getPointerTy();
2036 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2037 std::vector<std::pair<SDOperand, const Type*> > Args;
2039 const char *FnName = 0;
2040 if (Node->getOpcode() == ISD::MEMSET) {
2041 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2042 // Extend the (previously legalized) ubyte argument to be an int value
2044 if (Tmp3.getValueType() > MVT::i32)
2045 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2047 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2048 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
2049 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2052 } else if (Node->getOpcode() == ISD::MEMCPY ||
2053 Node->getOpcode() == ISD::MEMMOVE) {
2054 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2055 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
2056 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2057 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2059 assert(0 && "Unknown op!");
2062 std::pair<SDOperand,SDOperand> CallResult =
2063 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
2064 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2065 Result = CallResult.second;
2072 case ISD::SHL_PARTS:
2073 case ISD::SRA_PARTS:
2074 case ISD::SRL_PARTS: {
2075 SmallVector<SDOperand, 8> Ops;
2076 bool Changed = false;
2077 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2078 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2079 Changed |= Ops.back() != Node->getOperand(i);
2082 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2084 switch (TLI.getOperationAction(Node->getOpcode(),
2085 Node->getValueType(0))) {
2086 default: assert(0 && "This action is not supported yet!");
2087 case TargetLowering::Legal: break;
2088 case TargetLowering::Custom:
2089 Tmp1 = TLI.LowerOperation(Result, DAG);
2091 SDOperand Tmp2, RetVal(0, 0);
2092 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2093 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2094 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2098 assert(RetVal.Val && "Illegal result number");
2104 // Since these produce multiple values, make sure to remember that we
2105 // legalized all of them.
2106 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2107 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2108 return Result.getValue(Op.ResNo);
2129 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2130 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2131 case Expand: assert(0 && "Not possible");
2133 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2136 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2140 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2142 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2143 default: assert(0 && "BinOp legalize operation not supported");
2144 case TargetLowering::Legal: break;
2145 case TargetLowering::Custom:
2146 Tmp1 = TLI.LowerOperation(Result, DAG);
2147 if (Tmp1.Val) Result = Tmp1;
2149 case TargetLowering::Expand: {
2150 assert(MVT::isVector(Node->getValueType(0)) &&
2151 "Cannot expand this binary operator!");
2152 // Expand the operation into a bunch of nasty scalar code.
2153 SmallVector<SDOperand, 8> Ops;
2154 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
2155 MVT::ValueType PtrVT = TLI.getPointerTy();
2156 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2158 SDOperand Idx = DAG.getConstant(i, PtrVT);
2159 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2160 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2161 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2163 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2164 &Ops[0], Ops.size());
2167 case TargetLowering::Promote: {
2168 switch (Node->getOpcode()) {
2169 default: assert(0 && "Do not know how to promote this BinOp!");
2173 MVT::ValueType OVT = Node->getValueType(0);
2174 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2175 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2176 // Bit convert each of the values to the new type.
2177 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2178 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2179 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2180 // Bit convert the result back the original type.
2181 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2189 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2190 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2191 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2192 case Expand: assert(0 && "Not possible");
2194 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2197 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2201 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2203 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2204 default: assert(0 && "Operation not supported");
2205 case TargetLowering::Custom:
2206 Tmp1 = TLI.LowerOperation(Result, DAG);
2207 if (Tmp1.Val) Result = Tmp1;
2209 case TargetLowering::Legal: break;
2210 case TargetLowering::Expand:
2211 // If this target supports fabs/fneg natively, do this efficiently.
2212 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
2213 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
2214 // Get the sign bit of the RHS.
2215 MVT::ValueType IVT =
2216 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2217 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2218 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2219 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2220 // Get the absolute value of the result.
2221 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2222 // Select between the nabs and abs value based on the sign bit of
2224 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2225 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2228 Result = LegalizeOp(Result);
2232 // Otherwise, do bitwise ops!
2234 // copysign -> copysignf/copysign libcall.
2236 if (Node->getValueType(0) == MVT::f32) {
2237 FnName = "copysignf";
2238 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type.
2239 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2240 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2));
2242 FnName = "copysign";
2243 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type.
2244 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2245 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2));
2248 Result = ExpandLibCall(FnName, Node, Dummy);
2255 Tmp1 = LegalizeOp(Node->getOperand(0));
2256 Tmp2 = LegalizeOp(Node->getOperand(1));
2257 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2258 // Since this produces two values, make sure to remember that we legalized
2260 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2261 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2266 Tmp1 = LegalizeOp(Node->getOperand(0));
2267 Tmp2 = LegalizeOp(Node->getOperand(1));
2268 Tmp3 = LegalizeOp(Node->getOperand(2));
2269 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2270 // Since this produces two values, make sure to remember that we legalized
2272 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2273 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2276 case ISD::BUILD_PAIR: {
2277 MVT::ValueType PairTy = Node->getValueType(0);
2278 // TODO: handle the case where the Lo and Hi operands are not of legal type
2279 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2280 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2281 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2282 case TargetLowering::Promote:
2283 case TargetLowering::Custom:
2284 assert(0 && "Cannot promote/custom this yet!");
2285 case TargetLowering::Legal:
2286 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2287 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2289 case TargetLowering::Expand:
2290 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2291 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2292 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2293 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2294 TLI.getShiftAmountTy()));
2295 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2304 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2305 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2307 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2308 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2309 case TargetLowering::Custom:
2312 case TargetLowering::Legal:
2313 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2315 Tmp1 = TLI.LowerOperation(Result, DAG);
2316 if (Tmp1.Val) Result = Tmp1;
2319 case TargetLowering::Expand:
2320 if (MVT::isInteger(Node->getValueType(0))) {
2322 MVT::ValueType VT = Node->getValueType(0);
2323 unsigned Opc = Node->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
2324 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
2325 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2326 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2328 // Floating point mod -> fmod libcall.
2329 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
2331 Result = ExpandLibCall(FnName, Node, Dummy);
2337 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2338 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2340 MVT::ValueType VT = Node->getValueType(0);
2341 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2342 default: assert(0 && "This action is not supported yet!");
2343 case TargetLowering::Custom:
2346 case TargetLowering::Legal:
2347 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2348 Result = Result.getValue(0);
2349 Tmp1 = Result.getValue(1);
2352 Tmp2 = TLI.LowerOperation(Result, DAG);
2354 Result = LegalizeOp(Tmp2);
2355 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2359 case TargetLowering::Expand: {
2360 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2361 Node->getOperand(2));
2362 // Increment the pointer, VAList, to the next vaarg
2363 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2364 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2365 TLI.getPointerTy()));
2366 // Store the incremented VAList to the legalized pointer
2367 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2,
2368 Node->getOperand(2));
2369 // Load the actual argument out of the pointer VAList
2370 Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0));
2371 Tmp1 = LegalizeOp(Result.getValue(1));
2372 Result = LegalizeOp(Result);
2376 // Since VAARG produces two values, make sure to remember that we
2377 // legalized both of them.
2378 AddLegalizedOperand(SDOperand(Node, 0), Result);
2379 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2380 return Op.ResNo ? Tmp1 : Result;
2384 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2385 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2386 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2388 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2389 default: assert(0 && "This action is not supported yet!");
2390 case TargetLowering::Custom:
2393 case TargetLowering::Legal:
2394 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2395 Node->getOperand(3), Node->getOperand(4));
2397 Tmp1 = TLI.LowerOperation(Result, DAG);
2398 if (Tmp1.Val) Result = Tmp1;
2401 case TargetLowering::Expand:
2402 // This defaults to loading a pointer from the input and storing it to the
2403 // output, returning the chain.
2404 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, Node->getOperand(3));
2405 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp4.getValue(1), Tmp4, Tmp2,
2406 Node->getOperand(4));
2412 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2413 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2415 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2416 default: assert(0 && "This action is not supported yet!");
2417 case TargetLowering::Custom:
2420 case TargetLowering::Legal:
2421 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2423 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2424 if (Tmp1.Val) Result = Tmp1;
2427 case TargetLowering::Expand:
2428 Result = Tmp1; // Default to a no-op, return the chain
2434 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2435 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2437 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2439 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2440 default: assert(0 && "This action is not supported yet!");
2441 case TargetLowering::Legal: break;
2442 case TargetLowering::Custom:
2443 Tmp1 = TLI.LowerOperation(Result, DAG);
2444 if (Tmp1.Val) Result = Tmp1;
2451 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2452 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2454 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2455 "Cannot handle this yet!");
2456 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2460 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2461 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2462 case TargetLowering::Custom:
2463 assert(0 && "Cannot custom legalize this yet!");
2464 case TargetLowering::Legal:
2465 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2467 case TargetLowering::Promote: {
2468 MVT::ValueType OVT = Tmp1.getValueType();
2469 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2470 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2472 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2473 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2474 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2475 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2478 case TargetLowering::Expand:
2479 Result = ExpandBSWAP(Tmp1);
2487 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2488 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2489 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2490 case TargetLowering::Legal:
2491 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2493 case TargetLowering::Promote: {
2494 MVT::ValueType OVT = Tmp1.getValueType();
2495 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2497 // Zero extend the argument.
2498 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2499 // Perform the larger operation, then subtract if needed.
2500 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2501 switch (Node->getOpcode()) {
2506 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2507 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2508 DAG.getConstant(getSizeInBits(NVT), NVT),
2510 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2511 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2514 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2515 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2516 DAG.getConstant(getSizeInBits(NVT) -
2517 getSizeInBits(OVT), NVT));
2522 case TargetLowering::Expand:
2523 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2534 Tmp1 = LegalizeOp(Node->getOperand(0));
2535 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2536 case TargetLowering::Promote:
2537 case TargetLowering::Custom:
2540 case TargetLowering::Legal:
2541 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2543 Tmp1 = TLI.LowerOperation(Result, DAG);
2544 if (Tmp1.Val) Result = Tmp1;
2547 case TargetLowering::Expand:
2548 switch (Node->getOpcode()) {
2549 default: assert(0 && "Unreachable!");
2551 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2552 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2553 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2556 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2557 MVT::ValueType VT = Node->getValueType(0);
2558 Tmp2 = DAG.getConstantFP(0.0, VT);
2559 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2560 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2561 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2567 MVT::ValueType VT = Node->getValueType(0);
2568 const char *FnName = 0;
2569 switch(Node->getOpcode()) {
2570 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2571 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2572 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2573 default: assert(0 && "Unreachable!");
2576 Result = ExpandLibCall(FnName, Node, Dummy);
2584 case ISD::BIT_CONVERT:
2585 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2586 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2588 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2589 Node->getOperand(0).getValueType())) {
2590 default: assert(0 && "Unknown operation action!");
2591 case TargetLowering::Expand:
2592 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2594 case TargetLowering::Legal:
2595 Tmp1 = LegalizeOp(Node->getOperand(0));
2596 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2601 case ISD::VBIT_CONVERT: {
2602 assert(Op.getOperand(0).getValueType() == MVT::Vector &&
2603 "Can only have VBIT_CONVERT where input or output is MVT::Vector!");
2605 // The input has to be a vector type, we have to either scalarize it, pack
2606 // it, or convert it based on whether the input vector type is legal.
2607 SDNode *InVal = Node->getOperand(0).Val;
2609 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
2610 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
2612 // Figure out if there is a Packed type corresponding to this Vector
2613 // type. If so, convert to the packed type.
2614 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2615 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
2616 // Turn this into a bit convert of the packed input.
2617 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2618 PackVectorOp(Node->getOperand(0), TVT));
2620 } else if (NumElems == 1) {
2621 // Turn this into a bit convert of the scalar input.
2622 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2623 PackVectorOp(Node->getOperand(0), EVT));
2626 // FIXME: UNIMP! Store then reload
2627 assert(0 && "Cast from unsupported vector type not implemented yet!");
2631 // Conversion operators. The source and destination have different types.
2632 case ISD::SINT_TO_FP:
2633 case ISD::UINT_TO_FP: {
2634 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2635 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2637 switch (TLI.getOperationAction(Node->getOpcode(),
2638 Node->getOperand(0).getValueType())) {
2639 default: assert(0 && "Unknown operation action!");
2640 case TargetLowering::Custom:
2643 case TargetLowering::Legal:
2644 Tmp1 = LegalizeOp(Node->getOperand(0));
2645 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2647 Tmp1 = TLI.LowerOperation(Result, DAG);
2648 if (Tmp1.Val) Result = Tmp1;
2651 case TargetLowering::Expand:
2652 Result = ExpandLegalINT_TO_FP(isSigned,
2653 LegalizeOp(Node->getOperand(0)),
2654 Node->getValueType(0));
2656 case TargetLowering::Promote:
2657 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2658 Node->getValueType(0),
2664 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2665 Node->getValueType(0), Node->getOperand(0));
2668 Tmp1 = PromoteOp(Node->getOperand(0));
2670 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2671 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2673 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2674 Node->getOperand(0).getValueType());
2676 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2677 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2683 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2685 Tmp1 = LegalizeOp(Node->getOperand(0));
2686 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2689 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2691 // Since the result is legal, we should just be able to truncate the low
2692 // part of the source.
2693 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2696 Result = PromoteOp(Node->getOperand(0));
2697 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2702 case ISD::FP_TO_SINT:
2703 case ISD::FP_TO_UINT:
2704 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2706 Tmp1 = LegalizeOp(Node->getOperand(0));
2708 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2709 default: assert(0 && "Unknown operation action!");
2710 case TargetLowering::Custom:
2713 case TargetLowering::Legal:
2714 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2716 Tmp1 = TLI.LowerOperation(Result, DAG);
2717 if (Tmp1.Val) Result = Tmp1;
2720 case TargetLowering::Promote:
2721 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2722 Node->getOpcode() == ISD::FP_TO_SINT);
2724 case TargetLowering::Expand:
2725 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2726 SDOperand True, False;
2727 MVT::ValueType VT = Node->getOperand(0).getValueType();
2728 MVT::ValueType NVT = Node->getValueType(0);
2729 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2730 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2731 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2732 Node->getOperand(0), Tmp2, ISD::SETLT);
2733 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2734 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2735 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2737 False = DAG.getNode(ISD::XOR, NVT, False,
2738 DAG.getConstant(1ULL << ShiftAmt, NVT));
2739 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2742 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2748 assert(0 && "Shouldn't need to expand other operators here!");
2750 Tmp1 = PromoteOp(Node->getOperand(0));
2751 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
2752 Result = LegalizeOp(Result);
2757 case ISD::ANY_EXTEND:
2758 case ISD::ZERO_EXTEND:
2759 case ISD::SIGN_EXTEND:
2760 case ISD::FP_EXTEND:
2762 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2763 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
2765 Tmp1 = LegalizeOp(Node->getOperand(0));
2766 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2769 switch (Node->getOpcode()) {
2770 case ISD::ANY_EXTEND:
2771 Tmp1 = PromoteOp(Node->getOperand(0));
2772 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
2774 case ISD::ZERO_EXTEND:
2775 Result = PromoteOp(Node->getOperand(0));
2776 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2777 Result = DAG.getZeroExtendInReg(Result,
2778 Node->getOperand(0).getValueType());
2780 case ISD::SIGN_EXTEND:
2781 Result = PromoteOp(Node->getOperand(0));
2782 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2783 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2785 DAG.getValueType(Node->getOperand(0).getValueType()));
2787 case ISD::FP_EXTEND:
2788 Result = PromoteOp(Node->getOperand(0));
2789 if (Result.getValueType() != Op.getValueType())
2790 // Dynamically dead while we have only 2 FP types.
2791 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2794 Result = PromoteOp(Node->getOperand(0));
2795 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2800 case ISD::FP_ROUND_INREG:
2801 case ISD::SIGN_EXTEND_INREG: {
2802 Tmp1 = LegalizeOp(Node->getOperand(0));
2803 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2805 // If this operation is not supported, convert it to a shl/shr or load/store
2807 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2808 default: assert(0 && "This action not supported for this op yet!");
2809 case TargetLowering::Legal:
2810 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2812 case TargetLowering::Expand:
2813 // If this is an integer extend and shifts are supported, do that.
2814 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2815 // NOTE: we could fall back on load/store here too for targets without
2816 // SAR. However, it is doubtful that any exist.
2817 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2818 MVT::getSizeInBits(ExtraVT);
2819 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2820 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2821 Node->getOperand(0), ShiftCst);
2822 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2824 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2825 // The only way we can lower this is to turn it into a STORETRUNC,
2826 // EXTLOAD pair, targetting a temporary location (a stack slot).
2828 // NOTE: there is a choice here between constantly creating new stack
2829 // slots and always reusing the same one. We currently always create
2830 // new ones, as reuse may inhibit scheduling.
2831 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2832 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty);
2833 unsigned Align = TLI.getTargetData()->getTypeAlignment(Ty);
2834 MachineFunction &MF = DAG.getMachineFunction();
2836 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2837 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2838 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2839 Node->getOperand(0), StackSlot,
2840 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2841 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2842 Result, StackSlot, DAG.getSrcValue(NULL),
2845 assert(0 && "Unknown op");
2853 assert(Result.getValueType() == Op.getValueType() &&
2854 "Bad legalization!");
2856 // Make sure that the generated code is itself legal.
2858 Result = LegalizeOp(Result);
2860 // Note that LegalizeOp may be reentered even from single-use nodes, which
2861 // means that we always must cache transformed nodes.
2862 AddLegalizedOperand(Op, Result);
2866 /// PromoteOp - Given an operation that produces a value in an invalid type,
2867 /// promote it to compute the value into a larger type. The produced value will
2868 /// have the correct bits for the low portion of the register, but no guarantee
2869 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2870 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2871 MVT::ValueType VT = Op.getValueType();
2872 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2873 assert(getTypeAction(VT) == Promote &&
2874 "Caller should expand or legalize operands that are not promotable!");
2875 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2876 "Cannot promote to smaller type!");
2878 SDOperand Tmp1, Tmp2, Tmp3;
2880 SDNode *Node = Op.Val;
2882 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2883 if (I != PromotedNodes.end()) return I->second;
2885 switch (Node->getOpcode()) {
2886 case ISD::CopyFromReg:
2887 assert(0 && "CopyFromReg must be legal!");
2890 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2892 assert(0 && "Do not know how to promote this operator!");
2895 Result = DAG.getNode(ISD::UNDEF, NVT);
2899 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2901 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2902 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2904 case ISD::ConstantFP:
2905 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2906 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2910 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2911 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2912 Node->getOperand(1), Node->getOperand(2));
2916 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2918 Result = LegalizeOp(Node->getOperand(0));
2919 assert(Result.getValueType() >= NVT &&
2920 "This truncation doesn't make sense!");
2921 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2922 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2925 // The truncation is not required, because we don't guarantee anything
2926 // about high bits anyway.
2927 Result = PromoteOp(Node->getOperand(0));
2930 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2931 // Truncate the low part of the expanded value to the result type
2932 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2935 case ISD::SIGN_EXTEND:
2936 case ISD::ZERO_EXTEND:
2937 case ISD::ANY_EXTEND:
2938 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2939 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2941 // Input is legal? Just do extend all the way to the larger type.
2942 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2945 // Promote the reg if it's smaller.
2946 Result = PromoteOp(Node->getOperand(0));
2947 // The high bits are not guaranteed to be anything. Insert an extend.
2948 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2949 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2950 DAG.getValueType(Node->getOperand(0).getValueType()));
2951 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2952 Result = DAG.getZeroExtendInReg(Result,
2953 Node->getOperand(0).getValueType());
2957 case ISD::BIT_CONVERT:
2958 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2959 Result = PromoteOp(Result);
2962 case ISD::FP_EXTEND:
2963 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2965 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2966 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2967 case Promote: assert(0 && "Unreachable with 2 FP types!");
2969 // Input is legal? Do an FP_ROUND_INREG.
2970 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
2971 DAG.getValueType(VT));
2976 case ISD::SINT_TO_FP:
2977 case ISD::UINT_TO_FP:
2978 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2980 // No extra round required here.
2981 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2985 Result = PromoteOp(Node->getOperand(0));
2986 if (Node->getOpcode() == ISD::SINT_TO_FP)
2987 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2989 DAG.getValueType(Node->getOperand(0).getValueType()));
2991 Result = DAG.getZeroExtendInReg(Result,
2992 Node->getOperand(0).getValueType());
2993 // No extra round required here.
2994 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2997 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
2998 Node->getOperand(0));
2999 // Round if we cannot tolerate excess precision.
3000 if (NoExcessFPPrecision)
3001 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3002 DAG.getValueType(VT));
3007 case ISD::SIGN_EXTEND_INREG:
3008 Result = PromoteOp(Node->getOperand(0));
3009 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3010 Node->getOperand(1));
3012 case ISD::FP_TO_SINT:
3013 case ISD::FP_TO_UINT:
3014 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3016 Tmp1 = Node->getOperand(0);
3019 // The input result is prerounded, so we don't have to do anything
3021 Tmp1 = PromoteOp(Node->getOperand(0));
3024 assert(0 && "not implemented");
3026 // If we're promoting a UINT to a larger size, check to see if the new node
3027 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3028 // we can use that instead. This allows us to generate better code for
3029 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3030 // legal, such as PowerPC.
3031 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3032 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3033 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3034 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3035 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3037 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3043 Tmp1 = PromoteOp(Node->getOperand(0));
3044 assert(Tmp1.getValueType() == NVT);
3045 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3046 // NOTE: we do not have to do any extra rounding here for
3047 // NoExcessFPPrecision, because we know the input will have the appropriate
3048 // precision, and these operations don't modify precision at all.
3054 Tmp1 = PromoteOp(Node->getOperand(0));
3055 assert(Tmp1.getValueType() == NVT);
3056 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3057 if (NoExcessFPPrecision)
3058 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3059 DAG.getValueType(VT));
3068 // The input may have strange things in the top bits of the registers, but
3069 // these operations don't care. They may have weird bits going out, but
3070 // that too is okay if they are integer operations.
3071 Tmp1 = PromoteOp(Node->getOperand(0));
3072 Tmp2 = PromoteOp(Node->getOperand(1));
3073 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3074 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3079 Tmp1 = PromoteOp(Node->getOperand(0));
3080 Tmp2 = PromoteOp(Node->getOperand(1));
3081 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3082 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3084 // Floating point operations will give excess precision that we may not be
3085 // able to tolerate. If we DO allow excess precision, just leave it,
3086 // otherwise excise it.
3087 // FIXME: Why would we need to round FP ops more than integer ones?
3088 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3089 if (NoExcessFPPrecision)
3090 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3091 DAG.getValueType(VT));
3096 // These operators require that their input be sign extended.
3097 Tmp1 = PromoteOp(Node->getOperand(0));
3098 Tmp2 = PromoteOp(Node->getOperand(1));
3099 if (MVT::isInteger(NVT)) {
3100 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3101 DAG.getValueType(VT));
3102 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3103 DAG.getValueType(VT));
3105 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3107 // Perform FP_ROUND: this is probably overly pessimistic.
3108 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3109 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3110 DAG.getValueType(VT));
3114 case ISD::FCOPYSIGN:
3115 // These operators require that their input be fp extended.
3116 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3118 Tmp1 = LegalizeOp(Node->getOperand(0));
3121 Tmp1 = PromoteOp(Node->getOperand(0));
3124 assert(0 && "not implemented");
3126 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3128 Tmp2 = LegalizeOp(Node->getOperand(1));
3131 Tmp2 = PromoteOp(Node->getOperand(1));
3134 assert(0 && "not implemented");
3136 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3138 // Perform FP_ROUND: this is probably overly pessimistic.
3139 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3140 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3141 DAG.getValueType(VT));
3146 // These operators require that their input be zero extended.
3147 Tmp1 = PromoteOp(Node->getOperand(0));
3148 Tmp2 = PromoteOp(Node->getOperand(1));
3149 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3150 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3151 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3152 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3156 Tmp1 = PromoteOp(Node->getOperand(0));
3157 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3160 // The input value must be properly sign extended.
3161 Tmp1 = PromoteOp(Node->getOperand(0));
3162 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3163 DAG.getValueType(VT));
3164 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3167 // The input value must be properly zero extended.
3168 Tmp1 = PromoteOp(Node->getOperand(0));
3169 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3170 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3174 Tmp1 = Node->getOperand(0); // Get the chain.
3175 Tmp2 = Node->getOperand(1); // Get the pointer.
3176 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3177 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3178 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3180 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3181 Node->getOperand(2));
3182 // Increment the pointer, VAList, to the next vaarg
3183 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3184 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3185 TLI.getPointerTy()));
3186 // Store the incremented VAList to the legalized pointer
3187 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2,
3188 Node->getOperand(2));
3189 // Load the actual argument out of the pointer VAList
3190 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList,
3191 DAG.getSrcValue(0), VT);
3193 // Remember that we legalized the chain.
3194 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3198 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Node->getOperand(0),
3199 Node->getOperand(1), Node->getOperand(2), VT);
3200 // Remember that we legalized the chain.
3201 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3206 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Node->getOperand(0),
3207 Node->getOperand(1), Node->getOperand(2),
3208 cast<VTSDNode>(Node->getOperand(3))->getVT());
3209 // Remember that we legalized the chain.
3210 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3213 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3214 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3215 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3217 case ISD::SELECT_CC:
3218 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3219 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3220 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3221 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3224 Tmp1 = Node->getOperand(0);
3225 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3226 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3227 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3228 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
3229 TLI.getShiftAmountTy()));
3234 // Zero extend the argument
3235 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3236 // Perform the larger operation, then subtract if needed.
3237 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3238 switch(Node->getOpcode()) {
3243 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3244 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3245 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
3246 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3247 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
3250 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3251 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3252 DAG.getConstant(getSizeInBits(NVT) -
3253 getSizeInBits(VT), NVT));
3257 case ISD::VEXTRACT_VECTOR_ELT:
3258 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
3260 case ISD::EXTRACT_VECTOR_ELT:
3261 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3265 assert(Result.Val && "Didn't set a result!");
3267 // Make sure the result is itself legal.
3268 Result = LegalizeOp(Result);
3270 // Remember that we promoted this!
3271 AddPromotedOperand(Op, Result);
3275 /// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
3276 /// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
3277 /// on the vector type. The return type of this matches the element type of the
3278 /// vector, which may not be legal for the target.
3279 SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
3280 // We know that operand #0 is the Vec vector. If the index is a constant
3281 // or if the invec is a supported hardware type, we can use it. Otherwise,
3282 // lower to a store then an indexed load.
3283 SDOperand Vec = Op.getOperand(0);
3284 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3286 SDNode *InVal = Vec.Val;
3287 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
3288 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
3290 // Figure out if there is a Packed type corresponding to this Vector
3291 // type. If so, convert to the packed type.
3292 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3293 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
3294 // Turn this into a packed extract_vector_elt operation.
3295 Vec = PackVectorOp(Vec, TVT);
3296 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
3297 } else if (NumElems == 1) {
3298 // This must be an access of the only element. Return it.
3299 return PackVectorOp(Vec, EVT);
3300 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
3302 SplitVectorOp(Vec, Lo, Hi);
3303 if (CIdx->getValue() < NumElems/2) {
3307 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3310 // It's now an extract from the appropriate high or low part. Recurse.
3311 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3312 return LowerVEXTRACT_VECTOR_ELT(Op);
3314 // Variable index case for extract element.
3315 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
3316 assert(0 && "unimp!");
3321 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3323 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3324 SDOperand Vector = Op.getOperand(0);
3325 SDOperand Idx = Op.getOperand(1);
3327 // If the target doesn't support this, store the value to a temporary
3328 // stack slot, then LOAD the scalar element back out.
3329 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
3330 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3331 Vector, StackPtr, DAG.getSrcValue(NULL));
3333 // Add the offset to the index.
3334 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3335 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3336 DAG.getConstant(EltSize, Idx.getValueType()));
3337 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3339 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, DAG.getSrcValue(NULL));
3343 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3344 /// with condition CC on the current target. This usually involves legalizing
3345 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3346 /// there may be no choice but to create a new SetCC node to represent the
3347 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3348 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3349 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3352 SDOperand Tmp1, Tmp2, Result;
3354 switch (getTypeAction(LHS.getValueType())) {
3356 Tmp1 = LegalizeOp(LHS); // LHS
3357 Tmp2 = LegalizeOp(RHS); // RHS
3360 Tmp1 = PromoteOp(LHS); // LHS
3361 Tmp2 = PromoteOp(RHS); // RHS
3363 // If this is an FP compare, the operands have already been extended.
3364 if (MVT::isInteger(LHS.getValueType())) {
3365 MVT::ValueType VT = LHS.getValueType();
3366 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3368 // Otherwise, we have to insert explicit sign or zero extends. Note
3369 // that we could insert sign extends for ALL conditions, but zero extend
3370 // is cheaper on many machines (an AND instead of two shifts), so prefer
3372 switch (cast<CondCodeSDNode>(CC)->get()) {
3373 default: assert(0 && "Unknown integer comparison!");
3380 // ALL of these operations will work if we either sign or zero extend
3381 // the operands (including the unsigned comparisons!). Zero extend is
3382 // usually a simpler/cheaper operation, so prefer it.
3383 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3384 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3390 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3391 DAG.getValueType(VT));
3392 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3393 DAG.getValueType(VT));
3399 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3400 ExpandOp(LHS, LHSLo, LHSHi);
3401 ExpandOp(RHS, RHSLo, RHSHi);
3402 switch (cast<CondCodeSDNode>(CC)->get()) {
3406 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3407 if (RHSCST->isAllOnesValue()) {
3408 // Comparison to -1.
3409 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3414 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3415 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3416 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3417 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3420 // If this is a comparison of the sign bit, just look at the top part.
3422 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3423 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3424 CST->getValue() == 0) || // X < 0
3425 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3426 CST->isAllOnesValue())) { // X > -1
3432 // FIXME: This generated code sucks.
3433 ISD::CondCode LowCC;
3434 switch (cast<CondCodeSDNode>(CC)->get()) {
3435 default: assert(0 && "Unknown integer setcc!");
3437 case ISD::SETULT: LowCC = ISD::SETULT; break;
3439 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3441 case ISD::SETULE: LowCC = ISD::SETULE; break;
3443 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3446 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3447 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3448 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3450 // NOTE: on targets without efficient SELECT of bools, we can always use
3451 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3452 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3453 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3454 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3455 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3456 Result, Tmp1, Tmp2));
3465 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3466 /// The resultant code need not be legal. Note that SrcOp is the input operand
3467 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3468 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3470 // Create the stack frame object.
3471 SDOperand FIPtr = CreateStackTemporary(DestVT);
3473 // Emit a store to the stack slot.
3474 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3475 SrcOp, FIPtr, DAG.getSrcValue(NULL));
3476 // Result is a load from the stack slot.
3477 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0));
3480 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3481 // Create a vector sized/aligned stack slot, store the value to element #0,
3482 // then load the whole vector back out.
3483 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3484 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3485 Node->getOperand(0), StackPtr,
3486 DAG.getSrcValue(NULL));
3487 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,DAG.getSrcValue(NULL));
3491 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3492 /// support the operation, but do support the resultant packed vector type.
3493 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3495 // If the only non-undef value is the low element, turn this into a
3496 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3497 unsigned NumElems = Node->getNumOperands();
3498 bool isOnlyLowElement = true;
3499 SDOperand SplatValue = Node->getOperand(0);
3500 std::map<SDOperand, std::vector<unsigned> > Values;
3501 Values[SplatValue].push_back(0);
3502 bool isConstant = true;
3503 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3504 SplatValue.getOpcode() != ISD::UNDEF)
3507 for (unsigned i = 1; i < NumElems; ++i) {
3508 SDOperand V = Node->getOperand(i);
3509 Values[V].push_back(i);
3510 if (V.getOpcode() != ISD::UNDEF)
3511 isOnlyLowElement = false;
3512 if (SplatValue != V)
3513 SplatValue = SDOperand(0,0);
3515 // If this isn't a constant element or an undef, we can't use a constant
3517 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3518 V.getOpcode() != ISD::UNDEF)
3522 if (isOnlyLowElement) {
3523 // If the low element is an undef too, then this whole things is an undef.
3524 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3525 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3526 // Otherwise, turn this into a scalar_to_vector node.
3527 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3528 Node->getOperand(0));
3531 // If all elements are constants, create a load from the constant pool.
3533 MVT::ValueType VT = Node->getValueType(0);
3535 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3536 std::vector<Constant*> CV;
3537 for (unsigned i = 0, e = NumElems; i != e; ++i) {
3538 if (ConstantFPSDNode *V =
3539 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3540 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3541 } else if (ConstantSDNode *V =
3542 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3543 CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
3545 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3546 CV.push_back(UndefValue::get(OpNTy));
3549 Constant *CP = ConstantPacked::get(CV);
3550 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3551 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
3552 DAG.getSrcValue(NULL));
3555 if (SplatValue.Val) { // Splat of one value?
3556 // Build the shuffle constant vector: <0, 0, 0, 0>
3557 MVT::ValueType MaskVT =
3558 MVT::getIntVectorWithNumElements(NumElems);
3559 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
3560 std::vector<SDOperand> ZeroVec(NumElems, Zero);
3561 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3562 &ZeroVec[0], ZeroVec.size());
3564 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3565 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
3566 // Get the splatted value into the low element of a vector register.
3567 SDOperand LowValVec =
3568 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3570 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3571 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3572 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3577 // If there are only two unique elements, we may be able to turn this into a
3579 if (Values.size() == 2) {
3580 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
3581 MVT::ValueType MaskVT =
3582 MVT::getIntVectorWithNumElements(NumElems);
3583 std::vector<SDOperand> MaskVec(NumElems);
3585 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3586 E = Values.end(); I != E; ++I) {
3587 for (std::vector<unsigned>::iterator II = I->second.begin(),
3588 EE = I->second.end(); II != EE; ++II)
3589 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
3592 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3593 &MaskVec[0], MaskVec.size());
3595 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3596 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
3597 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
3598 SmallVector<SDOperand, 8> Ops;
3599 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3600 E = Values.end(); I != E; ++I) {
3601 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3605 Ops.push_back(ShuffleMask);
3607 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
3608 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
3609 &Ops[0], Ops.size());
3613 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
3614 // aligned object on the stack, store each element into it, then load
3615 // the result as a vector.
3616 MVT::ValueType VT = Node->getValueType(0);
3617 // Create the stack frame object.
3618 SDOperand FIPtr = CreateStackTemporary(VT);
3620 // Emit a store of each element to the stack slot.
3621 SmallVector<SDOperand, 8> Stores;
3622 unsigned TypeByteSize =
3623 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
3624 unsigned VectorSize = MVT::getSizeInBits(VT)/8;
3625 // Store (in the right endianness) the elements to memory.
3626 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3627 // Ignore undef elements.
3628 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3630 unsigned Offset = TypeByteSize*i;
3632 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
3633 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
3635 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3636 Node->getOperand(i), Idx,
3637 DAG.getSrcValue(NULL)));
3640 SDOperand StoreChain;
3641 if (!Stores.empty()) // Not all undef elements?
3642 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3643 &Stores[0], Stores.size());
3645 StoreChain = DAG.getEntryNode();
3647 // Result is a load from the stack slot.
3648 return DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0));
3651 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
3652 /// specified value type.
3653 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
3654 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3655 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
3656 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
3657 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
3660 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
3661 SDOperand Op, SDOperand Amt,
3662 SDOperand &Lo, SDOperand &Hi) {
3663 // Expand the subcomponents.
3664 SDOperand LHSL, LHSH;
3665 ExpandOp(Op, LHSL, LHSH);
3667 SDOperand Ops[] = { LHSL, LHSH, Amt };
3668 MVT::ValueType VT = LHSL.getValueType();
3669 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
3670 Hi = Lo.getValue(1);
3674 /// ExpandShift - Try to find a clever way to expand this shift operation out to
3675 /// smaller elements. If we can't find a way that is more efficient than a
3676 /// libcall on this target, return false. Otherwise, return true with the
3677 /// low-parts expanded into Lo and Hi.
3678 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3679 SDOperand &Lo, SDOperand &Hi) {
3680 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3681 "This is not a shift!");
3683 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3684 SDOperand ShAmt = LegalizeOp(Amt);
3685 MVT::ValueType ShTy = ShAmt.getValueType();
3686 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3687 unsigned NVTBits = MVT::getSizeInBits(NVT);
3689 // Handle the case when Amt is an immediate. Other cases are currently broken
3690 // and are disabled.
3691 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3692 unsigned Cst = CN->getValue();
3693 // Expand the incoming operand to be shifted, so that we have its parts
3695 ExpandOp(Op, InL, InH);
3699 Lo = DAG.getConstant(0, NVT);
3700 Hi = DAG.getConstant(0, NVT);
3701 } else if (Cst > NVTBits) {
3702 Lo = DAG.getConstant(0, NVT);
3703 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
3704 } else if (Cst == NVTBits) {
3705 Lo = DAG.getConstant(0, NVT);
3708 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
3709 Hi = DAG.getNode(ISD::OR, NVT,
3710 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
3711 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
3716 Lo = DAG.getConstant(0, NVT);
3717 Hi = DAG.getConstant(0, NVT);
3718 } else if (Cst > NVTBits) {
3719 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
3720 Hi = DAG.getConstant(0, NVT);
3721 } else if (Cst == NVTBits) {
3723 Hi = DAG.getConstant(0, NVT);
3725 Lo = DAG.getNode(ISD::OR, NVT,
3726 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3727 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3728 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
3733 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
3734 DAG.getConstant(NVTBits-1, ShTy));
3735 } else if (Cst > NVTBits) {
3736 Lo = DAG.getNode(ISD::SRA, NVT, InH,
3737 DAG.getConstant(Cst-NVTBits, ShTy));
3738 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3739 DAG.getConstant(NVTBits-1, ShTy));
3740 } else if (Cst == NVTBits) {
3742 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3743 DAG.getConstant(NVTBits-1, ShTy));
3745 Lo = DAG.getNode(ISD::OR, NVT,
3746 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3747 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3748 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
3757 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
3758 // does not fit into a register, return the lo part and set the hi part to the
3759 // by-reg argument. If it does fit into a single register, return the result
3760 // and leave the Hi part unset.
3761 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3763 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
3764 // The input chain to this libcall is the entry node of the function.
3765 // Legalizing the call will automatically add the previous call to the
3767 SDOperand InChain = DAG.getEntryNode();
3769 TargetLowering::ArgListTy Args;
3770 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3771 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3772 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3773 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3775 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3777 // Splice the libcall in wherever FindInputOutputChains tells us to.
3778 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3779 std::pair<SDOperand,SDOperand> CallInfo =
3780 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3783 // Legalize the call sequence, starting with the chain. This will advance
3784 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
3785 // was added by LowerCallTo (guaranteeing proper serialization of calls).
3786 LegalizeOp(CallInfo.second);
3788 switch (getTypeAction(CallInfo.first.getValueType())) {
3789 default: assert(0 && "Unknown thing");
3791 Result = CallInfo.first;
3794 ExpandOp(CallInfo.first, Result, Hi);
3801 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3802 /// destination type is legal.
3803 SDOperand SelectionDAGLegalize::
3804 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3805 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3806 assert(getTypeAction(Source.getValueType()) == Expand &&
3807 "This is not an expansion!");
3808 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3811 assert(Source.getValueType() == MVT::i64 &&
3812 "This only works for 64-bit -> FP");
3813 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3814 // incoming integer is set. To handle this, we dynamically test to see if
3815 // it is set, and, if so, add a fudge factor.
3817 ExpandOp(Source, Lo, Hi);
3819 // If this is unsigned, and not supported, first perform the conversion to
3820 // signed, then adjust the result if the sign bit is set.
3821 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3822 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3824 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3825 DAG.getConstant(0, Hi.getValueType()),
3827 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3828 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3829 SignSet, Four, Zero);
3830 uint64_t FF = 0x5f800000ULL;
3831 if (TLI.isLittleEndian()) FF <<= 32;
3832 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3834 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3835 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3836 SDOperand FudgeInReg;
3837 if (DestTy == MVT::f32)
3838 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3839 DAG.getSrcValue(NULL));
3841 assert(DestTy == MVT::f64 && "Unexpected conversion");
3842 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3843 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
3845 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3848 // Check to see if the target has a custom way to lower this. If so, use it.
3849 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3850 default: assert(0 && "This action not implemented for this operation!");
3851 case TargetLowering::Legal:
3852 case TargetLowering::Expand:
3853 break; // This case is handled below.
3854 case TargetLowering::Custom: {
3855 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3858 return LegalizeOp(NV);
3859 break; // The target decided this was legal after all
3863 // Expand the source, then glue it back together for the call. We must expand
3864 // the source in case it is shared (this pass of legalize must traverse it).
3865 SDOperand SrcLo, SrcHi;
3866 ExpandOp(Source, SrcLo, SrcHi);
3867 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
3869 const char *FnName = 0;
3870 if (DestTy == MVT::f32)
3871 FnName = "__floatdisf";
3873 assert(DestTy == MVT::f64 && "Unknown fp value type!");
3874 FnName = "__floatdidf";
3877 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
3878 SDOperand UnusedHiPart;
3879 return ExpandLibCall(FnName, Source.Val, UnusedHiPart);
3882 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
3883 /// INT_TO_FP operation of the specified operand when the target requests that
3884 /// we expand it. At this point, we know that the result and operand types are
3885 /// legal for the target.
3886 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
3888 MVT::ValueType DestVT) {
3889 if (Op0.getValueType() == MVT::i32) {
3890 // simple 32-bit [signed|unsigned] integer to float/double expansion
3892 // get the stack frame index of a 8 byte buffer
3893 MachineFunction &MF = DAG.getMachineFunction();
3894 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3895 // get address of 8 byte buffer
3896 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3897 // word offset constant for Hi/Lo address computation
3898 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
3899 // set up Hi and Lo (into buffer) address based on endian
3900 SDOperand Hi = StackSlot;
3901 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
3902 if (TLI.isLittleEndian())
3905 // if signed map to unsigned space
3906 SDOperand Op0Mapped;
3908 // constant used to invert sign bit (signed to unsigned mapping)
3909 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
3910 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
3914 // store the lo of the constructed double - based on integer input
3915 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3916 Op0Mapped, Lo, DAG.getSrcValue(NULL));
3917 // initial hi portion of constructed double
3918 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
3919 // store the hi of the constructed double - biased exponent
3920 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
3921 InitialHi, Hi, DAG.getSrcValue(NULL));
3922 // load the constructed double
3923 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
3924 DAG.getSrcValue(NULL));
3925 // FP constant to bias correct the final result
3926 SDOperand Bias = DAG.getConstantFP(isSigned ?
3927 BitsToDouble(0x4330000080000000ULL)
3928 : BitsToDouble(0x4330000000000000ULL),
3930 // subtract the bias
3931 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
3934 // handle final rounding
3935 if (DestVT == MVT::f64) {
3939 // if f32 then cast to f32
3940 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
3944 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
3945 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
3947 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
3948 DAG.getConstant(0, Op0.getValueType()),
3950 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3951 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3952 SignSet, Four, Zero);
3954 // If the sign bit of the integer is set, the large number will be treated
3955 // as a negative number. To counteract this, the dynamic code adds an
3956 // offset depending on the data type.
3958 switch (Op0.getValueType()) {
3959 default: assert(0 && "Unsupported integer type!");
3960 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
3961 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
3962 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
3963 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
3965 if (TLI.isLittleEndian()) FF <<= 32;
3966 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3968 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3969 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3970 SDOperand FudgeInReg;
3971 if (DestVT == MVT::f32)
3972 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3973 DAG.getSrcValue(NULL));
3975 assert(DestVT == MVT::f64 && "Unexpected conversion");
3976 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
3977 DAG.getEntryNode(), CPIdx,
3978 DAG.getSrcValue(NULL), MVT::f32));
3981 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
3984 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
3985 /// *INT_TO_FP operation of the specified operand when the target requests that
3986 /// we promote it. At this point, we know that the result and operand types are
3987 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
3988 /// operation that takes a larger input.
3989 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
3990 MVT::ValueType DestVT,
3992 // First step, figure out the appropriate *INT_TO_FP operation to use.
3993 MVT::ValueType NewInTy = LegalOp.getValueType();
3995 unsigned OpToUse = 0;
3997 // Scan for the appropriate larger type to use.
3999 NewInTy = (MVT::ValueType)(NewInTy+1);
4000 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4002 // If the target supports SINT_TO_FP of this type, use it.
4003 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4005 case TargetLowering::Legal:
4006 if (!TLI.isTypeLegal(NewInTy))
4007 break; // Can't use this datatype.
4009 case TargetLowering::Custom:
4010 OpToUse = ISD::SINT_TO_FP;
4014 if (isSigned) continue;
4016 // If the target supports UINT_TO_FP of this type, use it.
4017 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4019 case TargetLowering::Legal:
4020 if (!TLI.isTypeLegal(NewInTy))
4021 break; // Can't use this datatype.
4023 case TargetLowering::Custom:
4024 OpToUse = ISD::UINT_TO_FP;
4029 // Otherwise, try a larger type.
4032 // Okay, we found the operation and type to use. Zero extend our input to the
4033 // desired type then run the operation on it.
4034 return DAG.getNode(OpToUse, DestVT,
4035 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4039 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4040 /// FP_TO_*INT operation of the specified operand when the target requests that
4041 /// we promote it. At this point, we know that the result and operand types are
4042 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4043 /// operation that returns a larger result.
4044 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4045 MVT::ValueType DestVT,
4047 // First step, figure out the appropriate FP_TO*INT operation to use.
4048 MVT::ValueType NewOutTy = DestVT;
4050 unsigned OpToUse = 0;
4052 // Scan for the appropriate larger type to use.
4054 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4055 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4057 // If the target supports FP_TO_SINT returning this type, use it.
4058 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4060 case TargetLowering::Legal:
4061 if (!TLI.isTypeLegal(NewOutTy))
4062 break; // Can't use this datatype.
4064 case TargetLowering::Custom:
4065 OpToUse = ISD::FP_TO_SINT;
4070 // If the target supports FP_TO_UINT of this type, use it.
4071 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4073 case TargetLowering::Legal:
4074 if (!TLI.isTypeLegal(NewOutTy))
4075 break; // Can't use this datatype.
4077 case TargetLowering::Custom:
4078 OpToUse = ISD::FP_TO_UINT;
4083 // Otherwise, try a larger type.
4086 // Okay, we found the operation and type to use. Truncate the result of the
4087 // extended FP_TO_*INT operation to the desired size.
4088 return DAG.getNode(ISD::TRUNCATE, DestVT,
4089 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4092 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4094 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4095 MVT::ValueType VT = Op.getValueType();
4096 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4097 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4099 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4101 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4102 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4103 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4105 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4106 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4107 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4108 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4109 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4110 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4111 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4112 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4113 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4115 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4116 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4117 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4118 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4119 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4120 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4121 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4122 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4123 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4124 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4125 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4126 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4127 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4128 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4129 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4130 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4131 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4132 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4133 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4134 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4135 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4139 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4141 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4143 default: assert(0 && "Cannot expand this yet!");
4145 static const uint64_t mask[6] = {
4146 0x5555555555555555ULL, 0x3333333333333333ULL,
4147 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4148 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4150 MVT::ValueType VT = Op.getValueType();
4151 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4152 unsigned len = getSizeInBits(VT);
4153 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4154 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4155 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4156 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4157 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4158 DAG.getNode(ISD::AND, VT,
4159 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4164 // for now, we do this:
4165 // x = x | (x >> 1);
4166 // x = x | (x >> 2);
4168 // x = x | (x >>16);
4169 // x = x | (x >>32); // for 64-bit input
4170 // return popcount(~x);
4172 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4173 MVT::ValueType VT = Op.getValueType();
4174 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4175 unsigned len = getSizeInBits(VT);
4176 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4177 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4178 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4180 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4181 return DAG.getNode(ISD::CTPOP, VT, Op);
4184 // for now, we use: { return popcount(~x & (x - 1)); }
4185 // unless the target has ctlz but not ctpop, in which case we use:
4186 // { return 32 - nlz(~x & (x-1)); }
4187 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4188 MVT::ValueType VT = Op.getValueType();
4189 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4190 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4191 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4192 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4193 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4194 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4195 TLI.isOperationLegal(ISD::CTLZ, VT))
4196 return DAG.getNode(ISD::SUB, VT,
4197 DAG.getConstant(getSizeInBits(VT), VT),
4198 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4199 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4204 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4205 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4206 /// LegalizeNodes map is filled in for any results that are not expanded, the
4207 /// ExpandedNodes map is filled in for any results that are expanded, and the
4208 /// Lo/Hi values are returned.
4209 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4210 MVT::ValueType VT = Op.getValueType();
4211 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4212 SDNode *Node = Op.Val;
4213 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4214 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
4215 "Cannot expand FP values!");
4216 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
4217 "Cannot expand to FP value or to larger int value!");
4219 // See if we already expanded it.
4220 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4221 = ExpandedNodes.find(Op);
4222 if (I != ExpandedNodes.end()) {
4223 Lo = I->second.first;
4224 Hi = I->second.second;
4228 switch (Node->getOpcode()) {
4229 case ISD::CopyFromReg:
4230 assert(0 && "CopyFromReg must be legal!");
4233 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
4235 assert(0 && "Do not know how to expand this operator!");
4238 Lo = DAG.getNode(ISD::UNDEF, NVT);
4239 Hi = DAG.getNode(ISD::UNDEF, NVT);
4241 case ISD::Constant: {
4242 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4243 Lo = DAG.getConstant(Cst, NVT);
4244 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4247 case ISD::BUILD_PAIR:
4248 // Return the operands.
4249 Lo = Node->getOperand(0);
4250 Hi = Node->getOperand(1);
4253 case ISD::SIGN_EXTEND_INREG:
4254 ExpandOp(Node->getOperand(0), Lo, Hi);
4255 // Sign extend the lo-part.
4256 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4257 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4258 TLI.getShiftAmountTy()));
4259 // sext_inreg the low part if needed.
4260 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4264 ExpandOp(Node->getOperand(0), Lo, Hi);
4265 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4266 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4272 ExpandOp(Node->getOperand(0), Lo, Hi);
4273 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4274 DAG.getNode(ISD::CTPOP, NVT, Lo),
4275 DAG.getNode(ISD::CTPOP, NVT, Hi));
4276 Hi = DAG.getConstant(0, NVT);
4280 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4281 ExpandOp(Node->getOperand(0), Lo, Hi);
4282 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4283 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4284 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4286 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4287 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4289 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4290 Hi = DAG.getConstant(0, NVT);
4295 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4296 ExpandOp(Node->getOperand(0), Lo, Hi);
4297 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4298 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4299 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4301 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4302 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4304 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4305 Hi = DAG.getConstant(0, NVT);
4310 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4311 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4312 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4313 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4315 // Remember that we legalized the chain.
4316 Hi = LegalizeOp(Hi);
4317 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4318 if (!TLI.isLittleEndian())
4324 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4325 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4326 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
4328 // Increment the pointer to the other half.
4329 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4330 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4331 getIntPtrConstant(IncrementSize));
4332 // FIXME: This creates a bogus srcvalue!
4333 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
4335 // Build a factor node to remember that this load is independent of the
4337 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4340 // Remember that we legalized the chain.
4341 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4342 if (!TLI.isLittleEndian())
4348 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
4349 SDOperand LL, LH, RL, RH;
4350 ExpandOp(Node->getOperand(0), LL, LH);
4351 ExpandOp(Node->getOperand(1), RL, RH);
4352 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4353 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4357 SDOperand LL, LH, RL, RH;
4358 ExpandOp(Node->getOperand(1), LL, LH);
4359 ExpandOp(Node->getOperand(2), RL, RH);
4360 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4361 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4364 case ISD::SELECT_CC: {
4365 SDOperand TL, TH, FL, FH;
4366 ExpandOp(Node->getOperand(2), TL, TH);
4367 ExpandOp(Node->getOperand(3), FL, FH);
4368 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4369 Node->getOperand(1), TL, FL, Node->getOperand(4));
4370 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4371 Node->getOperand(1), TH, FH, Node->getOperand(4));
4374 case ISD::SEXTLOAD: {
4375 SDOperand Chain = Node->getOperand(0);
4376 SDOperand Ptr = Node->getOperand(1);
4377 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4380 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4382 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4385 // Remember that we legalized the chain.
4386 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4388 // The high part is obtained by SRA'ing all but one of the bits of the lo
4390 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4391 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
4392 TLI.getShiftAmountTy()));
4395 case ISD::ZEXTLOAD: {
4396 SDOperand Chain = Node->getOperand(0);
4397 SDOperand Ptr = Node->getOperand(1);
4398 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4401 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4403 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4406 // Remember that we legalized the chain.
4407 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4409 // The high part is just a zero.
4410 Hi = DAG.getConstant(0, NVT);
4413 case ISD::EXTLOAD: {
4414 SDOperand Chain = Node->getOperand(0);
4415 SDOperand Ptr = Node->getOperand(1);
4416 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4419 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4421 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4424 // Remember that we legalized the chain.
4425 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4427 // The high part is undefined.
4428 Hi = DAG.getNode(ISD::UNDEF, NVT);
4431 case ISD::ANY_EXTEND:
4432 // The low part is any extension of the input (which degenerates to a copy).
4433 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4434 // The high part is undefined.
4435 Hi = DAG.getNode(ISD::UNDEF, NVT);
4437 case ISD::SIGN_EXTEND: {
4438 // The low part is just a sign extension of the input (which degenerates to
4440 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4442 // The high part is obtained by SRA'ing all but one of the bits of the lo
4444 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4445 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4446 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4449 case ISD::ZERO_EXTEND:
4450 // The low part is just a zero extension of the input (which degenerates to
4452 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4454 // The high part is just a zero.
4455 Hi = DAG.getConstant(0, NVT);
4458 case ISD::BIT_CONVERT: {
4459 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0),
4460 Node->getOperand(0));
4461 ExpandOp(Tmp, Lo, Hi);
4465 case ISD::READCYCLECOUNTER:
4466 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
4467 TargetLowering::Custom &&
4468 "Must custom expand ReadCycleCounter");
4469 Lo = TLI.LowerOperation(Op, DAG);
4470 assert(Lo.Val && "Node must be custom expanded!");
4471 Hi = Lo.getValue(1);
4472 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
4473 LegalizeOp(Lo.getValue(2)));
4476 // These operators cannot be expanded directly, emit them as calls to
4477 // library functions.
4478 case ISD::FP_TO_SINT:
4479 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
4481 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4482 case Expand: assert(0 && "cannot expand FP!");
4483 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4484 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4487 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
4489 // Now that the custom expander is done, expand the result, which is still
4492 ExpandOp(Op, Lo, Hi);
4497 if (Node->getOperand(0).getValueType() == MVT::f32)
4498 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
4500 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
4503 case ISD::FP_TO_UINT:
4504 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
4506 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4507 case Expand: assert(0 && "cannot expand FP!");
4508 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4509 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4512 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
4514 // Now that the custom expander is done, expand the result.
4516 ExpandOp(Op, Lo, Hi);
4521 if (Node->getOperand(0).getValueType() == MVT::f32)
4522 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
4524 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
4528 // If the target wants custom lowering, do so.
4529 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4530 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
4531 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
4532 Op = TLI.LowerOperation(Op, DAG);
4534 // Now that the custom expander is done, expand the result, which is
4536 ExpandOp(Op, Lo, Hi);
4541 // If we can emit an efficient shift operation, do so now.
4542 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4545 // If this target supports SHL_PARTS, use it.
4546 TargetLowering::LegalizeAction Action =
4547 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
4548 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4549 Action == TargetLowering::Custom) {
4550 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4554 // Otherwise, emit a libcall.
4555 Lo = ExpandLibCall("__ashldi3", Node, Hi);
4560 // If the target wants custom lowering, do so.
4561 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4562 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
4563 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
4564 Op = TLI.LowerOperation(Op, DAG);
4566 // Now that the custom expander is done, expand the result, which is
4568 ExpandOp(Op, Lo, Hi);
4573 // If we can emit an efficient shift operation, do so now.
4574 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
4577 // If this target supports SRA_PARTS, use it.
4578 TargetLowering::LegalizeAction Action =
4579 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
4580 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4581 Action == TargetLowering::Custom) {
4582 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4586 // Otherwise, emit a libcall.
4587 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
4592 // If the target wants custom lowering, do so.
4593 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4594 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
4595 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
4596 Op = TLI.LowerOperation(Op, DAG);
4598 // Now that the custom expander is done, expand the result, which is
4600 ExpandOp(Op, Lo, Hi);
4605 // If we can emit an efficient shift operation, do so now.
4606 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4609 // If this target supports SRL_PARTS, use it.
4610 TargetLowering::LegalizeAction Action =
4611 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
4612 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4613 Action == TargetLowering::Custom) {
4614 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4618 // Otherwise, emit a libcall.
4619 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
4625 // If the target wants to custom expand this, let them.
4626 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
4627 TargetLowering::Custom) {
4628 Op = TLI.LowerOperation(Op, DAG);
4630 ExpandOp(Op, Lo, Hi);
4635 // Expand the subcomponents.
4636 SDOperand LHSL, LHSH, RHSL, RHSH;
4637 ExpandOp(Node->getOperand(0), LHSL, LHSH);
4638 ExpandOp(Node->getOperand(1), RHSL, RHSH);
4639 const MVT::ValueType *VTs =
4640 DAG.getNodeValueTypes(LHSL.getValueType(),MVT::Flag);
4641 SDOperand LoOps[2], HiOps[2];
4646 if (Node->getOpcode() == ISD::ADD) {
4647 Lo = DAG.getNode(ISD::ADDC, VTs, 2, LoOps, 2);
4648 HiOps[2] = Lo.getValue(1);
4649 Hi = DAG.getNode(ISD::ADDE, VTs, 2, HiOps, 3);
4651 Lo = DAG.getNode(ISD::SUBC, VTs, 2, LoOps, 2);
4652 HiOps[2] = Lo.getValue(1);
4653 Hi = DAG.getNode(ISD::SUBE, VTs, 2, HiOps, 3);
4658 if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
4659 SDOperand LL, LH, RL, RH;
4660 ExpandOp(Node->getOperand(0), LL, LH);
4661 ExpandOp(Node->getOperand(1), RL, RH);
4662 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
4663 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
4664 // extended the sign bit of the low half through the upper half, and if so
4665 // emit a MULHS instead of the alternate sequence that is valid for any
4666 // i64 x i64 multiply.
4667 if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
4668 // is RH an extension of the sign bit of RL?
4669 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
4670 RH.getOperand(1).getOpcode() == ISD::Constant &&
4671 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
4672 // is LH an extension of the sign bit of LL?
4673 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
4674 LH.getOperand(1).getOpcode() == ISD::Constant &&
4675 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
4676 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
4678 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
4679 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
4680 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
4681 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
4682 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
4684 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4686 Lo = ExpandLibCall("__muldi3" , Node, Hi);
4690 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
4691 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
4692 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
4693 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
4696 // Make sure the resultant values have been legalized themselves, unless this
4697 // is a type that requires multi-step expansion.
4698 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
4699 Lo = LegalizeOp(Lo);
4700 Hi = LegalizeOp(Hi);
4703 // Remember in a map if the values will be reused later.
4705 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4706 assert(isNew && "Value already expanded?!?");
4709 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
4710 /// two smaller values of MVT::Vector type.
4711 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
4713 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
4714 SDNode *Node = Op.Val;
4715 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
4716 assert(NumElements > 1 && "Cannot split a single element vector!");
4717 unsigned NewNumElts = NumElements/2;
4718 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
4719 SDOperand TypeNode = *(Node->op_end()-1);
4721 // See if we already split it.
4722 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4723 = SplitNodes.find(Op);
4724 if (I != SplitNodes.end()) {
4725 Lo = I->second.first;
4726 Hi = I->second.second;
4730 switch (Node->getOpcode()) {
4735 assert(0 && "Unhandled operation in SplitVectorOp!");
4736 case ISD::VBUILD_VECTOR: {
4737 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
4738 Node->op_begin()+NewNumElts);
4739 LoOps.push_back(NewNumEltsNode);
4740 LoOps.push_back(TypeNode);
4741 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size());
4743 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
4745 HiOps.push_back(NewNumEltsNode);
4746 HiOps.push_back(TypeNode);
4747 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size());
4758 SDOperand LL, LH, RL, RH;
4759 SplitVectorOp(Node->getOperand(0), LL, LH);
4760 SplitVectorOp(Node->getOperand(1), RL, RH);
4762 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
4763 NewNumEltsNode, TypeNode);
4764 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
4765 NewNumEltsNode, TypeNode);
4769 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4770 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4771 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4773 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4774 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
4775 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4776 getIntPtrConstant(IncrementSize));
4777 // FIXME: This creates a bogus srcvalue!
4778 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4780 // Build a factor node to remember that this load is independent of the
4782 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4785 // Remember that we legalized the chain.
4786 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4789 case ISD::VBIT_CONVERT: {
4790 // We know the result is a vector. The input may be either a vector or a
4792 if (Op.getOperand(0).getValueType() != MVT::Vector) {
4793 // Lower to a store/load. FIXME: this could be improved probably.
4794 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
4796 SDOperand St = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
4797 Op.getOperand(0), Ptr, DAG.getSrcValue(0));
4798 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4799 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0));
4800 SplitVectorOp(St, Lo, Hi);
4802 // If the input is a vector type, we have to either scalarize it, pack it
4803 // or convert it based on whether the input vector type is legal.
4804 SDNode *InVal = Node->getOperand(0).Val;
4806 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
4807 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
4809 // If the input is from a single element vector, scalarize the vector,
4810 // then treat like a scalar.
4811 if (NumElems == 1) {
4812 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT);
4813 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar,
4814 Op.getOperand(1), Op.getOperand(2));
4815 SplitVectorOp(Scalar, Lo, Hi);
4817 // Split the input vector.
4818 SplitVectorOp(Op.getOperand(0), Lo, Hi);
4820 // Convert each of the pieces now.
4821 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo,
4822 NewNumEltsNode, TypeNode);
4823 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi,
4824 NewNumEltsNode, TypeNode);
4831 // Remember in a map if the values will be reused later.
4833 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4834 assert(isNew && "Value already expanded?!?");
4838 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
4839 /// equivalent operation that returns a scalar (e.g. F32) or packed value
4840 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
4841 /// type for the result.
4842 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
4843 MVT::ValueType NewVT) {
4844 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
4845 SDNode *Node = Op.Val;
4847 // See if we already packed it.
4848 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
4849 if (I != PackedNodes.end()) return I->second;
4852 switch (Node->getOpcode()) {
4855 Node->dump(); std::cerr << "\n";
4857 assert(0 && "Unknown vector operation in PackVectorOp!");
4866 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
4868 PackVectorOp(Node->getOperand(0), NewVT),
4869 PackVectorOp(Node->getOperand(1), NewVT));
4872 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
4873 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
4875 Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(2));
4877 // Remember that we legalized the chain.
4878 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4881 case ISD::VBUILD_VECTOR:
4882 if (Node->getOperand(0).getValueType() == NewVT) {
4883 // Returning a scalar?
4884 Result = Node->getOperand(0);
4886 // Returning a BUILD_VECTOR?
4888 // If all elements of the build_vector are undefs, return an undef.
4889 bool AllUndef = true;
4890 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i)
4891 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) {
4896 Result = DAG.getNode(ISD::UNDEF, NewVT);
4898 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(),
4899 Node->getNumOperands()-2);
4903 case ISD::VINSERT_VECTOR_ELT:
4904 if (!MVT::isVector(NewVT)) {
4905 // Returning a scalar? Must be the inserted element.
4906 Result = Node->getOperand(1);
4908 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
4909 PackVectorOp(Node->getOperand(0), NewVT),
4910 Node->getOperand(1), Node->getOperand(2));
4913 case ISD::VVECTOR_SHUFFLE:
4914 if (!MVT::isVector(NewVT)) {
4915 // Returning a scalar? Figure out if it is the LHS or RHS and return it.
4916 SDOperand EltNum = Node->getOperand(2).getOperand(0);
4917 if (cast<ConstantSDNode>(EltNum)->getValue())
4918 Result = PackVectorOp(Node->getOperand(1), NewVT);
4920 Result = PackVectorOp(Node->getOperand(0), NewVT);
4922 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index
4923 // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
4924 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
4925 Node->getOperand(2).Val->op_end()-2);
4926 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
4927 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT,
4928 Node->getOperand(2).Val->op_begin(),
4929 Node->getOperand(2).Val->getNumOperands()-2);
4931 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
4932 PackVectorOp(Node->getOperand(0), NewVT),
4933 PackVectorOp(Node->getOperand(1), NewVT), BV);
4936 case ISD::VBIT_CONVERT:
4937 if (Op.getOperand(0).getValueType() != MVT::Vector)
4938 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
4940 // If the input is a vector type, we have to either scalarize it, pack it
4941 // or convert it based on whether the input vector type is legal.
4942 SDNode *InVal = Node->getOperand(0).Val;
4944 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
4945 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
4947 // Figure out if there is a Packed type corresponding to this Vector
4948 // type. If so, convert to the packed type.
4949 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
4950 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
4951 // Turn this into a bit convert of the packed input.
4952 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
4953 PackVectorOp(Node->getOperand(0), TVT));
4955 } else if (NumElems == 1) {
4956 // Turn this into a bit convert of the scalar input.
4957 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
4958 PackVectorOp(Node->getOperand(0), EVT));
4962 assert(0 && "Cast from unsupported vector type not implemented yet!");
4967 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
4968 PackVectorOp(Op.getOperand(1), NewVT),
4969 PackVectorOp(Op.getOperand(2), NewVT));
4973 if (TLI.isTypeLegal(NewVT))
4974 Result = LegalizeOp(Result);
4975 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
4976 assert(isNew && "Value already packed?");
4981 // SelectionDAG::Legalize - This is the entry point for the file.
4983 void SelectionDAG::Legalize() {
4984 if (ViewLegalizeDAGs) viewGraph();
4986 /// run - This is the main entry point to this class.
4988 SelectionDAGLegalize(*this).LegalizeDAG();