1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Target/TargetLowering.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Support/MathExtras.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/Compiler.h"
26 #include "llvm/ADT/SmallVector.h"
33 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
34 cl::desc("Pop up a window to show dags before legalize"));
36 static const bool ViewLegalizeDAGs = 0;
39 //===----------------------------------------------------------------------===//
40 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
41 /// hacks on it until the target machine can handle it. This involves
42 /// eliminating value sizes the machine cannot handle (promoting small sizes to
43 /// large sizes or splitting up large values into small values) as well as
44 /// eliminating operations the machine cannot handle.
46 /// This code also does a small amount of optimization and recognition of idioms
47 /// as part of its processing. For example, if a target does not support a
48 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
49 /// will attempt merge setcc and brc instructions into brcc's.
52 class VISIBILITY_HIDDEN SelectionDAGLegalize {
56 // Libcall insertion helpers.
58 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
59 /// legalized. We use this to ensure that calls are properly serialized
60 /// against each other, including inserted libcalls.
61 SDOperand LastCALLSEQ_END;
63 /// IsLegalizingCall - This member is used *only* for purposes of providing
64 /// helpful assertions that a libcall isn't created while another call is
65 /// being legalized (which could lead to non-serialized call sequences).
66 bool IsLegalizingCall;
69 Legal, // The target natively supports this operation.
70 Promote, // This operation should be executed in a larger type.
71 Expand // Try to expand this to other ops, otherwise use a libcall.
74 /// ValueTypeActions - This is a bitvector that contains two bits for each
75 /// value type, where the two bits correspond to the LegalizeAction enum.
76 /// This can be queried with "getTypeAction(VT)".
77 TargetLowering::ValueTypeActionImpl ValueTypeActions;
79 /// LegalizedNodes - For nodes that are of legal width, and that have more
80 /// than one use, this map indicates what regularized operand to use. This
81 /// allows us to avoid legalizing the same thing more than once.
82 std::map<SDOperand, SDOperand> LegalizedNodes;
84 /// PromotedNodes - For nodes that are below legal width, and that have more
85 /// than one use, this map indicates what promoted value to use. This allows
86 /// us to avoid promoting the same thing more than once.
87 std::map<SDOperand, SDOperand> PromotedNodes;
89 /// ExpandedNodes - For nodes that need to be expanded this map indicates
90 /// which which operands are the expanded version of the input. This allows
91 /// us to avoid expanding the same node more than once.
92 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
94 /// SplitNodes - For vector nodes that need to be split, this map indicates
95 /// which which operands are the split version of the input. This allows us
96 /// to avoid splitting the same node more than once.
97 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
99 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
100 /// concrete packed types, this contains the mapping of ones we have already
101 /// processed to the result.
102 std::map<SDOperand, SDOperand> PackedNodes;
104 void AddLegalizedOperand(SDOperand From, SDOperand To) {
105 LegalizedNodes.insert(std::make_pair(From, To));
106 // If someone requests legalization of the new node, return itself.
108 LegalizedNodes.insert(std::make_pair(To, To));
110 void AddPromotedOperand(SDOperand From, SDOperand To) {
111 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
112 assert(isNew && "Got into the map somehow?");
113 // If someone requests legalization of the new node, return itself.
114 LegalizedNodes.insert(std::make_pair(To, To));
119 SelectionDAGLegalize(SelectionDAG &DAG);
121 /// getTypeAction - Return how we should legalize values of this type, either
122 /// it is already legal or we need to expand it into multiple registers of
123 /// smaller integer type, or we need to promote it to a larger type.
124 LegalizeAction getTypeAction(MVT::ValueType VT) const {
125 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
128 /// isTypeLegal - Return true if this type is legal on this target.
130 bool isTypeLegal(MVT::ValueType VT) const {
131 return getTypeAction(VT) == Legal;
137 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
138 /// appropriate for its type.
139 void HandleOp(SDOperand Op);
141 /// LegalizeOp - We know that the specified value has a legal type.
142 /// Recursively ensure that the operands have legal types, then return the
144 SDOperand LegalizeOp(SDOperand O);
146 /// PromoteOp - Given an operation that produces a value in an invalid type,
147 /// promote it to compute the value into a larger type. The produced value
148 /// will have the correct bits for the low portion of the register, but no
149 /// guarantee is made about the top bits: it may be zero, sign-extended, or
151 SDOperand PromoteOp(SDOperand O);
153 /// ExpandOp - Expand the specified SDOperand into its two component pieces
154 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
155 /// the LegalizeNodes map is filled in for any results that are not expanded,
156 /// the ExpandedNodes map is filled in for any results that are expanded, and
157 /// the Lo/Hi values are returned. This applies to integer types and Vector
159 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
161 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
162 /// two smaller values of MVT::Vector type.
163 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
165 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
166 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
167 /// this is called, we know that PackedVT is the right type for the result and
168 /// we know that this type is legal for the target.
169 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
171 /// isShuffleLegal - Return true if a vector shuffle is legal with the
172 /// specified mask and type. Targets can specify exactly which masks they
173 /// support and the code generator is tasked with not creating illegal masks.
175 /// Note that this will also return true for shuffles that are promoted to a
178 /// If this is a legal shuffle, this method returns the (possibly promoted)
179 /// build_vector Mask. If it's not a legal shuffle, it returns null.
180 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
182 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
183 std::set<SDNode*> &NodesLeadingTo);
185 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
187 SDOperand CreateStackTemporary(MVT::ValueType VT);
189 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
191 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
194 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
195 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
196 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
197 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
199 MVT::ValueType DestVT);
200 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
202 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
205 SDOperand ExpandBSWAP(SDOperand Op);
206 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
207 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
208 SDOperand &Lo, SDOperand &Hi);
209 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
210 SDOperand &Lo, SDOperand &Hi);
212 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
213 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
215 SDOperand getIntPtrConstant(uint64_t Val) {
216 return DAG.getConstant(Val, TLI.getPointerTy());
221 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
222 /// specified mask and type. Targets can specify exactly which masks they
223 /// support and the code generator is tasked with not creating illegal masks.
225 /// Note that this will also return true for shuffles that are promoted to a
227 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
228 SDOperand Mask) const {
229 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
231 case TargetLowering::Legal:
232 case TargetLowering::Custom:
234 case TargetLowering::Promote: {
235 // If this is promoted to a different type, convert the shuffle mask and
236 // ask if it is legal in the promoted type!
237 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
239 // If we changed # elements, change the shuffle mask.
240 unsigned NumEltsGrowth =
241 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
242 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
243 if (NumEltsGrowth > 1) {
244 // Renumber the elements.
245 SmallVector<SDOperand, 8> Ops;
246 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
247 SDOperand InOp = Mask.getOperand(i);
248 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
249 if (InOp.getOpcode() == ISD::UNDEF)
250 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
252 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
253 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
257 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
263 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
266 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
267 /// specified vector opcode.
268 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
270 default: assert(0 && "Don't know how to scalarize this opcode!");
271 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
272 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
273 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
274 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
275 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
276 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
277 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
278 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
282 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
283 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
284 ValueTypeActions(TLI.getValueTypeActions()) {
285 assert(MVT::LAST_VALUETYPE <= 32 &&
286 "Too many value types for ValueTypeActions to hold!");
289 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
290 /// not been visited yet and if all of its operands have already been visited.
291 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
292 std::map<SDNode*, unsigned> &Visited) {
293 if (++Visited[N] != N->getNumOperands())
294 return; // Haven't visited all operands yet
298 if (N->hasOneUse()) { // Tail recurse in common case.
299 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
303 // Now that we have N in, add anything that uses it if all of their operands
305 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
306 ComputeTopDownOrdering(*UI, Order, Visited);
310 void SelectionDAGLegalize::LegalizeDAG() {
311 LastCALLSEQ_END = DAG.getEntryNode();
312 IsLegalizingCall = false;
314 // The legalize process is inherently a bottom-up recursive process (users
315 // legalize their uses before themselves). Given infinite stack space, we
316 // could just start legalizing on the root and traverse the whole graph. In
317 // practice however, this causes us to run out of stack space on large basic
318 // blocks. To avoid this problem, compute an ordering of the nodes where each
319 // node is only legalized after all of its operands are legalized.
320 std::map<SDNode*, unsigned> Visited;
321 std::vector<SDNode*> Order;
323 // Compute ordering from all of the leaves in the graphs, those (like the
324 // entry node) that have no operands.
325 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
326 E = DAG.allnodes_end(); I != E; ++I) {
327 if (I->getNumOperands() == 0) {
329 ComputeTopDownOrdering(I, Order, Visited);
333 assert(Order.size() == Visited.size() &&
335 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
336 "Error: DAG is cyclic!");
339 for (unsigned i = 0, e = Order.size(); i != e; ++i)
340 HandleOp(SDOperand(Order[i], 0));
342 // Finally, it's possible the root changed. Get the new root.
343 SDOperand OldRoot = DAG.getRoot();
344 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
345 DAG.setRoot(LegalizedNodes[OldRoot]);
347 ExpandedNodes.clear();
348 LegalizedNodes.clear();
349 PromotedNodes.clear();
353 // Remove dead nodes now.
354 DAG.RemoveDeadNodes();
358 /// FindCallEndFromCallStart - Given a chained node that is part of a call
359 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
360 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
361 if (Node->getOpcode() == ISD::CALLSEQ_END)
363 if (Node->use_empty())
364 return 0; // No CallSeqEnd
366 // The chain is usually at the end.
367 SDOperand TheChain(Node, Node->getNumValues()-1);
368 if (TheChain.getValueType() != MVT::Other) {
369 // Sometimes it's at the beginning.
370 TheChain = SDOperand(Node, 0);
371 if (TheChain.getValueType() != MVT::Other) {
372 // Otherwise, hunt for it.
373 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
374 if (Node->getValueType(i) == MVT::Other) {
375 TheChain = SDOperand(Node, i);
379 // Otherwise, we walked into a node without a chain.
380 if (TheChain.getValueType() != MVT::Other)
385 for (SDNode::use_iterator UI = Node->use_begin(),
386 E = Node->use_end(); UI != E; ++UI) {
388 // Make sure to only follow users of our token chain.
390 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
391 if (User->getOperand(i) == TheChain)
392 if (SDNode *Result = FindCallEndFromCallStart(User))
398 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
399 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
400 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
401 assert(Node && "Didn't find callseq_start for a call??");
402 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
404 assert(Node->getOperand(0).getValueType() == MVT::Other &&
405 "Node doesn't have a token chain argument!");
406 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
409 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
410 /// see if any uses can reach Dest. If no dest operands can get to dest,
411 /// legalize them, legalize ourself, and return false, otherwise, return true.
413 /// Keep track of the nodes we fine that actually do lead to Dest in
414 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
416 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
417 std::set<SDNode*> &NodesLeadingTo) {
418 if (N == Dest) return true; // N certainly leads to Dest :)
420 // If we've already processed this node and it does lead to Dest, there is no
421 // need to reprocess it.
422 if (NodesLeadingTo.count(N)) return true;
424 // If the first result of this node has been already legalized, then it cannot
426 switch (getTypeAction(N->getValueType(0))) {
428 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
431 if (PromotedNodes.count(SDOperand(N, 0))) return false;
434 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
438 // Okay, this node has not already been legalized. Check and legalize all
439 // operands. If none lead to Dest, then we can legalize this node.
440 bool OperandsLeadToDest = false;
441 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
442 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
443 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
445 if (OperandsLeadToDest) {
446 NodesLeadingTo.insert(N);
450 // Okay, this node looks safe, legalize it and return false.
451 HandleOp(SDOperand(N, 0));
455 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
456 /// appropriate for its type.
457 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
458 switch (getTypeAction(Op.getValueType())) {
459 default: assert(0 && "Bad type action!");
460 case Legal: LegalizeOp(Op); break;
461 case Promote: PromoteOp(Op); break;
463 if (Op.getValueType() != MVT::Vector) {
468 unsigned NumOps = N->getNumOperands();
469 unsigned NumElements =
470 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
471 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
472 MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
473 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
474 // In the common case, this is a legal vector type, convert it to the
475 // packed operation and type now.
476 PackVectorOp(Op, PackedVT);
477 } else if (NumElements == 1) {
478 // Otherwise, if this is a single element vector, convert it to a
480 PackVectorOp(Op, EVT);
482 // Otherwise, this is a multiple element vector that isn't supported.
483 // Split it in half and legalize both parts.
485 SplitVectorOp(Op, X, Y);
493 /// LegalizeOp - We know that the specified value has a legal type.
494 /// Recursively ensure that the operands have legal types, then return the
496 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
497 assert(isTypeLegal(Op.getValueType()) &&
498 "Caller should expand or promote operands that are not legal!");
499 SDNode *Node = Op.Val;
501 // If this operation defines any values that cannot be represented in a
502 // register on this target, make sure to expand or promote them.
503 if (Node->getNumValues() > 1) {
504 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
505 if (getTypeAction(Node->getValueType(i)) != Legal) {
506 HandleOp(Op.getValue(i));
507 assert(LegalizedNodes.count(Op) &&
508 "Handling didn't add legal operands!");
509 return LegalizedNodes[Op];
513 // Note that LegalizeOp may be reentered even from single-use nodes, which
514 // means that we always must cache transformed nodes.
515 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
516 if (I != LegalizedNodes.end()) return I->second;
518 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
519 SDOperand Result = Op;
520 bool isCustom = false;
522 switch (Node->getOpcode()) {
523 case ISD::FrameIndex:
524 case ISD::EntryToken:
526 case ISD::BasicBlock:
527 case ISD::TargetFrameIndex:
528 case ISD::TargetJumpTable:
529 case ISD::TargetConstant:
530 case ISD::TargetConstantFP:
531 case ISD::TargetConstantPool:
532 case ISD::TargetGlobalAddress:
533 case ISD::TargetExternalSymbol:
538 case ISD::GLOBAL_OFFSET_TABLE:
539 // Primitives must all be legal.
540 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
541 "This must be legal!");
544 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
545 // If this is a target node, legalize it by legalizing the operands then
546 // passing it through.
547 SmallVector<SDOperand, 8> Ops;
548 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
549 Ops.push_back(LegalizeOp(Node->getOperand(i)));
551 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
553 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
554 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
555 return Result.getValue(Op.ResNo);
557 // Otherwise this is an unhandled builtin node. splat.
559 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
561 assert(0 && "Do not know how to legalize this operator!");
563 case ISD::GlobalAddress:
564 case ISD::ExternalSymbol:
565 case ISD::ConstantPool:
566 case ISD::JumpTable: // Nothing to do.
567 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
568 default: assert(0 && "This action is not supported yet!");
569 case TargetLowering::Custom:
570 Tmp1 = TLI.LowerOperation(Op, DAG);
571 if (Tmp1.Val) Result = Tmp1;
572 // FALLTHROUGH if the target doesn't want to lower this op after all.
573 case TargetLowering::Legal:
577 case ISD::AssertSext:
578 case ISD::AssertZext:
579 Tmp1 = LegalizeOp(Node->getOperand(0));
580 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
582 case ISD::MERGE_VALUES:
583 // Legalize eliminates MERGE_VALUES nodes.
584 Result = Node->getOperand(Op.ResNo);
586 case ISD::CopyFromReg:
587 Tmp1 = LegalizeOp(Node->getOperand(0));
588 Result = Op.getValue(0);
589 if (Node->getNumValues() == 2) {
590 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
592 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
593 if (Node->getNumOperands() == 3) {
594 Tmp2 = LegalizeOp(Node->getOperand(2));
595 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
597 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
599 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
601 // Since CopyFromReg produces two values, make sure to remember that we
602 // legalized both of them.
603 AddLegalizedOperand(Op.getValue(0), Result);
604 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
605 return Result.getValue(Op.ResNo);
607 MVT::ValueType VT = Op.getValueType();
608 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
609 default: assert(0 && "This action is not supported yet!");
610 case TargetLowering::Expand:
611 if (MVT::isInteger(VT))
612 Result = DAG.getConstant(0, VT);
613 else if (MVT::isFloatingPoint(VT))
614 Result = DAG.getConstantFP(0, VT);
616 assert(0 && "Unknown value type!");
618 case TargetLowering::Legal:
624 case ISD::INTRINSIC_W_CHAIN:
625 case ISD::INTRINSIC_WO_CHAIN:
626 case ISD::INTRINSIC_VOID: {
627 SmallVector<SDOperand, 8> Ops;
628 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
629 Ops.push_back(LegalizeOp(Node->getOperand(i)));
630 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
632 // Allow the target to custom lower its intrinsics if it wants to.
633 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
634 TargetLowering::Custom) {
635 Tmp3 = TLI.LowerOperation(Result, DAG);
636 if (Tmp3.Val) Result = Tmp3;
639 if (Result.Val->getNumValues() == 1) break;
641 // Must have return value and chain result.
642 assert(Result.Val->getNumValues() == 2 &&
643 "Cannot return more than two values!");
645 // Since loads produce two values, make sure to remember that we
646 // legalized both of them.
647 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
648 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
649 return Result.getValue(Op.ResNo);
653 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
654 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
656 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
657 case TargetLowering::Promote:
658 default: assert(0 && "This action is not supported yet!");
659 case TargetLowering::Expand: {
660 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
661 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
662 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
664 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
665 const std::string &FName =
666 cast<StringSDNode>(Node->getOperand(3))->getValue();
667 const std::string &DirName =
668 cast<StringSDNode>(Node->getOperand(4))->getValue();
669 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
671 SmallVector<SDOperand, 8> Ops;
672 Ops.push_back(Tmp1); // chain
673 SDOperand LineOp = Node->getOperand(1);
674 SDOperand ColOp = Node->getOperand(2);
677 Ops.push_back(LineOp); // line #
678 Ops.push_back(ColOp); // col #
679 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
680 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
682 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
683 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
684 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
685 Ops.push_back(DAG.getConstant(ID, MVT::i32));
686 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,&Ops[0],Ops.size());
689 Result = Tmp1; // chain
693 case TargetLowering::Legal:
694 if (Tmp1 != Node->getOperand(0) ||
695 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
696 SmallVector<SDOperand, 8> Ops;
698 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
699 Ops.push_back(Node->getOperand(1)); // line # must be legal.
700 Ops.push_back(Node->getOperand(2)); // col # must be legal.
702 // Otherwise promote them.
703 Ops.push_back(PromoteOp(Node->getOperand(1)));
704 Ops.push_back(PromoteOp(Node->getOperand(2)));
706 Ops.push_back(Node->getOperand(3)); // filename must be legal.
707 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
708 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
715 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
716 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
717 default: assert(0 && "This action is not supported yet!");
718 case TargetLowering::Legal:
719 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
720 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
721 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
722 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
723 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
728 case ISD::DEBUG_LABEL:
729 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
730 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
731 default: assert(0 && "This action is not supported yet!");
732 case TargetLowering::Legal:
733 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
734 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
735 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
741 // We know we don't need to expand constants here, constants only have one
742 // value and we check that it is fine above.
744 // FIXME: Maybe we should handle things like targets that don't support full
745 // 32-bit immediates?
747 case ISD::ConstantFP: {
748 // Spill FP immediates to the constant pool if the target cannot directly
749 // codegen them. Targets often have some immediate values that can be
750 // efficiently generated into an FP register without a load. We explicitly
751 // leave these constants as ConstantFP nodes for the target to deal with.
752 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
754 // Check to see if this FP immediate is already legal.
755 bool isLegal = false;
756 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
757 E = TLI.legal_fpimm_end(); I != E; ++I)
758 if (CFP->isExactlyValue(*I)) {
763 // If this is a legal constant, turn it into a TargetConstantFP node.
765 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
769 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
770 default: assert(0 && "This action is not supported yet!");
771 case TargetLowering::Custom:
772 Tmp3 = TLI.LowerOperation(Result, DAG);
778 case TargetLowering::Expand:
779 // Otherwise we need to spill the constant to memory.
782 // If a FP immediate is precise when represented as a float and if the
783 // target can do an extending load from float to double, we put it into
784 // the constant pool as a float, even if it's is statically typed as a
786 MVT::ValueType VT = CFP->getValueType(0);
787 bool isDouble = VT == MVT::f64;
788 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
789 Type::FloatTy, CFP->getValue());
790 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
791 // Only do this if the target has a native EXTLOAD instruction from
793 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
794 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
799 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
801 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
802 CPIdx, NULL, 0, MVT::f32);
804 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
809 case ISD::TokenFactor:
810 if (Node->getNumOperands() == 2) {
811 Tmp1 = LegalizeOp(Node->getOperand(0));
812 Tmp2 = LegalizeOp(Node->getOperand(1));
813 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
814 } else if (Node->getNumOperands() == 3) {
815 Tmp1 = LegalizeOp(Node->getOperand(0));
816 Tmp2 = LegalizeOp(Node->getOperand(1));
817 Tmp3 = LegalizeOp(Node->getOperand(2));
818 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
820 SmallVector<SDOperand, 8> Ops;
821 // Legalize the operands.
822 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
823 Ops.push_back(LegalizeOp(Node->getOperand(i)));
824 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
828 case ISD::FORMAL_ARGUMENTS:
830 // The only option for this is to custom lower it.
831 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
832 assert(Tmp3.Val && "Target didn't custom lower this node!");
833 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
834 "Lowering call/formal_arguments produced unexpected # results!");
836 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
837 // remember that we legalized all of them, so it doesn't get relegalized.
838 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
839 Tmp1 = LegalizeOp(Tmp3.getValue(i));
842 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
846 case ISD::BUILD_VECTOR:
847 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
848 default: assert(0 && "This action is not supported yet!");
849 case TargetLowering::Custom:
850 Tmp3 = TLI.LowerOperation(Result, DAG);
856 case TargetLowering::Expand:
857 Result = ExpandBUILD_VECTOR(Result.Val);
861 case ISD::INSERT_VECTOR_ELT:
862 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
863 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
864 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
865 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
867 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
868 Node->getValueType(0))) {
869 default: assert(0 && "This action is not supported yet!");
870 case TargetLowering::Legal:
872 case TargetLowering::Custom:
873 Tmp3 = TLI.LowerOperation(Result, DAG);
879 case TargetLowering::Expand: {
880 // If the insert index is a constant, codegen this as a scalar_to_vector,
881 // then a shuffle that inserts it into the right position in the vector.
882 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
883 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
884 Tmp1.getValueType(), Tmp2);
886 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
887 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
888 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT);
890 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
891 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
893 SmallVector<SDOperand, 8> ShufOps;
894 for (unsigned i = 0; i != NumElts; ++i) {
895 if (i != InsertPos->getValue())
896 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
898 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
900 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
901 &ShufOps[0], ShufOps.size());
903 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
904 Tmp1, ScVec, ShufMask);
905 Result = LegalizeOp(Result);
909 // If the target doesn't support this, we have to spill the input vector
910 // to a temporary stack slot, update the element, then reload it. This is
911 // badness. We could also load the value into a vector register (either
912 // with a "move to register" or "extload into register" instruction, then
913 // permute it into place, if the idx is a constant and if the idx is
914 // supported by the target.
915 MVT::ValueType VT = Tmp1.getValueType();
916 MVT::ValueType EltVT = Tmp2.getValueType();
917 MVT::ValueType IdxVT = Tmp3.getValueType();
918 MVT::ValueType PtrVT = TLI.getPointerTy();
919 SDOperand StackPtr = CreateStackTemporary(VT);
921 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
923 // Truncate or zero extend offset to target pointer type.
924 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
925 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
926 // Add the offset to the index.
927 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
928 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
929 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
930 // Store the scalar value.
931 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
932 // Load the updated vector.
933 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
938 case ISD::SCALAR_TO_VECTOR:
939 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
940 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
944 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
945 Result = DAG.UpdateNodeOperands(Result, Tmp1);
946 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
947 Node->getValueType(0))) {
948 default: assert(0 && "This action is not supported yet!");
949 case TargetLowering::Legal:
951 case TargetLowering::Custom:
952 Tmp3 = TLI.LowerOperation(Result, DAG);
958 case TargetLowering::Expand:
959 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
963 case ISD::VECTOR_SHUFFLE:
964 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
965 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
966 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
968 // Allow targets to custom lower the SHUFFLEs they support.
969 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
970 default: assert(0 && "Unknown operation action!");
971 case TargetLowering::Legal:
972 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
973 "vector shuffle should not be created if not legal!");
975 case TargetLowering::Custom:
976 Tmp3 = TLI.LowerOperation(Result, DAG);
982 case TargetLowering::Expand: {
983 MVT::ValueType VT = Node->getValueType(0);
984 MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
985 MVT::ValueType PtrVT = TLI.getPointerTy();
986 SDOperand Mask = Node->getOperand(2);
987 unsigned NumElems = Mask.getNumOperands();
988 SmallVector<SDOperand,8> Ops;
989 for (unsigned i = 0; i != NumElems; ++i) {
990 SDOperand Arg = Mask.getOperand(i);
991 if (Arg.getOpcode() == ISD::UNDEF) {
992 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
994 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
995 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
997 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
998 DAG.getConstant(Idx, PtrVT)));
1000 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1001 DAG.getConstant(Idx - NumElems, PtrVT)));
1004 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1007 case TargetLowering::Promote: {
1008 // Change base type to a different vector type.
1009 MVT::ValueType OVT = Node->getValueType(0);
1010 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1012 // Cast the two input vectors.
1013 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1014 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1016 // Convert the shuffle mask to the right # elements.
1017 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1018 assert(Tmp3.Val && "Shuffle not legal?");
1019 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1020 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1026 case ISD::EXTRACT_VECTOR_ELT:
1027 Tmp1 = LegalizeOp(Node->getOperand(0));
1028 Tmp2 = LegalizeOp(Node->getOperand(1));
1029 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1031 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
1032 Tmp1.getValueType())) {
1033 default: assert(0 && "This action is not supported yet!");
1034 case TargetLowering::Legal:
1036 case TargetLowering::Custom:
1037 Tmp3 = TLI.LowerOperation(Result, DAG);
1043 case TargetLowering::Expand:
1044 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1049 case ISD::VEXTRACT_VECTOR_ELT:
1050 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
1053 case ISD::CALLSEQ_START: {
1054 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1056 // Recursively Legalize all of the inputs of the call end that do not lead
1057 // to this call start. This ensures that any libcalls that need be inserted
1058 // are inserted *before* the CALLSEQ_START.
1059 {std::set<SDNode*> NodesLeadingTo;
1060 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1061 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1065 // Now that we legalized all of the inputs (which may have inserted
1066 // libcalls) create the new CALLSEQ_START node.
1067 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1069 // Merge in the last call, to ensure that this call start after the last
1071 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1072 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1073 Tmp1 = LegalizeOp(Tmp1);
1076 // Do not try to legalize the target-specific arguments (#1+).
1077 if (Tmp1 != Node->getOperand(0)) {
1078 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1080 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1083 // Remember that the CALLSEQ_START is legalized.
1084 AddLegalizedOperand(Op.getValue(0), Result);
1085 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1086 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1088 // Now that the callseq_start and all of the non-call nodes above this call
1089 // sequence have been legalized, legalize the call itself. During this
1090 // process, no libcalls can/will be inserted, guaranteeing that no calls
1092 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1093 SDOperand InCallSEQ = LastCALLSEQ_END;
1094 // Note that we are selecting this call!
1095 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1096 IsLegalizingCall = true;
1098 // Legalize the call, starting from the CALLSEQ_END.
1099 LegalizeOp(LastCALLSEQ_END);
1100 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1103 case ISD::CALLSEQ_END:
1104 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1105 // will cause this node to be legalized as well as handling libcalls right.
1106 if (LastCALLSEQ_END.Val != Node) {
1107 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1108 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1109 assert(I != LegalizedNodes.end() &&
1110 "Legalizing the call start should have legalized this node!");
1114 // Otherwise, the call start has been legalized and everything is going
1115 // according to plan. Just legalize ourselves normally here.
1116 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1117 // Do not try to legalize the target-specific arguments (#1+), except for
1118 // an optional flag input.
1119 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1120 if (Tmp1 != Node->getOperand(0)) {
1121 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1123 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1126 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1127 if (Tmp1 != Node->getOperand(0) ||
1128 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1129 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1132 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1135 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1136 // This finishes up call legalization.
1137 IsLegalizingCall = false;
1139 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1140 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1141 if (Node->getNumValues() == 2)
1142 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1143 return Result.getValue(Op.ResNo);
1144 case ISD::DYNAMIC_STACKALLOC: {
1145 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1146 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1147 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1148 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1150 Tmp1 = Result.getValue(0);
1151 Tmp2 = Result.getValue(1);
1152 switch (TLI.getOperationAction(Node->getOpcode(),
1153 Node->getValueType(0))) {
1154 default: assert(0 && "This action is not supported yet!");
1155 case TargetLowering::Expand: {
1156 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1157 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1158 " not tell us which reg is the stack pointer!");
1159 SDOperand Chain = Tmp1.getOperand(0);
1160 SDOperand Size = Tmp2.getOperand(1);
1161 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1162 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1163 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1164 Tmp1 = LegalizeOp(Tmp1);
1165 Tmp2 = LegalizeOp(Tmp2);
1168 case TargetLowering::Custom:
1169 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1171 Tmp1 = LegalizeOp(Tmp3);
1172 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1175 case TargetLowering::Legal:
1178 // Since this op produce two values, make sure to remember that we
1179 // legalized both of them.
1180 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1181 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1182 return Op.ResNo ? Tmp2 : Tmp1;
1184 case ISD::INLINEASM: {
1185 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1186 bool Changed = false;
1187 // Legalize all of the operands of the inline asm, in case they are nodes
1188 // that need to be expanded or something. Note we skip the asm string and
1189 // all of the TargetConstant flags.
1190 SDOperand Op = LegalizeOp(Ops[0]);
1191 Changed = Op != Ops[0];
1194 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1195 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1196 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1197 for (++i; NumVals; ++i, --NumVals) {
1198 SDOperand Op = LegalizeOp(Ops[i]);
1207 Op = LegalizeOp(Ops.back());
1208 Changed |= Op != Ops.back();
1213 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1215 // INLINE asm returns a chain and flag, make sure to add both to the map.
1216 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1217 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1218 return Result.getValue(Op.ResNo);
1221 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1222 // Ensure that libcalls are emitted before a branch.
1223 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1224 Tmp1 = LegalizeOp(Tmp1);
1225 LastCALLSEQ_END = DAG.getEntryNode();
1227 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1230 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1231 // Ensure that libcalls are emitted before a branch.
1232 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1233 Tmp1 = LegalizeOp(Tmp1);
1234 LastCALLSEQ_END = DAG.getEntryNode();
1236 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1237 default: assert(0 && "Indirect target must be legal type (pointer)!");
1239 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1242 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1245 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1246 // Ensure that libcalls are emitted before a branch.
1247 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1248 Tmp1 = LegalizeOp(Tmp1);
1249 LastCALLSEQ_END = DAG.getEntryNode();
1251 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1252 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1254 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1255 default: assert(0 && "This action is not supported yet!");
1256 case TargetLowering::Legal: break;
1257 case TargetLowering::Custom:
1258 Tmp1 = TLI.LowerOperation(Result, DAG);
1259 if (Tmp1.Val) Result = Tmp1;
1261 case TargetLowering::Expand: {
1262 SDOperand Chain = Result.getOperand(0);
1263 SDOperand Table = Result.getOperand(1);
1264 SDOperand Index = Result.getOperand(2);
1266 MVT::ValueType PTy = TLI.getPointerTy();
1267 bool isPIC = TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_;
1268 // PIC jump table entries are 32-bit values.
1269 unsigned EntrySize = isPIC ? 4 : MVT::getSizeInBits(PTy)/8;
1270 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1271 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1272 SDOperand LD = DAG.getLoad(isPIC ? MVT::i32 : PTy, Chain, Addr, NULL, 0);
1274 // For PIC, the sequence is:
1275 // BRIND(load(Jumptable + index) + RelocBase)
1276 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
1278 if (TLI.usesGlobalOffsetTable())
1279 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
1282 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
1283 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
1284 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1286 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD);
1292 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1293 // Ensure that libcalls are emitted before a return.
1294 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1295 Tmp1 = LegalizeOp(Tmp1);
1296 LastCALLSEQ_END = DAG.getEntryNode();
1298 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1299 case Expand: assert(0 && "It's impossible to expand bools");
1301 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1304 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1308 // Basic block destination (Op#2) is always legal.
1309 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1311 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1312 default: assert(0 && "This action is not supported yet!");
1313 case TargetLowering::Legal: break;
1314 case TargetLowering::Custom:
1315 Tmp1 = TLI.LowerOperation(Result, DAG);
1316 if (Tmp1.Val) Result = Tmp1;
1318 case TargetLowering::Expand:
1319 // Expand brcond's setcc into its constituent parts and create a BR_CC
1321 if (Tmp2.getOpcode() == ISD::SETCC) {
1322 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1323 Tmp2.getOperand(0), Tmp2.getOperand(1),
1324 Node->getOperand(2));
1326 // Make sure the condition is either zero or one. It may have been
1327 // promoted from something else.
1328 unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType());
1329 if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1))
1330 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1332 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1333 DAG.getCondCode(ISD::SETNE), Tmp2,
1334 DAG.getConstant(0, Tmp2.getValueType()),
1335 Node->getOperand(2));
1341 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1342 // Ensure that libcalls are emitted before a branch.
1343 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1344 Tmp1 = LegalizeOp(Tmp1);
1345 LastCALLSEQ_END = DAG.getEntryNode();
1347 Tmp2 = Node->getOperand(2); // LHS
1348 Tmp3 = Node->getOperand(3); // RHS
1349 Tmp4 = Node->getOperand(1); // CC
1351 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1353 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1354 // the LHS is a legal SETCC itself. In this case, we need to compare
1355 // the result against zero to select between true and false values.
1356 if (Tmp3.Val == 0) {
1357 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1358 Tmp4 = DAG.getCondCode(ISD::SETNE);
1361 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1362 Node->getOperand(4));
1364 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1365 default: assert(0 && "Unexpected action for BR_CC!");
1366 case TargetLowering::Legal: break;
1367 case TargetLowering::Custom:
1368 Tmp4 = TLI.LowerOperation(Result, DAG);
1369 if (Tmp4.Val) Result = Tmp4;
1374 LoadSDNode *LD = cast<LoadSDNode>(Node);
1375 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1376 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1378 ISD::LoadExtType ExtType = LD->getExtensionType();
1379 if (ExtType == ISD::NON_EXTLOAD) {
1380 MVT::ValueType VT = Node->getValueType(0);
1381 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1382 Tmp3 = Result.getValue(0);
1383 Tmp4 = Result.getValue(1);
1385 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1386 default: assert(0 && "This action is not supported yet!");
1387 case TargetLowering::Legal: break;
1388 case TargetLowering::Custom:
1389 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1391 Tmp3 = LegalizeOp(Tmp1);
1392 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1395 case TargetLowering::Promote: {
1396 // Only promote a load of vector type to another.
1397 assert(MVT::isVector(VT) && "Cannot promote this load!");
1398 // Change base type to a different vector type.
1399 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1401 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1402 LD->getSrcValueOffset());
1403 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1404 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1408 // Since loads produce two values, make sure to remember that we
1409 // legalized both of them.
1410 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1411 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1412 return Op.ResNo ? Tmp4 : Tmp3;
1414 MVT::ValueType SrcVT = LD->getLoadedVT();
1415 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1416 default: assert(0 && "This action is not supported yet!");
1417 case TargetLowering::Promote:
1418 assert(SrcVT == MVT::i1 &&
1419 "Can only promote extending LOAD from i1 -> i8!");
1420 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1421 LD->getSrcValue(), LD->getSrcValueOffset(),
1423 Tmp1 = Result.getValue(0);
1424 Tmp2 = Result.getValue(1);
1426 case TargetLowering::Custom:
1429 case TargetLowering::Legal:
1430 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1431 Tmp1 = Result.getValue(0);
1432 Tmp2 = Result.getValue(1);
1435 Tmp3 = TLI.LowerOperation(Result, DAG);
1437 Tmp1 = LegalizeOp(Tmp3);
1438 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1442 case TargetLowering::Expand:
1443 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1444 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1445 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1446 LD->getSrcValueOffset());
1447 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1448 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1449 Tmp2 = LegalizeOp(Load.getValue(1));
1452 assert(ExtType != ISD::EXTLOAD && "EXTLOAD should always be supported!");
1453 // Turn the unsupported load into an EXTLOAD followed by an explicit
1454 // zero/sign extend inreg.
1455 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1456 Tmp1, Tmp2, LD->getSrcValue(),
1457 LD->getSrcValueOffset(), SrcVT);
1459 if (ExtType == ISD::SEXTLOAD)
1460 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1461 Result, DAG.getValueType(SrcVT));
1463 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1464 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1465 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1468 // Since loads produce two values, make sure to remember that we legalized
1470 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1471 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1472 return Op.ResNo ? Tmp2 : Tmp1;
1475 case ISD::EXTRACT_ELEMENT: {
1476 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1477 switch (getTypeAction(OpTy)) {
1478 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1480 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1482 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1483 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1484 TLI.getShiftAmountTy()));
1485 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1488 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1489 Node->getOperand(0));
1493 // Get both the low and high parts.
1494 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1495 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1496 Result = Tmp2; // 1 -> Hi
1498 Result = Tmp1; // 0 -> Lo
1504 case ISD::CopyToReg:
1505 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1507 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1508 "Register type must be legal!");
1509 // Legalize the incoming value (must be a legal type).
1510 Tmp2 = LegalizeOp(Node->getOperand(2));
1511 if (Node->getNumValues() == 1) {
1512 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1514 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1515 if (Node->getNumOperands() == 4) {
1516 Tmp3 = LegalizeOp(Node->getOperand(3));
1517 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1520 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1523 // Since this produces two values, make sure to remember that we legalized
1525 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1526 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1532 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1534 // Ensure that libcalls are emitted before a return.
1535 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1536 Tmp1 = LegalizeOp(Tmp1);
1537 LastCALLSEQ_END = DAG.getEntryNode();
1539 switch (Node->getNumOperands()) {
1541 Tmp2 = Node->getOperand(1);
1542 Tmp3 = Node->getOperand(2); // Signness
1543 switch (getTypeAction(Tmp2.getValueType())) {
1545 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1548 if (Tmp2.getValueType() != MVT::Vector) {
1550 ExpandOp(Tmp2, Lo, Hi);
1551 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1552 Result = LegalizeOp(Result);
1554 SDNode *InVal = Tmp2.Val;
1556 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1557 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1559 // Figure out if there is a Packed type corresponding to this Vector
1560 // type. If so, convert to the packed type.
1561 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1562 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1563 // Turn this into a return of the packed type.
1564 Tmp2 = PackVectorOp(Tmp2, TVT);
1565 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1566 } else if (NumElems == 1) {
1567 // Turn this into a return of the scalar type.
1568 Tmp2 = PackVectorOp(Tmp2, EVT);
1569 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1571 // FIXME: Returns of gcc generic vectors smaller than a legal type
1572 // should be returned in integer registers!
1574 // The scalarized value type may not be legal, e.g. it might require
1575 // promotion or expansion. Relegalize the return.
1576 Result = LegalizeOp(Result);
1578 // FIXME: Returns of gcc generic vectors larger than a legal vector
1579 // type should be returned by reference!
1581 SplitVectorOp(Tmp2, Lo, Hi);
1582 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1583 Result = LegalizeOp(Result);
1588 Tmp2 = PromoteOp(Node->getOperand(1));
1589 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1590 Result = LegalizeOp(Result);
1595 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1597 default: { // ret <values>
1598 SmallVector<SDOperand, 8> NewValues;
1599 NewValues.push_back(Tmp1);
1600 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1601 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1603 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1604 NewValues.push_back(Node->getOperand(i+1));
1608 assert(Node->getOperand(i).getValueType() != MVT::Vector &&
1609 "FIXME: TODO: implement returning non-legal vector types!");
1610 ExpandOp(Node->getOperand(i), Lo, Hi);
1611 NewValues.push_back(Lo);
1612 NewValues.push_back(Node->getOperand(i+1));
1613 NewValues.push_back(Hi);
1614 NewValues.push_back(Node->getOperand(i+1));
1618 assert(0 && "Can't promote multiple return value yet!");
1621 if (NewValues.size() == Node->getNumOperands())
1622 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1624 Result = DAG.getNode(ISD::RET, MVT::Other,
1625 &NewValues[0], NewValues.size());
1630 if (Result.getOpcode() == ISD::RET) {
1631 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1632 default: assert(0 && "This action is not supported yet!");
1633 case TargetLowering::Legal: break;
1634 case TargetLowering::Custom:
1635 Tmp1 = TLI.LowerOperation(Result, DAG);
1636 if (Tmp1.Val) Result = Tmp1;
1642 StoreSDNode *ST = cast<StoreSDNode>(Node);
1643 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1644 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1646 if (!ST->isTruncatingStore()) {
1647 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1648 // FIXME: We shouldn't do this for TargetConstantFP's.
1649 // FIXME: move this to the DAG Combiner!
1650 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(ST->getValue())) {
1651 if (CFP->getValueType(0) == MVT::f32) {
1652 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1654 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1655 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1657 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1658 ST->getSrcValueOffset());
1662 switch (getTypeAction(ST->getStoredVT())) {
1664 Tmp3 = LegalizeOp(ST->getValue());
1665 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1668 MVT::ValueType VT = Tmp3.getValueType();
1669 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1670 default: assert(0 && "This action is not supported yet!");
1671 case TargetLowering::Legal: break;
1672 case TargetLowering::Custom:
1673 Tmp1 = TLI.LowerOperation(Result, DAG);
1674 if (Tmp1.Val) Result = Tmp1;
1676 case TargetLowering::Promote:
1677 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1678 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1679 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1680 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
1681 ST->getSrcValue(), ST->getSrcValueOffset());
1687 // Truncate the value and store the result.
1688 Tmp3 = PromoteOp(ST->getValue());
1689 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1690 ST->getSrcValueOffset(), ST->getStoredVT());
1694 unsigned IncrementSize = 0;
1697 // If this is a vector type, then we have to calculate the increment as
1698 // the product of the element size in bytes, and the number of elements
1699 // in the high half of the vector.
1700 if (ST->getValue().getValueType() == MVT::Vector) {
1701 SDNode *InVal = ST->getValue().Val;
1703 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1704 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1706 // Figure out if there is a Packed type corresponding to this Vector
1707 // type. If so, convert to the packed type.
1708 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1709 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1710 // Turn this into a normal store of the packed type.
1711 Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1712 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1713 ST->getSrcValueOffset());
1714 Result = LegalizeOp(Result);
1716 } else if (NumElems == 1) {
1717 // Turn this into a normal store of the scalar type.
1718 Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1719 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1720 ST->getSrcValueOffset());
1721 // The scalarized value type may not be legal, e.g. it might require
1722 // promotion or expansion. Relegalize the scalar store.
1723 Result = LegalizeOp(Result);
1726 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1727 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1730 ExpandOp(Node->getOperand(1), Lo, Hi);
1731 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1733 if (!TLI.isLittleEndian())
1737 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
1738 ST->getSrcValueOffset());
1739 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1740 getIntPtrConstant(IncrementSize));
1741 assert(isTypeLegal(Tmp2.getValueType()) &&
1742 "Pointers must be legal!");
1743 // FIXME: This sets the srcvalue of both halves to be the same, which is
1745 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
1746 ST->getSrcValueOffset());
1747 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1752 assert(isTypeLegal(ST->getValue().getValueType()) &&
1753 "Cannot handle illegal TRUNCSTORE yet!");
1754 Tmp3 = LegalizeOp(ST->getValue());
1756 // The only promote case we handle is TRUNCSTORE:i1 X into
1757 // -> TRUNCSTORE:i8 (and X, 1)
1758 if (ST->getStoredVT() == MVT::i1 &&
1759 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
1760 // Promote the bool to a mask then store.
1761 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
1762 DAG.getConstant(1, Tmp3.getValueType()));
1763 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1764 ST->getSrcValueOffset(), MVT::i8);
1765 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1766 Tmp2 != ST->getBasePtr()) {
1767 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1771 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
1772 switch (TLI.getStoreXAction(StVT)) {
1773 default: assert(0 && "This action is not supported yet!");
1774 case TargetLowering::Legal: break;
1775 case TargetLowering::Custom:
1776 Tmp1 = TLI.LowerOperation(Result, DAG);
1777 if (Tmp1.Val) Result = Tmp1;
1784 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1785 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1787 case ISD::STACKSAVE:
1788 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1789 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1790 Tmp1 = Result.getValue(0);
1791 Tmp2 = Result.getValue(1);
1793 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1794 default: assert(0 && "This action is not supported yet!");
1795 case TargetLowering::Legal: break;
1796 case TargetLowering::Custom:
1797 Tmp3 = TLI.LowerOperation(Result, DAG);
1799 Tmp1 = LegalizeOp(Tmp3);
1800 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1803 case TargetLowering::Expand:
1804 // Expand to CopyFromReg if the target set
1805 // StackPointerRegisterToSaveRestore.
1806 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1807 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1808 Node->getValueType(0));
1809 Tmp2 = Tmp1.getValue(1);
1811 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1812 Tmp2 = Node->getOperand(0);
1817 // Since stacksave produce two values, make sure to remember that we
1818 // legalized both of them.
1819 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1820 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1821 return Op.ResNo ? Tmp2 : Tmp1;
1823 case ISD::STACKRESTORE:
1824 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1825 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1826 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1828 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1829 default: assert(0 && "This action is not supported yet!");
1830 case TargetLowering::Legal: break;
1831 case TargetLowering::Custom:
1832 Tmp1 = TLI.LowerOperation(Result, DAG);
1833 if (Tmp1.Val) Result = Tmp1;
1835 case TargetLowering::Expand:
1836 // Expand to CopyToReg if the target set
1837 // StackPointerRegisterToSaveRestore.
1838 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1839 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1847 case ISD::READCYCLECOUNTER:
1848 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1849 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1851 // Since rdcc produce two values, make sure to remember that we legalized
1853 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1854 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1858 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1859 case Expand: assert(0 && "It's impossible to expand bools");
1861 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1864 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1867 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1868 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1870 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1872 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1873 default: assert(0 && "This action is not supported yet!");
1874 case TargetLowering::Legal: break;
1875 case TargetLowering::Custom: {
1876 Tmp1 = TLI.LowerOperation(Result, DAG);
1877 if (Tmp1.Val) Result = Tmp1;
1880 case TargetLowering::Expand:
1881 if (Tmp1.getOpcode() == ISD::SETCC) {
1882 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1884 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1886 // Make sure the condition is either zero or one. It may have been
1887 // promoted from something else.
1888 unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType());
1889 if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1))
1890 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1891 Result = DAG.getSelectCC(Tmp1,
1892 DAG.getConstant(0, Tmp1.getValueType()),
1893 Tmp2, Tmp3, ISD::SETNE);
1896 case TargetLowering::Promote: {
1897 MVT::ValueType NVT =
1898 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1899 unsigned ExtOp, TruncOp;
1900 if (MVT::isVector(Tmp2.getValueType())) {
1901 ExtOp = ISD::BIT_CONVERT;
1902 TruncOp = ISD::BIT_CONVERT;
1903 } else if (MVT::isInteger(Tmp2.getValueType())) {
1904 ExtOp = ISD::ANY_EXTEND;
1905 TruncOp = ISD::TRUNCATE;
1907 ExtOp = ISD::FP_EXTEND;
1908 TruncOp = ISD::FP_ROUND;
1910 // Promote each of the values to the new type.
1911 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1912 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1913 // Perform the larger operation, then round down.
1914 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1915 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1920 case ISD::SELECT_CC: {
1921 Tmp1 = Node->getOperand(0); // LHS
1922 Tmp2 = Node->getOperand(1); // RHS
1923 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1924 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1925 SDOperand CC = Node->getOperand(4);
1927 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
1929 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1930 // the LHS is a legal SETCC itself. In this case, we need to compare
1931 // the result against zero to select between true and false values.
1932 if (Tmp2.Val == 0) {
1933 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1934 CC = DAG.getCondCode(ISD::SETNE);
1936 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
1938 // Everything is legal, see if we should expand this op or something.
1939 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
1940 default: assert(0 && "This action is not supported yet!");
1941 case TargetLowering::Legal: break;
1942 case TargetLowering::Custom:
1943 Tmp1 = TLI.LowerOperation(Result, DAG);
1944 if (Tmp1.Val) Result = Tmp1;
1950 Tmp1 = Node->getOperand(0);
1951 Tmp2 = Node->getOperand(1);
1952 Tmp3 = Node->getOperand(2);
1953 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
1955 // If we had to Expand the SetCC operands into a SELECT node, then it may
1956 // not always be possible to return a true LHS & RHS. In this case, just
1957 // return the value we legalized, returned in the LHS
1958 if (Tmp2.Val == 0) {
1963 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
1964 default: assert(0 && "Cannot handle this action for SETCC yet!");
1965 case TargetLowering::Custom:
1968 case TargetLowering::Legal:
1969 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1971 Tmp3 = TLI.LowerOperation(Result, DAG);
1972 if (Tmp3.Val) Result = Tmp3;
1975 case TargetLowering::Promote: {
1976 // First step, figure out the appropriate operation to use.
1977 // Allow SETCC to not be supported for all legal data types
1978 // Mostly this targets FP
1979 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1980 MVT::ValueType OldVT = NewInTy;
1982 // Scan for the appropriate larger type to use.
1984 NewInTy = (MVT::ValueType)(NewInTy+1);
1986 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1987 "Fell off of the edge of the integer world");
1988 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1989 "Fell off of the edge of the floating point world");
1991 // If the target supports SETCC of this type, use it.
1992 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
1995 if (MVT::isInteger(NewInTy))
1996 assert(0 && "Cannot promote Legal Integer SETCC yet");
1998 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1999 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2001 Tmp1 = LegalizeOp(Tmp1);
2002 Tmp2 = LegalizeOp(Tmp2);
2003 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2004 Result = LegalizeOp(Result);
2007 case TargetLowering::Expand:
2008 // Expand a setcc node into a select_cc of the same condition, lhs, and
2009 // rhs that selects between const 1 (true) and const 0 (false).
2010 MVT::ValueType VT = Node->getValueType(0);
2011 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2012 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2013 Node->getOperand(2));
2019 case ISD::MEMMOVE: {
2020 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2021 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2023 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2024 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2025 case Expand: assert(0 && "Cannot expand a byte!");
2027 Tmp3 = LegalizeOp(Node->getOperand(2));
2030 Tmp3 = PromoteOp(Node->getOperand(2));
2034 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2038 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2040 // Length is too big, just take the lo-part of the length.
2042 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2046 Tmp4 = LegalizeOp(Node->getOperand(3));
2049 Tmp4 = PromoteOp(Node->getOperand(3));
2054 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2055 case Expand: assert(0 && "Cannot expand this yet!");
2057 Tmp5 = LegalizeOp(Node->getOperand(4));
2060 Tmp5 = PromoteOp(Node->getOperand(4));
2064 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2065 default: assert(0 && "This action not implemented for this operation!");
2066 case TargetLowering::Custom:
2069 case TargetLowering::Legal:
2070 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2072 Tmp1 = TLI.LowerOperation(Result, DAG);
2073 if (Tmp1.Val) Result = Tmp1;
2076 case TargetLowering::Expand: {
2077 // Otherwise, the target does not support this operation. Lower the
2078 // operation to an explicit libcall as appropriate.
2079 MVT::ValueType IntPtr = TLI.getPointerTy();
2080 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2081 std::vector<std::pair<SDOperand, const Type*> > Args;
2083 const char *FnName = 0;
2084 if (Node->getOpcode() == ISD::MEMSET) {
2085 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2086 // Extend the (previously legalized) ubyte argument to be an int value
2088 if (Tmp3.getValueType() > MVT::i32)
2089 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2091 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2092 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
2093 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2096 } else if (Node->getOpcode() == ISD::MEMCPY ||
2097 Node->getOpcode() == ISD::MEMMOVE) {
2098 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2099 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
2100 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2101 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2103 assert(0 && "Unknown op!");
2106 std::pair<SDOperand,SDOperand> CallResult =
2107 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
2108 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2109 Result = CallResult.second;
2116 case ISD::SHL_PARTS:
2117 case ISD::SRA_PARTS:
2118 case ISD::SRL_PARTS: {
2119 SmallVector<SDOperand, 8> Ops;
2120 bool Changed = false;
2121 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2122 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2123 Changed |= Ops.back() != Node->getOperand(i);
2126 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2128 switch (TLI.getOperationAction(Node->getOpcode(),
2129 Node->getValueType(0))) {
2130 default: assert(0 && "This action is not supported yet!");
2131 case TargetLowering::Legal: break;
2132 case TargetLowering::Custom:
2133 Tmp1 = TLI.LowerOperation(Result, DAG);
2135 SDOperand Tmp2, RetVal(0, 0);
2136 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2137 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2138 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2142 assert(RetVal.Val && "Illegal result number");
2148 // Since these produce multiple values, make sure to remember that we
2149 // legalized all of them.
2150 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2151 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2152 return Result.getValue(Op.ResNo);
2173 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2174 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2175 case Expand: assert(0 && "Not possible");
2177 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2180 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2184 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2186 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2187 default: assert(0 && "BinOp legalize operation not supported");
2188 case TargetLowering::Legal: break;
2189 case TargetLowering::Custom:
2190 Tmp1 = TLI.LowerOperation(Result, DAG);
2191 if (Tmp1.Val) Result = Tmp1;
2193 case TargetLowering::Expand: {
2194 if (Node->getValueType(0) == MVT::i32) {
2195 switch (Node->getOpcode()) {
2196 default: assert(0 && "Do not know how to expand this integer BinOp!");
2199 const char *FnName = Node->getOpcode() == ISD::UDIV
2200 ? "__udivsi3" : "__divsi3";
2202 Result = ExpandLibCall(FnName, Node, Dummy);
2207 assert(MVT::isVector(Node->getValueType(0)) &&
2208 "Cannot expand this binary operator!");
2209 // Expand the operation into a bunch of nasty scalar code.
2210 SmallVector<SDOperand, 8> Ops;
2211 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
2212 MVT::ValueType PtrVT = TLI.getPointerTy();
2213 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2215 SDOperand Idx = DAG.getConstant(i, PtrVT);
2216 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2217 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2218 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2220 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2221 &Ops[0], Ops.size());
2224 case TargetLowering::Promote: {
2225 switch (Node->getOpcode()) {
2226 default: assert(0 && "Do not know how to promote this BinOp!");
2230 MVT::ValueType OVT = Node->getValueType(0);
2231 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2232 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2233 // Bit convert each of the values to the new type.
2234 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2235 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2236 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2237 // Bit convert the result back the original type.
2238 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2246 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2247 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2248 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2249 case Expand: assert(0 && "Not possible");
2251 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2254 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2258 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2260 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2261 default: assert(0 && "Operation not supported");
2262 case TargetLowering::Custom:
2263 Tmp1 = TLI.LowerOperation(Result, DAG);
2264 if (Tmp1.Val) Result = Tmp1;
2266 case TargetLowering::Legal: break;
2267 case TargetLowering::Expand:
2268 // If this target supports fabs/fneg natively, do this efficiently.
2269 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
2270 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
2271 // Get the sign bit of the RHS.
2272 MVT::ValueType IVT =
2273 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2274 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2275 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2276 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2277 // Get the absolute value of the result.
2278 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2279 // Select between the nabs and abs value based on the sign bit of
2281 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2282 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2285 Result = LegalizeOp(Result);
2289 // Otherwise, do bitwise ops!
2291 // copysign -> copysignf/copysign libcall.
2293 if (Node->getValueType(0) == MVT::f32) {
2294 FnName = "copysignf";
2295 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type.
2296 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2297 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2));
2299 FnName = "copysign";
2300 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type.
2301 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2302 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2));
2305 Result = ExpandLibCall(FnName, Node, Dummy);
2312 Tmp1 = LegalizeOp(Node->getOperand(0));
2313 Tmp2 = LegalizeOp(Node->getOperand(1));
2314 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2315 // Since this produces two values, make sure to remember that we legalized
2317 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2318 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2323 Tmp1 = LegalizeOp(Node->getOperand(0));
2324 Tmp2 = LegalizeOp(Node->getOperand(1));
2325 Tmp3 = LegalizeOp(Node->getOperand(2));
2326 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2327 // Since this produces two values, make sure to remember that we legalized
2329 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2330 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2333 case ISD::BUILD_PAIR: {
2334 MVT::ValueType PairTy = Node->getValueType(0);
2335 // TODO: handle the case where the Lo and Hi operands are not of legal type
2336 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2337 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2338 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2339 case TargetLowering::Promote:
2340 case TargetLowering::Custom:
2341 assert(0 && "Cannot promote/custom this yet!");
2342 case TargetLowering::Legal:
2343 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2344 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2346 case TargetLowering::Expand:
2347 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2348 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2349 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2350 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2351 TLI.getShiftAmountTy()));
2352 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2361 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2362 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2364 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2365 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2366 case TargetLowering::Custom:
2369 case TargetLowering::Legal:
2370 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2372 Tmp1 = TLI.LowerOperation(Result, DAG);
2373 if (Tmp1.Val) Result = Tmp1;
2376 case TargetLowering::Expand:
2377 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2378 if (MVT::isInteger(Node->getValueType(0))) {
2379 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2380 TargetLowering::Legal) {
2382 MVT::ValueType VT = Node->getValueType(0);
2383 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2384 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2385 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2387 assert(Node->getValueType(0) == MVT::i32 &&
2388 "Cannot expand this binary operator!");
2389 const char *FnName = Node->getOpcode() == ISD::UREM
2390 ? "__umodsi3" : "__modsi3";
2392 Result = ExpandLibCall(FnName, Node, Dummy);
2395 // Floating point mod -> fmod libcall.
2396 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
2398 Result = ExpandLibCall(FnName, Node, Dummy);
2404 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2405 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2407 MVT::ValueType VT = Node->getValueType(0);
2408 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2409 default: assert(0 && "This action is not supported yet!");
2410 case TargetLowering::Custom:
2413 case TargetLowering::Legal:
2414 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2415 Result = Result.getValue(0);
2416 Tmp1 = Result.getValue(1);
2419 Tmp2 = TLI.LowerOperation(Result, DAG);
2421 Result = LegalizeOp(Tmp2);
2422 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2426 case TargetLowering::Expand: {
2427 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2428 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2429 SV->getValue(), SV->getOffset());
2430 // Increment the pointer, VAList, to the next vaarg
2431 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2432 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2433 TLI.getPointerTy()));
2434 // Store the incremented VAList to the legalized pointer
2435 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
2437 // Load the actual argument out of the pointer VAList
2438 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2439 Tmp1 = LegalizeOp(Result.getValue(1));
2440 Result = LegalizeOp(Result);
2444 // Since VAARG produces two values, make sure to remember that we
2445 // legalized both of them.
2446 AddLegalizedOperand(SDOperand(Node, 0), Result);
2447 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2448 return Op.ResNo ? Tmp1 : Result;
2452 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2453 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2454 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2456 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2457 default: assert(0 && "This action is not supported yet!");
2458 case TargetLowering::Custom:
2461 case TargetLowering::Legal:
2462 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2463 Node->getOperand(3), Node->getOperand(4));
2465 Tmp1 = TLI.LowerOperation(Result, DAG);
2466 if (Tmp1.Val) Result = Tmp1;
2469 case TargetLowering::Expand:
2470 // This defaults to loading a pointer from the input and storing it to the
2471 // output, returning the chain.
2472 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
2473 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
2474 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
2476 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
2483 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2484 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2486 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2487 default: assert(0 && "This action is not supported yet!");
2488 case TargetLowering::Custom:
2491 case TargetLowering::Legal:
2492 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2494 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2495 if (Tmp1.Val) Result = Tmp1;
2498 case TargetLowering::Expand:
2499 Result = Tmp1; // Default to a no-op, return the chain
2505 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2506 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2508 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2510 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2511 default: assert(0 && "This action is not supported yet!");
2512 case TargetLowering::Legal: break;
2513 case TargetLowering::Custom:
2514 Tmp1 = TLI.LowerOperation(Result, DAG);
2515 if (Tmp1.Val) Result = Tmp1;
2522 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2523 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2525 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2526 "Cannot handle this yet!");
2527 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2531 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2532 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2533 case TargetLowering::Custom:
2534 assert(0 && "Cannot custom legalize this yet!");
2535 case TargetLowering::Legal:
2536 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2538 case TargetLowering::Promote: {
2539 MVT::ValueType OVT = Tmp1.getValueType();
2540 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2541 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2543 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2544 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2545 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2546 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2549 case TargetLowering::Expand:
2550 Result = ExpandBSWAP(Tmp1);
2558 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2559 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2560 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2561 case TargetLowering::Legal:
2562 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2564 case TargetLowering::Promote: {
2565 MVT::ValueType OVT = Tmp1.getValueType();
2566 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2568 // Zero extend the argument.
2569 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2570 // Perform the larger operation, then subtract if needed.
2571 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2572 switch (Node->getOpcode()) {
2577 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2578 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2579 DAG.getConstant(getSizeInBits(NVT), NVT),
2581 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2582 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2585 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2586 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2587 DAG.getConstant(getSizeInBits(NVT) -
2588 getSizeInBits(OVT), NVT));
2593 case TargetLowering::Expand:
2594 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2605 Tmp1 = LegalizeOp(Node->getOperand(0));
2606 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2607 case TargetLowering::Promote:
2608 case TargetLowering::Custom:
2611 case TargetLowering::Legal:
2612 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2614 Tmp1 = TLI.LowerOperation(Result, DAG);
2615 if (Tmp1.Val) Result = Tmp1;
2618 case TargetLowering::Expand:
2619 switch (Node->getOpcode()) {
2620 default: assert(0 && "Unreachable!");
2622 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2623 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2624 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2627 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2628 MVT::ValueType VT = Node->getValueType(0);
2629 Tmp2 = DAG.getConstantFP(0.0, VT);
2630 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2631 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2632 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2638 MVT::ValueType VT = Node->getValueType(0);
2639 const char *FnName = 0;
2640 switch(Node->getOpcode()) {
2641 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2642 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2643 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2644 default: assert(0 && "Unreachable!");
2647 Result = ExpandLibCall(FnName, Node, Dummy);
2655 // We always lower FPOWI into a libcall. No target support it yet.
2656 const char *FnName = Node->getValueType(0) == MVT::f32
2657 ? "__powisf2" : "__powidf2";
2659 Result = ExpandLibCall(FnName, Node, Dummy);
2662 case ISD::BIT_CONVERT:
2663 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2664 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2666 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2667 Node->getOperand(0).getValueType())) {
2668 default: assert(0 && "Unknown operation action!");
2669 case TargetLowering::Expand:
2670 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2672 case TargetLowering::Legal:
2673 Tmp1 = LegalizeOp(Node->getOperand(0));
2674 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2679 case ISD::VBIT_CONVERT: {
2680 assert(Op.getOperand(0).getValueType() == MVT::Vector &&
2681 "Can only have VBIT_CONVERT where input or output is MVT::Vector!");
2683 // The input has to be a vector type, we have to either scalarize it, pack
2684 // it, or convert it based on whether the input vector type is legal.
2685 SDNode *InVal = Node->getOperand(0).Val;
2687 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
2688 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
2690 // Figure out if there is a Packed type corresponding to this Vector
2691 // type. If so, convert to the packed type.
2692 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2693 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
2694 // Turn this into a bit convert of the packed input.
2695 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2696 PackVectorOp(Node->getOperand(0), TVT));
2698 } else if (NumElems == 1) {
2699 // Turn this into a bit convert of the scalar input.
2700 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2701 PackVectorOp(Node->getOperand(0), EVT));
2704 // FIXME: UNIMP! Store then reload
2705 assert(0 && "Cast from unsupported vector type not implemented yet!");
2709 // Conversion operators. The source and destination have different types.
2710 case ISD::SINT_TO_FP:
2711 case ISD::UINT_TO_FP: {
2712 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2713 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2715 switch (TLI.getOperationAction(Node->getOpcode(),
2716 Node->getOperand(0).getValueType())) {
2717 default: assert(0 && "Unknown operation action!");
2718 case TargetLowering::Custom:
2721 case TargetLowering::Legal:
2722 Tmp1 = LegalizeOp(Node->getOperand(0));
2723 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2725 Tmp1 = TLI.LowerOperation(Result, DAG);
2726 if (Tmp1.Val) Result = Tmp1;
2729 case TargetLowering::Expand:
2730 Result = ExpandLegalINT_TO_FP(isSigned,
2731 LegalizeOp(Node->getOperand(0)),
2732 Node->getValueType(0));
2734 case TargetLowering::Promote:
2735 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2736 Node->getValueType(0),
2742 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2743 Node->getValueType(0), Node->getOperand(0));
2746 Tmp1 = PromoteOp(Node->getOperand(0));
2748 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2749 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2751 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2752 Node->getOperand(0).getValueType());
2754 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2755 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2761 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2763 Tmp1 = LegalizeOp(Node->getOperand(0));
2764 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2767 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2769 // Since the result is legal, we should just be able to truncate the low
2770 // part of the source.
2771 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2774 Result = PromoteOp(Node->getOperand(0));
2775 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2780 case ISD::FP_TO_SINT:
2781 case ISD::FP_TO_UINT:
2782 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2784 Tmp1 = LegalizeOp(Node->getOperand(0));
2786 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2787 default: assert(0 && "Unknown operation action!");
2788 case TargetLowering::Custom:
2791 case TargetLowering::Legal:
2792 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2794 Tmp1 = TLI.LowerOperation(Result, DAG);
2795 if (Tmp1.Val) Result = Tmp1;
2798 case TargetLowering::Promote:
2799 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2800 Node->getOpcode() == ISD::FP_TO_SINT);
2802 case TargetLowering::Expand:
2803 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2804 SDOperand True, False;
2805 MVT::ValueType VT = Node->getOperand(0).getValueType();
2806 MVT::ValueType NVT = Node->getValueType(0);
2807 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2808 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2809 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2810 Node->getOperand(0), Tmp2, ISD::SETLT);
2811 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2812 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2813 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2815 False = DAG.getNode(ISD::XOR, NVT, False,
2816 DAG.getConstant(1ULL << ShiftAmt, NVT));
2817 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2820 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2826 assert(0 && "Shouldn't need to expand other operators here!");
2828 Tmp1 = PromoteOp(Node->getOperand(0));
2829 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
2830 Result = LegalizeOp(Result);
2835 case ISD::ANY_EXTEND:
2836 case ISD::ZERO_EXTEND:
2837 case ISD::SIGN_EXTEND:
2838 case ISD::FP_EXTEND:
2840 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2841 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
2843 Tmp1 = LegalizeOp(Node->getOperand(0));
2844 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2847 switch (Node->getOpcode()) {
2848 case ISD::ANY_EXTEND:
2849 Tmp1 = PromoteOp(Node->getOperand(0));
2850 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
2852 case ISD::ZERO_EXTEND:
2853 Result = PromoteOp(Node->getOperand(0));
2854 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2855 Result = DAG.getZeroExtendInReg(Result,
2856 Node->getOperand(0).getValueType());
2858 case ISD::SIGN_EXTEND:
2859 Result = PromoteOp(Node->getOperand(0));
2860 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2861 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2863 DAG.getValueType(Node->getOperand(0).getValueType()));
2865 case ISD::FP_EXTEND:
2866 Result = PromoteOp(Node->getOperand(0));
2867 if (Result.getValueType() != Op.getValueType())
2868 // Dynamically dead while we have only 2 FP types.
2869 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2872 Result = PromoteOp(Node->getOperand(0));
2873 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2878 case ISD::FP_ROUND_INREG:
2879 case ISD::SIGN_EXTEND_INREG: {
2880 Tmp1 = LegalizeOp(Node->getOperand(0));
2881 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2883 // If this operation is not supported, convert it to a shl/shr or load/store
2885 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2886 default: assert(0 && "This action not supported for this op yet!");
2887 case TargetLowering::Legal:
2888 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2890 case TargetLowering::Expand:
2891 // If this is an integer extend and shifts are supported, do that.
2892 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2893 // NOTE: we could fall back on load/store here too for targets without
2894 // SAR. However, it is doubtful that any exist.
2895 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2896 MVT::getSizeInBits(ExtraVT);
2897 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2898 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2899 Node->getOperand(0), ShiftCst);
2900 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2902 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2903 // The only way we can lower this is to turn it into a TRUNCSTORE,
2904 // EXTLOAD pair, targetting a temporary location (a stack slot).
2906 // NOTE: there is a choice here between constantly creating new stack
2907 // slots and always reusing the same one. We currently always create
2908 // new ones, as reuse may inhibit scheduling.
2909 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2910 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty);
2911 unsigned Align = TLI.getTargetData()->getTypeAlignment(Ty);
2912 MachineFunction &MF = DAG.getMachineFunction();
2914 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2915 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2916 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
2917 StackSlot, NULL, 0, ExtraVT);
2918 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2919 Result, StackSlot, NULL, 0, ExtraVT);
2921 assert(0 && "Unknown op");
2929 assert(Result.getValueType() == Op.getValueType() &&
2930 "Bad legalization!");
2932 // Make sure that the generated code is itself legal.
2934 Result = LegalizeOp(Result);
2936 // Note that LegalizeOp may be reentered even from single-use nodes, which
2937 // means that we always must cache transformed nodes.
2938 AddLegalizedOperand(Op, Result);
2942 /// PromoteOp - Given an operation that produces a value in an invalid type,
2943 /// promote it to compute the value into a larger type. The produced value will
2944 /// have the correct bits for the low portion of the register, but no guarantee
2945 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2946 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2947 MVT::ValueType VT = Op.getValueType();
2948 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2949 assert(getTypeAction(VT) == Promote &&
2950 "Caller should expand or legalize operands that are not promotable!");
2951 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2952 "Cannot promote to smaller type!");
2954 SDOperand Tmp1, Tmp2, Tmp3;
2956 SDNode *Node = Op.Val;
2958 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2959 if (I != PromotedNodes.end()) return I->second;
2961 switch (Node->getOpcode()) {
2962 case ISD::CopyFromReg:
2963 assert(0 && "CopyFromReg must be legal!");
2966 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2968 assert(0 && "Do not know how to promote this operator!");
2971 Result = DAG.getNode(ISD::UNDEF, NVT);
2975 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2977 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2978 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2980 case ISD::ConstantFP:
2981 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2982 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2986 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2987 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2988 Node->getOperand(1), Node->getOperand(2));
2992 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2994 Result = LegalizeOp(Node->getOperand(0));
2995 assert(Result.getValueType() >= NVT &&
2996 "This truncation doesn't make sense!");
2997 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2998 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3001 // The truncation is not required, because we don't guarantee anything
3002 // about high bits anyway.
3003 Result = PromoteOp(Node->getOperand(0));
3006 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3007 // Truncate the low part of the expanded value to the result type
3008 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3011 case ISD::SIGN_EXTEND:
3012 case ISD::ZERO_EXTEND:
3013 case ISD::ANY_EXTEND:
3014 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3015 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3017 // Input is legal? Just do extend all the way to the larger type.
3018 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3021 // Promote the reg if it's smaller.
3022 Result = PromoteOp(Node->getOperand(0));
3023 // The high bits are not guaranteed to be anything. Insert an extend.
3024 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3025 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3026 DAG.getValueType(Node->getOperand(0).getValueType()));
3027 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3028 Result = DAG.getZeroExtendInReg(Result,
3029 Node->getOperand(0).getValueType());
3033 case ISD::BIT_CONVERT:
3034 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3035 Result = PromoteOp(Result);
3038 case ISD::FP_EXTEND:
3039 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3041 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3042 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3043 case Promote: assert(0 && "Unreachable with 2 FP types!");
3045 // Input is legal? Do an FP_ROUND_INREG.
3046 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3047 DAG.getValueType(VT));
3052 case ISD::SINT_TO_FP:
3053 case ISD::UINT_TO_FP:
3054 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3056 // No extra round required here.
3057 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3061 Result = PromoteOp(Node->getOperand(0));
3062 if (Node->getOpcode() == ISD::SINT_TO_FP)
3063 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3065 DAG.getValueType(Node->getOperand(0).getValueType()));
3067 Result = DAG.getZeroExtendInReg(Result,
3068 Node->getOperand(0).getValueType());
3069 // No extra round required here.
3070 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3073 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3074 Node->getOperand(0));
3075 // Round if we cannot tolerate excess precision.
3076 if (NoExcessFPPrecision)
3077 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3078 DAG.getValueType(VT));
3083 case ISD::SIGN_EXTEND_INREG:
3084 Result = PromoteOp(Node->getOperand(0));
3085 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3086 Node->getOperand(1));
3088 case ISD::FP_TO_SINT:
3089 case ISD::FP_TO_UINT:
3090 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3092 Tmp1 = Node->getOperand(0);
3095 // The input result is prerounded, so we don't have to do anything
3097 Tmp1 = PromoteOp(Node->getOperand(0));
3100 assert(0 && "not implemented");
3102 // If we're promoting a UINT to a larger size, check to see if the new node
3103 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3104 // we can use that instead. This allows us to generate better code for
3105 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3106 // legal, such as PowerPC.
3107 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3108 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3109 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3110 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3111 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3113 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3119 Tmp1 = PromoteOp(Node->getOperand(0));
3120 assert(Tmp1.getValueType() == NVT);
3121 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3122 // NOTE: we do not have to do any extra rounding here for
3123 // NoExcessFPPrecision, because we know the input will have the appropriate
3124 // precision, and these operations don't modify precision at all.
3130 Tmp1 = PromoteOp(Node->getOperand(0));
3131 assert(Tmp1.getValueType() == NVT);
3132 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3133 if (NoExcessFPPrecision)
3134 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3135 DAG.getValueType(VT));
3144 // The input may have strange things in the top bits of the registers, but
3145 // these operations don't care. They may have weird bits going out, but
3146 // that too is okay if they are integer operations.
3147 Tmp1 = PromoteOp(Node->getOperand(0));
3148 Tmp2 = PromoteOp(Node->getOperand(1));
3149 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3150 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3155 Tmp1 = PromoteOp(Node->getOperand(0));
3156 Tmp2 = PromoteOp(Node->getOperand(1));
3157 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3158 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3160 // Floating point operations will give excess precision that we may not be
3161 // able to tolerate. If we DO allow excess precision, just leave it,
3162 // otherwise excise it.
3163 // FIXME: Why would we need to round FP ops more than integer ones?
3164 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3165 if (NoExcessFPPrecision)
3166 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3167 DAG.getValueType(VT));
3172 // These operators require that their input be sign extended.
3173 Tmp1 = PromoteOp(Node->getOperand(0));
3174 Tmp2 = PromoteOp(Node->getOperand(1));
3175 if (MVT::isInteger(NVT)) {
3176 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3177 DAG.getValueType(VT));
3178 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3179 DAG.getValueType(VT));
3181 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3183 // Perform FP_ROUND: this is probably overly pessimistic.
3184 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3185 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3186 DAG.getValueType(VT));
3190 case ISD::FCOPYSIGN:
3191 // These operators require that their input be fp extended.
3192 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3194 Tmp1 = LegalizeOp(Node->getOperand(0));
3197 Tmp1 = PromoteOp(Node->getOperand(0));
3200 assert(0 && "not implemented");
3202 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3204 Tmp2 = LegalizeOp(Node->getOperand(1));
3207 Tmp2 = PromoteOp(Node->getOperand(1));
3210 assert(0 && "not implemented");
3212 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3214 // Perform FP_ROUND: this is probably overly pessimistic.
3215 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3216 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3217 DAG.getValueType(VT));
3222 // These operators require that their input be zero extended.
3223 Tmp1 = PromoteOp(Node->getOperand(0));
3224 Tmp2 = PromoteOp(Node->getOperand(1));
3225 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3226 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3227 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3228 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3232 Tmp1 = PromoteOp(Node->getOperand(0));
3233 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3236 // The input value must be properly sign extended.
3237 Tmp1 = PromoteOp(Node->getOperand(0));
3238 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3239 DAG.getValueType(VT));
3240 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3243 // The input value must be properly zero extended.
3244 Tmp1 = PromoteOp(Node->getOperand(0));
3245 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3246 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3250 Tmp1 = Node->getOperand(0); // Get the chain.
3251 Tmp2 = Node->getOperand(1); // Get the pointer.
3252 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3253 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3254 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3256 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3257 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3258 SV->getValue(), SV->getOffset());
3259 // Increment the pointer, VAList, to the next vaarg
3260 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3261 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3262 TLI.getPointerTy()));
3263 // Store the incremented VAList to the legalized pointer
3264 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3266 // Load the actual argument out of the pointer VAList
3267 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
3269 // Remember that we legalized the chain.
3270 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3274 LoadSDNode *LD = cast<LoadSDNode>(Node);
3275 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
3276 ? ISD::EXTLOAD : LD->getExtensionType();
3277 Result = DAG.getExtLoad(ExtType, NVT,
3278 LD->getChain(), LD->getBasePtr(),
3279 LD->getSrcValue(), LD->getSrcValueOffset(),
3281 // Remember that we legalized the chain.
3282 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3286 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3287 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3288 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3290 case ISD::SELECT_CC:
3291 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3292 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3293 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3294 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3297 Tmp1 = Node->getOperand(0);
3298 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3299 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3300 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3301 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
3302 TLI.getShiftAmountTy()));
3307 // Zero extend the argument
3308 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3309 // Perform the larger operation, then subtract if needed.
3310 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3311 switch(Node->getOpcode()) {
3316 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3317 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3318 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
3319 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3320 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
3323 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3324 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3325 DAG.getConstant(getSizeInBits(NVT) -
3326 getSizeInBits(VT), NVT));
3330 case ISD::VEXTRACT_VECTOR_ELT:
3331 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
3333 case ISD::EXTRACT_VECTOR_ELT:
3334 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3338 assert(Result.Val && "Didn't set a result!");
3340 // Make sure the result is itself legal.
3341 Result = LegalizeOp(Result);
3343 // Remember that we promoted this!
3344 AddPromotedOperand(Op, Result);
3348 /// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
3349 /// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
3350 /// on the vector type. The return type of this matches the element type of the
3351 /// vector, which may not be legal for the target.
3352 SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
3353 // We know that operand #0 is the Vec vector. If the index is a constant
3354 // or if the invec is a supported hardware type, we can use it. Otherwise,
3355 // lower to a store then an indexed load.
3356 SDOperand Vec = Op.getOperand(0);
3357 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3359 SDNode *InVal = Vec.Val;
3360 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
3361 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
3363 // Figure out if there is a Packed type corresponding to this Vector
3364 // type. If so, convert to the packed type.
3365 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3366 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
3367 // Turn this into a packed extract_vector_elt operation.
3368 Vec = PackVectorOp(Vec, TVT);
3369 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
3370 } else if (NumElems == 1) {
3371 // This must be an access of the only element. Return it.
3372 return PackVectorOp(Vec, EVT);
3373 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
3375 SplitVectorOp(Vec, Lo, Hi);
3376 if (CIdx->getValue() < NumElems/2) {
3380 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3383 // It's now an extract from the appropriate high or low part. Recurse.
3384 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3385 return LowerVEXTRACT_VECTOR_ELT(Op);
3387 // Variable index case for extract element.
3388 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
3389 assert(0 && "unimp!");
3394 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3396 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3397 SDOperand Vector = Op.getOperand(0);
3398 SDOperand Idx = Op.getOperand(1);
3400 // If the target doesn't support this, store the value to a temporary
3401 // stack slot, then LOAD the scalar element back out.
3402 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
3403 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vector, StackPtr, NULL, 0);
3405 // Add the offset to the index.
3406 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3407 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3408 DAG.getConstant(EltSize, Idx.getValueType()));
3409 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3411 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
3415 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3416 /// with condition CC on the current target. This usually involves legalizing
3417 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3418 /// there may be no choice but to create a new SetCC node to represent the
3419 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3420 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3421 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3424 SDOperand Tmp1, Tmp2, Result;
3426 switch (getTypeAction(LHS.getValueType())) {
3428 Tmp1 = LegalizeOp(LHS); // LHS
3429 Tmp2 = LegalizeOp(RHS); // RHS
3432 Tmp1 = PromoteOp(LHS); // LHS
3433 Tmp2 = PromoteOp(RHS); // RHS
3435 // If this is an FP compare, the operands have already been extended.
3436 if (MVT::isInteger(LHS.getValueType())) {
3437 MVT::ValueType VT = LHS.getValueType();
3438 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3440 // Otherwise, we have to insert explicit sign or zero extends. Note
3441 // that we could insert sign extends for ALL conditions, but zero extend
3442 // is cheaper on many machines (an AND instead of two shifts), so prefer
3444 switch (cast<CondCodeSDNode>(CC)->get()) {
3445 default: assert(0 && "Unknown integer comparison!");
3452 // ALL of these operations will work if we either sign or zero extend
3453 // the operands (including the unsigned comparisons!). Zero extend is
3454 // usually a simpler/cheaper operation, so prefer it.
3455 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3456 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3462 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3463 DAG.getValueType(VT));
3464 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3465 DAG.getValueType(VT));
3471 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3472 ExpandOp(LHS, LHSLo, LHSHi);
3473 ExpandOp(RHS, RHSLo, RHSHi);
3474 switch (cast<CondCodeSDNode>(CC)->get()) {
3478 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3479 if (RHSCST->isAllOnesValue()) {
3480 // Comparison to -1.
3481 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3486 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3487 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3488 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3489 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3492 // If this is a comparison of the sign bit, just look at the top part.
3494 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3495 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3496 CST->getValue() == 0) || // X < 0
3497 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3498 CST->isAllOnesValue())) { // X > -1
3504 // FIXME: This generated code sucks.
3505 ISD::CondCode LowCC;
3506 switch (cast<CondCodeSDNode>(CC)->get()) {
3507 default: assert(0 && "Unknown integer setcc!");
3509 case ISD::SETULT: LowCC = ISD::SETULT; break;
3511 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3513 case ISD::SETULE: LowCC = ISD::SETULE; break;
3515 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3518 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3519 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3520 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3522 // NOTE: on targets without efficient SELECT of bools, we can always use
3523 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3524 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3525 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3526 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3527 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3528 Result, Tmp1, Tmp2));
3537 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3538 /// The resultant code need not be legal. Note that SrcOp is the input operand
3539 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3540 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3542 // Create the stack frame object.
3543 SDOperand FIPtr = CreateStackTemporary(DestVT);
3545 // Emit a store to the stack slot.
3546 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
3547 // Result is a load from the stack slot.
3548 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
3551 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3552 // Create a vector sized/aligned stack slot, store the value to element #0,
3553 // then load the whole vector back out.
3554 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3555 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
3557 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
3561 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3562 /// support the operation, but do support the resultant packed vector type.
3563 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3565 // If the only non-undef value is the low element, turn this into a
3566 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3567 unsigned NumElems = Node->getNumOperands();
3568 bool isOnlyLowElement = true;
3569 SDOperand SplatValue = Node->getOperand(0);
3570 std::map<SDOperand, std::vector<unsigned> > Values;
3571 Values[SplatValue].push_back(0);
3572 bool isConstant = true;
3573 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3574 SplatValue.getOpcode() != ISD::UNDEF)
3577 for (unsigned i = 1; i < NumElems; ++i) {
3578 SDOperand V = Node->getOperand(i);
3579 Values[V].push_back(i);
3580 if (V.getOpcode() != ISD::UNDEF)
3581 isOnlyLowElement = false;
3582 if (SplatValue != V)
3583 SplatValue = SDOperand(0,0);
3585 // If this isn't a constant element or an undef, we can't use a constant
3587 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3588 V.getOpcode() != ISD::UNDEF)
3592 if (isOnlyLowElement) {
3593 // If the low element is an undef too, then this whole things is an undef.
3594 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3595 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3596 // Otherwise, turn this into a scalar_to_vector node.
3597 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3598 Node->getOperand(0));
3601 // If all elements are constants, create a load from the constant pool.
3603 MVT::ValueType VT = Node->getValueType(0);
3605 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3606 std::vector<Constant*> CV;
3607 for (unsigned i = 0, e = NumElems; i != e; ++i) {
3608 if (ConstantFPSDNode *V =
3609 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3610 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3611 } else if (ConstantSDNode *V =
3612 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3613 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
3615 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3616 CV.push_back(UndefValue::get(OpNTy));
3619 Constant *CP = ConstantPacked::get(CV);
3620 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3621 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
3624 if (SplatValue.Val) { // Splat of one value?
3625 // Build the shuffle constant vector: <0, 0, 0, 0>
3626 MVT::ValueType MaskVT =
3627 MVT::getIntVectorWithNumElements(NumElems);
3628 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
3629 std::vector<SDOperand> ZeroVec(NumElems, Zero);
3630 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3631 &ZeroVec[0], ZeroVec.size());
3633 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3634 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
3635 // Get the splatted value into the low element of a vector register.
3636 SDOperand LowValVec =
3637 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3639 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3640 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3641 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3646 // If there are only two unique elements, we may be able to turn this into a
3648 if (Values.size() == 2) {
3649 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
3650 MVT::ValueType MaskVT =
3651 MVT::getIntVectorWithNumElements(NumElems);
3652 std::vector<SDOperand> MaskVec(NumElems);
3654 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3655 E = Values.end(); I != E; ++I) {
3656 for (std::vector<unsigned>::iterator II = I->second.begin(),
3657 EE = I->second.end(); II != EE; ++II)
3658 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
3661 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3662 &MaskVec[0], MaskVec.size());
3664 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3665 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
3666 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
3667 SmallVector<SDOperand, 8> Ops;
3668 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3669 E = Values.end(); I != E; ++I) {
3670 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3674 Ops.push_back(ShuffleMask);
3676 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
3677 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
3678 &Ops[0], Ops.size());
3682 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
3683 // aligned object on the stack, store each element into it, then load
3684 // the result as a vector.
3685 MVT::ValueType VT = Node->getValueType(0);
3686 // Create the stack frame object.
3687 SDOperand FIPtr = CreateStackTemporary(VT);
3689 // Emit a store of each element to the stack slot.
3690 SmallVector<SDOperand, 8> Stores;
3691 unsigned TypeByteSize =
3692 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
3693 // Store (in the right endianness) the elements to memory.
3694 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3695 // Ignore undef elements.
3696 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3698 unsigned Offset = TypeByteSize*i;
3700 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
3701 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
3703 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
3707 SDOperand StoreChain;
3708 if (!Stores.empty()) // Not all undef elements?
3709 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3710 &Stores[0], Stores.size());
3712 StoreChain = DAG.getEntryNode();
3714 // Result is a load from the stack slot.
3715 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
3718 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
3719 /// specified value type.
3720 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
3721 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3722 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
3723 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
3724 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
3727 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
3728 SDOperand Op, SDOperand Amt,
3729 SDOperand &Lo, SDOperand &Hi) {
3730 // Expand the subcomponents.
3731 SDOperand LHSL, LHSH;
3732 ExpandOp(Op, LHSL, LHSH);
3734 SDOperand Ops[] = { LHSL, LHSH, Amt };
3735 MVT::ValueType VT = LHSL.getValueType();
3736 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
3737 Hi = Lo.getValue(1);
3741 /// ExpandShift - Try to find a clever way to expand this shift operation out to
3742 /// smaller elements. If we can't find a way that is more efficient than a
3743 /// libcall on this target, return false. Otherwise, return true with the
3744 /// low-parts expanded into Lo and Hi.
3745 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3746 SDOperand &Lo, SDOperand &Hi) {
3747 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3748 "This is not a shift!");
3750 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3751 SDOperand ShAmt = LegalizeOp(Amt);
3752 MVT::ValueType ShTy = ShAmt.getValueType();
3753 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3754 unsigned NVTBits = MVT::getSizeInBits(NVT);
3756 // Handle the case when Amt is an immediate. Other cases are currently broken
3757 // and are disabled.
3758 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3759 unsigned Cst = CN->getValue();
3760 // Expand the incoming operand to be shifted, so that we have its parts
3762 ExpandOp(Op, InL, InH);
3766 Lo = DAG.getConstant(0, NVT);
3767 Hi = DAG.getConstant(0, NVT);
3768 } else if (Cst > NVTBits) {
3769 Lo = DAG.getConstant(0, NVT);
3770 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
3771 } else if (Cst == NVTBits) {
3772 Lo = DAG.getConstant(0, NVT);
3775 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
3776 Hi = DAG.getNode(ISD::OR, NVT,
3777 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
3778 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
3783 Lo = DAG.getConstant(0, NVT);
3784 Hi = DAG.getConstant(0, NVT);
3785 } else if (Cst > NVTBits) {
3786 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
3787 Hi = DAG.getConstant(0, NVT);
3788 } else if (Cst == NVTBits) {
3790 Hi = DAG.getConstant(0, NVT);
3792 Lo = DAG.getNode(ISD::OR, NVT,
3793 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3794 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3795 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
3800 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
3801 DAG.getConstant(NVTBits-1, ShTy));
3802 } else if (Cst > NVTBits) {
3803 Lo = DAG.getNode(ISD::SRA, NVT, InH,
3804 DAG.getConstant(Cst-NVTBits, ShTy));
3805 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3806 DAG.getConstant(NVTBits-1, ShTy));
3807 } else if (Cst == NVTBits) {
3809 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3810 DAG.getConstant(NVTBits-1, ShTy));
3812 Lo = DAG.getNode(ISD::OR, NVT,
3813 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3814 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3815 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
3821 // Okay, the shift amount isn't constant. However, if we can tell that it is
3822 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
3823 uint64_t Mask = NVTBits, KnownZero, KnownOne;
3824 TLI.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
3826 // If we know that the high bit of the shift amount is one, then we can do
3827 // this as a couple of simple shifts.
3828 if (KnownOne & Mask) {
3829 // Mask out the high bit, which we know is set.
3830 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
3831 DAG.getConstant(NVTBits-1, Amt.getValueType()));
3833 // Expand the incoming operand to be shifted, so that we have its parts
3835 ExpandOp(Op, InL, InH);
3838 Lo = DAG.getConstant(0, NVT); // Low part is zero.
3839 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
3842 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
3843 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
3846 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
3847 DAG.getConstant(NVTBits-1, Amt.getValueType()));
3848 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
3853 // If we know that the high bit of the shift amount is zero, then we can do
3854 // this as a couple of simple shifts.
3855 if (KnownZero & Mask) {
3857 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
3858 DAG.getConstant(NVTBits, Amt.getValueType()),
3861 // Expand the incoming operand to be shifted, so that we have its parts
3863 ExpandOp(Op, InL, InH);
3866 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
3867 Hi = DAG.getNode(ISD::OR, NVT,
3868 DAG.getNode(ISD::SHL, NVT, InH, Amt),
3869 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
3872 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
3873 Lo = DAG.getNode(ISD::OR, NVT,
3874 DAG.getNode(ISD::SRL, NVT, InL, Amt),
3875 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
3878 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
3879 Lo = DAG.getNode(ISD::OR, NVT,
3880 DAG.getNode(ISD::SRL, NVT, InL, Amt),
3881 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
3890 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
3891 // does not fit into a register, return the lo part and set the hi part to the
3892 // by-reg argument. If it does fit into a single register, return the result
3893 // and leave the Hi part unset.
3894 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3896 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
3897 // The input chain to this libcall is the entry node of the function.
3898 // Legalizing the call will automatically add the previous call to the
3900 SDOperand InChain = DAG.getEntryNode();
3902 TargetLowering::ArgListTy Args;
3903 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3904 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3905 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3906 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3908 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3910 // Splice the libcall in wherever FindInputOutputChains tells us to.
3911 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3912 std::pair<SDOperand,SDOperand> CallInfo =
3913 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3916 // Legalize the call sequence, starting with the chain. This will advance
3917 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
3918 // was added by LowerCallTo (guaranteeing proper serialization of calls).
3919 LegalizeOp(CallInfo.second);
3921 switch (getTypeAction(CallInfo.first.getValueType())) {
3922 default: assert(0 && "Unknown thing");
3924 Result = CallInfo.first;
3927 ExpandOp(CallInfo.first, Result, Hi);
3934 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3935 /// destination type is legal.
3936 SDOperand SelectionDAGLegalize::
3937 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3938 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3939 assert(getTypeAction(Source.getValueType()) == Expand &&
3940 "This is not an expansion!");
3941 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3944 assert(Source.getValueType() == MVT::i64 &&
3945 "This only works for 64-bit -> FP");
3946 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3947 // incoming integer is set. To handle this, we dynamically test to see if
3948 // it is set, and, if so, add a fudge factor.
3950 ExpandOp(Source, Lo, Hi);
3952 // If this is unsigned, and not supported, first perform the conversion to
3953 // signed, then adjust the result if the sign bit is set.
3954 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3955 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3957 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3958 DAG.getConstant(0, Hi.getValueType()),
3960 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3961 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3962 SignSet, Four, Zero);
3963 uint64_t FF = 0x5f800000ULL;
3964 if (TLI.isLittleEndian()) FF <<= 32;
3965 static Constant *FudgeFactor = ConstantInt::get(Type::ULongTy, FF);
3967 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3968 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3969 SDOperand FudgeInReg;
3970 if (DestTy == MVT::f32)
3971 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
3973 assert(DestTy == MVT::f64 && "Unexpected conversion");
3974 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3975 CPIdx, NULL, 0, MVT::f32);
3977 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3980 // Check to see if the target has a custom way to lower this. If so, use it.
3981 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3982 default: assert(0 && "This action not implemented for this operation!");
3983 case TargetLowering::Legal:
3984 case TargetLowering::Expand:
3985 break; // This case is handled below.
3986 case TargetLowering::Custom: {
3987 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3990 return LegalizeOp(NV);
3991 break; // The target decided this was legal after all
3995 // Expand the source, then glue it back together for the call. We must expand
3996 // the source in case it is shared (this pass of legalize must traverse it).
3997 SDOperand SrcLo, SrcHi;
3998 ExpandOp(Source, SrcLo, SrcHi);
3999 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
4001 const char *FnName = 0;
4002 if (DestTy == MVT::f32)
4003 FnName = "__floatdisf";
4005 assert(DestTy == MVT::f64 && "Unknown fp value type!");
4006 FnName = "__floatdidf";
4009 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
4010 SDOperand UnusedHiPart;
4011 return ExpandLibCall(FnName, Source.Val, UnusedHiPart);
4014 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
4015 /// INT_TO_FP operation of the specified operand when the target requests that
4016 /// we expand it. At this point, we know that the result and operand types are
4017 /// legal for the target.
4018 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
4020 MVT::ValueType DestVT) {
4021 if (Op0.getValueType() == MVT::i32) {
4022 // simple 32-bit [signed|unsigned] integer to float/double expansion
4024 // get the stack frame index of a 8 byte buffer
4025 MachineFunction &MF = DAG.getMachineFunction();
4026 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4027 // get address of 8 byte buffer
4028 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4029 // word offset constant for Hi/Lo address computation
4030 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
4031 // set up Hi and Lo (into buffer) address based on endian
4032 SDOperand Hi = StackSlot;
4033 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4034 if (TLI.isLittleEndian())
4037 // if signed map to unsigned space
4038 SDOperand Op0Mapped;
4040 // constant used to invert sign bit (signed to unsigned mapping)
4041 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4042 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4046 // store the lo of the constructed double - based on integer input
4047 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4048 Op0Mapped, Lo, NULL, 0);
4049 // initial hi portion of constructed double
4050 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4051 // store the hi of the constructed double - biased exponent
4052 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
4053 // load the constructed double
4054 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4055 // FP constant to bias correct the final result
4056 SDOperand Bias = DAG.getConstantFP(isSigned ?
4057 BitsToDouble(0x4330000080000000ULL)
4058 : BitsToDouble(0x4330000000000000ULL),
4060 // subtract the bias
4061 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4064 // handle final rounding
4065 if (DestVT == MVT::f64) {
4069 // if f32 then cast to f32
4070 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
4074 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4075 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4077 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4078 DAG.getConstant(0, Op0.getValueType()),
4080 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4081 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4082 SignSet, Four, Zero);
4084 // If the sign bit of the integer is set, the large number will be treated
4085 // as a negative number. To counteract this, the dynamic code adds an
4086 // offset depending on the data type.
4088 switch (Op0.getValueType()) {
4089 default: assert(0 && "Unsupported integer type!");
4090 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4091 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4092 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4093 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4095 if (TLI.isLittleEndian()) FF <<= 32;
4096 static Constant *FudgeFactor = ConstantInt::get(Type::ULongTy, FF);
4098 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4099 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4100 SDOperand FudgeInReg;
4101 if (DestVT == MVT::f32)
4102 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4104 assert(DestVT == MVT::f64 && "Unexpected conversion");
4105 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
4106 DAG.getEntryNode(), CPIdx,
4107 NULL, 0, MVT::f32));
4110 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4113 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4114 /// *INT_TO_FP operation of the specified operand when the target requests that
4115 /// we promote it. At this point, we know that the result and operand types are
4116 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4117 /// operation that takes a larger input.
4118 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4119 MVT::ValueType DestVT,
4121 // First step, figure out the appropriate *INT_TO_FP operation to use.
4122 MVT::ValueType NewInTy = LegalOp.getValueType();
4124 unsigned OpToUse = 0;
4126 // Scan for the appropriate larger type to use.
4128 NewInTy = (MVT::ValueType)(NewInTy+1);
4129 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4131 // If the target supports SINT_TO_FP of this type, use it.
4132 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4134 case TargetLowering::Legal:
4135 if (!TLI.isTypeLegal(NewInTy))
4136 break; // Can't use this datatype.
4138 case TargetLowering::Custom:
4139 OpToUse = ISD::SINT_TO_FP;
4143 if (isSigned) continue;
4145 // If the target supports UINT_TO_FP of this type, use it.
4146 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4148 case TargetLowering::Legal:
4149 if (!TLI.isTypeLegal(NewInTy))
4150 break; // Can't use this datatype.
4152 case TargetLowering::Custom:
4153 OpToUse = ISD::UINT_TO_FP;
4158 // Otherwise, try a larger type.
4161 // Okay, we found the operation and type to use. Zero extend our input to the
4162 // desired type then run the operation on it.
4163 return DAG.getNode(OpToUse, DestVT,
4164 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4168 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4169 /// FP_TO_*INT operation of the specified operand when the target requests that
4170 /// we promote it. At this point, we know that the result and operand types are
4171 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4172 /// operation that returns a larger result.
4173 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4174 MVT::ValueType DestVT,
4176 // First step, figure out the appropriate FP_TO*INT operation to use.
4177 MVT::ValueType NewOutTy = DestVT;
4179 unsigned OpToUse = 0;
4181 // Scan for the appropriate larger type to use.
4183 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4184 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4186 // If the target supports FP_TO_SINT returning this type, use it.
4187 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4189 case TargetLowering::Legal:
4190 if (!TLI.isTypeLegal(NewOutTy))
4191 break; // Can't use this datatype.
4193 case TargetLowering::Custom:
4194 OpToUse = ISD::FP_TO_SINT;
4199 // If the target supports FP_TO_UINT of this type, use it.
4200 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4202 case TargetLowering::Legal:
4203 if (!TLI.isTypeLegal(NewOutTy))
4204 break; // Can't use this datatype.
4206 case TargetLowering::Custom:
4207 OpToUse = ISD::FP_TO_UINT;
4212 // Otherwise, try a larger type.
4215 // Okay, we found the operation and type to use. Truncate the result of the
4216 // extended FP_TO_*INT operation to the desired size.
4217 return DAG.getNode(ISD::TRUNCATE, DestVT,
4218 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4221 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4223 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4224 MVT::ValueType VT = Op.getValueType();
4225 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4226 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4228 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4230 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4231 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4232 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4234 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4235 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4236 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4237 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4238 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4239 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4240 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4241 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4242 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4244 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4245 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4246 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4247 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4248 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4249 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4250 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4251 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4252 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4253 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4254 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4255 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4256 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4257 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4258 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4259 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4260 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4261 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4262 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4263 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4264 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4268 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4270 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4272 default: assert(0 && "Cannot expand this yet!");
4274 static const uint64_t mask[6] = {
4275 0x5555555555555555ULL, 0x3333333333333333ULL,
4276 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4277 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4279 MVT::ValueType VT = Op.getValueType();
4280 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4281 unsigned len = getSizeInBits(VT);
4282 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4283 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4284 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4285 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4286 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4287 DAG.getNode(ISD::AND, VT,
4288 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4293 // for now, we do this:
4294 // x = x | (x >> 1);
4295 // x = x | (x >> 2);
4297 // x = x | (x >>16);
4298 // x = x | (x >>32); // for 64-bit input
4299 // return popcount(~x);
4301 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4302 MVT::ValueType VT = Op.getValueType();
4303 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4304 unsigned len = getSizeInBits(VT);
4305 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4306 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4307 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4309 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4310 return DAG.getNode(ISD::CTPOP, VT, Op);
4313 // for now, we use: { return popcount(~x & (x - 1)); }
4314 // unless the target has ctlz but not ctpop, in which case we use:
4315 // { return 32 - nlz(~x & (x-1)); }
4316 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4317 MVT::ValueType VT = Op.getValueType();
4318 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4319 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4320 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4321 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4322 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4323 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4324 TLI.isOperationLegal(ISD::CTLZ, VT))
4325 return DAG.getNode(ISD::SUB, VT,
4326 DAG.getConstant(getSizeInBits(VT), VT),
4327 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4328 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4333 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4334 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4335 /// LegalizeNodes map is filled in for any results that are not expanded, the
4336 /// ExpandedNodes map is filled in for any results that are expanded, and the
4337 /// Lo/Hi values are returned.
4338 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4339 MVT::ValueType VT = Op.getValueType();
4340 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4341 SDNode *Node = Op.Val;
4342 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4343 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
4344 "Cannot expand FP values!");
4345 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
4346 "Cannot expand to FP value or to larger int value!");
4348 // See if we already expanded it.
4349 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4350 = ExpandedNodes.find(Op);
4351 if (I != ExpandedNodes.end()) {
4352 Lo = I->second.first;
4353 Hi = I->second.second;
4357 switch (Node->getOpcode()) {
4358 case ISD::CopyFromReg:
4359 assert(0 && "CopyFromReg must be legal!");
4362 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
4364 assert(0 && "Do not know how to expand this operator!");
4367 Lo = DAG.getNode(ISD::UNDEF, NVT);
4368 Hi = DAG.getNode(ISD::UNDEF, NVT);
4370 case ISD::Constant: {
4371 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4372 Lo = DAG.getConstant(Cst, NVT);
4373 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4376 case ISD::BUILD_PAIR:
4377 // Return the operands.
4378 Lo = Node->getOperand(0);
4379 Hi = Node->getOperand(1);
4382 case ISD::SIGN_EXTEND_INREG:
4383 ExpandOp(Node->getOperand(0), Lo, Hi);
4384 // sext_inreg the low part if needed.
4385 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4387 // The high part gets the sign extension from the lo-part. This handles
4388 // things like sextinreg V:i64 from i8.
4389 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4390 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4391 TLI.getShiftAmountTy()));
4395 ExpandOp(Node->getOperand(0), Lo, Hi);
4396 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4397 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4403 ExpandOp(Node->getOperand(0), Lo, Hi);
4404 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4405 DAG.getNode(ISD::CTPOP, NVT, Lo),
4406 DAG.getNode(ISD::CTPOP, NVT, Hi));
4407 Hi = DAG.getConstant(0, NVT);
4411 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4412 ExpandOp(Node->getOperand(0), Lo, Hi);
4413 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4414 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4415 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4417 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4418 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4420 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4421 Hi = DAG.getConstant(0, NVT);
4426 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4427 ExpandOp(Node->getOperand(0), Lo, Hi);
4428 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4429 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4430 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4432 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4433 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4435 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4436 Hi = DAG.getConstant(0, NVT);
4441 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4442 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4443 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4444 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4446 // Remember that we legalized the chain.
4447 Hi = LegalizeOp(Hi);
4448 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4449 if (!TLI.isLittleEndian())
4455 LoadSDNode *LD = cast<LoadSDNode>(Node);
4456 SDOperand Ch = LD->getChain(); // Legalize the chain.
4457 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
4458 ISD::LoadExtType ExtType = LD->getExtensionType();
4460 if (ExtType == ISD::NON_EXTLOAD) {
4461 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset());
4463 // Increment the pointer to the other half.
4464 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4465 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4466 getIntPtrConstant(IncrementSize));
4467 // FIXME: This creates a bogus srcvalue!
4468 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset());
4470 // Build a factor node to remember that this load is independent of the
4472 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4475 // Remember that we legalized the chain.
4476 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4477 if (!TLI.isLittleEndian())
4480 MVT::ValueType EVT = LD->getLoadedVT();
4483 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
4484 LD->getSrcValueOffset());
4486 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
4487 LD->getSrcValueOffset(), EVT);
4489 // Remember that we legalized the chain.
4490 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4492 if (ExtType == ISD::SEXTLOAD) {
4493 // The high part is obtained by SRA'ing all but one of the bits of the
4495 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4496 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4497 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4498 } else if (ExtType == ISD::ZEXTLOAD) {
4499 // The high part is just a zero.
4500 Hi = DAG.getConstant(0, NVT);
4501 } else /* if (ExtType == ISD::EXTLOAD) */ {
4502 // The high part is undefined.
4503 Hi = DAG.getNode(ISD::UNDEF, NVT);
4510 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
4511 SDOperand LL, LH, RL, RH;
4512 ExpandOp(Node->getOperand(0), LL, LH);
4513 ExpandOp(Node->getOperand(1), RL, RH);
4514 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4515 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4519 SDOperand LL, LH, RL, RH;
4520 ExpandOp(Node->getOperand(1), LL, LH);
4521 ExpandOp(Node->getOperand(2), RL, RH);
4522 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4523 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4526 case ISD::SELECT_CC: {
4527 SDOperand TL, TH, FL, FH;
4528 ExpandOp(Node->getOperand(2), TL, TH);
4529 ExpandOp(Node->getOperand(3), FL, FH);
4530 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4531 Node->getOperand(1), TL, FL, Node->getOperand(4));
4532 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4533 Node->getOperand(1), TH, FH, Node->getOperand(4));
4536 case ISD::ANY_EXTEND:
4537 // The low part is any extension of the input (which degenerates to a copy).
4538 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4539 // The high part is undefined.
4540 Hi = DAG.getNode(ISD::UNDEF, NVT);
4542 case ISD::SIGN_EXTEND: {
4543 // The low part is just a sign extension of the input (which degenerates to
4545 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4547 // The high part is obtained by SRA'ing all but one of the bits of the lo
4549 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4550 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4551 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4554 case ISD::ZERO_EXTEND:
4555 // The low part is just a zero extension of the input (which degenerates to
4557 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4559 // The high part is just a zero.
4560 Hi = DAG.getConstant(0, NVT);
4563 case ISD::BIT_CONVERT: {
4565 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
4566 // If the target wants to, allow it to lower this itself.
4567 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4568 case Expand: assert(0 && "cannot expand FP!");
4569 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
4570 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
4572 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
4575 // Turn this into a load/store pair by default.
4577 Tmp = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
4579 ExpandOp(Tmp, Lo, Hi);
4583 case ISD::READCYCLECOUNTER:
4584 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
4585 TargetLowering::Custom &&
4586 "Must custom expand ReadCycleCounter");
4587 Lo = TLI.LowerOperation(Op, DAG);
4588 assert(Lo.Val && "Node must be custom expanded!");
4589 Hi = Lo.getValue(1);
4590 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
4591 LegalizeOp(Lo.getValue(2)));
4594 // These operators cannot be expanded directly, emit them as calls to
4595 // library functions.
4596 case ISD::FP_TO_SINT:
4597 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
4599 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4600 case Expand: assert(0 && "cannot expand FP!");
4601 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4602 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4605 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
4607 // Now that the custom expander is done, expand the result, which is still
4610 ExpandOp(Op, Lo, Hi);
4615 if (Node->getOperand(0).getValueType() == MVT::f32)
4616 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
4618 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
4621 case ISD::FP_TO_UINT:
4622 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
4624 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4625 case Expand: assert(0 && "cannot expand FP!");
4626 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4627 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4630 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
4632 // Now that the custom expander is done, expand the result.
4634 ExpandOp(Op, Lo, Hi);
4639 if (Node->getOperand(0).getValueType() == MVT::f32)
4640 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
4642 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
4646 // If the target wants custom lowering, do so.
4647 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4648 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
4649 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
4650 Op = TLI.LowerOperation(Op, DAG);
4652 // Now that the custom expander is done, expand the result, which is
4654 ExpandOp(Op, Lo, Hi);
4659 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
4660 // this X << 1 as X+X.
4661 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
4662 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
4663 TLI.isOperationLegal(ISD::ADDE, NVT)) {
4664 SDOperand LoOps[2], HiOps[3];
4665 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
4666 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
4667 LoOps[1] = LoOps[0];
4668 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
4670 HiOps[1] = HiOps[0];
4671 HiOps[2] = Lo.getValue(1);
4672 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
4677 // If we can emit an efficient shift operation, do so now.
4678 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4681 // If this target supports SHL_PARTS, use it.
4682 TargetLowering::LegalizeAction Action =
4683 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
4684 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4685 Action == TargetLowering::Custom) {
4686 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4690 // Otherwise, emit a libcall.
4691 Lo = ExpandLibCall("__ashldi3", Node, Hi);
4696 // If the target wants custom lowering, do so.
4697 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4698 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
4699 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
4700 Op = TLI.LowerOperation(Op, DAG);
4702 // Now that the custom expander is done, expand the result, which is
4704 ExpandOp(Op, Lo, Hi);
4709 // If we can emit an efficient shift operation, do so now.
4710 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
4713 // If this target supports SRA_PARTS, use it.
4714 TargetLowering::LegalizeAction Action =
4715 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
4716 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4717 Action == TargetLowering::Custom) {
4718 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4722 // Otherwise, emit a libcall.
4723 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
4728 // If the target wants custom lowering, do so.
4729 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4730 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
4731 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
4732 Op = TLI.LowerOperation(Op, DAG);
4734 // Now that the custom expander is done, expand the result, which is
4736 ExpandOp(Op, Lo, Hi);
4741 // If we can emit an efficient shift operation, do so now.
4742 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4745 // If this target supports SRL_PARTS, use it.
4746 TargetLowering::LegalizeAction Action =
4747 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
4748 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4749 Action == TargetLowering::Custom) {
4750 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4754 // Otherwise, emit a libcall.
4755 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
4761 // If the target wants to custom expand this, let them.
4762 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
4763 TargetLowering::Custom) {
4764 Op = TLI.LowerOperation(Op, DAG);
4766 ExpandOp(Op, Lo, Hi);
4771 // Expand the subcomponents.
4772 SDOperand LHSL, LHSH, RHSL, RHSH;
4773 ExpandOp(Node->getOperand(0), LHSL, LHSH);
4774 ExpandOp(Node->getOperand(1), RHSL, RHSH);
4775 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
4776 SDOperand LoOps[2], HiOps[3];
4781 if (Node->getOpcode() == ISD::ADD) {
4782 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
4783 HiOps[2] = Lo.getValue(1);
4784 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
4786 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
4787 HiOps[2] = Lo.getValue(1);
4788 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
4793 // If the target wants to custom expand this, let them.
4794 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
4795 SDOperand New = TLI.LowerOperation(Op, DAG);
4797 ExpandOp(New, Lo, Hi);
4802 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
4803 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
4804 if (HasMULHS || HasMULHU) {
4805 SDOperand LL, LH, RL, RH;
4806 ExpandOp(Node->getOperand(0), LL, LH);
4807 ExpandOp(Node->getOperand(1), RL, RH);
4808 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
4809 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
4810 // extended the sign bit of the low half through the upper half, and if so
4811 // emit a MULHS instead of the alternate sequence that is valid for any
4812 // i64 x i64 multiply.
4814 // is RH an extension of the sign bit of RL?
4815 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
4816 RH.getOperand(1).getOpcode() == ISD::Constant &&
4817 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
4818 // is LH an extension of the sign bit of LL?
4819 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
4820 LH.getOperand(1).getOpcode() == ISD::Constant &&
4821 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
4822 // FIXME: Move this to the dag combiner.
4825 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4827 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
4829 } else if (HasMULHU) {
4831 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4834 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
4835 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
4836 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
4837 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
4838 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
4843 Lo = ExpandLibCall("__muldi3" , Node, Hi);
4846 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
4847 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
4848 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
4849 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
4852 // Make sure the resultant values have been legalized themselves, unless this
4853 // is a type that requires multi-step expansion.
4854 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
4855 Lo = LegalizeOp(Lo);
4856 Hi = LegalizeOp(Hi);
4859 // Remember in a map if the values will be reused later.
4861 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4862 assert(isNew && "Value already expanded?!?");
4865 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
4866 /// two smaller values of MVT::Vector type.
4867 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
4869 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
4870 SDNode *Node = Op.Val;
4871 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
4872 assert(NumElements > 1 && "Cannot split a single element vector!");
4873 unsigned NewNumElts = NumElements/2;
4874 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
4875 SDOperand TypeNode = *(Node->op_end()-1);
4877 // See if we already split it.
4878 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4879 = SplitNodes.find(Op);
4880 if (I != SplitNodes.end()) {
4881 Lo = I->second.first;
4882 Hi = I->second.second;
4886 switch (Node->getOpcode()) {
4891 assert(0 && "Unhandled operation in SplitVectorOp!");
4892 case ISD::VBUILD_VECTOR: {
4893 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
4894 Node->op_begin()+NewNumElts);
4895 LoOps.push_back(NewNumEltsNode);
4896 LoOps.push_back(TypeNode);
4897 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size());
4899 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
4901 HiOps.push_back(NewNumEltsNode);
4902 HiOps.push_back(TypeNode);
4903 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size());
4914 SDOperand LL, LH, RL, RH;
4915 SplitVectorOp(Node->getOperand(0), LL, LH);
4916 SplitVectorOp(Node->getOperand(1), RL, RH);
4918 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
4919 NewNumEltsNode, TypeNode);
4920 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
4921 NewNumEltsNode, TypeNode);
4925 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4926 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4927 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4929 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4930 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
4931 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4932 getIntPtrConstant(IncrementSize));
4933 // FIXME: This creates a bogus srcvalue!
4934 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4936 // Build a factor node to remember that this load is independent of the
4938 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4941 // Remember that we legalized the chain.
4942 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4945 case ISD::VBIT_CONVERT: {
4946 // We know the result is a vector. The input may be either a vector or a
4948 if (Op.getOperand(0).getValueType() != MVT::Vector) {
4949 // Lower to a store/load. FIXME: this could be improved probably.
4950 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
4952 SDOperand St = DAG.getStore(DAG.getEntryNode(),
4953 Op.getOperand(0), Ptr, NULL, 0);
4954 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4955 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0));
4956 SplitVectorOp(St, Lo, Hi);
4958 // If the input is a vector type, we have to either scalarize it, pack it
4959 // or convert it based on whether the input vector type is legal.
4960 SDNode *InVal = Node->getOperand(0).Val;
4962 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
4963 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
4965 // If the input is from a single element vector, scalarize the vector,
4966 // then treat like a scalar.
4967 if (NumElems == 1) {
4968 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT);
4969 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar,
4970 Op.getOperand(1), Op.getOperand(2));
4971 SplitVectorOp(Scalar, Lo, Hi);
4973 // Split the input vector.
4974 SplitVectorOp(Op.getOperand(0), Lo, Hi);
4976 // Convert each of the pieces now.
4977 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo,
4978 NewNumEltsNode, TypeNode);
4979 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi,
4980 NewNumEltsNode, TypeNode);
4987 // Remember in a map if the values will be reused later.
4989 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4990 assert(isNew && "Value already expanded?!?");
4994 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
4995 /// equivalent operation that returns a scalar (e.g. F32) or packed value
4996 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
4997 /// type for the result.
4998 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
4999 MVT::ValueType NewVT) {
5000 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
5001 SDNode *Node = Op.Val;
5003 // See if we already packed it.
5004 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
5005 if (I != PackedNodes.end()) return I->second;
5008 switch (Node->getOpcode()) {
5011 Node->dump(); std::cerr << "\n";
5013 assert(0 && "Unknown vector operation in PackVectorOp!");
5022 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
5024 PackVectorOp(Node->getOperand(0), NewVT),
5025 PackVectorOp(Node->getOperand(1), NewVT));
5028 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
5029 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
5031 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
5032 Result = DAG.getLoad(NewVT, Ch, Ptr, SV->getValue(), SV->getOffset());
5034 // Remember that we legalized the chain.
5035 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
5038 case ISD::VBUILD_VECTOR:
5039 if (Node->getOperand(0).getValueType() == NewVT) {
5040 // Returning a scalar?
5041 Result = Node->getOperand(0);
5043 // Returning a BUILD_VECTOR?
5045 // If all elements of the build_vector are undefs, return an undef.
5046 bool AllUndef = true;
5047 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i)
5048 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) {
5053 Result = DAG.getNode(ISD::UNDEF, NewVT);
5055 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(),
5056 Node->getNumOperands()-2);
5060 case ISD::VINSERT_VECTOR_ELT:
5061 if (!MVT::isVector(NewVT)) {
5062 // Returning a scalar? Must be the inserted element.
5063 Result = Node->getOperand(1);
5065 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
5066 PackVectorOp(Node->getOperand(0), NewVT),
5067 Node->getOperand(1), Node->getOperand(2));
5070 case ISD::VVECTOR_SHUFFLE:
5071 if (!MVT::isVector(NewVT)) {
5072 // Returning a scalar? Figure out if it is the LHS or RHS and return it.
5073 SDOperand EltNum = Node->getOperand(2).getOperand(0);
5074 if (cast<ConstantSDNode>(EltNum)->getValue())
5075 Result = PackVectorOp(Node->getOperand(1), NewVT);
5077 Result = PackVectorOp(Node->getOperand(0), NewVT);
5079 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index
5080 // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
5081 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
5082 Node->getOperand(2).Val->op_end()-2);
5083 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
5084 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT,
5085 Node->getOperand(2).Val->op_begin(),
5086 Node->getOperand(2).Val->getNumOperands()-2);
5088 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
5089 PackVectorOp(Node->getOperand(0), NewVT),
5090 PackVectorOp(Node->getOperand(1), NewVT), BV);
5093 case ISD::VBIT_CONVERT:
5094 if (Op.getOperand(0).getValueType() != MVT::Vector)
5095 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
5097 // If the input is a vector type, we have to either scalarize it, pack it
5098 // or convert it based on whether the input vector type is legal.
5099 SDNode *InVal = Node->getOperand(0).Val;
5101 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
5102 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
5104 // Figure out if there is a Packed type corresponding to this Vector
5105 // type. If so, convert to the packed type.
5106 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
5107 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
5108 // Turn this into a bit convert of the packed input.
5109 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5110 PackVectorOp(Node->getOperand(0), TVT));
5112 } else if (NumElems == 1) {
5113 // Turn this into a bit convert of the scalar input.
5114 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5115 PackVectorOp(Node->getOperand(0), EVT));
5119 assert(0 && "Cast from unsupported vector type not implemented yet!");
5124 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
5125 PackVectorOp(Op.getOperand(1), NewVT),
5126 PackVectorOp(Op.getOperand(2), NewVT));
5130 if (TLI.isTypeLegal(NewVT))
5131 Result = LegalizeOp(Result);
5132 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
5133 assert(isNew && "Value already packed?");
5138 // SelectionDAG::Legalize - This is the entry point for the file.
5140 void SelectionDAG::Legalize() {
5141 if (ViewLegalizeDAGs) viewGraph();
5143 /// run - This is the main entry point to this class.
5145 SelectionDAGLegalize(*this).LegalizeDAG();