1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 #define DEBUG_TYPE "legalize-types"
29 //===----------------------------------------------------------------------===//
30 // Integer Result Promotion
31 //===----------------------------------------------------------------------===//
33 /// PromoteIntegerResult - This method is called when a result of a node is
34 /// found to be in need of promotion to a larger type. At this point, the node
35 /// may also have invalid operands or may have other results that need
36 /// expansion, we just know that (at least) one result needs promotion.
37 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
38 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
39 SDValue Res = SDValue();
41 // See if the target wants to custom expand this node.
42 if (CustomLowerNode(N, N->getValueType(ResNo), true))
45 switch (N->getOpcode()) {
48 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
49 N->dump(&DAG); dbgs() << "\n";
51 llvm_unreachable("Do not know how to promote this operator!");
52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
56 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
57 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
58 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
59 case ISD::CONVERT_RNDSAT:
60 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
61 case ISD::CTLZ_ZERO_UNDEF:
62 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
63 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
64 case ISD::CTTZ_ZERO_UNDEF:
65 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
66 case ISD::EXTRACT_VECTOR_ELT:
67 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
68 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
69 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
70 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
71 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
72 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
73 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
74 case ISD::SIGN_EXTEND_INREG:
75 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
76 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
77 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
78 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
79 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
80 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
82 case ISD::EXTRACT_SUBVECTOR:
83 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
84 case ISD::VECTOR_SHUFFLE:
85 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
86 case ISD::INSERT_VECTOR_ELT:
87 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
88 case ISD::BUILD_VECTOR:
89 Res = PromoteIntRes_BUILD_VECTOR(N); break;
90 case ISD::SCALAR_TO_VECTOR:
91 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
92 case ISD::CONCAT_VECTORS:
93 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
95 case ISD::SIGN_EXTEND:
96 case ISD::ZERO_EXTEND:
97 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
100 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
102 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
109 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
112 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
115 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
118 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
120 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
122 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
124 case ISD::ATOMIC_LOAD:
125 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
127 case ISD::ATOMIC_LOAD_ADD:
128 case ISD::ATOMIC_LOAD_SUB:
129 case ISD::ATOMIC_LOAD_AND:
130 case ISD::ATOMIC_LOAD_OR:
131 case ISD::ATOMIC_LOAD_XOR:
132 case ISD::ATOMIC_LOAD_NAND:
133 case ISD::ATOMIC_LOAD_MIN:
134 case ISD::ATOMIC_LOAD_MAX:
135 case ISD::ATOMIC_LOAD_UMIN:
136 case ISD::ATOMIC_LOAD_UMAX:
137 case ISD::ATOMIC_SWAP:
138 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
140 case ISD::ATOMIC_CMP_SWAP:
141 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
142 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
146 // If the result is null then the sub-method took care of registering it.
148 SetPromotedInteger(SDValue(N, ResNo), Res);
151 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
153 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
154 return GetPromotedInteger(Op);
157 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
158 // Sign-extend the new bits, and continue the assertion.
159 SDValue Op = SExtPromotedInteger(N->getOperand(0));
160 return DAG.getNode(ISD::AssertSext, SDLoc(N),
161 Op.getValueType(), Op, N->getOperand(1));
164 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
165 // Zero the new bits, and continue the assertion.
166 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
167 return DAG.getNode(ISD::AssertZext, SDLoc(N),
168 Op.getValueType(), Op, N->getOperand(1));
171 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
172 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
173 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
174 N->getMemoryVT(), ResVT,
175 N->getChain(), N->getBasePtr(),
176 N->getMemOperand(), N->getOrdering(),
178 // Legalized the chain result - switch anything that used the old chain to
180 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
184 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
185 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
186 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
188 N->getChain(), N->getBasePtr(),
189 Op2, N->getMemOperand(), N->getOrdering(),
191 // Legalized the chain result - switch anything that used the old chain to
193 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
197 SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
200 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
201 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
202 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
204 // Only use the result of getSetCCResultType if it is legal,
205 // otherwise just use the promoted result type (NVT).
206 if (!TLI.isTypeLegal(SVT))
209 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
210 SDValue Res = DAG.getAtomicCmpSwap(
211 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
212 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
213 N->getMemOperand(), N->getSuccessOrdering(), N->getFailureOrdering(),
215 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
216 ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
217 return Res.getValue(1);
220 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
221 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
223 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
224 SDValue Res = DAG.getAtomicCmpSwap(
225 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
226 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(),
227 N->getFailureOrdering(), N->getSynchScope());
228 // Update the use to N with the newly created Res.
229 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
230 ReplaceValueWith(SDValue(N, i), Res.getValue(i));
234 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
235 SDValue InOp = N->getOperand(0);
236 EVT InVT = InOp.getValueType();
237 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
238 EVT OutVT = N->getValueType(0);
239 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
242 switch (getTypeAction(InVT)) {
243 case TargetLowering::TypeLegal:
245 case TargetLowering::TypePromoteInteger:
246 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
247 // The input promotes to the same size. Convert the promoted value.
248 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
250 case TargetLowering::TypeSoftenFloat:
251 // Promote the integer operand by hand.
252 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
253 case TargetLowering::TypeExpandInteger:
254 case TargetLowering::TypeExpandFloat:
256 case TargetLowering::TypeScalarizeVector:
257 // Convert the element to an integer and promote it by hand.
258 if (!NOutVT.isVector())
259 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
260 BitConvertToInteger(GetScalarizedVector(InOp)));
262 case TargetLowering::TypeSplitVector: {
263 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
264 // pieces of the input into integers and reassemble in the final type.
266 GetSplitVector(N->getOperand(0), Lo, Hi);
267 Lo = BitConvertToInteger(Lo);
268 Hi = BitConvertToInteger(Hi);
270 if (TLI.isBigEndian())
273 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
274 EVT::getIntegerVT(*DAG.getContext(),
275 NOutVT.getSizeInBits()),
276 JoinIntegers(Lo, Hi));
277 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
279 case TargetLowering::TypeWidenVector:
280 // The input is widened to the same size. Convert to the widened value.
281 // Make sure that the outgoing value is not a vector, because this would
282 // make us bitcast between two vectors which are legalized in different ways.
283 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
284 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
287 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
288 CreateStackStoreLoad(InOp, OutVT));
291 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
292 SDValue Op = GetPromotedInteger(N->getOperand(0));
293 EVT OVT = N->getValueType(0);
294 EVT NVT = Op.getValueType();
297 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
298 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
299 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
302 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
303 // The pair element type may be legal, or may not promote to the same type as
304 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
305 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
306 TLI.getTypeToTransformTo(*DAG.getContext(),
307 N->getValueType(0)), JoinIntegers(N->getOperand(0),
311 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
312 EVT VT = N->getValueType(0);
313 // FIXME there is no actual debug info here
315 // Zero extend things like i1, sign extend everything else. It shouldn't
316 // matter in theory which one we pick, but this tends to give better code?
317 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
318 SDValue Result = DAG.getNode(Opc, dl,
319 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
321 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
325 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
326 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
327 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
328 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
329 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
330 "can only promote integers");
331 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
332 return DAG.getConvertRndSat(OutVT, SDLoc(N), N->getOperand(0),
333 N->getOperand(1), N->getOperand(2),
334 N->getOperand(3), N->getOperand(4), CvtCode);
337 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
338 // Zero extend to the promoted type and do the count there.
339 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
341 EVT OVT = N->getValueType(0);
342 EVT NVT = Op.getValueType();
343 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
344 // Subtract off the extra leading bits in the bigger type.
345 return DAG.getNode(ISD::SUB, dl, NVT, Op,
346 DAG.getConstant(NVT.getSizeInBits() -
347 OVT.getSizeInBits(), NVT));
350 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
351 // Zero extend to the promoted type and do the count there.
352 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
353 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
356 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
357 SDValue Op = GetPromotedInteger(N->getOperand(0));
358 EVT OVT = N->getValueType(0);
359 EVT NVT = Op.getValueType();
361 if (N->getOpcode() == ISD::CTTZ) {
362 // The count is the same in the promoted type except if the original
363 // value was zero. This can be handled by setting the bit just off
364 // the top of the original type.
365 APInt TopBit(NVT.getSizeInBits(), 0);
366 TopBit.setBit(OVT.getSizeInBits());
367 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
369 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
372 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
374 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
375 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
379 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
380 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
381 unsigned NewOpc = N->getOpcode();
384 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
385 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
386 // and SINT conversions are Custom, there is no way to tell which is
387 // preferable. We choose SINT because that's the right thing on PPC.)
388 if (N->getOpcode() == ISD::FP_TO_UINT &&
389 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
390 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
391 NewOpc = ISD::FP_TO_SINT;
393 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
395 // Assert that the converted value fits in the original type. If it doesn't
396 // (eg: because the value being converted is too big), then the result of the
397 // original operation was undefined anyway, so the assert is still correct.
398 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
399 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
400 DAG.getValueType(N->getValueType(0).getScalarType()));
403 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
404 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
407 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
409 return DAG.getNode(ISD::AssertZext, dl,
410 NVT, Res, DAG.getValueType(N->getValueType(0)));
413 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
414 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
417 if (getTypeAction(N->getOperand(0).getValueType())
418 == TargetLowering::TypePromoteInteger) {
419 SDValue Res = GetPromotedInteger(N->getOperand(0));
420 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
422 // If the result and operand types are the same after promotion, simplify
423 // to an in-register extension.
424 if (NVT == Res.getValueType()) {
425 // The high bits are not guaranteed to be anything. Insert an extend.
426 if (N->getOpcode() == ISD::SIGN_EXTEND)
427 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
428 DAG.getValueType(N->getOperand(0).getValueType()));
429 if (N->getOpcode() == ISD::ZERO_EXTEND)
430 return DAG.getZeroExtendInReg(Res, dl,
431 N->getOperand(0).getValueType().getScalarType());
432 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
437 // Otherwise, just extend the original operand all the way to the larger type.
438 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
441 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
442 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
443 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
444 ISD::LoadExtType ExtType =
445 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
447 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
448 N->getMemoryVT(), N->getMemOperand());
450 // Legalized the chain result - switch anything that used the old chain to
452 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
456 /// Promote the overflow flag of an overflowing arithmetic node.
457 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
458 // Simply change the return type of the boolean result.
459 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
460 EVT ValueVTs[] = { N->getValueType(0), NVT };
461 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
462 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
463 DAG.getVTList(ValueVTs), Ops);
465 // Modified the sum result - switch anything that used the old sum to use
467 ReplaceValueWith(SDValue(N, 0), Res);
469 return SDValue(Res.getNode(), 1);
472 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
474 return PromoteIntRes_Overflow(N);
476 // The operation overflowed iff the result in the larger type is not the
477 // sign extension of its truncation to the original type.
478 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
479 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
480 EVT OVT = N->getOperand(0).getValueType();
481 EVT NVT = LHS.getValueType();
484 // Do the arithmetic in the larger type.
485 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
486 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
488 // Calculate the overflow flag: sign extend the arithmetic result from
489 // the original type.
490 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
491 DAG.getValueType(OVT));
492 // Overflowed if and only if this is not equal to Res.
493 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
495 // Use the calculated overflow everywhere.
496 ReplaceValueWith(SDValue(N, 1), Ofl);
501 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
502 // Sign extend the input.
503 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
504 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
505 return DAG.getNode(N->getOpcode(), SDLoc(N),
506 LHS.getValueType(), LHS, RHS);
509 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
510 SDValue LHS = GetPromotedInteger(N->getOperand(1));
511 SDValue RHS = GetPromotedInteger(N->getOperand(2));
512 return DAG.getSelect(SDLoc(N),
513 LHS.getValueType(), N->getOperand(0), LHS, RHS);
516 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
517 SDValue Mask = N->getOperand(0);
518 EVT OpTy = N->getOperand(1).getValueType();
520 // Promote all the way up to the canonical SetCC type.
521 Mask = PromoteTargetBoolean(Mask, OpTy);
522 SDValue LHS = GetPromotedInteger(N->getOperand(1));
523 SDValue RHS = GetPromotedInteger(N->getOperand(2));
524 return DAG.getNode(ISD::VSELECT, SDLoc(N),
525 LHS.getValueType(), Mask, LHS, RHS);
528 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
529 SDValue LHS = GetPromotedInteger(N->getOperand(2));
530 SDValue RHS = GetPromotedInteger(N->getOperand(3));
531 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
532 LHS.getValueType(), N->getOperand(0),
533 N->getOperand(1), LHS, RHS, N->getOperand(4));
536 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
537 EVT SVT = getSetCCResultType(N->getOperand(0).getValueType());
539 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
541 // Only use the result of getSetCCResultType if it is legal,
542 // otherwise just use the promoted result type (NVT).
543 if (!TLI.isTypeLegal(SVT))
547 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
548 "Vector compare must return a vector result!");
550 SDValue LHS = N->getOperand(0);
551 SDValue RHS = N->getOperand(1);
552 if (LHS.getValueType() != RHS.getValueType()) {
553 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger &&
554 !LHS.getValueType().isVector())
555 LHS = GetPromotedInteger(LHS);
556 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger &&
557 !RHS.getValueType().isVector())
558 RHS = GetPromotedInteger(RHS);
561 // Get the SETCC result using the canonical SETCC type.
562 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
565 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
566 // Convert to the expected type.
567 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
570 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
571 SDValue Res = GetPromotedInteger(N->getOperand(0));
572 SDValue Amt = N->getOperand(1);
573 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
574 return DAG.getNode(ISD::SHL, SDLoc(N), Res.getValueType(), Res, Amt);
577 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
578 SDValue Op = GetPromotedInteger(N->getOperand(0));
579 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
580 Op.getValueType(), Op, N->getOperand(1));
583 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
584 // The input may have strange things in the top bits of the registers, but
585 // these operations don't care. They may have weird bits going out, but
586 // that too is okay if they are integer operations.
587 SDValue LHS = GetPromotedInteger(N->getOperand(0));
588 SDValue RHS = GetPromotedInteger(N->getOperand(1));
589 return DAG.getNode(N->getOpcode(), SDLoc(N),
590 LHS.getValueType(), LHS, RHS);
593 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
594 // The input value must be properly sign extended.
595 SDValue Res = SExtPromotedInteger(N->getOperand(0));
596 SDValue Amt = N->getOperand(1);
597 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
598 return DAG.getNode(ISD::SRA, SDLoc(N), Res.getValueType(), Res, Amt);
601 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
602 // The input value must be properly zero extended.
603 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
604 SDValue Amt = N->getOperand(1);
605 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
606 return DAG.getNode(ISD::SRL, SDLoc(N), Res.getValueType(), Res, Amt);
609 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
610 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
612 SDValue InOp = N->getOperand(0);
615 switch (getTypeAction(InOp.getValueType())) {
616 default: llvm_unreachable("Unknown type action!");
617 case TargetLowering::TypeLegal:
618 case TargetLowering::TypeExpandInteger:
621 case TargetLowering::TypePromoteInteger:
622 Res = GetPromotedInteger(InOp);
624 case TargetLowering::TypeSplitVector:
625 EVT InVT = InOp.getValueType();
626 assert(InVT.isVector() && "Cannot split scalar types");
627 unsigned NumElts = InVT.getVectorNumElements();
628 assert(NumElts == NVT.getVectorNumElements() &&
629 "Dst and Src must have the same number of elements");
630 assert(isPowerOf2_32(NumElts) &&
631 "Promoted vector type must be a power of two");
634 GetSplitVector(InOp, EOp1, EOp2);
636 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
638 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
639 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
641 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
644 // Truncate to NVT instead of VT
645 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
648 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
650 return PromoteIntRes_Overflow(N);
652 // The operation overflowed iff the result in the larger type is not the
653 // zero extension of its truncation to the original type.
654 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
655 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
656 EVT OVT = N->getOperand(0).getValueType();
657 EVT NVT = LHS.getValueType();
660 // Do the arithmetic in the larger type.
661 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
662 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
664 // Calculate the overflow flag: zero extend the arithmetic result from
665 // the original type.
666 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
667 // Overflowed if and only if this is not equal to Res.
668 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
670 // Use the calculated overflow everywhere.
671 ReplaceValueWith(SDValue(N, 1), Ofl);
676 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
677 // Promote the overflow bit trivially.
679 return PromoteIntRes_Overflow(N);
681 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
683 EVT SmallVT = LHS.getValueType();
685 // To determine if the result overflowed in a larger type, we extend the
686 // input to the larger type, do the multiply (checking if it overflows),
687 // then also check the high bits of the result to see if overflow happened
689 if (N->getOpcode() == ISD::SMULO) {
690 LHS = SExtPromotedInteger(LHS);
691 RHS = SExtPromotedInteger(RHS);
693 LHS = ZExtPromotedInteger(LHS);
694 RHS = ZExtPromotedInteger(RHS);
696 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
697 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
699 // Overflow occurred if it occurred in the larger type, or if the high part
700 // of the result does not zero/sign-extend the low part. Check this second
701 // possibility first.
703 if (N->getOpcode() == ISD::UMULO) {
704 // Unsigned overflow occurred if the high part is non-zero.
705 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
706 DAG.getIntPtrConstant(SmallVT.getSizeInBits()));
707 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
708 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
710 // Signed overflow occurred if the high part does not sign extend the low.
711 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
712 Mul, DAG.getValueType(SmallVT));
713 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
716 // The only other way for overflow to occur is if the multiplication in the
717 // larger type itself overflowed.
718 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
719 SDValue(Mul.getNode(), 1));
721 // Use the calculated overflow everywhere.
722 ReplaceValueWith(SDValue(N, 1), Overflow);
726 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
727 // Zero extend the input.
728 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
729 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
730 return DAG.getNode(N->getOpcode(), SDLoc(N),
731 LHS.getValueType(), LHS, RHS);
734 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
735 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
736 N->getValueType(0)));
739 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
740 SDValue Chain = N->getOperand(0); // Get the chain.
741 SDValue Ptr = N->getOperand(1); // Get the pointer.
742 EVT VT = N->getValueType(0);
745 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
746 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
747 // The argument is passed as NumRegs registers of type RegVT.
749 SmallVector<SDValue, 8> Parts(NumRegs);
750 for (unsigned i = 0; i < NumRegs; ++i) {
751 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
752 N->getConstantOperandVal(3));
753 Chain = Parts[i].getValue(1);
756 // Handle endianness of the load.
757 if (TLI.isBigEndian())
758 std::reverse(Parts.begin(), Parts.end());
760 // Assemble the parts in the promoted type.
761 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
762 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
763 for (unsigned i = 1; i < NumRegs; ++i) {
764 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
765 // Shift it to the right position and "or" it in.
766 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
767 DAG.getConstant(i * RegVT.getSizeInBits(),
768 TLI.getPointerTy()));
769 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
772 // Modified the chain result - switch anything that used the old chain to
774 ReplaceValueWith(SDValue(N, 1), Chain);
779 //===----------------------------------------------------------------------===//
780 // Integer Operand Promotion
781 //===----------------------------------------------------------------------===//
783 /// PromoteIntegerOperand - This method is called when the specified operand of
784 /// the specified node is found to need promotion. At this point, all of the
785 /// result types of the node are known to be legal, but other operands of the
786 /// node may need promotion or expansion as well as the specified one.
787 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
788 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
789 SDValue Res = SDValue();
791 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
794 switch (N->getOpcode()) {
797 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
798 N->dump(&DAG); dbgs() << "\n";
800 llvm_unreachable("Do not know how to promote this operator's operand!");
802 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
803 case ISD::ATOMIC_STORE:
804 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
806 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
807 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
808 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
809 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
810 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
811 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
812 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
813 case ISD::CONVERT_RNDSAT:
814 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
815 case ISD::INSERT_VECTOR_ELT:
816 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
817 case ISD::SCALAR_TO_VECTOR:
818 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
820 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
821 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
822 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
823 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
824 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
825 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
827 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
828 case ISD::FP16_TO_FP:
829 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
830 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
836 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
839 // If the result is null, the sub-method took care of registering results etc.
840 if (!Res.getNode()) return false;
842 // If the result is N, the sub-method updated N in place. Tell the legalizer
844 if (Res.getNode() == N)
847 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
848 "Invalid operand expansion");
850 ReplaceValueWith(SDValue(N, 0), Res);
854 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
855 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
856 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
857 ISD::CondCode CCCode) {
858 // We have to insert explicit sign or zero extends. Note that we could
859 // insert sign extends for ALL conditions, but zero extend is cheaper on
860 // many machines (an AND instead of two shifts), so prefer it.
862 default: llvm_unreachable("Unknown integer comparison!");
869 // ALL of these operations will work if we either sign or zero extend
870 // the operands (including the unsigned comparisons!). Zero extend is
871 // usually a simpler/cheaper operation, so prefer it.
872 NewLHS = ZExtPromotedInteger(NewLHS);
873 NewRHS = ZExtPromotedInteger(NewRHS);
879 NewLHS = SExtPromotedInteger(NewLHS);
880 NewRHS = SExtPromotedInteger(NewRHS);
885 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
886 SDValue Op = GetPromotedInteger(N->getOperand(0));
887 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
890 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
891 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
892 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
893 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
894 N->getOrdering(), N->getSynchScope());
897 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
898 // This should only occur in unusual situations like bitcasting to an
899 // x86_fp80, so just turn it into a store+load
900 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
903 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
904 assert(OpNo == 2 && "Don't know how to promote this operand!");
906 SDValue LHS = N->getOperand(2);
907 SDValue RHS = N->getOperand(3);
908 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
910 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
912 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
913 N->getOperand(1), LHS, RHS, N->getOperand(4)),
917 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
918 assert(OpNo == 1 && "only know how to promote condition");
920 // Promote all the way up to the canonical SetCC type.
921 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
923 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
924 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
925 N->getOperand(2)), 0);
928 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
929 // Since the result type is legal, the operands must promote to it.
930 EVT OVT = N->getOperand(0).getValueType();
931 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
932 SDValue Hi = GetPromotedInteger(N->getOperand(1));
933 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
936 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
937 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
938 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
941 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
942 // The vector type is legal but the element type is not. This implies
943 // that the vector is a power-of-two in length and that the element
944 // type does not have a strange size (eg: it is not i1).
945 EVT VecVT = N->getValueType(0);
946 unsigned NumElts = VecVT.getVectorNumElements();
947 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
948 "Legal vector of one illegal element?");
950 // Promote the inserted value. The type does not need to match the
951 // vector element type. Check that any extra bits introduced will be
953 assert(N->getOperand(0).getValueType().getSizeInBits() >=
954 N->getValueType(0).getVectorElementType().getSizeInBits() &&
955 "Type of inserted value narrower than vector element type!");
957 SmallVector<SDValue, 16> NewOps;
958 for (unsigned i = 0; i < NumElts; ++i)
959 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
961 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
964 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
965 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
966 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
967 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
968 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
969 "can only promote integer arguments");
970 SDValue InOp = GetPromotedInteger(N->getOperand(0));
971 return DAG.getConvertRndSat(N->getValueType(0), SDLoc(N), InOp,
972 N->getOperand(1), N->getOperand(2),
973 N->getOperand(3), N->getOperand(4), CvtCode);
976 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
979 // Promote the inserted value. This is valid because the type does not
980 // have to match the vector element type.
982 // Check that any extra bits introduced will be truncated away.
983 assert(N->getOperand(1).getValueType().getSizeInBits() >=
984 N->getValueType(0).getVectorElementType().getSizeInBits() &&
985 "Type of inserted value narrower than vector element type!");
986 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
987 GetPromotedInteger(N->getOperand(1)),
992 assert(OpNo == 2 && "Different operand and result vector types?");
994 // Promote the index.
995 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
996 TLI.getVectorIdxTy());
997 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
998 N->getOperand(1), Idx), 0);
1001 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1002 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1003 // the operand in place.
1004 return SDValue(DAG.UpdateNodeOperands(N,
1005 GetPromotedInteger(N->getOperand(0))), 0);
1008 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1009 assert(OpNo == 0 && "Only know how to promote the condition!");
1010 SDValue Cond = N->getOperand(0);
1011 EVT OpTy = N->getOperand(1).getValueType();
1013 // Promote all the way up to the canonical SetCC type.
1014 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1015 Cond = PromoteTargetBoolean(Cond, OpVT);
1017 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1018 N->getOperand(2)), 0);
1021 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1022 assert(OpNo == 0 && "Don't know how to promote this operand!");
1024 SDValue LHS = N->getOperand(0);
1025 SDValue RHS = N->getOperand(1);
1026 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1028 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1029 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1030 N->getOperand(3), N->getOperand(4)), 0);
1033 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1034 assert(OpNo == 0 && "Don't know how to promote this operand!");
1036 SDValue LHS = N->getOperand(0);
1037 SDValue RHS = N->getOperand(1);
1038 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1040 // The CC (#2) is always legal.
1041 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1044 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1045 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1046 ZExtPromotedInteger(N->getOperand(1))), 0);
1049 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1050 SDValue Op = GetPromotedInteger(N->getOperand(0));
1052 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1053 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1054 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1057 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1058 return SDValue(DAG.UpdateNodeOperands(N,
1059 SExtPromotedInteger(N->getOperand(0))), 0);
1062 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1063 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1064 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1067 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1069 // Truncate the value and store the result.
1070 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1071 N->getMemoryVT(), N->getMemOperand());
1074 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1075 SDValue Op = GetPromotedInteger(N->getOperand(0));
1076 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1079 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1080 return SDValue(DAG.UpdateNodeOperands(N,
1081 ZExtPromotedInteger(N->getOperand(0))), 0);
1084 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1086 SDValue Op = GetPromotedInteger(N->getOperand(0));
1087 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1088 return DAG.getZeroExtendInReg(Op, dl,
1089 N->getOperand(0).getValueType().getScalarType());
1093 //===----------------------------------------------------------------------===//
1094 // Integer Result Expansion
1095 //===----------------------------------------------------------------------===//
1097 /// ExpandIntegerResult - This method is called when the specified result of the
1098 /// specified node is found to need expansion. At this point, the node may also
1099 /// have invalid operands or may have other results that need promotion, we just
1100 /// know that (at least) one result needs expansion.
1101 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1102 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1104 Lo = Hi = SDValue();
1106 // See if the target wants to custom expand this node.
1107 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1110 switch (N->getOpcode()) {
1113 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1114 N->dump(&DAG); dbgs() << "\n";
1116 llvm_unreachable("Do not know how to expand the result of this operator!");
1118 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1119 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1120 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1121 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1123 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1124 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1125 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1126 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1127 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1129 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1130 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1131 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1132 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1133 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1134 case ISD::CTLZ_ZERO_UNDEF:
1135 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1136 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1137 case ISD::CTTZ_ZERO_UNDEF:
1138 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1139 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1140 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1141 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1142 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1143 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1144 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1145 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1146 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1147 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1148 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1149 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1150 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1151 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1153 case ISD::ATOMIC_LOAD_ADD:
1154 case ISD::ATOMIC_LOAD_SUB:
1155 case ISD::ATOMIC_LOAD_AND:
1156 case ISD::ATOMIC_LOAD_OR:
1157 case ISD::ATOMIC_LOAD_XOR:
1158 case ISD::ATOMIC_LOAD_NAND:
1159 case ISD::ATOMIC_LOAD_MIN:
1160 case ISD::ATOMIC_LOAD_MAX:
1161 case ISD::ATOMIC_LOAD_UMIN:
1162 case ISD::ATOMIC_LOAD_UMAX:
1163 case ISD::ATOMIC_SWAP:
1164 case ISD::ATOMIC_CMP_SWAP: {
1165 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1166 SplitInteger(Tmp.first, Lo, Hi);
1167 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1170 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
1171 AtomicSDNode *AN = cast<AtomicSDNode>(N);
1172 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
1173 SDValue Tmp = DAG.getAtomicCmpSwap(
1174 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
1175 N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
1176 AN->getMemOperand(), AN->getSuccessOrdering(), AN->getFailureOrdering(),
1177 AN->getSynchScope());
1179 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
1180 // success simply by comparing the loaded value against the ingoing
1182 SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
1183 N->getOperand(2), ISD::SETEQ);
1185 SplitInteger(Tmp, Lo, Hi);
1186 ReplaceValueWith(SDValue(N, 1), Success);
1187 ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
1193 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1196 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1199 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1202 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1206 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1209 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1211 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1213 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1216 // If Lo/Hi is null, the sub-method took care of registering results etc.
1218 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1221 /// Lower an atomic node to the appropriate builtin call.
1222 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1223 unsigned Opc = Node->getOpcode();
1224 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1229 llvm_unreachable("Unhandled atomic intrinsic Expand!");
1230 case ISD::ATOMIC_SWAP:
1231 switch (VT.SimpleTy) {
1232 default: llvm_unreachable("Unexpected value type for atomic!");
1233 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
1234 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
1235 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
1236 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
1237 case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;
1240 case ISD::ATOMIC_CMP_SWAP:
1241 switch (VT.SimpleTy) {
1242 default: llvm_unreachable("Unexpected value type for atomic!");
1243 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
1244 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
1245 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
1246 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
1247 case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;
1250 case ISD::ATOMIC_LOAD_ADD:
1251 switch (VT.SimpleTy) {
1252 default: llvm_unreachable("Unexpected value type for atomic!");
1253 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
1254 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
1255 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
1256 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
1257 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;
1260 case ISD::ATOMIC_LOAD_SUB:
1261 switch (VT.SimpleTy) {
1262 default: llvm_unreachable("Unexpected value type for atomic!");
1263 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
1264 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
1265 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
1266 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
1267 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;
1270 case ISD::ATOMIC_LOAD_AND:
1271 switch (VT.SimpleTy) {
1272 default: llvm_unreachable("Unexpected value type for atomic!");
1273 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
1274 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
1275 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
1276 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
1277 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;
1280 case ISD::ATOMIC_LOAD_OR:
1281 switch (VT.SimpleTy) {
1282 default: llvm_unreachable("Unexpected value type for atomic!");
1283 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
1284 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
1285 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
1286 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
1287 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;
1290 case ISD::ATOMIC_LOAD_XOR:
1291 switch (VT.SimpleTy) {
1292 default: llvm_unreachable("Unexpected value type for atomic!");
1293 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
1294 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
1295 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
1296 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
1297 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;
1300 case ISD::ATOMIC_LOAD_NAND:
1301 switch (VT.SimpleTy) {
1302 default: llvm_unreachable("Unexpected value type for atomic!");
1303 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
1304 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
1305 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
1306 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
1307 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;
1312 return ExpandChainLibCall(LC, Node, false);
1315 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1316 /// and the shift amount is a constant 'Amt'. Expand the operation.
1317 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1318 SDValue &Lo, SDValue &Hi) {
1319 assert(Amt && "Expected zero shifts to be already optimized away.");
1321 // Expand the incoming operand to be shifted, so that we have its parts
1323 GetExpandedInteger(N->getOperand(0), InL, InH);
1325 EVT NVT = InL.getValueType();
1326 unsigned VTBits = N->getValueType(0).getSizeInBits();
1327 unsigned NVTBits = NVT.getSizeInBits();
1328 EVT ShTy = N->getOperand(1).getValueType();
1330 if (N->getOpcode() == ISD::SHL) {
1332 Lo = Hi = DAG.getConstant(0, NVT);
1333 } else if (Amt > NVTBits) {
1334 Lo = DAG.getConstant(0, NVT);
1335 Hi = DAG.getNode(ISD::SHL, DL,
1336 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
1337 } else if (Amt == NVTBits) {
1338 Lo = DAG.getConstant(0, NVT);
1340 } else if (Amt == 1 &&
1341 TLI.isOperationLegalOrCustom(ISD::ADDC,
1342 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1343 // Emit this X << 1 as X+X.
1344 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1345 SDValue LoOps[2] = { InL, InL };
1346 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps);
1347 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1348 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps);
1350 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
1351 Hi = DAG.getNode(ISD::OR, DL, NVT,
1352 DAG.getNode(ISD::SHL, DL, NVT, InH,
1353 DAG.getConstant(Amt, ShTy)),
1354 DAG.getNode(ISD::SRL, DL, NVT, InL,
1355 DAG.getConstant(NVTBits-Amt, ShTy)));
1360 if (N->getOpcode() == ISD::SRL) {
1362 Lo = DAG.getConstant(0, NVT);
1363 Hi = DAG.getConstant(0, NVT);
1364 } else if (Amt > NVTBits) {
1365 Lo = DAG.getNode(ISD::SRL, DL,
1366 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1367 Hi = DAG.getConstant(0, NVT);
1368 } else if (Amt == NVTBits) {
1370 Hi = DAG.getConstant(0, NVT);
1372 Lo = DAG.getNode(ISD::OR, DL, NVT,
1373 DAG.getNode(ISD::SRL, DL, NVT, InL,
1374 DAG.getConstant(Amt, ShTy)),
1375 DAG.getNode(ISD::SHL, DL, NVT, InH,
1376 DAG.getConstant(NVTBits-Amt, ShTy)));
1377 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1382 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1384 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1385 DAG.getConstant(NVTBits-1, ShTy));
1386 } else if (Amt > NVTBits) {
1387 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1388 DAG.getConstant(Amt-NVTBits, ShTy));
1389 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1390 DAG.getConstant(NVTBits-1, ShTy));
1391 } else if (Amt == NVTBits) {
1393 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1394 DAG.getConstant(NVTBits-1, ShTy));
1396 Lo = DAG.getNode(ISD::OR, DL, NVT,
1397 DAG.getNode(ISD::SRL, DL, NVT, InL,
1398 DAG.getConstant(Amt, ShTy)),
1399 DAG.getNode(ISD::SHL, DL, NVT, InH,
1400 DAG.getConstant(NVTBits-Amt, ShTy)));
1401 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1405 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1406 /// this shift based on knowledge of the high bit of the shift amount. If we
1407 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1409 bool DAGTypeLegalizer::
1410 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1411 SDValue Amt = N->getOperand(1);
1412 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1413 EVT ShTy = Amt.getValueType();
1414 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1415 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1416 assert(isPowerOf2_32(NVTBits) &&
1417 "Expanded integer type size not a power of two!");
1420 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1421 APInt KnownZero, KnownOne;
1422 DAG.computeKnownBits(N->getOperand(1), KnownZero, KnownOne);
1424 // If we don't know anything about the high bits, exit.
1425 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1428 // Get the incoming operand to be shifted.
1430 GetExpandedInteger(N->getOperand(0), InL, InH);
1432 // If we know that any of the high bits of the shift amount are one, then we
1433 // can do this as a couple of simple shifts.
1434 if (KnownOne.intersects(HighBitMask)) {
1435 // Mask out the high bit, which we know is set.
1436 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1437 DAG.getConstant(~HighBitMask, ShTy));
1439 switch (N->getOpcode()) {
1440 default: llvm_unreachable("Unknown shift");
1442 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1443 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1446 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1447 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1450 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1451 DAG.getConstant(NVTBits-1, ShTy));
1452 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1457 // If we know that all of the high bits of the shift amount are zero, then we
1458 // can do this as a couple of simple shifts.
1459 if ((KnownZero & HighBitMask) == HighBitMask) {
1460 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
1461 // shift if x is zero. We can use XOR here because x is known to be smaller
1463 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1464 DAG.getConstant(NVTBits-1, ShTy));
1467 switch (N->getOpcode()) {
1468 default: llvm_unreachable("Unknown shift");
1469 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1471 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1474 // When shifting right the arithmetic for Lo and Hi is swapped.
1475 if (N->getOpcode() != ISD::SHL)
1476 std::swap(InL, InH);
1478 // Use a little trick to get the bits that move from Lo to Hi. First
1479 // shift by one bit.
1480 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, ShTy));
1481 // Then compute the remaining shift with amount-1.
1482 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
1484 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
1485 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1487 if (N->getOpcode() != ISD::SHL)
1495 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1497 bool DAGTypeLegalizer::
1498 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1499 SDValue Amt = N->getOperand(1);
1500 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1501 EVT ShTy = Amt.getValueType();
1502 unsigned NVTBits = NVT.getSizeInBits();
1503 assert(isPowerOf2_32(NVTBits) &&
1504 "Expanded integer type size not a power of two!");
1507 // Get the incoming operand to be shifted.
1509 GetExpandedInteger(N->getOperand(0), InL, InH);
1511 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1512 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1513 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1514 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1515 Amt, NVBitsNode, ISD::SETULT);
1517 SDValue LoS, HiS, LoL, HiL;
1518 switch (N->getOpcode()) {
1519 default: llvm_unreachable("Unknown shift");
1521 // Short: ShAmt < NVTBits
1522 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1523 HiS = DAG.getNode(ISD::OR, dl, NVT,
1524 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1525 // FIXME: If Amt is zero, the following shift generates an undefined result
1526 // on some architectures.
1527 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1529 // Long: ShAmt >= NVTBits
1530 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1531 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1533 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1534 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1537 // Short: ShAmt < NVTBits
1538 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1539 LoS = DAG.getNode(ISD::OR, dl, NVT,
1540 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1541 // FIXME: If Amt is zero, the following shift generates an undefined result
1542 // on some architectures.
1543 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1545 // Long: ShAmt >= NVTBits
1546 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1547 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1549 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1550 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1553 // Short: ShAmt < NVTBits
1554 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1555 LoS = DAG.getNode(ISD::OR, dl, NVT,
1556 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1557 // FIXME: If Amt is zero, the following shift generates an undefined result
1558 // on some architectures.
1559 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1561 // Long: ShAmt >= NVTBits
1562 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1563 DAG.getConstant(NVTBits-1, ShTy));
1564 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1566 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1567 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1572 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1573 SDValue &Lo, SDValue &Hi) {
1575 // Expand the subcomponents.
1576 SDValue LHSL, LHSH, RHSL, RHSH;
1577 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1578 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1580 EVT NVT = LHSL.getValueType();
1581 SDValue LoOps[2] = { LHSL, RHSL };
1582 SDValue HiOps[3] = { LHSH, RHSH };
1584 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1585 // them. TODO: Teach operation legalization how to expand unsupported
1586 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1587 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1588 // generate a value of this type in the expanded code sequence.
1590 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1591 ISD::ADDC : ISD::SUBC,
1592 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1595 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1596 if (N->getOpcode() == ISD::ADD) {
1597 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1598 HiOps[2] = Lo.getValue(1);
1599 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1601 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1602 HiOps[2] = Lo.getValue(1);
1603 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1608 if (N->getOpcode() == ISD::ADD) {
1609 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
1610 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1611 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
1613 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
1614 DAG.getConstant(1, NVT),
1615 DAG.getConstant(0, NVT));
1616 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
1618 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
1619 DAG.getConstant(1, NVT), Carry1);
1620 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1622 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
1623 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1625 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
1626 LoOps[0], LoOps[1], ISD::SETULT);
1627 SDValue Borrow = DAG.getSelect(dl, NVT, Cmp,
1628 DAG.getConstant(1, NVT),
1629 DAG.getConstant(0, NVT));
1630 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1634 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1635 SDValue &Lo, SDValue &Hi) {
1636 // Expand the subcomponents.
1637 SDValue LHSL, LHSH, RHSL, RHSH;
1639 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1640 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1641 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1642 SDValue LoOps[2] = { LHSL, RHSL };
1643 SDValue HiOps[3] = { LHSH, RHSH };
1645 if (N->getOpcode() == ISD::ADDC) {
1646 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1647 HiOps[2] = Lo.getValue(1);
1648 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1650 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1651 HiOps[2] = Lo.getValue(1);
1652 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1655 // Legalized the flag result - switch anything that used the old flag to
1657 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1660 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1661 SDValue &Lo, SDValue &Hi) {
1662 // Expand the subcomponents.
1663 SDValue LHSL, LHSH, RHSL, RHSH;
1665 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1666 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1667 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1668 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1669 SDValue HiOps[3] = { LHSH, RHSH };
1671 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
1672 HiOps[2] = Lo.getValue(1);
1673 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
1675 // Legalized the flag result - switch anything that used the old flag to
1677 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1680 void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
1681 SDValue &Lo, SDValue &Hi) {
1682 SDValue Res = DisintegrateMERGE_VALUES(N, ResNo);
1683 SplitInteger(Res, Lo, Hi);
1686 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1687 SDValue &Lo, SDValue &Hi) {
1688 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1690 SDValue Op = N->getOperand(0);
1691 if (Op.getValueType().bitsLE(NVT)) {
1692 // The low part is any extension of the input (which degenerates to a copy).
1693 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1694 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1696 // For example, extension of an i48 to an i64. The operand type necessarily
1697 // promotes to the result type, so will end up being expanded too.
1698 assert(getTypeAction(Op.getValueType()) ==
1699 TargetLowering::TypePromoteInteger &&
1700 "Only know how to promote this result!");
1701 SDValue Res = GetPromotedInteger(Op);
1702 assert(Res.getValueType() == N->getValueType(0) &&
1703 "Operand over promoted?");
1704 // Split the promoted operand. This will simplify when it is expanded.
1705 SplitInteger(Res, Lo, Hi);
1709 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1710 SDValue &Lo, SDValue &Hi) {
1712 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1713 EVT NVT = Lo.getValueType();
1714 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1715 unsigned NVTBits = NVT.getSizeInBits();
1716 unsigned EVTBits = EVT.getSizeInBits();
1718 if (NVTBits < EVTBits) {
1719 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1720 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1721 EVTBits - NVTBits)));
1723 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1724 // The high part replicates the sign bit of Lo, make it explicit.
1725 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1726 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1730 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1731 SDValue &Lo, SDValue &Hi) {
1733 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1734 EVT NVT = Lo.getValueType();
1735 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1736 unsigned NVTBits = NVT.getSizeInBits();
1737 unsigned EVTBits = EVT.getSizeInBits();
1739 if (NVTBits < EVTBits) {
1740 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1741 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1742 EVTBits - NVTBits)));
1744 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1745 // The high part must be zero, make it explicit.
1746 Hi = DAG.getConstant(0, NVT);
1750 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1751 SDValue &Lo, SDValue &Hi) {
1753 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1754 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1755 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1758 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1759 SDValue &Lo, SDValue &Hi) {
1760 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1761 unsigned NBitWidth = NVT.getSizeInBits();
1762 auto Constant = cast<ConstantSDNode>(N);
1763 const APInt &Cst = Constant->getAPIntValue();
1764 bool IsTarget = Constant->isTargetOpcode();
1765 bool IsOpaque = Constant->isOpaque();
1766 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT, IsTarget, IsOpaque);
1767 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT, IsTarget,
1771 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1772 SDValue &Lo, SDValue &Hi) {
1774 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1775 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1776 EVT NVT = Lo.getValueType();
1778 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
1779 DAG.getConstant(0, NVT), ISD::SETNE);
1781 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
1782 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1784 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
1785 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1786 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1787 Hi = DAG.getConstant(0, NVT);
1790 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1791 SDValue &Lo, SDValue &Hi) {
1793 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1794 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1795 EVT NVT = Lo.getValueType();
1796 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1797 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1798 Hi = DAG.getConstant(0, NVT);
1801 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1802 SDValue &Lo, SDValue &Hi) {
1804 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1805 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1806 EVT NVT = Lo.getValueType();
1808 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
1809 DAG.getConstant(0, NVT), ISD::SETNE);
1811 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1812 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
1814 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
1815 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1816 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1817 Hi = DAG.getConstant(0, NVT);
1820 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1823 EVT VT = N->getValueType(0);
1824 SDValue Op = N->getOperand(0);
1825 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1826 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1827 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, true/*irrelevant*/,
1832 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1835 EVT VT = N->getValueType(0);
1836 SDValue Op = N->getOperand(0);
1837 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1838 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1839 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, false/*irrelevant*/,
1844 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1845 SDValue &Lo, SDValue &Hi) {
1846 if (ISD::isNormalLoad(N)) {
1847 ExpandRes_NormalLoad(N, Lo, Hi);
1851 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1853 EVT VT = N->getValueType(0);
1854 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1855 SDValue Ch = N->getChain();
1856 SDValue Ptr = N->getBasePtr();
1857 ISD::LoadExtType ExtType = N->getExtensionType();
1858 unsigned Alignment = N->getAlignment();
1859 bool isVolatile = N->isVolatile();
1860 bool isNonTemporal = N->isNonTemporal();
1861 bool isInvariant = N->isInvariant();
1862 AAMDNodes AAInfo = N->getAAInfo();
1865 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1867 if (N->getMemoryVT().bitsLE(NVT)) {
1868 EVT MemVT = N->getMemoryVT();
1870 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1871 MemVT, isVolatile, isNonTemporal, isInvariant,
1874 // Remember the chain.
1875 Ch = Lo.getValue(1);
1877 if (ExtType == ISD::SEXTLOAD) {
1878 // The high part is obtained by SRA'ing all but one of the bits of the
1880 unsigned LoSize = Lo.getValueType().getSizeInBits();
1881 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1882 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1883 } else if (ExtType == ISD::ZEXTLOAD) {
1884 // The high part is just a zero.
1885 Hi = DAG.getConstant(0, NVT);
1887 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1888 // The high part is undefined.
1889 Hi = DAG.getUNDEF(NVT);
1891 } else if (TLI.isLittleEndian()) {
1892 // Little-endian - low bits are at low addresses.
1893 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1894 isVolatile, isNonTemporal, isInvariant, Alignment,
1897 unsigned ExcessBits =
1898 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1899 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1901 // Increment the pointer to the other half.
1902 unsigned IncrementSize = NVT.getSizeInBits()/8;
1903 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1904 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1905 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
1906 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
1907 isVolatile, isNonTemporal, isInvariant,
1908 MinAlign(Alignment, IncrementSize), AAInfo);
1910 // Build a factor node to remember that this load is independent of the
1912 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1915 // Big-endian - high bits are at low addresses. Favor aligned loads at
1916 // the cost of some bit-fiddling.
1917 EVT MemVT = N->getMemoryVT();
1918 unsigned EBytes = MemVT.getStoreSize();
1919 unsigned IncrementSize = NVT.getSizeInBits()/8;
1920 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1922 // Load both the high bits and maybe some of the low bits.
1923 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1924 EVT::getIntegerVT(*DAG.getContext(),
1925 MemVT.getSizeInBits() - ExcessBits),
1926 isVolatile, isNonTemporal, isInvariant, Alignment,
1929 // Increment the pointer to the other half.
1930 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1931 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1932 // Load the rest of the low bits.
1933 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
1934 N->getPointerInfo().getWithOffset(IncrementSize),
1935 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1936 isVolatile, isNonTemporal, isInvariant,
1937 MinAlign(Alignment, IncrementSize), AAInfo);
1939 // Build a factor node to remember that this load is independent of the
1941 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1944 if (ExcessBits < NVT.getSizeInBits()) {
1945 // Transfer low bits from the bottom of Hi to the top of Lo.
1946 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1947 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1948 DAG.getConstant(ExcessBits,
1949 TLI.getPointerTy())));
1950 // Move high bits to the right position in Hi.
1951 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1953 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1954 TLI.getPointerTy()));
1958 // Legalized the chain result - switch anything that used the old chain to
1960 ReplaceValueWith(SDValue(N, 1), Ch);
1963 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1964 SDValue &Lo, SDValue &Hi) {
1966 SDValue LL, LH, RL, RH;
1967 GetExpandedInteger(N->getOperand(0), LL, LH);
1968 GetExpandedInteger(N->getOperand(1), RL, RH);
1969 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1970 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1973 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1974 SDValue &Lo, SDValue &Hi) {
1975 EVT VT = N->getValueType(0);
1976 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1979 SDValue LL, LH, RL, RH;
1980 GetExpandedInteger(N->getOperand(0), LL, LH);
1981 GetExpandedInteger(N->getOperand(1), RL, RH);
1983 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG, LL, LH, RL, RH))
1986 // If nothing else, we can make a libcall.
1987 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1989 LC = RTLIB::MUL_I16;
1990 else if (VT == MVT::i32)
1991 LC = RTLIB::MUL_I32;
1992 else if (VT == MVT::i64)
1993 LC = RTLIB::MUL_I64;
1994 else if (VT == MVT::i128)
1995 LC = RTLIB::MUL_I128;
1996 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1998 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1999 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true/*irrelevant*/,
2004 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
2005 SDValue &Lo, SDValue &Hi) {
2006 SDValue LHS = Node->getOperand(0);
2007 SDValue RHS = Node->getOperand(1);
2010 // Expand the result by simply replacing it with the equivalent
2011 // non-overflow-checking operation.
2012 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2013 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2015 SplitInteger(Sum, Lo, Hi);
2017 // Compute the overflow.
2019 // LHSSign -> LHS >= 0
2020 // RHSSign -> RHS >= 0
2021 // SumSign -> Sum >= 0
2024 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2026 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2028 EVT OType = Node->getValueType(1);
2029 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2031 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2032 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2033 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2034 Node->getOpcode() == ISD::SADDO ?
2035 ISD::SETEQ : ISD::SETNE);
2037 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2038 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2040 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2042 // Use the calculated overflow everywhere.
2043 ReplaceValueWith(SDValue(Node, 1), Cmp);
2046 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2047 SDValue &Lo, SDValue &Hi) {
2048 EVT VT = N->getValueType(0);
2051 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2053 LC = RTLIB::SDIV_I16;
2054 else if (VT == MVT::i32)
2055 LC = RTLIB::SDIV_I32;
2056 else if (VT == MVT::i64)
2057 LC = RTLIB::SDIV_I64;
2058 else if (VT == MVT::i128)
2059 LC = RTLIB::SDIV_I128;
2060 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2062 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2063 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2066 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2067 SDValue &Lo, SDValue &Hi) {
2068 EVT VT = N->getValueType(0);
2071 // If we can emit an efficient shift operation, do so now. Check to see if
2072 // the RHS is a constant.
2073 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2074 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
2076 // If we can determine that the high bit of the shift is zero or one, even if
2077 // the low bits are variable, emit this shift in an optimized form.
2078 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2081 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2083 if (N->getOpcode() == ISD::SHL) {
2084 PartsOpc = ISD::SHL_PARTS;
2085 } else if (N->getOpcode() == ISD::SRL) {
2086 PartsOpc = ISD::SRL_PARTS;
2088 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2089 PartsOpc = ISD::SRA_PARTS;
2092 // Next check to see if the target supports this SHL_PARTS operation or if it
2093 // will custom expand it.
2094 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2095 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2096 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2097 Action == TargetLowering::Custom) {
2098 // Expand the subcomponents.
2100 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2101 EVT VT = LHSL.getValueType();
2103 // If the shift amount operand is coming from a vector legalization it may
2104 // have an illegal type. Fix that first by casting the operand, otherwise
2105 // the new SHL_PARTS operation would need further legalization.
2106 SDValue ShiftOp = N->getOperand(1);
2107 EVT ShiftTy = TLI.getShiftAmountTy(VT);
2108 assert(ShiftTy.getScalarType().getSizeInBits() >=
2109 Log2_32_Ceil(VT.getScalarType().getSizeInBits()) &&
2110 "ShiftAmountTy is too small to cover the range of this type!");
2111 if (ShiftOp.getValueType() != ShiftTy)
2112 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
2114 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
2115 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
2116 Hi = Lo.getValue(1);
2120 // Otherwise, emit a libcall.
2121 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2123 if (N->getOpcode() == ISD::SHL) {
2124 isSigned = false; /*sign irrelevant*/
2126 LC = RTLIB::SHL_I16;
2127 else if (VT == MVT::i32)
2128 LC = RTLIB::SHL_I32;
2129 else if (VT == MVT::i64)
2130 LC = RTLIB::SHL_I64;
2131 else if (VT == MVT::i128)
2132 LC = RTLIB::SHL_I128;
2133 } else if (N->getOpcode() == ISD::SRL) {
2136 LC = RTLIB::SRL_I16;
2137 else if (VT == MVT::i32)
2138 LC = RTLIB::SRL_I32;
2139 else if (VT == MVT::i64)
2140 LC = RTLIB::SRL_I64;
2141 else if (VT == MVT::i128)
2142 LC = RTLIB::SRL_I128;
2144 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2147 LC = RTLIB::SRA_I16;
2148 else if (VT == MVT::i32)
2149 LC = RTLIB::SRA_I32;
2150 else if (VT == MVT::i64)
2151 LC = RTLIB::SRA_I64;
2152 else if (VT == MVT::i128)
2153 LC = RTLIB::SRA_I128;
2156 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2157 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2158 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, isSigned, dl).first, Lo,
2163 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2164 llvm_unreachable("Unsupported shift!");
2167 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2168 SDValue &Lo, SDValue &Hi) {
2169 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2171 SDValue Op = N->getOperand(0);
2172 if (Op.getValueType().bitsLE(NVT)) {
2173 // The low part is sign extension of the input (degenerates to a copy).
2174 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2175 // The high part is obtained by SRA'ing all but one of the bits of low part.
2176 unsigned LoSize = NVT.getSizeInBits();
2177 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2178 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
2180 // For example, extension of an i48 to an i64. The operand type necessarily
2181 // promotes to the result type, so will end up being expanded too.
2182 assert(getTypeAction(Op.getValueType()) ==
2183 TargetLowering::TypePromoteInteger &&
2184 "Only know how to promote this result!");
2185 SDValue Res = GetPromotedInteger(Op);
2186 assert(Res.getValueType() == N->getValueType(0) &&
2187 "Operand over promoted?");
2188 // Split the promoted operand. This will simplify when it is expanded.
2189 SplitInteger(Res, Lo, Hi);
2190 unsigned ExcessBits =
2191 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2192 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2193 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2198 void DAGTypeLegalizer::
2199 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2201 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2202 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2204 if (EVT.bitsLE(Lo.getValueType())) {
2205 // sext_inreg the low part if needed.
2206 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2209 // The high part gets the sign extension from the lo-part. This handles
2210 // things like sextinreg V:i64 from i8.
2211 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2212 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
2213 TLI.getPointerTy()));
2215 // For example, extension of an i48 to an i64. Leave the low part alone,
2216 // sext_inreg the high part.
2217 unsigned ExcessBits =
2218 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2219 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2220 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2225 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2226 SDValue &Lo, SDValue &Hi) {
2227 EVT VT = N->getValueType(0);
2230 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2232 LC = RTLIB::SREM_I16;
2233 else if (VT == MVT::i32)
2234 LC = RTLIB::SREM_I32;
2235 else if (VT == MVT::i64)
2236 LC = RTLIB::SREM_I64;
2237 else if (VT == MVT::i128)
2238 LC = RTLIB::SREM_I128;
2239 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2241 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2242 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2245 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2246 SDValue &Lo, SDValue &Hi) {
2247 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2249 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2250 Hi = DAG.getNode(ISD::SRL, dl,
2251 N->getOperand(0).getValueType(), N->getOperand(0),
2252 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
2253 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2256 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2257 SDValue &Lo, SDValue &Hi) {
2258 SDValue LHS = N->getOperand(0);
2259 SDValue RHS = N->getOperand(1);
2262 // Expand the result by simply replacing it with the equivalent
2263 // non-overflow-checking operation.
2264 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2265 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2267 SplitInteger(Sum, Lo, Hi);
2269 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2270 // overflows iff a - b > a.
2271 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2272 N->getOpcode () == ISD::UADDO ?
2273 ISD::SETULT : ISD::SETUGT);
2275 // Use the calculated overflow everywhere.
2276 ReplaceValueWith(SDValue(N, 1), Ofl);
2279 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2280 SDValue &Lo, SDValue &Hi) {
2281 EVT VT = N->getValueType(0);
2284 // A divide for UMULO should be faster than a function call.
2285 if (N->getOpcode() == ISD::UMULO) {
2286 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2288 SDValue MUL = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS);
2289 SplitInteger(MUL, Lo, Hi);
2291 // A divide for UMULO will be faster than a function call. Select to
2292 // make sure we aren't using 0.
2293 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(VT),
2294 RHS, DAG.getConstant(0, VT), ISD::SETEQ);
2295 SDValue NotZero = DAG.getSelect(dl, VT, isZero,
2296 DAG.getConstant(1, VT), RHS);
2297 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero);
2298 SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS,
2300 Overflow = DAG.getSelect(dl, N->getValueType(1), isZero,
2301 DAG.getConstant(0, N->getValueType(1)),
2303 ReplaceValueWith(SDValue(N, 1), Overflow);
2307 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2308 EVT PtrVT = TLI.getPointerTy();
2309 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2311 // Replace this with a libcall that will check overflow.
2312 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2314 LC = RTLIB::MULO_I32;
2315 else if (VT == MVT::i64)
2316 LC = RTLIB::MULO_I64;
2317 else if (VT == MVT::i128)
2318 LC = RTLIB::MULO_I128;
2319 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2321 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2322 // Temporary for the overflow value, default it to zero.
2323 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2324 DAG.getConstant(0, PtrVT), Temp,
2325 MachinePointerInfo(), false, false, 0);
2327 TargetLowering::ArgListTy Args;
2328 TargetLowering::ArgListEntry Entry;
2329 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2330 EVT ArgVT = N->getOperand(i).getValueType();
2331 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2332 Entry.Node = N->getOperand(i);
2334 Entry.isSExt = true;
2335 Entry.isZExt = false;
2336 Args.push_back(Entry);
2339 // Also pass the address of the overflow check.
2341 Entry.Ty = PtrTy->getPointerTo();
2342 Entry.isSExt = true;
2343 Entry.isZExt = false;
2344 Args.push_back(Entry);
2346 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2348 TargetLowering::CallLoweringInfo CLI(DAG);
2349 CLI.setDebugLoc(dl).setChain(Chain)
2350 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args), 0)
2353 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2355 SplitInteger(CallInfo.first, Lo, Hi);
2356 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2357 MachinePointerInfo(), false, false, false, 0);
2358 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2359 DAG.getConstant(0, PtrVT),
2361 // Use the overflow from the libcall everywhere.
2362 ReplaceValueWith(SDValue(N, 1), Ofl);
2365 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2366 SDValue &Lo, SDValue &Hi) {
2367 EVT VT = N->getValueType(0);
2370 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2372 LC = RTLIB::UDIV_I16;
2373 else if (VT == MVT::i32)
2374 LC = RTLIB::UDIV_I32;
2375 else if (VT == MVT::i64)
2376 LC = RTLIB::UDIV_I64;
2377 else if (VT == MVT::i128)
2378 LC = RTLIB::UDIV_I128;
2379 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2381 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2382 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2385 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2386 SDValue &Lo, SDValue &Hi) {
2387 EVT VT = N->getValueType(0);
2390 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2392 LC = RTLIB::UREM_I16;
2393 else if (VT == MVT::i32)
2394 LC = RTLIB::UREM_I32;
2395 else if (VT == MVT::i64)
2396 LC = RTLIB::UREM_I64;
2397 else if (VT == MVT::i128)
2398 LC = RTLIB::UREM_I128;
2399 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2401 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2402 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2405 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2406 SDValue &Lo, SDValue &Hi) {
2407 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2409 SDValue Op = N->getOperand(0);
2410 if (Op.getValueType().bitsLE(NVT)) {
2411 // The low part is zero extension of the input (degenerates to a copy).
2412 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2413 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2415 // For example, extension of an i48 to an i64. The operand type necessarily
2416 // promotes to the result type, so will end up being expanded too.
2417 assert(getTypeAction(Op.getValueType()) ==
2418 TargetLowering::TypePromoteInteger &&
2419 "Only know how to promote this result!");
2420 SDValue Res = GetPromotedInteger(Op);
2421 assert(Res.getValueType() == N->getValueType(0) &&
2422 "Operand over promoted?");
2423 // Split the promoted operand. This will simplify when it is expanded.
2424 SplitInteger(Res, Lo, Hi);
2425 unsigned ExcessBits =
2426 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2427 Hi = DAG.getZeroExtendInReg(Hi, dl,
2428 EVT::getIntegerVT(*DAG.getContext(),
2433 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
2434 SDValue &Lo, SDValue &Hi) {
2436 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
2437 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
2438 SDValue Zero = DAG.getConstant(0, VT);
2439 SDValue Swap = DAG.getAtomicCmpSwap(
2440 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
2441 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
2442 N->getOperand(1), Zero, Zero, cast<AtomicSDNode>(N)->getMemOperand(),
2443 cast<AtomicSDNode>(N)->getOrdering(),
2444 cast<AtomicSDNode>(N)->getOrdering(),
2445 cast<AtomicSDNode>(N)->getSynchScope());
2447 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2448 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
2451 //===----------------------------------------------------------------------===//
2452 // Integer Operand Expansion
2453 //===----------------------------------------------------------------------===//
2455 /// ExpandIntegerOperand - This method is called when the specified operand of
2456 /// the specified node is found to need expansion. At this point, all of the
2457 /// result types of the node are known to be legal, but other operands of the
2458 /// node may need promotion or expansion as well as the specified one.
2459 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2460 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2461 SDValue Res = SDValue();
2463 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2466 switch (N->getOpcode()) {
2469 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2470 N->dump(&DAG); dbgs() << "\n";
2472 llvm_unreachable("Do not know how to expand this operator's operand!");
2474 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2475 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2476 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2477 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2478 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2479 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2480 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2481 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2482 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2483 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2484 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2485 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2491 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2492 case ISD::RETURNADDR:
2493 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2495 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2498 // If the result is null, the sub-method took care of registering results etc.
2499 if (!Res.getNode()) return false;
2501 // If the result is N, the sub-method updated N in place. Tell the legalizer
2503 if (Res.getNode() == N)
2506 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2507 "Invalid operand expansion");
2509 ReplaceValueWith(SDValue(N, 0), Res);
2513 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2514 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2515 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2517 ISD::CondCode &CCCode,
2519 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2520 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2521 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2523 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2524 if (RHSLo == RHSHi) {
2525 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2526 if (RHSCST->isAllOnesValue()) {
2527 // Equality comparison to -1.
2528 NewLHS = DAG.getNode(ISD::AND, dl,
2529 LHSLo.getValueType(), LHSLo, LHSHi);
2536 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2537 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2538 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2539 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2543 // If this is a comparison of the sign bit, just look at the top part.
2545 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2546 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2547 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2553 // FIXME: This generated code sucks.
2554 ISD::CondCode LowCC;
2556 default: llvm_unreachable("Unknown integer setcc!");
2558 case ISD::SETULT: LowCC = ISD::SETULT; break;
2560 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2562 case ISD::SETULE: LowCC = ISD::SETULE; break;
2564 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2567 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2568 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2569 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2571 // NOTE: on targets without efficient SELECT of bools, we can always use
2572 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2573 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
2576 if (TLI.isTypeLegal(LHSLo.getValueType()) &&
2577 TLI.isTypeLegal(RHSLo.getValueType()))
2578 Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()),
2579 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2580 if (!Tmp1.getNode())
2581 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
2582 LHSLo, RHSLo, LowCC);
2583 if (TLI.isTypeLegal(LHSHi.getValueType()) &&
2584 TLI.isTypeLegal(RHSHi.getValueType()))
2585 Tmp2 = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2586 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2587 if (!Tmp2.getNode())
2588 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2589 getSetCCResultType(LHSHi.getValueType()),
2590 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2592 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2593 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2594 if ((Tmp1C && Tmp1C->isNullValue()) ||
2595 (Tmp2C && Tmp2C->isNullValue() &&
2596 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2597 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2598 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2599 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2600 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2601 // low part is known false, returns high part.
2602 // For LE / GE, if high part is known false, ignore the low part.
2603 // For LT / GT, if high part is known true, ignore the low part.
2609 NewLHS = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2610 LHSHi, RHSHi, ISD::SETEQ, false,
2611 DagCombineInfo, dl);
2612 if (!NewLHS.getNode())
2613 NewLHS = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
2614 LHSHi, RHSHi, ISD::SETEQ);
2615 NewLHS = DAG.getSelect(dl, Tmp1.getValueType(),
2616 NewLHS, Tmp1, Tmp2);
2620 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2621 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2622 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2623 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2625 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2626 // against zero to select between true and false values.
2627 if (!NewRHS.getNode()) {
2628 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2629 CCCode = ISD::SETNE;
2632 // Update N to have the operands specified.
2633 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2634 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2635 N->getOperand(4)), 0);
2638 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2639 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2640 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2641 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2643 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2644 // against zero to select between true and false values.
2645 if (!NewRHS.getNode()) {
2646 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2647 CCCode = ISD::SETNE;
2650 // Update N to have the operands specified.
2651 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2652 N->getOperand(2), N->getOperand(3),
2653 DAG.getCondCode(CCCode)), 0);
2656 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2657 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2658 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2659 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2661 // If ExpandSetCCOperands returned a scalar, use it.
2662 if (!NewRHS.getNode()) {
2663 assert(NewLHS.getValueType() == N->getValueType(0) &&
2664 "Unexpected setcc expansion!");
2668 // Otherwise, update N to have the operands specified.
2669 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2670 DAG.getCondCode(CCCode)), 0);
2673 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2674 // The value being shifted is legal, but the shift amount is too big.
2675 // It follows that either the result of the shift is undefined, or the
2676 // upper half of the shift amount is zero. Just use the lower half.
2678 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2679 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2682 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2683 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2684 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2685 // constant to valid type.
2687 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2688 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2691 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2692 SDValue Op = N->getOperand(0);
2693 EVT DstVT = N->getValueType(0);
2694 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2695 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2696 "Don't know how to expand this SINT_TO_FP!");
2697 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, SDLoc(N)).first;
2700 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2701 if (ISD::isNormalStore(N))
2702 return ExpandOp_NormalStore(N, OpNo);
2704 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2705 assert(OpNo == 1 && "Can only expand the stored value so far");
2707 EVT VT = N->getOperand(1).getValueType();
2708 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2709 SDValue Ch = N->getChain();
2710 SDValue Ptr = N->getBasePtr();
2711 unsigned Alignment = N->getAlignment();
2712 bool isVolatile = N->isVolatile();
2713 bool isNonTemporal = N->isNonTemporal();
2714 AAMDNodes AAInfo = N->getAAInfo();
2718 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2720 if (N->getMemoryVT().bitsLE(NVT)) {
2721 GetExpandedInteger(N->getValue(), Lo, Hi);
2722 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2723 N->getMemoryVT(), isVolatile, isNonTemporal,
2727 if (TLI.isLittleEndian()) {
2728 // Little-endian - low bits are at low addresses.
2729 GetExpandedInteger(N->getValue(), Lo, Hi);
2731 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2732 isVolatile, isNonTemporal, Alignment, AAInfo);
2734 unsigned ExcessBits =
2735 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2736 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2738 // Increment the pointer to the other half.
2739 unsigned IncrementSize = NVT.getSizeInBits()/8;
2740 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2741 DAG.getConstant(IncrementSize, Ptr.getValueType()));
2742 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2743 N->getPointerInfo().getWithOffset(IncrementSize),
2744 NEVT, isVolatile, isNonTemporal,
2745 MinAlign(Alignment, IncrementSize), AAInfo);
2746 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2749 // Big-endian - high bits are at low addresses. Favor aligned stores at
2750 // the cost of some bit-fiddling.
2751 GetExpandedInteger(N->getValue(), Lo, Hi);
2753 EVT ExtVT = N->getMemoryVT();
2754 unsigned EBytes = ExtVT.getStoreSize();
2755 unsigned IncrementSize = NVT.getSizeInBits()/8;
2756 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2757 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2758 ExtVT.getSizeInBits() - ExcessBits);
2760 if (ExcessBits < NVT.getSizeInBits()) {
2761 // Transfer high bits from the top of Lo to the bottom of Hi.
2762 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2763 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2764 TLI.getPointerTy()));
2765 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2766 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2767 DAG.getConstant(ExcessBits,
2768 TLI.getPointerTy())));
2771 // Store both the high bits and maybe some of the low bits.
2772 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2773 HiVT, isVolatile, isNonTemporal, Alignment, AAInfo);
2775 // Increment the pointer to the other half.
2776 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2777 DAG.getConstant(IncrementSize, Ptr.getValueType()));
2778 // Store the lowest ExcessBits bits in the second half.
2779 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2780 N->getPointerInfo().getWithOffset(IncrementSize),
2781 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2782 isVolatile, isNonTemporal,
2783 MinAlign(Alignment, IncrementSize), AAInfo);
2784 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2787 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2789 GetExpandedInteger(N->getOperand(0), InL, InH);
2790 // Just truncate the low part of the source.
2791 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
2794 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2795 SDValue Op = N->getOperand(0);
2796 EVT SrcVT = Op.getValueType();
2797 EVT DstVT = N->getValueType(0);
2800 // The following optimization is valid only if every value in SrcVT (when
2801 // treated as signed) is representable in DstVT. Check that the mantissa
2802 // size of DstVT is >= than the number of bits in SrcVT -1.
2803 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT);
2804 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
2805 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2806 // Do a signed conversion then adjust the result.
2807 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2808 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2810 // The result of the signed conversion needs adjusting if the 'sign bit' of
2811 // the incoming integer was set. To handle this, we dynamically test to see
2812 // if it is set, and, if so, add a fudge factor.
2814 const uint64_t F32TwoE32 = 0x4F800000ULL;
2815 const uint64_t F32TwoE64 = 0x5F800000ULL;
2816 const uint64_t F32TwoE128 = 0x7F800000ULL;
2819 if (SrcVT == MVT::i32)
2820 FF = APInt(32, F32TwoE32);
2821 else if (SrcVT == MVT::i64)
2822 FF = APInt(32, F32TwoE64);
2823 else if (SrcVT == MVT::i128)
2824 FF = APInt(32, F32TwoE128);
2826 llvm_unreachable("Unsupported UINT_TO_FP!");
2828 // Check whether the sign bit is set.
2830 GetExpandedInteger(Op, Lo, Hi);
2831 SDValue SignSet = DAG.getSetCC(dl,
2832 getSetCCResultType(Hi.getValueType()),
2833 Hi, DAG.getConstant(0, Hi.getValueType()),
2836 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2837 SDValue FudgePtr = DAG.getConstantPool(
2838 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2839 TLI.getPointerTy());
2841 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2842 SDValue Zero = DAG.getIntPtrConstant(0);
2843 SDValue Four = DAG.getIntPtrConstant(4);
2844 if (TLI.isBigEndian()) std::swap(Zero, Four);
2845 SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
2847 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2848 FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
2850 Alignment = std::min(Alignment, 4u);
2852 // Load the value out, extending it from f32 to the destination float type.
2853 // FIXME: Avoid the extend by constructing the right constant pool?
2854 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2856 MachinePointerInfo::getConstantPool(),
2858 false, false, false, Alignment);
2859 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2862 // Otherwise, use a libcall.
2863 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2864 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2865 "Don't know how to expand this UINT_TO_FP!");
2866 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, dl).first;
2869 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
2871 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2872 cast<AtomicSDNode>(N)->getMemoryVT(),
2874 N->getOperand(1), N->getOperand(2),
2875 cast<AtomicSDNode>(N)->getMemOperand(),
2876 cast<AtomicSDNode>(N)->getOrdering(),
2877 cast<AtomicSDNode>(N)->getSynchScope());
2878 return Swap.getValue(1);
2882 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
2883 SDValue InOp0 = N->getOperand(0);
2884 EVT InVT = InOp0.getValueType();
2886 EVT OutVT = N->getValueType(0);
2887 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2888 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2889 unsigned OutNumElems = OutVT.getVectorNumElements();
2890 EVT NOutVTElem = NOutVT.getVectorElementType();
2893 SDValue BaseIdx = N->getOperand(1);
2895 SmallVector<SDValue, 8> Ops;
2896 Ops.reserve(OutNumElems);
2897 for (unsigned i = 0; i != OutNumElems; ++i) {
2899 // Extract the element from the original vector.
2900 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
2901 BaseIdx, DAG.getConstant(i, BaseIdx.getValueType()));
2902 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2903 InVT.getVectorElementType(), N->getOperand(0), Index);
2905 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
2906 // Insert the converted element to the new vector.
2910 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
2914 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
2915 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
2916 EVT VT = N->getValueType(0);
2919 unsigned NumElts = VT.getVectorNumElements();
2920 SmallVector<int, 8> NewMask;
2921 for (unsigned i = 0; i != NumElts; ++i) {
2922 NewMask.push_back(SV->getMaskElt(i));
2925 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2926 SDValue V1 = GetPromotedInteger(N->getOperand(1));
2927 EVT OutVT = V0.getValueType();
2929 return DAG.getVectorShuffle(OutVT, dl, V0, V1, &NewMask[0]);
2933 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
2934 EVT OutVT = N->getValueType(0);
2935 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2936 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2937 unsigned NumElems = N->getNumOperands();
2938 EVT NOutVTElem = NOutVT.getVectorElementType();
2942 SmallVector<SDValue, 8> Ops;
2943 Ops.reserve(NumElems);
2944 for (unsigned i = 0; i != NumElems; ++i) {
2946 // BUILD_VECTOR integer operand types are allowed to be larger than the
2947 // result's element type. This may still be true after the promotion. For
2948 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
2949 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
2950 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
2951 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
2953 Op = N->getOperand(i);
2957 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
2960 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
2964 assert(!N->getOperand(0).getValueType().isVector() &&
2965 "Input must be a scalar");
2967 EVT OutVT = N->getValueType(0);
2968 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2969 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2970 EVT NOutVTElem = NOutVT.getVectorElementType();
2972 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
2974 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
2977 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
2980 EVT OutVT = N->getValueType(0);
2981 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2982 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2984 EVT InElemTy = OutVT.getVectorElementType();
2985 EVT OutElemTy = NOutVT.getVectorElementType();
2987 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
2988 unsigned NumOutElem = NOutVT.getVectorNumElements();
2989 unsigned NumOperands = N->getNumOperands();
2990 assert(NumElem * NumOperands == NumOutElem &&
2991 "Unexpected number of elements");
2993 // Take the elements from the first vector.
2994 SmallVector<SDValue, 8> Ops(NumOutElem);
2995 for (unsigned i = 0; i < NumOperands; ++i) {
2996 SDValue Op = N->getOperand(i);
2997 for (unsigned j = 0; j < NumElem; ++j) {
2998 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2999 InElemTy, Op, DAG.getConstant(j,
3000 TLI.getVectorIdxTy()));
3001 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
3005 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3008 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
3009 EVT OutVT = N->getValueType(0);
3010 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3011 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3013 EVT NOutVTElem = NOutVT.getVectorElementType();
3016 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3018 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
3019 NOutVTElem, N->getOperand(1));
3020 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
3021 V0, ConvElem, N->getOperand(2));
3024 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3026 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3027 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl, TLI.getVectorIdxTy());
3028 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3029 V0->getValueType(0).getScalarType(), V0, V1);
3031 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
3032 // element types. If this is the case then we need to expand the outgoing
3033 // value and not truncate it.
3034 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
3037 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
3039 unsigned NumElems = N->getNumOperands();
3041 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
3043 SmallVector<SDValue, 8> NewOps;
3044 NewOps.reserve(NumElems);
3046 // For each incoming vector
3047 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3048 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
3049 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
3050 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
3052 for (unsigned i=0; i<NumElem; ++i) {
3053 // Extract element from incoming vector
3054 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy,
3055 Incoming, DAG.getConstant(i, TLI.getVectorIdxTy()));
3056 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3057 NewOps.push_back(Tr);
3061 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), NewOps);