1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 //===----------------------------------------------------------------------===//
28 // Integer Result Promotion
29 //===----------------------------------------------------------------------===//
31 /// PromoteIntegerResult - This method is called when a result of a node is
32 /// found to be in need of promotion to a larger type. At this point, the node
33 /// may also have invalid operands or may have other results that need
34 /// expansion, we just know that (at least) one result needs promotion.
35 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
37 SDValue Res = SDValue();
39 // See if the target wants to custom expand this node.
40 if (CustomLowerNode(N, N->getValueType(ResNo), true))
43 switch (N->getOpcode()) {
46 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
47 N->dump(&DAG); dbgs() << "\n";
49 llvm_unreachable("Do not know how to promote this operator!");
50 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
51 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
52 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break;
53 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
54 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
55 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
56 case ISD::CONVERT_RNDSAT:
57 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
58 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
59 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
60 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
61 case ISD::EXTRACT_VECTOR_ELT:
62 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
63 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
64 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
65 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
66 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
67 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
68 case ISD::SIGN_EXTEND_INREG:
69 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
70 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
71 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
72 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
73 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
74 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
76 case ISD::SIGN_EXTEND:
77 case ISD::ZERO_EXTEND:
78 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
81 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
83 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break;
90 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
93 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
96 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
99 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
101 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
103 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
105 case ISD::ATOMIC_LOAD_ADD:
106 case ISD::ATOMIC_LOAD_SUB:
107 case ISD::ATOMIC_LOAD_AND:
108 case ISD::ATOMIC_LOAD_OR:
109 case ISD::ATOMIC_LOAD_XOR:
110 case ISD::ATOMIC_LOAD_NAND:
111 case ISD::ATOMIC_LOAD_MIN:
112 case ISD::ATOMIC_LOAD_MAX:
113 case ISD::ATOMIC_LOAD_UMIN:
114 case ISD::ATOMIC_LOAD_UMAX:
115 case ISD::ATOMIC_SWAP:
116 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
118 case ISD::ATOMIC_CMP_SWAP:
119 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
122 // If the result is null then the sub-method took care of registering it.
124 SetPromotedInteger(SDValue(N, ResNo), Res);
127 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
128 // Sign-extend the new bits, and continue the assertion.
129 SDValue Op = SExtPromotedInteger(N->getOperand(0));
130 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
131 Op.getValueType(), Op, N->getOperand(1));
134 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
135 // Zero the new bits, and continue the assertion.
136 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
137 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
138 Op.getValueType(), Op, N->getOperand(1));
141 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
142 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
143 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
145 N->getChain(), N->getBasePtr(),
146 Op2, N->getSrcValue(), N->getAlignment());
147 // Legalized the chain result - switch anything that used the old chain to
149 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
153 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
154 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
155 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
156 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
157 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
158 Op2, Op3, N->getSrcValue(), N->getAlignment());
159 // Legalized the chain result - switch anything that used the old chain to
161 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
165 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
166 SDValue InOp = N->getOperand(0);
167 EVT InVT = InOp.getValueType();
168 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
169 EVT OutVT = N->getValueType(0);
170 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
171 DebugLoc dl = N->getDebugLoc();
173 switch (getTypeAction(InVT)) {
175 assert(false && "Unknown type action!");
180 if (NOutVT.bitsEq(NInVT))
181 // The input promotes to the same size. Convert the promoted value.
182 return DAG.getNode(ISD::BIT_CONVERT, dl,
183 NOutVT, GetPromotedInteger(InOp));
186 // Promote the integer operand by hand.
187 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
191 case ScalarizeVector:
192 // Convert the element to an integer and promote it by hand.
193 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
194 BitConvertToInteger(GetScalarizedVector(InOp)));
196 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
197 // pieces of the input into integers and reassemble in the final type.
199 GetSplitVector(N->getOperand(0), Lo, Hi);
200 Lo = BitConvertToInteger(Lo);
201 Hi = BitConvertToInteger(Hi);
203 if (TLI.isBigEndian())
206 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
207 EVT::getIntegerVT(*DAG.getContext(),
208 NOutVT.getSizeInBits()),
209 JoinIntegers(Lo, Hi));
210 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp);
213 if (OutVT.bitsEq(NInVT))
214 // The input is widened to the same size. Convert to the widened value.
215 return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp));
218 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
219 CreateStackStoreLoad(InOp, OutVT));
222 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
223 SDValue Op = GetPromotedInteger(N->getOperand(0));
224 EVT OVT = N->getValueType(0);
225 EVT NVT = Op.getValueType();
226 DebugLoc dl = N->getDebugLoc();
228 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
229 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
230 DAG.getConstant(DiffBits, TLI.getPointerTy()));
233 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
234 // The pair element type may be legal, or may not promote to the same type as
235 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
236 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
237 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
238 JoinIntegers(N->getOperand(0), N->getOperand(1)));
241 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
242 EVT VT = N->getValueType(0);
243 // FIXME there is no actual debug info here
244 DebugLoc dl = N->getDebugLoc();
245 // Zero extend things like i1, sign extend everything else. It shouldn't
246 // matter in theory which one we pick, but this tends to give better code?
247 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
248 SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(*DAG.getContext(), VT),
250 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
254 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
255 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
256 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
257 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
258 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
259 "can only promote integers");
260 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
261 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
262 N->getOperand(1), N->getOperand(2),
263 N->getOperand(3), N->getOperand(4), CvtCode);
266 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
267 // Zero extend to the promoted type and do the count there.
268 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
269 DebugLoc dl = N->getDebugLoc();
270 EVT OVT = N->getValueType(0);
271 EVT NVT = Op.getValueType();
272 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
273 // Subtract off the extra leading bits in the bigger type.
274 return DAG.getNode(ISD::SUB, dl, NVT, Op,
275 DAG.getConstant(NVT.getSizeInBits() -
276 OVT.getSizeInBits(), NVT));
279 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
280 // Zero extend to the promoted type and do the count there.
281 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
282 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
285 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
286 SDValue Op = GetPromotedInteger(N->getOperand(0));
287 EVT OVT = N->getValueType(0);
288 EVT NVT = Op.getValueType();
289 DebugLoc dl = N->getDebugLoc();
290 // The count is the same in the promoted type except if the original
291 // value was zero. This can be handled by setting the bit just off
292 // the top of the original type.
293 APInt TopBit(NVT.getSizeInBits(), 0);
294 TopBit.set(OVT.getSizeInBits());
295 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
296 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
299 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
300 DebugLoc dl = N->getDebugLoc();
301 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
302 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
306 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
307 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
308 unsigned NewOpc = N->getOpcode();
309 DebugLoc dl = N->getDebugLoc();
311 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
312 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
313 // and SINT conversions are Custom, there is no way to tell which is preferable.
314 // We choose SINT because that's the right thing on PPC.)
315 if (N->getOpcode() == ISD::FP_TO_UINT &&
316 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
317 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
318 NewOpc = ISD::FP_TO_SINT;
320 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
322 // Assert that the converted value fits in the original type. If it doesn't
323 // (eg: because the value being converted is too big), then the result of the
324 // original operation was undefined anyway, so the assert is still correct.
325 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
326 ISD::AssertZext : ISD::AssertSext, dl,
327 NVT, Res, DAG.getValueType(N->getValueType(0)));
330 SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) {
331 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
332 DebugLoc dl = N->getDebugLoc();
334 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
336 return DAG.getNode(ISD::AssertZext, dl,
337 NVT, Res, DAG.getValueType(N->getValueType(0)));
340 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
341 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
342 DebugLoc dl = N->getDebugLoc();
344 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
345 SDValue Res = GetPromotedInteger(N->getOperand(0));
346 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
348 // If the result and operand types are the same after promotion, simplify
349 // to an in-register extension.
350 if (NVT == Res.getValueType()) {
351 // The high bits are not guaranteed to be anything. Insert an extend.
352 if (N->getOpcode() == ISD::SIGN_EXTEND)
353 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
354 DAG.getValueType(N->getOperand(0).getValueType()));
355 if (N->getOpcode() == ISD::ZERO_EXTEND)
356 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
357 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
362 // Otherwise, just extend the original operand all the way to the larger type.
363 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
366 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
367 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
368 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
369 ISD::LoadExtType ExtType =
370 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
371 DebugLoc dl = N->getDebugLoc();
372 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
373 N->getSrcValue(), N->getSrcValueOffset(),
374 N->getMemoryVT(), N->isVolatile(),
375 N->isNonTemporal(), N->getAlignment());
377 // Legalized the chain result - switch anything that used the old chain to
379 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
383 /// Promote the overflow flag of an overflowing arithmetic node.
384 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
385 // Simply change the return type of the boolean result.
386 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
387 EVT ValueVTs[] = { N->getValueType(0), NVT };
388 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
389 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
390 DAG.getVTList(ValueVTs, 2), Ops, 2);
392 // Modified the sum result - switch anything that used the old sum to use
394 ReplaceValueWith(SDValue(N, 0), Res);
396 return SDValue(Res.getNode(), 1);
399 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
401 return PromoteIntRes_Overflow(N);
403 // The operation overflowed iff the result in the larger type is not the
404 // sign extension of its truncation to the original type.
405 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
406 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
407 EVT OVT = N->getOperand(0).getValueType();
408 EVT NVT = LHS.getValueType();
409 DebugLoc dl = N->getDebugLoc();
411 // Do the arithmetic in the larger type.
412 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
413 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
415 // Calculate the overflow flag: sign extend the arithmetic result from
416 // the original type.
417 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
418 DAG.getValueType(OVT));
419 // Overflowed if and only if this is not equal to Res.
420 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
422 // Use the calculated overflow everywhere.
423 ReplaceValueWith(SDValue(N, 1), Ofl);
428 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
429 // Sign extend the input.
430 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
431 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
432 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
433 LHS.getValueType(), LHS, RHS);
436 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
437 SDValue LHS = GetPromotedInteger(N->getOperand(1));
438 SDValue RHS = GetPromotedInteger(N->getOperand(2));
439 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
440 LHS.getValueType(), N->getOperand(0),LHS,RHS);
443 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
444 SDValue LHS = GetPromotedInteger(N->getOperand(2));
445 SDValue RHS = GetPromotedInteger(N->getOperand(3));
446 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
447 LHS.getValueType(), N->getOperand(0),
448 N->getOperand(1), LHS, RHS, N->getOperand(4));
451 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
452 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
453 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
454 DebugLoc dl = N->getDebugLoc();
456 // Get the SETCC result using the canonical SETCC type.
457 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
458 N->getOperand(1), N->getOperand(2));
460 // Convert to the expected type.
461 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
462 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
463 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
466 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
467 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
468 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
469 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
472 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
473 SDValue Op = GetPromotedInteger(N->getOperand(0));
474 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
475 Op.getValueType(), Op, N->getOperand(1));
478 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
479 // The input may have strange things in the top bits of the registers, but
480 // these operations don't care. They may have weird bits going out, but
481 // that too is okay if they are integer operations.
482 SDValue LHS = GetPromotedInteger(N->getOperand(0));
483 SDValue RHS = GetPromotedInteger(N->getOperand(1));
484 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
485 LHS.getValueType(), LHS, RHS);
488 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
489 // The input value must be properly sign extended.
490 SDValue Res = SExtPromotedInteger(N->getOperand(0));
491 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
492 Res.getValueType(), Res, N->getOperand(1));
495 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
496 // The input value must be properly zero extended.
497 EVT VT = N->getValueType(0);
498 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
499 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
500 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
503 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
504 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
507 switch (getTypeAction(N->getOperand(0).getValueType())) {
508 default: llvm_unreachable("Unknown type action!");
511 Res = N->getOperand(0);
514 Res = GetPromotedInteger(N->getOperand(0));
518 // Truncate to NVT instead of VT
519 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
522 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
524 return PromoteIntRes_Overflow(N);
526 // The operation overflowed iff the result in the larger type is not the
527 // zero extension of its truncation to the original type.
528 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
529 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
530 EVT OVT = N->getOperand(0).getValueType();
531 EVT NVT = LHS.getValueType();
532 DebugLoc dl = N->getDebugLoc();
534 // Do the arithmetic in the larger type.
535 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
536 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
538 // Calculate the overflow flag: zero extend the arithmetic result from
539 // the original type.
540 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
541 // Overflowed if and only if this is not equal to Res.
542 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
544 // Use the calculated overflow everywhere.
545 ReplaceValueWith(SDValue(N, 1), Ofl);
550 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
551 // Zero extend the input.
552 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
553 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
554 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
555 LHS.getValueType(), LHS, RHS);
558 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
559 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)));
562 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
563 SDValue Chain = N->getOperand(0); // Get the chain.
564 SDValue Ptr = N->getOperand(1); // Get the pointer.
565 EVT VT = N->getValueType(0);
566 DebugLoc dl = N->getDebugLoc();
568 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
569 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
570 // The argument is passed as NumRegs registers of type RegVT.
572 SmallVector<SDValue, 8> Parts(NumRegs);
573 for (unsigned i = 0; i < NumRegs; ++i) {
574 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2));
575 Chain = Parts[i].getValue(1);
578 // Handle endianness of the load.
579 if (TLI.isBigEndian())
580 std::reverse(Parts.begin(), Parts.end());
582 // Assemble the parts in the promoted type.
583 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
584 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
585 for (unsigned i = 1; i < NumRegs; ++i) {
586 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
587 // Shift it to the right position and "or" it in.
588 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
589 DAG.getConstant(i * RegVT.getSizeInBits(),
590 TLI.getPointerTy()));
591 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
594 // Modified the chain result - switch anything that used the old chain to
596 ReplaceValueWith(SDValue(N, 1), Chain);
601 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
602 assert(ResNo == 1 && "Only boolean result promotion currently supported!");
603 return PromoteIntRes_Overflow(N);
606 //===----------------------------------------------------------------------===//
607 // Integer Operand Promotion
608 //===----------------------------------------------------------------------===//
610 /// PromoteIntegerOperand - This method is called when the specified operand of
611 /// the specified node is found to need promotion. At this point, all of the
612 /// result types of the node are known to be legal, but other operands of the
613 /// node may need promotion or expansion as well as the specified one.
614 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
615 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
616 SDValue Res = SDValue();
618 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
621 switch (N->getOpcode()) {
624 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
625 N->dump(&DAG); dbgs() << "\n";
627 llvm_unreachable("Do not know how to promote this operator's operand!");
629 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
630 case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break;
631 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
632 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
633 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
634 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
635 case ISD::CONVERT_RNDSAT:
636 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
637 case ISD::INSERT_VECTOR_ELT:
638 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
639 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
640 case ISD::SCALAR_TO_VECTOR:
641 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
642 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
643 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
644 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
645 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
646 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
647 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
649 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
650 case ISD::FP16_TO_FP32:
651 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
652 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
658 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
661 // If the result is null, the sub-method took care of registering results etc.
662 if (!Res.getNode()) return false;
664 // If the result is N, the sub-method updated N in place. Tell the legalizer
666 if (Res.getNode() == N)
669 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
670 "Invalid operand expansion");
672 ReplaceValueWith(SDValue(N, 0), Res);
676 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
677 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
678 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
679 ISD::CondCode CCCode) {
680 // We have to insert explicit sign or zero extends. Note that we could
681 // insert sign extends for ALL conditions, but zero extend is cheaper on
682 // many machines (an AND instead of two shifts), so prefer it.
684 default: llvm_unreachable("Unknown integer comparison!");
691 // ALL of these operations will work if we either sign or zero extend
692 // the operands (including the unsigned comparisons!). Zero extend is
693 // usually a simpler/cheaper operation, so prefer it.
694 NewLHS = ZExtPromotedInteger(NewLHS);
695 NewRHS = ZExtPromotedInteger(NewRHS);
701 NewLHS = SExtPromotedInteger(NewLHS);
702 NewRHS = SExtPromotedInteger(NewRHS);
707 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
708 SDValue Op = GetPromotedInteger(N->getOperand(0));
709 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
712 SDValue DAGTypeLegalizer::PromoteIntOp_BIT_CONVERT(SDNode *N) {
713 // This should only occur in unusual situations like bitcasting to an
714 // x86_fp80, so just turn it into a store+load
715 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
718 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
719 assert(OpNo == 2 && "Don't know how to promote this operand!");
721 SDValue LHS = N->getOperand(2);
722 SDValue RHS = N->getOperand(3);
723 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
725 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
727 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
728 N->getOperand(1), LHS, RHS, N->getOperand(4));
731 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
732 assert(OpNo == 1 && "only know how to promote condition");
734 // Promote all the way up to the canonical SetCC type.
735 EVT SVT = TLI.getSetCCResultType(MVT::Other);
736 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
738 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
739 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
743 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
744 // Since the result type is legal, the operands must promote to it.
745 EVT OVT = N->getOperand(0).getValueType();
746 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
747 SDValue Hi = GetPromotedInteger(N->getOperand(1));
748 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
749 DebugLoc dl = N->getDebugLoc();
751 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
752 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
753 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
756 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
757 // The vector type is legal but the element type is not. This implies
758 // that the vector is a power-of-two in length and that the element
759 // type does not have a strange size (eg: it is not i1).
760 EVT VecVT = N->getValueType(0);
761 unsigned NumElts = VecVT.getVectorNumElements();
762 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
764 // Promote the inserted value. The type does not need to match the
765 // vector element type. Check that any extra bits introduced will be
767 assert(N->getOperand(0).getValueType().getSizeInBits() >=
768 N->getValueType(0).getVectorElementType().getSizeInBits() &&
769 "Type of inserted value narrower than vector element type!");
771 SmallVector<SDValue, 16> NewOps;
772 for (unsigned i = 0; i < NumElts; ++i)
773 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
775 return DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0], NumElts);
778 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
779 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
780 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
781 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
782 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
783 "can only promote integer arguments");
784 SDValue InOp = GetPromotedInteger(N->getOperand(0));
785 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
786 N->getOperand(1), N->getOperand(2),
787 N->getOperand(3), N->getOperand(4), CvtCode);
790 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
793 // Promote the inserted value. This is valid because the type does not
794 // have to match the vector element type.
796 // Check that any extra bits introduced will be truncated away.
797 assert(N->getOperand(1).getValueType().getSizeInBits() >=
798 N->getValueType(0).getVectorElementType().getSizeInBits() &&
799 "Type of inserted value narrower than vector element type!");
800 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
801 GetPromotedInteger(N->getOperand(1)),
805 assert(OpNo == 2 && "Different operand and result vector types?");
807 // Promote the index.
808 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
809 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
810 N->getOperand(1), Idx);
813 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
815 DebugLoc dl = N->getDebugLoc();
816 NewOps[0] = N->getOperand(0);
817 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
818 SDValue Flag = GetPromotedInteger(N->getOperand(i));
819 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
821 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
822 array_lengthof(NewOps));
825 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
826 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
827 // the operand in place.
828 return DAG.UpdateNodeOperands(SDValue(N, 0),
829 GetPromotedInteger(N->getOperand(0)));
832 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
833 assert(OpNo == 0 && "Only know how to promote condition");
835 // Promote all the way up to the canonical SetCC type.
836 EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
837 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
839 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
840 N->getOperand(1), N->getOperand(2));
843 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
844 assert(OpNo == 0 && "Don't know how to promote this operand!");
846 SDValue LHS = N->getOperand(0);
847 SDValue RHS = N->getOperand(1);
848 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
850 // The CC (#4) and the possible return values (#2 and #3) have legal types.
851 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
852 N->getOperand(3), N->getOperand(4));
855 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
856 assert(OpNo == 0 && "Don't know how to promote this operand!");
858 SDValue LHS = N->getOperand(0);
859 SDValue RHS = N->getOperand(1);
860 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
862 // The CC (#2) is always legal.
863 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
866 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
867 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
868 ZExtPromotedInteger(N->getOperand(1)));
871 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
872 SDValue Op = GetPromotedInteger(N->getOperand(0));
873 DebugLoc dl = N->getDebugLoc();
874 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
875 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
876 Op, DAG.getValueType(N->getOperand(0).getValueType()));
879 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
880 return DAG.UpdateNodeOperands(SDValue(N, 0),
881 SExtPromotedInteger(N->getOperand(0)));
884 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
885 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
886 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
887 int SVOffset = N->getSrcValueOffset();
888 unsigned Alignment = N->getAlignment();
889 bool isVolatile = N->isVolatile();
890 bool isNonTemporal = N->isNonTemporal();
891 DebugLoc dl = N->getDebugLoc();
893 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
895 // Truncate the value and store the result.
896 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(),
897 SVOffset, N->getMemoryVT(),
898 isVolatile, isNonTemporal, Alignment);
901 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
902 SDValue Op = GetPromotedInteger(N->getOperand(0));
903 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
906 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
907 return DAG.UpdateNodeOperands(SDValue(N, 0),
908 ZExtPromotedInteger(N->getOperand(0)));
911 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
912 DebugLoc dl = N->getDebugLoc();
913 SDValue Op = GetPromotedInteger(N->getOperand(0));
914 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
915 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
919 //===----------------------------------------------------------------------===//
920 // Integer Result Expansion
921 //===----------------------------------------------------------------------===//
923 /// ExpandIntegerResult - This method is called when the specified result of the
924 /// specified node is found to need expansion. At this point, the node may also
925 /// have invalid operands or may have other results that need promotion, we just
926 /// know that (at least) one result needs expansion.
927 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
928 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
932 // See if the target wants to custom expand this node.
933 if (CustomLowerNode(N, N->getValueType(ResNo), true))
936 switch (N->getOpcode()) {
939 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
940 N->dump(&DAG); dbgs() << "\n";
942 llvm_unreachable("Do not know how to expand the result of this operator!");
944 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
945 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
946 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
947 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
949 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
950 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
951 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
952 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
953 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
955 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
956 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
957 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
958 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
959 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
960 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
961 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
962 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
963 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
964 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
965 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
966 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
967 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
968 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
969 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
970 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
971 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
972 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
973 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
974 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
978 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
981 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
984 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
987 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
991 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
994 // If Lo/Hi is null, the sub-method took care of registering results etc.
996 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
999 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1000 /// and the shift amount is a constant 'Amt'. Expand the operation.
1001 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1002 SDValue &Lo, SDValue &Hi) {
1003 DebugLoc dl = N->getDebugLoc();
1004 // Expand the incoming operand to be shifted, so that we have its parts
1006 GetExpandedInteger(N->getOperand(0), InL, InH);
1008 EVT NVT = InL.getValueType();
1009 unsigned VTBits = N->getValueType(0).getSizeInBits();
1010 unsigned NVTBits = NVT.getSizeInBits();
1011 EVT ShTy = N->getOperand(1).getValueType();
1013 if (N->getOpcode() == ISD::SHL) {
1015 Lo = Hi = DAG.getConstant(0, NVT);
1016 } else if (Amt > NVTBits) {
1017 Lo = DAG.getConstant(0, NVT);
1018 Hi = DAG.getNode(ISD::SHL, dl,
1019 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1020 } else if (Amt == NVTBits) {
1021 Lo = DAG.getConstant(0, NVT);
1023 } else if (Amt == 1 &&
1024 TLI.isOperationLegalOrCustom(ISD::ADDC,
1025 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1026 // Emit this X << 1 as X+X.
1027 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1028 SDValue LoOps[2] = { InL, InL };
1029 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1030 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1031 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1033 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy));
1034 Hi = DAG.getNode(ISD::OR, dl, NVT,
1035 DAG.getNode(ISD::SHL, dl, NVT, InH,
1036 DAG.getConstant(Amt, ShTy)),
1037 DAG.getNode(ISD::SRL, dl, NVT, InL,
1038 DAG.getConstant(NVTBits-Amt, ShTy)));
1043 if (N->getOpcode() == ISD::SRL) {
1045 Lo = DAG.getConstant(0, NVT);
1046 Hi = DAG.getConstant(0, NVT);
1047 } else if (Amt > NVTBits) {
1048 Lo = DAG.getNode(ISD::SRL, dl,
1049 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1050 Hi = DAG.getConstant(0, NVT);
1051 } else if (Amt == NVTBits) {
1053 Hi = DAG.getConstant(0, NVT);
1055 Lo = DAG.getNode(ISD::OR, dl, NVT,
1056 DAG.getNode(ISD::SRL, dl, NVT, InL,
1057 DAG.getConstant(Amt, ShTy)),
1058 DAG.getNode(ISD::SHL, dl, NVT, InH,
1059 DAG.getConstant(NVTBits-Amt, ShTy)));
1060 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1065 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1067 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1068 DAG.getConstant(NVTBits-1, ShTy));
1069 } else if (Amt > NVTBits) {
1070 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1071 DAG.getConstant(Amt-NVTBits, ShTy));
1072 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1073 DAG.getConstant(NVTBits-1, ShTy));
1074 } else if (Amt == NVTBits) {
1076 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1077 DAG.getConstant(NVTBits-1, ShTy));
1079 Lo = DAG.getNode(ISD::OR, dl, NVT,
1080 DAG.getNode(ISD::SRL, dl, NVT, InL,
1081 DAG.getConstant(Amt, ShTy)),
1082 DAG.getNode(ISD::SHL, dl, NVT, InH,
1083 DAG.getConstant(NVTBits-Amt, ShTy)));
1084 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1088 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1089 /// this shift based on knowledge of the high bit of the shift amount. If we
1090 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1092 bool DAGTypeLegalizer::
1093 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1094 SDValue Amt = N->getOperand(1);
1095 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1096 EVT ShTy = Amt.getValueType();
1097 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1098 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1099 assert(isPowerOf2_32(NVTBits) &&
1100 "Expanded integer type size not a power of two!");
1101 DebugLoc dl = N->getDebugLoc();
1103 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1104 APInt KnownZero, KnownOne;
1105 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1107 // If we don't know anything about the high bits, exit.
1108 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1111 // Get the incoming operand to be shifted.
1113 GetExpandedInteger(N->getOperand(0), InL, InH);
1115 // If we know that any of the high bits of the shift amount are one, then we
1116 // can do this as a couple of simple shifts.
1117 if (KnownOne.intersects(HighBitMask)) {
1118 // Mask out the high bit, which we know is set.
1119 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1120 DAG.getConstant(~HighBitMask, ShTy));
1122 switch (N->getOpcode()) {
1123 default: llvm_unreachable("Unknown shift");
1125 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1126 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1129 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1130 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1133 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1134 DAG.getConstant(NVTBits-1, ShTy));
1135 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1141 // FIXME: This code is broken for shifts with a zero amount!
1142 // If we know that all of the high bits of the shift amount are zero, then we
1143 // can do this as a couple of simple shifts.
1144 if ((KnownZero & HighBitMask) == HighBitMask) {
1146 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1147 DAG.getConstant(NVTBits, ShTy),
1150 switch (N->getOpcode()) {
1151 default: llvm_unreachable("Unknown shift");
1152 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1154 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1157 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1158 Hi = DAG.getNode(ISD::OR, NVT,
1159 DAG.getNode(Op1, NVT, InH, Amt),
1160 DAG.getNode(Op2, NVT, InL, Amt2));
1168 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1170 bool DAGTypeLegalizer::
1171 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1172 SDValue Amt = N->getOperand(1);
1173 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1174 EVT ShTy = Amt.getValueType();
1175 unsigned NVTBits = NVT.getSizeInBits();
1176 assert(isPowerOf2_32(NVTBits) &&
1177 "Expanded integer type size not a power of two!");
1178 DebugLoc dl = N->getDebugLoc();
1180 // Get the incoming operand to be shifted.
1182 GetExpandedInteger(N->getOperand(0), InL, InH);
1184 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1185 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1186 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1187 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1188 Amt, NVBitsNode, ISD::SETULT);
1190 SDValue LoS, HiS, LoL, HiL;
1191 switch (N->getOpcode()) {
1192 default: llvm_unreachable("Unknown shift");
1194 // Short: ShAmt < NVTBits
1195 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1196 HiS = DAG.getNode(ISD::OR, dl, NVT,
1197 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1198 // FIXME: If Amt is zero, the following shift generates an undefined result
1199 // on some architectures.
1200 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1202 // Long: ShAmt >= NVTBits
1203 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1204 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1206 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1207 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1210 // Short: ShAmt < NVTBits
1211 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1212 LoS = DAG.getNode(ISD::OR, dl, NVT,
1213 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1214 // FIXME: If Amt is zero, the following shift generates an undefined result
1215 // on some architectures.
1216 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1218 // Long: ShAmt >= NVTBits
1219 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1220 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1222 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1223 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1226 // Short: ShAmt < NVTBits
1227 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1228 LoS = DAG.getNode(ISD::OR, dl, NVT,
1229 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1230 // FIXME: If Amt is zero, the following shift generates an undefined result
1231 // on some architectures.
1232 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1234 // Long: ShAmt >= NVTBits
1235 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1236 DAG.getConstant(NVTBits-1, ShTy));
1237 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1239 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1240 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1247 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1248 SDValue &Lo, SDValue &Hi) {
1249 DebugLoc dl = N->getDebugLoc();
1250 // Expand the subcomponents.
1251 SDValue LHSL, LHSH, RHSL, RHSH;
1252 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1253 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1255 EVT NVT = LHSL.getValueType();
1256 SDValue LoOps[2] = { LHSL, RHSL };
1257 SDValue HiOps[3] = { LHSH, RHSH };
1259 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1260 // them. TODO: Teach operation legalization how to expand unsupported
1261 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1262 // a carry of type MVT::Flag, but there doesn't seem to be any way to
1263 // generate a value of this type in the expanded code sequence.
1265 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1266 ISD::ADDC : ISD::SUBC,
1267 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1270 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1271 if (N->getOpcode() == ISD::ADD) {
1272 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1273 HiOps[2] = Lo.getValue(1);
1274 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1276 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1277 HiOps[2] = Lo.getValue(1);
1278 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1281 if (N->getOpcode() == ISD::ADD) {
1282 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1283 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1284 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1286 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1287 DAG.getConstant(1, NVT),
1288 DAG.getConstant(0, NVT));
1289 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1291 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1292 DAG.getConstant(1, NVT), Carry1);
1293 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1295 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1296 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1298 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1299 LoOps[0], LoOps[1], ISD::SETULT);
1300 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1301 DAG.getConstant(1, NVT),
1302 DAG.getConstant(0, NVT));
1303 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1308 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1309 SDValue &Lo, SDValue &Hi) {
1310 // Expand the subcomponents.
1311 SDValue LHSL, LHSH, RHSL, RHSH;
1312 DebugLoc dl = N->getDebugLoc();
1313 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1314 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1315 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1316 SDValue LoOps[2] = { LHSL, RHSL };
1317 SDValue HiOps[3] = { LHSH, RHSH };
1319 if (N->getOpcode() == ISD::ADDC) {
1320 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1321 HiOps[2] = Lo.getValue(1);
1322 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1324 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1325 HiOps[2] = Lo.getValue(1);
1326 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1329 // Legalized the flag result - switch anything that used the old flag to
1331 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1334 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1335 SDValue &Lo, SDValue &Hi) {
1336 // Expand the subcomponents.
1337 SDValue LHSL, LHSH, RHSL, RHSH;
1338 DebugLoc dl = N->getDebugLoc();
1339 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1340 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1341 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1342 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1343 SDValue HiOps[3] = { LHSH, RHSH };
1345 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1346 HiOps[2] = Lo.getValue(1);
1347 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1349 // Legalized the flag result - switch anything that used the old flag to
1351 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1354 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1355 SDValue &Lo, SDValue &Hi) {
1356 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1357 DebugLoc dl = N->getDebugLoc();
1358 SDValue Op = N->getOperand(0);
1359 if (Op.getValueType().bitsLE(NVT)) {
1360 // The low part is any extension of the input (which degenerates to a copy).
1361 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1362 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1364 // For example, extension of an i48 to an i64. The operand type necessarily
1365 // promotes to the result type, so will end up being expanded too.
1366 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1367 "Only know how to promote this result!");
1368 SDValue Res = GetPromotedInteger(Op);
1369 assert(Res.getValueType() == N->getValueType(0) &&
1370 "Operand over promoted?");
1371 // Split the promoted operand. This will simplify when it is expanded.
1372 SplitInteger(Res, Lo, Hi);
1376 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1377 SDValue &Lo, SDValue &Hi) {
1378 DebugLoc dl = N->getDebugLoc();
1379 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1380 EVT NVT = Lo.getValueType();
1381 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1382 unsigned NVTBits = NVT.getSizeInBits();
1383 unsigned EVTBits = EVT.getSizeInBits();
1385 if (NVTBits < EVTBits) {
1386 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1387 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), EVTBits - NVTBits)));
1389 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1390 // The high part replicates the sign bit of Lo, make it explicit.
1391 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1392 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1396 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1397 SDValue &Lo, SDValue &Hi) {
1398 DebugLoc dl = N->getDebugLoc();
1399 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1400 EVT NVT = Lo.getValueType();
1401 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1402 unsigned NVTBits = NVT.getSizeInBits();
1403 unsigned EVTBits = EVT.getSizeInBits();
1405 if (NVTBits < EVTBits) {
1406 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1407 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), EVTBits - NVTBits)));
1409 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1410 // The high part must be zero, make it explicit.
1411 Hi = DAG.getConstant(0, NVT);
1415 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1416 SDValue &Lo, SDValue &Hi) {
1417 DebugLoc dl = N->getDebugLoc();
1418 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1419 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1420 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1423 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1424 SDValue &Lo, SDValue &Hi) {
1425 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1426 unsigned NBitWidth = NVT.getSizeInBits();
1427 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1428 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1429 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1432 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1433 SDValue &Lo, SDValue &Hi) {
1434 DebugLoc dl = N->getDebugLoc();
1435 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1436 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1437 EVT NVT = Lo.getValueType();
1439 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1440 DAG.getConstant(0, NVT), ISD::SETNE);
1442 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1443 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1445 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1446 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1447 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1448 Hi = DAG.getConstant(0, NVT);
1451 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1452 SDValue &Lo, SDValue &Hi) {
1453 DebugLoc dl = N->getDebugLoc();
1454 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1455 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1456 EVT NVT = Lo.getValueType();
1457 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1458 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1459 Hi = DAG.getConstant(0, NVT);
1462 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1463 SDValue &Lo, SDValue &Hi) {
1464 DebugLoc dl = N->getDebugLoc();
1465 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1466 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1467 EVT NVT = Lo.getValueType();
1469 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1470 DAG.getConstant(0, NVT), ISD::SETNE);
1472 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1473 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1475 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1476 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1477 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1478 Hi = DAG.getConstant(0, NVT);
1481 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1483 DebugLoc dl = N->getDebugLoc();
1484 EVT VT = N->getValueType(0);
1485 SDValue Op = N->getOperand(0);
1486 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1487 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1488 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1491 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1493 DebugLoc dl = N->getDebugLoc();
1494 EVT VT = N->getValueType(0);
1495 SDValue Op = N->getOperand(0);
1496 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1497 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1498 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1501 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1502 SDValue &Lo, SDValue &Hi) {
1503 if (ISD::isNormalLoad(N)) {
1504 ExpandRes_NormalLoad(N, Lo, Hi);
1508 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1510 EVT VT = N->getValueType(0);
1511 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1512 SDValue Ch = N->getChain();
1513 SDValue Ptr = N->getBasePtr();
1514 ISD::LoadExtType ExtType = N->getExtensionType();
1515 int SVOffset = N->getSrcValueOffset();
1516 unsigned Alignment = N->getAlignment();
1517 bool isVolatile = N->isVolatile();
1518 bool isNonTemporal = N->isNonTemporal();
1519 DebugLoc dl = N->getDebugLoc();
1521 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1523 if (N->getMemoryVT().bitsLE(NVT)) {
1524 EVT MemVT = N->getMemoryVT();
1526 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1527 MemVT, isVolatile, isNonTemporal, Alignment);
1529 // Remember the chain.
1530 Ch = Lo.getValue(1);
1532 if (ExtType == ISD::SEXTLOAD) {
1533 // The high part is obtained by SRA'ing all but one of the bits of the
1535 unsigned LoSize = Lo.getValueType().getSizeInBits();
1536 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1537 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1538 } else if (ExtType == ISD::ZEXTLOAD) {
1539 // The high part is just a zero.
1540 Hi = DAG.getConstant(0, NVT);
1542 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1543 // The high part is undefined.
1544 Hi = DAG.getUNDEF(NVT);
1546 } else if (TLI.isLittleEndian()) {
1547 // Little-endian - low bits are at low addresses.
1548 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
1549 isVolatile, isNonTemporal, Alignment);
1551 unsigned ExcessBits =
1552 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1553 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1555 // Increment the pointer to the other half.
1556 unsigned IncrementSize = NVT.getSizeInBits()/8;
1557 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1558 DAG.getIntPtrConstant(IncrementSize));
1559 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(),
1560 SVOffset+IncrementSize, NEVT,
1561 isVolatile, isNonTemporal,
1562 MinAlign(Alignment, IncrementSize));
1564 // Build a factor node to remember that this load is independent of the
1566 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1569 // Big-endian - high bits are at low addresses. Favor aligned loads at
1570 // the cost of some bit-fiddling.
1571 EVT MemVT = N->getMemoryVT();
1572 unsigned EBytes = MemVT.getStoreSize();
1573 unsigned IncrementSize = NVT.getSizeInBits()/8;
1574 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1576 // Load both the high bits and maybe some of the low bits.
1577 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1578 EVT::getIntegerVT(*DAG.getContext(),
1579 MemVT.getSizeInBits() - ExcessBits),
1580 isVolatile, isNonTemporal, Alignment);
1582 // Increment the pointer to the other half.
1583 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1584 DAG.getIntPtrConstant(IncrementSize));
1585 // Load the rest of the low bits.
1586 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(),
1587 SVOffset+IncrementSize,
1588 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1589 isVolatile, isNonTemporal,
1590 MinAlign(Alignment, IncrementSize));
1592 // Build a factor node to remember that this load is independent of the
1594 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1597 if (ExcessBits < NVT.getSizeInBits()) {
1598 // Transfer low bits from the bottom of Hi to the top of Lo.
1599 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1600 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1601 DAG.getConstant(ExcessBits,
1602 TLI.getPointerTy())));
1603 // Move high bits to the right position in Hi.
1604 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1606 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1607 TLI.getPointerTy()));
1611 // Legalized the chain result - switch anything that used the old chain to
1613 ReplaceValueWith(SDValue(N, 1), Ch);
1616 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1617 SDValue &Lo, SDValue &Hi) {
1618 DebugLoc dl = N->getDebugLoc();
1619 SDValue LL, LH, RL, RH;
1620 GetExpandedInteger(N->getOperand(0), LL, LH);
1621 GetExpandedInteger(N->getOperand(1), RL, RH);
1622 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1623 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1626 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1627 SDValue &Lo, SDValue &Hi) {
1628 EVT VT = N->getValueType(0);
1629 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1630 DebugLoc dl = N->getDebugLoc();
1632 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1633 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1634 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1635 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1636 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1637 SDValue LL, LH, RL, RH;
1638 GetExpandedInteger(N->getOperand(0), LL, LH);
1639 GetExpandedInteger(N->getOperand(1), RL, RH);
1640 unsigned OuterBitSize = VT.getSizeInBits();
1641 unsigned InnerBitSize = NVT.getSizeInBits();
1642 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1643 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1645 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1646 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1647 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1648 // The inputs are both zero-extended.
1650 // We can emit a umul_lohi.
1651 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1652 Hi = SDValue(Lo.getNode(), 1);
1656 // We can emit a mulhu+mul.
1657 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1658 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1662 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1663 // The input values are both sign-extended.
1665 // We can emit a smul_lohi.
1666 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1667 Hi = SDValue(Lo.getNode(), 1);
1671 // We can emit a mulhs+mul.
1672 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1673 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1678 // Lo,Hi = umul LHS, RHS.
1679 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1680 DAG.getVTList(NVT, NVT), LL, RL);
1682 Hi = UMulLOHI.getValue(1);
1683 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1684 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1685 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1686 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1690 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1691 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1692 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1693 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1694 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1695 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1700 // If nothing else, we can make a libcall.
1701 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1703 LC = RTLIB::MUL_I16;
1704 else if (VT == MVT::i32)
1705 LC = RTLIB::MUL_I32;
1706 else if (VT == MVT::i64)
1707 LC = RTLIB::MUL_I64;
1708 else if (VT == MVT::i128)
1709 LC = RTLIB::MUL_I128;
1710 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1712 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1713 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1716 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1717 SDValue &Lo, SDValue &Hi) {
1718 EVT VT = N->getValueType(0);
1719 DebugLoc dl = N->getDebugLoc();
1721 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1723 LC = RTLIB::SDIV_I16;
1724 else if (VT == MVT::i32)
1725 LC = RTLIB::SDIV_I32;
1726 else if (VT == MVT::i64)
1727 LC = RTLIB::SDIV_I64;
1728 else if (VT == MVT::i128)
1729 LC = RTLIB::SDIV_I128;
1730 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1732 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1733 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1736 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1737 SDValue &Lo, SDValue &Hi) {
1738 EVT VT = N->getValueType(0);
1739 DebugLoc dl = N->getDebugLoc();
1741 // If we can emit an efficient shift operation, do so now. Check to see if
1742 // the RHS is a constant.
1743 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1744 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1746 // If we can determine that the high bit of the shift is zero or one, even if
1747 // the low bits are variable, emit this shift in an optimized form.
1748 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1751 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1753 if (N->getOpcode() == ISD::SHL) {
1754 PartsOpc = ISD::SHL_PARTS;
1755 } else if (N->getOpcode() == ISD::SRL) {
1756 PartsOpc = ISD::SRL_PARTS;
1758 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1759 PartsOpc = ISD::SRA_PARTS;
1762 // Next check to see if the target supports this SHL_PARTS operation or if it
1763 // will custom expand it.
1764 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1765 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1766 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1767 Action == TargetLowering::Custom) {
1768 // Expand the subcomponents.
1770 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1772 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1773 EVT VT = LHSL.getValueType();
1774 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
1775 Hi = Lo.getValue(1);
1779 // Otherwise, emit a libcall.
1780 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1782 if (N->getOpcode() == ISD::SHL) {
1783 isSigned = false; /*sign irrelevant*/
1785 LC = RTLIB::SHL_I16;
1786 else if (VT == MVT::i32)
1787 LC = RTLIB::SHL_I32;
1788 else if (VT == MVT::i64)
1789 LC = RTLIB::SHL_I64;
1790 else if (VT == MVT::i128)
1791 LC = RTLIB::SHL_I128;
1792 } else if (N->getOpcode() == ISD::SRL) {
1795 LC = RTLIB::SRL_I16;
1796 else if (VT == MVT::i32)
1797 LC = RTLIB::SRL_I32;
1798 else if (VT == MVT::i64)
1799 LC = RTLIB::SRL_I64;
1800 else if (VT == MVT::i128)
1801 LC = RTLIB::SRL_I128;
1803 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1806 LC = RTLIB::SRA_I16;
1807 else if (VT == MVT::i32)
1808 LC = RTLIB::SRA_I32;
1809 else if (VT == MVT::i64)
1810 LC = RTLIB::SRA_I64;
1811 else if (VT == MVT::i128)
1812 LC = RTLIB::SRA_I128;
1815 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
1816 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1817 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
1821 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
1822 llvm_unreachable("Unsupported shift!");
1825 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1826 SDValue &Lo, SDValue &Hi) {
1827 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1828 DebugLoc dl = N->getDebugLoc();
1829 SDValue Op = N->getOperand(0);
1830 if (Op.getValueType().bitsLE(NVT)) {
1831 // The low part is sign extension of the input (degenerates to a copy).
1832 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
1833 // The high part is obtained by SRA'ing all but one of the bits of low part.
1834 unsigned LoSize = NVT.getSizeInBits();
1835 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1836 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1838 // For example, extension of an i48 to an i64. The operand type necessarily
1839 // promotes to the result type, so will end up being expanded too.
1840 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1841 "Only know how to promote this result!");
1842 SDValue Res = GetPromotedInteger(Op);
1843 assert(Res.getValueType() == N->getValueType(0) &&
1844 "Operand over promoted?");
1845 // Split the promoted operand. This will simplify when it is expanded.
1846 SplitInteger(Res, Lo, Hi);
1847 unsigned ExcessBits =
1848 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1849 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1850 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), ExcessBits)));
1854 void DAGTypeLegalizer::
1855 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1856 DebugLoc dl = N->getDebugLoc();
1857 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1858 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1860 if (EVT.bitsLE(Lo.getValueType())) {
1861 // sext_inreg the low part if needed.
1862 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
1865 // The high part gets the sign extension from the lo-part. This handles
1866 // things like sextinreg V:i64 from i8.
1867 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
1868 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1869 TLI.getPointerTy()));
1871 // For example, extension of an i48 to an i64. Leave the low part alone,
1872 // sext_inreg the high part.
1873 unsigned ExcessBits =
1874 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1875 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1876 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), ExcessBits)));
1880 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1881 SDValue &Lo, SDValue &Hi) {
1882 EVT VT = N->getValueType(0);
1883 DebugLoc dl = N->getDebugLoc();
1885 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1887 LC = RTLIB::SREM_I16;
1888 else if (VT == MVT::i32)
1889 LC = RTLIB::SREM_I32;
1890 else if (VT == MVT::i64)
1891 LC = RTLIB::SREM_I64;
1892 else if (VT == MVT::i128)
1893 LC = RTLIB::SREM_I128;
1894 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1896 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1897 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1900 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1901 SDValue &Lo, SDValue &Hi) {
1902 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1903 DebugLoc dl = N->getDebugLoc();
1904 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
1905 Hi = DAG.getNode(ISD::SRL, dl,
1906 N->getOperand(0).getValueType(), N->getOperand(0),
1907 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
1908 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
1911 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1912 SDValue &Lo, SDValue &Hi) {
1913 EVT VT = N->getValueType(0);
1914 DebugLoc dl = N->getDebugLoc();
1916 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1918 LC = RTLIB::UDIV_I16;
1919 else if (VT == MVT::i32)
1920 LC = RTLIB::UDIV_I32;
1921 else if (VT == MVT::i64)
1922 LC = RTLIB::UDIV_I64;
1923 else if (VT == MVT::i128)
1924 LC = RTLIB::UDIV_I128;
1925 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1927 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1928 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1931 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1932 SDValue &Lo, SDValue &Hi) {
1933 EVT VT = N->getValueType(0);
1934 DebugLoc dl = N->getDebugLoc();
1936 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1938 LC = RTLIB::UREM_I16;
1939 else if (VT == MVT::i32)
1940 LC = RTLIB::UREM_I32;
1941 else if (VT == MVT::i64)
1942 LC = RTLIB::UREM_I64;
1943 else if (VT == MVT::i128)
1944 LC = RTLIB::UREM_I128;
1945 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1947 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1948 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1951 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1952 SDValue &Lo, SDValue &Hi) {
1953 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1954 DebugLoc dl = N->getDebugLoc();
1955 SDValue Op = N->getOperand(0);
1956 if (Op.getValueType().bitsLE(NVT)) {
1957 // The low part is zero extension of the input (degenerates to a copy).
1958 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
1959 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1961 // For example, extension of an i48 to an i64. The operand type necessarily
1962 // promotes to the result type, so will end up being expanded too.
1963 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1964 "Only know how to promote this result!");
1965 SDValue Res = GetPromotedInteger(Op);
1966 assert(Res.getValueType() == N->getValueType(0) &&
1967 "Operand over promoted?");
1968 // Split the promoted operand. This will simplify when it is expanded.
1969 SplitInteger(Res, Lo, Hi);
1970 unsigned ExcessBits =
1971 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1972 Hi = DAG.getZeroExtendInReg(Hi, dl,
1973 EVT::getIntegerVT(*DAG.getContext(), ExcessBits));
1978 //===----------------------------------------------------------------------===//
1979 // Integer Operand Expansion
1980 //===----------------------------------------------------------------------===//
1982 /// ExpandIntegerOperand - This method is called when the specified operand of
1983 /// the specified node is found to need expansion. At this point, all of the
1984 /// result types of the node are known to be legal, but other operands of the
1985 /// node may need promotion or expansion as well as the specified one.
1986 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1987 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
1988 SDValue Res = SDValue();
1990 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1993 switch (N->getOpcode()) {
1996 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
1997 N->dump(&DAG); dbgs() << "\n";
1999 llvm_unreachable("Do not know how to expand this operator's operand!");
2001 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
2002 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2003 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2004 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2005 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2006 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2007 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2008 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2009 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2010 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2011 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2012 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2018 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2019 case ISD::RETURNADDR:
2020 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2023 // If the result is null, the sub-method took care of registering results etc.
2024 if (!Res.getNode()) return false;
2026 // If the result is N, the sub-method updated N in place. Tell the legalizer
2028 if (Res.getNode() == N)
2031 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2032 "Invalid operand expansion");
2034 ReplaceValueWith(SDValue(N, 0), Res);
2038 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2039 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2040 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2042 ISD::CondCode &CCCode,
2044 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2045 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2046 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2048 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2049 if (RHSLo == RHSHi) {
2050 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2051 if (RHSCST->isAllOnesValue()) {
2052 // Equality comparison to -1.
2053 NewLHS = DAG.getNode(ISD::AND, dl,
2054 LHSLo.getValueType(), LHSLo, LHSHi);
2061 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2062 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2063 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2064 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2068 // If this is a comparison of the sign bit, just look at the top part.
2070 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2071 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2072 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2078 // FIXME: This generated code sucks.
2079 ISD::CondCode LowCC;
2081 default: llvm_unreachable("Unknown integer setcc!");
2083 case ISD::SETULT: LowCC = ISD::SETULT; break;
2085 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2087 case ISD::SETULE: LowCC = ISD::SETULE; break;
2089 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2092 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2093 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2094 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2096 // NOTE: on targets without efficient SELECT of bools, we can always use
2097 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2098 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL);
2100 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2101 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2102 if (!Tmp1.getNode())
2103 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2104 LHSLo, RHSLo, LowCC);
2105 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2106 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2107 if (!Tmp2.getNode())
2108 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2109 TLI.getSetCCResultType(LHSHi.getValueType()),
2110 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2112 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2113 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2114 if ((Tmp1C && Tmp1C->isNullValue()) ||
2115 (Tmp2C && Tmp2C->isNullValue() &&
2116 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2117 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2118 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2119 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2120 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2121 // low part is known false, returns high part.
2122 // For LE / GE, if high part is known false, ignore the low part.
2123 // For LT / GT, if high part is known true, ignore the low part.
2129 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2130 LHSHi, RHSHi, ISD::SETEQ, false,
2131 DagCombineInfo, dl);
2132 if (!NewLHS.getNode())
2133 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2134 LHSHi, RHSHi, ISD::SETEQ);
2135 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2136 NewLHS, Tmp1, Tmp2);
2140 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2141 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2142 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2143 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2145 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2146 // against zero to select between true and false values.
2147 if (NewRHS.getNode() == 0) {
2148 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2149 CCCode = ISD::SETNE;
2152 // Update N to have the operands specified.
2153 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
2154 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2158 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2159 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2160 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2161 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2163 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2164 // against zero to select between true and false values.
2165 if (NewRHS.getNode() == 0) {
2166 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2167 CCCode = ISD::SETNE;
2170 // Update N to have the operands specified.
2171 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2172 N->getOperand(2), N->getOperand(3),
2173 DAG.getCondCode(CCCode));
2176 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2177 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2178 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2179 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2181 // If ExpandSetCCOperands returned a scalar, use it.
2182 if (NewRHS.getNode() == 0) {
2183 assert(NewLHS.getValueType() == N->getValueType(0) &&
2184 "Unexpected setcc expansion!");
2188 // Otherwise, update N to have the operands specified.
2189 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2190 DAG.getCondCode(CCCode));
2193 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2194 // The value being shifted is legal, but the shift amount is too big.
2195 // It follows that either the result of the shift is undefined, or the
2196 // upper half of the shift amount is zero. Just use the lower half.
2198 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2199 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Lo);
2202 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2203 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2204 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2205 // constant to valid type.
2207 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2208 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo);
2211 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2212 SDValue Op = N->getOperand(0);
2213 EVT DstVT = N->getValueType(0);
2214 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2215 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2216 "Don't know how to expand this SINT_TO_FP!");
2217 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2220 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2221 if (ISD::isNormalStore(N))
2222 return ExpandOp_NormalStore(N, OpNo);
2224 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2225 assert(OpNo == 1 && "Can only expand the stored value so far");
2227 EVT VT = N->getOperand(1).getValueType();
2228 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2229 SDValue Ch = N->getChain();
2230 SDValue Ptr = N->getBasePtr();
2231 int SVOffset = N->getSrcValueOffset();
2232 unsigned Alignment = N->getAlignment();
2233 bool isVolatile = N->isVolatile();
2234 bool isNonTemporal = N->isNonTemporal();
2235 DebugLoc dl = N->getDebugLoc();
2238 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2240 if (N->getMemoryVT().bitsLE(NVT)) {
2241 GetExpandedInteger(N->getValue(), Lo, Hi);
2242 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2243 N->getMemoryVT(), isVolatile, isNonTemporal,
2245 } else if (TLI.isLittleEndian()) {
2246 // Little-endian - low bits are at low addresses.
2247 GetExpandedInteger(N->getValue(), Lo, Hi);
2249 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2250 isVolatile, isNonTemporal, Alignment);
2252 unsigned ExcessBits =
2253 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2254 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2256 // Increment the pointer to the other half.
2257 unsigned IncrementSize = NVT.getSizeInBits()/8;
2258 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2259 DAG.getIntPtrConstant(IncrementSize));
2260 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2261 SVOffset+IncrementSize, NEVT,
2262 isVolatile, isNonTemporal,
2263 MinAlign(Alignment, IncrementSize));
2264 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2266 // Big-endian - high bits are at low addresses. Favor aligned stores at
2267 // the cost of some bit-fiddling.
2268 GetExpandedInteger(N->getValue(), Lo, Hi);
2270 EVT ExtVT = N->getMemoryVT();
2271 unsigned EBytes = ExtVT.getStoreSize();
2272 unsigned IncrementSize = NVT.getSizeInBits()/8;
2273 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2274 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2275 ExtVT.getSizeInBits() - ExcessBits);
2277 if (ExcessBits < NVT.getSizeInBits()) {
2278 // Transfer high bits from the top of Lo to the bottom of Hi.
2279 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2280 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2281 TLI.getPointerTy()));
2282 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2283 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2284 DAG.getConstant(ExcessBits,
2285 TLI.getPointerTy())));
2288 // Store both the high bits and maybe some of the low bits.
2289 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2290 SVOffset, HiVT, isVolatile, isNonTemporal,
2293 // Increment the pointer to the other half.
2294 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2295 DAG.getIntPtrConstant(IncrementSize));
2296 // Store the lowest ExcessBits bits in the second half.
2297 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(),
2298 SVOffset+IncrementSize,
2299 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2300 isVolatile, isNonTemporal,
2301 MinAlign(Alignment, IncrementSize));
2302 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2306 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2308 GetExpandedInteger(N->getOperand(0), InL, InH);
2309 // Just truncate the low part of the source.
2310 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2313 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2314 SDValue Op = N->getOperand(0);
2315 EVT SrcVT = Op.getValueType();
2316 EVT DstVT = N->getValueType(0);
2317 DebugLoc dl = N->getDebugLoc();
2319 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2320 // Do a signed conversion then adjust the result.
2321 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2322 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2324 // The result of the signed conversion needs adjusting if the 'sign bit' of
2325 // the incoming integer was set. To handle this, we dynamically test to see
2326 // if it is set, and, if so, add a fudge factor.
2328 const uint64_t F32TwoE32 = 0x4F800000ULL;
2329 const uint64_t F32TwoE64 = 0x5F800000ULL;
2330 const uint64_t F32TwoE128 = 0x7F800000ULL;
2333 if (SrcVT == MVT::i32)
2334 FF = APInt(32, F32TwoE32);
2335 else if (SrcVT == MVT::i64)
2336 FF = APInt(32, F32TwoE64);
2337 else if (SrcVT == MVT::i128)
2338 FF = APInt(32, F32TwoE128);
2340 assert(false && "Unsupported UINT_TO_FP!");
2342 // Check whether the sign bit is set.
2344 GetExpandedInteger(Op, Lo, Hi);
2345 SDValue SignSet = DAG.getSetCC(dl,
2346 TLI.getSetCCResultType(Hi.getValueType()),
2347 Hi, DAG.getConstant(0, Hi.getValueType()),
2350 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2351 SDValue FudgePtr = DAG.getConstantPool(
2352 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2353 TLI.getPointerTy());
2355 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2356 SDValue Zero = DAG.getIntPtrConstant(0);
2357 SDValue Four = DAG.getIntPtrConstant(4);
2358 if (TLI.isBigEndian()) std::swap(Zero, Four);
2359 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2361 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2362 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2363 Alignment = std::min(Alignment, 4u);
2365 // Load the value out, extending it from f32 to the destination float type.
2366 // FIXME: Avoid the extend by constructing the right constant pool?
2367 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2368 FudgePtr, NULL, 0, MVT::f32,
2369 false, false, Alignment);
2370 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2373 // Otherwise, use a libcall.
2374 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2375 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2376 "Don't know how to expand this UINT_TO_FP!");
2377 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);