1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 //===----------------------------------------------------------------------===//
28 // Integer Result Promotion
29 //===----------------------------------------------------------------------===//
31 /// PromoteIntegerResult - This method is called when a result of a node is
32 /// found to be in need of promotion to a larger type. At this point, the node
33 /// may also have invalid operands or may have other results that need
34 /// expansion, we just know that (at least) one result needs promotion.
35 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
37 SDValue Res = SDValue();
39 // See if the target wants to custom expand this node.
40 if (CustomLowerNode(N, N->getValueType(ResNo), true))
43 switch (N->getOpcode()) {
46 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
47 N->dump(&DAG); dbgs() << "\n";
49 llvm_unreachable("Do not know how to promote this operator!");
50 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
51 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
52 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
53 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
54 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
55 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
56 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
57 case ISD::CONVERT_RNDSAT:
58 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
59 case ISD::CTLZ_ZERO_UNDEF:
60 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
61 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
62 case ISD::CTTZ_ZERO_UNDEF:
63 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
64 case ISD::EXTRACT_VECTOR_ELT:
65 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
66 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
67 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
68 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
69 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
70 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
71 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
72 case ISD::SIGN_EXTEND_INREG:
73 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
74 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
75 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
76 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
77 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
78 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
80 case ISD::EXTRACT_SUBVECTOR:
81 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
82 case ISD::VECTOR_SHUFFLE:
83 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
84 case ISD::INSERT_VECTOR_ELT:
85 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
86 case ISD::BUILD_VECTOR:
87 Res = PromoteIntRes_BUILD_VECTOR(N); break;
88 case ISD::SCALAR_TO_VECTOR:
89 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
90 case ISD::CONCAT_VECTORS:
91 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
93 case ISD::SIGN_EXTEND:
94 case ISD::ZERO_EXTEND:
95 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
98 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
100 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break;
107 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
110 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
113 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
116 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
118 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
120 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
122 case ISD::ATOMIC_LOAD:
123 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
125 case ISD::ATOMIC_LOAD_ADD:
126 case ISD::ATOMIC_LOAD_SUB:
127 case ISD::ATOMIC_LOAD_AND:
128 case ISD::ATOMIC_LOAD_OR:
129 case ISD::ATOMIC_LOAD_XOR:
130 case ISD::ATOMIC_LOAD_NAND:
131 case ISD::ATOMIC_LOAD_MIN:
132 case ISD::ATOMIC_LOAD_MAX:
133 case ISD::ATOMIC_LOAD_UMIN:
134 case ISD::ATOMIC_LOAD_UMAX:
135 case ISD::ATOMIC_SWAP:
136 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
138 case ISD::ATOMIC_CMP_SWAP:
139 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
142 // If the result is null then the sub-method took care of registering it.
144 SetPromotedInteger(SDValue(N, ResNo), Res);
147 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
149 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
150 return GetPromotedInteger(Op);
153 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
154 // Sign-extend the new bits, and continue the assertion.
155 SDValue Op = SExtPromotedInteger(N->getOperand(0));
156 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
157 Op.getValueType(), Op, N->getOperand(1));
160 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
161 // Zero the new bits, and continue the assertion.
162 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
163 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
164 Op.getValueType(), Op, N->getOperand(1));
167 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
168 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
169 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
170 N->getMemoryVT(), ResVT,
171 N->getChain(), N->getBasePtr(),
172 N->getMemOperand(), N->getOrdering(),
174 // Legalized the chain result - switch anything that used the old chain to
176 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
180 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
181 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
182 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
184 N->getChain(), N->getBasePtr(),
185 Op2, N->getMemOperand(), N->getOrdering(),
187 // Legalized the chain result - switch anything that used the old chain to
189 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
193 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
194 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
195 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
196 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
197 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
198 Op2, Op3, N->getMemOperand(), N->getOrdering(),
200 // Legalized the chain result - switch anything that used the old chain to
202 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
206 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
207 SDValue InOp = N->getOperand(0);
208 EVT InVT = InOp.getValueType();
209 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
210 EVT OutVT = N->getValueType(0);
211 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
212 DebugLoc dl = N->getDebugLoc();
214 switch (getTypeAction(InVT)) {
215 case TargetLowering::TypeLegal:
217 case TargetLowering::TypePromoteInteger:
218 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
219 // The input promotes to the same size. Convert the promoted value.
220 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
222 case TargetLowering::TypeSoftenFloat:
223 // Promote the integer operand by hand.
224 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
225 case TargetLowering::TypeExpandInteger:
226 case TargetLowering::TypeExpandFloat:
228 case TargetLowering::TypeScalarizeVector:
229 // Convert the element to an integer and promote it by hand.
230 if (!NOutVT.isVector())
231 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
232 BitConvertToInteger(GetScalarizedVector(InOp)));
234 case TargetLowering::TypeSplitVector: {
235 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
236 // pieces of the input into integers and reassemble in the final type.
238 GetSplitVector(N->getOperand(0), Lo, Hi);
239 Lo = BitConvertToInteger(Lo);
240 Hi = BitConvertToInteger(Hi);
242 if (TLI.isBigEndian())
245 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
246 EVT::getIntegerVT(*DAG.getContext(),
247 NOutVT.getSizeInBits()),
248 JoinIntegers(Lo, Hi));
249 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
251 case TargetLowering::TypeWidenVector:
252 // The input is widened to the same size. Convert to the widened value.
253 // Make sure that the outgoing value is not a vector, because this would
254 // make us bitcast between two vectors which are legalized in different ways.
255 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
256 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
259 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
260 CreateStackStoreLoad(InOp, OutVT));
263 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
264 SDValue Op = GetPromotedInteger(N->getOperand(0));
265 EVT OVT = N->getValueType(0);
266 EVT NVT = Op.getValueType();
267 DebugLoc dl = N->getDebugLoc();
269 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
270 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
271 DAG.getConstant(DiffBits, TLI.getPointerTy()));
274 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
275 // The pair element type may be legal, or may not promote to the same type as
276 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
277 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
278 TLI.getTypeToTransformTo(*DAG.getContext(),
279 N->getValueType(0)), JoinIntegers(N->getOperand(0),
283 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
284 EVT VT = N->getValueType(0);
285 // FIXME there is no actual debug info here
286 DebugLoc dl = N->getDebugLoc();
287 // Zero extend things like i1, sign extend everything else. It shouldn't
288 // matter in theory which one we pick, but this tends to give better code?
289 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
290 SDValue Result = DAG.getNode(Opc, dl,
291 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
293 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
297 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
298 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
299 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
300 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
301 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
302 "can only promote integers");
303 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
304 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
305 N->getOperand(1), N->getOperand(2),
306 N->getOperand(3), N->getOperand(4), CvtCode);
309 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
310 // Zero extend to the promoted type and do the count there.
311 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
312 DebugLoc dl = N->getDebugLoc();
313 EVT OVT = N->getValueType(0);
314 EVT NVT = Op.getValueType();
315 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
316 // Subtract off the extra leading bits in the bigger type.
317 return DAG.getNode(ISD::SUB, dl, NVT, Op,
318 DAG.getConstant(NVT.getSizeInBits() -
319 OVT.getSizeInBits(), NVT));
322 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
323 // Zero extend to the promoted type and do the count there.
324 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
325 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
328 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
329 SDValue Op = GetPromotedInteger(N->getOperand(0));
330 EVT OVT = N->getValueType(0);
331 EVT NVT = Op.getValueType();
332 DebugLoc dl = N->getDebugLoc();
333 if (N->getOpcode() == ISD::CTTZ) {
334 // The count is the same in the promoted type except if the original
335 // value was zero. This can be handled by setting the bit just off
336 // the top of the original type.
337 APInt TopBit(NVT.getSizeInBits(), 0);
338 TopBit.setBit(OVT.getSizeInBits());
339 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
341 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
344 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
345 DebugLoc dl = N->getDebugLoc();
346 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
347 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
351 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
352 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
353 unsigned NewOpc = N->getOpcode();
354 DebugLoc dl = N->getDebugLoc();
356 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
357 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
358 // and SINT conversions are Custom, there is no way to tell which is
359 // preferable. We choose SINT because that's the right thing on PPC.)
360 if (N->getOpcode() == ISD::FP_TO_UINT &&
361 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
362 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
363 NewOpc = ISD::FP_TO_SINT;
365 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
367 // Assert that the converted value fits in the original type. If it doesn't
368 // (eg: because the value being converted is too big), then the result of the
369 // original operation was undefined anyway, so the assert is still correct.
370 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
371 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
372 DAG.getValueType(N->getValueType(0).getScalarType()));
375 SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) {
376 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
377 DebugLoc dl = N->getDebugLoc();
379 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
381 return DAG.getNode(ISD::AssertZext, dl,
382 NVT, Res, DAG.getValueType(N->getValueType(0)));
385 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
386 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
387 DebugLoc dl = N->getDebugLoc();
389 if (getTypeAction(N->getOperand(0).getValueType())
390 == TargetLowering::TypePromoteInteger) {
391 SDValue Res = GetPromotedInteger(N->getOperand(0));
392 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
394 // If the result and operand types are the same after promotion, simplify
395 // to an in-register extension.
396 if (NVT == Res.getValueType()) {
397 // The high bits are not guaranteed to be anything. Insert an extend.
398 if (N->getOpcode() == ISD::SIGN_EXTEND)
399 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
400 DAG.getValueType(N->getOperand(0).getValueType()));
401 if (N->getOpcode() == ISD::ZERO_EXTEND)
402 return DAG.getZeroExtendInReg(Res, dl,
403 N->getOperand(0).getValueType().getScalarType());
404 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
409 // Otherwise, just extend the original operand all the way to the larger type.
410 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
413 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
414 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
415 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
416 ISD::LoadExtType ExtType =
417 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
418 DebugLoc dl = N->getDebugLoc();
419 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
421 N->getMemoryVT(), N->isVolatile(),
422 N->isNonTemporal(), N->getAlignment());
424 // Legalized the chain result - switch anything that used the old chain to
426 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
430 /// Promote the overflow flag of an overflowing arithmetic node.
431 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
432 // Simply change the return type of the boolean result.
433 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
434 EVT ValueVTs[] = { N->getValueType(0), NVT };
435 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
436 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
437 DAG.getVTList(ValueVTs, 2), Ops, 2);
439 // Modified the sum result - switch anything that used the old sum to use
441 ReplaceValueWith(SDValue(N, 0), Res);
443 return SDValue(Res.getNode(), 1);
446 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
448 return PromoteIntRes_Overflow(N);
450 // The operation overflowed iff the result in the larger type is not the
451 // sign extension of its truncation to the original type.
452 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
453 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
454 EVT OVT = N->getOperand(0).getValueType();
455 EVT NVT = LHS.getValueType();
456 DebugLoc dl = N->getDebugLoc();
458 // Do the arithmetic in the larger type.
459 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
460 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
462 // Calculate the overflow flag: sign extend the arithmetic result from
463 // the original type.
464 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
465 DAG.getValueType(OVT));
466 // Overflowed if and only if this is not equal to Res.
467 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
469 // Use the calculated overflow everywhere.
470 ReplaceValueWith(SDValue(N, 1), Ofl);
475 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
476 // Sign extend the input.
477 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
478 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
479 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
480 LHS.getValueType(), LHS, RHS);
483 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
484 SDValue LHS = GetPromotedInteger(N->getOperand(1));
485 SDValue RHS = GetPromotedInteger(N->getOperand(2));
486 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
487 LHS.getValueType(), N->getOperand(0),LHS,RHS);
490 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
491 SDValue Mask = N->getOperand(0);
492 EVT OpTy = N->getOperand(1).getValueType();
494 // Promote all the way up to the canonical SetCC type.
495 Mask = PromoteTargetBoolean(Mask, TLI.getSetCCResultType(OpTy));
496 SDValue LHS = GetPromotedInteger(N->getOperand(1));
497 SDValue RHS = GetPromotedInteger(N->getOperand(2));
498 return DAG.getNode(ISD::VSELECT, N->getDebugLoc(),
499 LHS.getValueType(), Mask, LHS, RHS);
502 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
503 SDValue LHS = GetPromotedInteger(N->getOperand(2));
504 SDValue RHS = GetPromotedInteger(N->getOperand(3));
505 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
506 LHS.getValueType(), N->getOperand(0),
507 N->getOperand(1), LHS, RHS, N->getOperand(4));
510 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
511 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
513 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
515 // Only use the result of getSetCCResultType if it is legal,
516 // otherwise just use the promoted result type (NVT).
517 if (!TLI.isTypeLegal(SVT))
520 DebugLoc dl = N->getDebugLoc();
521 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
522 "Vector compare must return a vector result!");
524 // Get the SETCC result using the canonical SETCC type.
525 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
526 N->getOperand(1), N->getOperand(2));
528 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
529 // Convert to the expected type.
530 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
533 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
534 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
535 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
536 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
539 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
540 SDValue Op = GetPromotedInteger(N->getOperand(0));
541 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
542 Op.getValueType(), Op, N->getOperand(1));
545 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
546 // The input may have strange things in the top bits of the registers, but
547 // these operations don't care. They may have weird bits going out, but
548 // that too is okay if they are integer operations.
549 SDValue LHS = GetPromotedInteger(N->getOperand(0));
550 SDValue RHS = GetPromotedInteger(N->getOperand(1));
551 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
552 LHS.getValueType(), LHS, RHS);
555 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
556 // The input value must be properly sign extended.
557 SDValue Res = SExtPromotedInteger(N->getOperand(0));
558 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
559 Res.getValueType(), Res, N->getOperand(1));
562 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
563 // The input value must be properly zero extended.
564 EVT VT = N->getValueType(0);
565 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
566 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
567 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
570 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
571 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
573 SDValue InOp = N->getOperand(0);
574 DebugLoc dl = N->getDebugLoc();
576 switch (getTypeAction(InOp.getValueType())) {
577 default: llvm_unreachable("Unknown type action!");
578 case TargetLowering::TypeLegal:
579 case TargetLowering::TypeExpandInteger:
582 case TargetLowering::TypePromoteInteger:
583 Res = GetPromotedInteger(InOp);
585 case TargetLowering::TypeSplitVector:
586 EVT InVT = InOp.getValueType();
587 assert(InVT.isVector() && "Cannot split scalar types");
588 unsigned NumElts = InVT.getVectorNumElements();
589 assert(NumElts == NVT.getVectorNumElements() &&
590 "Dst and Src must have the same number of elements");
591 assert(isPowerOf2_32(NumElts) &&
592 "Promoted vector type must be a power of two");
595 GetSplitVector(InOp, EOp1, EOp2);
597 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
599 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
600 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
602 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
605 // Truncate to NVT instead of VT
606 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
609 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
611 return PromoteIntRes_Overflow(N);
613 // The operation overflowed iff the result in the larger type is not the
614 // zero extension of its truncation to the original type.
615 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
616 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
617 EVT OVT = N->getOperand(0).getValueType();
618 EVT NVT = LHS.getValueType();
619 DebugLoc dl = N->getDebugLoc();
621 // Do the arithmetic in the larger type.
622 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
623 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
625 // Calculate the overflow flag: zero extend the arithmetic result from
626 // the original type.
627 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
628 // Overflowed if and only if this is not equal to Res.
629 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
631 // Use the calculated overflow everywhere.
632 ReplaceValueWith(SDValue(N, 1), Ofl);
637 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
638 // Promote the overflow bit trivially.
640 return PromoteIntRes_Overflow(N);
642 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
643 DebugLoc DL = N->getDebugLoc();
644 EVT SmallVT = LHS.getValueType();
646 // To determine if the result overflowed in a larger type, we extend the
647 // input to the larger type, do the multiply, then check the high bits of
648 // the result to see if the overflow happened.
649 if (N->getOpcode() == ISD::SMULO) {
650 LHS = SExtPromotedInteger(LHS);
651 RHS = SExtPromotedInteger(RHS);
653 LHS = ZExtPromotedInteger(LHS);
654 RHS = ZExtPromotedInteger(RHS);
656 SDValue Mul = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS);
658 // Overflow occurred iff the high part of the result does not
659 // zero/sign-extend the low part.
661 if (N->getOpcode() == ISD::UMULO) {
662 // Unsigned overflow occurred iff the high part is non-zero.
663 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
664 DAG.getIntPtrConstant(SmallVT.getSizeInBits()));
665 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
666 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
668 // Signed overflow occurred iff the high part does not sign extend the low.
669 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
670 Mul, DAG.getValueType(SmallVT));
671 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
674 // Use the calculated overflow everywhere.
675 ReplaceValueWith(SDValue(N, 1), Overflow);
679 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
680 // Zero extend the input.
681 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
682 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
683 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
684 LHS.getValueType(), LHS, RHS);
687 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
688 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
689 N->getValueType(0)));
692 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
693 SDValue Chain = N->getOperand(0); // Get the chain.
694 SDValue Ptr = N->getOperand(1); // Get the pointer.
695 EVT VT = N->getValueType(0);
696 DebugLoc dl = N->getDebugLoc();
698 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
699 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
700 // The argument is passed as NumRegs registers of type RegVT.
702 SmallVector<SDValue, 8> Parts(NumRegs);
703 for (unsigned i = 0; i < NumRegs; ++i) {
704 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
705 N->getConstantOperandVal(3));
706 Chain = Parts[i].getValue(1);
709 // Handle endianness of the load.
710 if (TLI.isBigEndian())
711 std::reverse(Parts.begin(), Parts.end());
713 // Assemble the parts in the promoted type.
714 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
715 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
716 for (unsigned i = 1; i < NumRegs; ++i) {
717 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
718 // Shift it to the right position and "or" it in.
719 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
720 DAG.getConstant(i * RegVT.getSizeInBits(),
721 TLI.getPointerTy()));
722 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
725 // Modified the chain result - switch anything that used the old chain to
727 ReplaceValueWith(SDValue(N, 1), Chain);
732 //===----------------------------------------------------------------------===//
733 // Integer Operand Promotion
734 //===----------------------------------------------------------------------===//
736 /// PromoteIntegerOperand - This method is called when the specified operand of
737 /// the specified node is found to need promotion. At this point, all of the
738 /// result types of the node are known to be legal, but other operands of the
739 /// node may need promotion or expansion as well as the specified one.
740 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
741 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
742 SDValue Res = SDValue();
744 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
747 switch (N->getOpcode()) {
750 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
751 N->dump(&DAG); dbgs() << "\n";
753 llvm_unreachable("Do not know how to promote this operator's operand!");
755 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
756 case ISD::ATOMIC_STORE:
757 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
759 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
760 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
761 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
762 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
763 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
764 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
765 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
766 case ISD::CONVERT_RNDSAT:
767 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
768 case ISD::INSERT_VECTOR_ELT:
769 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
770 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
771 case ISD::SCALAR_TO_VECTOR:
772 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
774 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
775 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
776 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
777 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
778 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
779 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
781 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
782 case ISD::FP16_TO_FP32:
783 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
784 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
790 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
793 // If the result is null, the sub-method took care of registering results etc.
794 if (!Res.getNode()) return false;
796 // If the result is N, the sub-method updated N in place. Tell the legalizer
798 if (Res.getNode() == N)
801 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
802 "Invalid operand expansion");
804 ReplaceValueWith(SDValue(N, 0), Res);
808 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
809 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
810 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
811 ISD::CondCode CCCode) {
812 // We have to insert explicit sign or zero extends. Note that we could
813 // insert sign extends for ALL conditions, but zero extend is cheaper on
814 // many machines (an AND instead of two shifts), so prefer it.
816 default: llvm_unreachable("Unknown integer comparison!");
823 // ALL of these operations will work if we either sign or zero extend
824 // the operands (including the unsigned comparisons!). Zero extend is
825 // usually a simpler/cheaper operation, so prefer it.
826 NewLHS = ZExtPromotedInteger(NewLHS);
827 NewRHS = ZExtPromotedInteger(NewRHS);
833 NewLHS = SExtPromotedInteger(NewLHS);
834 NewRHS = SExtPromotedInteger(NewRHS);
839 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
840 SDValue Op = GetPromotedInteger(N->getOperand(0));
841 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
844 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
845 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
846 return DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), N->getMemoryVT(),
847 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
848 N->getOrdering(), N->getSynchScope());
851 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
852 // This should only occur in unusual situations like bitcasting to an
853 // x86_fp80, so just turn it into a store+load
854 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
857 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
858 assert(OpNo == 2 && "Don't know how to promote this operand!");
860 SDValue LHS = N->getOperand(2);
861 SDValue RHS = N->getOperand(3);
862 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
864 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
866 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
867 N->getOperand(1), LHS, RHS, N->getOperand(4)),
871 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
872 assert(OpNo == 1 && "only know how to promote condition");
874 // Promote all the way up to the canonical SetCC type.
875 EVT SVT = TLI.getSetCCResultType(MVT::Other);
876 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
878 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
879 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
880 N->getOperand(2)), 0);
883 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
884 // Since the result type is legal, the operands must promote to it.
885 EVT OVT = N->getOperand(0).getValueType();
886 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
887 SDValue Hi = GetPromotedInteger(N->getOperand(1));
888 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
889 DebugLoc dl = N->getDebugLoc();
891 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
892 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
893 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
896 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
897 // The vector type is legal but the element type is not. This implies
898 // that the vector is a power-of-two in length and that the element
899 // type does not have a strange size (eg: it is not i1).
900 EVT VecVT = N->getValueType(0);
901 unsigned NumElts = VecVT.getVectorNumElements();
902 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
904 // Promote the inserted value. The type does not need to match the
905 // vector element type. Check that any extra bits introduced will be
907 assert(N->getOperand(0).getValueType().getSizeInBits() >=
908 N->getValueType(0).getVectorElementType().getSizeInBits() &&
909 "Type of inserted value narrower than vector element type!");
911 SmallVector<SDValue, 16> NewOps;
912 for (unsigned i = 0; i < NumElts; ++i)
913 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
915 return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0);
918 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
919 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
920 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
921 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
922 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
923 "can only promote integer arguments");
924 SDValue InOp = GetPromotedInteger(N->getOperand(0));
925 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
926 N->getOperand(1), N->getOperand(2),
927 N->getOperand(3), N->getOperand(4), CvtCode);
930 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
933 // Promote the inserted value. This is valid because the type does not
934 // have to match the vector element type.
936 // Check that any extra bits introduced will be truncated away.
937 assert(N->getOperand(1).getValueType().getSizeInBits() >=
938 N->getValueType(0).getVectorElementType().getSizeInBits() &&
939 "Type of inserted value narrower than vector element type!");
940 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
941 GetPromotedInteger(N->getOperand(1)),
946 assert(OpNo == 2 && "Different operand and result vector types?");
948 // Promote the index.
949 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
950 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
951 N->getOperand(1), Idx), 0);
954 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
956 DebugLoc dl = N->getDebugLoc();
957 NewOps[0] = N->getOperand(0);
958 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
959 SDValue Flag = GetPromotedInteger(N->getOperand(i));
960 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
962 return SDValue(DAG.UpdateNodeOperands(N, NewOps, array_lengthof(NewOps)), 0);
965 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
966 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
967 // the operand in place.
968 return SDValue(DAG.UpdateNodeOperands(N,
969 GetPromotedInteger(N->getOperand(0))), 0);
972 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
973 assert(OpNo == 0 && "Only know how to promote the condition!");
974 SDValue Cond = N->getOperand(0);
975 EVT OpTy = N->getOperand(1).getValueType();
977 // Promote all the way up to the canonical SetCC type.
978 EVT SVT = TLI.getSetCCResultType(N->getOpcode() == ISD::SELECT ?
979 OpTy.getScalarType() : OpTy);
980 Cond = PromoteTargetBoolean(Cond, SVT);
982 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
983 N->getOperand(2)), 0);
986 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
987 assert(OpNo == 0 && "Don't know how to promote this operand!");
989 SDValue LHS = N->getOperand(0);
990 SDValue RHS = N->getOperand(1);
991 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
993 // The CC (#4) and the possible return values (#2 and #3) have legal types.
994 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
995 N->getOperand(3), N->getOperand(4)), 0);
998 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
999 assert(OpNo == 0 && "Don't know how to promote this operand!");
1001 SDValue LHS = N->getOperand(0);
1002 SDValue RHS = N->getOperand(1);
1003 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1005 // The CC (#2) is always legal.
1006 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1009 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1010 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1011 ZExtPromotedInteger(N->getOperand(1))), 0);
1014 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1015 SDValue Op = GetPromotedInteger(N->getOperand(0));
1016 DebugLoc dl = N->getDebugLoc();
1017 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1018 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1019 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1022 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1023 return SDValue(DAG.UpdateNodeOperands(N,
1024 SExtPromotedInteger(N->getOperand(0))), 0);
1027 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1028 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1029 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1030 unsigned Alignment = N->getAlignment();
1031 bool isVolatile = N->isVolatile();
1032 bool isNonTemporal = N->isNonTemporal();
1033 DebugLoc dl = N->getDebugLoc();
1035 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1037 // Truncate the value and store the result.
1038 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getPointerInfo(),
1040 isVolatile, isNonTemporal, Alignment);
1043 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1044 SDValue Op = GetPromotedInteger(N->getOperand(0));
1045 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
1048 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1049 return SDValue(DAG.UpdateNodeOperands(N,
1050 ZExtPromotedInteger(N->getOperand(0))), 0);
1053 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1054 DebugLoc dl = N->getDebugLoc();
1055 SDValue Op = GetPromotedInteger(N->getOperand(0));
1056 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1057 return DAG.getZeroExtendInReg(Op, dl,
1058 N->getOperand(0).getValueType().getScalarType());
1062 //===----------------------------------------------------------------------===//
1063 // Integer Result Expansion
1064 //===----------------------------------------------------------------------===//
1066 /// ExpandIntegerResult - This method is called when the specified result of the
1067 /// specified node is found to need expansion. At this point, the node may also
1068 /// have invalid operands or may have other results that need promotion, we just
1069 /// know that (at least) one result needs expansion.
1070 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1071 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1073 Lo = Hi = SDValue();
1075 // See if the target wants to custom expand this node.
1076 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1079 switch (N->getOpcode()) {
1082 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1083 N->dump(&DAG); dbgs() << "\n";
1085 llvm_unreachable("Do not know how to expand the result of this operator!");
1087 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1088 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1089 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1090 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1092 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1093 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1094 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1095 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1096 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1098 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1099 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1100 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1101 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1102 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1103 case ISD::CTLZ_ZERO_UNDEF:
1104 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1105 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1106 case ISD::CTTZ_ZERO_UNDEF:
1107 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1108 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1109 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1110 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1111 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1112 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1113 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1114 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1115 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1116 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1117 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1118 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1119 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1120 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1122 case ISD::ATOMIC_LOAD_ADD:
1123 case ISD::ATOMIC_LOAD_SUB:
1124 case ISD::ATOMIC_LOAD_AND:
1125 case ISD::ATOMIC_LOAD_OR:
1126 case ISD::ATOMIC_LOAD_XOR:
1127 case ISD::ATOMIC_LOAD_NAND:
1128 case ISD::ATOMIC_LOAD_MIN:
1129 case ISD::ATOMIC_LOAD_MAX:
1130 case ISD::ATOMIC_LOAD_UMIN:
1131 case ISD::ATOMIC_LOAD_UMAX:
1132 case ISD::ATOMIC_SWAP: {
1133 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1134 SplitInteger(Tmp.first, Lo, Hi);
1135 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1141 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1144 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1147 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1150 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1154 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1157 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1159 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1161 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1164 // If Lo/Hi is null, the sub-method took care of registering results etc.
1166 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1169 /// Lower an atomic node to the appropriate builtin call.
1170 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1171 unsigned Opc = Node->getOpcode();
1172 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1177 llvm_unreachable("Unhandled atomic intrinsic Expand!");
1178 case ISD::ATOMIC_SWAP:
1179 switch (VT.SimpleTy) {
1180 default: llvm_unreachable("Unexpected value type for atomic!");
1181 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
1182 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
1183 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
1184 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
1187 case ISD::ATOMIC_CMP_SWAP:
1188 switch (VT.SimpleTy) {
1189 default: llvm_unreachable("Unexpected value type for atomic!");
1190 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
1191 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
1192 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
1193 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
1196 case ISD::ATOMIC_LOAD_ADD:
1197 switch (VT.SimpleTy) {
1198 default: llvm_unreachable("Unexpected value type for atomic!");
1199 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
1200 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
1201 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
1202 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
1205 case ISD::ATOMIC_LOAD_SUB:
1206 switch (VT.SimpleTy) {
1207 default: llvm_unreachable("Unexpected value type for atomic!");
1208 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
1209 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
1210 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
1211 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
1214 case ISD::ATOMIC_LOAD_AND:
1215 switch (VT.SimpleTy) {
1216 default: llvm_unreachable("Unexpected value type for atomic!");
1217 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
1218 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
1219 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
1220 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
1223 case ISD::ATOMIC_LOAD_OR:
1224 switch (VT.SimpleTy) {
1225 default: llvm_unreachable("Unexpected value type for atomic!");
1226 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
1227 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
1228 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
1229 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
1232 case ISD::ATOMIC_LOAD_XOR:
1233 switch (VT.SimpleTy) {
1234 default: llvm_unreachable("Unexpected value type for atomic!");
1235 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
1236 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
1237 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
1238 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
1241 case ISD::ATOMIC_LOAD_NAND:
1242 switch (VT.SimpleTy) {
1243 default: llvm_unreachable("Unexpected value type for atomic!");
1244 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
1245 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
1246 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
1247 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
1252 return ExpandChainLibCall(LC, Node, false);
1255 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1256 /// and the shift amount is a constant 'Amt'. Expand the operation.
1257 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1258 SDValue &Lo, SDValue &Hi) {
1259 DebugLoc DL = N->getDebugLoc();
1260 // Expand the incoming operand to be shifted, so that we have its parts
1262 GetExpandedInteger(N->getOperand(0), InL, InH);
1264 EVT NVT = InL.getValueType();
1265 unsigned VTBits = N->getValueType(0).getSizeInBits();
1266 unsigned NVTBits = NVT.getSizeInBits();
1267 EVT ShTy = N->getOperand(1).getValueType();
1269 if (N->getOpcode() == ISD::SHL) {
1271 Lo = Hi = DAG.getConstant(0, NVT);
1272 } else if (Amt > NVTBits) {
1273 Lo = DAG.getConstant(0, NVT);
1274 Hi = DAG.getNode(ISD::SHL, DL,
1275 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
1276 } else if (Amt == NVTBits) {
1277 Lo = DAG.getConstant(0, NVT);
1279 } else if (Amt == 1 &&
1280 TLI.isOperationLegalOrCustom(ISD::ADDC,
1281 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1282 // Emit this X << 1 as X+X.
1283 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1284 SDValue LoOps[2] = { InL, InL };
1285 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps, 2);
1286 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1287 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3);
1289 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
1290 Hi = DAG.getNode(ISD::OR, DL, NVT,
1291 DAG.getNode(ISD::SHL, DL, NVT, InH,
1292 DAG.getConstant(Amt, ShTy)),
1293 DAG.getNode(ISD::SRL, DL, NVT, InL,
1294 DAG.getConstant(NVTBits-Amt, ShTy)));
1299 if (N->getOpcode() == ISD::SRL) {
1301 Lo = DAG.getConstant(0, NVT);
1302 Hi = DAG.getConstant(0, NVT);
1303 } else if (Amt > NVTBits) {
1304 Lo = DAG.getNode(ISD::SRL, DL,
1305 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1306 Hi = DAG.getConstant(0, NVT);
1307 } else if (Amt == NVTBits) {
1309 Hi = DAG.getConstant(0, NVT);
1311 Lo = DAG.getNode(ISD::OR, DL, NVT,
1312 DAG.getNode(ISD::SRL, DL, NVT, InL,
1313 DAG.getConstant(Amt, ShTy)),
1314 DAG.getNode(ISD::SHL, DL, NVT, InH,
1315 DAG.getConstant(NVTBits-Amt, ShTy)));
1316 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1321 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1323 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1324 DAG.getConstant(NVTBits-1, ShTy));
1325 } else if (Amt > NVTBits) {
1326 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1327 DAG.getConstant(Amt-NVTBits, ShTy));
1328 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1329 DAG.getConstant(NVTBits-1, ShTy));
1330 } else if (Amt == NVTBits) {
1332 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1333 DAG.getConstant(NVTBits-1, ShTy));
1335 Lo = DAG.getNode(ISD::OR, DL, NVT,
1336 DAG.getNode(ISD::SRL, DL, NVT, InL,
1337 DAG.getConstant(Amt, ShTy)),
1338 DAG.getNode(ISD::SHL, DL, NVT, InH,
1339 DAG.getConstant(NVTBits-Amt, ShTy)));
1340 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1344 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1345 /// this shift based on knowledge of the high bit of the shift amount. If we
1346 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1348 bool DAGTypeLegalizer::
1349 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1350 SDValue Amt = N->getOperand(1);
1351 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1352 EVT ShTy = Amt.getValueType();
1353 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1354 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1355 assert(isPowerOf2_32(NVTBits) &&
1356 "Expanded integer type size not a power of two!");
1357 DebugLoc dl = N->getDebugLoc();
1359 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1360 APInt KnownZero, KnownOne;
1361 DAG.ComputeMaskedBits(N->getOperand(1), KnownZero, KnownOne);
1363 // If we don't know anything about the high bits, exit.
1364 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1367 // Get the incoming operand to be shifted.
1369 GetExpandedInteger(N->getOperand(0), InL, InH);
1371 // If we know that any of the high bits of the shift amount are one, then we
1372 // can do this as a couple of simple shifts.
1373 if (KnownOne.intersects(HighBitMask)) {
1374 // Mask out the high bit, which we know is set.
1375 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1376 DAG.getConstant(~HighBitMask, ShTy));
1378 switch (N->getOpcode()) {
1379 default: llvm_unreachable("Unknown shift");
1381 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1382 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1385 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1386 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1389 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1390 DAG.getConstant(NVTBits-1, ShTy));
1391 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1396 // If we know that all of the high bits of the shift amount are zero, then we
1397 // can do this as a couple of simple shifts.
1398 if ((KnownZero & HighBitMask) == HighBitMask) {
1399 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
1400 // shift if x is zero. We can use XOR here because x is known to be smaller
1402 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1403 DAG.getConstant(NVTBits-1, ShTy));
1406 switch (N->getOpcode()) {
1407 default: llvm_unreachable("Unknown shift");
1408 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1410 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1413 // When shifting right the arithmetic for Lo and Hi is swapped.
1414 if (N->getOpcode() != ISD::SHL)
1415 std::swap(InL, InH);
1417 // Use a little trick to get the bits that move from Lo to Hi. First
1418 // shift by one bit.
1419 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, ShTy));
1420 // Then compute the remaining shift with amount-1.
1421 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
1423 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
1424 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1426 if (N->getOpcode() != ISD::SHL)
1434 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1436 bool DAGTypeLegalizer::
1437 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1438 SDValue Amt = N->getOperand(1);
1439 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1440 EVT ShTy = Amt.getValueType();
1441 unsigned NVTBits = NVT.getSizeInBits();
1442 assert(isPowerOf2_32(NVTBits) &&
1443 "Expanded integer type size not a power of two!");
1444 DebugLoc dl = N->getDebugLoc();
1446 // Get the incoming operand to be shifted.
1448 GetExpandedInteger(N->getOperand(0), InL, InH);
1450 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1451 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1452 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1453 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1454 Amt, NVBitsNode, ISD::SETULT);
1456 SDValue LoS, HiS, LoL, HiL;
1457 switch (N->getOpcode()) {
1458 default: llvm_unreachable("Unknown shift");
1460 // Short: ShAmt < NVTBits
1461 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1462 HiS = DAG.getNode(ISD::OR, dl, NVT,
1463 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1464 // FIXME: If Amt is zero, the following shift generates an undefined result
1465 // on some architectures.
1466 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1468 // Long: ShAmt >= NVTBits
1469 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1470 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1472 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1473 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1476 // Short: ShAmt < NVTBits
1477 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1478 LoS = DAG.getNode(ISD::OR, dl, NVT,
1479 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1480 // FIXME: If Amt is zero, the following shift generates an undefined result
1481 // on some architectures.
1482 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1484 // Long: ShAmt >= NVTBits
1485 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1486 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1488 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1489 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1492 // Short: ShAmt < NVTBits
1493 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1494 LoS = DAG.getNode(ISD::OR, dl, NVT,
1495 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1496 // FIXME: If Amt is zero, the following shift generates an undefined result
1497 // on some architectures.
1498 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1500 // Long: ShAmt >= NVTBits
1501 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1502 DAG.getConstant(NVTBits-1, ShTy));
1503 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1505 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1506 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1511 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1512 SDValue &Lo, SDValue &Hi) {
1513 DebugLoc dl = N->getDebugLoc();
1514 // Expand the subcomponents.
1515 SDValue LHSL, LHSH, RHSL, RHSH;
1516 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1517 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1519 EVT NVT = LHSL.getValueType();
1520 SDValue LoOps[2] = { LHSL, RHSL };
1521 SDValue HiOps[3] = { LHSH, RHSH };
1523 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1524 // them. TODO: Teach operation legalization how to expand unsupported
1525 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1526 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1527 // generate a value of this type in the expanded code sequence.
1529 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1530 ISD::ADDC : ISD::SUBC,
1531 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1534 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1535 if (N->getOpcode() == ISD::ADD) {
1536 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1537 HiOps[2] = Lo.getValue(1);
1538 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1540 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1541 HiOps[2] = Lo.getValue(1);
1542 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1547 if (N->getOpcode() == ISD::ADD) {
1548 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1549 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1550 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1552 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1553 DAG.getConstant(1, NVT),
1554 DAG.getConstant(0, NVT));
1555 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1557 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1558 DAG.getConstant(1, NVT), Carry1);
1559 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1561 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1562 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1564 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1565 LoOps[0], LoOps[1], ISD::SETULT);
1566 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1567 DAG.getConstant(1, NVT),
1568 DAG.getConstant(0, NVT));
1569 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1573 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1574 SDValue &Lo, SDValue &Hi) {
1575 // Expand the subcomponents.
1576 SDValue LHSL, LHSH, RHSL, RHSH;
1577 DebugLoc dl = N->getDebugLoc();
1578 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1579 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1580 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1581 SDValue LoOps[2] = { LHSL, RHSL };
1582 SDValue HiOps[3] = { LHSH, RHSH };
1584 if (N->getOpcode() == ISD::ADDC) {
1585 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1586 HiOps[2] = Lo.getValue(1);
1587 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1589 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1590 HiOps[2] = Lo.getValue(1);
1591 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1594 // Legalized the flag result - switch anything that used the old flag to
1596 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1599 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1600 SDValue &Lo, SDValue &Hi) {
1601 // Expand the subcomponents.
1602 SDValue LHSL, LHSH, RHSL, RHSH;
1603 DebugLoc dl = N->getDebugLoc();
1604 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1605 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1606 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1607 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1608 SDValue HiOps[3] = { LHSH, RHSH };
1610 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1611 HiOps[2] = Lo.getValue(1);
1612 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1614 // Legalized the flag result - switch anything that used the old flag to
1616 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1619 void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
1620 SDValue &Lo, SDValue &Hi) {
1621 SDValue Res = DisintegrateMERGE_VALUES(N, ResNo);
1622 SplitInteger(Res, Lo, Hi);
1625 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1626 SDValue &Lo, SDValue &Hi) {
1627 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1628 DebugLoc dl = N->getDebugLoc();
1629 SDValue Op = N->getOperand(0);
1630 if (Op.getValueType().bitsLE(NVT)) {
1631 // The low part is any extension of the input (which degenerates to a copy).
1632 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1633 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1635 // For example, extension of an i48 to an i64. The operand type necessarily
1636 // promotes to the result type, so will end up being expanded too.
1637 assert(getTypeAction(Op.getValueType()) ==
1638 TargetLowering::TypePromoteInteger &&
1639 "Only know how to promote this result!");
1640 SDValue Res = GetPromotedInteger(Op);
1641 assert(Res.getValueType() == N->getValueType(0) &&
1642 "Operand over promoted?");
1643 // Split the promoted operand. This will simplify when it is expanded.
1644 SplitInteger(Res, Lo, Hi);
1648 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1649 SDValue &Lo, SDValue &Hi) {
1650 DebugLoc dl = N->getDebugLoc();
1651 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1652 EVT NVT = Lo.getValueType();
1653 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1654 unsigned NVTBits = NVT.getSizeInBits();
1655 unsigned EVTBits = EVT.getSizeInBits();
1657 if (NVTBits < EVTBits) {
1658 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1659 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1660 EVTBits - NVTBits)));
1662 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1663 // The high part replicates the sign bit of Lo, make it explicit.
1664 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1665 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1669 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1670 SDValue &Lo, SDValue &Hi) {
1671 DebugLoc dl = N->getDebugLoc();
1672 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1673 EVT NVT = Lo.getValueType();
1674 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1675 unsigned NVTBits = NVT.getSizeInBits();
1676 unsigned EVTBits = EVT.getSizeInBits();
1678 if (NVTBits < EVTBits) {
1679 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1680 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1681 EVTBits - NVTBits)));
1683 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1684 // The high part must be zero, make it explicit.
1685 Hi = DAG.getConstant(0, NVT);
1689 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1690 SDValue &Lo, SDValue &Hi) {
1691 DebugLoc dl = N->getDebugLoc();
1692 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1693 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1694 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1697 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1698 SDValue &Lo, SDValue &Hi) {
1699 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1700 unsigned NBitWidth = NVT.getSizeInBits();
1701 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1702 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT);
1703 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1706 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1707 SDValue &Lo, SDValue &Hi) {
1708 DebugLoc dl = N->getDebugLoc();
1709 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1710 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1711 EVT NVT = Lo.getValueType();
1713 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1714 DAG.getConstant(0, NVT), ISD::SETNE);
1716 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
1717 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1719 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1720 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1721 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1722 Hi = DAG.getConstant(0, NVT);
1725 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1726 SDValue &Lo, SDValue &Hi) {
1727 DebugLoc dl = N->getDebugLoc();
1728 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1729 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1730 EVT NVT = Lo.getValueType();
1731 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1732 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1733 Hi = DAG.getConstant(0, NVT);
1736 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1737 SDValue &Lo, SDValue &Hi) {
1738 DebugLoc dl = N->getDebugLoc();
1739 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1740 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1741 EVT NVT = Lo.getValueType();
1743 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1744 DAG.getConstant(0, NVT), ISD::SETNE);
1746 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1747 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
1749 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1750 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1751 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1752 Hi = DAG.getConstant(0, NVT);
1755 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1757 DebugLoc dl = N->getDebugLoc();
1758 EVT VT = N->getValueType(0);
1759 SDValue Op = N->getOperand(0);
1760 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1761 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1762 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1765 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1767 DebugLoc dl = N->getDebugLoc();
1768 EVT VT = N->getValueType(0);
1769 SDValue Op = N->getOperand(0);
1770 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1771 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1772 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1775 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1776 SDValue &Lo, SDValue &Hi) {
1777 if (ISD::isNormalLoad(N)) {
1778 ExpandRes_NormalLoad(N, Lo, Hi);
1782 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1784 EVT VT = N->getValueType(0);
1785 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1786 SDValue Ch = N->getChain();
1787 SDValue Ptr = N->getBasePtr();
1788 ISD::LoadExtType ExtType = N->getExtensionType();
1789 unsigned Alignment = N->getAlignment();
1790 bool isVolatile = N->isVolatile();
1791 bool isNonTemporal = N->isNonTemporal();
1792 bool isInvariant = N->isInvariant();
1793 DebugLoc dl = N->getDebugLoc();
1795 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1797 if (N->getMemoryVT().bitsLE(NVT)) {
1798 EVT MemVT = N->getMemoryVT();
1800 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1801 MemVT, isVolatile, isNonTemporal, Alignment);
1803 // Remember the chain.
1804 Ch = Lo.getValue(1);
1806 if (ExtType == ISD::SEXTLOAD) {
1807 // The high part is obtained by SRA'ing all but one of the bits of the
1809 unsigned LoSize = Lo.getValueType().getSizeInBits();
1810 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1811 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1812 } else if (ExtType == ISD::ZEXTLOAD) {
1813 // The high part is just a zero.
1814 Hi = DAG.getConstant(0, NVT);
1816 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1817 // The high part is undefined.
1818 Hi = DAG.getUNDEF(NVT);
1820 } else if (TLI.isLittleEndian()) {
1821 // Little-endian - low bits are at low addresses.
1822 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1823 isVolatile, isNonTemporal, isInvariant, Alignment);
1825 unsigned ExcessBits =
1826 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1827 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1829 // Increment the pointer to the other half.
1830 unsigned IncrementSize = NVT.getSizeInBits()/8;
1831 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1832 DAG.getIntPtrConstant(IncrementSize));
1833 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
1834 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
1835 isVolatile, isNonTemporal,
1836 MinAlign(Alignment, IncrementSize));
1838 // Build a factor node to remember that this load is independent of the
1840 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1843 // Big-endian - high bits are at low addresses. Favor aligned loads at
1844 // the cost of some bit-fiddling.
1845 EVT MemVT = N->getMemoryVT();
1846 unsigned EBytes = MemVT.getStoreSize();
1847 unsigned IncrementSize = NVT.getSizeInBits()/8;
1848 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1850 // Load both the high bits and maybe some of the low bits.
1851 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1852 EVT::getIntegerVT(*DAG.getContext(),
1853 MemVT.getSizeInBits() - ExcessBits),
1854 isVolatile, isNonTemporal, Alignment);
1856 // Increment the pointer to the other half.
1857 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1858 DAG.getIntPtrConstant(IncrementSize));
1859 // Load the rest of the low bits.
1860 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
1861 N->getPointerInfo().getWithOffset(IncrementSize),
1862 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1863 isVolatile, isNonTemporal,
1864 MinAlign(Alignment, IncrementSize));
1866 // Build a factor node to remember that this load is independent of the
1868 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1871 if (ExcessBits < NVT.getSizeInBits()) {
1872 // Transfer low bits from the bottom of Hi to the top of Lo.
1873 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1874 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1875 DAG.getConstant(ExcessBits,
1876 TLI.getPointerTy())));
1877 // Move high bits to the right position in Hi.
1878 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1880 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1881 TLI.getPointerTy()));
1885 // Legalized the chain result - switch anything that used the old chain to
1887 ReplaceValueWith(SDValue(N, 1), Ch);
1890 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1891 SDValue &Lo, SDValue &Hi) {
1892 DebugLoc dl = N->getDebugLoc();
1893 SDValue LL, LH, RL, RH;
1894 GetExpandedInteger(N->getOperand(0), LL, LH);
1895 GetExpandedInteger(N->getOperand(1), RL, RH);
1896 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1897 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1900 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1901 SDValue &Lo, SDValue &Hi) {
1902 EVT VT = N->getValueType(0);
1903 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1904 DebugLoc dl = N->getDebugLoc();
1906 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1907 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1908 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1909 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1910 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1911 SDValue LL, LH, RL, RH;
1912 GetExpandedInteger(N->getOperand(0), LL, LH);
1913 GetExpandedInteger(N->getOperand(1), RL, RH);
1914 unsigned OuterBitSize = VT.getSizeInBits();
1915 unsigned InnerBitSize = NVT.getSizeInBits();
1916 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1917 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1919 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1920 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1921 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1922 // The inputs are both zero-extended.
1924 // We can emit a umul_lohi.
1925 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1926 Hi = SDValue(Lo.getNode(), 1);
1930 // We can emit a mulhu+mul.
1931 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1932 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1936 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1937 // The input values are both sign-extended.
1939 // We can emit a smul_lohi.
1940 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1941 Hi = SDValue(Lo.getNode(), 1);
1945 // We can emit a mulhs+mul.
1946 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1947 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1952 // Lo,Hi = umul LHS, RHS.
1953 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1954 DAG.getVTList(NVT, NVT), LL, RL);
1956 Hi = UMulLOHI.getValue(1);
1957 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1958 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1959 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1960 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1964 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1965 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1966 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1967 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1968 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1969 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1974 // If nothing else, we can make a libcall.
1975 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1977 LC = RTLIB::MUL_I16;
1978 else if (VT == MVT::i32)
1979 LC = RTLIB::MUL_I32;
1980 else if (VT == MVT::i64)
1981 LC = RTLIB::MUL_I64;
1982 else if (VT == MVT::i128)
1983 LC = RTLIB::MUL_I128;
1984 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1986 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1987 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1990 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
1991 SDValue &Lo, SDValue &Hi) {
1992 SDValue LHS = Node->getOperand(0);
1993 SDValue RHS = Node->getOperand(1);
1994 DebugLoc dl = Node->getDebugLoc();
1996 // Expand the result by simply replacing it with the equivalent
1997 // non-overflow-checking operation.
1998 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
1999 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2001 SplitInteger(Sum, Lo, Hi);
2003 // Compute the overflow.
2005 // LHSSign -> LHS >= 0
2006 // RHSSign -> RHS >= 0
2007 // SumSign -> Sum >= 0
2010 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2012 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2014 EVT OType = Node->getValueType(1);
2015 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2017 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2018 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2019 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2020 Node->getOpcode() == ISD::SADDO ?
2021 ISD::SETEQ : ISD::SETNE);
2023 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2024 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2026 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2028 // Use the calculated overflow everywhere.
2029 ReplaceValueWith(SDValue(Node, 1), Cmp);
2032 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2033 SDValue &Lo, SDValue &Hi) {
2034 EVT VT = N->getValueType(0);
2035 DebugLoc dl = N->getDebugLoc();
2037 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2039 LC = RTLIB::SDIV_I16;
2040 else if (VT == MVT::i32)
2041 LC = RTLIB::SDIV_I32;
2042 else if (VT == MVT::i64)
2043 LC = RTLIB::SDIV_I64;
2044 else if (VT == MVT::i128)
2045 LC = RTLIB::SDIV_I128;
2046 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2048 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2049 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
2052 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2053 SDValue &Lo, SDValue &Hi) {
2054 EVT VT = N->getValueType(0);
2055 DebugLoc dl = N->getDebugLoc();
2057 // If we can emit an efficient shift operation, do so now. Check to see if
2058 // the RHS is a constant.
2059 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2060 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
2062 // If we can determine that the high bit of the shift is zero or one, even if
2063 // the low bits are variable, emit this shift in an optimized form.
2064 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2067 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2069 if (N->getOpcode() == ISD::SHL) {
2070 PartsOpc = ISD::SHL_PARTS;
2071 } else if (N->getOpcode() == ISD::SRL) {
2072 PartsOpc = ISD::SRL_PARTS;
2074 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2075 PartsOpc = ISD::SRA_PARTS;
2078 // Next check to see if the target supports this SHL_PARTS operation or if it
2079 // will custom expand it.
2080 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2081 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2082 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2083 Action == TargetLowering::Custom) {
2084 // Expand the subcomponents.
2086 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2088 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
2089 EVT VT = LHSL.getValueType();
2090 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
2091 Hi = Lo.getValue(1);
2095 // Otherwise, emit a libcall.
2096 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2098 if (N->getOpcode() == ISD::SHL) {
2099 isSigned = false; /*sign irrelevant*/
2101 LC = RTLIB::SHL_I16;
2102 else if (VT == MVT::i32)
2103 LC = RTLIB::SHL_I32;
2104 else if (VT == MVT::i64)
2105 LC = RTLIB::SHL_I64;
2106 else if (VT == MVT::i128)
2107 LC = RTLIB::SHL_I128;
2108 } else if (N->getOpcode() == ISD::SRL) {
2111 LC = RTLIB::SRL_I16;
2112 else if (VT == MVT::i32)
2113 LC = RTLIB::SRL_I32;
2114 else if (VT == MVT::i64)
2115 LC = RTLIB::SRL_I64;
2116 else if (VT == MVT::i128)
2117 LC = RTLIB::SRL_I128;
2119 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2122 LC = RTLIB::SRA_I16;
2123 else if (VT == MVT::i32)
2124 LC = RTLIB::SRA_I32;
2125 else if (VT == MVT::i64)
2126 LC = RTLIB::SRA_I64;
2127 else if (VT == MVT::i128)
2128 LC = RTLIB::SRA_I128;
2131 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2132 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2133 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
2137 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2138 llvm_unreachable("Unsupported shift!");
2141 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2142 SDValue &Lo, SDValue &Hi) {
2143 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2144 DebugLoc dl = N->getDebugLoc();
2145 SDValue Op = N->getOperand(0);
2146 if (Op.getValueType().bitsLE(NVT)) {
2147 // The low part is sign extension of the input (degenerates to a copy).
2148 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2149 // The high part is obtained by SRA'ing all but one of the bits of low part.
2150 unsigned LoSize = NVT.getSizeInBits();
2151 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2152 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
2154 // For example, extension of an i48 to an i64. The operand type necessarily
2155 // promotes to the result type, so will end up being expanded too.
2156 assert(getTypeAction(Op.getValueType()) ==
2157 TargetLowering::TypePromoteInteger &&
2158 "Only know how to promote this result!");
2159 SDValue Res = GetPromotedInteger(Op);
2160 assert(Res.getValueType() == N->getValueType(0) &&
2161 "Operand over promoted?");
2162 // Split the promoted operand. This will simplify when it is expanded.
2163 SplitInteger(Res, Lo, Hi);
2164 unsigned ExcessBits =
2165 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2166 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2167 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2172 void DAGTypeLegalizer::
2173 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2174 DebugLoc dl = N->getDebugLoc();
2175 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2176 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2178 if (EVT.bitsLE(Lo.getValueType())) {
2179 // sext_inreg the low part if needed.
2180 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2183 // The high part gets the sign extension from the lo-part. This handles
2184 // things like sextinreg V:i64 from i8.
2185 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2186 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
2187 TLI.getPointerTy()));
2189 // For example, extension of an i48 to an i64. Leave the low part alone,
2190 // sext_inreg the high part.
2191 unsigned ExcessBits =
2192 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2193 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2194 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2199 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2200 SDValue &Lo, SDValue &Hi) {
2201 EVT VT = N->getValueType(0);
2202 DebugLoc dl = N->getDebugLoc();
2204 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2206 LC = RTLIB::SREM_I16;
2207 else if (VT == MVT::i32)
2208 LC = RTLIB::SREM_I32;
2209 else if (VT == MVT::i64)
2210 LC = RTLIB::SREM_I64;
2211 else if (VT == MVT::i128)
2212 LC = RTLIB::SREM_I128;
2213 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2215 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2216 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
2219 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2220 SDValue &Lo, SDValue &Hi) {
2221 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2222 DebugLoc dl = N->getDebugLoc();
2223 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2224 Hi = DAG.getNode(ISD::SRL, dl,
2225 N->getOperand(0).getValueType(), N->getOperand(0),
2226 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
2227 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2230 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2231 SDValue &Lo, SDValue &Hi) {
2232 SDValue LHS = N->getOperand(0);
2233 SDValue RHS = N->getOperand(1);
2234 DebugLoc dl = N->getDebugLoc();
2236 // Expand the result by simply replacing it with the equivalent
2237 // non-overflow-checking operation.
2238 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2239 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2241 SplitInteger(Sum, Lo, Hi);
2243 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2244 // overflows iff a - b > a.
2245 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2246 N->getOpcode () == ISD::UADDO ?
2247 ISD::SETULT : ISD::SETUGT);
2249 // Use the calculated overflow everywhere.
2250 ReplaceValueWith(SDValue(N, 1), Ofl);
2253 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2254 SDValue &Lo, SDValue &Hi) {
2255 EVT VT = N->getValueType(0);
2256 DebugLoc dl = N->getDebugLoc();
2258 // A divide for UMULO should be faster than a function call.
2259 if (N->getOpcode() == ISD::UMULO) {
2260 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2262 SDValue MUL = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS);
2263 SplitInteger(MUL, Lo, Hi);
2265 // A divide for UMULO will be faster than a function call. Select to
2266 // make sure we aren't using 0.
2267 SDValue isZero = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2268 RHS, DAG.getConstant(0, VT), ISD::SETEQ);
2269 SDValue NotZero = DAG.getNode(ISD::SELECT, dl, VT, isZero,
2270 DAG.getConstant(1, VT), RHS);
2271 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero);
2272 SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS,
2274 Overflow = DAG.getNode(ISD::SELECT, dl, N->getValueType(1), isZero,
2275 DAG.getConstant(0, N->getValueType(1)),
2277 ReplaceValueWith(SDValue(N, 1), Overflow);
2281 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2282 EVT PtrVT = TLI.getPointerTy();
2283 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2285 // Replace this with a libcall that will check overflow.
2286 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2288 LC = RTLIB::MULO_I32;
2289 else if (VT == MVT::i64)
2290 LC = RTLIB::MULO_I64;
2291 else if (VT == MVT::i128)
2292 LC = RTLIB::MULO_I128;
2293 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2295 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2296 // Temporary for the overflow value, default it to zero.
2297 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2298 DAG.getConstant(0, PtrVT), Temp,
2299 MachinePointerInfo(), false, false, 0);
2301 TargetLowering::ArgListTy Args;
2302 TargetLowering::ArgListEntry Entry;
2303 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2304 EVT ArgVT = N->getOperand(i).getValueType();
2305 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2306 Entry.Node = N->getOperand(i);
2308 Entry.isSExt = true;
2309 Entry.isZExt = false;
2310 Args.push_back(Entry);
2313 // Also pass the address of the overflow check.
2315 Entry.Ty = PtrTy->getPointerTo();
2316 Entry.isSExt = true;
2317 Entry.isZExt = false;
2318 Args.push_back(Entry);
2320 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2322 CallLoweringInfo CLI(Chain, RetTy, true, false, false, false,
2323 0, TLI.getLibcallCallingConv(LC),
2324 /*isTailCall=*/false,
2325 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2326 Func, Args, DAG, dl);
2327 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2329 SplitInteger(CallInfo.first, Lo, Hi);
2330 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2331 MachinePointerInfo(), false, false, false, 0);
2332 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2333 DAG.getConstant(0, PtrVT),
2335 // Use the overflow from the libcall everywhere.
2336 ReplaceValueWith(SDValue(N, 1), Ofl);
2339 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2340 SDValue &Lo, SDValue &Hi) {
2341 EVT VT = N->getValueType(0);
2342 DebugLoc dl = N->getDebugLoc();
2344 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2346 LC = RTLIB::UDIV_I16;
2347 else if (VT == MVT::i32)
2348 LC = RTLIB::UDIV_I32;
2349 else if (VT == MVT::i64)
2350 LC = RTLIB::UDIV_I64;
2351 else if (VT == MVT::i128)
2352 LC = RTLIB::UDIV_I128;
2353 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2355 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2356 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2359 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2360 SDValue &Lo, SDValue &Hi) {
2361 EVT VT = N->getValueType(0);
2362 DebugLoc dl = N->getDebugLoc();
2364 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2366 LC = RTLIB::UREM_I16;
2367 else if (VT == MVT::i32)
2368 LC = RTLIB::UREM_I32;
2369 else if (VT == MVT::i64)
2370 LC = RTLIB::UREM_I64;
2371 else if (VT == MVT::i128)
2372 LC = RTLIB::UREM_I128;
2373 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2375 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2376 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2379 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2380 SDValue &Lo, SDValue &Hi) {
2381 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2382 DebugLoc dl = N->getDebugLoc();
2383 SDValue Op = N->getOperand(0);
2384 if (Op.getValueType().bitsLE(NVT)) {
2385 // The low part is zero extension of the input (degenerates to a copy).
2386 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2387 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2389 // For example, extension of an i48 to an i64. The operand type necessarily
2390 // promotes to the result type, so will end up being expanded too.
2391 assert(getTypeAction(Op.getValueType()) ==
2392 TargetLowering::TypePromoteInteger &&
2393 "Only know how to promote this result!");
2394 SDValue Res = GetPromotedInteger(Op);
2395 assert(Res.getValueType() == N->getValueType(0) &&
2396 "Operand over promoted?");
2397 // Split the promoted operand. This will simplify when it is expanded.
2398 SplitInteger(Res, Lo, Hi);
2399 unsigned ExcessBits =
2400 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2401 Hi = DAG.getZeroExtendInReg(Hi, dl,
2402 EVT::getIntegerVT(*DAG.getContext(),
2407 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
2408 SDValue &Lo, SDValue &Hi) {
2409 DebugLoc dl = N->getDebugLoc();
2410 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
2411 SDValue Zero = DAG.getConstant(0, VT);
2412 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
2414 N->getOperand(1), Zero, Zero,
2415 cast<AtomicSDNode>(N)->getMemOperand(),
2416 cast<AtomicSDNode>(N)->getOrdering(),
2417 cast<AtomicSDNode>(N)->getSynchScope());
2418 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2419 ReplaceValueWith(SDValue(N, 1), Swap.getValue(1));
2422 //===----------------------------------------------------------------------===//
2423 // Integer Operand Expansion
2424 //===----------------------------------------------------------------------===//
2426 /// ExpandIntegerOperand - This method is called when the specified operand of
2427 /// the specified node is found to need expansion. At this point, all of the
2428 /// result types of the node are known to be legal, but other operands of the
2429 /// node may need promotion or expansion as well as the specified one.
2430 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2431 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2432 SDValue Res = SDValue();
2434 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2437 switch (N->getOpcode()) {
2440 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2441 N->dump(&DAG); dbgs() << "\n";
2443 llvm_unreachable("Do not know how to expand this operator's operand!");
2445 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2446 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2447 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2448 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2449 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2450 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2451 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2452 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2453 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2454 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2455 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2456 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2462 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2463 case ISD::RETURNADDR:
2464 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2466 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2469 // If the result is null, the sub-method took care of registering results etc.
2470 if (!Res.getNode()) return false;
2472 // If the result is N, the sub-method updated N in place. Tell the legalizer
2474 if (Res.getNode() == N)
2477 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2478 "Invalid operand expansion");
2480 ReplaceValueWith(SDValue(N, 0), Res);
2484 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2485 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2486 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2488 ISD::CondCode &CCCode,
2490 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2491 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2492 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2494 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2495 if (RHSLo == RHSHi) {
2496 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2497 if (RHSCST->isAllOnesValue()) {
2498 // Equality comparison to -1.
2499 NewLHS = DAG.getNode(ISD::AND, dl,
2500 LHSLo.getValueType(), LHSLo, LHSHi);
2507 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2508 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2509 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2510 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2514 // If this is a comparison of the sign bit, just look at the top part.
2516 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2517 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2518 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2524 // FIXME: This generated code sucks.
2525 ISD::CondCode LowCC;
2527 default: llvm_unreachable("Unknown integer setcc!");
2529 case ISD::SETULT: LowCC = ISD::SETULT; break;
2531 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2533 case ISD::SETULE: LowCC = ISD::SETULE; break;
2535 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2538 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2539 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2540 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2542 // NOTE: on targets without efficient SELECT of bools, we can always use
2543 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2544 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL);
2546 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2547 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2548 if (!Tmp1.getNode())
2549 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2550 LHSLo, RHSLo, LowCC);
2551 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2552 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2553 if (!Tmp2.getNode())
2554 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2555 TLI.getSetCCResultType(LHSHi.getValueType()),
2556 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2558 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2559 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2560 if ((Tmp1C && Tmp1C->isNullValue()) ||
2561 (Tmp2C && Tmp2C->isNullValue() &&
2562 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2563 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2564 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2565 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2566 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2567 // low part is known false, returns high part.
2568 // For LE / GE, if high part is known false, ignore the low part.
2569 // For LT / GT, if high part is known true, ignore the low part.
2575 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2576 LHSHi, RHSHi, ISD::SETEQ, false,
2577 DagCombineInfo, dl);
2578 if (!NewLHS.getNode())
2579 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2580 LHSHi, RHSHi, ISD::SETEQ);
2581 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2582 NewLHS, Tmp1, Tmp2);
2586 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2587 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2588 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2589 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2591 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2592 // against zero to select between true and false values.
2593 if (NewRHS.getNode() == 0) {
2594 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2595 CCCode = ISD::SETNE;
2598 // Update N to have the operands specified.
2599 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2600 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2601 N->getOperand(4)), 0);
2604 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2605 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2606 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2607 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2609 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2610 // against zero to select between true and false values.
2611 if (NewRHS.getNode() == 0) {
2612 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2613 CCCode = ISD::SETNE;
2616 // Update N to have the operands specified.
2617 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2618 N->getOperand(2), N->getOperand(3),
2619 DAG.getCondCode(CCCode)), 0);
2622 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2623 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2624 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2625 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2627 // If ExpandSetCCOperands returned a scalar, use it.
2628 if (NewRHS.getNode() == 0) {
2629 assert(NewLHS.getValueType() == N->getValueType(0) &&
2630 "Unexpected setcc expansion!");
2634 // Otherwise, update N to have the operands specified.
2635 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2636 DAG.getCondCode(CCCode)), 0);
2639 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2640 // The value being shifted is legal, but the shift amount is too big.
2641 // It follows that either the result of the shift is undefined, or the
2642 // upper half of the shift amount is zero. Just use the lower half.
2644 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2645 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2648 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2649 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2650 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2651 // constant to valid type.
2653 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2654 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2657 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2658 SDValue Op = N->getOperand(0);
2659 EVT DstVT = N->getValueType(0);
2660 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2661 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2662 "Don't know how to expand this SINT_TO_FP!");
2663 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2666 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2667 if (ISD::isNormalStore(N))
2668 return ExpandOp_NormalStore(N, OpNo);
2670 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2671 assert(OpNo == 1 && "Can only expand the stored value so far");
2673 EVT VT = N->getOperand(1).getValueType();
2674 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2675 SDValue Ch = N->getChain();
2676 SDValue Ptr = N->getBasePtr();
2677 unsigned Alignment = N->getAlignment();
2678 bool isVolatile = N->isVolatile();
2679 bool isNonTemporal = N->isNonTemporal();
2680 DebugLoc dl = N->getDebugLoc();
2683 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2685 if (N->getMemoryVT().bitsLE(NVT)) {
2686 GetExpandedInteger(N->getValue(), Lo, Hi);
2687 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2688 N->getMemoryVT(), isVolatile, isNonTemporal,
2692 if (TLI.isLittleEndian()) {
2693 // Little-endian - low bits are at low addresses.
2694 GetExpandedInteger(N->getValue(), Lo, Hi);
2696 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2697 isVolatile, isNonTemporal, Alignment);
2699 unsigned ExcessBits =
2700 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2701 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2703 // Increment the pointer to the other half.
2704 unsigned IncrementSize = NVT.getSizeInBits()/8;
2705 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2706 DAG.getIntPtrConstant(IncrementSize));
2707 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2708 N->getPointerInfo().getWithOffset(IncrementSize),
2709 NEVT, isVolatile, isNonTemporal,
2710 MinAlign(Alignment, IncrementSize));
2711 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2714 // Big-endian - high bits are at low addresses. Favor aligned stores at
2715 // the cost of some bit-fiddling.
2716 GetExpandedInteger(N->getValue(), Lo, Hi);
2718 EVT ExtVT = N->getMemoryVT();
2719 unsigned EBytes = ExtVT.getStoreSize();
2720 unsigned IncrementSize = NVT.getSizeInBits()/8;
2721 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2722 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2723 ExtVT.getSizeInBits() - ExcessBits);
2725 if (ExcessBits < NVT.getSizeInBits()) {
2726 // Transfer high bits from the top of Lo to the bottom of Hi.
2727 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2728 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2729 TLI.getPointerTy()));
2730 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2731 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2732 DAG.getConstant(ExcessBits,
2733 TLI.getPointerTy())));
2736 // Store both the high bits and maybe some of the low bits.
2737 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2738 HiVT, isVolatile, isNonTemporal, Alignment);
2740 // Increment the pointer to the other half.
2741 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2742 DAG.getIntPtrConstant(IncrementSize));
2743 // Store the lowest ExcessBits bits in the second half.
2744 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2745 N->getPointerInfo().getWithOffset(IncrementSize),
2746 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2747 isVolatile, isNonTemporal,
2748 MinAlign(Alignment, IncrementSize));
2749 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2752 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2754 GetExpandedInteger(N->getOperand(0), InL, InH);
2755 // Just truncate the low part of the source.
2756 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2759 static const fltSemantics *EVTToAPFloatSemantics(EVT VT) {
2760 switch (VT.getSimpleVT().SimpleTy) {
2761 default: llvm_unreachable("Unknown FP format");
2762 case MVT::f32: return &APFloat::IEEEsingle;
2763 case MVT::f64: return &APFloat::IEEEdouble;
2764 case MVT::f80: return &APFloat::x87DoubleExtended;
2765 case MVT::f128: return &APFloat::IEEEquad;
2766 case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
2770 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2771 SDValue Op = N->getOperand(0);
2772 EVT SrcVT = Op.getValueType();
2773 EVT DstVT = N->getValueType(0);
2774 DebugLoc dl = N->getDebugLoc();
2776 // The following optimization is valid only if every value in SrcVT (when
2777 // treated as signed) is representable in DstVT. Check that the mantissa
2778 // size of DstVT is >= than the number of bits in SrcVT -1.
2779 const fltSemantics *sem = EVTToAPFloatSemantics(DstVT);
2780 if (APFloat::semanticsPrecision(*sem) >= SrcVT.getSizeInBits()-1 &&
2781 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2782 // Do a signed conversion then adjust the result.
2783 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2784 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2786 // The result of the signed conversion needs adjusting if the 'sign bit' of
2787 // the incoming integer was set. To handle this, we dynamically test to see
2788 // if it is set, and, if so, add a fudge factor.
2790 const uint64_t F32TwoE32 = 0x4F800000ULL;
2791 const uint64_t F32TwoE64 = 0x5F800000ULL;
2792 const uint64_t F32TwoE128 = 0x7F800000ULL;
2795 if (SrcVT == MVT::i32)
2796 FF = APInt(32, F32TwoE32);
2797 else if (SrcVT == MVT::i64)
2798 FF = APInt(32, F32TwoE64);
2799 else if (SrcVT == MVT::i128)
2800 FF = APInt(32, F32TwoE128);
2802 llvm_unreachable("Unsupported UINT_TO_FP!");
2804 // Check whether the sign bit is set.
2806 GetExpandedInteger(Op, Lo, Hi);
2807 SDValue SignSet = DAG.getSetCC(dl,
2808 TLI.getSetCCResultType(Hi.getValueType()),
2809 Hi, DAG.getConstant(0, Hi.getValueType()),
2812 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2813 SDValue FudgePtr = DAG.getConstantPool(
2814 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2815 TLI.getPointerTy());
2817 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2818 SDValue Zero = DAG.getIntPtrConstant(0);
2819 SDValue Four = DAG.getIntPtrConstant(4);
2820 if (TLI.isBigEndian()) std::swap(Zero, Four);
2821 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2823 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2824 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2825 Alignment = std::min(Alignment, 4u);
2827 // Load the value out, extending it from f32 to the destination float type.
2828 // FIXME: Avoid the extend by constructing the right constant pool?
2829 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2831 MachinePointerInfo::getConstantPool(),
2833 false, false, Alignment);
2834 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2837 // Otherwise, use a libcall.
2838 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2839 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2840 "Don't know how to expand this UINT_TO_FP!");
2841 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);
2844 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
2845 DebugLoc dl = N->getDebugLoc();
2846 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2847 cast<AtomicSDNode>(N)->getMemoryVT(),
2849 N->getOperand(1), N->getOperand(2),
2850 cast<AtomicSDNode>(N)->getMemOperand(),
2851 cast<AtomicSDNode>(N)->getOrdering(),
2852 cast<AtomicSDNode>(N)->getSynchScope());
2853 return Swap.getValue(1);
2857 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
2858 SDValue InOp0 = N->getOperand(0);
2859 EVT InVT = InOp0.getValueType();
2861 EVT OutVT = N->getValueType(0);
2862 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2863 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2864 unsigned OutNumElems = OutVT.getVectorNumElements();
2865 EVT NOutVTElem = NOutVT.getVectorElementType();
2867 DebugLoc dl = N->getDebugLoc();
2868 SDValue BaseIdx = N->getOperand(1);
2870 SmallVector<SDValue, 8> Ops;
2871 Ops.reserve(OutNumElems);
2872 for (unsigned i = 0; i != OutNumElems; ++i) {
2874 // Extract the element from the original vector.
2875 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
2876 BaseIdx, DAG.getIntPtrConstant(i));
2877 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2878 InVT.getVectorElementType(), N->getOperand(0), Index);
2880 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
2881 // Insert the converted element to the new vector.
2885 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2889 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
2890 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
2891 EVT VT = N->getValueType(0);
2892 DebugLoc dl = N->getDebugLoc();
2894 unsigned NumElts = VT.getVectorNumElements();
2895 SmallVector<int, 8> NewMask;
2896 for (unsigned i = 0; i != NumElts; ++i) {
2897 NewMask.push_back(SV->getMaskElt(i));
2900 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2901 SDValue V1 = GetPromotedInteger(N->getOperand(1));
2902 EVT OutVT = V0.getValueType();
2904 return DAG.getVectorShuffle(OutVT, dl, V0, V1, &NewMask[0]);
2908 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
2909 EVT OutVT = N->getValueType(0);
2910 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2911 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2912 unsigned NumElems = N->getNumOperands();
2913 EVT NOutVTElem = NOutVT.getVectorElementType();
2915 DebugLoc dl = N->getDebugLoc();
2917 SmallVector<SDValue, 8> Ops;
2918 Ops.reserve(NumElems);
2919 for (unsigned i = 0; i != NumElems; ++i) {
2920 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
2924 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2927 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
2929 DebugLoc dl = N->getDebugLoc();
2931 assert(!N->getOperand(0).getValueType().isVector() &&
2932 "Input must be a scalar");
2934 EVT OutVT = N->getValueType(0);
2935 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2936 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2937 EVT NOutVTElem = NOutVT.getVectorElementType();
2939 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
2941 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
2944 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
2945 DebugLoc dl = N->getDebugLoc();
2947 EVT OutVT = N->getValueType(0);
2948 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2949 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2951 EVT InElemTy = OutVT.getVectorElementType();
2952 EVT OutElemTy = NOutVT.getVectorElementType();
2954 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
2955 unsigned NumOutElem = NOutVT.getVectorNumElements();
2956 unsigned NumOperands = N->getNumOperands();
2957 assert(NumElem * NumOperands == NumOutElem &&
2958 "Unexpected number of elements");
2960 // Take the elements from the first vector.
2961 SmallVector<SDValue, 8> Ops(NumOutElem);
2962 for (unsigned i = 0; i < NumOperands; ++i) {
2963 SDValue Op = N->getOperand(i);
2964 for (unsigned j = 0; j < NumElem; ++j) {
2965 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2966 InElemTy, Op, DAG.getIntPtrConstant(j));
2967 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
2971 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2974 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
2975 EVT OutVT = N->getValueType(0);
2976 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2977 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2979 EVT NOutVTElem = NOutVT.getVectorElementType();
2981 DebugLoc dl = N->getDebugLoc();
2982 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2984 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
2985 NOutVTElem, N->getOperand(1));
2986 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
2987 V0, ConvElem, N->getOperand(2));
2990 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2991 DebugLoc dl = N->getDebugLoc();
2992 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2993 SDValue V1 = N->getOperand(1);
2994 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2995 V0->getValueType(0).getScalarType(), V0, V1);
2997 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
2998 // element types. If this is the case then we need to expand the outgoing
2999 // value and not truncate it.
3000 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
3003 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
3004 DebugLoc dl = N->getDebugLoc();
3005 unsigned NumElems = N->getNumOperands();
3007 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
3009 SmallVector<SDValue, 8> NewOps;
3010 NewOps.reserve(NumElems);
3012 // For each incoming vector
3013 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3014 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
3015 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
3016 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
3018 for (unsigned i=0; i<NumElem; ++i) {
3019 // Extract element from incoming vector
3020 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy,
3021 Incoming, DAG.getIntPtrConstant(i));
3022 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3023 NewOps.push_back(Tr);
3027 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0),
3028 &NewOps[0], NewOps.size());