1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/Constants.h"
25 //===----------------------------------------------------------------------===//
26 // Integer Result Promotion
27 //===----------------------------------------------------------------------===//
29 /// PromoteIntegerResult - This method is called when a result of a node is
30 /// found to be in need of promotion to a larger type. At this point, the node
31 /// may also have invalid operands or may have other results that need
32 /// expansion, we just know that (at least) one result needs promotion.
33 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
34 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
35 SDOperand Result = SDOperand();
37 switch (N->getOpcode()) {
40 cerr << "PromoteIntegerResult #" << ResNo << ": ";
41 N->dump(&DAG); cerr << "\n";
43 assert(0 && "Do not know how to promote this operator!");
45 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break;
46 case ISD::Constant: Result = PromoteIntRes_Constant(N); break;
48 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break;
49 case ISD::SIGN_EXTEND:
50 case ISD::ZERO_EXTEND:
51 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break;
52 case ISD::FP_ROUND: Result = PromoteIntRes_FP_ROUND(N); break;
54 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break;
55 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break;
56 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N)); break;
57 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break;
58 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break;
65 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break;
68 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break;
71 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break;
73 case ISD::SHL: Result = PromoteIntRes_SHL(N); break;
74 case ISD::SRA: Result = PromoteIntRes_SRA(N); break;
75 case ISD::SRL: Result = PromoteIntRes_SRL(N); break;
77 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break;
78 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break;
80 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break;
81 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break;
82 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break;
84 case ISD::EXTRACT_VECTOR_ELT:
85 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N);
89 // If Result is null, the sub-method took care of registering the result.
91 SetPromotedInteger(SDOperand(N, ResNo), Result);
94 SDOperand DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
95 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
98 SDOperand DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
99 MVT VT = N->getValueType(0);
100 // Zero extend things like i1, sign extend everything else. It shouldn't
101 // matter in theory which one we pick, but this tends to give better code?
102 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
103 SDOperand Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
105 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
109 SDOperand DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
112 switch (getTypeAction(N->getOperand(0).getValueType())) {
113 default: assert(0 && "Unknown type action!");
116 Res = N->getOperand(0);
119 Res = GetPromotedInteger(N->getOperand(0));
123 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
124 assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() &&
125 "Truncation doesn't make sense!");
126 if (Res.getValueType() == NVT)
129 // Truncate to NVT instead of VT
130 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
133 SDOperand DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
134 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
136 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
137 SDOperand Res = GetPromotedInteger(N->getOperand(0));
138 assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() &&
139 "Extension doesn't make sense!");
141 // If the result and operand types are the same after promotion, simplify
142 // to an in-register extension.
143 if (NVT == Res.getValueType()) {
144 // The high bits are not guaranteed to be anything. Insert an extend.
145 if (N->getOpcode() == ISD::SIGN_EXTEND)
146 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
147 DAG.getValueType(N->getOperand(0).getValueType()));
148 if (N->getOpcode() == ISD::ZERO_EXTEND)
149 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
150 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
155 // Otherwise, just extend the original operand all the way to the larger type.
156 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
159 SDOperand DAGTypeLegalizer::PromoteIntRes_FP_ROUND(SDNode *N) {
160 // NOTE: Assumes input is legal.
161 if (N->getConstantOperandVal(1) == 0)
162 return DAG.getNode(ISD::FP_ROUND_INREG, N->getOperand(0).getValueType(),
163 N->getOperand(0), DAG.getValueType(N->getValueType(0)));
164 // If the precision discard isn't needed, just return the operand unrounded.
165 return N->getOperand(0);
168 SDOperand DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
169 unsigned NewOpc = N->getOpcode();
170 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
172 // If we're promoting a UINT to a larger size, check to see if the new node
173 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
174 // we can use that instead. This allows us to generate better code for
175 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
176 // legal, such as PowerPC.
177 if (N->getOpcode() == ISD::FP_TO_UINT) {
178 if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
179 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
180 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom))
181 NewOpc = ISD::FP_TO_SINT;
184 return DAG.getNode(NewOpc, NVT, N->getOperand(0));
187 SDOperand DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
188 assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0)))
189 && "SetCC type is not legal??");
190 return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)),
191 N->getOperand(0), N->getOperand(1), N->getOperand(2));
194 SDOperand DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
195 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
196 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
197 ISD::LoadExtType ExtType =
198 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
199 SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
200 N->getSrcValue(), N->getSrcValueOffset(),
201 N->getMemoryVT(), N->isVolatile(),
204 // Legalized the chain result - switch anything that used the old chain to
206 ReplaceValueWith(SDOperand(N, 1), Res.getValue(1));
210 SDOperand DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
211 // The pair element type may be legal, or may not promote to the same type as
212 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
213 return DAG.getNode(ISD::ANY_EXTEND,
214 TLI.getTypeToTransformTo(N->getValueType(0)),
215 JoinIntegers(N->getOperand(0), N->getOperand(1)));
218 SDOperand DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
219 SDOperand InOp = N->getOperand(0);
220 MVT InVT = InOp.getValueType();
221 MVT NInVT = TLI.getTypeToTransformTo(InVT);
222 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
224 switch (getTypeAction(InVT)) {
226 assert(false && "Unknown type action!");
231 if (OutVT.getSizeInBits() == NInVT.getSizeInBits())
232 // The input promotes to the same size. Convert the promoted value.
233 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp));
236 // Promote the integer operand by hand.
237 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp));
242 // Convert the element to an integer and promote it by hand.
243 return DAG.getNode(ISD::ANY_EXTEND, OutVT,
244 BitConvertToInteger(GetScalarizedVector(InOp)));
246 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
247 // pieces of the input into integers and reassemble in the final type.
249 GetSplitVector(N->getOperand(0), Lo, Hi);
250 Lo = BitConvertToInteger(Lo);
251 Hi = BitConvertToInteger(Hi);
253 if (TLI.isBigEndian())
256 InOp = DAG.getNode(ISD::ANY_EXTEND,
257 MVT::getIntegerVT(OutVT.getSizeInBits()),
258 JoinIntegers(Lo, Hi));
259 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp);
262 // Otherwise, lower the bit-convert to a store/load from the stack, then
264 SDOperand Op = CreateStackStoreLoad(InOp, N->getValueType(0));
265 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.Val));
268 SDOperand DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
269 // The input may have strange things in the top bits of the registers, but
270 // these operations don't care. They may have weird bits going out, but
271 // that too is okay if they are integer operations.
272 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
273 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
274 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
277 SDOperand DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
278 // Sign extend the input.
279 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
280 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
281 MVT VT = N->getValueType(0);
282 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
283 DAG.getValueType(VT));
284 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
285 DAG.getValueType(VT));
287 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
290 SDOperand DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
291 // Zero extend the input.
292 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
293 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
294 MVT VT = N->getValueType(0);
295 LHS = DAG.getZeroExtendInReg(LHS, VT);
296 RHS = DAG.getZeroExtendInReg(RHS, VT);
298 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
301 SDOperand DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
302 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
303 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
306 SDOperand DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
307 // The input value must be properly sign extended.
308 MVT VT = N->getValueType(0);
309 MVT NVT = TLI.getTypeToTransformTo(VT);
310 SDOperand Res = GetPromotedInteger(N->getOperand(0));
311 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT));
312 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1));
315 SDOperand DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
316 // The input value must be properly zero extended.
317 MVT VT = N->getValueType(0);
318 MVT NVT = TLI.getTypeToTransformTo(VT);
319 SDOperand Res = ZExtPromotedInteger(N->getOperand(0));
320 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
323 SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
324 SDOperand LHS = GetPromotedInteger(N->getOperand(1));
325 SDOperand RHS = GetPromotedInteger(N->getOperand(2));
326 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
329 SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
330 SDOperand LHS = GetPromotedInteger(N->getOperand(2));
331 SDOperand RHS = GetPromotedInteger(N->getOperand(3));
332 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
333 N->getOperand(1), LHS, RHS, N->getOperand(4));
336 SDOperand DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
337 SDOperand Op = GetPromotedInteger(N->getOperand(0));
338 MVT OVT = N->getValueType(0);
339 MVT NVT = Op.getValueType();
340 // Zero extend to the promoted type and do the count there.
341 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT));
342 // Subtract off the extra leading bits in the bigger type.
343 return DAG.getNode(ISD::SUB, NVT, Op,
344 DAG.getConstant(NVT.getSizeInBits() -
345 OVT.getSizeInBits(), NVT));
348 SDOperand DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
349 SDOperand Op = GetPromotedInteger(N->getOperand(0));
350 MVT OVT = N->getValueType(0);
351 MVT NVT = Op.getValueType();
352 // Zero extend to the promoted type and do the count there.
353 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT));
356 SDOperand DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
357 SDOperand Op = GetPromotedInteger(N->getOperand(0));
358 MVT OVT = N->getValueType(0);
359 MVT NVT = Op.getValueType();
360 // The count is the same in the promoted type except if the original
361 // value was zero. This can be handled by setting the bit just off
362 // the top of the original type.
363 Op = DAG.getNode(ISD::OR, NVT, Op,
364 // FIXME: Do this using an APINT constant.
365 DAG.getConstant(1UL << OVT.getSizeInBits(), NVT));
366 return DAG.getNode(ISD::CTTZ, NVT, Op);
369 SDOperand DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
370 MVT OldVT = N->getValueType(0);
371 SDOperand OldVec = N->getOperand(0);
372 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
375 assert(!isTypeLegal(OldVec.getValueType()) &&
376 "Legal one-element vector of a type needing promotion!");
377 // It is tempting to follow GetScalarizedVector by a call to
378 // GetPromotedInteger, but this would be wrong because the
379 // scalarized value may not yet have been processed.
380 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT),
381 GetScalarizedVector(OldVec));
384 // Convert to a vector half as long with an element type of twice the width,
385 // for example <4 x i16> -> <2 x i32>.
386 assert(!(OldElts & 1) && "Odd length vectors not supported!");
387 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
388 assert(OldVT.isSimple() && NewVT.isSimple());
390 SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT,
391 MVT::getVectorVT(NewVT, OldElts / 2),
394 // Extract the element at OldIdx / 2 from the new vector.
395 SDOperand OldIdx = N->getOperand(1);
396 SDOperand NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
397 DAG.getConstant(1, TLI.getShiftAmountTy()));
398 SDOperand Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
400 // Select the appropriate half of the element: Lo if OldIdx was even,
403 SDOperand Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
404 DAG.getConstant(OldVT.getSizeInBits(),
405 TLI.getShiftAmountTy()));
406 if (TLI.isBigEndian())
409 SDOperand Odd = DAG.getNode(ISD::AND, OldIdx.getValueType(), OldIdx,
410 DAG.getConstant(1, TLI.getShiftAmountTy()));
411 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
414 //===----------------------------------------------------------------------===//
415 // Integer Operand Promotion
416 //===----------------------------------------------------------------------===//
418 /// PromoteIntegerOperand - This method is called when the specified operand of
419 /// the specified node is found to need promotion. At this point, all of the
420 /// result types of the node are known to be legal, but other operands of the
421 /// node may need promotion or expansion as well as the specified one.
422 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
423 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
425 switch (N->getOpcode()) {
428 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
429 N->dump(&DAG); cerr << "\n";
431 assert(0 && "Do not know how to promote this operator's operand!");
434 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
435 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
436 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
437 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
438 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break;
439 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break;
440 case ISD::SINT_TO_FP:
441 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break;
442 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
444 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
445 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
446 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
447 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
449 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
452 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
453 case ISD::INSERT_VECTOR_ELT:
454 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);
457 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
460 // If the result is null, the sub-method took care of registering results etc.
461 if (!Res.Val) return false;
462 // If the result is N, the sub-method updated N in place.
464 // Mark N as new and remark N and its operands. This allows us to correctly
465 // revisit N if it needs another step of promotion and allows us to visit
466 // any new operands to N.
471 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
472 "Invalid operand expansion");
474 ReplaceValueWith(SDOperand(N, 0), Res);
478 SDOperand DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
479 SDOperand Op = GetPromotedInteger(N->getOperand(0));
480 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
483 SDOperand DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
484 SDOperand Op = GetPromotedInteger(N->getOperand(0));
485 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
486 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
489 SDOperand DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
490 SDOperand Op = GetPromotedInteger(N->getOperand(0));
491 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
492 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
493 Op, DAG.getValueType(N->getOperand(0).getValueType()));
496 SDOperand DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
497 SDOperand Op = GetPromotedInteger(N->getOperand(0));
498 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
501 SDOperand DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) {
502 SDOperand Op = GetPromotedInteger(N->getOperand(0));
503 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op);
506 SDOperand DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) {
507 SDOperand Op = GetPromotedInteger(N->getOperand(0));
508 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op,
509 DAG.getIntPtrConstant(0));
512 SDOperand DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) {
513 SDOperand In = GetPromotedInteger(N->getOperand(0));
514 MVT OpVT = N->getOperand(0).getValueType();
515 if (N->getOpcode() == ISD::UINT_TO_FP)
516 In = DAG.getZeroExtendInReg(In, OpVT);
518 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(),
519 In, DAG.getValueType(OpVT));
521 return DAG.UpdateNodeOperands(SDOperand(N, 0), In);
524 SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
525 // Since the result type is legal, the operands must promote to it.
526 MVT OVT = N->getOperand(0).getValueType();
527 SDOperand Lo = GetPromotedInteger(N->getOperand(0));
528 SDOperand Hi = GetPromotedInteger(N->getOperand(1));
529 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
531 Lo = DAG.getZeroExtendInReg(Lo, OVT);
532 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
533 DAG.getConstant(OVT.getSizeInBits(),
534 TLI.getShiftAmountTy()));
535 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
538 SDOperand DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
539 assert(OpNo == 0 && "Only know how to promote condition");
540 SDOperand Cond = GetPromotedInteger(N->getOperand(0)); // Promote condition.
542 // The top bits of the promoted condition are not necessarily zero, ensure
543 // that the value is properly zero extended.
544 unsigned BitWidth = Cond.getValueSizeInBits();
545 if (!DAG.MaskedValueIsZero(Cond,
546 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
547 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
549 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
550 return DAG.UpdateNodeOperands(SDOperand(N, 0), Cond, N->getOperand(1),
554 SDOperand DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
555 assert(OpNo == 1 && "only know how to promote condition");
556 SDOperand Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition.
558 // The top bits of the promoted condition are not necessarily zero, ensure
559 // that the value is properly zero extended.
560 unsigned BitWidth = Cond.getValueSizeInBits();
561 if (!DAG.MaskedValueIsZero(Cond,
562 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
563 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
565 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
566 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), Cond,
570 SDOperand DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
571 assert(OpNo == 2 && "Don't know how to promote this operand");
573 SDOperand LHS = N->getOperand(2);
574 SDOperand RHS = N->getOperand(3);
575 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
577 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
579 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
580 N->getOperand(1), LHS, RHS, N->getOperand(4));
583 SDOperand DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
584 assert(OpNo == 0 && "Don't know how to promote this operand");
586 SDOperand LHS = N->getOperand(0);
587 SDOperand RHS = N->getOperand(1);
588 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
590 // The CC (#2) is always legal.
591 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2));
594 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
595 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
596 void DAGTypeLegalizer::PromoteSetCCOperands(SDOperand &NewLHS,SDOperand &NewRHS,
597 ISD::CondCode CCCode) {
598 MVT VT = NewLHS.getValueType();
600 // Get the promoted values.
601 NewLHS = GetPromotedInteger(NewLHS);
602 NewRHS = GetPromotedInteger(NewRHS);
604 // If this is an FP compare, the operands have already been extended.
605 if (!NewLHS.getValueType().isInteger())
608 // Otherwise, we have to insert explicit sign or zero extends. Note
609 // that we could insert sign extends for ALL conditions, but zero extend
610 // is cheaper on many machines (an AND instead of two shifts), so prefer
613 default: assert(0 && "Unknown integer comparison!");
620 // ALL of these operations will work if we either sign or zero extend
621 // the operands (including the unsigned comparisons!). Zero extend is
622 // usually a simpler/cheaper operation, so prefer it.
623 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT);
624 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT);
630 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS,
631 DAG.getValueType(VT));
632 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS,
633 DAG.getValueType(VT));
638 SDOperand DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
639 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
640 SDOperand Ch = N->getChain(), Ptr = N->getBasePtr();
641 int SVOffset = N->getSrcValueOffset();
642 unsigned Alignment = N->getAlignment();
643 bool isVolatile = N->isVolatile();
645 SDOperand Val = GetPromotedInteger(N->getValue()); // Get promoted value.
647 assert(!N->isTruncatingStore() && "Cannot promote this store operand!");
649 // Truncate the value and store the result.
650 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
651 SVOffset, N->getMemoryVT(),
652 isVolatile, Alignment);
655 SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
656 // The vector type is legal but the element type is not. This implies
657 // that the vector is a power-of-two in length and that the element
658 // type does not have a strange size (eg: it is not i1).
659 MVT VecVT = N->getValueType(0);
660 unsigned NumElts = VecVT.getVectorNumElements();
661 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
663 // Build a vector of half the length out of elements of twice the bitwidth.
664 // For example <4 x i16> -> <2 x i32>.
665 MVT OldVT = N->getOperand(0).getValueType();
666 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
667 assert(OldVT.isSimple() && NewVT.isSimple());
669 std::vector<SDOperand> NewElts;
670 NewElts.reserve(NumElts/2);
672 for (unsigned i = 0; i < NumElts; i += 2) {
673 // Combine two successive elements into one promoted element.
674 SDOperand Lo = N->getOperand(i);
675 SDOperand Hi = N->getOperand(i+1);
676 if (TLI.isBigEndian())
678 NewElts.push_back(JoinIntegers(Lo, Hi));
681 SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR,
682 MVT::getVectorVT(NewVT, NewElts.size()),
683 &NewElts[0], NewElts.size());
685 // Convert the new vector to the old vector type.
686 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
689 SDOperand DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
692 // Promote the inserted value. This is valid because the type does not
693 // have to match the vector element type.
695 // Check that any extra bits introduced will be truncated away.
696 assert(N->getOperand(1).getValueType().getSizeInBits() >=
697 N->getValueType(0).getVectorElementType().getSizeInBits() &&
698 "Type of inserted value narrower than vector element type!");
699 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
700 GetPromotedInteger(N->getOperand(1)),
704 assert(OpNo == 2 && "Different operand and result vector types?");
706 // Promote the index.
707 SDOperand Idx = N->getOperand(2);
708 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType());
709 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
710 N->getOperand(1), Idx);
713 SDOperand DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
715 NewOps[0] = N->getOperand(0);
716 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
717 SDOperand Flag = GetPromotedInteger(N->getOperand(i));
718 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
720 return DAG.UpdateNodeOperands(SDOperand (N, 0), NewOps,
721 array_lengthof(NewOps));
725 //===----------------------------------------------------------------------===//
726 // Integer Result Expansion
727 //===----------------------------------------------------------------------===//
729 /// ExpandIntegerResult - This method is called when the specified result of the
730 /// specified node is found to need expansion. At this point, the node may also
731 /// have invalid operands or may have other results that need promotion, we just
732 /// know that (at least) one result needs expansion.
733 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
734 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
736 Lo = Hi = SDOperand();
738 // See if the target wants to custom expand this node.
739 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(0)) ==
740 TargetLowering::Custom) {
741 // If the target wants to, allow it to lower this itself.
742 if (SDNode *P = TLI.ExpandOperationResult(N, DAG)) {
743 // Everything that once used N now uses P. We are guaranteed that the
744 // result value types of N and the result value types of P match.
745 ReplaceNodeWith(N, P);
750 switch (N->getOpcode()) {
753 cerr << "ExpandIntegerResult #" << ResNo << ": ";
754 N->dump(&DAG); cerr << "\n";
756 assert(0 && "Do not know how to expand the result of this operator!");
759 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
760 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
761 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
762 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
764 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
765 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
766 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
767 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
769 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
770 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
771 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
772 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
773 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
774 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
775 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
776 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
777 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
778 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
782 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
783 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
785 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
787 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
789 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
790 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
791 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
792 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
793 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
794 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
797 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
799 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
800 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
801 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
804 // If Lo/Hi is null, the sub-method took care of registering results etc.
806 SetExpandedInteger(SDOperand(N, ResNo), Lo, Hi);
809 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
810 SDOperand &Lo, SDOperand &Hi) {
811 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
812 unsigned NBitWidth = NVT.getSizeInBits();
813 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
814 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
815 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
818 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
819 SDOperand &Lo, SDOperand &Hi) {
820 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
821 SDOperand Op = N->getOperand(0);
822 if (Op.getValueType().bitsLE(NVT)) {
823 // The low part is any extension of the input (which degenerates to a copy).
824 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
825 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined.
827 // For example, extension of an i48 to an i64. The operand type necessarily
828 // promotes to the result type, so will end up being expanded too.
829 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
830 "Only know how to promote this result!");
831 SDOperand Res = GetPromotedInteger(Op);
832 assert(Res.getValueType() == N->getValueType(0) &&
833 "Operand over promoted?");
834 // Split the promoted operand. This will simplify when it is expanded.
835 SplitInteger(Res, Lo, Hi);
839 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
840 SDOperand &Lo, SDOperand &Hi) {
841 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
842 SDOperand Op = N->getOperand(0);
843 if (Op.getValueType().bitsLE(NVT)) {
844 // The low part is zero extension of the input (which degenerates to a copy).
845 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
846 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
848 // For example, extension of an i48 to an i64. The operand type necessarily
849 // promotes to the result type, so will end up being expanded too.
850 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
851 "Only know how to promote this result!");
852 SDOperand Res = GetPromotedInteger(Op);
853 assert(Res.getValueType() == N->getValueType(0) &&
854 "Operand over promoted?");
855 // Split the promoted operand. This will simplify when it is expanded.
856 SplitInteger(Res, Lo, Hi);
857 unsigned ExcessBits =
858 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
859 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits));
863 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
864 SDOperand &Lo, SDOperand &Hi) {
865 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
866 SDOperand Op = N->getOperand(0);
867 if (Op.getValueType().bitsLE(NVT)) {
868 // The low part is sign extension of the input (which degenerates to a copy).
869 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
870 // The high part is obtained by SRA'ing all but one of the bits of low part.
871 unsigned LoSize = NVT.getSizeInBits();
872 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
873 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
875 // For example, extension of an i48 to an i64. The operand type necessarily
876 // promotes to the result type, so will end up being expanded too.
877 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
878 "Only know how to promote this result!");
879 SDOperand Res = GetPromotedInteger(Op);
880 assert(Res.getValueType() == N->getValueType(0) &&
881 "Operand over promoted?");
882 // Split the promoted operand. This will simplify when it is expanded.
883 SplitInteger(Res, Lo, Hi);
884 unsigned ExcessBits =
885 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
886 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
887 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
891 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
892 SDOperand &Lo, SDOperand &Hi) {
893 GetExpandedInteger(N->getOperand(0), Lo, Hi);
894 MVT NVT = Lo.getValueType();
895 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
896 unsigned NVTBits = NVT.getSizeInBits();
897 unsigned EVTBits = EVT.getSizeInBits();
899 if (NVTBits < EVTBits) {
900 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi,
901 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
903 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT));
904 // The high part must be zero, make it explicit.
905 Hi = DAG.getConstant(0, NVT);
909 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
910 SDOperand &Lo, SDOperand &Hi) {
911 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
912 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0));
913 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0),
914 DAG.getConstant(NVT.getSizeInBits(),
915 TLI.getShiftAmountTy()));
916 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi);
919 void DAGTypeLegalizer::
920 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
921 GetExpandedInteger(N->getOperand(0), Lo, Hi);
922 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
924 if (EVT.bitsLE(Lo.getValueType())) {
925 // sext_inreg the low part if needed.
926 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
929 // The high part gets the sign extension from the lo-part. This handles
930 // things like sextinreg V:i64 from i8.
931 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
932 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
933 TLI.getShiftAmountTy()));
935 // For example, extension of an i48 to an i64. Leave the low part alone,
936 // sext_inreg the high part.
937 unsigned ExcessBits =
938 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
939 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
940 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
944 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDOperand &Lo,
946 MVT VT = N->getValueType(0);
947 SDOperand Op = N->getOperand(0);
948 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
949 if (VT == MVT::i64) {
950 if (Op.getValueType() == MVT::f32)
951 LC = RTLIB::FPTOSINT_F32_I64;
952 else if (Op.getValueType() == MVT::f64)
953 LC = RTLIB::FPTOSINT_F64_I64;
954 else if (Op.getValueType() == MVT::f80)
955 LC = RTLIB::FPTOSINT_F80_I64;
956 else if (Op.getValueType() == MVT::ppcf128)
957 LC = RTLIB::FPTOSINT_PPCF128_I64;
958 } else if (VT == MVT::i128) {
959 if (Op.getValueType() == MVT::f32)
960 LC = RTLIB::FPTOSINT_F32_I128;
961 else if (Op.getValueType() == MVT::f64)
962 LC = RTLIB::FPTOSINT_F64_I128;
963 else if (Op.getValueType() == MVT::f80)
964 LC = RTLIB::FPTOSINT_F80_I128;
965 else if (Op.getValueType() == MVT::ppcf128)
966 LC = RTLIB::FPTOSINT_PPCF128_I128;
968 assert(0 && "Unexpected fp-to-sint conversion!");
970 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi);
973 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDOperand &Lo,
975 MVT VT = N->getValueType(0);
976 SDOperand Op = N->getOperand(0);
977 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
978 if (VT == MVT::i64) {
979 if (Op.getValueType() == MVT::f32)
980 LC = RTLIB::FPTOUINT_F32_I64;
981 else if (Op.getValueType() == MVT::f64)
982 LC = RTLIB::FPTOUINT_F64_I64;
983 else if (Op.getValueType() == MVT::f80)
984 LC = RTLIB::FPTOUINT_F80_I64;
985 else if (Op.getValueType() == MVT::ppcf128)
986 LC = RTLIB::FPTOUINT_PPCF128_I64;
987 } else if (VT == MVT::i128) {
988 if (Op.getValueType() == MVT::f32)
989 LC = RTLIB::FPTOUINT_F32_I128;
990 else if (Op.getValueType() == MVT::f64)
991 LC = RTLIB::FPTOUINT_F64_I128;
992 else if (Op.getValueType() == MVT::f80)
993 LC = RTLIB::FPTOUINT_F80_I128;
994 else if (Op.getValueType() == MVT::ppcf128)
995 LC = RTLIB::FPTOUINT_PPCF128_I128;
997 assert(0 && "Unexpected fp-to-uint conversion!");
999 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi);
1002 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1003 SDOperand &Lo, SDOperand &Hi) {
1004 if (ISD::isNormalLoad(N)) {
1005 ExpandRes_NormalLoad(N, Lo, Hi);
1009 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1011 MVT VT = N->getValueType(0);
1012 MVT NVT = TLI.getTypeToTransformTo(VT);
1013 SDOperand Ch = N->getChain(); // Legalize the chain.
1014 SDOperand Ptr = N->getBasePtr(); // Legalize the pointer.
1015 ISD::LoadExtType ExtType = N->getExtensionType();
1016 int SVOffset = N->getSrcValueOffset();
1017 unsigned Alignment = N->getAlignment();
1018 bool isVolatile = N->isVolatile();
1020 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1022 if (N->getMemoryVT().bitsLE(NVT)) {
1023 MVT EVT = N->getMemoryVT();
1025 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
1026 isVolatile, Alignment);
1028 // Remember the chain.
1029 Ch = Lo.getValue(1);
1031 if (ExtType == ISD::SEXTLOAD) {
1032 // The high part is obtained by SRA'ing all but one of the bits of the
1034 unsigned LoSize = Lo.getValueType().getSizeInBits();
1035 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1036 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1037 } else if (ExtType == ISD::ZEXTLOAD) {
1038 // The high part is just a zero.
1039 Hi = DAG.getConstant(0, NVT);
1041 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1042 // The high part is undefined.
1043 Hi = DAG.getNode(ISD::UNDEF, NVT);
1045 } else if (TLI.isLittleEndian()) {
1046 // Little-endian - low bits are at low addresses.
1047 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1048 isVolatile, Alignment);
1050 unsigned ExcessBits =
1051 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1052 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1054 // Increment the pointer to the other half.
1055 unsigned IncrementSize = NVT.getSizeInBits()/8;
1056 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1057 DAG.getIntPtrConstant(IncrementSize));
1058 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
1059 SVOffset+IncrementSize, NEVT,
1060 isVolatile, MinAlign(Alignment, IncrementSize));
1062 // Build a factor node to remember that this load is independent of the
1064 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1067 // Big-endian - high bits are at low addresses. Favor aligned loads at
1068 // the cost of some bit-fiddling.
1069 MVT EVT = N->getMemoryVT();
1070 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1071 unsigned IncrementSize = NVT.getSizeInBits()/8;
1072 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1074 // Load both the high bits and maybe some of the low bits.
1075 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1076 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1077 isVolatile, Alignment);
1079 // Increment the pointer to the other half.
1080 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1081 DAG.getIntPtrConstant(IncrementSize));
1082 // Load the rest of the low bits.
1083 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
1084 SVOffset+IncrementSize,
1085 MVT::getIntegerVT(ExcessBits),
1086 isVolatile, MinAlign(Alignment, IncrementSize));
1088 // Build a factor node to remember that this load is independent of the
1090 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1093 if (ExcessBits < NVT.getSizeInBits()) {
1094 // Transfer low bits from the bottom of Hi to the top of Lo.
1095 Lo = DAG.getNode(ISD::OR, NVT, Lo,
1096 DAG.getNode(ISD::SHL, NVT, Hi,
1097 DAG.getConstant(ExcessBits,
1098 TLI.getShiftAmountTy())));
1099 // Move high bits to the right position in Hi.
1100 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi,
1101 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1102 TLI.getShiftAmountTy()));
1106 // Legalized the chain result - switch anything that used the old chain to
1108 ReplaceValueWith(SDOperand(N, 1), Ch);
1111 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1112 SDOperand &Lo, SDOperand &Hi) {
1113 SDOperand LL, LH, RL, RH;
1114 GetExpandedInteger(N->getOperand(0), LL, LH);
1115 GetExpandedInteger(N->getOperand(1), RL, RH);
1116 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL);
1117 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH);
1120 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1121 SDOperand &Lo, SDOperand &Hi) {
1122 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1123 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo);
1124 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi);
1127 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1128 SDOperand &Lo, SDOperand &Hi) {
1129 // Expand the subcomponents.
1130 SDOperand LHSL, LHSH, RHSL, RHSH;
1131 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1132 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1133 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1134 SDOperand LoOps[2] = { LHSL, RHSL };
1135 SDOperand HiOps[3] = { LHSH, RHSH };
1137 if (N->getOpcode() == ISD::ADD) {
1138 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1139 HiOps[2] = Lo.getValue(1);
1140 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1142 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1143 HiOps[2] = Lo.getValue(1);
1144 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1148 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1149 SDOperand &Lo, SDOperand &Hi) {
1150 // Expand the subcomponents.
1151 SDOperand LHSL, LHSH, RHSL, RHSH;
1152 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1153 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1154 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1155 SDOperand LoOps[2] = { LHSL, RHSL };
1156 SDOperand HiOps[3] = { LHSH, RHSH };
1158 if (N->getOpcode() == ISD::ADDC) {
1159 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1160 HiOps[2] = Lo.getValue(1);
1161 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1163 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1164 HiOps[2] = Lo.getValue(1);
1165 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1168 // Legalized the flag result - switch anything that used the old flag to
1170 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1));
1173 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1174 SDOperand &Lo, SDOperand &Hi) {
1175 // Expand the subcomponents.
1176 SDOperand LHSL, LHSH, RHSL, RHSH;
1177 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1178 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1179 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1180 SDOperand LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1181 SDOperand HiOps[3] = { LHSH, RHSH };
1183 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3);
1184 HiOps[2] = Lo.getValue(1);
1185 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3);
1187 // Legalized the flag result - switch anything that used the old flag to
1189 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1));
1192 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1193 SDOperand &Lo, SDOperand &Hi) {
1194 MVT VT = N->getValueType(0);
1195 MVT NVT = TLI.getTypeToTransformTo(VT);
1197 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
1198 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
1199 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
1200 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
1201 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1202 SDOperand LL, LH, RL, RH;
1203 GetExpandedInteger(N->getOperand(0), LL, LH);
1204 GetExpandedInteger(N->getOperand(1), RL, RH);
1205 unsigned OuterBitSize = VT.getSizeInBits();
1206 unsigned BitSize = NVT.getSizeInBits();
1207 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1208 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1210 if (DAG.MaskedValueIsZero(N->getOperand(0),
1211 APInt::getHighBitsSet(OuterBitSize, LHSSB)) &&
1212 DAG.MaskedValueIsZero(N->getOperand(1),
1213 APInt::getHighBitsSet(OuterBitSize, RHSSB))) {
1214 // The inputs are both zero-extended.
1216 // We can emit a umul_lohi.
1217 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1218 Hi = SDOperand(Lo.Val, 1);
1222 // We can emit a mulhu+mul.
1223 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1224 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1228 if (LHSSB > BitSize && RHSSB > BitSize) {
1229 // The input values are both sign-extended.
1231 // We can emit a smul_lohi.
1232 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1233 Hi = SDOperand(Lo.Val, 1);
1237 // We can emit a mulhs+mul.
1238 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1239 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
1244 // Lo,Hi = umul LHS, RHS.
1245 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
1246 DAG.getVTList(NVT, NVT), LL, RL);
1248 Hi = UMulLOHI.getValue(1);
1249 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1250 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1251 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1252 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1257 // If nothing else, we can make a libcall.
1258 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1259 SplitInteger(MakeLibCall(RTLIB::MUL_I64, VT, Ops, 2, true/*sign irrelevant*/),
1263 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1264 SDOperand &Lo, SDOperand &Hi) {
1265 assert(N->getValueType(0) == MVT::i64 && "Unsupported sdiv!");
1266 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1267 SplitInteger(MakeLibCall(RTLIB::SDIV_I64, N->getValueType(0), Ops, 2, true),
1271 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1272 SDOperand &Lo, SDOperand &Hi) {
1273 assert(N->getValueType(0) == MVT::i64 && "Unsupported srem!");
1274 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1275 SplitInteger(MakeLibCall(RTLIB::SREM_I64, N->getValueType(0), Ops, 2, true),
1279 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1280 SDOperand &Lo, SDOperand &Hi) {
1281 assert(N->getValueType(0) == MVT::i64 && "Unsupported udiv!");
1282 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1283 SplitInteger(MakeLibCall(RTLIB::UDIV_I64, N->getValueType(0), Ops, 2, false),
1287 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1288 SDOperand &Lo, SDOperand &Hi) {
1289 assert(N->getValueType(0) == MVT::i64 && "Unsupported urem!");
1290 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1291 SplitInteger(MakeLibCall(RTLIB::UREM_I64, N->getValueType(0), Ops, 2, false),
1295 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1296 SDOperand &Lo, SDOperand &Hi) {
1297 MVT VT = N->getValueType(0);
1299 // If we can emit an efficient shift operation, do so now. Check to see if
1300 // the RHS is a constant.
1301 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1302 return ExpandShiftByConstant(N, CN->getValue(), Lo, Hi);
1304 // If we can determine that the high bit of the shift is zero or one, even if
1305 // the low bits are variable, emit this shift in an optimized form.
1306 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1309 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1311 if (N->getOpcode() == ISD::SHL) {
1312 PartsOpc = ISD::SHL_PARTS;
1313 } else if (N->getOpcode() == ISD::SRL) {
1314 PartsOpc = ISD::SRL_PARTS;
1316 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1317 PartsOpc = ISD::SRA_PARTS;
1320 // Next check to see if the target supports this SHL_PARTS operation or if it
1321 // will custom expand it.
1322 MVT NVT = TLI.getTypeToTransformTo(VT);
1323 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1324 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1325 Action == TargetLowering::Custom) {
1326 // Expand the subcomponents.
1327 SDOperand LHSL, LHSH;
1328 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1330 SDOperand Ops[] = { LHSL, LHSH, N->getOperand(1) };
1331 MVT VT = LHSL.getValueType();
1332 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
1333 Hi = Lo.getValue(1);
1337 // Otherwise, emit a libcall.
1338 assert(VT == MVT::i64 && "Unsupported shift!");
1342 if (N->getOpcode() == ISD::SHL) {
1343 LC = RTLIB::SHL_I64;
1344 isSigned = false; /*sign irrelevant*/
1345 } else if (N->getOpcode() == ISD::SRL) {
1346 LC = RTLIB::SRL_I64;
1349 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1350 LC = RTLIB::SRA_I64;
1354 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1355 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi);
1358 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1359 SDOperand &Lo, SDOperand &Hi) {
1360 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1361 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1362 MVT NVT = Lo.getValueType();
1364 SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
1365 DAG.getConstant(0, NVT), ISD::SETNE);
1367 SDOperand LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
1368 SDOperand HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
1370 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ,
1371 DAG.getNode(ISD::ADD, NVT, LoLZ,
1372 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1373 Hi = DAG.getConstant(0, NVT);
1376 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1377 SDOperand &Lo, SDOperand &Hi) {
1378 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1379 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1380 MVT NVT = Lo.getValueType();
1381 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
1382 DAG.getNode(ISD::CTPOP, NVT, Hi));
1383 Hi = DAG.getConstant(0, NVT);
1386 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1387 SDOperand &Lo, SDOperand &Hi) {
1388 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1389 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1390 MVT NVT = Lo.getValueType();
1392 SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
1393 DAG.getConstant(0, NVT), ISD::SETNE);
1395 SDOperand LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
1396 SDOperand HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi);
1398 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ,
1399 DAG.getNode(ISD::ADD, NVT, HiLZ,
1400 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1401 Hi = DAG.getConstant(0, NVT);
1404 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1405 /// and the shift amount is a constant 'Amt'. Expand the operation.
1406 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1407 SDOperand &Lo, SDOperand &Hi) {
1408 // Expand the incoming operand to be shifted, so that we have its parts
1410 GetExpandedInteger(N->getOperand(0), InL, InH);
1412 MVT NVT = InL.getValueType();
1413 unsigned VTBits = N->getValueType(0).getSizeInBits();
1414 unsigned NVTBits = NVT.getSizeInBits();
1415 MVT ShTy = N->getOperand(1).getValueType();
1417 if (N->getOpcode() == ISD::SHL) {
1419 Lo = Hi = DAG.getConstant(0, NVT);
1420 } else if (Amt > NVTBits) {
1421 Lo = DAG.getConstant(0, NVT);
1422 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1423 } else if (Amt == NVTBits) {
1424 Lo = DAG.getConstant(0, NVT);
1427 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
1428 Hi = DAG.getNode(ISD::OR, NVT,
1429 DAG.getNode(ISD::SHL, NVT, InH,
1430 DAG.getConstant(Amt, ShTy)),
1431 DAG.getNode(ISD::SRL, NVT, InL,
1432 DAG.getConstant(NVTBits-Amt, ShTy)));
1437 if (N->getOpcode() == ISD::SRL) {
1439 Lo = DAG.getConstant(0, NVT);
1440 Hi = DAG.getConstant(0, NVT);
1441 } else if (Amt > NVTBits) {
1442 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1443 Hi = DAG.getConstant(0, NVT);
1444 } else if (Amt == NVTBits) {
1446 Hi = DAG.getConstant(0, NVT);
1448 Lo = DAG.getNode(ISD::OR, NVT,
1449 DAG.getNode(ISD::SRL, NVT, InL,
1450 DAG.getConstant(Amt, ShTy)),
1451 DAG.getNode(ISD::SHL, NVT, InH,
1452 DAG.getConstant(NVTBits-Amt, ShTy)));
1453 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy));
1458 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1460 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
1461 DAG.getConstant(NVTBits-1, ShTy));
1462 } else if (Amt > NVTBits) {
1463 Lo = DAG.getNode(ISD::SRA, NVT, InH,
1464 DAG.getConstant(Amt-NVTBits, ShTy));
1465 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1466 DAG.getConstant(NVTBits-1, ShTy));
1467 } else if (Amt == NVTBits) {
1469 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1470 DAG.getConstant(NVTBits-1, ShTy));
1472 Lo = DAG.getNode(ISD::OR, NVT,
1473 DAG.getNode(ISD::SRL, NVT, InL,
1474 DAG.getConstant(Amt, ShTy)),
1475 DAG.getNode(ISD::SHL, NVT, InH,
1476 DAG.getConstant(NVTBits-Amt, ShTy)));
1477 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy));
1481 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1482 /// this shift based on knowledge of the high bit of the shift amount. If we
1483 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1485 bool DAGTypeLegalizer::
1486 ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
1487 SDOperand Amt = N->getOperand(1);
1488 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1489 MVT ShTy = Amt.getValueType();
1490 unsigned ShBits = ShTy.getSizeInBits();
1491 unsigned NVTBits = NVT.getSizeInBits();
1492 assert(isPowerOf2_32(NVTBits) &&
1493 "Expanded integer type size not a power of two!");
1495 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1496 APInt KnownZero, KnownOne;
1497 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1499 // If we don't know anything about the high bits, exit.
1500 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1503 // Get the incoming operand to be shifted.
1505 GetExpandedInteger(N->getOperand(0), InL, InH);
1507 // If we know that any of the high bits of the shift amount are one, then we
1508 // can do this as a couple of simple shifts.
1509 if (KnownOne.intersects(HighBitMask)) {
1510 // Mask out the high bit, which we know is set.
1511 Amt = DAG.getNode(ISD::AND, ShTy, Amt,
1512 DAG.getConstant(~HighBitMask, ShTy));
1514 switch (N->getOpcode()) {
1515 default: assert(0 && "Unknown shift");
1517 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1518 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
1521 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1522 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
1525 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
1526 DAG.getConstant(NVTBits-1, ShTy));
1527 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
1532 // If we know that all of the high bits of the shift amount are zero, then we
1533 // can do this as a couple of simple shifts.
1534 if ((KnownZero & HighBitMask) == HighBitMask) {
1536 SDOperand Amt2 = DAG.getNode(ISD::SUB, ShTy,
1537 DAG.getConstant(NVTBits, ShTy),
1540 switch (N->getOpcode()) {
1541 default: assert(0 && "Unknown shift");
1542 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1544 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1547 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1548 Hi = DAG.getNode(ISD::OR, NVT,
1549 DAG.getNode(Op1, NVT, InH, Amt),
1550 DAG.getNode(Op2, NVT, InL, Amt2));
1558 //===----------------------------------------------------------------------===//
1559 // Integer Operand Expansion
1560 //===----------------------------------------------------------------------===//
1562 /// ExpandIntegerOperand - This method is called when the specified operand of
1563 /// the specified node is found to need expansion. At this point, all of the
1564 /// result types of the node are known to be legal, but other operands of the
1565 /// node may need promotion or expansion as well as the specified one.
1566 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1567 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
1568 SDOperand Res(0, 0);
1570 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
1571 == TargetLowering::Custom)
1572 Res = TLI.LowerOperation(SDOperand(N, 0), DAG);
1575 switch (N->getOpcode()) {
1578 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
1579 N->dump(&DAG); cerr << "\n";
1581 assert(0 && "Do not know how to expand this operator's operand!");
1584 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1585 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1586 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1588 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1590 case ISD::SINT_TO_FP:
1591 Res = ExpandIntOp_SINT_TO_FP(N->getOperand(0), N->getValueType(0));
1593 case ISD::UINT_TO_FP:
1594 Res = ExpandIntOp_UINT_TO_FP(N->getOperand(0), N->getValueType(0));
1597 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1598 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1601 Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo);
1606 // If the result is null, the sub-method took care of registering results etc.
1607 if (!Res.Val) return false;
1608 // If the result is N, the sub-method updated N in place. Check to see if any
1609 // operands are new, and if so, mark them.
1611 // Mark N as new and remark N and its operands. This allows us to correctly
1612 // revisit N if it needs another step of expansion and allows us to visit
1613 // any new operands to N.
1618 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1619 "Invalid operand expansion");
1621 ReplaceValueWith(SDOperand(N, 0), Res);
1625 SDOperand DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
1627 GetExpandedInteger(N->getOperand(0), InL, InH);
1628 // Just truncate the low part of the source.
1629 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
1632 SDOperand DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDOperand Source,
1634 // We know the destination is legal, but that the input needs to be expanded.
1635 MVT SourceVT = Source.getValueType();
1637 // Check to see if the target has a custom way to lower this. If so, use it.
1638 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
1639 default: assert(0 && "This action not implemented for this operation!");
1640 case TargetLowering::Legal:
1641 case TargetLowering::Expand:
1642 break; // This case is handled below.
1643 case TargetLowering::Custom:
1644 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
1646 if (NV.Val) return NV;
1647 break; // The target lowered this.
1650 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1651 if (SourceVT == MVT::i64) {
1652 if (DestTy == MVT::f32)
1653 LC = RTLIB::SINTTOFP_I64_F32;
1655 assert(DestTy == MVT::f64 && "Unknown fp value type!");
1656 LC = RTLIB::SINTTOFP_I64_F64;
1658 } else if (SourceVT == MVT::i128) {
1659 if (DestTy == MVT::f32)
1660 LC = RTLIB::SINTTOFP_I128_F32;
1661 else if (DestTy == MVT::f64)
1662 LC = RTLIB::SINTTOFP_I128_F64;
1663 else if (DestTy == MVT::f80)
1664 LC = RTLIB::SINTTOFP_I128_F80;
1666 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
1667 LC = RTLIB::SINTTOFP_I128_PPCF128;
1670 assert(0 && "Unknown int value type!");
1673 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
1674 "Don't know how to expand this SINT_TO_FP!");
1675 return MakeLibCall(LC, DestTy, &Source, 1, true);
1678 SDOperand DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDOperand Source,
1680 // We know the destination is legal, but that the input needs to be expanded.
1681 assert(getTypeAction(Source.getValueType()) == ExpandInteger &&
1682 "This is not an expansion!");
1684 // If this is unsigned, and not supported, first perform the conversion to
1685 // signed, then adjust the result if the sign bit is set.
1686 SDOperand SignedConv = ExpandIntOp_SINT_TO_FP(Source, DestTy);
1688 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
1689 // incoming integer is set. To handle this, we dynamically test to see if
1690 // it is set, and, if so, add a fudge factor.
1692 GetExpandedInteger(Source, Lo, Hi);
1694 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
1695 DAG.getConstant(0, Hi.getValueType()),
1697 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
1698 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
1699 SignSet, Four, Zero);
1700 uint64_t FF = 0x5f800000ULL;
1701 if (TLI.isLittleEndian()) FF <<= 32;
1702 Constant *FudgeFactor = ConstantInt::get((Type*)Type::Int64Ty, FF);
1704 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
1705 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
1706 SDOperand FudgeInReg;
1707 if (DestTy == MVT::f32)
1708 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
1709 else if (DestTy.bitsGT(MVT::f32))
1710 // FIXME: Avoid the extend by construction the right constantpool?
1711 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
1712 CPIdx, NULL, 0, MVT::f32);
1714 assert(0 && "Unexpected conversion");
1716 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
1719 SDOperand DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
1720 SDOperand NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
1721 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
1722 ExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1724 // If ExpandSetCCOperands returned a scalar, we need to compare the result
1725 // against zero to select between true and false values.
1726 if (NewRHS.Val == 0) {
1727 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1728 CCCode = ISD::SETNE;
1731 // Update N to have the operands specified.
1732 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
1733 DAG.getCondCode(CCCode), NewLHS, NewRHS,
1737 SDOperand DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
1738 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1739 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
1740 ExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1742 // If ExpandSetCCOperands returned a scalar, use it.
1743 if (NewRHS.Val == 0) return NewLHS;
1745 // Otherwise, update N to have the operands specified.
1746 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
1747 DAG.getCondCode(CCCode));
1750 /// ExpandSetCCOperands - Expand the operands of a comparison. This code is
1751 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
1752 void DAGTypeLegalizer::ExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
1753 ISD::CondCode &CCCode) {
1754 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
1755 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
1756 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
1758 MVT VT = NewLHS.getValueType();
1759 if (VT == MVT::ppcf128) {
1760 // FIXME: This generated code sucks. We want to generate
1761 // FCMP crN, hi1, hi2
1763 // FCMP crN, lo1, lo2
1764 // The following can be improved, but not that much.
1765 SDOperand Tmp1, Tmp2, Tmp3;
1766 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
1767 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
1768 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
1769 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE);
1770 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
1771 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
1772 NewLHS = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
1773 NewRHS = SDOperand(); // LHS is the result, not a compare.
1777 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
1779 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
1780 if (RHSCST->isAllOnesValue()) {
1781 // Equality comparison to -1.
1782 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1787 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1788 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1789 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS);
1790 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1794 // If this is a comparison of the sign bit, just look at the top part.
1796 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
1797 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
1798 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
1804 // FIXME: This generated code sucks.
1805 ISD::CondCode LowCC;
1807 default: assert(0 && "Unknown integer setcc!");
1809 case ISD::SETULT: LowCC = ISD::SETULT; break;
1811 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1813 case ISD::SETULE: LowCC = ISD::SETULE; break;
1815 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1818 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1819 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1820 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1822 // NOTE: on targets without efficient SELECT of bools, we can always use
1823 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1824 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
1825 SDOperand Tmp1, Tmp2;
1826 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
1827 false, DagCombineInfo);
1829 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
1830 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1831 CCCode, false, DagCombineInfo);
1833 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1834 DAG.getCondCode(CCCode));
1836 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
1837 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
1838 if ((Tmp1C && Tmp1C->isNullValue()) ||
1839 (Tmp2C && Tmp2C->isNullValue() &&
1840 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
1841 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
1842 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
1843 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
1844 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
1845 // low part is known false, returns high part.
1846 // For LE / GE, if high part is known false, ignore the low part.
1847 // For LT / GT, if high part is known true, ignore the low part.
1849 NewRHS = SDOperand();
1853 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1854 ISD::SETEQ, false, DagCombineInfo);
1856 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1858 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1859 NewLHS, Tmp1, Tmp2);
1860 NewRHS = SDOperand();
1863 SDOperand DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
1864 if (ISD::isNormalStore(N))
1865 return ExpandOp_NormalStore(N, OpNo);
1867 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1868 assert(OpNo == 1 && "Can only expand the stored value so far");
1870 MVT VT = N->getOperand(1).getValueType();
1871 MVT NVT = TLI.getTypeToTransformTo(VT);
1872 SDOperand Ch = N->getChain();
1873 SDOperand Ptr = N->getBasePtr();
1874 int SVOffset = N->getSrcValueOffset();
1875 unsigned Alignment = N->getAlignment();
1876 bool isVolatile = N->isVolatile();
1879 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1881 if (N->getMemoryVT().bitsLE(NVT)) {
1882 GetExpandedInteger(N->getValue(), Lo, Hi);
1883 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
1884 N->getMemoryVT(), isVolatile, Alignment);
1885 } else if (TLI.isLittleEndian()) {
1886 // Little-endian - low bits are at low addresses.
1887 GetExpandedInteger(N->getValue(), Lo, Hi);
1889 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
1890 isVolatile, Alignment);
1892 unsigned ExcessBits =
1893 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1894 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1896 // Increment the pointer to the other half.
1897 unsigned IncrementSize = NVT.getSizeInBits()/8;
1898 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1899 DAG.getIntPtrConstant(IncrementSize));
1900 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
1901 SVOffset+IncrementSize, NEVT,
1902 isVolatile, MinAlign(Alignment, IncrementSize));
1903 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1905 // Big-endian - high bits are at low addresses. Favor aligned stores at
1906 // the cost of some bit-fiddling.
1907 GetExpandedInteger(N->getValue(), Lo, Hi);
1909 MVT EVT = N->getMemoryVT();
1910 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1911 unsigned IncrementSize = NVT.getSizeInBits()/8;
1912 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1913 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
1915 if (ExcessBits < NVT.getSizeInBits()) {
1916 // Transfer high bits from the top of Lo to the bottom of Hi.
1917 Hi = DAG.getNode(ISD::SHL, NVT, Hi,
1918 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1919 TLI.getShiftAmountTy()));
1920 Hi = DAG.getNode(ISD::OR, NVT, Hi,
1921 DAG.getNode(ISD::SRL, NVT, Lo,
1922 DAG.getConstant(ExcessBits,
1923 TLI.getShiftAmountTy())));
1926 // Store both the high bits and maybe some of the low bits.
1927 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
1928 SVOffset, HiVT, isVolatile, Alignment);
1930 // Increment the pointer to the other half.
1931 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1932 DAG.getIntPtrConstant(IncrementSize));
1933 // Store the lowest ExcessBits bits in the second half.
1934 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
1935 SVOffset+IncrementSize,
1936 MVT::getIntegerVT(ExcessBits),
1937 isVolatile, MinAlign(Alignment, IncrementSize));
1938 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);